#

# This file addds inline T4 instruction support to OpenSSL upstream code.

#

Index: Configure

===================================================================

diff -ru openssl-1.0.1e/Configure openssl-1.0.1e/Configure

--- openssl-1.0.1e/Configure 2011-05-24 17:02:24.000000000 -0700

+++ openssl-1.0.1e/Configure 2011-07-27 10:48:17.817470000 -0700

@@ -135,7 +135,7 @@

 my $x86_64_asm="x86_64cpuid.o:x86_64-gcc.o x86_64-mont.o x86_64-mont5.o x86_64-gf2m.o modexp512-x86_64.o::aes-x86_64.o vpaes-x86_64.o bsaes-x86_64.o aesni-x86_64.o aesni-sha1-x86_64.o::md5-x86_64.o:sha1-x86_64.o sha256-x86_64.o sha512-x86_64.o::rc4-x86_64.o rc4-md5-x86_64.o:::wp-x86_64.o:cmll-x86_64.o cmll_misc.o:ghash-x86_64.o:";

 my $ia64_asm="ia64cpuid.o:bn-ia64.o ia64-mont.o::aes_core.o aes_cbc.o aes-ia64.o::md5-ia64.o:sha1-ia64.o sha256-ia64.o sha512-ia64.o::rc4-ia64.o rc4_skey.o:::::ghash-ia64.o::void";

-my $sparcv9_asm="sparcv9cap.o sparccpuid.o:bn-sparcv9.o sparcv9-mont.o sparcv9a-mont.o:des_enc-sparc.o fcrypt_b.o:aes_core.o aes_cbc.o aes-sparcv9.o:::sha1-sparcv9.o sha256-sparcv9.o sha512-sparcv9.o:::::::ghash-sparcv9.o::void";

+my $sparcv9_asm="sparcv9cap.o sparccpuid.o:bn-sparcv9.o sparcv9-mont.o sparcv9a-mont.o:des_enc-sparc.o fcrypt_b.o:aes_core.o aes_cbc.o aes-sparcv9.o::md5-sparcv9.o:sha1-sparcv9.o sha256-sparcv9.o sha512-sparcv9.o:::::::ghash-sparcv9.o::void";

 my $sparcv8_asm=":sparcv8.o:des_enc-sparc.o fcrypt_b.o:::::::::::::void";

 my $alpha_asm="alphacpuid.o:bn_asm.o alpha-mont.o:::::sha1-alpha.o:::::::ghash-alpha.o::void";

 my $mips32_asm=":bn-mips.o::aes_cbc.o aes-mips.o:::sha1-mips.o sha256-mips.o::::::::";

Index: crypto/sparccpuid.S

===================================================================

diff -ru openssl-1.0.1e/crypto/sparccpuid.S openssl-1.0.1e/crypto/sparccpuid.S

--- openssl-1.0.1e/crypto/sparccpuid.S 2011-05-24 17:02:24.000000000 -0700

+++ openssl-1.0.1e/crypto/sparccpuid.S 2011-07-27 10:48:17.817470000 -0700

@@ -251,6 +251,11 @@

 !	UltraSPARC IIe		7

 !	UltraSPARC III		7

 !	UltraSPARC T1		24

+!	SPARC T4		65(*)

+!

+! (*)	result has lesser to do with VIS instruction latencies, rdtick

+!	appears that slow, but it does the trick in sense that FP and

+!	VIS code paths are still slower than integer-only ones.

 !

 ! Numbers for T2 and SPARC64 V-VII are more than welcomed.

 !

@@ -260,6 +265,8 @@

 .global	_sparcv9_vis1_instrument

 .align	8

 _sparcv9_vis1_instrument:

+	.word	0x81b00d80	!fxor	%f0,%f0,%f0

+	.word	0x85b08d82	!fxor	%f2,%f2,%f2

 	.word	0x91410000	!rd	%tick,%o0

 	.word	0x81b00d80	!fxor	%f0,%f0,%f0

 	.word	0x85b08d82	!fxor	%f2,%f2,%f2

@@ -314,6 +321,30 @@

 .type	_sparcv9_fmadd_probe,#function

 .size	_sparcv9_fmadd_probe,.-_sparcv9_fmadd_probe

+.global	_sparcv9_rdcfr

+.align	8

+_sparcv9_rdcfr:

+	retl

+	.word	0x91468000	!rd	%asr26,%o0

+.type	_sparcv9_rdcfr,#function

+.size	_sparcv9_rdcfr,.-_sparcv9_rdcfr

+

+.global	_sparcv9_vis3_probe

+.align	8

+_sparcv9_vis3_probe:

+	retl

+	.word	0x81b022a0	!xmulx	%g0,%g0,%g0

+.type	_sparcv9_vis3_probe,#function

+.size	_sparcv9_vis3_probe,.-_sparcv9_vis3_probe

+

+.global	_sparcv9_random

+.align	8

+_sparcv9_random:

+	retl

+	.word	0x91b002a0	!random	%o0

+.type	_sparcv9_random,#function

+.size	_sparcv9_random,.-_sparcv9_vis3_probe

+

 .global	OPENSSL_cleanse

 .align	32

 OPENSSL_cleanse:

Index: crypto/sparcv9cap.c

===================================================================

diff -ru openssl-1.0.1e/crypto/sparcv9cap.c openssl-1.0.1e/crypto/sparcv9cap.c

--- openssl-1.0.1e/crypto/sparcv9cap.c 2011-05-24 17:02:24.000000000 -0700

+++ openssl-1.0.1e/crypto/sparcv9cap.c 2011-07-27 10:48:17.817470000 -0700

@@ -6,16 +6,15 @@

 #include <sys/time.h>

 #include <openssl/bn.h>

-#define SPARCV9_TICK_PRIVILEGED	(1<<0)

-#define SPARCV9_PREFER_FPU	(1<<1)

-#define SPARCV9_VIS1		(1<<2)

-#define SPARCV9_VIS2		(1<<3)	/* reserved */

-#define SPARCV9_FMADD		(1<<4)	/* reserved for SPARC64 V */

+#include "sparc_arch.h"

+#if defined(__GNUC__) && defined(__linux)

+__attribute__((visibility("hidden")))

+#endif

 #ifndef	_BOOT

-static int OPENSSL_sparcv9cap_P=SPARCV9_TICK_PRIVILEGED;

+unsigned int OPENSSL_sparcv9cap_P[2]={SPARCV9_TICK_PRIVILEGED,0};

 #else

-static int OPENSSL_sparcv9cap_P = SPARCV9_VIS1;

+unsigned int OPENSSL_sparcv9cap_P[2]={SPARCV9_VIS1,0};

 #endif

 int bn_mul_mont(BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp, const BN_ULONG *np,const BN_ULONG *n0, int num)

@@ -24,7 +23,7 @@

 	int bn_mul_mont_int(BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp, const BN_ULONG *np,const BN_ULONG *n0, int num);

 	if (num>=8 && !(num&1) &&

-	    (OPENSSL_sparcv9cap_P&(SPARCV9_PREFER_FPU|SPARCV9_VIS1)) ==

+	    (OPENSSL_sparcv9cap_P[0]&(SPARCV9_PREFER_FPU|SPARCV9_VIS1)) ==

 		(SPARCV9_PREFER_FPU|SPARCV9_VIS1))

 		return bn_mul_mont_fpu(rp,ap,bp,np,n0,num);

 	else

@@ -36,11 +35,16 @@

 unsigned long	_sparcv9_vis1_instrument(void);

 void		_sparcv9_vis2_probe(void);

 void		_sparcv9_fmadd_probe(void);

+unsigned long	_sparcv9_rdcfr(void);

+void		_sparcv9_vis3_probe(void);

+unsigned long	_sparcv9_random(void);

+size_t 		_sparcv9_vis1_instrument_bus(unsigned int *,size_t);

+size_t		_sparcv9_vis1_instrument_bus2(unsigned int *,size_t,size_t);

 #ifndef _BOOT

 unsigned long OPENSSL_rdtsc(void)

 	{

-	if (OPENSSL_sparcv9cap_P&SPARCV9_TICK_PRIVILEGED)

+	if (OPENSSL_sparcv9cap_P[0]&SPARCV9_TICK_PRIVILEGED)

 #if defined(__sun) && defined(__SVR4)

 		return gethrtime();

 #else

@@ -51,6 +55,25 @@

 	}

 #endif

+size_t OPENSSL_instrument_bus(unsigned int *out,size_t cnt)

+	{

+	if (OPENSSL_sparcv9cap_P[0]&(SPARCV9_TICK_PRIVILEGED|SPARCV9_BLK) ==

+			SPARCV9_BLK)

+		return _sparcv9_vis1_instrument_bus(out,cnt);

+	else

+		return 0;

+	}

+

+size_t OPENSSL_instrument_bus2(unsigned int *out,size_t cnt,size_t max)

+	{

+	if (OPENSSL_sparcv9cap_P[0]&(SPARCV9_TICK_PRIVILEGED|SPARCV9_BLK) ==

+			SPARCV9_BLK)

+		return _sparcv9_vis1_instrument_bus2(out,cnt,max);

+	else

+		return 0;

+	}

+

+

 #if defined(_BOOT)

 /*

  * Hardcoding sparc capabilities for wanboot.

@@ -58,7 +81,7 @@

  */

 void OPENSSL_cpuid_setup(void)

 	{

-	OPENSSL_sparcv9cap_P = SPARCV9_VIS1;

+	OPENSSL_sparcv9cap_P[0] = SPARCV9_VIS1;

 	}

 #elif 0 && defined(__sun) && defined(__SVR4)

@@ -85,11 +108,11 @@

 	if (!strcmp (name,"SUNW,UltraSPARC") ||

 	    !strncmp(name,"SUNW,UltraSPARC-I",17))  /* covers II,III,IV */

 		{

-		OPENSSL_sparcv9cap_P |= SPARCV9_PREFER_FPU|SPARCV9_VIS1;

+		OPENSSL_sparcv9cap_P[0] |= SPARCV9_PREFER_FPU|SPARCV9_VIS1;

 		/* %tick is privileged only on UltraSPARC-I/II, but not IIe */

 		if (name[14]!='\0' && name[17]!='\0' && name[18]!='\0')

-			OPENSSL_sparcv9cap_P &= ~SPARCV9_TICK_PRIVILEGED;

+			OPENSSL_sparcv9cap_P[0] &= ~SPARCV9_TICK_PRIVILEGED;

 		return DI_WALK_TERMINATE;

 		}

@@ -96,7 +119,7 @@

 	/* This is expected to catch remaining UltraSPARCs, such as T1 */

 	else if (!strncmp(name,"SUNW,UltraSPARC",15))

 		{

-		OPENSSL_sparcv9cap_P &= ~SPARCV9_TICK_PRIVILEGED;

+		OPENSSL_sparcv9cap_P[0] &= ~SPARCV9_TICK_PRIVILEGED;

 		return DI_WALK_TERMINATE;

 		}

@@ -115,7 +138,7 @@

 	if ((e=getenv("OPENSSL_sparcv9cap")))

 		{

-		OPENSSL_sparcv9cap_P=strtoul(e,NULL,0);

+		OPENSSL_sparcv9cap_P[0]=strtoul(e,NULL,0);

 		return;

 		}

@@ -123,17 +146,17 @@

 		{

 		if (strcmp(si,"sun4v"))

 			/* FPU is preferred for all CPUs, but US-T1/2 */

-			OPENSSL_sparcv9cap_P |= SPARCV9_PREFER_FPU;

+			OPENSSL_sparcv9cap_P[0] |= SPARCV9_PREFER_FPU;

 		}

 	if (sysinfo(SI_ISALIST,si,sizeof(si))>0)

 		{

 		if (strstr(si,"+vis"))

-			OPENSSL_sparcv9cap_P |= SPARCV9_VIS1;

+			OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS1|SPARCV9_BLK;

 		if (strstr(si,"+vis2"))

 			{

-			OPENSSL_sparcv9cap_P |= SPARCV9_VIS2;

-			OPENSSL_sparcv9cap_P &= ~SPARCV9_TICK_PRIVILEGED;

+			OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS2;

+			OPENSSL_sparcv9cap_P[0] &= ~SPARCV9_TICK_PRIVILEGED;

 			return;

 			}

 		}

@@ -193,12 +216,14 @@

 	if ((e=getenv("OPENSSL_sparcv9cap")))

 		{

-		OPENSSL_sparcv9cap_P=strtoul(e,NULL,0);

+		OPENSSL_sparcv9cap_P[0]=strtoul(e,NULL,0);

+		if ((e=strchr(e,':')))

+			OPENSSL_sparcv9cap_P[1]=strtoul(e+1,NULL,0);

 		return;

 		}

 	/* Initial value, fits UltraSPARC-I&II... */

-	OPENSSL_sparcv9cap_P = SPARCV9_PREFER_FPU|SPARCV9_TICK_PRIVILEGED;

+	OPENSSL_sparcv9cap_P[0] = SPARCV9_PREFER_FPU|SPARCV9_TICK_PRIVILEGED;

 	sigfillset(&all_masked);

 	sigdelset(&all_masked,SIGILL);

@@ -221,20 +246,20 @@

 	if (sigsetjmp(common_jmp,1) == 0)

 		{

 		_sparcv9_rdtick();

-		OPENSSL_sparcv9cap_P &= ~SPARCV9_TICK_PRIVILEGED;

+		OPENSSL_sparcv9cap_P[0] &= ~SPARCV9_TICK_PRIVILEGED;

 		}

 	if (sigsetjmp(common_jmp,1) == 0)

 		{

 		_sparcv9_vis1_probe();

-		OPENSSL_sparcv9cap_P |= SPARCV9_VIS1;

+		OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS1|SPARCV9_BLK;

 		/* detect UltraSPARC-Tx, see sparccpud.S for details... */

 		if (_sparcv9_vis1_instrument() >= 12)

-			OPENSSL_sparcv9cap_P &= ~(SPARCV9_VIS1|SPARCV9_PREFER_FPU);

+			OPENSSL_sparcv9cap_P[0] &= ~(SPARCV9_VIS1|SPARCV9_PREFER_FPU);

 		else

 			{

 			_sparcv9_vis2_probe();

-			OPENSSL_sparcv9cap_P |= SPARCV9_VIS2;

+			OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS2;

 			}

 		}

@@ -241,9 +266,37 @@

 	if (sigsetjmp(common_jmp,1) == 0)

 		{

 		_sparcv9_fmadd_probe();

-		OPENSSL_sparcv9cap_P |= SPARCV9_FMADD;

+		OPENSSL_sparcv9cap_P[0] |= SPARCV9_FMADD;

 		}

+	/*

+	 * VIS3 flag is tested independently from VIS1, unlike VIS2 that is,

+	 * because VIS3 defines even integer instructions.

+	 */

+	if (sigsetjmp(common_jmp,1) == 0)

+		{

+		_sparcv9_vis3_probe();

+		OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS3;

+		}

+

+	if (sigsetjmp(common_jmp,1) == 0)

+		{

+		(void)_sparcv9_random();

+		OPENSSL_sparcv9cap_P[0] |= SPARCV9_RANDOM;

+		}

+

+	/*

+	 * In wait for better solution _sparcv9_rdcfr is masked by

+	 * VIS3 flag, because it goes to uninterruptable endless

+	 * loop on UltraSPARC II running Solaris. Things might be

+	 * different on Linux...

+	 */

+	if ((OPENSSL_sparcv9cap_P[0]&SPARCV9_VIS3) &&

+	    sigsetjmp(common_jmp,1) == 0)

+		{

+		OPENSSL_sparcv9cap_P[1] = (unsigned int)_sparcv9_rdcfr();

+		}

+

 	sigaction(SIGBUS,&bus_oact,NULL);

 	sigaction(SIGILL,&ill_oact,NULL);

Index: crypto/md5/Makefile

===================================================================

diff -ru openssl-1.0.1e/crypto/md5/Makefile openssl-1.0.1e/crypto/md5/Makefile

--- openssl-1.0.1e/crypto/md5/Makefile    2011-05-24 17:02:24.000000000 -0700

+++ openssl-1.0.1e/crypto/md5/Makefile    2011-07-27 10:48:17.817470000 -0700

@@ -52,6 +52,9 @@

 	$(CC) $(CFLAGS) -E asm/md5-ia64.S | \

 	$(PERL) -ne 's/;\s+/;\n/g; print;' > $@

+md5-sparcv9.S:	asm/md5-sparcv9.pl

+	$(PERL) asm/md5-sparcv9.pl $@ $(CFLAGS)

+

 files:

 	$(PERL) $(TOP)/util/files.pl Makefile >> $(TOP)/MINFO

Index: crypto/md5/md5_locl.h

===================================================================

diff -ru openssl-1.0.1e/crypto/md5/md5_locl.h openssl-1.0.1e/crypto/md5/md5_locl.h

--- openssl-1.0.1e/crypto/md5/md5_locl.h    2011-05-24 17:02:24.000000000 -0700

+++ openssl-1.0.1e/crypto/md5/md5_locl.h    2011-07-27 10:48:17.817470000 -0700

@@ -71,6 +71,8 @@

 #  define md5_block_data_order md5_block_asm_data_order

 # elif defined(__ia64) || defined(__ia64__) || defined(_M_IA64)

 #  define md5_block_data_order md5_block_asm_data_order

+# elif defined(__sparc) || defined(__sparc__)

+#  define md5_block_data_order md5_block_asm_data_order

 # endif

 #endif

Index: crypto/sha/Makefile

===================================================================

diff -ru openssl-1.0.1e/crypto/sha/Makefile openssl-1.0.1e/crypto/sha/Makefile

--- openssl-1.0.1e/crypto/sha/Makefile    2011-05-24 17:02:24.000000000 -0700

+++ openssl-1.0.1e/crypto/sha/Makefile    2011-07-27 10:48:17.817470000 -0700

@@ -66,9 +66,9 @@

 sha1-x86_64.s:	asm/sha1-x86_64.pl;	$(PERL) asm/sha1-x86_64.pl $(PERLASM_SCHEME) > $@

 sha256-x86_64.s:asm/sha512-x86_64.pl;	$(PERL) asm/sha512-x86_64.pl $(PERLASM_SCHEME) $@

 sha512-x86_64.s:asm/sha512-x86_64.pl;	$(PERL) asm/sha512-x86_64.pl $(PERLASM_SCHEME) $@

-sha1-sparcv9.s:	asm/sha1-sparcv9.pl;	$(PERL) asm/sha1-sparcv9.pl $@ $(CFLAGS)

-sha256-sparcv9.s:asm/sha512-sparcv9.pl;	$(PERL) asm/sha512-sparcv9.pl $@ $(CFLAGS)

-sha512-sparcv9.s:asm/sha512-sparcv9.pl;	$(PERL) asm/sha512-sparcv9.pl $@ $(CFLAGS)

+sha1-sparcv9.S:	asm/sha1-sparcv9.pl;	$(PERL) asm/sha1-sparcv9.pl $@ $(CFLAGS)

+sha256-sparcv9.S:asm/sha512-sparcv9.pl;	$(PERL) asm/sha512-sparcv9.pl $@ $(CFLAGS)

+sha512-sparcv9.S:asm/sha512-sparcv9.pl;	$(PERL) asm/sha512-sparcv9.pl $@ $(CFLAGS)

 sha1-ppc.s:	asm/sha1-ppc.pl;	$(PERL) asm/sha1-ppc.pl $(PERLASM_SCHEME) $@

 sha256-ppc.s:	asm/sha512-ppc.pl;	$(PERL) asm/sha512-ppc.pl $(PERLASM_SCHEME) $@

Index: crypto/sha/asm/sha1-sparcv9.pl

===================================================================

diff -ru openssl-1.0.1e/crypto/sha/asm/sha1-sparcv9.pl openssl-1.0.1e/crypto/sha/asm/sha1-sparcv9.pl

--- openssl-1.0.1e/crypto/sha/asm/sha1-sparcv9.pl 2011-05-24 17:02:24.000000000 -0700

+++ openssl-1.0.1e/crypto/sha/asm/sha1-sparcv9.pl 2011-07-27 10:48:17.817470000 -0700

@@ -5,6 +5,8 @@

 # project. The module is, however, dual licensed under OpenSSL and

 # CRYPTOGAMS licenses depending on where you obtain it. For further

 # details see http://www.openssl.org/~appro/cryptogams/.

+#

+# Hardware SPARC T4 support by David S. Miller <[email protected]>.

 # ====================================================================

 # Performance improvement is not really impressive on pre-T1 CPU: +8%

@@ -18,6 +20,11 @@

 # ensure scalability on UltraSPARC T1, or rather to avoid decay when

 # amount of active threads exceeds the number of physical cores.

+# SPARC T4 SHA1 hardware achieves 3.72 cycles per byte, which is 3.1x

+# faster than software. Multi-process benchmark saturates at 11x

+# single-process result on 8-core processor, or ~9GBps per 2.85GHz

+# socket.

+

 $bits=32;

 for (@ARGV)	{ $bits=64 if (/\-m64/ || /\-xarch\=v9/); }

 if ($bits==64)	{ $bias=2047; $frame=192; }

@@ -183,11 +190,93 @@

 .register	%g3,#scratch

 ___

 $code.=<<___;

+#include "sparc_arch.h"

+

 .section	".text",#alloc,#execinstr

+#ifdef __PIC__

+SPARC_PIC_THUNK(%g1)

+#endif

+

 .align	32

 .globl	sha1_block_data_order

 sha1_block_data_order:

+	SPARC_LOAD_ADDRESS_LEAF(OPENSSL_sparcv9cap_P,%g1,%g5)

+	ld	[%g1+4],%g1		! OPENSSL_sparcv9cap_P[1]

+

+	andcc	%g1, CFR_SHA1, %g0

+	be	.Lsoftware

+	nop

+

+	ld	[%o0 + 0x00], %f0	! load context

+	ld	[%o0 + 0x04], %f1

+	ld	[%o0 + 0x08], %f2

+	andcc	%o1, 0x7, %g0

+	ld	[%o0 + 0x0c], %f3

+	bne,pn	%icc, .Lhwunaligned

+	 ld	[%o0 + 0x10], %f4

+

+.Lhw_loop:

+	ldd	[%o1 + 0x00], %f8

+	ldd	[%o1 + 0x08], %f10

+	ldd	[%o1 + 0x10], %f12

+	ldd	[%o1 + 0x18], %f14

+	ldd	[%o1 + 0x20], %f16

+	ldd	[%o1 + 0x28], %f18

+	ldd	[%o1 + 0x30], %f20

+	subcc	%o2, 1, %o2		! done yet? 

+	ldd	[%o1 + 0x38], %f22

+	add	%o1, 0x40, %o1

+

+	.word	0x81b02820		! SHA1

+

+	bne,pt	`$bits==64?"%xcc":"%icc"`, .Lhw_loop

+	nop

+

+.Lhwfinish:

+	st	%f0, [%o0 + 0x00]	! store context

+	st	%f1, [%o0 + 0x04]

+	st	%f2, [%o0 + 0x08]

+	st	%f3, [%o0 + 0x0c]

+	retl

+	st	%f4, [%o0 + 0x10]

+

+.align	8

+.Lhwunaligned:

+	alignaddr %o1, %g0, %o1

+

+	ldd	[%o1 + 0x00], %f10

+.Lhwunaligned_loop:

+	ldd	[%o1 + 0x08], %f12

+	ldd	[%o1 + 0x10], %f14

+	ldd	[%o1 + 0x18], %f16

+	ldd	[%o1 + 0x20], %f18

+	ldd	[%o1 + 0x28], %f20

+	ldd	[%o1 + 0x30], %f22

+	ldd	[%o1 + 0x38], %f24

+	subcc	%o2, 1, %o2		! done yet?

+	ldd	[%o1 + 0x40], %f26

+	add	%o1, 0x40, %o1

+

+	faligndata %f10, %f12, %f8

+	faligndata %f12, %f14, %f10

+	faligndata %f14, %f16, %f12

+	faligndata %f16, %f18, %f14

+	faligndata %f18, %f20, %f16

+	faligndata %f20, %f22, %f18

+	faligndata %f22, %f24, %f20

+	faligndata %f24, %f26, %f22

+

+	.word	0x81b02820		! SHA1

+

+	bne,pt	`$bits==64?"%xcc":"%icc"`, .Lhwunaligned_loop

+	for	%f26, %f26, %f10	! %f10=%f26

+

+	ba	.Lhwfinish

+	nop

+

+.align	16

+.Lsoftware:

 	save	%sp,-$frame,%sp

 	sllx	$len,6,$len

 	add	$inp,$len,$len

@@ -279,6 +368,62 @@

 .align	4

 ___

-$code =~ s/\`([^\`]*)\`/eval $1/gem;

-print $code;

+# Purpose of these subroutines is to explicitly encode VIS instructions,

+# so that one can compile the module without having to specify VIS

+# extentions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.

+# Idea is to reserve for option to produce "universal" binary and let

+# programmer detect if current CPU is VIS capable at run-time.

+sub unvis {

+my ($mnemonic,$rs1,$rs2,$rd)=@_;

+my $ref,$opf;

+my %visopf = (	"faligndata"	=> 0x048,

+		"for"		=> 0x07c	);

+

+    $ref = "$mnemonic\t$rs1,$rs2,$rd";

+

+    if ($opf=$visopf{$mnemonic}) {

+	foreach ($rs1,$rs2,$rd) {

+	    return $ref if (!/%f([0-9]{1,2})/);

+	    $_=$1;

+	    if ($1>=32) {

+		return $ref if ($1&1);

+		# re-encode for upper double register addressing

+		$_=($1|$1>>5)&31;

+	    }

+	}

+

+	return	sprintf ".word\t0x%08x !%s",

+			0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,

+			$ref;

+    } else {

+	return $ref;

+    }

+}

+sub unalignaddr {

+my ($mnemonic,$rs1,$rs2,$rd)=@_;

+my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );

+my $ref="$mnemonic\t$rs1,$rs2,$rd";

+

+    foreach ($rs1,$rs2,$rd) {

+	if (/%([goli])([0-7])/)	{ $_=$bias{$1}+$2; }

+	else			{ return $ref; }

+    }

+    return  sprintf ".word\t0x%08x !%s",

+		    0x81b00300|$rd<<25|$rs1<<14|$rs2,

+		    $ref;

+}

+

+foreach (split("\n",$code)) {

+	s/\`([^\`]*)\`/eval $1/ge;

+

+	s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/

+		&unvis($1,$2,$3,$4)

+	 /ge;

+	s/\b(alignaddr)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/

+		&unalignaddr($1,$2,$3,$4)

+	 /ge;

+