/*

 * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.

 */

/*

 * Redistribution and use in source and binary forms, with or without modification,

 * are permitted provided that the following conditions are met:

 *

 * 1. Redistributions of source code must retain the above copyright notice,

 *    this list of conditions and the following disclaimer.

 *

 * 2. Redistributions in binary form must reproduce the above copyright notice,

 *    this list of conditions and the following disclaimer in the documentation

 *    and/or other materials provided with the distribution.

 *

 * 3. Neither the name of the copyright holder nor the names of its contributors

 *    may be used to endorse or promote products derived from this software without

 *    specific prior written permission.

 *

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.

 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF

 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED

 * OF THE POSSIBILITY OF SUCH DAMAGE.

 */

#ifndef	_PSIF_HW_SETGET_H

#define	_PSIF_HW_SETGET_H

#ifdef __cplusplus

extern "C" {

#endif

#include "psif_api.h"

#if defined(__arm__)

#include "epsfw_misc.h"

#  define htobe64(x) eps_htobe64(x)

#  define be64toh(x) eps_be64toh(x)

#endif /* __arm__ */

#include "psif_endian.h"

#if !defined(__KERNEL__)

#include "os_header.h"

#endif

/*

 * PSIF_WR_INVALIDATE_LKEY: key to invalidate/flush from the DMA VT cache.

 * PSIF_WR_INVALIDATE_RKEY: key to invalidate/flush from the DMA VT cache.

 * PSIF_WR_INVALIDATE_BOTH_KEYS: key to invalidate/flush from the DMA VT

 * cache. PSIF_WR_INVALIDATE_TLB: this is the address vector to invalidate in

 * the TLB.

 */

static inline void set_psif_wr_su__key(volatile struct psif_wr_su *ptr, u32 data)

{

	/* group=2 shift=32 bits=32 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[2] = htobe64((be64toh(pte[2]) & 0x00000000ffffffffull) | 

		((((u64)(data)) & 0x00000000ffffffffull) << 32));

}

static inline u32 get_psif_wr_su__key(volatile struct psif_wr_su *ptr)

{

	/* group=2 shift=32 bits=32 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u32)((be64toh(pte[2]) >> 32) & 0x00000000ffffffffull));

}

/*

 * Send queue sequence number. Used to map request to a particular work

 * request in the send queue.

 */

static inline void set_psif_wr__sq_seq(volatile struct psif_wr *ptr, u16 data)

{

	/* group=0 shift=0 bits=16 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xffffffffffff0000ull) | 

		((((u64)(data)) & 0x000000000000ffffull) << 0));

}

static inline u16 get_psif_wr__sq_seq(volatile struct psif_wr *ptr)

{

	/* group=0 shift=0 bits=16 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u16)((be64toh(pte[0]) >> 0) & 0x000000000000ffffull));

}

/*

 * QP sending this request. XXX: Should name be own_qp_num as defined in QP

 * state?

 */

static inline void set_psif_wr__local_qp(volatile struct psif_wr *ptr, u32 data)

{

	/* group=0 shift=32 bits=24 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xff000000ffffffffull) | 

		((((u64)(data)) & 0x0000000000ffffffull) << 32));

}

static inline u32 get_psif_wr__local_qp(volatile struct psif_wr *ptr)

{

	/* group=0 shift=32 bits=24 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u32)((be64toh(pte[0]) >> 32) & 0x0000000000ffffffull));

}

/* Completion notification identifier. */

static inline void set_psif_wr__completion(volatile struct psif_wr *ptr, u8 data)

{

	/* group=1 shift=31 bits=1 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[1] = htobe64((be64toh(pte[1]) & 0xffffffff7fffffffull) | 

		((((u64)(data)) & 0x0000000000000001ull) << 31));

}

static inline u8 get_psif_wr__completion(volatile struct psif_wr *ptr)

{

	/* group=1 shift=31 bits=1 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u8)((be64toh(pte[1]) >> 31) & 0x0000000000000001ull));

}

/*

 * Checksum used for data protection and consistency between work request and

 * QP state.

 */

static inline void set_psif_wr__checksum(volatile struct psif_wr *ptr, u32 data)

{

	/* group=2 shift=32 bits=32 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[2] = htobe64((be64toh(pte[2]) & 0x00000000ffffffffull) | 

		((((u64)(data)) & 0x00000000ffffffffull) << 32));

}

static inline u32 get_psif_wr__checksum(volatile struct psif_wr *ptr)

{

	/* group=2 shift=32 bits=32 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u32)((be64toh(pte[2]) >> 32) & 0x00000000ffffffffull));

}

/*

 * Index to where elements are added to the send queue by SW. SW is

 * responsibel for keeping track of how many entries there are in the send

 * queue. I.e. SW needs to keep track of the head_index so it doesn't

 * overwrite entries in the send queue which is not yet completed.

 */

static inline void set_psif_sq_sw__tail_indx(volatile struct psif_sq_sw *ptr, u16 data)

{

	/* group=0 shift=32 bits=16 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xffff0000ffffffffull) | 

		((((u64)(data)) & 0x000000000000ffffull) << 32));

}

static inline u16 get_psif_sq_sw__tail_indx(volatile struct psif_sq_sw *ptr)

{

	/* group=0 shift=32 bits=16 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u16)((be64toh(pte[0]) >> 32) & 0x000000000000ffffull));

}

/*

 * Send queue sequence number used by the SQS to maintain ordering and keep

 * track of where which send queue elements to fetch. This field is not in

 * sync with the field in qp_t. This number is typically a little bit before

 * the number in the qp_t as SQS has to fetch the elements from host memory.

 * This is also used as tail_index when checking if there are more elements

 * in the send queue.

 */

static inline void set_psif_sq_hw__last_seq(volatile struct psif_sq_hw *ptr, u16 data)

{

	/* group=0 shift=16 bits=16 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xffffffff0000ffffull) | 

		((((u64)(data)) & 0x000000000000ffffull) << 16));

}

static inline u16 get_psif_sq_hw__last_seq(volatile struct psif_sq_hw *ptr)

{

	/* group=0 shift=16 bits=16 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u16)((be64toh(pte[0]) >> 16) & 0x000000000000ffffull));

}

/* QP and UF to be processed next. */

static inline void set_psif_sq_hw__sq_next(volatile struct psif_sq_hw *ptr, u32 data)

{

	/* group=0 shift=32 bits=32 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0x00000000ffffffffull) | 

		((((u64)(data)) & 0x00000000ffffffffull) << 32));

}

static inline u32 get_psif_sq_hw__sq_next(volatile struct psif_sq_hw *ptr)

{

	/* group=0 shift=32 bits=32 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u32)((be64toh(pte[0]) >> 32) & 0x00000000ffffffffull));

}

/*

 * This bit is set through the doorbell. SW should check this bit plus

 * psif_next = null to ensure SW can own the SQ descriptor.

 */

static inline void set_psif_sq_hw__destroyed(volatile struct psif_sq_hw *ptr, u8 data)

{

	/* group=1 shift=27 bits=1 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[1] = htobe64((be64toh(pte[1]) & 0xfffffffff7ffffffull) | 

		((((u64)(data)) & 0x0000000000000001ull) << 27));

}

static inline u8 get_psif_sq_hw__destroyed(volatile struct psif_sq_hw *ptr)

{

	/* group=1 shift=27 bits=1 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u8)((be64toh(pte[1]) >> 27) & 0x0000000000000001ull));

}

/* Software modified index pointing to the tail reecive entry in host memory. */

static inline void set_psif_rq_sw__tail_indx(volatile struct psif_rq_sw *ptr, u16 data)

{

	/* group=0 shift=32 bits=14 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xffffc000ffffffffull) | 

		((((u64)(data)) & 0x0000000000003fffull) << 32));

}

static inline u16 get_psif_rq_sw__tail_indx(volatile struct psif_rq_sw *ptr)

{

	/* group=0 shift=32 bits=14 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u16)((be64toh(pte[0]) >> 32) & 0x0000000000003fffull));

}

/*

 * Hardware modified index pointing to the head of the receive queue. TSU is

 * using this to find the address of the receive queue entry.

 */

static inline void set_psif_rq_hw__head_indx(volatile struct psif_rq_hw *ptr, u16 data)

{

	/* group=0 shift=14 bits=14 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xfffffffff0003fffull) | 

		((((u64)(data)) & 0x0000000000003fffull) << 14));

}

static inline u16 get_psif_rq_hw__head_indx(volatile struct psif_rq_hw *ptr)

{

	/* group=0 shift=14 bits=14 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u16)((be64toh(pte[0]) >> 14) & 0x0000000000003fffull));

}

/* The desciptor is valid. */

static inline void set_psif_rq_hw__valid(volatile struct psif_rq_hw *ptr, u8 data)

{

	/* group=3 shift=55 bits=1 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[3] = htobe64((be64toh(pte[3]) & 0xff7fffffffffffffull) | 

		((((u64)(data)) & 0x0000000000000001ull) << 55));

}

static inline u8 get_psif_rq_hw__valid(volatile struct psif_rq_hw *ptr)

{

	/* group=3 shift=55 bits=1 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u8)((be64toh(pte[3]) >> 55) & 0x0000000000000001ull));

}

/*

 * Receive queue entry ID. This is added to the receive completion using this

 * receive queue entry.

 */

static inline void set_psif_rq_entry__rqe_id(volatile struct psif_rq_entry *ptr, u64 data)

{

	/* group=0 shift=0 bits=64 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((__be64)data);

}

static inline u64 get_psif_rq_entry__rqe_id(volatile struct psif_rq_entry *ptr)

{

	/* group=0 shift=0 bits=64 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u64)be64toh(pte[0]));

}

/*

 * This retry tag is the one used by tsu_rqs and added to the packets sent to

 * tsu_dma. It is the responsibility of tsu_rqs to update this retry tag

 * whenever the sq_sequence_number in QP state is equal to the one in the

 * request.

 */

static inline void set_psif_qp_core__retry_tag_committed(volatile struct psif_qp_core *ptr, u8 data)

{

	/* group=0 shift=0 bits=3 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xfffffffffffffff8ull) | 

		((((u64)(data)) & 0x0000000000000007ull) << 0));

}

static inline u8 get_psif_qp_core__retry_tag_committed(volatile struct psif_qp_core *ptr)

{

	/* group=0 shift=0 bits=3 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u8)((be64toh(pte[0]) >> 0) & 0x0000000000000007ull));

}

/*

 * This retry tag is updated by the error block when an error occur. If

 * tsu_rqs reads this retry tag and it is different than the

 * retry_tag_comitted, tsu_rqs must update retry_tag_comitted to the value of

 * retry_tag_err when the sq_sequence_number indicates this is the valid

 * request. The sq_sequence_number has been updated by tsu_err at the same

 * time the retry_tag_err is updated.

 */

static inline void set_psif_qp_core__retry_tag_err(volatile struct psif_qp_core *ptr, u8 data)

{

	/* group=0 shift=3 bits=3 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xffffffffffffffc7ull) | 

		((((u64)(data)) & 0x0000000000000007ull) << 3));

}

static inline u8 get_psif_qp_core__retry_tag_err(volatile struct psif_qp_core *ptr)

{

	/* group=0 shift=3 bits=3 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u8)((be64toh(pte[0]) >> 3) & 0x0000000000000007ull));

}

/*

 * Error retry counter initial value. Read by tsu_dma and used by tsu_cmpl to

 * calculate exp_backoff etc..

 */

static inline void set_psif_qp_core__error_retry_init(volatile struct psif_qp_core *ptr, u8 data)

{

	/* group=0 shift=32 bits=3 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xfffffff8ffffffffull) | 

		((((u64)(data)) & 0x0000000000000007ull) << 32));

}

static inline u8 get_psif_qp_core__error_retry_init(volatile struct psif_qp_core *ptr)

{

	/* group=0 shift=32 bits=3 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u8)((be64toh(pte[0]) >> 32) & 0x0000000000000007ull));

}

/*

 * Retry counter associated with retries to received NAK or implied NAK. If

 * it expires, a path migration will be attempted if it is armed, or the QP

 * will go to error state. Read by tsu_dma and used by tsu_cmpl.

 */

static inline void set_psif_qp_core__error_retry_count(volatile struct psif_qp_core *ptr, u8 data)

{

	/* group=0 shift=35 bits=3 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xffffffc7ffffffffull) | 

		((((u64)(data)) & 0x0000000000000007ull) << 35));

}

static inline u8 get_psif_qp_core__error_retry_count(volatile struct psif_qp_core *ptr)

{

	/* group=0 shift=35 bits=3 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u8)((be64toh(pte[0]) >> 35) & 0x0000000000000007ull));

}

/* A hit in the set locally spun out of tsu_cmpl is found. */

static inline void set_psif_qp_core__spin_hit(volatile struct psif_qp_core *ptr, u8 data)

{

	/* group=0 shift=39 bits=1 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[0] = htobe64((be64toh(pte[0]) & 0xffffff7fffffffffull) | 

		((((u64)(data)) & 0x0000000000000001ull) << 39));

}

static inline u8 get_psif_qp_core__spin_hit(volatile struct psif_qp_core *ptr)

{

	/* group=0 shift=39 bits=1 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u8)((be64toh(pte[0]) >> 39) & 0x0000000000000001ull));

}

/*

 * Minium RNR NAK timeout. This is added to RNR NAK packets and the requester

 * receiving the RNR NAK must wait until the timer has expired before the

 * retry is sent.

 */

static inline void set_psif_qp_core__min_rnr_nak_time(volatile struct psif_qp_core *ptr, u8 data)

{

	/* group=1 shift=0 bits=5 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[1] = htobe64((be64toh(pte[1]) & 0xffffffffffffffe0ull) | 

		((((u64)(data)) & 0x000000000000001full) << 0));

}

static inline u8 get_psif_qp_core__min_rnr_nak_time(volatile struct psif_qp_core *ptr)

{

	/* group=1 shift=0 bits=5 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u8)((be64toh(pte[1]) >> 0) & 0x000000000000001full));

}

/* QP State for this QP. */

static inline void set_psif_qp_core__state(volatile struct psif_qp_core *ptr, enum psif_qp_state data)

{

	/* group=1 shift=5 bits=3 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[1] = htobe64((be64toh(pte[1]) & 0xffffffffffffff1full) | 

		((((u64)(data)) & 0x0000000000000007ull) << 5));

}

static inline enum psif_qp_state get_psif_qp_core__state(volatile struct psif_qp_core *ptr)

{

	/* group=1 shift=5 bits=3 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((enum psif_qp_state)((be64toh(pte[1]) >> 5) & 0x0000000000000007ull));

}

/* QP number for the remote node. */

static inline void set_psif_qp_core__remote_qp(volatile struct psif_qp_core *ptr, u32 data)

{

	/* group=1 shift=8 bits=24 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[1] = htobe64((be64toh(pte[1]) & 0xffffffff000000ffull) | 

		((((u64)(data)) & 0x0000000000ffffffull) << 8));

}

static inline u32 get_psif_qp_core__remote_qp(volatile struct psif_qp_core *ptr)

{

	/* group=1 shift=8 bits=24 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u32)((be64toh(pte[1]) >> 8) & 0x0000000000ffffffull));

}

static inline void set_psif_qp_core__retry_sq_seq(volatile struct psif_qp_core *ptr, u16 data)

{

	/* group=2 shift=32 bits=16 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[2] = htobe64((be64toh(pte[2]) & 0xffff0000ffffffffull) | 

		((((u64)(data)) & 0x000000000000ffffull) << 32));

}

static inline u16 get_psif_qp_core__retry_sq_seq(volatile struct psif_qp_core *ptr)

{

	/* group=2 shift=32 bits=16 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u16)((be64toh(pte[2]) >> 32) & 0x000000000000ffffull));

}

static inline void set_psif_qp_core__sq_seq(volatile struct psif_qp_core *ptr, u16 data)

{

	/* group=2 shift=48 bits=16 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[2] = htobe64((be64toh(pte[2]) & 0x0000ffffffffffffull) | 

		((((u64)(data)) & 0x000000000000ffffull) << 48));

}

static inline u16 get_psif_qp_core__sq_seq(volatile struct psif_qp_core *ptr)

{

	/* group=2 shift=48 bits=16 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u16)((be64toh(pte[2]) >> 48) & 0x000000000000ffffull));

}

/*

 * Magic number used to verify use of QP state. This is done by calculating a

 * checksum of the work request incorporating the magic number. This checksum

 * is checked against the checksum in the work request.

 */

static inline void set_psif_qp_core__magic(volatile struct psif_qp_core *ptr, u32 data)

{

	/* group=3 shift=0 bits=32 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[3] = htobe64((be64toh(pte[3]) & 0xffffffff00000000ull) | 

		((((u64)(data)) & 0x00000000ffffffffull) << 0));

}

static inline u32 get_psif_qp_core__magic(volatile struct psif_qp_core *ptr)

{

	/* group=3 shift=0 bits=32 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u32)((be64toh(pte[3]) >> 0) & 0x00000000ffffffffull));

}

/*

 * Q-Key received in incoming IB packet is checked towards this Q-Key. Q-Key

 * used on transmit if top bit of Q-Key in WR is set.

 */

static inline void set_psif_qp_core__qkey(volatile struct psif_qp_core *ptr, u32 data)

{

	/* group=4 shift=0 bits=32 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[4] = htobe64((be64toh(pte[4]) & 0xffffffff00000000ull) | 

		((((u64)(data)) & 0x00000000ffffffffull) << 0));

}

static inline u32 get_psif_qp_core__qkey(volatile struct psif_qp_core *ptr)

{

	/* group=4 shift=0 bits=32 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u32)((be64toh(pte[4]) >> 0) & 0x00000000ffffffffull));

}

/*

 * Sequence number of the last ACK received. Read and written by tsu_cmpl.

 * Used to verify that the received response packet is a valid response.

 */

static inline void set_psif_qp_core__last_acked_psn(volatile struct psif_qp_core *ptr, u32 data)

{

	/* group=4 shift=40 bits=24 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[4] = htobe64((be64toh(pte[4]) & 0x000000ffffffffffull) | 

		((((u64)(data)) & 0x0000000000ffffffull) << 40));

}

static inline u32 get_psif_qp_core__last_acked_psn(volatile struct psif_qp_core *ptr)

{

	/* group=4 shift=40 bits=24 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u32)((be64toh(pte[4]) >> 40) & 0x0000000000ffffffull));

}

/* Index to scatter element of in progress SEND. */

static inline void set_psif_qp_core__scatter_indx(volatile struct psif_qp_core *ptr, u8 data)

{

	/* group=5 shift=32 bits=5 */

	volatile __be64 *const pte = (__be64 *)ptr;

	pte[5] = htobe64((be64toh(pte[5]) & 0xffffffe0ffffffffull) | 

		((((u64)(data)) & 0x000000000000001full) << 32));

}

static inline u8 get_psif_qp_core__scatter_indx(volatile struct psif_qp_core *ptr)

{

	/* group=5 shift=32 bits=5 */

	volatile __be64 *const pte = (__be64 *)ptr;

	return((u8)((be64toh(pte[5]) >> 32) & 0x000000000000001full));

}

/*

 * Expected packet sequence number: Sequence number on next expected packet.

 */

static inline void set_psif_qp_core__expected_psn(volatile struct psif_qp_core *ptr, u32 data)

{

	/* group=5 shift=40 bits=24 */

	volatile __be64 *const pte = (__be64 *)ptr;