equal
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inserted
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18 # |
18 # |
19 # CDDL HEADER END |
19 # CDDL HEADER END |
20 # |
20 # |
21 |
21 |
22 # |
22 # |
23 # Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved. |
23 # Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved. |
24 # |
24 # |
25 |
25 |
26 include ../../../make-rules/shared-macros.mk |
26 include ../../../make-rules/shared-macros.mk |
27 |
27 |
28 COMPONENT_NAME= logilab-common |
28 COMPONENT_NAME= logilab-common |
32 COMPONENT_ARCHIVE= $(COMPONENT_SRC).tar.gz |
32 COMPONENT_ARCHIVE= $(COMPONENT_SRC).tar.gz |
33 COMPONENT_ARCHIVE_HASH= \ |
33 COMPONENT_ARCHIVE_HASH= \ |
34 sha256:62b0d88d9276e86b48c7188cea8d91d8ff1744d046ea6323d40359aa53aef708 |
34 sha256:62b0d88d9276e86b48c7188cea8d91d8ff1744d046ea6323d40359aa53aef708 |
35 COMPONENT_ARCHIVE_URL= $(call pypi_url) |
35 COMPONENT_ARCHIVE_URL= $(call pypi_url) |
36 COMPONENT_BUGDB= python-mod/logilab-common |
36 COMPONENT_BUGDB= python-mod/logilab-common |
|
37 COMPONENT_ANITYA_ID= 13260 |
37 |
38 |
38 TPNO= 31342 |
39 TPNO= 31342 |
39 |
40 |
40 include $(WS_MAKE_RULES)/prep.mk |
41 include $(WS_MAKE_RULES)/prep.mk |
41 include $(WS_MAKE_RULES)/ips.mk |
42 include $(WS_MAKE_RULES)/ips.mk |