1 #!/usr/bin/env perl |
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2 |
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3 # ==================================================================== |
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4 # Written by Andy Polyakov <[email protected]> for the OpenSSL |
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5 # project. The module is, however, dual licensed under OpenSSL and |
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6 # CRYPTOGAMS licenses depending on where you obtain it. For further |
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7 # details see http://www.openssl.org/~appro/cryptogams/. |
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8 # |
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9 # Hardware SPARC T4 support by David S. Miller <[email protected]>. |
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10 # ==================================================================== |
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11 |
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12 # MD5 for SPARCv9, 6.9 cycles per byte on UltraSPARC, >40% faster than |
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13 # code generated by Sun C 5.2. |
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14 |
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15 # SPARC T4 MD5 hardware achieves 3.20 cycles per byte, which is 2.1x |
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16 # faster than software. Multi-process benchmark saturates at 12x |
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17 # single-process result on 8-core processor, or ~11GBps per 2.85GHz |
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18 # socket. |
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19 |
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20 $bits=32; |
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21 for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); } |
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22 if ($bits==64) { $bias=2047; $frame=192; } |
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23 else { $bias=0; $frame=112; } |
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24 |
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25 $output=shift; |
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26 open STDOUT,">$output"; |
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27 |
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28 use integer; |
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29 |
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30 ($ctx,$inp,$len)=("%i0","%i1","%i2"); # input arguments |
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31 |
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32 # 64-bit values |
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33 @X=("%o0","%o1","%o2","%o3","%o4","%o5","%o7","%g1","%g2"); |
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34 $tx="%g3"; |
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35 ($AB,$CD)=("%g4","%g5"); |
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36 |
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37 # 32-bit values |
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38 @V=($A,$B,$C,$D)=map("%l$_",(0..3)); |
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39 ($t1,$t2,$t3,$saved_asi)=map("%l$_",(4..7)); |
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40 ($shr,$shl1,$shl2)=("%i3","%i4","%i5"); |
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41 |
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42 my @K=( 0xd76aa478,0xe8c7b756,0x242070db,0xc1bdceee, |
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43 0xf57c0faf,0x4787c62a,0xa8304613,0xfd469501, |
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44 0x698098d8,0x8b44f7af,0xffff5bb1,0x895cd7be, |
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45 0x6b901122,0xfd987193,0xa679438e,0x49b40821, |
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46 |
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47 0xf61e2562,0xc040b340,0x265e5a51,0xe9b6c7aa, |
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48 0xd62f105d,0x02441453,0xd8a1e681,0xe7d3fbc8, |
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49 0x21e1cde6,0xc33707d6,0xf4d50d87,0x455a14ed, |
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50 0xa9e3e905,0xfcefa3f8,0x676f02d9,0x8d2a4c8a, |
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51 |
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52 0xfffa3942,0x8771f681,0x6d9d6122,0xfde5380c, |
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53 0xa4beea44,0x4bdecfa9,0xf6bb4b60,0xbebfbc70, |
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54 0x289b7ec6,0xeaa127fa,0xd4ef3085,0x04881d05, |
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55 0xd9d4d039,0xe6db99e5,0x1fa27cf8,0xc4ac5665, |
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56 |
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57 0xf4292244,0x432aff97,0xab9423a7,0xfc93a039, |
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58 0x655b59c3,0x8f0ccc92,0xffeff47d,0x85845dd1, |
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59 0x6fa87e4f,0xfe2ce6e0,0xa3014314,0x4e0811a1, |
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60 0xf7537e82,0xbd3af235,0x2ad7d2bb,0xeb86d391, 0 ); |
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61 |
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62 sub R0 { |
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63 my ($i,$a,$b,$c,$d) = @_; |
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64 my $rot = (7,12,17,22)[$i%4]; |
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65 my $j = ($i+1)/2; |
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66 |
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67 if ($i&1) { |
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68 $code.=<<___; |
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69 srlx @X[$j],$shr,@X[$j] ! align X[`$i+1`] |
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70 and $b,$t1,$t1 ! round $i |
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71 sllx @X[$j+1],$shl1,$tx |
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72 add $t2,$a,$a |
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73 sllx $tx,$shl2,$tx |
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74 xor $d,$t1,$t1 |
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75 or $tx,@X[$j],@X[$j] |
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76 sethi %hi(@K[$i+1]),$t2 |
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77 add $t1,$a,$a |
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78 or $t2,%lo(@K[$i+1]),$t2 |
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79 sll $a,$rot,$t3 |
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80 add @X[$j],$t2,$t2 ! X[`$i+1`]+K[`$i+1`] |
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81 srl $a,32-$rot,$a |
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82 add $b,$t3,$t3 |
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83 xor $b,$c,$t1 |
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84 add $t3,$a,$a |
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85 ___ |
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86 } else { |
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87 $code.=<<___; |
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88 srlx @X[$j],32,$tx ! extract X[`2*$j+1`] |
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89 and $b,$t1,$t1 ! round $i |
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90 add $t2,$a,$a |
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91 xor $d,$t1,$t1 |
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92 sethi %hi(@K[$i+1]),$t2 |
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93 add $t1,$a,$a |
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94 or $t2,%lo(@K[$i+1]),$t2 |
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95 sll $a,$rot,$t3 |
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96 add $tx,$t2,$t2 ! X[`2*$j+1`]+K[`$i+1`] |
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97 srl $a,32-$rot,$a |
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98 add $b,$t3,$t3 |
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99 xor $b,$c,$t1 |
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100 add $t3,$a,$a |
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101 ___ |
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102 } |
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103 } |
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104 |
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105 sub R0_1 { |
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106 my ($i,$a,$b,$c,$d) = @_; |
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107 my $rot = (7,12,17,22)[$i%4]; |
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108 |
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109 $code.=<<___; |
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110 srlx @X[0],32,$tx ! extract X[1] |
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111 and $b,$t1,$t1 ! round $i |
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112 add $t2,$a,$a |
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113 xor $d,$t1,$t1 |
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114 sethi %hi(@K[$i+1]),$t2 |
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115 add $t1,$a,$a |
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116 or $t2,%lo(@K[$i+1]),$t2 |
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117 sll $a,$rot,$t3 |
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118 add $tx,$t2,$t2 ! X[1]+K[`$i+1`] |
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119 srl $a,32-$rot,$a |
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120 add $b,$t3,$t3 |
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121 andn $b,$c,$t1 |
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122 add $t3,$a,$a |
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123 ___ |
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124 } |
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125 |
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126 sub R1 { |
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127 my ($i,$a,$b,$c,$d) = @_; |
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128 my $rot = (5,9,14,20)[$i%4]; |
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129 my $j = $i<31 ? (1+5*($i+1))%16 : (5+3*($i+1))%16; |
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130 my $xi = @X[$j/2]; |
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131 |
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132 $code.=<<___ if ($j&1 && ($xi=$tx)); |
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133 srlx @X[$j/2],32,$xi ! extract X[$j] |
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134 ___ |
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135 $code.=<<___; |
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136 and $b,$d,$t3 ! round $i |
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137 add $t2,$a,$a |
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138 or $t3,$t1,$t1 |
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139 sethi %hi(@K[$i+1]),$t2 |
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140 add $t1,$a,$a |
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141 or $t2,%lo(@K[$i+1]),$t2 |
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142 sll $a,$rot,$t3 |
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143 add $xi,$t2,$t2 ! X[$j]+K[`$i+1`] |
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144 srl $a,32-$rot,$a |
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145 add $b,$t3,$t3 |
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146 `$i<31?"andn":"xor"` $b,$c,$t1 |
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147 add $t3,$a,$a |
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148 ___ |
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149 } |
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150 |
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151 sub R2 { |
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152 my ($i,$a,$b,$c,$d) = @_; |
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153 my $rot = (4,11,16,23)[$i%4]; |
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154 my $j = $i<47 ? (5+3*($i+1))%16 : (0+7*($i+1))%16; |
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155 my $xi = @X[$j/2]; |
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156 |
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157 $code.=<<___ if ($j&1 && ($xi=$tx)); |
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158 srlx @X[$j/2],32,$xi ! extract X[$j] |
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159 ___ |
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160 $code.=<<___; |
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161 add $t2,$a,$a ! round $i |
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162 xor $b,$t1,$t1 |
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163 sethi %hi(@K[$i+1]),$t2 |
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164 add $t1,$a,$a |
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165 or $t2,%lo(@K[$i+1]),$t2 |
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166 sll $a,$rot,$t3 |
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167 add $xi,$t2,$t2 ! X[$j]+K[`$i+1`] |
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168 srl $a,32-$rot,$a |
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169 add $b,$t3,$t3 |
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170 xor $b,$c,$t1 |
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171 add $t3,$a,$a |
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172 ___ |
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173 } |
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174 |
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175 sub R3 { |
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176 my ($i,$a,$b,$c,$d) = @_; |
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177 my $rot = (6,10,15,21)[$i%4]; |
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178 my $j = (0+7*($i+1))%16; |
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179 my $xi = @X[$j/2]; |
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180 |
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181 $code.=<<___; |
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182 add $t2,$a,$a ! round $i |
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183 ___ |
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184 $code.=<<___ if ($j&1 && ($xi=$tx)); |
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185 srlx @X[$j/2],32,$xi ! extract X[$j] |
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186 ___ |
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187 $code.=<<___; |
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188 orn $b,$d,$t1 |
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189 sethi %hi(@K[$i+1]),$t2 |
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190 xor $c,$t1,$t1 |
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191 or $t2,%lo(@K[$i+1]),$t2 |
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192 add $t1,$a,$a |
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193 sll $a,$rot,$t3 |
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194 add $xi,$t2,$t2 ! X[$j]+K[`$i+1`] |
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195 srl $a,32-$rot,$a |
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196 add $b,$t3,$t3 |
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197 add $t3,$a,$a |
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198 ___ |
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199 } |
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200 |
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201 $code.=<<___ if ($bits==64); |
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202 .register %g2,#scratch |
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203 .register %g3,#scratch |
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204 ___ |
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205 $code.=<<___; |
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206 #include "sparc_arch.h" |
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207 |
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208 .section ".text",#alloc,#execinstr |
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209 |
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210 #ifdef __PIC__ |
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211 SPARC_PIC_THUNK(%g1) |
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212 #endif |
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213 |
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214 .globl md5_block_asm_data_order |
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215 .align 32 |
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216 md5_block_asm_data_order: |
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217 SPARC_LOAD_ADDRESS_LEAF(OPENSSL_sparcv9cap_P,%g1,%g5) |
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218 ld [%g1+4],%g1 ! OPENSSL_sparcv9cap_P[1] |
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219 |
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220 andcc %g1, CFR_MD5, %g0 |
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221 be .Lsoftware |
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222 nop |
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223 |
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224 mov 4, %g1 |
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225 andcc %o1, 0x7, %g0 |
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226 lda [%o0 + %g0]0x88, %f0 ! load context |
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227 lda [%o0 + %g1]0x88, %f1 |
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228 add %o0, 8, %o0 |
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229 lda [%o0 + %g0]0x88, %f2 |
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230 lda [%o0 + %g1]0x88, %f3 |
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231 bne,pn %icc, .Lhwunaligned |
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232 sub %o0, 8, %o0 |
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233 |
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234 .Lhw_loop: |
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235 ldd [%o1 + 0x00], %f8 |
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236 ldd [%o1 + 0x08], %f10 |
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237 ldd [%o1 + 0x10], %f12 |
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238 ldd [%o1 + 0x18], %f14 |
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239 ldd [%o1 + 0x20], %f16 |
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240 ldd [%o1 + 0x28], %f18 |
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241 ldd [%o1 + 0x30], %f20 |
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242 subcc %o2, 1, %o2 ! done yet? |
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243 ldd [%o1 + 0x38], %f22 |
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244 add %o1, 0x40, %o1 |
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245 prefetch [%o1 + 63], 20 |
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246 |
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247 .word 0x81b02800 ! MD5 |
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248 |
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249 bne,pt `$bits==64?"%xcc":"%icc"`, .Lhw_loop |
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250 nop |
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251 |
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252 .Lhwfinish: |
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253 sta %f0, [%o0 + %g0]0x88 ! store context |
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254 sta %f1, [%o0 + %g1]0x88 |
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255 add %o0, 8, %o0 |
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256 sta %f2, [%o0 + %g0]0x88 |
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257 sta %f3, [%o0 + %g1]0x88 |
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258 retl |
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259 nop |
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260 |
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261 .align 8 |
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262 .Lhwunaligned: |
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263 alignaddr %o1, %g0, %o1 |
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264 |
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265 ldd [%o1 + 0x00], %f10 |
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266 .Lhwunaligned_loop: |
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267 ldd [%o1 + 0x08], %f12 |
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268 ldd [%o1 + 0x10], %f14 |
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269 ldd [%o1 + 0x18], %f16 |
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270 ldd [%o1 + 0x20], %f18 |
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271 ldd [%o1 + 0x28], %f20 |
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272 ldd [%o1 + 0x30], %f22 |
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273 ldd [%o1 + 0x38], %f24 |
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274 subcc %o2, 1, %o2 ! done yet? |
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275 ldd [%o1 + 0x40], %f26 |
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276 add %o1, 0x40, %o1 |
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277 prefetch [%o1 + 63], 20 |
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278 |
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279 faligndata %f10, %f12, %f8 |
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280 faligndata %f12, %f14, %f10 |
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281 faligndata %f14, %f16, %f12 |
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282 faligndata %f16, %f18, %f14 |
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283 faligndata %f18, %f20, %f16 |
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284 faligndata %f20, %f22, %f18 |
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285 faligndata %f22, %f24, %f20 |
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286 faligndata %f24, %f26, %f22 |
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287 |
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288 .word 0x81b02800 ! MD5 |
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289 |
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290 bne,pt `$bits==64?"%xcc":"%icc"`, .Lhwunaligned_loop |
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291 for %f26, %f26, %f10 ! %f10=%f26 |
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292 |
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293 ba .Lhwfinish |
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294 nop |
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295 |
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296 .align 16 |
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297 .Lsoftware: |
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298 save %sp,-$frame,%sp |
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299 |
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300 rd %asi,$saved_asi |
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301 wr %g0,0x88,%asi ! ASI_PRIMARY_LITTLE |
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302 and $inp,7,$shr |
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303 andn $inp,7,$inp |
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304 |
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305 sll $shr,3,$shr ! *=8 |
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306 mov 56,$shl2 |
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307 ld [$ctx+0],$A |
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308 sub $shl2,$shr,$shl2 |
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309 ld [$ctx+4],$B |
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310 and $shl2,32,$shl1 |
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311 add $shl2,8,$shl2 |
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312 ld [$ctx+8],$C |
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313 sub $shl2,$shl1,$shl2 ! shr+shl1+shl2==64 |
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314 ld [$ctx+12],$D |
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315 nop |
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316 |
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317 .Loop: |
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318 cmp $shr,0 ! was inp aligned? |
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319 ldxa [$inp+0]%asi,@X[0] ! load little-endian input |
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320 ldxa [$inp+8]%asi,@X[1] |
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321 ldxa [$inp+16]%asi,@X[2] |
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322 ldxa [$inp+24]%asi,@X[3] |
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323 ldxa [$inp+32]%asi,@X[4] |
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324 sllx $A,32,$AB ! pack A,B |
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325 ldxa [$inp+40]%asi,@X[5] |
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326 sllx $C,32,$CD ! pack C,D |
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327 ldxa [$inp+48]%asi,@X[6] |
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328 or $B,$AB,$AB |
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329 ldxa [$inp+56]%asi,@X[7] |
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330 or $D,$CD,$CD |
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331 bnz,a,pn %icc,.+8 |
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332 ldxa [$inp+64]%asi,@X[8] |
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333 |
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334 srlx @X[0],$shr,@X[0] ! align X[0] |
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335 sllx @X[1],$shl1,$tx |
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336 sethi %hi(@K[0]),$t2 |
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337 sllx $tx,$shl2,$tx |
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338 or $t2,%lo(@K[0]),$t2 |
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339 or $tx,@X[0],@X[0] |
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340 xor $C,$D,$t1 |
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341 add @X[0],$t2,$t2 ! X[0]+K[0] |
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342 ___ |
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343 for ($i=0;$i<15;$i++) { &R0($i,@V); unshift(@V,pop(@V)); } |
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344 for (;$i<16;$i++) { &R0_1($i,@V); unshift(@V,pop(@V)); } |
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345 for (;$i<32;$i++) { &R1($i,@V); unshift(@V,pop(@V)); } |
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346 for (;$i<48;$i++) { &R2($i,@V); unshift(@V,pop(@V)); } |
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347 for (;$i<64;$i++) { &R3($i,@V); unshift(@V,pop(@V)); } |
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348 $code.=<<___; |
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349 srlx $AB,32,$t1 ! unpack A,B,C,D and accumulate |
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350 add $inp,64,$inp ! advance inp |
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351 srlx $CD,32,$t2 |
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352 add $t1,$A,$A |
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353 subcc $len,1,$len ! done yet? |
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354 add $AB,$B,$B |
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355 add $t2,$C,$C |
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356 add $CD,$D,$D |
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357 srl $B,0,$B ! clruw $B |
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358 bne `$bits==64?"%xcc":"%icc"`,.Loop |
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359 srl $D,0,$D ! clruw $D |
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360 |
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361 st $A,[$ctx+0] ! write out ctx |
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362 st $B,[$ctx+4] |
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363 st $C,[$ctx+8] |
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364 st $D,[$ctx+12] |
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365 |
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366 wr %g0,$saved_asi,%asi |
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367 ret |
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368 restore |
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369 .type md5_block_asm_data_order,#function |
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370 .size md5_block_asm_data_order,(.-md5_block_asm_data_order) |
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371 |
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372 .asciz "MD5 block transform for SPARCv9, CRYPTOGAMS by <appro\@openssl.org>" |
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373 .align 4 |
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374 ___ |
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375 |
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376 # Purpose of these subroutines is to explicitly encode VIS instructions, |
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377 # so that one can compile the module without having to specify VIS |
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378 # extentions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a. |
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379 # Idea is to reserve for option to produce "universal" binary and let |
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380 # programmer detect if current CPU is VIS capable at run-time. |
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381 sub unvis { |
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382 my ($mnemonic,$rs1,$rs2,$rd)=@_; |
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383 my $ref,$opf; |
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384 my %visopf = ( "faligndata" => 0x048, |
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385 "for" => 0x07c ); |
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386 |
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387 $ref = "$mnemonic\t$rs1,$rs2,$rd"; |
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388 |
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389 if ($opf=$visopf{$mnemonic}) { |
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390 foreach ($rs1,$rs2,$rd) { |
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391 return $ref if (!/%f([0-9]{1,2})/); |
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392 $_=$1; |
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393 if ($1>=32) { |
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394 return $ref if ($1&1); |
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395 # re-encode for upper double register addressing |
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396 $_=($1|$1>>5)&31; |
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397 } |
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398 } |
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399 |
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400 return sprintf ".word\t0x%08x !%s", |
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401 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2, |
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402 $ref; |
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403 } else { |
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404 return $ref; |
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405 } |
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406 } |
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407 sub unalignaddr { |
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408 my ($mnemonic,$rs1,$rs2,$rd)=@_; |
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409 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 ); |
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410 my $ref="$mnemonic\t$rs1,$rs2,$rd"; |
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411 |
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412 foreach ($rs1,$rs2,$rd) { |
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413 if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; } |
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414 else { return $ref; } |
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415 } |
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416 return sprintf ".word\t0x%08x !%s", |
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417 0x81b00300|$rd<<25|$rs1<<14|$rs2, |
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418 $ref; |
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419 } |
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420 |
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421 foreach (split("\n",$code)) { |
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422 s/\`([^\`]*)\`/eval $1/ge; |
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423 |
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424 s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/ |
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425 &unvis($1,$2,$3,$4) |
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426 /ge; |
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427 s/\b(alignaddr)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/ |
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428 &unalignaddr($1,$2,$3,$4) |
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429 /ge; |
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430 |
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431 print $_,"\n"; |
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432 } |
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433 |
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434 close STDOUT; |
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