1 Sparc assembler and fixes a bug in JIT. |
|
2 Also some endian patch. |
|
3 |
|
4 --- comm-esr31/mozilla/js/src/assembler/assembler/MacroAssemblerSparc.h.orig 2015-06-04 17:42:51.654203814 -0700 |
|
5 +++ comm-esr31/mozilla/js/src/assembler/assembler/MacroAssemblerSparc.h 2015-06-04 17:42:51.667707756 -0700 |
|
6 @@ -337,6 +337,17 @@ |
|
7 } |
|
8 } |
|
9 |
|
10 + void load16Unaligned(BaseIndex address, RegisterID dest) |
|
11 + { |
|
12 + m_assembler.sll_imm(address.index, address.scale, SparcRegisters::g2); |
|
13 + add32(Imm32(address.offset+1), SparcRegisters::g2); |
|
14 + m_assembler.ldub_r(address.base, SparcRegisters::g2, dest); |
|
15 + m_assembler.subcc_imm(SparcRegisters::g2, 1, SparcRegisters::g2); |
|
16 + m_assembler.ldub_r(address.base, SparcRegisters::g2, SparcRegisters::g3); |
|
17 + m_assembler.sll_imm(SparcRegisters::g3, 8, SparcRegisters::g3); |
|
18 + m_assembler.or_r(SparcRegisters::g3, dest, dest); |
|
19 + } |
|
20 + |
|
21 void store8(RegisterID src, ImplicitAddress address) |
|
22 { |
|
23 if (m_assembler.isimm13(address.offset)) |
|
24 @@ -416,6 +427,11 @@ |
|
25 } |
|
26 } |
|
27 |
|
28 + void load8(BaseIndex address, RegisterID dest) |
|
29 + { |
|
30 + load8ZeroExtend(address, dest); |
|
31 + } |
|
32 + |
|
33 void load8SignExtend(BaseIndex address, RegisterID dest) |
|
34 { |
|
35 m_assembler.sll_imm(address.index, address.scale, SparcRegisters::g2); |
|
36 --- comm-esr31/mozilla/js/src/assembler/assembler/SparcAssembler.h.orig 2015-06-04 17:42:51.659564348 -0700 |
|
37 +++ comm-esr31/mozilla/js/src/assembler/assembler/SparcAssembler.h 2015-06-04 17:42:51.667904536 -0700 |
|
38 @@ -161,6 +161,10 @@ |
|
39 { |
|
40 } |
|
41 |
|
42 + bool isSet() const { |
|
43 + return m_offset != -1; |
|
44 + } |
|
45 + |
|
46 private: |
|
47 JmpSrc(int offset) |
|
48 : m_offset(offset) |
|
49 --- comm-esr31/mozilla/js/src/yarr/YarrJIT.cpp.orig 2015-06-04 17:42:51.665227855 -0700 |
|
50 +++ comm-esr31/mozilla/js/src/yarr/YarrJIT.cpp 2015-06-04 17:42:51.668284205 -0700 |
|
51 @@ -84,6 +84,7 @@ |
|
52 static const RegisterID regT1 = SparcRegisters::i5; |
|
53 |
|
54 static const RegisterID returnRegister = SparcRegisters::i0; |
|
55 + static const RegisterID returnRegister2 = SparcRegisters::i1; |
|
56 #elif WTF_CPU_X86 |
|
57 static const RegisterID input = X86Registers::eax; |
|
58 static const RegisterID index = X86Registers::edx; |
|
59 @@ -824,6 +825,18 @@ |
|
60 ignoreCaseMask |= 32 << shiftAmount; |
|
61 } |
|
62 |
|
63 +#if WTF_CPU_BIG_ENDIAN |
|
64 + if (m_charSize == Char8) { |
|
65 + allCharacters = (allCharacters << 24) | ((allCharacters << 8) & 0xff0000) | |
|
66 + ((allCharacters >> 8) & 0xff00) | ((allCharacters >> 24) & 0xff); |
|
67 + ignoreCaseMask = (ignoreCaseMask << 24) | ((ignoreCaseMask << 8) & 0xff0000) | |
|
68 + ((ignoreCaseMask >> 8) & 0xff00) | ((ignoreCaseMask >> 24) & 0xff); |
|
69 + } else { |
|
70 + allCharacters = (allCharacters << 16) | ((allCharacters >> 16) & 0xffff); |
|
71 + ignoreCaseMask = (ignoreCaseMask << 16) | ((ignoreCaseMask >> 16) & 0xffff); |
|
72 + } |
|
73 +#endif |
|
74 + |
|
75 if (m_charSize == Char8) { |
|
76 switch (numberCharacters) { |
|
77 case 1: |
|