53 |
53 |
54 /* |
54 /* |
55 * We use the extension here to communicate with the driver |
55 * We use the extension here to communicate with the driver |
56 * (for correct debugfs reporting) |
56 * (for correct debugfs reporting) |
57 */ |
57 */ |
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58 |
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59 enum sq_sw_state { |
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60 FLUSH_SQ_IN_PROGRESS = 0, |
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61 FLUSH_SQ_IN_FLIGHT = 1, |
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62 }; |
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63 |
58 typedef struct sif_sq_sw { |
64 typedef struct sif_sq_sw { |
59 struct psif_sq_sw d; /* Hardware visible descriptor */ |
65 struct psif_sq_sw d; /* Hardware visible descriptor */ |
60 /* separate the cache lines */ |
66 /* separate the cache lines */ |
61 __u8 fill[SIF_CACHE_BYTES - sizeof (struct psif_sq_sw)]; |
67 __u8 fill[SIF_CACHE_BYTES - sizeof (struct psif_sq_sw)]; |
62 __u16 last_seq; /* Last used sq seq.num (req. sq->lock) */ |
68 __u16 last_seq; /* Last used sq seq.num (req. sq->lock) */ |
63 /* Last sq seq.number seen in a compl (req. cq->lock) */ |
69 /* Last sq seq.number seen in a compl (req. cq->lock) */ |
64 volatile __u16 head_seq; |
70 volatile __u16 head_seq; |
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71 __u16 trusted_seq; |
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72 __u8 tsl; |
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73 volatile __u64 flags; |
65 }sif_sq_sw_t; |
74 }sif_sq_sw_t; |
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75 |
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76 enum rq_sw_state { |
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77 FLUSH_RQ_IN_PROGRESS = 0, |
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78 FLUSH_RQ_IN_FLIGHT = 1, |
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79 FLUSH_RQ_FIRST_TIME = 2, |
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80 RQ_IS_INVALIDATED = 3, |
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81 }; |
66 |
82 |
67 typedef struct sif_rq_sw { |
83 typedef struct sif_rq_sw { |
68 struct psif_rq_sw d; /* Hardware visible descriptor */ |
84 struct psif_rq_sw d; /* Hardware visible descriptor */ |
69 /* separate the cache lines */ |
85 /* separate the cache lines */ |
70 __u8 fill[SIF_CACHE_BYTES - sizeof (struct psif_rq_sw)]; |
86 __u8 fill[SIF_CACHE_BYTES - sizeof (struct psif_rq_sw)]; |
71 /* current length of queue as #posted - #completed */ |
87 /* current length of queue as #posted - #completed */ |
72 volatile uint32_t length; |
88 volatile uint32_t length; |
73 __u32 next_seq; /* First unused sequence number */ |
89 __u32 next_seq; /* First unused sequence number */ |
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90 volatile __u64 flags; |
74 }sif_rq_sw_t; |
91 }sif_rq_sw_t; |
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92 |
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93 enum cq_sw_state { |
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94 CQ_POLLING_NOT_ALLOWED = 0, |
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95 CQ_POLLING_IGNORED_SEQ = 1, |
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96 FLUSH_SQ_FIRST_TIME = 2, |
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97 }; |
75 |
98 |
76 typedef struct sif_cq_sw { |
99 typedef struct sif_cq_sw { |
77 struct psif_cq_sw d; /* Hardware visible descriptor */ |
100 struct psif_cq_sw d; /* Hardware visible descriptor */ |
78 /* separate the cache lines */ |
101 /* separate the cache lines */ |
79 __u8 fill[SIF_CACHE_BYTES - sizeof (struct psif_cq_sw)]; |
102 __u8 fill[SIF_CACHE_BYTES - sizeof (struct psif_cq_sw)]; |