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1 /* |
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2 * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved. |
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3 */ |
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4 |
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5 /* |
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6 * Redistribution and use in source and binary forms, with or without modification, |
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7 * are permitted provided that the following conditions are met: |
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8 * |
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9 * 1. Redistributions of source code must retain the above copyright notice, |
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10 * this list of conditions and the following disclaimer. |
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11 * |
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12 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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13 * this list of conditions and the following disclaimer in the documentation |
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14 * and/or other materials provided with the distribution. |
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15 * |
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16 * 3. Neither the name of the copyright holder nor the names of its contributors |
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17 * may be used to endorse or promote products derived from this software without |
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18 * specific prior written permission. |
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19 * |
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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23 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
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24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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27 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
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28 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
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29 * OF THE POSSIBILITY OF SUCH DAMAGE. |
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30 */ |
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31 |
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32 #ifndef _PSIF_HW_DATA_H |
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33 #define _PSIF_HW_DATA_H |
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34 |
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35 #ifdef __cplusplus |
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36 extern "C" { |
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37 #endif |
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38 |
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39 #include "psif_api.h" |
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40 |
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41 #define psif_port_flags psif_event |
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42 #define string_enum_psif_port_flags(data) string_enum_psif_event((enum psif_event)data) |
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43 #include "psif_endian.h" |
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44 #if !defined(__KERNEL__) |
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45 #include "os_header.h" |
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46 #endif |
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47 |
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48 /* Extent of all psif enums */ |
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49 enum psif_enum_extent { |
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50 PSIF_MMU_TRANSLATION_EXTENT = 0x8, |
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51 PSIF_PAGE_SIZE_EXTENT = 0xf, |
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52 PSIF_WR_TYPE_EXTENT = 0x8f, |
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53 PSIF_PORT_EXTENT = 0x2, |
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54 PSIF_USE_AH_EXTENT = 0x2, |
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55 PSIF_TSU_QOS_EXTENT = 0x2, |
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56 PSIF_WC_OPCODE_EXTENT = 0x83, |
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57 PSIF_WC_STATUS_EXTENT = 0x16, |
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58 PSIF_TSL_QP_WR_EXTENT = 0x10, |
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59 PSIF_TABLE_LEVEL_EXTENT = 0x6, |
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60 IB_OPCODE_EXTENT = 0xca, |
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61 PSIF_RB_TYPE_EXTENT = 0x7, |
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62 PSIF_EPS_A_CORE_EXTENT = 0x4, |
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63 PSIF_QP_STATE_EXTENT = 0x8, |
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64 PSIF_CMPL_OUTSTANDING_ERROR_EXTENT = 0xa, |
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65 PSIF_EXPECTED_OP_EXTENT = 0x4, |
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66 PSIF_MIGRATION_EXTENT = 0x4, |
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67 PSIF_QP_TRANS_EXTENT = 0x8, |
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68 PSIF_BOOL_EXTENT = 0x2, |
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69 PSIF_EOIB_TYPE_EXTENT = 0x4, |
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70 PSIF_COMM_LIVE_EXTENT = 0x2, |
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71 PSIF_PATH_MTU_EXTENT = 0x8, |
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72 PSIF_USE_GRH_EXTENT = 0x2, |
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73 PSIF_LOOPBACK_EXTENT = 0x2, |
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74 PSIF_PORT_SPEED_EXTENT = 0x21, |
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75 PSIF_PCIE_WR_OFFS_EXTENT = 0x1000, |
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76 PSIF_QP_COMMAND_EXTENT = 0x4, |
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77 PSIF_SIBS_MBOX_TYPE_EXTENT = 0x2, |
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78 PSIF_MBOX_TYPE_EXTENT = 0x6, |
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79 PSIF_DMA_VT_KEY_STATES_EXTENT = 0x4, |
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80 PSIF_FLASH_IMAGE_TYPE_EXTENT = 0x5, |
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81 PSIF_EVENT_EXTENT = 0x11, |
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82 PSIF_TSU_ERROR_TYPES_EXTENT = 0x8c, |
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83 PSIF_EPS_CORE_ID_EXTENT = 0x5, |
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84 PSIF_EPSC_LOG_MODE_EXTENT = 0x11, |
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85 PSIF_EPSC_LOG_LEVEL_EXTENT = 0x8, |
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86 PSIF_EPSC_PORT_STATE_EXTENT = 0x6, |
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87 PSIF_EPSC_PATH_MTU_EXTENT = 0x8, |
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88 PSIF_EPSC_MONITOR_EXTENT = 0x5, |
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89 PSIF_EPSC_INTERRUPT_SOURCE_EXTENT = 0x15, |
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90 PSIF_EPSC_INTERRUPT_PRI_EXTENT = 0x4, |
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91 PSIF_EPSC_ATOMIC_CAP_EXTENT = 0x3, |
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92 PSIF_EPSC_CSR_STATUS_EXTENT = 0x100, |
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93 PSIF_EPSC_CSR_OPCODE_EXTENT = 0x4f, |
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94 PSIF_EPSC_CSR_FLAGS_EXTENT = 0x5, |
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95 PSIF_VLINK_STATE_EXTENT = 0x11, |
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96 PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_EXTENT = 0x3, |
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97 PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_EXTENT = 0x11, |
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98 PSIF_EPSC_CSR_EPSA_COMMAND_EXTENT = 0x4, |
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99 PSIF_EPSA_COMMAND_EXTENT = 0xc, |
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100 PSIF_EPSC_QUERY_OP_EXTENT = 0x50, |
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101 PSIF_EPSC_CSR_UPDATE_OPCODE_EXTENT = 0x8, |
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102 PSIF_EPSC_FLASH_SLOT_EXTENT = 0x6, |
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103 PSIF_EPSC_UPDATE_SET_EXTENT = 0x5, |
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104 PSIF_EPSC_CSR_UF_CTRL_OPCODE_EXTENT = 0x9, |
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105 PSIF_EPSC_VIMMA_CTRL_OPCODE_EXTENT = 0x8, |
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106 PSIF_EPSC_VIMMA_ADMMODE_EXTENT = 0x2, |
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107 PSIF_EPSC_CSR_PMA_COUNTERS_ENUM_EXTENT = 0x17, |
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108 PSIF_EPSC_CSR_ATOMIC_OP_EXTENT = 0x4, |
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109 PSIF_CQ_STATE_EXTENT = 0x4, |
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110 PSIF_RSS_HASH_SOURCE_EXTENT = 0x2 |
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111 }; /* enum psif_enum_extent [16 bits] */ |
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112 |
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113 /* MMU operation modes. */ |
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114 enum psif_mmu_translation { |
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115 MMU_PASS_THROUGH0, |
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116 MMU_PASS_THROUGH_PAD, |
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117 MMU_GVA2GPA_MODE, |
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118 MMU_GVA2GPA_MODE_PAD, |
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119 MMU_PRETRANSLATED, |
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120 MMU_PRETRANSLATED_PAD, |
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121 MMU_EPSA_MODE, |
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122 MMU_EPSC_MODE |
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123 }; /* enum psif_mmu_translation [ 3 bits] */ |
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124 |
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125 /* |
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126 * Enumeration for the different supported page sizes. XXX: Define the page |
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127 * sizes |
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128 */ |
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129 enum psif_page_size { |
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130 PAGE_SIZE_IA32E_4KB = 0, |
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131 PAGE_SIZE_IA32E_2MB = 0x1, |
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132 PAGE_SIZE_IA32E_1GB = 0x2, |
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133 PAGE_SIZE_S64_8KB = 0x8, |
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134 PAGE_SIZE_S64_64KB = 0x9, |
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135 PAGE_SIZE_S64_512KB = 0xa, |
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136 PAGE_SIZE_S64_4MB = 0xb, |
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137 PAGE_SIZE_S64_32MB = 0xc, |
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138 PAGE_SIZE_S64_2GB = 0xd, |
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139 PAGE_SIZE_S64_16GB = 0xe |
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140 }; /* enum psif_page_size [ 4 bits] */ |
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141 |
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142 /* |
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143 * These are the different work request opcodes supported by PSIF. |
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144 * PSIF_WR_ENTER_SQ_MODE and PSIF_WR_CANCEL_CMD are special opcodes only used |
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145 * when writing to a special offset of the VCBs. RQS must check that the |
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146 * PSIF_WR_SEND_EPS and PSIF_WR_SEND_EPS_DR really comes from the EPS. CBU |
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147 * must report the source of a WR to RQS. |
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148 */ |
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149 enum psif_wr_type { |
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150 PSIF_WR_SEND, |
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151 PSIF_WR_SEND_IMM, |
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152 PSIF_WR_SPECIAL_QP_SEND, |
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153 PSIF_WR_QP0_SEND_DR_XMIT, |
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154 PSIF_WR_QP0_SEND_DR_LOOPBACK, |
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155 PSIF_WR_EPS_SPECIAL_QP_SEND, |
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156 PSIF_WR_EPS_QP0_SEND_DR_XMIT, |
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157 PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK, |
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158 PSIF_WR_RDMA_WR, |
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159 PSIF_WR_RDMA_WR_IMM, |
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160 PSIF_WR_RDMA_RD, |
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161 PSIF_WR_CMP_SWAP, |
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162 PSIF_WR_FETCH_ADD, |
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163 PSIF_WR_MASK_CMP_SWAP, |
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164 PSIF_WR_MASK_FETCH_ADD, |
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165 PSIF_WR_LSO, |
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166 PSIF_WR_INVALIDATE_RKEY = 0x80, |
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167 PSIF_WR_INVALIDATE_LKEY, |
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168 PSIF_WR_INVALIDATE_BOTH_KEYS, |
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169 PSIF_WR_INVALIDATE_TLB, |
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170 PSIF_WR_RESIZE_CQ, |
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171 PSIF_WR_SET_SRQ_LIM, |
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172 PSIF_WR_SET_XRCSRQ_LIM, |
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173 PSIF_WR_REQ_CMPL_NOTIFY, |
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174 PSIF_WR_CMPL_NOTIFY_RCVD, |
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175 PSIF_WR_REARM_CMPL_EVENT, |
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176 PSIF_WR_GENERATE_COMPLETION, |
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177 PSIF_WR_INVALIDATE_RQ, |
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178 PSIF_WR_INVALIDATE_CQ, |
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179 PSIF_WR_INVALIDATE_XRCSRQ, |
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180 PSIF_WR_INVALIDATE_SGL_CACHE |
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181 }; /* enum psif_wr_type [ 8 bits] */ |
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182 |
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183 /* Port number the IB packet is transimitted on. */ |
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184 enum psif_port { |
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185 PORT_1 = 0, |
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186 PORT_2 = 0x1 |
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187 }; /* enum psif_port [ 1 bits] */ |
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188 |
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189 /* |
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190 * Enumeration for using AHA or not. When set, AHA should be used instead of |
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191 * information from the QP state in appropriate places. |
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192 */ |
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193 enum psif_use_ah { |
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194 NO_AHA = 0, |
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195 USE_AHA = 0x1 |
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196 }; /* enum psif_use_ah [ 1 bits] */ |
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197 |
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198 /* |
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199 * Indicating if this QP is configured as a high bandwidth or a low latency |
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200 * QP. |
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201 */ |
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202 enum psif_tsu_qos { |
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203 QOSL_HIGH_BANDWIDTH = 0, |
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204 QOSL_LOW_LATENCY = 0x1 |
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205 }; /* enum psif_tsu_qos [ 1 bits] */ |
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206 |
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207 /* |
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208 * Completion entry opcode indicating what type of request this completion |
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209 * entry is completed. |
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210 */ |
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211 enum psif_wc_opcode { |
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212 PSIF_WC_OPCODE_SEND = 0, |
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213 PSIF_WC_OPCODE_RDMA_WR = 0x1, |
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214 PSIF_WC_OPCODE_RDMA_READ = 0x2, |
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215 PSIF_WC_OPCODE_CMP_SWAP = 0x3, |
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216 PSIF_WC_OPCODE_FETCH_ADD = 0x4, |
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217 PSIF_WC_OPCODE_LSO = 0x6, |
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218 PSIF_WC_OPCODE_MASKED_CMP_SWAP = 0x9, |
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219 PSIF_WC_OPCODE_MASKED_FETCH_ADD, |
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220 PSIF_WC_OPCODE_INVALIDATE_RKEY = 0x40, |
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221 PSIF_WC_OPCODE_INVALIDATE_LKEY, |
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222 PSIF_WC_OPCODE_INVALIDATE_BOTH_KEYS, |
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223 PSIF_WC_OPCODE_INVALIDATE_TLB, |
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224 PSIF_WC_OPCODE_RESIZE_CQ, |
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225 PSIF_WC_OPCODE_SET_SRQ_LIM, |
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226 PSIF_WC_OPCODE_SET_XRCSRQ_LIM, |
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227 PSIF_WC_OPCODE_REQ_CMPL_NOTIFY, |
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228 PSIF_WC_OPCODE_CMPL_NOTIFY_RCVD, |
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229 PSIF_WC_OPCODE_REARM_CMPL_EVENT, |
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230 PSIF_WC_OPCODE_GENERATE_COMPLETION, |
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231 PSIF_WC_OPCODE_INVALIDATE_RQ, |
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232 PSIF_WC_OPCODE_INVALIDATE_CQ, |
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233 PSIF_WC_OPCODE_INVALIDATE_RB, |
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234 PSIF_WC_OPCODE_INVALIDATE_XRCSRQ, |
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235 PSIF_WC_OPCODE_INVALIDATE_SGL_CACHE, |
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236 PSIF_WC_OPCODE_RECEIVE_SEND = 0x80, |
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237 PSIF_WC_OPCODE_RECEIVE_RDMA_WR_IMM, |
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238 PSIF_WC_OPCODE_RECEIVE_CONDITIONAL_WR_IMM |
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239 }; /* enum psif_wc_opcode [ 8 bits] */ |
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240 |
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241 /* Completion status for this completion. */ |
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242 enum psif_wc_status { |
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243 PSIF_WC_STATUS_SUCCESS, |
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244 PSIF_WC_STATUS_LOC_LEN_ERR, |
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245 PSIF_WC_STATUS_LOC_QP_OP_ERR, |
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246 PSIF_WC_STATUS_LOC_EEC_OP_ERR, |
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247 PSIF_WC_STATUS_LOC_PROT_ERR, |
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248 PSIF_WC_STATUS_WR_FLUSH_ERR, |
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249 PSIF_WC_STATUS_MW_BIND_ERR, |
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250 PSIF_WC_STATUS_BAD_RESP_ERR, |
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251 PSIF_WC_STATUS_LOC_ACCESS_ERR, |
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252 PSIF_WC_STATUS_REM_INV_REQ_ERR, |
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253 PSIF_WC_STATUS_REM_ACCESS_ERR, |
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254 PSIF_WC_STATUS_REM_OP_ERR, |
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255 PSIF_WC_STATUS_RETRY_EXC_ERR, |
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256 PSIF_WC_STATUS_RNR_RETRY_EXC_ERR, |
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257 PSIF_WC_STATUS_LOC_RDD_VIOL_ERR, |
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258 PSIF_WC_STATUS_REM_INV_RD_REQ_ERR, |
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259 PSIF_WC_STATUS_REM_ABORT_ERR, |
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260 PSIF_WC_STATUS_INV_EECN_ERR, |
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261 PSIF_WC_STATUS_INV_EEC_STATE_ERR, |
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262 PSIF_WC_STATUS_FATAL_ERR, |
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263 PSIF_WC_STATUS_RESP_TIMEOUT_ERR, |
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264 PSIF_WC_STATUS_GENERAL_ERR, |
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265 /* Padding out to required bits allocated */ |
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266 PSIF_WC_STATUS_FIELD_MAX = 0xff |
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267 }; /* enum psif_wc_status [ 8 bits] */ |
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268 |
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269 /* TSU Service level required in the QP and WR */ |
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270 enum psif_tsl_qp_wr { |
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271 /* Dataplane traffic separated in 4 TSLs */ |
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272 TSL_DATA, |
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273 TSL_DATA_1, |
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274 TSL_DATA_2, |
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275 TSL_DATA_3, |
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276 /* TSL for privelidge QP */ |
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277 TSL_PRIV = 0xe, |
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278 /* Strapped down TSL for testing */ |
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279 TSL_JUNK = 0xf |
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280 }; /* enum psif_tsl_qp_wr [ 4 bits] */ |
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281 |
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282 /* MMU table level definition |
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283 * If page level is not applicable it should be set to PAGE_LEVEL0 |
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284 * Values beyond PAGE_LEVEL4 (5-7) are reserved by HW |
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285 */ |
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286 enum psif_table_level { |
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287 /* */ |
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288 PAGE_LEVEL0 = 0, |
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289 PAGE_LEVEL1, |
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290 PAGE_LEVEL2, |
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291 PAGE_LEVEL3, |
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292 /* PAGE_LEVEL4 is SPARC only ? */ |
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293 PAGE_LEVEL4, |
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294 PAGE_LEVEL_RESERVED |
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295 }; /* enum psif_table_level [ 3 bits] */ |
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296 |
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297 |
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298 enum ib_opcode { |
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299 RC_SEND_First = 0, |
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300 RC_SEND_Middle = 0x1, |
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301 RC_SEND_Last = 0x2, |
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302 RC_SEND_Last_Imm = 0x3, |
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303 RC_SEND_Only = 0x4, |
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304 RC_SEND_Only_Imm = 0x5, |
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305 RC_RDMA_WR_First = 0x6, |
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306 RC_RDMA_WR_Middle = 0x7, |
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307 RC_RDMA_WR_Last = 0x8, |
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308 RC_RDMA_WR_Last_Imm = 0x9, |
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309 RC_RDMA_WR_Only = 0xa, |
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310 RC_RDMA_WR_Only_Imm = 0xb, |
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311 RC_RDMA_RD_Req = 0xc, |
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312 RC_RDMA_RD_Resp_First = 0xd, |
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313 RC_RDMA_RD_Resp_Middle = 0xe, |
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314 RC_RDMA_RD_Resp_Last = 0xf, |
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315 RC_RDMA_RD_Resp_Only = 0x10, |
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316 RC_ACK = 0x11, |
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317 RC_Atomic_ACK = 0x12, |
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318 RC_CmpSwap = 0x13, |
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319 RC_FetchAdd = 0x14, |
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320 RC_Reserved = 0x15, |
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321 RC_SEND_Last_Invalid = 0x16, |
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322 RC_SEND_Only_Invalid = 0x17, |
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323 RC_MaskCmpSwap = 0x18, |
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324 RC_MaskFetchAdd = 0x19, |
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325 UC_SEND_First = 0x20, |
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326 UC_SEND_Middle = 0x21, |
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327 UC_SEND_Last = 0x22, |
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328 UC_SEND_Last_Imm = 0x23, |
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329 UC_SEND_Only = 0x24, |
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330 UC_SEND_Only_Imm = 0x25, |
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331 UC_RDMA_WR_First = 0x26, |
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332 UC_RDMA_WR_Middle = 0x27, |
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333 UC_RDMA_WR_Last = 0x28, |
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334 UC_RDMA_WR_Last_Imm = 0x29, |
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335 UC_RDMA_WR_Only = 0x2a, |
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336 UC_RDMA_WR_Only_Imm = 0x2b, |
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337 RD_SEND_First = 0x40, |
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338 RD_SEND_Middle = 0x41, |
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339 RD_SEND_Last = 0x42, |
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340 RD_SEND_Last_Imm = 0x43, |
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341 RD_SEND_Only = 0x44, |
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342 RD_SEND_Only_Imm = 0x45, |
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343 RD_RDMA_WR_First = 0x46, |
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344 RD_RDMA_WR_Middle = 0x47, |
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345 RD_RDMA_WR_Last = 0x48, |
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346 RD_RDMA_WR_Last_Imm = 0x49, |
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347 RD_RDMA_WR_Only = 0x4a, |
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348 RD_RDMA_WR_Only_Imm = 0x4b, |
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349 RD_RDMA_RD_Req = 0x4c, |
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350 RD_RDMA_RD_Resp_First = 0x4d, |
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351 RD_RDMA_RD_Resp_Middle = 0x4e, |
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352 RD_RDMA_RD_Resp_Last = 0x4f, |
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353 RD_RDMA_RD_Resp_Only = 0x50, |
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354 RD_ACK = 0x51, |
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355 RD_Atomic_ACK = 0x52, |
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356 RD_CmpSwap = 0x53, |
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357 RD_FetchAdd = 0x54, |
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358 RD_RESYNC = 0x55, |
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359 UD_SEND_Only = 0x64, |
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360 UD_SEND_Only_Imm = 0x65, |
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361 CNP = 0x80, |
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362 XRC_SEND_First = 0xa0, |
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363 XRC_SEND_Middle = 0xa1, |
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364 XRC_SEND_Last = 0xa2, |
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365 XRC_SEND_Last_Imm = 0xa3, |
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366 XRC_SEND_Only = 0xa4, |
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367 XRC_SEND_Only_Imm = 0xa5, |
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368 XRC_RDMA_WR_First = 0xa6, |
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369 XRC_RDMA_WR_Middle = 0xa7, |
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370 XRC_RDMA_WR_Last = 0xa8, |
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371 XRC_RDMA_WR_Last_Imm = 0xa9, |
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372 XRC_RDMA_WR_Only = 0xaa, |
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373 XRC_RDMA_WR_Only_Imm = 0xab, |
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374 XRC_RDMA_RD_Req = 0xac, |
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375 XRC_RDMA_RD_Resp_First = 0xad, |
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376 XRC_RDMA_RD_Resp_Middle = 0xae, |
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377 XRC_RDMA_RD_Resp_Last = 0xaf, |
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378 XRC_RDMA_RD_Resp_Only = 0xb0, |
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379 XRC_ACK = 0xb1, |
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380 XRC_Atomic_ACK = 0xb2, |
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381 XRC_CmpSwap = 0xb3, |
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382 XRC_FetchAdd = 0xb4, |
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383 XRC_Reserved = 0xb5, |
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384 XRC_SEND_Last_Invalid = 0xb6, |
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385 XRC_SEND_Only_Invalid = 0xb7, |
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386 XRC_MaskCmpSwap = 0xb8, |
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387 XRC_MaskFetchAdd = 0xb9, |
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388 MANSP1_INVALID = 0xc0, |
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389 MANSP1_HOST_READ = 0xc1, |
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390 MANSP1_HOST_WRITE = 0xc2, |
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391 MANSP1_HOST_READ_NO_DMAVT = 0xc3, |
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392 MANSP1_HOST_WRITE_NO_DMAVT = 0xc4, |
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393 MANSP1_INTERNAL_TYPE = 0xc5, |
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394 MANSP1_INTERNAL_TYPE_MMU_BYPASS = 0xc6, |
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395 MANSP1_HOST_CMP_SWAP = 0xc7, |
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396 MANSP1_DR_LOOPBACK = 0xc8, |
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397 MANSP1_ARP_LOOPBACK = 0xc9 |
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398 }; /* enum ib_opcode [ 8 bits] */ |
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399 |
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400 /* |
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401 * This is a ring buffer type defining the type of transaction this |
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402 * represents. |
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403 */ |
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404 enum psif_rb_type { |
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405 PSIF_RB_TYPE_INVALID, |
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406 PSIF_RB_TYPE_DM_PUT, |
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407 PSIF_RB_TYPE_DM_GET_RESP, |
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408 PSIF_RB_TYPE_RCV_PROXY_COMPLETION, |
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409 PSIF_RB_TYPE_RCV_PROXY_COMPLETION_AND_DATA, |
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410 PSIF_RB_TYPE_SEND_PROXY_COMPLETION, |
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411 PSIF_RB_TYPE_SEND_COMPLETION |
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412 }; /* enum psif_rb_type [ 3 bits] */ |
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413 |
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414 /* |
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415 * Core number for EPS-A.1 PSIF_EPS_A_1 PSIF_EPS_A_2 PSIF_EPS_A_3 |
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416 * PSIF_EPS_A_4 |
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417 */ |
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418 enum psif_eps_a_core { |
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419 PSIF_EPS_A_1, |
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420 PSIF_EPS_A_2, |
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421 PSIF_EPS_A_3, |
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422 PSIF_EPS_A_4 |
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423 }; /* enum psif_eps_a_core [ 2 bits] */ |
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424 |
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425 /* This is the state this QP is in. */ |
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426 enum psif_qp_state { |
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427 PSIF_QP_STATE_RESET = 0, |
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428 PSIF_QP_STATE_INIT = 0x1, |
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429 PSIF_QP_STATE_RTR = 0x2, |
|
430 PSIF_QP_STATE_RTS = 0x3, |
|
431 PSIF_QP_STATE_SQERR = 0x5, |
|
432 PSIF_QP_STATE_ERROR = 0x6, |
|
433 PSIF_QP_STATE_INVALID = 0x7 |
|
434 }; /* enum psif_qp_state [ 3 bits] */ |
|
435 |
|
436 /* |
|
437 * CMPL_NO_ERROR CMPL_RQS_INVALID_REQUEST_ERR CMPL_RQS_QP_IN_WRONG_STATE_ERR |
|
438 * CMPL_RQS_MAX_OUTSTANDING_REACHED_ERR CMPL_RQS_REQUEST_FENCED_ERR |
|
439 * CMPL_RQS_CMD_FROM_EPS_ERR CMPL_DMA_SGL_RD_ERR CMPL_DMA_PYLD_RD_ERR |
|
440 * CMPL_DMA_SGL_LENGTH_ERR CMPL_DMA_LKEY_ERR |
|
441 */ |
|
442 enum psif_cmpl_outstanding_error { |
|
443 CMPL_NO_ERROR, |
|
444 CMPL_RQS_INVALID_REQUEST_ERR, |
|
445 CMPL_RQS_QP_IN_WRONG_STATE_ERR, |
|
446 CMPL_RQS_MAX_OUTSTANDING_REACHED_ERR, |
|
447 CMPL_RQS_REQUEST_FENCED_ERR, |
|
448 CMPL_RQS_CMD_FROM_EPS_ERR, |
|
449 CMPL_DMA_SGL_RD_ERR, |
|
450 CMPL_DMA_PYLD_RD_ERR, |
|
451 CMPL_DMA_SGL_LENGTH_ERR, |
|
452 CMPL_DMA_LKEY_ERR |
|
453 }; /* enum psif_cmpl_outstanding_error [ 4 bits] */ |
|
454 |
|
455 /* |
|
456 * 2 bits (next_opcode) 0x0: No operation in progress 0x1: Expect SEND middle |
|
457 * or last 0x2: Expect RDMA_WR middle or last 0x3: Expect DM_PUT middle or |
|
458 * last |
|
459 */ |
|
460 enum psif_expected_op { |
|
461 NO_OPERATION_IN_PROGRESS = 0, |
|
462 EXPECT_SEND_MIDDLE_LAST = 0x1, |
|
463 EXPECT_RDMA_WR_MIDDLE_LAST = 0x2, |
|
464 EXPECT_DM_PUT_MIDDLE_LAST = 0x3 |
|
465 }; /* enum psif_expected_op [ 2 bits] */ |
|
466 |
|
467 /* |
|
468 * Migration state (migrated, re-arm and armed). XXX: Assign values to the |
|
469 * states. |
|
470 */ |
|
471 enum psif_migration { |
|
472 APM_OFF, |
|
473 APM_MIGRATED, |
|
474 APM_REARM, |
|
475 APM_ARMED |
|
476 }; /* enum psif_migration [ 2 bits] */ |
|
477 |
|
478 /* |
|
479 * 3 bits (transport) 0x0: RC - Reliable connection. 0x1: UC - Unreliable |
|
480 * connection. 0x2: RD - Reliable datagram - not supported. 0x3: UD - |
|
481 * Unreliable datagram. 0x4: RSVD1 0x5: XRC - Extended reliable connection. |
|
482 * 0x6: MANSP1 - manufacturer specific opcodes. 0x7: MANSP2 - manufacturer |
|
483 * specific opcodes. |
|
484 */ |
|
485 enum psif_qp_trans { |
|
486 PSIF_QP_TRANSPORT_RC = 0, |
|
487 PSIF_QP_TRANSPORT_UC = 0x1, |
|
488 PSIF_QP_TRANSPORT_RD = 0x2, |
|
489 PSIF_QP_TRANSPORT_UD = 0x3, |
|
490 PSIF_QP_TRANSPORT_RSVD1 = 0x4, |
|
491 PSIF_QP_TRANSPORT_XRC = 0x5, |
|
492 PSIF_QP_TRANSPORT_MANSP1 = 0x6, |
|
493 PSIF_QP_TRANSPORT_MANSP2 = 0x7 |
|
494 }; /* enum psif_qp_trans [ 3 bits] */ |
|
495 |
|
496 |
|
497 enum psif_bool { |
|
498 FALSE = 0, |
|
499 TRUE = 0x1 |
|
500 }; /* enum psif_bool [ 1 bits] */ |
|
501 |
|
502 /* |
|
503 * EoIB types enumerated type having these enumerations: EOIB_FULL, |
|
504 * EOIB_PARTIAL, EOIB_QKEY_ONLY, EOIB_NONE. |
|
505 */ |
|
506 enum psif_eoib_type { |
|
507 EOIB_FULL, |
|
508 EOIB_PARTIAL, |
|
509 EOIB_QKEY_ONLY, |
|
510 EOIB_NONE |
|
511 }; /* enum psif_eoib_type [ 2 bits] */ |
|
512 |
|
513 /* |
|
514 * Communication established state. This gets set when a packet is received |
|
515 * error free when in RTR state. |
|
516 */ |
|
517 enum psif_comm_live { |
|
518 NO_COMM_ESTABLISHED = 0, |
|
519 COMM_ESTABLISHED = 0x1 |
|
520 }; /* enum psif_comm_live [ 1 bits] */ |
|
521 |
|
522 /* Definitions for the different supported MTU sizes. */ |
|
523 enum psif_path_mtu { |
|
524 MTU_INVALID = 0, |
|
525 MTU_256B = 0x1, |
|
526 MTU_512B = 0x2, |
|
527 MTU_1024B = 0x3, |
|
528 MTU_2048B = 0x4, |
|
529 MTU_4096B = 0x5, |
|
530 MTU_10240B = 0x6, |
|
531 MTU_XXX = 0x7 |
|
532 }; /* enum psif_path_mtu [ 3 bits] */ |
|
533 |
|
534 /* Enumeration for using GRH or not. When set GRH should be used. */ |
|
535 enum psif_use_grh { |
|
536 NO_GRH = 0, |
|
537 USE_GRH = 0x1 |
|
538 }; /* enum psif_use_grh [ 1 bits] */ |
|
539 |
|
540 /* Enumeration for loopback indication NO_LOOPBACK = 0 LOOPBACK = 1. */ |
|
541 enum psif_loopback { |
|
542 NO_LOOPBACK = 0, |
|
543 LOOPBACK = 0x1 |
|
544 }; /* enum psif_loopback [ 1 bits] */ |
|
545 |
|
546 /* |
|
547 * Should match definitions in ib_verbs.h |
|
548 */ |
|
549 enum psif_port_speed { |
|
550 PSIF_SPEED_SDR = 0x1, |
|
551 PSIF_SPEED_DDR = 0x2, |
|
552 PSIF_SPEED_QDR = 0x4, |
|
553 PSIF_SPEED_FDR10 = 0x8, |
|
554 PSIF_SPEED_FDR = 0x10, |
|
555 PSIF_SPEED_EDR = 0x20, |
|
556 /* Padding out to required bits allocated */ |
|
557 PSIF_PORT_SPEED_FIELD_MAX = 0xff |
|
558 }; /* enum psif_port_speed [ 8 bits] */ |
|
559 |
|
560 /* Depricated data type... */ |
|
561 enum psif_pcie_wr_offs { |
|
562 WR_CB_START_OFFS = 0, |
|
563 WR_CB_LAST_OFFS = 0x140, |
|
564 WR_SQS_DOORBELL_OFFS = 0xfc0, |
|
565 WR_CB_CLEAR_OFFS = 0xff8, |
|
566 WR_MAX_BAR_OFFS = 0xfff |
|
567 }; /* enum psif_pcie_wr_offs [12 bits] */ |
|
568 |
|
569 /* Commands used for modify/query QP. */ |
|
570 enum psif_qp_command { |
|
571 QP_CMD_INVALID = 0, |
|
572 QP_CMD_MODIFY = 0x1, |
|
573 QP_CMD_QUERY = 0x2, |
|
574 QP_CMD_CHECK_TIMEOUT = 0x3 |
|
575 }; /* enum psif_qp_command [ 2 bits] */ |
|
576 |
|
577 |
|
578 enum psif_sibs_mbox_type { |
|
579 SIBS_MBOX_EPSC, |
|
580 SIBS_MBOX_EPS_MAX, |
|
581 /* Padding out to required bits allocated */ |
|
582 PSIF_SIBS_MBOX_TYPE_FIELD_MAX = 0xff |
|
583 }; /* enum psif_sibs_mbox_type [ 8 bits] */ |
|
584 |
|
585 |
|
586 enum psif_mbox_type { |
|
587 MBOX_EPSA0, |
|
588 MBOX_EPSA1, |
|
589 MBOX_EPSA2, |
|
590 MBOX_EPSA3, |
|
591 MBOX_EPSC, |
|
592 MBOX_EPS_MAX, |
|
593 /* Padding out to required bits allocated */ |
|
594 PSIF_MBOX_TYPE_FIELD_MAX = 0xff |
|
595 }; /* enum psif_mbox_type [ 8 bits] */ |
|
596 |
|
597 /* |
|
598 * DMA Validation Key states. The valid states are: PSIF_DMA_KEY_INVALID=0 |
|
599 * PSIF_DMA_KEY_FREE = 1 PSIF_DMA_KEY_VALID = 2 PSIF_DMA_KEY_MMU_VALID |
|
600 */ |
|
601 enum psif_dma_vt_key_states { |
|
602 PSIF_DMA_KEY_INVALID = 0, |
|
603 PSIF_DMA_KEY_FREE = 0x1, |
|
604 PSIF_DMA_KEY_VALID = 0x2, |
|
605 PSIF_DMA_KEY_MMU_VALID = 0x3 |
|
606 }; /* enum psif_dma_vt_key_states [ 2 bits] */ |
|
607 |
|
608 /** |
|
609 * Flash image types. More comming... |
|
610 */ |
|
611 enum psif_flash_image_type { |
|
612 PSIF_IMAGE_INVALID = 0, |
|
613 PSIF_IMAGE_BOOT_LOADER = 0x1, |
|
614 PSIF_IMAGE_EPS_C_APPLICATION = 0x2, |
|
615 PSIF_IMAGE_EPS_A_APPLICATION = 0x3, |
|
616 PSIF_IMAGE_DIAGNOSTICS = 0x4, |
|
617 /* Padding out to required bits allocated */ |
|
618 PSIF_FLASH_IMAGE_TYPE_FIELD_MAX = 0x7fffffff |
|
619 }; /* enum psif_flash_image_type [32 bits] */ |
|
620 |
|
621 /** \brief SW EQ event type |
|
622 * \details |
|
623 * Software events use `eq_entry::port_flags` for the event type. As this is |
|
624 * limited to 4 bits the special value `PSIF_EVENT_EXTENSION` is used to |
|
625 * indicate that the actual event type is to be found in |
|
626 * `eq_entry::extension_type`. This is done for all enum values larger than |
|
627 * 4 bits. |
|
628 * |
|
629 * \par Width |
|
630 * 32 bit |
|
631 * \par Used in |
|
632 * struct psif_eq_entry |
|
633 * \par Restrictions |
|
634 * none (all UF) |
|
635 * \par Classification |
|
636 * driver |
|
637 */ |
|
638 enum psif_event { |
|
639 /** Event without a reason... */ |
|
640 PSIF_EVENT_NO_CHANGE = 0, |
|
641 /** GID table have been updated */ |
|
642 PSIF_EVENT_SGID_TABLE_CHANGED, |
|
643 /** PKEY table have been updated by the SM */ |
|
644 PSIF_EVENT_PKEY_TABLE_CHANGED, |
|
645 /** SM lid have been updated by master SM */ |
|
646 PSIF_EVENT_MASTER_SM_LID_CHANGED, |
|
647 /** The SMs SL have changed */ |
|
648 PSIF_EVENT_MASTER_SM_SL_CHANGED, |
|
649 /** */ |
|
650 PSIF_EVENT_SUBNET_TIMEOUT_CHANGED, |
|
651 /** */ |
|
652 PSIF_EVENT_IS_SM_DISABLED_CHANGED, |
|
653 /** New master SM - client must reregister */ |
|
654 PSIF_EVENT_CLIENT_REREGISTER, |
|
655 /** vHCA have been assigned a new LID */ |
|
656 PSIF_EVENT_LID_TABLE_CHANGED, |
|
657 /** */ |
|
658 PSIF_EVENT_EPSC_COMPLETION, |
|
659 /** Mailbox request handled (only if EPSC_FL_NOTIFY was set in the request) */ |
|
660 PSIF_EVENT_MAILBOX, |
|
661 /** The real event type value is found in `eq_entry::extension_type` */ |
|
662 PSIF_EVENT_EXTENSION, |
|
663 /** Host should retrieve the EPS log for persistent storage */ |
|
664 PSIF_EVENT_LOG, |
|
665 /** */ |
|
666 PSIF_EVENT_PORT_ACTIVE, |
|
667 /** */ |
|
668 PSIF_EVENT_PORT_ERR, |
|
669 /** Event queue full (replaces the actual event) */ |
|
670 PSIF_EVENT_QUEUE_FULL, |
|
671 /** FW entered degraded mode */ |
|
672 PSIF_EVENT_DEGRADED_MODE, |
|
673 /* Padding out to required bits allocated */ |
|
674 PSIF_EVENT_FIELD_MAX = 0x7fffffff |
|
675 }; /* enum psif_event [32 bits] */ |
|
676 |
|
677 /* |
|
678 * Enumerations of error types. The following error types are defined for the |
|
679 * TSU: TSU_NO_ERROR = 8'h0 TSU_IBPR_ICRC_ERR TSU_IBPR_INVALID_PKEY_ERR |
|
680 * TSU_IBPR_INVALID_QP_ERR TSU_IBPR_VSWITCH_UF_ERR |
|
681 * TSU_IBPR_UNDEFINED_OPCODE_ERR TSU_IBPR_MCAST_NO_GRH_ERR |
|
682 * TSU_IBPR_MCAST_NO_TARGET_ERR TSU_IBPR_INVALID_DGID_ERR TSU_IBPR_BADPKT_ERR |
|
683 * TSU_RCV_QP_INVALID_ERR TSU_RCV_HDR_BTH_TVER_ERR TSU_RCV_HDR_BTH_QP_ERR |
|
684 * TSU_RCV_HDR_GRH_ERR TSU_RCV_HDR_PKEY_ERR TSU_RCV_HDR_QKEY_ERR |
|
685 * TSU_RCV_HDR_LID_ERR TSU_RCV_HDR_MAD_ERR TSU_RCV_EOIB_MCAST_ERR |
|
686 * TSU_RCV_EOIB_BCAST_ERR TSU_RCV_EOIB_UCAST_ERR TSU_RCV_EOIB_FRAGMENT_ERR |
|
687 * TSU_RCV_EOIB_RUNTS_ERR TSU_RCV_EOIB_OUTER_VLAN_ERR |
|
688 * TSU_RCV_EOIB_VLAN_TAG_ERR TSU_RCV_EOIB_VID_ERR TSU_RCV_MCAST_DUP_ERR |
|
689 * TSU_RCV_ECC_ERR TSU_DSCR_RESPONDER_RC_PSN_ERR |
|
690 * TSU_DSCR_RESPONDER_RC_DUPLICATE TSU_DSCR_RESPONDER_RC_OPCODE_SEQ_ERR |
|
691 * TSU_DSCR_RESPONDER_RC_OPCODE_VAL_ERR TSU_DSCR_RESPONDER_RC_OPCODE_LEN_ERR |
|
692 * TSU_DSCR_RESPONDER_RC_DMALEN_ERR TSU_DSCR_RESPONDER_XRC_PSN_ERR |
|
693 * TSU_DSCR_RESPONDER_XRC_DUPLICATE TSU_DSCR_RESPONDER_XRC_OPCODE_SEQ_ERR |
|
694 * TSU_DSCR_RESPONDER_XRC_OPCODE_VAL_ERR |
|
695 * TSU_DSCR_RESPONDER_XRC_OPCODE_LEN_ERR TSU_DSCR_RESPONDER_XRC_DMALEN_ERR |
|
696 * TSU_DSCR_RESPONDER_UC_PSN_ERR TSU_DSCR_RESPONDER_UC_OPCODE_SEQ_ERR |
|
697 * TSU_DSCR_RESPONDER_UC_OPCODE_VAL_ERR TSU_DSCR_RESPONDER_UC_OPCODE_LEN_ERR |
|
698 * TSU_DSCR_RESPONDER_UC_DMALEN_ERR TSU_DSCR_RESPONDER_UD_OPCODE_LEN_ERR |
|
699 * TSU_DSCR_RESPONDER_DUPLICATE_WITH_ERR |
|
700 * TSU_DSCR_QP_CAP_MASKED_ATOMIC_ENABLE_ERR |
|
701 * TSU_DSCR_QP_CAP_RDMA_RD_ENABLE_ERR TSU_DSCR_QP_CAP_RDMA_WR_ENABLE_ERR |
|
702 * TSU_DSCR_QP_CAP_ATOMIC_ENABLE_ERR TSU_DSCR_XRC_DOMAIN_VIOLATION_ERR |
|
703 * TSU_DSCR_XRCETH_ERR TSU_DSCR_RQ_INVALID_ERR TSU_DSCR_RQ_PD_CHECK_ERR |
|
704 * TSU_DSCR_RQ_EMPTY_ERR TSU_DSCR_RQ_IN_ERROR_ERR |
|
705 * TSU_DSCR_TRANSLATION_TYPE_ERR TSU_DSCR_RQ_DESCRIPTOR_INCONSISTENT_ERR |
|
706 * TSU_DSCR_PCIE_ERR TSU_DSCR_ECC_ERR TSU_RQH_PCIE_ERR TSU_RQH_SGL_LKEY_ERR |
|
707 * TSU_RQH_NOT_ENOUGH_RQ_SPACE_ERR TSU_RQH_ECC_ERR TSU_VAL_DUPLICATE_WITH_ERR |
|
708 * TSU_VAL_RKEY_VLD_ERR TSU_VAL_RKEY_ADDR_RANGE_ERR TSU_VAL_RKEY_ACCESS_ERR |
|
709 * TSU_VAL_RKEY_PD_ERR TSU_VAL_RKEY_RANGE_ERR TSU_VAL_LKEY_VLD_ERR |
|
710 * TSU_VAL_LKEY_ADDR_RANGE_ERR TSU_VAL_LKEY_ACCESS_ERR TSU_VAL_LKEY_PD_ERR |
|
711 * TSU_VAL_LKEY_RANGE_ERR TSU_VAL_TRANSLATION_TYPE_ERR TSU_VAL_PCIE_ERR |
|
712 * TSU_VAL_ECC_ERR TSU_MMU_DUPLICATE_WITH_ERR TSU_MMU_PTW_ERR TSU_MMU_UF_ERR |
|
713 * TSU_MMU_AC_ERR TSU_MMU_ECC_ERR TSU_CBLD_CQ_INVALID_ERR |
|
714 * TSU_CBLD_CQ_FULL_ERR TSU_CBLD_CQ_IS_PROXY_ERR |
|
715 * TSU_CBLD_TRANSLATION_TYPE_ERR TSU_CBLD_CQ_DESCRIPTOR_INCONSISTENT_ERR |
|
716 * TSU_CBLD_ECC_ERR TSU_CBLD_QP_ERR TSU_RQS_CHECKSUM_ERR TSU_RQS_SEQNUM_ERR |
|
717 * TSU_RQS_INVALID_REQUEST_ERR TSU_RQS_QP_IN_WRONG_STATE_ERR |
|
718 * TSU_RQS_STOP_TIMER_ERR TSU_RQS_CMD_FROM_EPS_ERR TSU_RQS_SQ_FLUSH_ERR |
|
719 * TSU_RQS_SMP_NOT_AUTH_ERR TSU_RQS_REQUEST_FENCED_ERR |
|
720 * TSU_RQS_MAX_OUTSTANDING_REACHED_ERR TSU_RQS_ECC_ERR |
|
721 * TSU_RQS_EOIB_QKEY_VIOLATION TSU_RQS_IPOIB_QKEY_VIOLATION |
|
722 * TSU_RQS_EOIB_MODE_VIOLATION TSU_RQS_MISCONFIGURED_QP |
|
723 * TSU_RQS_PORT_AUTH_VIOLATION TSU_DMA_SGL_RD_ERR TSU_DMA_PYLD_RD_ERR |
|
724 * TSU_DMA_SGL_LENGTH_ERR TSU_DMA_LKEY_ERR TSU_DMA_RKEY_ERR |
|
725 * TSU_DMA_LSO_PKTLEN_ERR TSU_DMA_LSO_ILLEGAL_CLASSIFICATION_ERR |
|
726 * TSU_DMA_PCIE_ERR TSU_DMA_ECC_ERR TSU_CMPL_PCIE_ERR TSU_CMPL_ECC_ERR |
|
727 * TSU_CMPL_REQUESTER_PSN_ERR TSU_CMPL_REQUESTER_SYNDROME_ERR |
|
728 * TSU_CMPL_REQUESTER_OUTSTANDING_MATCH_ERR TSU_CMPL_REQUESTER_LEN_ERR |
|
729 * TSU_CMPL_REQUESTER_UNEXP_OPCODE_ERR TSU_CMPL_REQUESTER_DUPLICATE |
|
730 * TSU_CMPL_RC_IN_ERROR_ERR TSU_CMPL_NAK_RNR_ERR TSU_CMPL_NAK_SEQUENCE_ERR |
|
731 * TSU_CMPL_NAK_INVALID_REQUEST_ERR TSU_CMPL_NAK_REMOTE_ACCESS_ERR |
|
732 * TSU_CMPL_NAK_REMOTE_OPS_ERR TSU_CMPL_NAK_INVALID_RD_REQUEST_ERR |
|
733 * TSU_CMPL_TIMEOUT_ERR TSU_CMPL_IMPLIED_NAK TSU_CMPL_GHOST_RESP_ERR |
|
734 */ |
|
735 enum psif_tsu_error_types { |
|
736 TSU_NO_ERROR = 0, |
|
737 TSU_IBPR_ICRC_ERR, |
|
738 TSU_IBPR_INVALID_PKEY_ERR, |
|
739 TSU_IBPR_INVALID_QP_ERR, |
|
740 TSU_IBPR_VSWITCH_UF_ERR, |
|
741 TSU_IBPR_PKTLEN_ERR, |
|
742 TSU_IBPR_UNDEFINED_OPCODE_ERR, |
|
743 TSU_IBPR_MCAST_NO_GRH_ERR, |
|
744 TSU_IBPR_MCAST_NO_TARGET_ERR, |
|
745 TSU_IBPR_INVALID_DGID_ERR, |
|
746 TSU_IBPR_BADPKT_ERR, |
|
747 TSU_RCV_QP_INVALID_ERR, |
|
748 TSU_RCV_HDR_BTH_TVER_ERR, |
|
749 TSU_RCV_HDR_BTH_QP_ERR, |
|
750 TSU_RCV_HDR_GRH_ERR, |
|
751 TSU_RCV_HDR_PKEY_ERR, |
|
752 TSU_RCV_HDR_QKEY_ERR, |
|
753 TSU_RCV_HDR_LID_ERR, |
|
754 TSU_RCV_HDR_MAD_ERR, |
|
755 TSU_RCV_EOIB_MCAST_ERR, |
|
756 TSU_RCV_EOIB_BCAST_ERR, |
|
757 TSU_RCV_EOIB_UCAST_ERR, |
|
758 TSU_RCV_EOIB_TCP_PORT_VIOLATION_ERR, |
|
759 TSU_RCV_EOIB_RUNTS_ERR, |
|
760 TSU_RCV_EOIB_OUTER_VLAN_ERR, |
|
761 TSU_RCV_EOIB_VLAN_TAG_ERR, |
|
762 TSU_RCV_EOIB_VID_ERR, |
|
763 TSU_RCV_IPOIB_TCP_PORT_VIOLATION_ERR, |
|
764 TSU_RCV_MCAST_DUP_ERR, |
|
765 TSU_RCV_ECC_ERR, |
|
766 TSU_DSCR_RESPONDER_RC_PSN_ERR, |
|
767 TSU_DSCR_RESPONDER_RC_DUPLICATE, |
|
768 TSU_DSCR_RESPONDER_RC_OPCODE_SEQ_ERR, |
|
769 TSU_DSCR_RESPONDER_RC_OPCODE_VAL_ERR, |
|
770 TSU_DSCR_RESPONDER_RC_OPCODE_LEN_ERR, |
|
771 TSU_DSCR_RESPONDER_RC_DMALEN_ERR, |
|
772 TSU_DSCR_RESPONDER_XRC_PSN_ERR, |
|
773 TSU_DSCR_RESPONDER_XRC_DUPLICATE, |
|
774 TSU_DSCR_RESPONDER_XRC_OPCODE_SEQ_ERR, |
|
775 TSU_DSCR_RESPONDER_XRC_OPCODE_VAL_ERR, |
|
776 TSU_DSCR_RESPONDER_XRC_OPCODE_LEN_ERR, |
|
777 TSU_DSCR_RESPONDER_XRC_DMALEN_ERR, |
|
778 TSU_DSCR_RESPONDER_UC_PSN_ERR, |
|
779 TSU_DSCR_RESPONDER_UC_OPCODE_SEQ_ERR, |
|
780 TSU_DSCR_RESPONDER_UC_OPCODE_VAL_ERR, |
|
781 TSU_DSCR_RESPONDER_UC_OPCODE_LEN_ERR, |
|
782 TSU_DSCR_RESPONDER_UC_DMALEN_ERR, |
|
783 TSU_DSCR_RESPONDER_UD_OPCODE_LEN_ERR, |
|
784 TSU_DSCR_RESPONDER_DUPLICATE_WITH_ERR, |
|
785 TSU_DSCR_QP_CAP_MASKED_ATOMIC_ENABLE_ERR, |
|
786 TSU_DSCR_QP_CAP_RDMA_RD_ENABLE_ERR, |
|
787 TSU_DSCR_QP_CAP_RDMA_WR_ENABLE_ERR, |
|
788 TSU_DSCR_QP_CAP_ATOMIC_ENABLE_ERR, |
|
789 TSU_DSCR_XRC_DOMAIN_VIOLATION_ERR, |
|
790 TSU_DSCR_XRCETH_ERR, |
|
791 TSU_DSCR_RQ_INVALID_ERR, |
|
792 TSU_DSCR_RQ_PD_CHECK_ERR, |
|
793 TSU_DSCR_RQ_EMPTY_ERR, |
|
794 TSU_DSCR_RQ_IN_ERROR_ERR, |
|
795 TSU_DSCR_TRANSLATION_TYPE_ERR, |
|
796 TSU_DSCR_RQ_DESCRIPTOR_INCONSISTENT_ERR, |
|
797 TSU_DSCR_MISALIGNED_ATOMIC_ERR, |
|
798 TSU_DSCR_PCIE_ERR, |
|
799 TSU_DSCR_ECC_ERR, |
|
800 TSU_RQH_PCIE_ERR, |
|
801 TSU_RQH_SGL_LKEY_ERR, |
|
802 TSU_RQH_NOT_ENOUGH_RQ_SPACE_ERR, |
|
803 TSU_RQH_ECC_ERR, |
|
804 TSU_VAL_DUPLICATE_WITH_ERR, |
|
805 TSU_VAL_RKEY_VLD_ERR, |
|
806 TSU_VAL_RKEY_ADDR_RANGE_ERR, |
|
807 TSU_VAL_RKEY_ACCESS_ERR, |
|
808 TSU_VAL_RKEY_PD_ERR, |
|
809 TSU_VAL_RKEY_RANGE_ERR, |
|
810 TSU_VAL_LKEY_VLD_ERR, |
|
811 TSU_VAL_LKEY_ADDR_RANGE_ERR, |
|
812 TSU_VAL_LKEY_ACCESS_ERR, |
|
813 TSU_VAL_LKEY_PD_ERR, |
|
814 TSU_VAL_LKEY_RANGE_ERR, |
|
815 TSU_VAL_TRANSLATION_TYPE_ERR, |
|
816 TSU_VAL_PCIE_ERR, |
|
817 TSU_VAL_ECC_ERR, |
|
818 TSU_MMU_DUPLICATE_WITH_ERR, |
|
819 TSU_MMU_PTW_ERR, |
|
820 TSU_MMU_UF_ERR, |
|
821 TSU_MMU_AC_ERR, |
|
822 TSU_MMU_ECC_ERR, |
|
823 TSU_CBLD_CQ_INVALID_ERR, |
|
824 TSU_CBLD_CQ_FULL_ERR, |
|
825 TSU_CBLD_CQ_ALREADY_IN_ERR, |
|
826 TSU_CBLD_CQ_IS_PROXY_ERR, |
|
827 TSU_CBLD_TRANSLATION_TYPE_ERR, |
|
828 TSU_CBLD_CQ_DESCRIPTOR_INCONSISTENT_ERR, |
|
829 TSU_CBLD_ECC_ERR, |
|
830 TSU_CBLD_PCIE_ERR, |
|
831 TSU_CBLD_QP_ERR, |
|
832 TSU_RQS_CHECKSUM_ERR, |
|
833 TSU_RQS_SEQNUM_ERR, |
|
834 TSU_RQS_INVALID_REQUEST_ERR, |
|
835 TSU_RQS_QP_IN_WRONG_STATE_ERR, |
|
836 TSU_RQS_STOP_TIMER_ERR, |
|
837 TSU_RQS_CMD_FROM_EPS_ERR, |
|
838 TSU_RQS_SQ_FLUSH_ERR, |
|
839 TSU_RQS_SMP_NOT_AUTH_ERR, |
|
840 TSU_RQS_REQUEST_FENCED_ERR, |
|
841 TSU_RQS_MAX_OUTSTANDING_REACHED_ERR, |
|
842 TSU_RQS_ECC_ERR, |
|
843 TSU_RQS_EOIB_QKEY_VIOLATION, |
|
844 TSU_RQS_IPOIB_QKEY_VIOLATION, |
|
845 TSU_RQS_EOIB_MODE_VIOLATION, |
|
846 TSU_RQS_MISCONFIGURED_QP, |
|
847 TSU_RQS_PORT_AUTH_VIOLATION, |
|
848 TSU_DMA_SGL_RD_ERR, |
|
849 TSU_DMA_REQ_PYLD_RD_ERR, |
|
850 TSU_DMA_RESP_PYLD_RD_ERR, |
|
851 TSU_DMA_SGL_LENGTH_ERR, |
|
852 TSU_DMA_LKEY_ERR, |
|
853 TSU_DMA_RKEY_ERR, |
|
854 TSU_DMA_LSO_PKTLEN_ERR, |
|
855 TSU_DMA_LSO_ILLEGAL_CLASSIFICATION_ERR, |
|
856 TSU_DMA_PCIE_ERR, |
|
857 TSU_DMA_ECC_ERR, |
|
858 TSU_CMPL_PCIE_ERR, |
|
859 TSU_CMPL_ECC_ERR, |
|
860 TSU_CMPL_REQUESTER_PSN_ERR, |
|
861 TSU_CMPL_REQUESTER_SYNDROME_ERR, |
|
862 TSU_CMPL_REQUESTER_OUTSTANDING_MATCH_ERR, |
|
863 TSU_CMPL_REQUESTER_LEN_ERR, |
|
864 TSU_CMPL_REQUESTER_UNEXP_OPCODE_ERR, |
|
865 TSU_CMPL_REQUESTER_DUPLICATE, |
|
866 TSU_CMPL_RC_IN_ERROR_ERR, |
|
867 TSU_CMPL_NAK_RNR_ERR, |
|
868 TSU_CMPL_NAK_SEQUENCE_ERR, |
|
869 TSU_CMPL_NAK_INVALID_REQUEST_ERR, |
|
870 TSU_CMPL_NAK_REMOTE_ACCESS_ERR, |
|
871 TSU_CMPL_NAK_REMOTE_OPS_ERR, |
|
872 TSU_CMPL_NAK_INVALID_RD_REQUEST_ERR, |
|
873 TSU_CMPL_TIMEOUT_ERR, |
|
874 TSU_CMPL_IMPLIED_NAK, |
|
875 TSU_CMPL_GHOST_RESP_ERR |
|
876 }; /* enum psif_tsu_error_types [ 8 bits] */ |
|
877 |
|
878 /* |
|
879 * Here are the different EPS core IDs: PSIF_EVENT_EPS_A_1 PSIF_EVENT_EPS_A_2 |
|
880 * PSIF_EVENT_EPS_A_3 PSIF_EVENT_EPS_A_4 PSIF_EVENT_EPS_C |
|
881 */ |
|
882 enum psif_eps_core_id { |
|
883 PSIF_EVENT_CORE_EPS_A_1, |
|
884 PSIF_EVENT_CORE_EPS_A_2, |
|
885 PSIF_EVENT_CORE_EPS_A_3, |
|
886 PSIF_EVENT_CORE_EPS_A_4, |
|
887 PSIF_EVENT_CORE_EPS_C, |
|
888 /* Padding out to required bits allocated */ |
|
889 PSIF_EPS_CORE_ID_FIELD_MAX = 0xf |
|
890 }; /* enum psif_eps_core_id [ 4 bits] */ |
|
891 |
|
892 |
|
893 enum psif_epsc_log_mode { |
|
894 /* Logging completely disabled */ |
|
895 |
|
896 EPSC_LOG_MODE_OFF = 0, |
|
897 /* See epsfw/src/include/logging.h */ |
|
898 |
|
899 EPSC_LOG_MODE_SCAT = 0x1, |
|
900 EPSC_LOG_MODE_MALLOC = 0x2, |
|
901 EPSC_LOG_MODE_LOCAL = 0x3, |
|
902 /* Redirect logging to host (dma) */ |
|
903 |
|
904 EPSC_LOG_MODE_HOST = 0x4, |
|
905 /* Save the set log mode in the flash */ |
|
906 |
|
907 EPSC_LOG_MODE_SAVE = 0x10, |
|
908 /* Padding out to required bits allocated */ |
|
909 PSIF_EPSC_LOG_MODE_FIELD_MAX = 0x7fffffff |
|
910 }; /* enum psif_epsc_log_mode [32 bits] */ |
|
911 |
|
912 /** |
|
913 * EPSC_LOG_CTRL |
|
914 */ |
|
915 enum psif_epsc_log_level { |
|
916 EPS_LOG_OFF = 0, |
|
917 EPS_LOG_FATAL = 0x1, |
|
918 EPS_LOG_ERROR = 0x2, |
|
919 EPS_LOG_WARN = 0x3, |
|
920 EPS_LOG_INFO = 0x4, |
|
921 EPS_LOG_DEBUG = 0x5, |
|
922 EPS_LOG_TRACE = 0x6, |
|
923 EPS_LOG_ALL = 0x7, |
|
924 /* Padding out to required bits allocated */ |
|
925 PSIF_EPSC_LOG_LEVEL_FIELD_MAX = 0x7fffffff |
|
926 }; /* enum psif_epsc_log_level [32 bits] */ |
|
927 |
|
928 /** |
|
929 * \brief Port state |
|
930 * \details |
|
931 * This enum specifies the state of a UF port's port state machine. It |
|
932 * is used to either force a new state or to report the current state |
|
933 * (via \ref EPSC_QUERY_PORT_1 and \ref EPSC_QUERY_PORT_2). |
|
934 * |
|
935 * \par Width |
|
936 * 32 bit |
|
937 * \par Used in |
|
938 * psif_epsc_port_attr_t |
|
939 * \par Classification |
|
940 * driver, internal |
|
941 * |
|
942 * \todo |
|
943 * The externally provided version of the documentation should probably |
|
944 * not contain the information about forcing the state as this is only |
|
945 * for FW. |
|
946 */ |
|
947 enum psif_epsc_port_state { |
|
948 /** No change */ |
|
949 EPSC_PORT_NOP = 0, |
|
950 /** The port is down. */ |
|
951 EPSC_PORT_DOWN = 0x1, |
|
952 /** The port is in init state. */ |
|
953 EPSC_PORT_INIT = 0x2, |
|
954 /** The port state is armed. */ |
|
955 EPSC_PORT_ARMED = 0x3, |
|
956 /** The port is active. */ |
|
957 EPSC_PORT_ACTIVE = 0x4, |
|
958 /** The port is in deferred active state. */ |
|
959 EPSC_PORT_ACTIVE_DEFER = 0x5, |
|
960 /* Padding out to required bits allocated */ |
|
961 PSIF_EPSC_PORT_STATE_FIELD_MAX = 0x7fffffff |
|
962 }; /* enum psif_epsc_port_state [32 bits] */ |
|
963 |
|
964 /** |
|
965 * \brief Version fixed copy of psif_path_mtu |
|
966 * \details |
|
967 * This enum specifies the path MTU values and is the same as `psif_path_mtu` |
|
968 * found in `psif_verbs.h`. The difference is the data type. The version in |
|
969 * `psif_verbs.h` is smaller! |
|
970 * |
|
971 * \todo |
|
972 * Change version in `psif_verbs.h` to 32b and then drop this one here? |
|
973 * |
|
974 * \par Width |
|
975 * 32 bit |
|
976 * \par Used in |
|
977 * psif_epsc_port_attr_t |
|
978 * \par Classification |
|
979 * driver |
|
980 */ |
|
981 enum psif_epsc_path_mtu { |
|
982 /** Not a valid MTU. */ |
|
983 EPSC_MTU_INVALID = 0, |
|
984 /** The MTU is 256 bytes. */ |
|
985 EPSC_MTU_256B = 0x1, |
|
986 /** The MTU is 512 bytes. */ |
|
987 EPSC_MTU_512B = 0x2, |
|
988 /** The MTU is 1024 bytes. */ |
|
989 EPSC_MTU_1024B = 0x3, |
|
990 /** The MTU is 2048 bytes. */ |
|
991 EPSC_MTU_2048B = 0x4, |
|
992 /** The MTU is 4069 bytes. */ |
|
993 EPSC_MTU_4096B = 0x5, |
|
994 /** The MTU is 10240 bytes. */ |
|
995 EPSC_MTU_10240B = 0x6, |
|
996 /** Not a specific MTU. */ |
|
997 EPSC_MTU_XXX = 0x7, |
|
998 /* Padding out to required bits allocated */ |
|
999 PSIF_EPSC_PATH_MTU_FIELD_MAX = 0x7fffffff |
|
1000 }; /* enum psif_epsc_path_mtu [32 bits] */ |
|
1001 |
|
1002 /** |
|
1003 * \brief Monitors handling asynchronous event |
|
1004 * \details |
|
1005 * This is only found in a structure definition in EPS-A but not used there. |
|
1006 * |
|
1007 * \todo |
|
1008 * Remove this? |
|
1009 * |
|
1010 * \par Width |
|
1011 * 4 bit |
|
1012 * \par Used in |
|
1013 * N/A |
|
1014 * \par Classification |
|
1015 * unused |
|
1016 */ |
|
1017 enum psif_epsc_monitor { |
|
1018 PSIF_MONITOR_ARM, |
|
1019 PSIF_MONITOR_TRIG, |
|
1020 PSIF_MONITOR_REARM, |
|
1021 PSIF_MONITOR_INACTIVE, |
|
1022 PSIF_MONITOR_ERROR, |
|
1023 /* Padding out to required bits allocated */ |
|
1024 PSIF_EPSC_MONITOR_FIELD_MAX = 0xf |
|
1025 }; /* enum psif_epsc_monitor [ 4 bits] */ |
|
1026 |
|
1027 /** |
|
1028 * \brief Interrupt sources definitions as bit indexes. |
|
1029 * \details |
|
1030 * In a mask the active interrupt sources are represented by set bits |
|
1031 * `bits[x]=(1 << EPSC_INTR_x)`. These values are defined by hardware. |
|
1032 * |
|
1033 * \par Width |
|
1034 * 5 bit |
|
1035 * \par Used in |
|
1036 * N/A |
|
1037 * \par Classification |
|
1038 * internal, development |
|
1039 */ |
|
1040 enum psif_epsc_interrupt_source { |
|
1041 /** Interrupt source is LCSR OR_LOW only with own (HI-)pin. */ |
|
1042 EPSC_INTR_LCSR, |
|
1043 /** Interrupt source is message box OR_LOW only with own (HI-)pin. */ |
|
1044 EPSC_INTR_MBOX, |
|
1045 /** Interrupt source is XIU OR_LOW only with own (HI-)pin. */ |
|
1046 EPSC_INTR_XIU, |
|
1047 /** Interrupt source is IBU-0 OR_LOW only with own (HI-)pin. */ |
|
1048 EPSC_INTR_IBU0, |
|
1049 /** Interrupt source is IBU-1 OR_LOW only with own (HI-)pin. */ |
|
1050 EPSC_INTR_IBU1, |
|
1051 /** Interrupt source is NCSI. */ |
|
1052 EPSC_INTR_TSU_NCSI, |
|
1053 /** Interrupt source is IBPB. */ |
|
1054 EPSC_INTR_TSU_IBPB, |
|
1055 /** Interrupt source is DMA. */ |
|
1056 EPSC_INTR_TSU_DMA, |
|
1057 /** Interrupt source is RQS. */ |
|
1058 EPSC_INTR_TSU_RQS, |
|
1059 /** Interrupt source is QPS. */ |
|
1060 EPSC_INTR_TSU_QPS, |
|
1061 /** Interrupt source is SQS. */ |
|
1062 EPSC_INTR_TSU_SQS, |
|
1063 /** Interrupt source is ERR. */ |
|
1064 EPSC_INTR_TSU_ERR, |
|
1065 /** Interrupt source is CMPL. */ |
|
1066 EPSC_INTR_TSU_CMPL, |
|
1067 /** Interrupt source is VAL. */ |
|
1068 EPSC_INTR_TSU_VAL, |
|
1069 /** Interrupt source is RQH. */ |
|
1070 EPSC_INTR_TSU_RQH, |
|
1071 /** Interrupt source is DSCR. */ |
|
1072 EPSC_INTR_TSU_DSCR, |
|
1073 /** Interrupt source is RCV. */ |
|
1074 EPSC_INTR_TSU_RCV, |
|
1075 /** Interrupt source is IBPR. */ |
|
1076 EPSC_INTR_TSU_IBPR, |
|
1077 /** Interrupt source is CBU. */ |
|
1078 EPSC_INTR_TSU_CBU, |
|
1079 /** Interrupt source is HOST. */ |
|
1080 EPSC_INTR_TSU_HOST, |
|
1081 /** Interrupt source is MMU. */ |
|
1082 EPSC_INTR_TSU_MMU |
|
1083 }; /* enum psif_epsc_interrupt_source [ 5 bits] */ |
|
1084 |
|
1085 /** |
|
1086 * \brief Interrupt severity levels |
|
1087 * \details |
|
1088 * This lists the interrupt levels as used by the simulators PRM responder |
|
1089 * (psifsim) and cosim. They are not in sync with the values used by EPS |
|
1090 * firmware. |
|
1091 * |
|
1092 * \par Width |
|
1093 * 2 bit |
|
1094 * \par Used in |
|
1095 * N/A |
|
1096 * \par Classification |
|
1097 * development |
|
1098 */ |
|
1099 enum psif_epsc_interrupt_pri { |
|
1100 /** unknown/invalid interrupt priority */ |
|
1101 EPSC_INTR_RESERVED, |
|
1102 /** low interrupt priority */ |
|
1103 EPSC_INTR_LOW, |
|
1104 /** high interrupt priority */ |
|
1105 EPSC_INTR_HIGH, |
|
1106 /** nonmaskable/fatal interrupt */ |
|
1107 EPSC_INTR_FATAL |
|
1108 }; /* enum psif_epsc_interrupt_pri [ 2 bits] */ |
|
1109 |
|
1110 /** |
|
1111 * \brief Query HCA verb response member `atomicity guarantee` values |
|
1112 * \details |
|
1113 * This enum specifies values possible for the (masked) atomicity guarantee |
|
1114 * capability reported in the Query HCA verb (via \ref EPSC_QUERY_DEVICE). |
|
1115 * |
|
1116 * \par Width |
|
1117 * 32 bit |
|
1118 * \par Used in |
|
1119 * psif_epsc_device_attr_t |
|
1120 * \par Classification |
|
1121 * driver |
|
1122 */ |
|
1123 enum psif_epsc_atomic_cap { |
|
1124 /** no atomicity guarantee */ |
|
1125 EPSC_ATOMIC_NONE, |
|
1126 /** HCA atomicity guarantee */ |
|
1127 EPSC_ATOMIC_HCA, |
|
1128 /** global atomicity guarantee */ |
|
1129 EPSC_ATOMIC_GLOB, |
|
1130 /* Padding out to required bits allocated */ |
|
1131 PSIF_EPSC_ATOMIC_CAP_FIELD_MAX = 0x7fffffff |
|
1132 }; /* enum psif_epsc_atomic_cap [32 bits] */ |
|
1133 |
|
1134 /** |
|
1135 * \brief The EPS-C FW status return codes |
|
1136 * \details These error codes are retured from the EPS-C. |
|
1137 * \par Width |
|
1138 * 8 bit |
|
1139 * \par Used in |
|
1140 * psif_epsc_csr_rsp member `status` |
|
1141 * \par Classification |
|
1142 * external, driver |
|
1143 */ |
|
1144 enum psif_epsc_csr_status { |
|
1145 /** Successful exit status. */ |
|
1146 EPSC_SUCCESS = 0, |
|
1147 /** Key was rejected by service. */ |
|
1148 EPSC_EKEYREJECTED = 0x1, |
|
1149 /** Cannot assign requested address. */ |
|
1150 EPSC_EADDRNOTAVAIL = 0x2, |
|
1151 /** Operation not supported on transport endpoint. */ |
|
1152 EPSC_EOPNOTSUPP = 0x3, |
|
1153 /** Out of memory. */ |
|
1154 EPSC_ENOMEM = 0x4, |
|
1155 /** No data available. */ |
|
1156 EPSC_ENODATA = 0x5, |
|
1157 /** Try again. */ |
|
1158 EPSC_EAGAIN = 0x6, |
|
1159 /** Operation canceled. */ |
|
1160 EPSC_ECANCELED = 0x7, |
|
1161 /** Connection reset by peer. */ |
|
1162 EPSC_ECONNRESET = 0x8, |
|
1163 /** CSR operation failed. */ |
|
1164 EPSC_ECSR = 0x9, |
|
1165 /** Modify queue pair error: QP index out of range. */ |
|
1166 EPSC_MODIFY_QP_OUT_OF_RANGE = 0xa, |
|
1167 /** Modify queue pair error: QP is invalid. */ |
|
1168 EPSC_MODIFY_QP_INVALID = 0xb, |
|
1169 /** Modify queue pair error: failed to change QP attribute. */ |
|
1170 EPSC_MODIFY_CANNOT_CHANGE_QP_ATTR = 0xc, |
|
1171 /** Modify queue pair error: failed to change QP due to invalid or not matching state. */ |
|
1172 EPSC_MODIFY_INVALID_QP_STATE = 0xd, |
|
1173 /** Modify queue pair error: failed to change QP due to invalid or not matching migration state. */ |
|
1174 EPSC_MODIFY_INVALID_MIG_STATE = 0xe, |
|
1175 /** Modify queue pair error: the operation timed out. */ |
|
1176 EPSC_MODIFY_TIMEOUT = 0xf, |
|
1177 /** DMA test failure in HEAD. */ |
|
1178 EPSC_ETEST_HEAD = 0x10, |
|
1179 /** DMA test failure in TAIL. */ |
|
1180 EPSC_ETEST_TAIL = 0x11, |
|
1181 /** DMA test failure in PATTERN. */ |
|
1182 EPSC_ETEST_PATTERN = 0x12, |
|
1183 /** Multicast address already exist. */ |
|
1184 EPSC_EADDRINUSE = 0x13, |
|
1185 /** vHCA out of range */ |
|
1186 EPSC_EINVALID_VHCA = 0x14, |
|
1187 /** Port out of range */ |
|
1188 EPSC_EINVALID_PORT = 0x15, |
|
1189 /** Address out of range */ |
|
1190 EPSC_EINVALID_ADDRESS = 0x16, |
|
1191 /** Parameter out of range */ |
|
1192 EPSC_EINVALID_PARAMETER = 0x17, |
|
1193 /** General failure. */ |
|
1194 EPSC_FAIL = 0xff |
|
1195 }; /* enum psif_epsc_csr_status [ 8 bits] */ |
|
1196 |
|
1197 /** |
|
1198 * \brief Host to EPS operation codes |
|
1199 * \details |
|
1200 * These operation codes are sent in the \ref psif_epsc_csr_req::opcode member |
|
1201 * from the host or a particular core (EPS-Ax/EPS-C) to the mailbox thread in |
|
1202 * EPS-C or EPS-Ax in order to specify the request. In addition the operation |
|
1203 * codes are used as a selector for the \ref psif_epsc_csr_req::u member of |
|
1204 * type \ref psif_epsc_csr_details_t in order to specify the particular |
|
1205 * structure if the request requires specific arguments. In some cases the |
|
1206 * selected structure defines an own set of sub-operation codes like for |
|
1207 * \ref EPSC_QUERY with \ref psif_epsc_query_req_t::op of type |
|
1208 * \ref psif_epsc_query_op_t. |
|
1209 * \par |
|
1210 * Responses are always of type \ref psif_epsc_csr_rsp_t but the meaning of the |
|
1211 * members of that structure depend on the operation code. The response state |
|
1212 * is \ref EPSC_EADDRNOTAVAIL for all not supported operation codes. |
|
1213 * |
|
1214 * \par Width |
|
1215 * 8 bit |
|
1216 * \par Used in |
|
1217 * psif_epsc_csr_req_t |
|
1218 * \par Classification |
|
1219 * see each of the operation codes |
|
1220 * |
|
1221 * \note |
|
1222 * - All codes must be unique and fit into a 8 bit number. |
|
1223 * - In order to provide backward compatibility new codes must start from the |
|
1224 * current value of \ref EPSC_LAST_OP and the value of \ref EPSC_LAST_OP |
|
1225 * must be incremented by the number of newly inserted codes. |
|
1226 */ |
|
1227 enum psif_epsc_csr_opcode { |
|
1228 /** Not a valid operation code. */ |
|
1229 EPSC_NOOP = 0, |
|
1230 /** EPS-C ping over mailbox. */ |
|
1231 EPSC_MAILBOX_PING = 0x4c, |
|
1232 /** Host patting of EPS-C SW watch-dog. */ |
|
1233 EPSC_KEEP_ALIVE = 0x4d, |
|
1234 /** Initial configuration request per UF. |
|
1235 * This request is transferred from the host to the epsc at driver |
|
1236 * attach using an encoding of the physical mailbox register. It |
|
1237 * is not a legal request on an operational mailbox communication |
|
1238 * |
|
1239 * \par Request |
|
1240 * Structure details: |
|
1241 * Member | Content |
|
1242 * -------|------------------- |
|
1243 * u | \ref psif_epsc_csr_config_t |
|
1244 * \par Response |
|
1245 * Structure contents: |
|
1246 * Member | Content |
|
1247 * -------|------------------- |
|
1248 * addr | number of event queues (EQ) per UF |
|
1249 * data | PSIF/EPS-C version |
|
1250 * \par |
|
1251 * The version is encoded this way: |
|
1252 * Bits | Version Specifier |
|
1253 * ------|--------- |
|
1254 * 63-48 | PSIF_MAJOR_VERSION |
|
1255 * 47-32 | PSIF_MINOR_VERSION |
|
1256 * 31-16 | EPSC_MAJOR_VERSION |
|
1257 * 15-0 | EPSC_MINOR_VERSION |
|
1258 * |
|
1259 * \par Return Codes |
|
1260 * \ref EPSC_SUCCESS |
|
1261 * \par Restrictions |
|
1262 * none (all UF) |
|
1263 * \par Classification |
|
1264 * driver |
|
1265 */ |
|
1266 EPSC_SETUP = 0x1, |
|
1267 /** Final de-configuration request. |
|
1268 * This request is sent from the host driver to indicate that it has |
|
1269 * cleaned up all queues and flushed caches associated with the current |
|
1270 * UF. It is the last command for that UF and the firmware will take down |
|
1271 * the associated virtual links and mailbox settings. For further |
|
1272 * communication with that UF the mailbox needs to be set up again via |
|
1273 * \ref EPSC_SETUP . |
|
1274 * |
|
1275 * \par Request |
|
1276 * N/A |
|
1277 * \par Return Codes |
|
1278 * \ref EPSC_SUCCESS |
|
1279 * \par Restrictions |
|
1280 * none (all UF) |
|
1281 * \par Classification |
|
1282 * driver |
|
1283 */ |
|
1284 EPSC_TEARDOWN = 0x36, |
|
1285 /** Operation code for a general set request. |
|
1286 * The request usees the same parameter structure as the \ref EPSC_QUERY |
|
1287 * request. Upon recieve the mailbox thread first processes the set request |
|
1288 * in \ref psif_epsc_csr_query_t::info and then the request in |
|
1289 * \ref psif_epsc_csr_query_t::data. Both members are of type |
|
1290 * \ref psif_epsc_query_req_t and have their own sub-operation codes in |
|
1291 * \ref psif_epsc_query_req_t::op (of type \ref psif_epsc_query_op_t). |
|
1292 * Therefore requests instantiating only one set attribute |
|
1293 * (i.e. \ref psif_epsc_csr_query_t::info or \ref psif_epsc_csr_query_t::data) |
|
1294 * have to set the sub-operation code of the other member to |
|
1295 * \ref EPSC_QUERY_BLANK. |
|
1296 * |
|
1297 * \par Request |
|
1298 * Structure details: |
|
1299 * Member | Content |
|
1300 * -------|------------------- |
|
1301 * u | \ref psif_epsc_csr_query_t |
|
1302 * \par Return Codes |
|
1303 * \ref EPSC_SUCCESS, \ref EPSC_EOPNOTSUPP, \ref EPSC_FAIL |
|
1304 * \par Restrictions |
|
1305 * none (all UF) |
|
1306 * \par Classification |
|
1307 * external |
|
1308 */ |
|
1309 EPSC_SET = 0x46, |
|
1310 /** Operation code for a single CSR write request. |
|
1311 * \note |
|
1312 * The request is deprecated and will be removed as soon as all |
|
1313 * references to this opcode have been cleaned up. |
|
1314 * \par Return Codes |
|
1315 * \ref EPSC_EADDRNOTAVAIL |
|
1316 */ |
|
1317 EPSC_SET_SINGLE = 0x2, |
|
1318 /** Operation code for setting an arbitrary CSR. |
|
1319 * \note |
|
1320 * The request is used mainly for debugging tools and will be either removed |
|
1321 * completely or limited to certain register addresses. |
|
1322 * |
|
1323 * \par Request |
|
1324 * Structure details: |
|
1325 * Member | Content |
|
1326 * -------|------------------- |
|
1327 * addr | CSR address |
|
1328 * u | `data[0]` value to write to CSR |
|
1329 * \par Response |
|
1330 * Structure contents: |
|
1331 * Member | Content |
|
1332 * -------|---------------------------------------- |
|
1333 * addr | the value `addr` from the request |
|
1334 * data | the value `data[0]` from the request |
|
1335 * |
|
1336 * \par Return Codes |
|
1337 * \ref EPSC_SUCCESS, \ref EPSC_FAIL |
|
1338 * \par Restrictions |
|
1339 * valid register addresses depend on UF |
|
1340 * \par Classification |
|
1341 * driver, development |
|
1342 */ |
|
1343 EPSC_SET_ONE_CSR = 0x3, |
|
1344 /** Old operation code to set up a descriptor base address. |
|
1345 * \note |
|
1346 * The request is deprecated and will be removed as soon as all |
|
1347 * references to this opcode have been cleaned up. |
|
1348 * |
|
1349 * \par Return Codes |
|
1350 * \ref EPSC_EADDRNOTAVAIL |
|
1351 * \par Classification |
|
1352 * driver |
|
1353 */ |
|
1354 EPSC_SETUP_BASEADDR = 0x4, |
|
1355 /** Operation code to set up a descriptor base address. |
|
1356 * With this request the driver configures the descriptor base addresses |
|
1357 * of queues, queue pairs and address handles. |
|
1358 * |
|
1359 * \par Request |
|
1360 * Structure details: |
|
1361 * Member | Content |
|
1362 * -------|------------------------------------------- |
|
1363 * addr | Descriptor base address setup CSR address |
|
1364 * u | \ref psif_epsc_csr_base_addr_t |
|
1365 * |
|
1366 * \par Return Codes |
|
1367 * \ref EPSC_SUCCESS, \ref EPSC_FAIL |
|
1368 * \par Restrictions |
|
1369 * none (all UF) |
|
1370 * \par Classification |
|
1371 * driver, development |
|
1372 */ |
|
1373 EPSC_SET_BASEADDR = 0x5, |
|
1374 /** Operation code to set up an event queue (EQ). |
|
1375 * With this request the driver configures an EQ descriptor base address |
|
1376 * as well as the associated interrupt. |
|
1377 * |
|
1378 * \par Request |
|
1379 * Structure details: |
|
1380 * Member | Content |
|
1381 * -------|------------------------------------------- |
|
1382 * addr | event queue number |
|
1383 * u | \ref psif_epsc_csr_base_addr_t |
|
1384 * |
|
1385 * \par Return Codes |
|
1386 * \ref EPSC_SUCCESS, \ref EPSC_FAIL |
|
1387 * \par Restrictions |
|
1388 * none (all UF) |
|
1389 * \par Classification |
|
1390 * driver |
|
1391 */ |
|
1392 EPSC_SET_BASEADDR_EQ = 0x6, |
|
1393 /* Set Local ID for UF (backdoor) */ |
|
1394 EPSC_SET_LID = 0x7, |
|
1395 OBSOLETE_1 = 0x8, |
|
1396 OBSOLETE_2 = 0x9, |
|
1397 /* Set Global ID for UF (backdoor) */ |
|
1398 EPSC_SET_GID = 0xa, |
|
1399 /* Set EoIB MAC address (backdoor) */ |
|
1400 EPSC_SET_EOIB_MAC = 0x40, |
|
1401 /* Set Vlink state */ |
|
1402 EPSC_SET_VLINK_STATE = 0xb, |
|
1403 /* Get Vlink state */ |
|
1404 EPSC_QUERY_VLINK_STATE = 0xc, |
|
1405 /* Reset UF at startup */ |
|
1406 EPSC_UF_RESET = 0xd, |
|
1407 /* Modify QP complete w/kick */ |
|
1408 EPSC_MODIFY_QP = 0xe, |
|
1409 /* Get single 64bit register - depricated */ |
|
1410 EPSC_GET_SINGLE = 0xf, |
|
1411 /* Get one 64bit register using CSR addr */ |
|
1412 EPSC_GET_ONE_CSR = 0x10, |
|
1413 /* Query QP sub-entry */ |
|
1414 EPSC_QUERY_QP = 0x11, |
|
1415 /** Query HW receive queue. */ |
|
1416 EPSC_QUERY_HW_RQ = 0x42, |
|
1417 /** Query HW SQ. */ |
|
1418 EPSC_QUERY_HW_SQ = 0x43, |
|
1419 /* Non-MAD query device */ |
|
1420 EPSC_QUERY_DEVICE = 0x12, |
|
1421 /* Non-MAD query port */ |
|
1422 EPSC_QUERY_PORT_1 = 0x13, |
|
1423 EPSC_QUERY_PORT_2 = 0x14, |
|
1424 /* Non-MAD SMA attribute query */ |
|
1425 EPSC_QUERY_PKEY = 0x15, |
|
1426 EPSC_QUERY_GID = 0x16, |
|
1427 /* Non-MAD SMA attribute setting */ |
|
1428 EPSC_MODIFY_DEVICE = 0x17, |
|
1429 EPSC_MODIFY_PORT_1 = 0x18, |
|
1430 EPSC_MODIFY_PORT_2 = 0x19, |
|
1431 /* Local MC subscription handling */ |
|
1432 EPSC_MC_ATTACH = 0x1a, |
|
1433 EPSC_MC_DETACH = 0x1b, |
|
1434 EPSC_MC_QUERY = 0x1c, |
|
1435 /* Handle asynchronous events */ |
|
1436 EPSC_EVENT_ACK = 0x1d, |
|
1437 EPSC_EVENT_INDEX = 0x1e, |
|
1438 /* Program flash content */ |
|
1439 EPSC_FLASH_START = 0x1f, |
|
1440 EPSC_FLASH_INFO = 0x20, |
|
1441 EPSC_FLASH_ERASE_SECTOR = 0x21, |
|
1442 EPSC_FLASH_RD = 0x22, |
|
1443 EPSC_FLASH_WR = 0x23, |
|
1444 EPSC_FLASH_CHECK = 0x24, |
|
1445 EPSC_FLASH_SCAN = 0x25, |
|
1446 EPSC_FLASH_STOP = 0x26, |
|
1447 /* new update handling */ |
|
1448 EPSC_UPDATE = 0x47, |
|
1449 /* IB packet tracer */ |
|
1450 EPSC_TRACE_STATUS = 0x27, |
|
1451 EPSC_TRACE_SETUP = 0x28, |
|
1452 EPSC_TRACE_START = 0x29, |
|
1453 EPSC_TRACE_STOP = 0x2a, |
|
1454 EPSC_TRACE_ACQUIRE = 0x2b, |
|
1455 /* Test operations */ |
|
1456 EPSC_TEST_HOST_RD = 0x2c, |
|
1457 EPSC_TEST_HOST_WR = 0x2d, |
|
1458 /* Get EPS-C version details */ |
|
1459 EPSC_FW_VERSION = 0x2e, |
|
1460 /* Redirection/configuration of EPSC's internal log subsystem */ |
|
1461 EPSC_LOG_CTRL = 0x2f, |
|
1462 EPSC_LOG_REQ_NOTIFY = 0x30, |
|
1463 /* Force & read back link speed */ |
|
1464 EPSC_LINK_CNTRL = 0x31, |
|
1465 /* EPS-A control & communication (to EPS-C) */ |
|
1466 EPSC_A_CONTROL = 0x33, |
|
1467 /* EPS-A targeted commands (to EPS-A) */ |
|
1468 EPSC_A_COMMAND = 0x35, |
|
1469 /* Exercise mmu with access from epsc */ |
|
1470 EPSC_EXERCISE_MMU = 0x34, |
|
1471 /* Access to EPS-C CLI */ |
|
1472 EPSC_CLI_ACCESS = 0x37, |
|
1473 /* IB packet proxy to/from host */ |
|
1474 EPSC_MAD_PROCESS = 0x38, |
|
1475 EPSC_MAD_SEND_WR = 0x39, |
|
1476 /** Generic query epsc interface. */ |
|
1477 EPSC_QUERY = 0x41, |
|
1478 /* Setup interrupt coalescing etc. */ |
|
1479 EPSC_HOST_INT_COMMON_CTRL = 0x44, |
|
1480 EPSC_HOST_INT_CHANNEL_CTRL = 0x45, |
|
1481 /** UF control depends on \ref psif_epsc_csr_uf_ctrl_t::opcode. */ |
|
1482 EPSC_UF_CTRL = 0x48, |
|
1483 /* Flush MMU and-or PTW Caches */ |
|
1484 EPSC_FLUSH_CACHES = 0x49, |
|
1485 /* Query PMA counters - alternative path to sending MAD's */ |
|
1486 EPSC_PMA_COUNTERS = 0x4a, |
|
1487 /** VIMMA operations depends on \ref psif_epsc_csr_vimma_ctrl_t::opcode. */ |
|
1488 EPSC_VIMMA_CTRL = 0x4b, |
|
1489 /** EOF marker - must be last and highest in this enum type. */ |
|
1490 EPSC_LAST_OP = 0x4e, |
|
1491 /* Padding out to required bits allocated */ |
|
1492 PSIF_EPSC_CSR_OPCODE_FIELD_MAX = 0xff |
|
1493 }; /* enum psif_epsc_csr_opcode [ 8 bits] */ |
|
1494 |
|
1495 /** |
|
1496 * The eps-c fw csr flags |
|
1497 */ |
|
1498 enum psif_epsc_csr_flags { |
|
1499 EPSC_FL_NONE = 0, |
|
1500 /* Request notification (interrupt) when completion is ready */ |
|
1501 EPSC_FL_NOTIFY = 0x1, |
|
1502 /* Privileged QP indicator only valid for query and modify QP */ |
|
1503 EPSC_FL_PQP = 0x2, |
|
1504 /* Allways report opertion success */ |
|
1505 EPSC_FL_IGNORE_ERROR = 0x4, |
|
1506 /* Padding out to required bits allocated */ |
|
1507 PSIF_EPSC_CSR_FLAGS_FIELD_MAX = 0xff |
|
1508 }; /* enum psif_epsc_csr_flags [ 8 bits] */ |
|
1509 |
|
1510 /* |
|
1511 * Link states for the virtual HCA and switch. The following onehot encoded |
|
1512 * states exist: PSIF_LINK_DISABLED = 1 PSIF_LINK_DOWN = 2 PSIF_LINK_INIT = 4 |
|
1513 * PSIF_LINK_ARM = 8 PSIF_LINK_ACTIVE = 16 |
|
1514 */ |
|
1515 enum psif_vlink_state { |
|
1516 PSIF_LINK_DISABLED = 0x1, |
|
1517 PSIF_LINK_DOWN = 0x2, |
|
1518 PSIF_LINK_INIT = 0x4, |
|
1519 PSIF_LINK_ARM = 0x8, |
|
1520 PSIF_LINK_ACTIVE = 0x10 |
|
1521 }; /* enum psif_vlink_state [ 5 bits] */ |
|
1522 |
|
1523 /** |
|
1524 * EPSC_MODIFY_DEVICE operations |
|
1525 */ |
|
1526 enum psif_epsc_csr_modify_device_flags { |
|
1527 PSIF_DEVICE_MODIFY_SYS_IMAGE_GUID = 0x1, |
|
1528 PSIF_DEVICE_MODIFY_NODE_DESC = 0x2, |
|
1529 /* Padding out to required bits allocated */ |
|
1530 PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_FIELD_MAX = 0xffff |
|
1531 }; /* enum psif_epsc_csr_modify_device_flags [16 bits] */ |
|
1532 |
|
1533 /** |
|
1534 * EPSC_MODIFY_PORT_{1,2} operations |
|
1535 */ |
|
1536 enum psif_epsc_csr_modify_port_flags { |
|
1537 PSIF_PORT_SHUTDOWN = 0x1, |
|
1538 PSIF_PORT_INIT_TYPE = 0x4, |
|
1539 PSIF_PORT_RESET_QKEY_CNTR = 0x8, |
|
1540 PSIF_PORT_RESET_PKEY_CNTR = 0x10, |
|
1541 /* Padding out to required bits allocated */ |
|
1542 PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_FIELD_MAX = 0xffff |
|
1543 }; /* enum psif_epsc_csr_modify_port_flags [16 bits] */ |
|
1544 |
|
1545 |
|
1546 enum psif_epsc_csr_epsa_command { |
|
1547 EPSC_A_LOAD, |
|
1548 EPSC_A_START, |
|
1549 EPSC_A_STOP, |
|
1550 EPSC_A_STATUS, |
|
1551 /* Padding out to required bits allocated */ |
|
1552 PSIF_EPSC_CSR_EPSA_COMMAND_FIELD_MAX = 0x7fffffff |
|
1553 }; /* enum psif_epsc_csr_epsa_command [32 bits] */ |
|
1554 |
|
1555 /* |
|
1556 */ |
|
1557 enum psif_epsa_command { |
|
1558 EPSA_DYNAMIC_LOAD, |
|
1559 EPSA_TEST_FABOUT, |
|
1560 EPSA_TEST_FABIN, |
|
1561 EPSA_TEST_FABIN_FABOUT, |
|
1562 EPSA_TEST_SKJM_MEMREAD, |
|
1563 EPSA_TEST_SKJM_MEMWRITE, |
|
1564 EPSA_TEST_SKJM_MEMLOCK, |
|
1565 EPSA_SKJM_LOAD, |
|
1566 EPSA_SKJM_ACC, |
|
1567 EPSA_SKJM_MEMACC, |
|
1568 EPSA_GET_PROXY_QP_SQ_KEY, |
|
1569 EPSA_GENERIC_CMD, |
|
1570 /* Padding out to required bits allocated */ |
|
1571 PSIF_EPSA_COMMAND_FIELD_MAX = 0x7fffffff |
|
1572 }; /* enum psif_epsa_command [32 bits] */ |
|
1573 |
|
1574 /** |
|
1575 * \brief Sub-operation codes as used by EPSC_QUERY and EPSC_SET requests. |
|
1576 * \details |
|
1577 * \par Width |
|
1578 * 32 bit |
|
1579 * \par Used in |
|
1580 * psif_epsc_query_req member `op` |
|
1581 * \par Classification |
|
1582 * internal, development |
|
1583 */ |
|
1584 enum psif_epsc_query_op { |
|
1585 /** If initiated from a EPSC_QUERY this operation code will always return zero and report success. |
|
1586 * In case of a intended set request (EPSC_SET) this operation code ignore the request and return success. |
|
1587 */ |
|
1588 EPSC_QUERY_BLANK = 0, |
|
1589 /* Obsolete - use EPSC_QUERY_CAP_VCB_{LO HI} */ |
|
1590 EPSC_QUERY_CAP_VCB = 0x1, |
|
1591 /* Obsolete - use EPSC_QUERY_CAP_PCB_{LO HI} */ |
|
1592 EPSC_QUERY_CAP_PCB = 0x2, |
|
1593 EPSC_QUERY_NUM_UF = 0x3, |
|
1594 EPSC_QUERY_GID_HI = 0x4, |
|
1595 EPSC_QUERY_GID_LO = 0x5, |
|
1596 EPSC_QUERY_P_KEY = 0x6, |
|
1597 EPSC_QUERY_Q_KEY = 0x7, |
|
1598 EPSC_QUERY_UF = 0x8, |
|
1599 EPSC_QUERY_LINK_STATE = 0x9, |
|
1600 EPSC_QUERY_VHCA_STATE = 0xa, |
|
1601 /* Corresponds to register TSU_HOST_INT_CTRL_ADDR */ |
|
1602 EPSC_QUERY_INT_COMMON = 0xb, |
|
1603 /* Corresponds to register TSU_HOST_INT_CHAN_CTRL_0 */ |
|
1604 EPSC_QUERY_INT_CHAN_RATE = 0xc, |
|
1605 /* Corresponds to register TSU_HOST_INT_CHAN_CTRL_1 */ |
|
1606 EPSC_QUERY_INT_CHAN_AUSEC = 0xd, |
|
1607 /* Corresponds to register TSU_HOST_INT_CHAN_CTRL_2 */ |
|
1608 EPSC_QUERY_INT_CHAN_PUSEC = 0xe, |
|
1609 /* Number of VCBs in PCI lo BAR */ |
|
1610 EPSC_QUERY_CAP_VCB_LO = 0xf, |
|
1611 /* Number of VCBs in PCI hi BAR */ |
|
1612 EPSC_QUERY_CAP_VCB_HI = 0x10, |
|
1613 /* Number of PCBs mapped to lo BAR VCBs */ |
|
1614 EPSC_QUERY_CAP_PCB_LO = 0x11, |
|
1615 /* Number of PCBs mapped to hi BAR VCBs */ |
|
1616 EPSC_QUERY_CAP_PCB_HI = 0x12, |
|
1617 /* psif_epsc_query_req.index = IB port number [1 2] */ |
|
1618 EPSC_QUERY_PMA_REDIRECT_QP = 0x13, |
|
1619 /* uptime in seconds */ |
|
1620 EPSC_QUERY_FW_UPTIME = 0x14, |
|
1621 /* date the firmware was programmed in epoch time */ |
|
1622 EPSC_QUERY_FW_PROG_DATE = 0x15, |
|
1623 /* date the firmware was built in epoch time */ |
|
1624 EPSC_QUERY_FW_BUILD_DATE = 0x16, |
|
1625 /* current firmware image number (flash slot) */ |
|
1626 EPSC_QUERY_FW_CURR_IMG = 0x17, |
|
1627 /* oneshot firmware image number (flash slot) */ |
|
1628 EPSC_QUERY_FW_ONESHOT_IMG = 0x18, |
|
1629 /* autostart firmware image number (flash slot) */ |
|
1630 EPSC_QUERY_FW_AUTOSTART_IMG = 0x19, |
|
1631 /* bit field encoding why the FW image was booted */ |
|
1632 EPSC_QUERY_FW_START_CAUSE = 0x1a, |
|
1633 /* firmware version */ |
|
1634 EPSC_QUERY_FW_VERSION = 0x1b, |
|
1635 /* Requester - number of bad response errors. */ |
|
1636 EPSC_QUERY_SQ_NUM_BRE = 0x1c, |
|
1637 /* Requester - number of bad response errors. */ |
|
1638 EPSC_QUERY_NUM_CQOVF = 0x1d, |
|
1639 /* Requester - number of CQEs with status flushed in error. */ |
|
1640 EPSC_QUERY_SQ_NUM_WRFE = 0x1e, |
|
1641 /* Responder - number of CQEs with status flushed in error. */ |
|
1642 EPSC_QUERY_RQ_NUM_WRFE = 0x1f, |
|
1643 /* Responder - number of local access errors. */ |
|
1644 EPSC_QUERY_RQ_NUM_LAE = 0x20, |
|
1645 /* Responder - number of local protection errors. */ |
|
1646 EPSC_QUERY_RQ_NUM_LPE = 0x21, |
|
1647 /* Requester - number of local length errors. */ |
|
1648 EPSC_QUERY_SQ_NUM_LLE = 0x22, |
|
1649 /* Responder - number of local length errors. */ |
|
1650 EPSC_QUERY_RQ_NUM_LLE = 0x23, |
|
1651 /* Requester - number local QP operation error. */ |
|
1652 EPSC_QUERY_SQ_NUM_LQPOE = 0x24, |
|
1653 /* Responder - number local QP operation error. */ |
|
1654 EPSC_QUERY_RQ_NUM_LQPOE = 0x25, |
|
1655 /* Requester - number of NAK-Sequence Error received. */ |
|
1656 EPSC_QUERY_SQ_NUM_OOS = 0x26, |
|
1657 /* Responder - number of NAK-Sequence Error sent. */ |
|
1658 EPSC_QUERY_RQ_NUM_OOS = 0x27, |
|
1659 /* Requester - number of RNR nak retries exceeded errors. */ |
|
1660 EPSC_QUERY_SQ_NUM_RREE = 0x28, |
|
1661 /* Requester - number of transport retries exceeded errors. */ |
|
1662 EPSC_QUERY_SQ_NUM_TREE = 0x29, |
|
1663 /* Requester - number of NAK-Remote Access Error received. */ |
|
1664 EPSC_QUERY_SQ_NUM_ROE = 0x2a, |
|
1665 /* |
|
1666 * Responder - number of NAK-Remote Access Error sent. NAK-Remote Operation |
|
1667 * Error on: 1. Malformed WQE: Responder detected a malformed Receive Queue |
|
1668 * WQE while processing the packet. 2. Remote Operation Error: Responder |
|
1669 * encountered an error, (local to the responder), which prevented it from |
|
1670 * completing the request. |
|
1671 */ |
|
1672 EPSC_QUERY_RQ_NUM_ROE = 0x2b, |
|
1673 /* |
|
1674 * Requester - number of NAK-Remote Access Error received. R_Key Violation: |
|
1675 * Responder detected an invalid R_Key while executing an RDMA Request. |
|
1676 */ |
|
1677 EPSC_QUERY_SQ_NUM_RAE = 0x2c, |
|
1678 /* |
|
1679 * Responder - number of NAK-Remote Access Error sent. R_Key Violation |
|
1680 * Responder detected an R_Key violation while executing an RDMA request. |
|
1681 */ |
|
1682 EPSC_QUERY_RQ_NUM_RAE = 0x2d, |
|
1683 /* |
|
1684 * The number of UD packets silently discarded on the receive queue due to |
|
1685 * lack of receive descriptor. |
|
1686 */ |
|
1687 EPSC_QUERY_RQ_NUM_UDSDPRD = 0x2e, |
|
1688 /* |
|
1689 * The number of UC packets silently discarded on the receive queue due to |
|
1690 * lack of receive descriptor. |
|
1691 */ |
|
1692 EPSC_QUERY_RQ_NUM_UCSDPRD = 0x2f, |
|
1693 /* |
|
1694 * Requester - number of remote invalid request errors NAK-Invalid Request |
|
1695 * on: 1. Unsupported OpCode: Responder detected an unsupported OpCode. 2. |
|
1696 * Unexpected OpCode: Responder detected an error in the sequence of OpCodes, |
|
1697 * such as a missing Last packet. |
|
1698 */ |
|
1699 EPSC_QUERY_SQ_NUM_RIRE = 0x30, |
|
1700 /* |
|
1701 * Responder - number of remote invalid request errors. NAK may or may not be |
|
1702 * sent. 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD |
|
1703 * only): Inbound request OpCode was either reserved, or was for a function |
|
1704 * not supported by thisQP. (E.g. RDMA or ATOMIC on QP not set up for this). |
|
1705 * 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic |
|
1706 * operation. 3. Too many RDMA READ or ATOMIC Requests: There were more |
|
1707 * requests received and not ACKed than allowed for the connection. 4. Out of |
|
1708 * Sequence OpCode, current packet is First or Only: The Responder detected |
|
1709 * an error in the sequence of OpCodes; a missing Last packet. 5. Out of |
|
1710 * Sequence OpCode, current packet is not First or Only: The Responder |
|
1711 * detected an error in the sequence of OpCodes; a missing First packet. 6. |
|
1712 * Local Length Error: Inbound Send request message exceeded the responder's |
|
1713 * available buffer space. 7. Length error: RDMA WRITE request message |
|
1714 * contained too much or too little pay-load data compared to the DMA length |
|
1715 * advertised in the first or only packet. 8. Length error: Payload length |
|
1716 * was not consistent with the opcode: a: only is between 0 and PMTU bytes b: |
|
1717 * (first or middle) equals PMTU bytes c: last is between 1 byte and PMTU |
|
1718 * bytes 9. Length error: Inbound message exceeded the size supported by the |
|
1719 * CA port. |
|
1720 */ |
|
1721 EPSC_QUERY_RQ_NUM_RIRE = 0x31, |
|
1722 /* Requester - the number of RNR Naks received. */ |
|
1723 EPSC_QUERY_SQ_NUM_RNR = 0x32, |
|
1724 /* Responder - the number of RNR Naks sent. */ |
|
1725 EPSC_QUERY_RQ_NUM_RNR = 0x33, |
|
1726 /* twoshot firmware image number (flash slot) */ |
|
1727 EPSC_QUERY_FW_TWOSHOT_IMG = 0x34, |
|
1728 /* firmware type */ |
|
1729 EPSC_QUERY_FW_TYPE = 0x35, |
|
1730 /* firmware size */ |
|
1731 EPSC_QUERY_FW_SIZE = 0x36, |
|
1732 /* firmware slot size (available space for an image) */ |
|
1733 EPSC_QUERY_FW_SLOT_SIZE = 0x37, |
|
1734 /* version of boot loader that has started the application */ |
|
1735 EPSC_QUERY_BL_VERSION = 0x38, |
|
1736 /* boot loader build date in epoch time format */ |
|
1737 EPSC_QUERY_BL_BUILD_DATE = 0x39, |
|
1738 /* only used by EPSC_SET mark a PQP CQ ID as clean (WA bug 3769) */ |
|
1739 EPSC_QUERY_CLEAN_CQ_ID = 0x3a, |
|
1740 /* Number of TSL supported by FW */ |
|
1741 EPSC_QUERY_CAP_TSL_TX = 0x3b, |
|
1742 EPSC_QUERY_CAP_TSL_RX = 0x3c, |
|
1743 /* Reset CBLD Diag counters. Only used by EPSC_SET */ |
|
1744 EPSC_QUERY_RESET_CBLD_DIAG_COUNTERS = 0x3d, |
|
1745 /* Max QP index used since power-on or host reset - to optimize WA for HW bug 3251 */ |
|
1746 EPSC_QUERY_MAX_QP_USED = 0x3e, |
|
1747 /** the UF and QP where modify QP timed out ((uf << 32) | (qp)) */ |
|
1748 EPSC_QUERY_MODQP_TO_SOURCE = 0x3f, |
|
1749 /** the debug register when modify QP timed out */ |
|
1750 EPSC_QUERY_MODQP_TO_DEBUG = 0x40, |
|
1751 /** the bit vector containing the reasons for entering degraded mode */ |
|
1752 EPSC_QUERY_DEGRADED_CAUSE = 0x41, |
|
1753 /** CMPL spin set mode (safe = 1 fast = 0) */ |
|
1754 EPSC_QUERY_SPIN_SET_CONTROL = 0x42, |
|
1755 /** VPD MAC address */ |
|
1756 EPSC_QUERY_VPD_MAC = 0x43, |
|
1757 /** VPD part number */ |
|
1758 EPSC_QUERY_VPD_PART_NUMBER = 0x44, |
|
1759 /** VPD revision */ |
|
1760 EPSC_QUERY_VPD_REVISION = 0x45, |
|
1761 /** VPD serial number (big endian sub-string) - 8 byte offset in query index */ |
|
1762 EPSC_QUERY_VPD_SERIAL_NUMBER = 0x46, |
|
1763 /** VPD manufacturer = = Oracle Corporation - 8 byte offset in query index */ |
|
1764 EPSC_QUERY_VPD_MANUFACTURER = 0x47, |
|
1765 /** VPD product name (big endian sub-string) - 8 byte offset in query index */ |
|
1766 EPSC_QUERY_VPD_PRODUCT_NAME = 0x4b, |
|
1767 /** VPD Base GUID */ |
|
1768 EPSC_QUERY_VPD_BASE_GUID = 0x4e, |
|
1769 /** PSIF TSU SL and QoS mapping for priv QP - port number in query index */ |
|
1770 EPSC_QUERY_MAP_PQP_TO_TSL = 0x48, |
|
1771 /** PSIF TSU SL and QoS mapping for IB SL 0-7 - port number in query index */ |
|
1772 EPSC_QUERY_MAP_SL_TO_TSL_LO = 0x49, |
|
1773 /** PSIF TSU SL and QoS mapping for IB SL 8-15 - port number in query index */ |
|
1774 EPSC_QUERY_MAP_SL_TO_TSL_HI = 0x4a, |
|
1775 /** MMU static configuration of TA_UPPER_TWELVE bits (SPARC only) */ |
|
1776 EPSC_QUERY_TA_UPPER_TWELVE = 0x4c, |
|
1777 /** MMU static configuration of PA_UPPER_TWELVE bits (SPARC only) */ |
|
1778 EPSC_QUERY_PA_UPPER_TWELVE = 0x4d, |
|
1779 /* EOF marker - must be last and highest in this enum type. */ |
|
1780 EPSC_QUERY_LAST = 0x4f, |
|
1781 /* Padding out to required bits allocated */ |
|
1782 PSIF_EPSC_QUERY_OP_FIELD_MAX = 0x7fffffff |
|
1783 }; /* enum psif_epsc_query_op [32 bits] */ |
|
1784 |
|
1785 /** |
|
1786 * Valid values for struct psif_epsc_csr_update::opcode |
|
1787 */ |
|
1788 enum psif_epsc_csr_update_opcode { |
|
1789 EPSC_UPDATE_OP_POLL = 0, |
|
1790 EPSC_UPDATE_OP_START, |
|
1791 EPSC_UPDATE_OP_ERASE, |
|
1792 EPSC_UPDATE_OP_WRITE, |
|
1793 EPSC_UPDATE_OP_READ, |
|
1794 EPSC_UPDATE_OP_STOP, |
|
1795 EPSC_UPDATE_OP_SET, |
|
1796 EPSC_UPDATE_OP_MAX, |
|
1797 /* Padding out to required bits allocated */ |
|
1798 PSIF_EPSC_CSR_UPDATE_OPCODE_FIELD_MAX = 0xffff |
|
1799 }; /* enum psif_epsc_csr_update_opcode [16 bits] */ |
|
1800 |
|
1801 /** |
|
1802 * Flash slot numbers used by e.g. EPSC_QUERY::EPSC_QUERY_FW_CURR_IMG |
|
1803 */ |
|
1804 enum psif_epsc_flash_slot { |
|
1805 EPSC_FLASH_SLOT_INVALID, |
|
1806 EPSC_FLASH_SLOT_EPS_C_IMG_1, |
|
1807 EPSC_FLASH_SLOT_EPS_C_IMG_2, |
|
1808 EPSC_FLASH_SLOT_EPS_A_IMG, |
|
1809 EPSC_FLASH_SLOT_BOOT_IMG, |
|
1810 /* always last */ |
|
1811 EPSC_FLASH_SLOT_COUNT, |
|
1812 /* Padding out to required bits allocated */ |
|
1813 PSIF_EPSC_FLASH_SLOT_FIELD_MAX = 0xffff |
|
1814 }; /* enum psif_epsc_flash_slot [16 bits] */ |
|
1815 |
|
1816 /** |
|
1817 * Valid values for struct psif_epsc_csr_update::u::set |
|
1818 */ |
|
1819 enum psif_epsc_update_set { |
|
1820 EPSC_UPDATE_SET_INVALID, |
|
1821 EPSC_UPDATE_SET_AUTOSTART_IMG, |
|
1822 EPSC_UPDATE_SET_ONESHOT_IMG, |
|
1823 EPSC_UPDATE_SET_TWOSHOT_IMG, |
|
1824 EPSC_UPDATE_SET_IMG_VALID, |
|
1825 /* Padding out to required bits allocated */ |
|
1826 PSIF_EPSC_UPDATE_SET_FIELD_MAX = 0x7fffffff |
|
1827 }; /* enum psif_epsc_update_set [32 bits] */ |
|
1828 |
|
1829 /** |
|
1830 * Opcodes for psif_epsc_csr_uf_ctrl_t::opcode |
|
1831 */ |
|
1832 enum psif_epsc_csr_uf_ctrl_opcode { |
|
1833 EPSC_UF_CTRL_MMU_FLUSH, |
|
1834 EPSC_UF_CTRL_GET_UF_USED_QP, |
|
1835 EPSC_UF_CTRL_CLEAR_UF_USED_QP, |
|
1836 /** For SMP {en dis}able is the flag param a bitvector for which ports to update 0x6 hence indicate P1 and P2. */ |
|
1837 EPSC_UF_CTRL_SMP_ENABLE, |
|
1838 EPSC_UF_CTRL_SMP_DISABLE, |
|
1839 /** For Vlink {dis }connect is the flag param a bitvector for which ports to update 0x6 hence indicate P1 and P2. */ |
|
1840 EPSC_UF_CTRL_VLINK_CONNECT, |
|
1841 EPSC_UF_CTRL_VLINK_DISCONNECT, |
|
1842 /** Retrieve the highest QP number used by the given UF */ |
|
1843 EPSC_UF_CTRL_GET_HIGHEST_QP_IDX, |
|
1844 /** Reset the highest QP number cache for the given UF */ |
|
1845 EPSC_UF_CTRL_RESET_HIGHEST_QP_IDX, |
|
1846 /* Padding out to required bits allocated */ |
|
1847 PSIF_EPSC_CSR_UF_CTRL_OPCODE_FIELD_MAX = 0x7fffffff |
|
1848 }; /* enum psif_epsc_csr_uf_ctrl_opcode [32 bits] */ |
|
1849 |
|
1850 /** |
|
1851 * \brief Host to VIMMA operation codes |
|
1852 * \details |
|
1853 * These operation codes are sent in the |
|
1854 * \ref psif_epsc_csr_vimma_ctrl_t::opcode member |
|
1855 * from the host to the mailbox thread in EPS-C in order to specify the |
|
1856 * VIMMA request. In addition the operation |
|
1857 * codes are used as a selector for the |
|
1858 * \ref psif_epsc_csr_vimma_ctrl_t::u member of |
|
1859 * psif_epsc_csr_vimma_ctrl_t in order to specify a particular |
|
1860 * set of arguments if the request requires specific arguments. |
|
1861 * \par |
|
1862 * User of the VIMMA operation codes is the "PSIF SRIOV control API" library |
|
1863 * running in Dom0 in user space. This library uses libsif to access the |
|
1864 * mailbox. Requests are formed by using the VIMMA operation codes. Response |
|
1865 * status is always delivered "inline" as return codes when the libsif API |
|
1866 * returns from the mailbox operations. |
|
1867 * Additional information retrieval can either be delivered "inline" as long |
|
1868 * as space permits inside the mailbox response, OR responses |
|
1869 * can also be extended by DMA-ing back response structures to pinned memory |
|
1870 * in the library. |
|
1871 * The DMA memory is prepared by the library before executing an opcode |
|
1872 * that requires DMA for requested data. |
|
1873 * \par |
|
1874 * INLINE responses: Response data from VIMMA operation codes are delivered |
|
1875 * via libsif to the "PSIF SRIOV control API" as two u64 |
|
1876 * parameters: "data" and "info". |
|
1877 * These are carried by \ref psif_epsc_csr_rsp_t as part of mailbox response. |
|
1878 * The encoding of the "data" and "info" responses depend on the VIMMA operation |
|
1879 * code. For code using libsif library, the two u64 response codes "data" |
|
1880 * and "info" is overlayed with the union |
|
1881 * \ref psif_epsc_csr_vimma_ctrl_resp_inline_u, |
|
1882 * and by using the opcode as a selector for the union members, the correct info |
|
1883 * from the operation will be found. |
|
1884 * \par |
|
1885 * DMA responses: The requested data using DMA is delivered back to caller in |
|
1886 * pinned memory of appropriate size. A pinned memory block of the maximum sized |
|
1887 * response structure will do, and this can be obtained as |
|
1888 * sizeof(psif_epsc_csr_vimma_ctrl_resp_dma_u) + appropriate extension for |
|
1889 * for some variable arrays if those extend outside of |
|
1890 * psif_epsc_csr_vimma_ctrl_resp_dma_uend of some union members. |
|
1891 * The opcode just executed will be the selector for the union members. |
|
1892 * |
|
1893 * \par Width |
|
1894 * 32 bit |
|
1895 * \par Used in |
|
1896 * psif_epsc_csr_vimma_ctrl_t |
|
1897 * \par Classification |
|
1898 * external |
|
1899 * |
|
1900 * \note |
|
1901 * - In order to provide backward compatibility new codes must be added |
|
1902 * at the end of the enum. Deprecated codes can not be removed, but will instead |
|
1903 * be responded to with error codes if not supported anymore. |
|
1904 */ |
|
1905 enum psif_epsc_vimma_ctrl_opcode { |
|
1906 /* no DMA.*/ |
|
1907 EPSC_VIMMA_CTRL_GET_VER_AND_COMPAT, |
|
1908 /* DMA for resp. */ |
|
1909 EPSC_VIMMA_CTRL_GET_MISC_INFO, |
|
1910 /* DMA for resp. */ |
|
1911 EPSC_VIMMA_CTRL_GET_GUIDS, |
|
1912 /* DMA for resp. */ |
|
1913 EPSC_VIMMA_CTRL_GET_REG_INFO, |
|
1914 /* DMA for resp. */ |
|
1915 EPSC_VIMMA_CTRL_GET_VHCA_STATS, |
|
1916 /* no DMA. */ |
|
1917 EPSC_VIMMA_CTRL_SET_VFP_VHCA_REGISTER, |
|
1918 /* no DMA. */ |
|
1919 EPSC_VIMMA_CTRL_SET_VFP_VHCA_DEREGISTER, |
|
1920 /* no DMA or DMA if multiple UFs */ |
|
1921 EPSC_VIMMA_CTRL_SET_ADMIN_MODE, |
|
1922 /* Padding out to required bits allocated */ |
|
1923 PSIF_EPSC_VIMMA_CTRL_OPCODE_FIELD_MAX = 0x7fffffff |
|
1924 }; /* enum psif_epsc_vimma_ctrl_opcode [32 bits] */ |
|
1925 |
|
1926 |
|
1927 enum psif_epsc_vimma_admmode { |
|
1928 EPSC_VIMMA_CTRL_IB_ADM_MODE_SM_STANDARD, |
|
1929 /* VFP used as short for VM Fabric Profile */ |
|
1930 EPSC_VIMMA_CTRL_IB_ADM_MODE_VM_FABRIC_PROFILE, |
|
1931 /* Padding out to required bits allocated */ |
|
1932 PSIF_EPSC_VIMMA_ADMMODE_FIELD_MAX = 0xffff |
|
1933 }; /* enum psif_epsc_vimma_admmode [16 bits] */ |
|
1934 |
|
1935 /** |
|
1936 * For response structure to EPSC_PMA_COUNTERS Op. |
|
1937 * Common PMA counters for TSU and IBU layers. |
|
1938 */ |
|
1939 enum psif_epsc_csr_pma_counters_enum { |
|
1940 /** Regular counters - IB Spec chapter 16.1.3.5 */ |
|
1941 EPSC_PMA_SYMBOL_ERR_CNTR = 0, |
|
1942 EPSC_PMA_LINK_ERR_RECOVERY_CNTR, |
|
1943 EPSC_PMA_LINK_DOWNED_CNTR, |
|
1944 EPSC_PMA_PORT_RCV_ERR, |
|
1945 EPSC_PMA_PORT_RCV_REMOTE_PHYSICAL_ERR, |
|
1946 EPSC_PMA_PORT_RCV_SWITCH_RELAY_ERR, |
|
1947 EPSC_PMA_PORT_XMIT_DISCARD, |
|
1948 EPSC_PMA_PORT_XMIT_CONSTRAINT_ERR, |
|
1949 EPSC_PMA_PORT_RCV_CONSTRAINT_ERR, |
|
1950 EPSC_PMA_LOCAL_LINK_INTEGRITY_ERR, |
|
1951 EPSC_PMA_EXCESS_BUFF_OVERRUN_ERR, |
|
1952 EPSC_PMA_VL15_DROPPED, |
|
1953 /** Extended counters if Extended Width supported Regular otherwise */ |
|
1954 EPSC_PMA_PORT_XMIT_DATA, |
|
1955 EPSC_PMA_PORT_RCV_DATA, |
|
1956 EPSC_PMA_PORT_XMIT_PKTS, |
|
1957 EPSC_PMA_PORT_RCV_PKTS, |
|
1958 /** |
|
1959 * If ClassPortInfo:CapabilityMask.PortCountersXmitWaitSupported |
|
1960 * set to 1. IB Spec chapter 16.1.3.5 |
|
1961 */ |
|
1962 EPSC_PMA_PORT_XMIT_WAIT, |
|
1963 /** Strictly Extended counters - IB Spec Chapter 16.1.4.11 */ |
|
1964 EPSC_PMA_PORT_UNICAST_XMIT_PKTS, |
|
1965 EPSC_PMA_PORT_UNICAST_RCV_PKTS, |
|
1966 EPSC_PMA_PORT_MULTICAST_XMIT_PKTS, |
|
1967 EPSC_PMA_PORT_MULTICAST_RCV_PKTS, |
|
1968 /* IB Spec Chapter 16.1.4.1 */ |
|
1969 EPSC_PMA_PORT_LOCAL_PHYSICAL_ERR, |
|
1970 /* Keep this in End */ |
|
1971 EPSC_PMA_COUNTERS_TOTAL, |
|
1972 /* Padding out to required bits allocated */ |
|
1973 PSIF_EPSC_CSR_PMA_COUNTERS_ENUM_FIELD_MAX = 0x7fffffff |
|
1974 }; /* enum psif_epsc_csr_pma_counters_enum [32 bits] */ |
|
1975 |
|
1976 /** |
|
1977 * \brief PSIF atomic op requester config values. |
|
1978 * \details |
|
1979 * \par Width |
|
1980 * 2 bit |
|
1981 * \par Used in |
|
1982 * psif_epsc_csr_config member `atomic_support` |
|
1983 * \par Classification |
|
1984 * driver |
|
1985 */ |
|
1986 enum psif_epsc_csr_atomic_op { |
|
1987 /** PSIF requests atomic operations for IB and SQS. */ |
|
1988 PSIF_PCIE_ATOMIC_OP_BOTH = 0, |
|
1989 /** PSIF requests atomic operations for IB. */ |
|
1990 PSIF_PCIE_ATOMIC_OP_IB, |
|
1991 /** PSIF requests atomic operations for SQS. */ |
|
1992 PSIF_PCIE_ATOMIC_OP_SQS, |
|
1993 /** PSIF doesn't request atomic operations. */ |
|
1994 PSIF_PCIE_ATOMIC_OP_NONE |
|
1995 }; /* enum psif_epsc_csr_atomic_op [ 2 bits] */ |
|
1996 |
|
1997 /* |
|
1998 * Completion notification states. Could take any of these values: |
|
1999 * PSIF_CQ_UNARMED PSIF_CQ_ARMED_SE PSIF_CQ_ARMED_ALL PSIF_CQ_TRIGGERED |
|
2000 */ |
|
2001 enum psif_cq_state { |
|
2002 PSIF_CQ_UNARMED, |
|
2003 PSIF_CQ_ARMED_SE, |
|
2004 PSIF_CQ_ARMED_ALL, |
|
2005 PSIF_CQ_TRIGGERED |
|
2006 }; /* enum psif_cq_state [ 2 bits] */ |
|
2007 |
|
2008 /* |
|
2009 * This is an indication if the RSS hash was generated with port inputs or |
|
2010 * not. |
|
2011 */ |
|
2012 enum psif_rss_hash_source { |
|
2013 RSS_WITHOUT_PORT, |
|
2014 RSS_WITH_PORT |
|
2015 }; /* enum psif_rss_hash_source [ 1 bits] */ |
|
2016 |
|
2017 #if defined (HOST_LITTLE_ENDIAN) |
|
2018 #include "psif_hw_data_le.h" |
|
2019 #elif defined (HOST_BIG_ENDIAN) |
|
2020 #include "psif_hw_data_be.h" |
|
2021 #else |
|
2022 #error "Could not determine byte order in psif_hw_data.h !?" |
|
2023 #endif |
|
2024 |
|
2025 |
|
2026 #ifdef __cplusplus |
|
2027 } |
|
2028 #endif |
|
2029 |
|
2030 |
|
2031 #endif /* _PSIF_HW_DATA_H */ |