|
1 /* |
|
2 * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved. |
|
3 */ |
|
4 |
|
5 /* |
|
6 * Redistribution and use in source and binary forms, with or without modification, |
|
7 * are permitted provided that the following conditions are met: |
|
8 * |
|
9 * 1. Redistributions of source code must retain the above copyright notice, |
|
10 * this list of conditions and the following disclaimer. |
|
11 * |
|
12 * 2. Redistributions in binary form must reproduce the above copyright notice, |
|
13 * this list of conditions and the following disclaimer in the documentation |
|
14 * and/or other materials provided with the distribution. |
|
15 * |
|
16 * 3. Neither the name of the copyright holder nor the names of its contributors |
|
17 * may be used to endorse or promote products derived from this software without |
|
18 * specific prior written permission. |
|
19 * |
|
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
|
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|
22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|
23 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
|
24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
|
25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
|
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
|
27 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
|
28 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
|
29 * OF THE POSSIBILITY OF SUCH DAMAGE. |
|
30 */ |
|
31 |
|
32 #ifndef _PSIF_HW_MACRO_H |
|
33 #define _PSIF_HW_MACRO_H |
|
34 |
|
35 #ifdef __cplusplus |
|
36 extern "C" { |
|
37 #endif |
|
38 |
|
39 #include "psif_api.h" |
|
40 |
|
41 #include "psif_endian.h" |
|
42 #if !defined(__KERNEL__) |
|
43 #include "os_header.h" |
|
44 #endif |
|
45 |
|
46 |
|
47 /* |
|
48 * PSIF_WR_INVALIDATE_LKEY: key to invalidate/flush from the DMA VT cache. |
|
49 * PSIF_WR_INVALIDATE_RKEY: key to invalidate/flush from the DMA VT cache. |
|
50 * PSIF_WR_INVALIDATE_BOTH_KEYS: key to invalidate/flush from the DMA VT |
|
51 * cache. PSIF_WR_INVALIDATE_TLB: this is the address vector to invalidate in |
|
52 * the TLB. |
|
53 */ |
|
54 #define PSIF_WR_SU_KEY_OFFSET 2 |
|
55 #define PSIF_WR_SU_2_KEY_SHIFT 32 |
|
56 #define PSIF_WR_SU_2_KEY_BITS 32 |
|
57 #define PSIF_WR_SU_2_KEY_MASK 0xffffffff00000000ull |
|
58 |
|
59 /* |
|
60 * Send queue sequence number. Used to map request to a particular work |
|
61 * request in the send queue. |
|
62 */ |
|
63 #define PSIF_WR_SQ_SEQ_OFFSET 0 |
|
64 #define PSIF_WR_SQ_SEQ_SHIFT 0 |
|
65 #define PSIF_WR_SQ_SEQ_BITS 16 |
|
66 #define PSIF_WR_SQ_SEQ_MASK 0x000000000000ffffull |
|
67 |
|
68 /* |
|
69 * QP sending this request. XXX: Should name be own_qp_num as defined in QP |
|
70 * state? |
|
71 */ |
|
72 #define PSIF_WR_LOCAL_QP_OFFSET 0 |
|
73 #define PSIF_WR_LOCAL_QP_SHIFT 32 |
|
74 #define PSIF_WR_LOCAL_QP_BITS 24 |
|
75 #define PSIF_WR_LOCAL_QP_MASK 0x00ffffff00000000ull |
|
76 |
|
77 /* Completion notification identifier. */ |
|
78 #define PSIF_WR_COMPLETION_OFFSET 1 |
|
79 #define PSIF_WR_1_COMPLETION_BIT_POSITION 31 |
|
80 #define PSIF_WR_1_COMPLETION_BIT 0x0000000080000000ull |
|
81 |
|
82 /* |
|
83 * Checksum used for data protection and consistency between work request and |
|
84 * QP state. |
|
85 */ |
|
86 #define PSIF_WR_CHECKSUM_OFFSET 2 |
|
87 #define PSIF_WR_2_CHECKSUM_SHIFT 32 |
|
88 #define PSIF_WR_2_CHECKSUM_BITS 32 |
|
89 #define PSIF_WR_2_CHECKSUM_MASK 0xffffffff00000000ull |
|
90 |
|
91 /* |
|
92 * Index to where elements are added to the send queue by SW. SW is |
|
93 * responsibel for keeping track of how many entries there are in the send |
|
94 * queue. I.e. SW needs to keep track of the head_index so it doesn't |
|
95 * overwrite entries in the send queue which is not yet completed. |
|
96 */ |
|
97 #define PSIF_SQ_SW_TAIL_INDX_OFFSET 0 |
|
98 #define PSIF_SQ_SW_TAIL_INDX_SHIFT 32 |
|
99 #define PSIF_SQ_SW_TAIL_INDX_BITS 16 |
|
100 #define PSIF_SQ_SW_TAIL_INDX_MASK 0x0000ffff00000000ull |
|
101 |
|
102 /* |
|
103 * Send queue sequence number used by the SQS to maintain ordering and keep |
|
104 * track of where which send queue elements to fetch. This field is not in |
|
105 * sync with the field in qp_t. This number is typically a little bit before |
|
106 * the number in the qp_t as SQS has to fetch the elements from host memory. |
|
107 * This is also used as tail_index when checking if there are more elements |
|
108 * in the send queue. |
|
109 */ |
|
110 #define PSIF_SQ_HW_LAST_SEQ_OFFSET 0 |
|
111 #define PSIF_SQ_HW_LAST_SEQ_SHIFT 16 |
|
112 #define PSIF_SQ_HW_LAST_SEQ_BITS 16 |
|
113 #define PSIF_SQ_HW_LAST_SEQ_MASK 0x00000000ffff0000ull |
|
114 |
|
115 /* QP and UF to be processed next. */ |
|
116 #define PSIF_SQ_HW_SQ_NEXT_OFFSET 0 |
|
117 #define PSIF_SQ_HW_SQ_NEXT_SHIFT 32 |
|
118 #define PSIF_SQ_HW_SQ_NEXT_BITS 32 |
|
119 #define PSIF_SQ_HW_SQ_NEXT_MASK 0xffffffff00000000ull |
|
120 |
|
121 /* |
|
122 * This bit is set through the doorbell. SW should check this bit plus |
|
123 * psif_next = null to ensure SW can own the SQ descriptor. |
|
124 */ |
|
125 #define PSIF_SQ_HW_DESTROYED_OFFSET 1 |
|
126 #define PSIF_SQ_HW_1_DESTROYED_BIT_POSITION 27 |
|
127 #define PSIF_SQ_HW_1_DESTROYED_BIT 0x0000000008000000ull |
|
128 |
|
129 /* Software modified index pointing to the tail reecive entry in host memory. */ |
|
130 #define PSIF_RQ_SW_TAIL_INDX_OFFSET 0 |
|
131 #define PSIF_RQ_SW_TAIL_INDX_SHIFT 32 |
|
132 #define PSIF_RQ_SW_TAIL_INDX_BITS 14 |
|
133 #define PSIF_RQ_SW_TAIL_INDX_MASK 0x00003fff00000000ull |
|
134 |
|
135 /* |
|
136 * Hardware modified index pointing to the head of the receive queue. TSU is |
|
137 * using this to find the address of the receive queue entry. |
|
138 */ |
|
139 #define PSIF_RQ_HW_HEAD_INDX_OFFSET 0 |
|
140 #define PSIF_RQ_HW_HEAD_INDX_SHIFT 14 |
|
141 #define PSIF_RQ_HW_HEAD_INDX_BITS 14 |
|
142 #define PSIF_RQ_HW_HEAD_INDX_MASK 0x000000000fffc000ull |
|
143 |
|
144 /* The desciptor is valid. */ |
|
145 #define PSIF_RQ_HW_VALID_OFFSET 3 |
|
146 #define PSIF_RQ_HW_3_VALID_BIT_POSITION 55 |
|
147 #define PSIF_RQ_HW_3_VALID_BIT 0x0080000000000000ull |
|
148 |
|
149 /* |
|
150 * Receive queue entry ID. This is added to the receive completion using this |
|
151 * receive queue entry. |
|
152 */ |
|
153 #define PSIF_RQ_ENTRY_RQE_ID_OFFSET 0 |
|
154 #define PSIF_RQ_ENTRY_RQE_ID_SHIFT 0 |
|
155 #define PSIF_RQ_ENTRY_RQE_ID_BITS 64 |
|
156 #define PSIF_RQ_ENTRY_RQE_ID_MASK 0xffffffffffffffffull |
|
157 |
|
158 /* |
|
159 * This retry tag is the one used by tsu_rqs and added to the packets sent to |
|
160 * tsu_dma. It is the responsibility of tsu_rqs to update this retry tag |
|
161 * whenever the sq_sequence_number in QP state is equal to the one in the |
|
162 * request. |
|
163 */ |
|
164 #define PSIF_QP_CORE_RETRY_TAG_COMMITTED_OFFSET 0 |
|
165 #define PSIF_QP_CORE_RETRY_TAG_COMMITTED_SHIFT 0 |
|
166 #define PSIF_QP_CORE_RETRY_TAG_COMMITTED_BITS 3 |
|
167 #define PSIF_QP_CORE_RETRY_TAG_COMMITTED_MASK 0x0000000000000007ull |
|
168 |
|
169 /* |
|
170 * This retry tag is updated by the error block when an error occur. If |
|
171 * tsu_rqs reads this retry tag and it is different than the |
|
172 * retry_tag_comitted, tsu_rqs must update retry_tag_comitted to the value of |
|
173 * retry_tag_err when the sq_sequence_number indicates this is the valid |
|
174 * request. The sq_sequence_number has been updated by tsu_err at the same |
|
175 * time the retry_tag_err is updated. |
|
176 */ |
|
177 #define PSIF_QP_CORE_RETRY_TAG_ERR_OFFSET 0 |
|
178 #define PSIF_QP_CORE_RETRY_TAG_ERR_SHIFT 3 |
|
179 #define PSIF_QP_CORE_RETRY_TAG_ERR_BITS 3 |
|
180 #define PSIF_QP_CORE_RETRY_TAG_ERR_MASK 0x0000000000000038ull |
|
181 |
|
182 /* |
|
183 * Error retry counter initial value. Read by tsu_dma and used by tsu_cmpl to |
|
184 * calculate exp_backoff etc.. |
|
185 */ |
|
186 #define PSIF_QP_CORE_ERROR_RETRY_INIT_OFFSET 0 |
|
187 #define PSIF_QP_CORE_ERROR_RETRY_INIT_SHIFT 32 |
|
188 #define PSIF_QP_CORE_ERROR_RETRY_INIT_BITS 3 |
|
189 #define PSIF_QP_CORE_ERROR_RETRY_INIT_MASK 0x0000000700000000ull |
|
190 |
|
191 /* |
|
192 * Retry counter associated with retries to received NAK or implied NAK. If |
|
193 * it expires, a path migration will be attempted if it is armed, or the QP |
|
194 * will go to error state. Read by tsu_dma and used by tsu_cmpl. |
|
195 */ |
|
196 #define PSIF_QP_CORE_ERROR_RETRY_COUNT_OFFSET 0 |
|
197 #define PSIF_QP_CORE_ERROR_RETRY_COUNT_SHIFT 35 |
|
198 #define PSIF_QP_CORE_ERROR_RETRY_COUNT_BITS 3 |
|
199 #define PSIF_QP_CORE_ERROR_RETRY_COUNT_MASK 0x0000003800000000ull |
|
200 |
|
201 /* A hit in the set locally spun out of tsu_cmpl is found. */ |
|
202 #define PSIF_QP_CORE_SPIN_HIT_OFFSET 0 |
|
203 #define PSIF_QP_CORE_SPIN_HIT_BIT_POSITION 39 |
|
204 #define PSIF_QP_CORE_SPIN_HIT_BIT 0x0000008000000000ull |
|
205 |
|
206 /* |
|
207 * Minium RNR NAK timeout. This is added to RNR NAK packets and the requester |
|
208 * receiving the RNR NAK must wait until the timer has expired before the |
|
209 * retry is sent. |
|
210 */ |
|
211 #define PSIF_QP_CORE_MIN_RNR_NAK_TIME_OFFSET 1 |
|
212 #define PSIF_QP_CORE_1_MIN_RNR_NAK_TIME_SHIFT 0 |
|
213 #define PSIF_QP_CORE_1_MIN_RNR_NAK_TIME_BITS 5 |
|
214 #define PSIF_QP_CORE_1_MIN_RNR_NAK_TIME_MASK 0x000000000000001full |
|
215 |
|
216 /* QP State for this QP. */ |
|
217 #define PSIF_QP_CORE_STATE_OFFSET 1 |
|
218 #define PSIF_QP_CORE_1_STATE_SHIFT 5 |
|
219 #define PSIF_QP_CORE_1_STATE_BITS 3 |
|
220 #define PSIF_QP_CORE_1_STATE_MASK 0x00000000000000e0ull |
|
221 |
|
222 /* QP number for the remote node. */ |
|
223 #define PSIF_QP_CORE_REMOTE_QP_OFFSET 1 |
|
224 #define PSIF_QP_CORE_1_REMOTE_QP_SHIFT 8 |
|
225 #define PSIF_QP_CORE_1_REMOTE_QP_BITS 24 |
|
226 #define PSIF_QP_CORE_1_REMOTE_QP_MASK 0x00000000ffffff00ull |
|
227 |
|
228 #define PSIF_QP_CORE_RETRY_SQ_SEQ_OFFSET 2 |
|
229 #define PSIF_QP_CORE_2_RETRY_SQ_SEQ_SHIFT 32 |
|
230 #define PSIF_QP_CORE_2_RETRY_SQ_SEQ_BITS 16 |
|
231 #define PSIF_QP_CORE_2_RETRY_SQ_SEQ_MASK 0x0000ffff00000000ull |
|
232 |
|
233 #define PSIF_QP_CORE_SQ_SEQ_OFFSET 2 |
|
234 #define PSIF_QP_CORE_2_SQ_SEQ_SHIFT 48 |
|
235 #define PSIF_QP_CORE_2_SQ_SEQ_BITS 16 |
|
236 #define PSIF_QP_CORE_2_SQ_SEQ_MASK 0xffff000000000000ull |
|
237 |
|
238 /* |
|
239 * Magic number used to verify use of QP state. This is done by calculating a |
|
240 * checksum of the work request incorporating the magic number. This checksum |
|
241 * is checked against the checksum in the work request. |
|
242 */ |
|
243 #define PSIF_QP_CORE_MAGIC_OFFSET 3 |
|
244 #define PSIF_QP_CORE_3_MAGIC_SHIFT 0 |
|
245 #define PSIF_QP_CORE_3_MAGIC_BITS 32 |
|
246 #define PSIF_QP_CORE_3_MAGIC_MASK 0x00000000ffffffffull |
|
247 |
|
248 /* |
|
249 * Q-Key received in incoming IB packet is checked towards this Q-Key. Q-Key |
|
250 * used on transmit if top bit of Q-Key in WR is set. |
|
251 */ |
|
252 #define PSIF_QP_CORE_QKEY_OFFSET 4 |
|
253 #define PSIF_QP_CORE_4_QKEY_SHIFT 0 |
|
254 #define PSIF_QP_CORE_4_QKEY_BITS 32 |
|
255 #define PSIF_QP_CORE_4_QKEY_MASK 0x00000000ffffffffull |
|
256 |
|
257 /* |
|
258 * Sequence number of the last ACK received. Read and written by tsu_cmpl. |
|
259 * Used to verify that the received response packet is a valid response. |
|
260 */ |
|
261 #define PSIF_QP_CORE_LAST_ACKED_PSN_OFFSET 4 |
|
262 #define PSIF_QP_CORE_4_LAST_ACKED_PSN_SHIFT 40 |
|
263 #define PSIF_QP_CORE_4_LAST_ACKED_PSN_BITS 24 |
|
264 #define PSIF_QP_CORE_4_LAST_ACKED_PSN_MASK 0xffffff0000000000ull |
|
265 |
|
266 /* Index to scatter element of in progress SEND. */ |
|
267 #define PSIF_QP_CORE_SCATTER_INDX_OFFSET 5 |
|
268 #define PSIF_QP_CORE_5_SCATTER_INDX_SHIFT 32 |
|
269 #define PSIF_QP_CORE_5_SCATTER_INDX_BITS 5 |
|
270 #define PSIF_QP_CORE_5_SCATTER_INDX_MASK 0x0000001f00000000ull |
|
271 |
|
272 /* |
|
273 * Expected packet sequence number: Sequence number on next expected packet. |
|
274 */ |
|
275 #define PSIF_QP_CORE_EXPECTED_PSN_OFFSET 5 |
|
276 #define PSIF_QP_CORE_5_EXPECTED_PSN_SHIFT 40 |
|
277 #define PSIF_QP_CORE_5_EXPECTED_PSN_BITS 24 |
|
278 #define PSIF_QP_CORE_5_EXPECTED_PSN_MASK 0xffffff0000000000ull |
|
279 |
|
280 /* |
|
281 * TSU quality of service level. Can take values indicating low latency and |
|
282 * high throughput. This is equivalent to high/low BAR when writing doorbells |
|
283 * to PSIF. The qosl bit in the doorbell request must match this bit in the |
|
284 * QP state, otherwise the QP must be put in error. This check only applies |
|
285 * to tsu_rqs. |
|
286 */ |
|
287 #define PSIF_QP_CORE_QOSL_OFFSET 6 |
|
288 #define PSIF_QP_CORE_6_QOSL_BIT_POSITION 49 |
|
289 #define PSIF_QP_CORE_6_QOSL_BIT 0x0002000000000000ull |
|
290 |
|
291 /* |
|
292 * Migration state (migrated, re-arm and armed). Since path migration is |
|
293 * handled by tsu_qps, this is controlled by tsu_qps. XXX: Should error |
|
294 * handler also be able to change the path? |
|
295 */ |
|
296 #define PSIF_QP_CORE_MSTATE_OFFSET 6 |
|
297 #define PSIF_QP_CORE_6_MSTATE_SHIFT 50 |
|
298 #define PSIF_QP_CORE_6_MSTATE_BITS 2 |
|
299 #define PSIF_QP_CORE_6_MSTATE_MASK 0x000c000000000000ull |
|
300 |
|
301 /* This is an IB over IB QP. */ |
|
302 #define PSIF_QP_CORE_IPOIB_ENABLE_OFFSET 6 |
|
303 #define PSIF_QP_CORE_6_IPOIB_ENABLE_BIT_POSITION 53 |
|
304 #define PSIF_QP_CORE_6_IPOIB_ENABLE_BIT 0x0020000000000000ull |
|
305 |
|
306 /* IB defined capability enable for receiving Atomic operations. */ |
|
307 #define PSIF_QP_CORE_ATOMIC_ENABLE_OFFSET 6 |
|
308 #define PSIF_QP_CORE_6_ATOMIC_ENABLE_BIT_POSITION 61 |
|
309 #define PSIF_QP_CORE_6_ATOMIC_ENABLE_BIT 0x2000000000000000ull |
|
310 |
|
311 /* IB defined capability enable for receiving RDMA WR. */ |
|
312 #define PSIF_QP_CORE_RDMA_WR_ENABLE_OFFSET 6 |
|
313 #define PSIF_QP_CORE_6_RDMA_WR_ENABLE_BIT_POSITION 62 |
|
314 #define PSIF_QP_CORE_6_RDMA_WR_ENABLE_BIT 0x4000000000000000ull |
|
315 |
|
316 /* IB defined capability enable for receiving RDMA RD. */ |
|
317 #define PSIF_QP_CORE_RDMA_RD_ENABLE_OFFSET 6 |
|
318 #define PSIF_QP_CORE_6_RDMA_RD_ENABLE_BIT_POSITION 63 |
|
319 #define PSIF_QP_CORE_6_RDMA_RD_ENABLE_BIT 0x8000000000000000ull |
|
320 |
|
321 /* |
|
322 * Transmit packet sequence number. Read and updated by tsu_dma before |
|
323 * sending packets to tsu_ibpb and tsu_cmpl. |
|
324 */ |
|
325 #define PSIF_QP_CORE_XMIT_PSN_OFFSET 7 |
|
326 #define PSIF_QP_CORE_7_XMIT_PSN_SHIFT 0 |
|
327 #define PSIF_QP_CORE_7_XMIT_PSN_BITS 24 |
|
328 #define PSIF_QP_CORE_7_XMIT_PSN_MASK 0x0000000000ffffffull |
|
329 |
|
330 /* |
|
331 * TSU Service Level used to decide the TSU VL for requests associated with |
|
332 * this QP. |
|
333 */ |
|
334 #define PSIF_QP_CORE_TSL_OFFSET 7 |
|
335 #define PSIF_QP_CORE_7_TSL_SHIFT 55 |
|
336 #define PSIF_QP_CORE_7_TSL_BITS 4 |
|
337 #define PSIF_QP_CORE_7_TSL_MASK 0x0780000000000000ull |
|
338 |
|
339 /* |
|
340 * Maximum number of outstanding read or atomic requests allowed by the |
|
341 * remote HCA. Initialized by software. |
|
342 */ |
|
343 #define PSIF_QP_CORE_MAX_OUTSTANDING_OFFSET 7 |
|
344 #define PSIF_QP_CORE_7_MAX_OUTSTANDING_SHIFT 59 |
|
345 #define PSIF_QP_CORE_7_MAX_OUTSTANDING_BITS 5 |
|
346 #define PSIF_QP_CORE_7_MAX_OUTSTANDING_MASK 0xf800000000000000ull |
|
347 |
|
348 /* Send Queue RNR retry count initialization value. */ |
|
349 #define PSIF_QP_CORE_RNR_RETRY_INIT_OFFSET 8 |
|
350 #define PSIF_QP_CORE_8_RNR_RETRY_INIT_SHIFT 32 |
|
351 #define PSIF_QP_CORE_8_RNR_RETRY_INIT_BITS 3 |
|
352 #define PSIF_QP_CORE_8_RNR_RETRY_INIT_MASK 0x0000000700000000ull |
|
353 |
|
354 /* |
|
355 * Retry counter associated with RNR NAK retries. If it expires, a path |
|
356 * migration will be attempted if it is armed, or the QP will go to error |
|
357 * state. |
|
358 */ |
|
359 #define PSIF_QP_CORE_RNR_RETRY_COUNT_OFFSET 8 |
|
360 #define PSIF_QP_CORE_8_RNR_RETRY_COUNT_SHIFT 35 |
|
361 #define PSIF_QP_CORE_8_RNR_RETRY_COUNT_BITS 3 |
|
362 #define PSIF_QP_CORE_8_RNR_RETRY_COUNT_MASK 0x0000003800000000ull |
|
363 |
|
364 /* |
|
365 * When set, RQS should only check that the orig_checksum is equal to magic |
|
366 * number. When not set, RQS should perform the checksum check towards the |
|
367 * checksum in the psif_wr. |
|
368 */ |
|
369 #define PSIF_QP_CORE_NO_CHECKSUM_OFFSET 8 |
|
370 #define PSIF_QP_CORE_8_NO_CHECKSUM_BIT_POSITION 39 |
|
371 #define PSIF_QP_CORE_8_NO_CHECKSUM_BIT 0x0000008000000000ull |
|
372 |
|
373 /* |
|
374 * Transport type of the QP (RC, UC, UD, XRC, MANSP1). MANSP1 is set for |
|
375 * privileged QPs. |
|
376 */ |
|
377 #define PSIF_QP_CORE_TRANSPORT_TYPE_OFFSET 9 |
|
378 #define PSIF_QP_CORE_9_TRANSPORT_TYPE_SHIFT 0 |
|
379 #define PSIF_QP_CORE_9_TRANSPORT_TYPE_BITS 3 |
|
380 #define PSIF_QP_CORE_9_TRANSPORT_TYPE_MASK 0x0000000000000007ull |
|
381 |
|
382 /* |
|
383 * Number of bytes received of in progress RDMA Write or SEND. The data |
|
384 * received for SENDs and RDMA WR w/Imm are needed for completions. This |
|
385 * should be added to the msg_length. |
|
386 */ |
|
387 #define PSIF_QP_CORE_BYTES_RECEIVED_OFFSET 9 |
|
388 #define PSIF_QP_CORE_9_BYTES_RECEIVED_SHIFT 32 |
|
389 #define PSIF_QP_CORE_9_BYTES_RECEIVED_BITS 32 |
|
390 #define PSIF_QP_CORE_9_BYTES_RECEIVED_MASK 0xffffffff00000000ull |
|
391 |
|
392 /* This QP is running IP over IB. */ |
|
393 #define PSIF_QP_CORE_IPOIB_OFFSET 10 |
|
394 #define PSIF_QP_CORE_10_IPOIB_BIT_POSITION 5 |
|
395 #define PSIF_QP_CORE_10_IPOIB_BIT 0x0000000000000020ull |
|
396 |
|
397 /* |
|
398 * Combined 'Last Received MSN' and 'Last Outstanding MSN', used to maintain |
|
399 * 'spin set floor' and indicate 'all retries completed', respectively. |
|
400 */ |
|
401 #define PSIF_QP_CORE_LAST_RECEIVED_OUTSTANDING_MSN_OFFSET 11 |
|
402 #define PSIF_QP_CORE_11_LAST_RECEIVED_OUTSTANDING_MSN_SHIFT 0 |
|
403 #define PSIF_QP_CORE_11_LAST_RECEIVED_OUTSTANDING_MSN_BITS 16 |
|
404 #define PSIF_QP_CORE_11_LAST_RECEIVED_OUTSTANDING_MSN_MASK 0x000000000000ffffull |
|
405 |
|
406 #define PSIF_QP_CORE_PATH_MTU_OFFSET 13 |
|
407 #define PSIF_QP_CORE_13_PATH_MTU_SHIFT 4 |
|
408 #define PSIF_QP_CORE_13_PATH_MTU_BITS 3 |
|
409 #define PSIF_QP_CORE_13_PATH_MTU_MASK 0x0000000000000070ull |
|
410 |
|
411 /* This PSN is committed - ACKs sent will contain this PSN. */ |
|
412 #define PSIF_QP_CORE_COMMITTED_RECEIVED_PSN_OFFSET 13 |
|
413 #define PSIF_QP_CORE_13_COMMITTED_RECEIVED_PSN_SHIFT 8 |
|
414 #define PSIF_QP_CORE_13_COMMITTED_RECEIVED_PSN_BITS 24 |
|
415 #define PSIF_QP_CORE_13_COMMITTED_RECEIVED_PSN_MASK 0x00000000ffffff00ull |
|
416 |
|
417 /* |
|
418 * Message sequence number used in AETH when sending ACKs. The number is |
|
419 * incremented every time a new inbound message is processed. |
|
420 */ |
|
421 #define PSIF_QP_CORE_MSN_OFFSET 14 |
|
422 #define PSIF_QP_CORE_14_MSN_SHIFT 0 |
|
423 #define PSIF_QP_CORE_14_MSN_BITS 24 |
|
424 #define PSIF_QP_CORE_14_MSN_MASK 0x0000000000ffffffull |
|
425 |
|
426 /* |
|
427 * This is an index to send completion queue descriptor. The descriptor |
|
428 * points to a send completion queue, which may or may not be the same as the |
|
429 * send completion queue. |
|
430 */ |
|
431 #define PSIF_QP_CORE_SEND_CQ_INDX_OFFSET 14 |
|
432 #define PSIF_QP_CORE_14_SEND_CQ_INDX_SHIFT 24 |
|
433 #define PSIF_QP_CORE_14_SEND_CQ_INDX_BITS 24 |
|
434 #define PSIF_QP_CORE_14_SEND_CQ_INDX_MASK 0x0000ffffff000000ull |
|
435 |
|
436 /* |
|
437 * Committed MSN - the MSN of the newest committed request for this QP. Only |
|
438 * the bottom 16 bits of the MSN is used. |
|
439 */ |
|
440 #define PSIF_QP_CORE_LAST_COMMITTED_MSN_OFFSET 14 |
|
441 #define PSIF_QP_CORE_14_LAST_COMMITTED_MSN_SHIFT 48 |
|
442 #define PSIF_QP_CORE_14_LAST_COMMITTED_MSN_BITS 16 |
|
443 #define PSIF_QP_CORE_14_LAST_COMMITTED_MSN_MASK 0xffff000000000000ull |
|
444 |
|
445 #define PSIF_QP_CORE_SRQ_PD_OFFSET 15 |
|
446 #define PSIF_QP_CORE_15_SRQ_PD_SHIFT 0 |
|
447 #define PSIF_QP_CORE_15_SRQ_PD_BITS 24 |
|
448 #define PSIF_QP_CORE_15_SRQ_PD_MASK 0x0000000000ffffffull |
|
449 |
|
450 #define PSIF_QP_PATH_REMOTE_GID_0_OFFSET 0 |
|
451 #define PSIF_QP_PATH_REMOTE_GID_0_SHIFT 0 |
|
452 #define PSIF_QP_PATH_REMOTE_GID_0_BITS 64 |
|
453 #define PSIF_QP_PATH_REMOTE_GID_0_MASK 0xffffffffffffffffull |
|
454 |
|
455 #define PSIF_QP_PATH_REMOTE_GID_1_OFFSET 1 |
|
456 #define PSIF_QP_PATH_1_REMOTE_GID_1_SHIFT 0 |
|
457 #define PSIF_QP_PATH_1_REMOTE_GID_1_BITS 64 |
|
458 #define PSIF_QP_PATH_1_REMOTE_GID_1_MASK 0xffffffffffffffffull |
|
459 |
|
460 #define PSIF_QP_PATH_REMOTE_LID_OFFSET 2 |
|
461 #define PSIF_QP_PATH_2_REMOTE_LID_SHIFT 0 |
|
462 #define PSIF_QP_PATH_2_REMOTE_LID_BITS 16 |
|
463 #define PSIF_QP_PATH_2_REMOTE_LID_MASK 0x000000000000ffffull |
|
464 |
|
465 #define PSIF_QP_PATH_PORT_OFFSET 2 |
|
466 #define PSIF_QP_PATH_2_PORT_BIT_POSITION 17 |
|
467 #define PSIF_QP_PATH_2_PORT_BIT 0x0000000000020000ull |
|
468 |
|
469 #define PSIF_QP_PATH_LOOPBACK_OFFSET 2 |
|
470 #define PSIF_QP_PATH_2_LOOPBACK_BIT_POSITION 18 |
|
471 #define PSIF_QP_PATH_2_LOOPBACK_BIT 0x0000000000040000ull |
|
472 |
|
473 #define PSIF_QP_PATH_USE_GRH_OFFSET 2 |
|
474 #define PSIF_QP_PATH_2_USE_GRH_BIT_POSITION 19 |
|
475 #define PSIF_QP_PATH_2_USE_GRH_BIT 0x0000000000080000ull |
|
476 |
|
477 #define PSIF_QP_PATH_SL_OFFSET 2 |
|
478 #define PSIF_QP_PATH_2_SL_SHIFT 20 |
|
479 #define PSIF_QP_PATH_2_SL_BITS 4 |
|
480 #define PSIF_QP_PATH_2_SL_MASK 0x0000000000f00000ull |
|
481 |
|
482 #define PSIF_QP_PATH_HOPLMT_OFFSET 2 |
|
483 #define PSIF_QP_PATH_2_HOPLMT_SHIFT 28 |
|
484 #define PSIF_QP_PATH_2_HOPLMT_BITS 8 |
|
485 #define PSIF_QP_PATH_2_HOPLMT_MASK 0x0000000ff0000000ull |
|
486 |
|
487 #define PSIF_QP_PATH_FLOWLABEL_OFFSET 2 |
|
488 #define PSIF_QP_PATH_2_FLOWLABEL_SHIFT 44 |
|
489 #define PSIF_QP_PATH_2_FLOWLABEL_BITS 20 |
|
490 #define PSIF_QP_PATH_2_FLOWLABEL_MASK 0xfffff00000000000ull |
|
491 |
|
492 #define PSIF_QP_PATH_LOCAL_ACK_TIMEOUT_OFFSET 3 |
|
493 #define PSIF_QP_PATH_3_LOCAL_ACK_TIMEOUT_SHIFT 27 |
|
494 #define PSIF_QP_PATH_3_LOCAL_ACK_TIMEOUT_BITS 5 |
|
495 #define PSIF_QP_PATH_3_LOCAL_ACK_TIMEOUT_MASK 0x00000000f8000000ull |
|
496 |
|
497 #define PSIF_QP_PATH_IPD_OFFSET 3 |
|
498 #define PSIF_QP_PATH_3_IPD_SHIFT 32 |
|
499 #define PSIF_QP_PATH_3_IPD_BITS 8 |
|
500 #define PSIF_QP_PATH_3_IPD_MASK 0x000000ff00000000ull |
|
501 |
|
502 /* |
|
503 * This is the LID path bits. This is used by tsu_ibpb when generating the |
|
504 * SLID in the packet, and it is used by tsu_rcv when checking the DLID. |
|
505 */ |
|
506 #define PSIF_QP_PATH_LOCAL_LID_PATH_OFFSET 3 |
|
507 #define PSIF_QP_PATH_3_LOCAL_LID_PATH_SHIFT 48 |
|
508 #define PSIF_QP_PATH_3_LOCAL_LID_PATH_BITS 7 |
|
509 #define PSIF_QP_PATH_3_LOCAL_LID_PATH_MASK 0x007f000000000000ull |
|
510 |
|
511 #define PSIF_QP_PATH_PKEY_INDX_OFFSET 3 |
|
512 #define PSIF_QP_PATH_3_PKEY_INDX_SHIFT 55 |
|
513 #define PSIF_QP_PATH_3_PKEY_INDX_BITS 9 |
|
514 #define PSIF_QP_PATH_3_PKEY_INDX_MASK 0xff80000000000000ull |
|
515 |
|
516 /* L-key state for this DMA validation entry */ |
|
517 #define PSIF_KEY_LKEY_STATE_OFFSET 0 |
|
518 #define PSIF_KEY_LKEY_STATE_SHIFT 60 |
|
519 #define PSIF_KEY_LKEY_STATE_BITS 2 |
|
520 #define PSIF_KEY_LKEY_STATE_MASK 0x3000000000000000ull |
|
521 |
|
522 /* R-key state for this DMA validation entry */ |
|
523 #define PSIF_KEY_RKEY_STATE_OFFSET 0 |
|
524 #define PSIF_KEY_RKEY_STATE_SHIFT 62 |
|
525 #define PSIF_KEY_RKEY_STATE_BITS 2 |
|
526 #define PSIF_KEY_RKEY_STATE_MASK 0xc000000000000000ull |
|
527 |
|
528 /* Length of memory region this validation entry is associated with. */ |
|
529 #define PSIF_KEY_LENGTH_OFFSET 1 |
|
530 #define PSIF_KEY_1_LENGTH_SHIFT 0 |
|
531 #define PSIF_KEY_1_LENGTH_BITS 64 |
|
532 #define PSIF_KEY_1_LENGTH_MASK 0xffffffffffffffffull |
|
533 |
|
534 #define PSIF_KEY_MMU_CONTEXT_OFFSET 2 |
|
535 #define PSIF_KEY_2_MMU_CONTEXT_SHIFT 0 |
|
536 #define PSIF_KEY_2_MMU_CONTEXT_BITS 64 |
|
537 #define PSIF_KEY_2_MMU_CONTEXT_MASK 0xffffffffffffffffull |
|
538 |
|
539 #define PSIF_KEY_BASE_ADDR_OFFSET 3 |
|
540 #define PSIF_KEY_3_BASE_ADDR_SHIFT 0 |
|
541 #define PSIF_KEY_3_BASE_ADDR_BITS 64 |
|
542 #define PSIF_KEY_3_BASE_ADDR_MASK 0xffffffffffffffffull |
|
543 |
|
544 /* sequence number for sanity checking */ |
|
545 #define PSIF_EQ_ENTRY_SEQ_NUM_OFFSET 7 |
|
546 #define PSIF_EQ_ENTRY_7_SEQ_NUM_SHIFT 0 |
|
547 #define PSIF_EQ_ENTRY_7_SEQ_NUM_BITS 32 |
|
548 #define PSIF_EQ_ENTRY_7_SEQ_NUM_MASK 0x00000000ffffffffull |
|
549 |
|
550 /* enum psif_epsc_csr_opcode from request */ |
|
551 #define PSIF_EPSC_CSR_RSP_OPCODE_OFFSET 0 |
|
552 #define PSIF_EPSC_CSR_RSP_OPCODE_SHIFT 48 |
|
553 #define PSIF_EPSC_CSR_RSP_OPCODE_BITS 8 |
|
554 #define PSIF_EPSC_CSR_RSP_OPCODE_MASK 0x00ff000000000000ull |
|
555 |
|
556 /* Sequence number from request */ |
|
557 #define PSIF_EPSC_CSR_RSP_SEQ_NUM_OFFSET 3 |
|
558 #define PSIF_EPSC_CSR_RSP_3_SEQ_NUM_SHIFT 0 |
|
559 #define PSIF_EPSC_CSR_RSP_3_SEQ_NUM_BITS 64 |
|
560 #define PSIF_EPSC_CSR_RSP_3_SEQ_NUM_MASK 0xffffffffffffffffull |
|
561 |
|
562 /* Sequence number - included in response */ |
|
563 #define PSIF_EPSC_CSR_REQ_SEQ_NUM_OFFSET 0 |
|
564 #define PSIF_EPSC_CSR_REQ_SEQ_NUM_SHIFT 32 |
|
565 #define PSIF_EPSC_CSR_REQ_SEQ_NUM_BITS 16 |
|
566 #define PSIF_EPSC_CSR_REQ_SEQ_NUM_MASK 0x0000ffff00000000ull |
|
567 |
|
568 #define PSIF_EPSC_CSR_REQ_OPCODE_OFFSET 0 |
|
569 #define PSIF_EPSC_CSR_REQ_OPCODE_SHIFT 56 |
|
570 #define PSIF_EPSC_CSR_REQ_OPCODE_BITS 8 |
|
571 #define PSIF_EPSC_CSR_REQ_OPCODE_MASK 0xff00000000000000ull |
|
572 |
|
573 /* Index to completion elements added by SW. */ |
|
574 #define PSIF_CQ_SW_HEAD_INDX_OFFSET 0 |
|
575 #define PSIF_CQ_SW_HEAD_INDX_SHIFT 32 |
|
576 #define PSIF_CQ_SW_HEAD_INDX_BITS 32 |
|
577 #define PSIF_CQ_SW_HEAD_INDX_MASK 0xffffffff00000000ull |
|
578 |
|
579 /* |
|
580 * EPS-A core number completions are forwarded to if the proxy_enabled bit is |
|
581 * set. |
|
582 */ |
|
583 #define PSIF_CQ_HW_EPS_CORE_OFFSET 0 |
|
584 #define PSIF_CQ_HW_EPS_CORE_SHIFT 52 |
|
585 #define PSIF_CQ_HW_EPS_CORE_BITS 2 |
|
586 #define PSIF_CQ_HW_EPS_CORE_MASK 0x0030000000000000ull |
|
587 |
|
588 /* |
|
589 * If set, this completion queue is proxy enabled and should send completions |
|
590 * to EPS core indicated by the eps_core field. |
|
591 */ |
|
592 #define PSIF_CQ_HW_PROXY_EN_OFFSET 0 |
|
593 #define PSIF_CQ_HW_PROXY_EN_BIT_POSITION 54 |
|
594 #define PSIF_CQ_HW_PROXY_EN_BIT 0x0040000000000000ull |
|
595 |
|
596 /* The descriptor is valid. */ |
|
597 #define PSIF_CQ_HW_VALID_OFFSET 0 |
|
598 #define PSIF_CQ_HW_VALID_BIT_POSITION 60 |
|
599 #define PSIF_CQ_HW_VALID_BIT 0x1000000000000000ull |
|
600 |
|
601 /* |
|
602 * VA or PA of the base of the completion queue. If PA the MMU context above |
|
603 * will be a bypass context. Updated by software. The head and tail pointers |
|
604 * can be calculated by the following calculations: Address = base_ptr + |
|
605 * (head * ($bits(completion_entry_t)/8 ) Head Pointer and Tail Pointer will |
|
606 * use the same MMU context as the base, and all need to be VA from one |
|
607 * address space, or all need to be PA. In typical use, to allow direct user |
|
608 * access to the head and tail pointer VAs are used. |
|
609 */ |
|
610 #define PSIF_CQ_HW_BASE_ADDR_OFFSET 2 |
|
611 #define PSIF_CQ_HW_2_BASE_ADDR_SHIFT 0 |
|
612 #define PSIF_CQ_HW_2_BASE_ADDR_BITS 64 |
|
613 #define PSIF_CQ_HW_2_BASE_ADDR_MASK 0xffffffffffffffffull |
|
614 |
|
615 /* Index to completion elements to be consumed by HW. */ |
|
616 #define PSIF_CQ_HW_TAIL_INDX_OFFSET 3 |
|
617 #define PSIF_CQ_HW_3_TAIL_INDX_SHIFT 32 |
|
618 #define PSIF_CQ_HW_3_TAIL_INDX_BITS 32 |
|
619 #define PSIF_CQ_HW_3_TAIL_INDX_MASK 0xffffffff00000000ull |
|
620 |
|
621 /* |
|
622 * Work queue completion ID. For receive completions this is the entry number |
|
623 * in the receive queue and the receive queue descriptor index. For send |
|
624 * completions this is the sq_sequence number. |
|
625 */ |
|
626 #define PSIF_CQ_ENTRY_WC_ID_OFFSET 0 |
|
627 #define PSIF_CQ_ENTRY_WC_ID_SHIFT 0 |
|
628 #define PSIF_CQ_ENTRY_WC_ID_BITS 64 |
|
629 #define PSIF_CQ_ENTRY_WC_ID_MASK 0xffffffffffffffffull |
|
630 |
|
631 #define PSIF_CQ_ENTRY_QP_OFFSET 1 |
|
632 #define PSIF_CQ_ENTRY_1_QP_SHIFT 0 |
|
633 #define PSIF_CQ_ENTRY_1_QP_BITS 24 |
|
634 #define PSIF_CQ_ENTRY_1_QP_MASK 0x0000000000ffffffull |
|
635 |
|
636 #define PSIF_CQ_ENTRY_OPCODE_OFFSET 1 |
|
637 #define PSIF_CQ_ENTRY_1_OPCODE_SHIFT 24 |
|
638 #define PSIF_CQ_ENTRY_1_OPCODE_BITS 8 |
|
639 #define PSIF_CQ_ENTRY_1_OPCODE_MASK 0x00000000ff000000ull |
|
640 |
|
641 #define PSIF_CQ_ENTRY_STATUS_OFFSET 2 |
|
642 #define PSIF_CQ_ENTRY_2_STATUS_SHIFT 24 |
|
643 #define PSIF_CQ_ENTRY_2_STATUS_BITS 8 |
|
644 #define PSIF_CQ_ENTRY_2_STATUS_MASK 0x00000000ff000000ull |
|
645 |
|
646 /* sequence number for sanity checking */ |
|
647 #define PSIF_CQ_ENTRY_SEQ_NUM_OFFSET 7 |
|
648 #define PSIF_CQ_ENTRY_7_SEQ_NUM_SHIFT 0 |
|
649 #define PSIF_CQ_ENTRY_7_SEQ_NUM_BITS 32 |
|
650 #define PSIF_CQ_ENTRY_7_SEQ_NUM_MASK 0x00000000ffffffffull |
|
651 |
|
652 #define PSIF_AH_REMOTE_LID_OFFSET 2 |
|
653 #define PSIF_AH_2_REMOTE_LID_SHIFT 0 |
|
654 #define PSIF_AH_2_REMOTE_LID_BITS 16 |
|
655 #define PSIF_AH_2_REMOTE_LID_MASK 0x000000000000ffffull |
|
656 |
|
657 #define PSIF_AH_SL_OFFSET 2 |
|
658 #define PSIF_AH_2_SL_SHIFT 20 |
|
659 #define PSIF_AH_2_SL_BITS 4 |
|
660 #define PSIF_AH_2_SL_MASK 0x0000000000f00000ull |
|
661 #if defined (HOST_LITTLE_ENDIAN) |
|
662 #elif defined (HOST_BIG_ENDIAN) |
|
663 #else |
|
664 #error "Could not determine byte order in psif_hw_macro.h !?" |
|
665 #endif |
|
666 |
|
667 |
|
668 #ifdef __cplusplus |
|
669 } |
|
670 #endif |
|
671 |
|
672 |
|
673 #endif /* _PSIF_HW_MACRO_H */ |