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1 /* |
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2 * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved. |
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3 */ |
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4 |
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5 /* |
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6 * Redistribution and use in source and binary forms, with or without |
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7 * modification, are permitted provided that the following conditions are met: |
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8 * |
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9 * 1. Redistributions of source code must retain the above copyright notice, |
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10 * this list of conditions and the following disclaimer. |
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11 * |
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12 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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13 * this list of conditions and the following disclaimer in the documentation |
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14 * and/or other materials provided with the distribution. |
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15 * |
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16 * 3. Neither the name of the copyright holder nor the names of its contributors |
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17 * may be used to endorse or promote products derived from this software |
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18 * without specific prior written permission. |
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19 * |
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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23 * ARE DISCLAIMED. |
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24 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY |
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25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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31 */ |
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32 |
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33 #ifndef _PSIF_HW_PRINT_C |
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34 #define _PSIF_HW_PRINT_C |
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35 |
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36 #if defined(__arm__) |
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37 |
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38 #include <stdio.h> |
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39 #include <stdint.h> |
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40 #include "psif_endian.h" |
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41 typedef uint64_t __be64; |
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42 |
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43 #else /* virtualized */ |
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44 #if !defined(__KERNEL__) |
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45 #include <stdio.h> |
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46 #include <string.h> |
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47 #if !defined(_PSIFAPI_KERNEL_TYPES_H) |
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48 #define _PSIFAPI_KERNEL_TYPES_H |
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49 #include <stdint.h> |
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50 typedef uint64_t u64; |
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51 typedef uint32_t u32; |
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52 typedef uint16_t u16; |
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53 typedef uint8_t u8; |
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54 #endif /* (_PSIFAPI_KERNEL_TYPES_H) */ |
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55 #include "os_header.h" |
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56 #endif /* !defined(__KERNEL__) */ |
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57 |
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58 #endif /* __arm__ */ |
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59 |
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60 #include "psif_api.h" |
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61 #include "psif_hw_data.h" |
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62 #include "psif_hw_macro.h" |
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63 #include "psif_hw_setget.h" |
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64 #include "psif_hw_print.h" |
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65 #include "psif_api.h" |
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66 |
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67 #if !defined(xprintf) |
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68 #define xprintf fprintf |
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69 #endif |
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70 #if !defined(OS_PRIx64) |
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71 #define OS_PRIx64 "llx" |
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72 #endif |
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73 |
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74 /* Write fixed size bit field represented as unsigned int types */ |
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75 void write_bits_u8(XFILE *fd, int extent, u8 data) |
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76 { |
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77 xprintf(fd, "%#04x", data); |
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78 } /* end write_bits_u8(u8 data) */ |
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79 |
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80 /* Write fixed size bit field represented as unsigned int types */ |
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81 void write_bits_u16(XFILE *fd, int extent, u16 data) |
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82 { |
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83 xprintf(fd, "%#06x", data); |
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84 } /* end write_bits_u16(u16 data) */ |
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85 |
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86 /* Write fixed size bit field represented as unsigned int types */ |
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87 void write_bits_u32(XFILE *fd, int extent, u32 data) |
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88 { |
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89 xprintf(fd, "%#010x", data); |
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90 } /* end write_bits_u32(u32 data) */ |
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91 |
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92 /* Write fixed size bit field represented as unsigned int types */ |
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93 void write_bits_u64(XFILE *fd, int extent, u64 data) |
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94 { |
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95 xprintf(fd, "%#018" OS_PRIx64 "", data); |
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96 } /* end write_bits_u64(u64 data) */ |
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97 |
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98 |
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99 /* Convert enum psif_epsc_degrade_cause to string */ |
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100 const char *string_enum_psif_epsc_degrade_cause(enum psif_epsc_degrade_cause val) |
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101 { |
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102 switch (val) { |
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103 case DEGRADE_CAUSE_FLAG_MISSING_GUID: |
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104 return "DEGRADE_CAUSE_FLAG_MISSING_GUID"; |
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105 case DEGRADE_CAUSE_FLAG_VPD_INVALID_NAME: |
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106 return "DEGRADE_CAUSE_FLAG_VPD_INVALID_NAME"; |
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107 case DEGRADE_CAUSE_FLAG_HW_UNSUPPORTED: |
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108 return "DEGRADE_CAUSE_FLAG_HW_UNSUPPORTED"; |
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109 case DEGRADE_CAUSE_FLAG_HW_MDIO_ERROR: |
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110 return "DEGRADE_CAUSE_FLAG_HW_MDIO_ERROR"; |
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111 case DEGRADE_CAUSE_FLAG_MODIFY_QP_TIMEOUT: |
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112 return "DEGRADE_CAUSE_FLAG_MODIFY_QP_TIMEOUT"; |
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113 case DEGRADE_CAUSE_FLAG_VIRTMODE_RECONF: |
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114 return "DEGRADE_CAUSE_FLAG_VIRTMODE_RECONF"; |
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115 case DEGRADE_CAUSE_FLAG_MCAST_LACK_OF_CREDIT: |
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116 return "DEGRADE_CAUSE_FLAG_MCAST_LACK_OF_CREDIT"; |
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117 case PSIF_EPSC_DEGRADE_CAUSE_FIELD_MAX: |
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118 return "PSIF_EPSC_DEGRADE_CAUSE_FIELD_MAX"; |
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119 default: |
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120 return "UNKNOWN_psif_epsc_degrade_cause"; |
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121 } |
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122 } |
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123 |
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124 void write_enum_psif_epsc_degrade_cause(XFILE *fd, |
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125 enum psif_epsc_degrade_cause data) |
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126 { |
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127 xprintf(fd, "%s", string_enum_psif_epsc_degrade_cause(data)); |
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128 } /* end write_..._psif_epsc_degrade_cause(psif_epsc_degrade_cause data) */ |
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129 |
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130 /* Convert enum psif_mmu_translation to string */ |
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131 const char *string_enum_psif_mmu_translation(enum psif_mmu_translation val) |
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132 { |
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133 switch (val) { |
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134 case MMU_PASS_THROUGH0: |
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135 return "MMU_PASS_THROUGH0"; |
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136 case MMU_PASS_THROUGH_PAD: |
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137 return "MMU_PASS_THROUGH_PAD"; |
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138 case MMU_GVA2GPA_MODE: |
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139 return "MMU_GVA2GPA_MODE"; |
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140 case MMU_GVA2GPA_MODE_PAD: |
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141 return "MMU_GVA2GPA_MODE_PAD"; |
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142 case MMU_PRETRANSLATED: |
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143 return "MMU_PRETRANSLATED"; |
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144 case MMU_PRETRANSLATED_PAD: |
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145 return "MMU_PRETRANSLATED_PAD"; |
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146 case MMU_EPSA_MODE: |
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147 return "MMU_EPSA_MODE"; |
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148 case MMU_EPSC_MODE: |
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149 return "MMU_EPSC_MODE"; |
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150 default: |
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151 return "UNKNOWN_psif_mmu_translation"; |
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152 } |
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153 } |
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154 |
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155 void write_enum_psif_mmu_translation(XFILE *fd, |
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156 enum psif_mmu_translation data) |
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157 { |
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158 xprintf(fd, "%s", string_enum_psif_mmu_translation(data)); |
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159 } /* end write_..._psif_mmu_translation(psif_mmu_translation data) */ |
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160 |
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161 /* Convert enum psif_page_size to string */ |
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162 const char *string_enum_psif_page_size(enum psif_page_size val) |
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163 { |
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164 switch (val) { |
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165 case PAGE_SIZE_IA32E_4KB: |
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166 return "PAGE_SIZE_IA32E_4KB"; |
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167 case PAGE_SIZE_IA32E_2MB: |
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168 return "PAGE_SIZE_IA32E_2MB"; |
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169 case PAGE_SIZE_IA32E_1GB: |
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170 return "PAGE_SIZE_IA32E_1GB"; |
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171 case PAGE_SIZE_S64_8KB: |
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172 return "PAGE_SIZE_S64_8KB"; |
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173 case PAGE_SIZE_S64_64KB: |
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174 return "PAGE_SIZE_S64_64KB"; |
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175 case PAGE_SIZE_S64_512KB: |
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176 return "PAGE_SIZE_S64_512KB"; |
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177 case PAGE_SIZE_S64_4MB: |
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178 return "PAGE_SIZE_S64_4MB"; |
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179 case PAGE_SIZE_S64_32MB: |
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180 return "PAGE_SIZE_S64_32MB"; |
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181 case PAGE_SIZE_S64_2GB: |
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182 return "PAGE_SIZE_S64_2GB"; |
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183 case PAGE_SIZE_S64_16GB: |
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184 return "PAGE_SIZE_S64_16GB"; |
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185 default: |
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186 return "UNKNOWN_psif_page_size"; |
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187 } |
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188 } |
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189 |
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190 void write_enum_psif_page_size(XFILE *fd, |
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191 enum psif_page_size data) |
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192 { |
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193 xprintf(fd, "%s", string_enum_psif_page_size(data)); |
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194 } /* end write_..._psif_page_size(psif_page_size data) */ |
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195 |
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196 /* Convert enum psif_wr_type to string */ |
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197 const char *string_enum_psif_wr_type(enum psif_wr_type val) |
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198 { |
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199 switch (val) { |
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200 case PSIF_WR_SEND: |
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201 return "PSIF_WR_SEND"; |
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202 case PSIF_WR_SEND_IMM: |
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203 return "PSIF_WR_SEND_IMM"; |
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204 case PSIF_WR_SPECIAL_QP_SEND: |
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205 return "PSIF_WR_SPECIAL_QP_SEND"; |
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206 case PSIF_WR_QP0_SEND_DR_XMIT: |
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207 return "PSIF_WR_QP0_SEND_DR_XMIT"; |
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208 case PSIF_WR_QP0_SEND_DR_LOOPBACK: |
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209 return "PSIF_WR_QP0_SEND_DR_LOOPBACK"; |
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210 case PSIF_WR_EPS_SPECIAL_QP_SEND: |
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211 return "PSIF_WR_EPS_SPECIAL_QP_SEND"; |
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212 case PSIF_WR_EPS_QP0_SEND_DR_XMIT: |
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213 return "PSIF_WR_EPS_QP0_SEND_DR_XMIT"; |
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214 case PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK: |
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215 return "PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK"; |
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216 case PSIF_WR_RDMA_WR: |
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217 return "PSIF_WR_RDMA_WR"; |
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218 case PSIF_WR_RDMA_WR_IMM: |
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219 return "PSIF_WR_RDMA_WR_IMM"; |
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220 case PSIF_WR_RDMA_RD: |
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221 return "PSIF_WR_RDMA_RD"; |
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222 case PSIF_WR_CMP_SWAP: |
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223 return "PSIF_WR_CMP_SWAP"; |
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224 case PSIF_WR_FETCH_ADD: |
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225 return "PSIF_WR_FETCH_ADD"; |
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226 case PSIF_WR_MASK_CMP_SWAP: |
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227 return "PSIF_WR_MASK_CMP_SWAP"; |
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228 case PSIF_WR_MASK_FETCH_ADD: |
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229 return "PSIF_WR_MASK_FETCH_ADD"; |
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230 case PSIF_WR_LSO: |
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231 return "PSIF_WR_LSO"; |
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232 case PSIF_WR_INVALIDATE_RKEY: |
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233 return "PSIF_WR_INVALIDATE_RKEY"; |
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234 case PSIF_WR_INVALIDATE_LKEY: |
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235 return "PSIF_WR_INVALIDATE_LKEY"; |
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236 case PSIF_WR_INVALIDATE_BOTH_KEYS: |
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237 return "PSIF_WR_INVALIDATE_BOTH_KEYS"; |
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238 case PSIF_WR_INVALIDATE_TLB: |
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239 return "PSIF_WR_INVALIDATE_TLB"; |
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240 case PSIF_WR_RESIZE_CQ: |
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241 return "PSIF_WR_RESIZE_CQ"; |
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242 case PSIF_WR_SET_SRQ_LIM: |
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243 return "PSIF_WR_SET_SRQ_LIM"; |
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244 case PSIF_WR_SET_XRCSRQ_LIM: |
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245 return "PSIF_WR_SET_XRCSRQ_LIM"; |
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246 case PSIF_WR_REQ_CMPL_NOTIFY: |
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247 return "PSIF_WR_REQ_CMPL_NOTIFY"; |
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248 case PSIF_WR_CMPL_NOTIFY_RCVD: |
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249 return "PSIF_WR_CMPL_NOTIFY_RCVD"; |
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250 case PSIF_WR_REARM_CMPL_EVENT: |
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251 return "PSIF_WR_REARM_CMPL_EVENT"; |
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252 case PSIF_WR_GENERATE_COMPLETION: |
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253 return "PSIF_WR_GENERATE_COMPLETION"; |
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254 case PSIF_WR_INVALIDATE_RQ: |
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255 return "PSIF_WR_INVALIDATE_RQ"; |
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256 case PSIF_WR_INVALIDATE_CQ: |
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257 return "PSIF_WR_INVALIDATE_CQ"; |
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258 case PSIF_WR_INVALIDATE_XRCSRQ: |
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259 return "PSIF_WR_INVALIDATE_XRCSRQ"; |
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260 case PSIF_WR_INVALIDATE_SGL_CACHE: |
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261 return "PSIF_WR_INVALIDATE_SGL_CACHE"; |
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262 default: |
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263 return "UNKNOWN_psif_wr_type"; |
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264 } |
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265 } |
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266 |
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267 void write_enum_psif_wr_type(XFILE *fd, |
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268 enum psif_wr_type data) |
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269 { |
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270 xprintf(fd, "%s", string_enum_psif_wr_type(data)); |
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271 } /* end write_..._psif_wr_type(psif_wr_type data) */ |
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272 |
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273 /* Convert enum psif_port to string */ |
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274 const char *string_enum_psif_port(enum psif_port val) |
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275 { |
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276 switch (val) { |
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277 case PORT_1: |
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278 return "PORT_1"; |
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279 case PORT_2: |
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280 return "PORT_2"; |
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281 default: |
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282 return "UNKNOWN_psif_port"; |
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283 } |
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284 } |
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285 |
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286 void write_enum_psif_port(XFILE *fd, |
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287 enum psif_port data) |
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288 { |
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289 xprintf(fd, "%s", string_enum_psif_port(data)); |
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290 } /* end write_..._psif_port(psif_port data) */ |
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291 |
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292 /* Convert enum psif_use_ah to string */ |
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293 const char *string_enum_psif_use_ah(enum psif_use_ah val) |
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294 { |
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295 switch (val) { |
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296 case NO_AHA: |
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297 return "NO_AHA"; |
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298 case USE_AHA: |
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299 return "USE_AHA"; |
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300 default: |
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301 return "UNKNOWN_psif_use_ah"; |
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302 } |
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303 } |
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304 |
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305 void write_enum_psif_use_ah(XFILE *fd, |
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306 enum psif_use_ah data) |
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307 { |
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308 xprintf(fd, "%s", string_enum_psif_use_ah(data)); |
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309 } /* end write_..._psif_use_ah(psif_use_ah data) */ |
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310 |
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311 /* Convert enum psif_tsu_qos to string */ |
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312 const char *string_enum_psif_tsu_qos(enum psif_tsu_qos val) |
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313 { |
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314 switch (val) { |
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315 case QOSL_HIGH_BANDWIDTH: |
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316 return "QOSL_HIGH_BANDWIDTH"; |
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317 case QOSL_LOW_LATENCY: |
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318 return "QOSL_LOW_LATENCY"; |
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319 default: |
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320 return "UNKNOWN_psif_tsu_qos"; |
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321 } |
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322 } |
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323 |
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324 void write_enum_psif_tsu_qos(XFILE *fd, |
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325 enum psif_tsu_qos data) |
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326 { |
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327 xprintf(fd, "%s", string_enum_psif_tsu_qos(data)); |
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328 } /* end write_..._psif_tsu_qos(psif_tsu_qos data) */ |
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329 |
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330 /* Convert enum psif_wc_opcode to string */ |
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331 const char *string_enum_psif_wc_opcode(enum psif_wc_opcode val) |
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332 { |
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333 switch (val) { |
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334 case PSIF_WC_OPCODE_SEND: |
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335 return "PSIF_WC_OPCODE_SEND"; |
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336 case PSIF_WC_OPCODE_RDMA_WR: |
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337 return "PSIF_WC_OPCODE_RDMA_WR"; |
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338 case PSIF_WC_OPCODE_RDMA_READ: |
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339 return "PSIF_WC_OPCODE_RDMA_READ"; |
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340 case PSIF_WC_OPCODE_CMP_SWAP: |
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341 return "PSIF_WC_OPCODE_CMP_SWAP"; |
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342 case PSIF_WC_OPCODE_FETCH_ADD: |
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343 return "PSIF_WC_OPCODE_FETCH_ADD"; |
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344 case PSIF_WC_OPCODE_LSO: |
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345 return "PSIF_WC_OPCODE_LSO"; |
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346 case PSIF_WC_OPCODE_MASKED_CMP_SWAP: |
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347 return "PSIF_WC_OPCODE_MASKED_CMP_SWAP"; |
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348 case PSIF_WC_OPCODE_MASKED_FETCH_ADD: |
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349 return "PSIF_WC_OPCODE_MASKED_FETCH_ADD"; |
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350 case PSIF_WC_OPCODE_INVALIDATE_RKEY: |
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351 return "PSIF_WC_OPCODE_INVALIDATE_RKEY"; |
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352 case PSIF_WC_OPCODE_INVALIDATE_LKEY: |
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353 return "PSIF_WC_OPCODE_INVALIDATE_LKEY"; |
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354 case PSIF_WC_OPCODE_INVALIDATE_BOTH_KEYS: |
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355 return "PSIF_WC_OPCODE_INVALIDATE_BOTH_KEYS"; |
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356 case PSIF_WC_OPCODE_INVALIDATE_TLB: |
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357 return "PSIF_WC_OPCODE_INVALIDATE_TLB"; |
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358 case PSIF_WC_OPCODE_RESIZE_CQ: |
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359 return "PSIF_WC_OPCODE_RESIZE_CQ"; |
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360 case PSIF_WC_OPCODE_SET_SRQ_LIM: |
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361 return "PSIF_WC_OPCODE_SET_SRQ_LIM"; |
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362 case PSIF_WC_OPCODE_SET_XRCSRQ_LIM: |
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363 return "PSIF_WC_OPCODE_SET_XRCSRQ_LIM"; |
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364 case PSIF_WC_OPCODE_REQ_CMPL_NOTIFY: |
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365 return "PSIF_WC_OPCODE_REQ_CMPL_NOTIFY"; |
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366 case PSIF_WC_OPCODE_CMPL_NOTIFY_RCVD: |
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367 return "PSIF_WC_OPCODE_CMPL_NOTIFY_RCVD"; |
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368 case PSIF_WC_OPCODE_REARM_CMPL_EVENT: |
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369 return "PSIF_WC_OPCODE_REARM_CMPL_EVENT"; |
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370 case PSIF_WC_OPCODE_GENERATE_COMPLETION: |
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371 return "PSIF_WC_OPCODE_GENERATE_COMPLETION"; |
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372 case PSIF_WC_OPCODE_INVALIDATE_RQ: |
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373 return "PSIF_WC_OPCODE_INVALIDATE_RQ"; |
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374 case PSIF_WC_OPCODE_INVALIDATE_CQ: |
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375 return "PSIF_WC_OPCODE_INVALIDATE_CQ"; |
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376 case PSIF_WC_OPCODE_INVALIDATE_RB: |
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377 return "PSIF_WC_OPCODE_INVALIDATE_RB"; |
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378 case PSIF_WC_OPCODE_INVALIDATE_XRCSRQ: |
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379 return "PSIF_WC_OPCODE_INVALIDATE_XRCSRQ"; |
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380 case PSIF_WC_OPCODE_INVALIDATE_SGL_CACHE: |
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381 return "PSIF_WC_OPCODE_INVALIDATE_SGL_CACHE"; |
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382 case PSIF_WC_OPCODE_RECEIVE_SEND: |
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383 return "PSIF_WC_OPCODE_RECEIVE_SEND"; |
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384 case PSIF_WC_OPCODE_RECEIVE_RDMA_WR_IMM: |
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385 return "PSIF_WC_OPCODE_RECEIVE_RDMA_WR_IMM"; |
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386 case PSIF_WC_OPCODE_RECEIVE_CONDITIONAL_WR_IMM: |
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387 return "PSIF_WC_OPCODE_RECEIVE_CONDITIONAL_WR_IMM"; |
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388 default: |
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389 return "UNKNOWN_psif_wc_opcode"; |
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390 } |
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391 } |
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392 |
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393 void write_enum_psif_wc_opcode(XFILE *fd, |
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394 enum psif_wc_opcode data) |
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395 { |
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396 xprintf(fd, "%s", string_enum_psif_wc_opcode(data)); |
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397 } /* end write_..._psif_wc_opcode(psif_wc_opcode data) */ |
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398 |
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399 /* Convert enum psif_wc_status to string */ |
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400 const char *string_enum_psif_wc_status(enum psif_wc_status val) |
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401 { |
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402 switch (val) { |
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403 case PSIF_WC_STATUS_SUCCESS: |
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404 return "PSIF_WC_STATUS_SUCCESS"; |
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405 case PSIF_WC_STATUS_LOC_LEN_ERR: |
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406 return "PSIF_WC_STATUS_LOC_LEN_ERR"; |
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407 case PSIF_WC_STATUS_LOC_QP_OP_ERR: |
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408 return "PSIF_WC_STATUS_LOC_QP_OP_ERR"; |
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409 case PSIF_WC_STATUS_LOC_EEC_OP_ERR: |
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410 return "PSIF_WC_STATUS_LOC_EEC_OP_ERR"; |
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411 case PSIF_WC_STATUS_LOC_PROT_ERR: |
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412 return "PSIF_WC_STATUS_LOC_PROT_ERR"; |
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413 case PSIF_WC_STATUS_WR_FLUSH_ERR: |
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414 return "PSIF_WC_STATUS_WR_FLUSH_ERR"; |
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415 case PSIF_WC_STATUS_MW_BIND_ERR: |
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416 return "PSIF_WC_STATUS_MW_BIND_ERR"; |
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417 case PSIF_WC_STATUS_BAD_RESP_ERR: |
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418 return "PSIF_WC_STATUS_BAD_RESP_ERR"; |
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419 case PSIF_WC_STATUS_LOC_ACCESS_ERR: |
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420 return "PSIF_WC_STATUS_LOC_ACCESS_ERR"; |
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421 case PSIF_WC_STATUS_REM_INV_REQ_ERR: |
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422 return "PSIF_WC_STATUS_REM_INV_REQ_ERR"; |
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423 case PSIF_WC_STATUS_REM_ACCESS_ERR: |
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424 return "PSIF_WC_STATUS_REM_ACCESS_ERR"; |
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425 case PSIF_WC_STATUS_REM_OP_ERR: |
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426 return "PSIF_WC_STATUS_REM_OP_ERR"; |
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427 case PSIF_WC_STATUS_RETRY_EXC_ERR: |
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428 return "PSIF_WC_STATUS_RETRY_EXC_ERR"; |
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429 case PSIF_WC_STATUS_RNR_RETRY_EXC_ERR: |
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430 return "PSIF_WC_STATUS_RNR_RETRY_EXC_ERR"; |
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431 case PSIF_WC_STATUS_LOC_RDD_VIOL_ERR: |
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432 return "PSIF_WC_STATUS_LOC_RDD_VIOL_ERR"; |
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433 case PSIF_WC_STATUS_REM_INV_RD_REQ_ERR: |
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434 return "PSIF_WC_STATUS_REM_INV_RD_REQ_ERR"; |
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435 case PSIF_WC_STATUS_REM_ABORT_ERR: |
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436 return "PSIF_WC_STATUS_REM_ABORT_ERR"; |
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437 case PSIF_WC_STATUS_INV_EECN_ERR: |
|
438 return "PSIF_WC_STATUS_INV_EECN_ERR"; |
|
439 case PSIF_WC_STATUS_INV_EEC_STATE_ERR: |
|
440 return "PSIF_WC_STATUS_INV_EEC_STATE_ERR"; |
|
441 case PSIF_WC_STATUS_FATAL_ERR: |
|
442 return "PSIF_WC_STATUS_FATAL_ERR"; |
|
443 case PSIF_WC_STATUS_RESP_TIMEOUT_ERR: |
|
444 return "PSIF_WC_STATUS_RESP_TIMEOUT_ERR"; |
|
445 case PSIF_WC_STATUS_GENERAL_ERR: |
|
446 return "PSIF_WC_STATUS_GENERAL_ERR"; |
|
447 case PSIF_WC_STATUS_FIELD_MAX: |
|
448 return "PSIF_WC_STATUS_FIELD_MAX"; |
|
449 default: |
|
450 return "UNKNOWN_psif_wc_status"; |
|
451 } |
|
452 } |
|
453 |
|
454 void write_enum_psif_wc_status(XFILE *fd, |
|
455 enum psif_wc_status data) |
|
456 { |
|
457 xprintf(fd, "%s", string_enum_psif_wc_status(data)); |
|
458 } /* end write_..._psif_wc_status(psif_wc_status data) */ |
|
459 |
|
460 /* Convert enum ib_opcode to string */ |
|
461 const char *string_enum_ib_opcode(enum ib_opcode val) |
|
462 { |
|
463 switch (val) { |
|
464 case RC_SEND_First: |
|
465 return "RC_SEND_First"; |
|
466 case RC_SEND_Middle: |
|
467 return "RC_SEND_Middle"; |
|
468 case RC_SEND_Last: |
|
469 return "RC_SEND_Last"; |
|
470 case RC_SEND_Last_Imm: |
|
471 return "RC_SEND_Last_Imm"; |
|
472 case RC_SEND_Only: |
|
473 return "RC_SEND_Only"; |
|
474 case RC_SEND_Only_Imm: |
|
475 return "RC_SEND_Only_Imm"; |
|
476 case RC_RDMA_WR_First: |
|
477 return "RC_RDMA_WR_First"; |
|
478 case RC_RDMA_WR_Middle: |
|
479 return "RC_RDMA_WR_Middle"; |
|
480 case RC_RDMA_WR_Last: |
|
481 return "RC_RDMA_WR_Last"; |
|
482 case RC_RDMA_WR_Last_Imm: |
|
483 return "RC_RDMA_WR_Last_Imm"; |
|
484 case RC_RDMA_WR_Only: |
|
485 return "RC_RDMA_WR_Only"; |
|
486 case RC_RDMA_WR_Only_Imm: |
|
487 return "RC_RDMA_WR_Only_Imm"; |
|
488 case RC_RDMA_RD_Req: |
|
489 return "RC_RDMA_RD_Req"; |
|
490 case RC_RDMA_RD_Resp_First: |
|
491 return "RC_RDMA_RD_Resp_First"; |
|
492 case RC_RDMA_RD_Resp_Middle: |
|
493 return "RC_RDMA_RD_Resp_Middle"; |
|
494 case RC_RDMA_RD_Resp_Last: |
|
495 return "RC_RDMA_RD_Resp_Last"; |
|
496 case RC_RDMA_RD_Resp_Only: |
|
497 return "RC_RDMA_RD_Resp_Only"; |
|
498 case RC_ACK: |
|
499 return "RC_ACK"; |
|
500 case RC_Atomic_ACK: |
|
501 return "RC_Atomic_ACK"; |
|
502 case RC_CmpSwap: |
|
503 return "RC_CmpSwap"; |
|
504 case RC_FetchAdd: |
|
505 return "RC_FetchAdd"; |
|
506 case RC_Reserved: |
|
507 return "RC_Reserved"; |
|
508 case RC_SEND_Last_Invalid: |
|
509 return "RC_SEND_Last_Invalid"; |
|
510 case RC_SEND_Only_Invalid: |
|
511 return "RC_SEND_Only_Invalid"; |
|
512 case RC_MaskCmpSwap: |
|
513 return "RC_MaskCmpSwap"; |
|
514 case RC_MaskFetchAdd: |
|
515 return "RC_MaskFetchAdd"; |
|
516 case UC_SEND_First: |
|
517 return "UC_SEND_First"; |
|
518 case UC_SEND_Middle: |
|
519 return "UC_SEND_Middle"; |
|
520 case UC_SEND_Last: |
|
521 return "UC_SEND_Last"; |
|
522 case UC_SEND_Last_Imm: |
|
523 return "UC_SEND_Last_Imm"; |
|
524 case UC_SEND_Only: |
|
525 return "UC_SEND_Only"; |
|
526 case UC_SEND_Only_Imm: |
|
527 return "UC_SEND_Only_Imm"; |
|
528 case UC_RDMA_WR_First: |
|
529 return "UC_RDMA_WR_First"; |
|
530 case UC_RDMA_WR_Middle: |
|
531 return "UC_RDMA_WR_Middle"; |
|
532 case UC_RDMA_WR_Last: |
|
533 return "UC_RDMA_WR_Last"; |
|
534 case UC_RDMA_WR_Last_Imm: |
|
535 return "UC_RDMA_WR_Last_Imm"; |
|
536 case UC_RDMA_WR_Only: |
|
537 return "UC_RDMA_WR_Only"; |
|
538 case UC_RDMA_WR_Only_Imm: |
|
539 return "UC_RDMA_WR_Only_Imm"; |
|
540 case RD_SEND_First: |
|
541 return "RD_SEND_First"; |
|
542 case RD_SEND_Middle: |
|
543 return "RD_SEND_Middle"; |
|
544 case RD_SEND_Last: |
|
545 return "RD_SEND_Last"; |
|
546 case RD_SEND_Last_Imm: |
|
547 return "RD_SEND_Last_Imm"; |
|
548 case RD_SEND_Only: |
|
549 return "RD_SEND_Only"; |
|
550 case RD_SEND_Only_Imm: |
|
551 return "RD_SEND_Only_Imm"; |
|
552 case RD_RDMA_WR_First: |
|
553 return "RD_RDMA_WR_First"; |
|
554 case RD_RDMA_WR_Middle: |
|
555 return "RD_RDMA_WR_Middle"; |
|
556 case RD_RDMA_WR_Last: |
|
557 return "RD_RDMA_WR_Last"; |
|
558 case RD_RDMA_WR_Last_Imm: |
|
559 return "RD_RDMA_WR_Last_Imm"; |
|
560 case RD_RDMA_WR_Only: |
|
561 return "RD_RDMA_WR_Only"; |
|
562 case RD_RDMA_WR_Only_Imm: |
|
563 return "RD_RDMA_WR_Only_Imm"; |
|
564 case RD_RDMA_RD_Req: |
|
565 return "RD_RDMA_RD_Req"; |
|
566 case RD_RDMA_RD_Resp_First: |
|
567 return "RD_RDMA_RD_Resp_First"; |
|
568 case RD_RDMA_RD_Resp_Middle: |
|
569 return "RD_RDMA_RD_Resp_Middle"; |
|
570 case RD_RDMA_RD_Resp_Last: |
|
571 return "RD_RDMA_RD_Resp_Last"; |
|
572 case RD_RDMA_RD_Resp_Only: |
|
573 return "RD_RDMA_RD_Resp_Only"; |
|
574 case RD_ACK: |
|
575 return "RD_ACK"; |
|
576 case RD_Atomic_ACK: |
|
577 return "RD_Atomic_ACK"; |
|
578 case RD_CmpSwap: |
|
579 return "RD_CmpSwap"; |
|
580 case RD_FetchAdd: |
|
581 return "RD_FetchAdd"; |
|
582 case RD_RESYNC: |
|
583 return "RD_RESYNC"; |
|
584 case UD_SEND_Only: |
|
585 return "UD_SEND_Only"; |
|
586 case UD_SEND_Only_Imm: |
|
587 return "UD_SEND_Only_Imm"; |
|
588 case CNP: |
|
589 return "CNP"; |
|
590 case XRC_SEND_First: |
|
591 return "XRC_SEND_First"; |
|
592 case XRC_SEND_Middle: |
|
593 return "XRC_SEND_Middle"; |
|
594 case XRC_SEND_Last: |
|
595 return "XRC_SEND_Last"; |
|
596 case XRC_SEND_Last_Imm: |
|
597 return "XRC_SEND_Last_Imm"; |
|
598 case XRC_SEND_Only: |
|
599 return "XRC_SEND_Only"; |
|
600 case XRC_SEND_Only_Imm: |
|
601 return "XRC_SEND_Only_Imm"; |
|
602 case XRC_RDMA_WR_First: |
|
603 return "XRC_RDMA_WR_First"; |
|
604 case XRC_RDMA_WR_Middle: |
|
605 return "XRC_RDMA_WR_Middle"; |
|
606 case XRC_RDMA_WR_Last: |
|
607 return "XRC_RDMA_WR_Last"; |
|
608 case XRC_RDMA_WR_Last_Imm: |
|
609 return "XRC_RDMA_WR_Last_Imm"; |
|
610 case XRC_RDMA_WR_Only: |
|
611 return "XRC_RDMA_WR_Only"; |
|
612 case XRC_RDMA_WR_Only_Imm: |
|
613 return "XRC_RDMA_WR_Only_Imm"; |
|
614 case XRC_RDMA_RD_Req: |
|
615 return "XRC_RDMA_RD_Req"; |
|
616 case XRC_RDMA_RD_Resp_First: |
|
617 return "XRC_RDMA_RD_Resp_First"; |
|
618 case XRC_RDMA_RD_Resp_Middle: |
|
619 return "XRC_RDMA_RD_Resp_Middle"; |
|
620 case XRC_RDMA_RD_Resp_Last: |
|
621 return "XRC_RDMA_RD_Resp_Last"; |
|
622 case XRC_RDMA_RD_Resp_Only: |
|
623 return "XRC_RDMA_RD_Resp_Only"; |
|
624 case XRC_ACK: |
|
625 return "XRC_ACK"; |
|
626 case XRC_Atomic_ACK: |
|
627 return "XRC_Atomic_ACK"; |
|
628 case XRC_CmpSwap: |
|
629 return "XRC_CmpSwap"; |
|
630 case XRC_FetchAdd: |
|
631 return "XRC_FetchAdd"; |
|
632 case XRC_Reserved: |
|
633 return "XRC_Reserved"; |
|
634 case XRC_SEND_Last_Invalid: |
|
635 return "XRC_SEND_Last_Invalid"; |
|
636 case XRC_SEND_Only_Invalid: |
|
637 return "XRC_SEND_Only_Invalid"; |
|
638 case XRC_MaskCmpSwap: |
|
639 return "XRC_MaskCmpSwap"; |
|
640 case XRC_MaskFetchAdd: |
|
641 return "XRC_MaskFetchAdd"; |
|
642 case MANSP1_INVALID: |
|
643 return "MANSP1_INVALID"; |
|
644 case MANSP1_HOST_READ: |
|
645 return "MANSP1_HOST_READ"; |
|
646 case MANSP1_HOST_WRITE: |
|
647 return "MANSP1_HOST_WRITE"; |
|
648 case MANSP1_HOST_READ_NO_DMAVT: |
|
649 return "MANSP1_HOST_READ_NO_DMAVT"; |
|
650 case MANSP1_HOST_WRITE_NO_DMAVT: |
|
651 return "MANSP1_HOST_WRITE_NO_DMAVT"; |
|
652 case MANSP1_INTERNAL_TYPE: |
|
653 return "MANSP1_INTERNAL_TYPE"; |
|
654 case MANSP1_INTERNAL_TYPE_MMU_BYPASS: |
|
655 return "MANSP1_INTERNAL_TYPE_MMU_BYPASS"; |
|
656 case MANSP1_HOST_CMP_SWAP: |
|
657 return "MANSP1_HOST_CMP_SWAP"; |
|
658 case MANSP1_DR_LOOPBACK: |
|
659 return "MANSP1_DR_LOOPBACK"; |
|
660 case MANSP1_ARP_LOOPBACK: |
|
661 return "MANSP1_ARP_LOOPBACK"; |
|
662 default: |
|
663 return "UNKNOWN_ib_opcode"; |
|
664 } |
|
665 } |
|
666 |
|
667 void write_enum_ib_opcode(XFILE *fd, |
|
668 enum ib_opcode data) |
|
669 { |
|
670 xprintf(fd, "%s", string_enum_ib_opcode(data)); |
|
671 } /* end write_..._ib_opcode(ib_opcode data) */ |
|
672 |
|
673 /* Convert enum psif_eps_a_core to string */ |
|
674 const char *string_enum_psif_eps_a_core(enum psif_eps_a_core val) |
|
675 { |
|
676 switch (val) { |
|
677 case PSIF_EPS_A_1: |
|
678 return "PSIF_EPS_A_1"; |
|
679 case PSIF_EPS_A_2: |
|
680 return "PSIF_EPS_A_2"; |
|
681 case PSIF_EPS_A_3: |
|
682 return "PSIF_EPS_A_3"; |
|
683 case PSIF_EPS_A_4: |
|
684 return "PSIF_EPS_A_4"; |
|
685 default: |
|
686 return "UNKNOWN_psif_eps_a_core"; |
|
687 } |
|
688 } |
|
689 |
|
690 void write_enum_psif_eps_a_core(XFILE *fd, |
|
691 enum psif_eps_a_core data) |
|
692 { |
|
693 xprintf(fd, "%s", string_enum_psif_eps_a_core(data)); |
|
694 } /* end write_..._psif_eps_a_core(psif_eps_a_core data) */ |
|
695 |
|
696 /* Convert enum psif_qp_state to string */ |
|
697 const char *string_enum_psif_qp_state(enum psif_qp_state val) |
|
698 { |
|
699 switch (val) { |
|
700 case PSIF_QP_STATE_RESET: |
|
701 return "PSIF_QP_STATE_RESET"; |
|
702 case PSIF_QP_STATE_INIT: |
|
703 return "PSIF_QP_STATE_INIT"; |
|
704 case PSIF_QP_STATE_RTR: |
|
705 return "PSIF_QP_STATE_RTR"; |
|
706 case PSIF_QP_STATE_RTS: |
|
707 return "PSIF_QP_STATE_RTS"; |
|
708 case PSIF_QP_STATE_SQERR: |
|
709 return "PSIF_QP_STATE_SQERR"; |
|
710 case PSIF_QP_STATE_ERROR: |
|
711 return "PSIF_QP_STATE_ERROR"; |
|
712 case PSIF_QP_STATE_INVALID: |
|
713 return "PSIF_QP_STATE_INVALID"; |
|
714 default: |
|
715 return "UNKNOWN_psif_qp_state"; |
|
716 } |
|
717 } |
|
718 |
|
719 void write_enum_psif_qp_state(XFILE *fd, |
|
720 enum psif_qp_state data) |
|
721 { |
|
722 xprintf(fd, "%s", string_enum_psif_qp_state(data)); |
|
723 } /* end write_..._psif_qp_state(psif_qp_state data) */ |
|
724 |
|
725 /* Convert enum psif_cmpl_outstanding_error to string */ |
|
726 const char *string_enum_psif_cmpl_outstanding_error(enum psif_cmpl_outstanding_error val) |
|
727 { |
|
728 switch (val) { |
|
729 case CMPL_NO_ERROR: |
|
730 return "CMPL_NO_ERROR"; |
|
731 case CMPL_RQS_INVALID_REQUEST_ERR: |
|
732 return "CMPL_RQS_INVALID_REQUEST_ERR"; |
|
733 case CMPL_RQS_QP_IN_WRONG_STATE_ERR: |
|
734 return "CMPL_RQS_QP_IN_WRONG_STATE_ERR"; |
|
735 case CMPL_RQS_MAX_OUTSTANDING_REACHED_ERR: |
|
736 return "CMPL_RQS_MAX_OUTSTANDING_REACHED_ERR"; |
|
737 case CMPL_RQS_REQUEST_FENCED_ERR: |
|
738 return "CMPL_RQS_REQUEST_FENCED_ERR"; |
|
739 case CMPL_RQS_CMD_FROM_EPS_ERR: |
|
740 return "CMPL_RQS_CMD_FROM_EPS_ERR"; |
|
741 case CMPL_DMA_SGL_RD_ERR: |
|
742 return "CMPL_DMA_SGL_RD_ERR"; |
|
743 case CMPL_DMA_PYLD_RD_ERR: |
|
744 return "CMPL_DMA_PYLD_RD_ERR"; |
|
745 case CMPL_DMA_SGL_LENGTH_ERR: |
|
746 return "CMPL_DMA_SGL_LENGTH_ERR"; |
|
747 case CMPL_DMA_LKEY_ERR: |
|
748 return "CMPL_DMA_LKEY_ERR"; |
|
749 default: |
|
750 return "UNKNOWN_psif_cmpl_outstanding_error"; |
|
751 } |
|
752 } |
|
753 |
|
754 void write_enum_psif_cmpl_outstanding_error(XFILE *fd, |
|
755 enum psif_cmpl_outstanding_error data) |
|
756 { |
|
757 xprintf(fd, "%s", string_enum_psif_cmpl_outstanding_error(data)); |
|
758 } /* end write_..._psif_cmpl_outstanding_error(psif_cmpl_outstanding_error data) */ |
|
759 |
|
760 /* Convert enum psif_expected_op to string */ |
|
761 const char *string_enum_psif_expected_op(enum psif_expected_op val) |
|
762 { |
|
763 switch (val) { |
|
764 case NO_OPERATION_IN_PROGRESS: |
|
765 return "NO_OPERATION_IN_PROGRESS"; |
|
766 case EXPECT_SEND_MIDDLE_LAST: |
|
767 return "EXPECT_SEND_MIDDLE_LAST"; |
|
768 case EXPECT_RDMA_WR_MIDDLE_LAST: |
|
769 return "EXPECT_RDMA_WR_MIDDLE_LAST"; |
|
770 case EXPECT_DM_PUT_MIDDLE_LAST: |
|
771 return "EXPECT_DM_PUT_MIDDLE_LAST"; |
|
772 default: |
|
773 return "UNKNOWN_psif_expected_op"; |
|
774 } |
|
775 } |
|
776 |
|
777 void write_enum_psif_expected_op(XFILE *fd, |
|
778 enum psif_expected_op data) |
|
779 { |
|
780 xprintf(fd, "%s", string_enum_psif_expected_op(data)); |
|
781 } /* end write_..._psif_expected_op(psif_expected_op data) */ |
|
782 |
|
783 /* Convert enum psif_migration to string */ |
|
784 const char *string_enum_psif_migration(enum psif_migration val) |
|
785 { |
|
786 switch (val) { |
|
787 case APM_OFF: |
|
788 return "APM_OFF"; |
|
789 case APM_MIGRATED: |
|
790 return "APM_MIGRATED"; |
|
791 case APM_REARM: |
|
792 return "APM_REARM"; |
|
793 case APM_ARMED: |
|
794 return "APM_ARMED"; |
|
795 default: |
|
796 return "UNKNOWN_psif_migration"; |
|
797 } |
|
798 } |
|
799 |
|
800 void write_enum_psif_migration(XFILE *fd, |
|
801 enum psif_migration data) |
|
802 { |
|
803 xprintf(fd, "%s", string_enum_psif_migration(data)); |
|
804 } /* end write_..._psif_migration(psif_migration data) */ |
|
805 |
|
806 /* Convert enum psif_qp_trans to string */ |
|
807 const char *string_enum_psif_qp_trans(enum psif_qp_trans val) |
|
808 { |
|
809 switch (val) { |
|
810 case PSIF_QP_TRANSPORT_RC: |
|
811 return "PSIF_QP_TRANSPORT_RC"; |
|
812 case PSIF_QP_TRANSPORT_UC: |
|
813 return "PSIF_QP_TRANSPORT_UC"; |
|
814 case PSIF_QP_TRANSPORT_RD: |
|
815 return "PSIF_QP_TRANSPORT_RD"; |
|
816 case PSIF_QP_TRANSPORT_UD: |
|
817 return "PSIF_QP_TRANSPORT_UD"; |
|
818 case PSIF_QP_TRANSPORT_RSVD1: |
|
819 return "PSIF_QP_TRANSPORT_RSVD1"; |
|
820 case PSIF_QP_TRANSPORT_XRC: |
|
821 return "PSIF_QP_TRANSPORT_XRC"; |
|
822 case PSIF_QP_TRANSPORT_MANSP1: |
|
823 return "PSIF_QP_TRANSPORT_MANSP1"; |
|
824 case PSIF_QP_TRANSPORT_MANSP2: |
|
825 return "PSIF_QP_TRANSPORT_MANSP2"; |
|
826 default: |
|
827 return "UNKNOWN_psif_qp_trans"; |
|
828 } |
|
829 } |
|
830 |
|
831 void write_enum_psif_qp_trans(XFILE *fd, |
|
832 enum psif_qp_trans data) |
|
833 { |
|
834 xprintf(fd, "%s", string_enum_psif_qp_trans(data)); |
|
835 } /* end write_..._psif_qp_trans(psif_qp_trans data) */ |
|
836 |
|
837 /* Convert enum psif_bool to string */ |
|
838 const char *string_enum_psif_bool(enum psif_bool val) |
|
839 { |
|
840 switch (val) { |
|
841 case FALSE: |
|
842 return "FALSE"; |
|
843 case TRUE: |
|
844 return "TRUE"; |
|
845 default: |
|
846 return "UNKNOWN_psif_bool"; |
|
847 } |
|
848 } |
|
849 |
|
850 void write_enum_psif_bool(XFILE *fd, |
|
851 enum psif_bool data) |
|
852 { |
|
853 xprintf(fd, "%s", string_enum_psif_bool(data)); |
|
854 } /* end write_..._psif_bool(psif_bool data) */ |
|
855 |
|
856 /* Convert enum psif_eoib_type to string */ |
|
857 const char *string_enum_psif_eoib_type(enum psif_eoib_type val) |
|
858 { |
|
859 switch (val) { |
|
860 case EOIB_FULL: |
|
861 return "EOIB_FULL"; |
|
862 case EOIB_PARTIAL: |
|
863 return "EOIB_PARTIAL"; |
|
864 case EOIB_QKEY_ONLY: |
|
865 return "EOIB_QKEY_ONLY"; |
|
866 case EOIB_NONE: |
|
867 return "EOIB_NONE"; |
|
868 default: |
|
869 return "UNKNOWN_psif_eoib_type"; |
|
870 } |
|
871 } |
|
872 |
|
873 void write_enum_psif_eoib_type(XFILE *fd, |
|
874 enum psif_eoib_type data) |
|
875 { |
|
876 xprintf(fd, "%s", string_enum_psif_eoib_type(data)); |
|
877 } /* end write_..._psif_eoib_type(psif_eoib_type data) */ |
|
878 |
|
879 /* Convert enum psif_comm_live to string */ |
|
880 const char *string_enum_psif_comm_live(enum psif_comm_live val) |
|
881 { |
|
882 switch (val) { |
|
883 case NO_COMM_ESTABLISHED: |
|
884 return "NO_COMM_ESTABLISHED"; |
|
885 case COMM_ESTABLISHED: |
|
886 return "COMM_ESTABLISHED"; |
|
887 default: |
|
888 return "UNKNOWN_psif_comm_live"; |
|
889 } |
|
890 } |
|
891 |
|
892 void write_enum_psif_comm_live(XFILE *fd, |
|
893 enum psif_comm_live data) |
|
894 { |
|
895 xprintf(fd, "%s", string_enum_psif_comm_live(data)); |
|
896 } /* end write_..._psif_comm_live(psif_comm_live data) */ |
|
897 |
|
898 /* Convert enum psif_path_mtu to string */ |
|
899 const char *string_enum_psif_path_mtu(enum psif_path_mtu val) |
|
900 { |
|
901 switch (val) { |
|
902 case MTU_INVALID: |
|
903 return "MTU_INVALID"; |
|
904 case MTU_256B: |
|
905 return "MTU_256B"; |
|
906 case MTU_512B: |
|
907 return "MTU_512B"; |
|
908 case MTU_1024B: |
|
909 return "MTU_1024B"; |
|
910 case MTU_2048B: |
|
911 return "MTU_2048B"; |
|
912 case MTU_4096B: |
|
913 return "MTU_4096B"; |
|
914 case MTU_10240B: |
|
915 return "MTU_10240B"; |
|
916 case MTU_XXX: |
|
917 return "MTU_XXX"; |
|
918 default: |
|
919 return "UNKNOWN_psif_path_mtu"; |
|
920 } |
|
921 } |
|
922 |
|
923 void write_enum_psif_path_mtu(XFILE *fd, |
|
924 enum psif_path_mtu data) |
|
925 { |
|
926 xprintf(fd, "%s", string_enum_psif_path_mtu(data)); |
|
927 } /* end write_..._psif_path_mtu(psif_path_mtu data) */ |
|
928 |
|
929 /* Convert enum psif_use_grh to string */ |
|
930 const char *string_enum_psif_use_grh(enum psif_use_grh val) |
|
931 { |
|
932 switch (val) { |
|
933 case NO_GRH: |
|
934 return "NO_GRH"; |
|
935 case USE_GRH: |
|
936 return "USE_GRH"; |
|
937 default: |
|
938 return "UNKNOWN_psif_use_grh"; |
|
939 } |
|
940 } |
|
941 |
|
942 void write_enum_psif_use_grh(XFILE *fd, |
|
943 enum psif_use_grh data) |
|
944 { |
|
945 xprintf(fd, "%s", string_enum_psif_use_grh(data)); |
|
946 } /* end write_..._psif_use_grh(psif_use_grh data) */ |
|
947 |
|
948 /* Convert enum psif_loopback to string */ |
|
949 const char *string_enum_psif_loopback(enum psif_loopback val) |
|
950 { |
|
951 switch (val) { |
|
952 case NO_LOOPBACK: |
|
953 return "NO_LOOPBACK"; |
|
954 case LOOPBACK: |
|
955 return "LOOPBACK"; |
|
956 default: |
|
957 return "UNKNOWN_psif_loopback"; |
|
958 } |
|
959 } |
|
960 |
|
961 void write_enum_psif_loopback(XFILE *fd, |
|
962 enum psif_loopback data) |
|
963 { |
|
964 xprintf(fd, "%s", string_enum_psif_loopback(data)); |
|
965 } /* end write_..._psif_loopback(psif_loopback data) */ |
|
966 |
|
967 /* Convert enum psif_qp_command to string */ |
|
968 const char *string_enum_psif_qp_command(enum psif_qp_command val) |
|
969 { |
|
970 switch (val) { |
|
971 case QP_CMD_INVALID: |
|
972 return "QP_CMD_INVALID"; |
|
973 case QP_CMD_MODIFY: |
|
974 return "QP_CMD_MODIFY"; |
|
975 case QP_CMD_QUERY: |
|
976 return "QP_CMD_QUERY"; |
|
977 case QP_CMD_CHECK_TIMEOUT: |
|
978 return "QP_CMD_CHECK_TIMEOUT"; |
|
979 default: |
|
980 return "UNKNOWN_psif_qp_command"; |
|
981 } |
|
982 } |
|
983 |
|
984 void write_enum_psif_qp_command(XFILE *fd, |
|
985 enum psif_qp_command data) |
|
986 { |
|
987 xprintf(fd, "%s", string_enum_psif_qp_command(data)); |
|
988 } /* end write_..._psif_qp_command(psif_qp_command data) */ |
|
989 |
|
990 /* Convert enum psif_mbox_type to string */ |
|
991 const char *string_enum_psif_mbox_type(enum psif_mbox_type val) |
|
992 { |
|
993 switch (val) { |
|
994 case MBOX_EPSA0: |
|
995 return "MBOX_EPSA0"; |
|
996 case MBOX_EPSA1: |
|
997 return "MBOX_EPSA1"; |
|
998 case MBOX_EPSA2: |
|
999 return "MBOX_EPSA2"; |
|
1000 case MBOX_EPSA3: |
|
1001 return "MBOX_EPSA3"; |
|
1002 case MBOX_EPSC: |
|
1003 return "MBOX_EPSC"; |
|
1004 case MBOX_EPS_MAX: |
|
1005 return "MBOX_EPS_MAX"; |
|
1006 case PSIF_MBOX_TYPE_FIELD_MAX: |
|
1007 return "PSIF_MBOX_TYPE_FIELD_MAX"; |
|
1008 default: |
|
1009 return "UNKNOWN_psif_mbox_type"; |
|
1010 } |
|
1011 } |
|
1012 |
|
1013 void write_enum_psif_mbox_type(XFILE *fd, |
|
1014 enum psif_mbox_type data) |
|
1015 { |
|
1016 xprintf(fd, "%s", string_enum_psif_mbox_type(data)); |
|
1017 } /* end write_..._psif_mbox_type(psif_mbox_type data) */ |
|
1018 |
|
1019 /* Convert enum psif_dma_vt_key_states to string */ |
|
1020 const char *string_enum_psif_dma_vt_key_states(enum psif_dma_vt_key_states val) |
|
1021 { |
|
1022 switch (val) { |
|
1023 case PSIF_DMA_KEY_INVALID: |
|
1024 return "PSIF_DMA_KEY_INVALID"; |
|
1025 case PSIF_DMA_KEY_FREE: |
|
1026 return "PSIF_DMA_KEY_FREE"; |
|
1027 case PSIF_DMA_KEY_VALID: |
|
1028 return "PSIF_DMA_KEY_VALID"; |
|
1029 case PSIF_DMA_KEY_MMU_VALID: |
|
1030 return "PSIF_DMA_KEY_MMU_VALID"; |
|
1031 default: |
|
1032 return "UNKNOWN_psif_dma_vt_key_states"; |
|
1033 } |
|
1034 } |
|
1035 |
|
1036 void write_enum_psif_dma_vt_key_states(XFILE *fd, |
|
1037 enum psif_dma_vt_key_states data) |
|
1038 { |
|
1039 xprintf(fd, "%s", string_enum_psif_dma_vt_key_states(data)); |
|
1040 } /* end write_..._psif_dma_vt_key_states(psif_dma_vt_key_states data) */ |
|
1041 |
|
1042 /* Convert enum psif_flash_image_type to string */ |
|
1043 const char *string_enum_psif_flash_image_type(enum psif_flash_image_type val) |
|
1044 { |
|
1045 switch (val) { |
|
1046 case PSIF_IMAGE_INVALID: |
|
1047 return "PSIF_IMAGE_INVALID"; |
|
1048 case PSIF_IMAGE_BOOT_LOADER: |
|
1049 return "PSIF_IMAGE_BOOT_LOADER"; |
|
1050 case PSIF_IMAGE_EPS_C_APPLICATION: |
|
1051 return "PSIF_IMAGE_EPS_C_APPLICATION"; |
|
1052 case PSIF_IMAGE_EPS_A_APPLICATION: |
|
1053 return "PSIF_IMAGE_EPS_A_APPLICATION"; |
|
1054 case PSIF_IMAGE_DIAGNOSTICS: |
|
1055 return "PSIF_IMAGE_DIAGNOSTICS"; |
|
1056 case PSIF_FLASH_IMAGE_TYPE_FIELD_MAX: |
|
1057 return "PSIF_FLASH_IMAGE_TYPE_FIELD_MAX"; |
|
1058 default: |
|
1059 return "UNKNOWN_psif_flash_image_type"; |
|
1060 } |
|
1061 } |
|
1062 |
|
1063 void write_enum_psif_flash_image_type(XFILE *fd, |
|
1064 enum psif_flash_image_type data) |
|
1065 { |
|
1066 xprintf(fd, "%s", string_enum_psif_flash_image_type(data)); |
|
1067 } /* end write_..._psif_flash_image_type(psif_flash_image_type data) */ |
|
1068 |
|
1069 /* Convert enum psif_event to string */ |
|
1070 const char *string_enum_psif_event(enum psif_event val) |
|
1071 { |
|
1072 switch (val) { |
|
1073 case PSIF_EVENT_NO_CHANGE: |
|
1074 return "PSIF_EVENT_NO_CHANGE"; |
|
1075 case PSIF_EVENT_SGID_TABLE_CHANGED: |
|
1076 return "PSIF_EVENT_SGID_TABLE_CHANGED"; |
|
1077 case PSIF_EVENT_PKEY_TABLE_CHANGED: |
|
1078 return "PSIF_EVENT_PKEY_TABLE_CHANGED"; |
|
1079 case PSIF_EVENT_MASTER_SM_LID_CHANGED: |
|
1080 return "PSIF_EVENT_MASTER_SM_LID_CHANGED"; |
|
1081 case PSIF_EVENT_MASTER_SM_SL_CHANGED: |
|
1082 return "PSIF_EVENT_MASTER_SM_SL_CHANGED"; |
|
1083 case PSIF_EVENT_SUBNET_TIMEOUT_CHANGED: |
|
1084 return "PSIF_EVENT_SUBNET_TIMEOUT_CHANGED"; |
|
1085 case PSIF_EVENT_IS_SM_DISABLED_CHANGED: |
|
1086 return "PSIF_EVENT_IS_SM_DISABLED_CHANGED"; |
|
1087 case PSIF_EVENT_CLIENT_REREGISTER: |
|
1088 return "PSIF_EVENT_CLIENT_REREGISTER"; |
|
1089 case PSIF_EVENT_LID_TABLE_CHANGED: |
|
1090 return "PSIF_EVENT_LID_TABLE_CHANGED"; |
|
1091 case PSIF_EVENT_EPSC_COMPLETION: |
|
1092 return "PSIF_EVENT_EPSC_COMPLETION"; |
|
1093 case PSIF_EVENT_MAILBOX: |
|
1094 return "PSIF_EVENT_MAILBOX"; |
|
1095 case PSIF_EVENT_EXTENSION: |
|
1096 return "PSIF_EVENT_EXTENSION"; |
|
1097 case PSIF_EVENT_LOG: |
|
1098 return "PSIF_EVENT_LOG"; |
|
1099 case PSIF_EVENT_PORT_ACTIVE: |
|
1100 return "PSIF_EVENT_PORT_ACTIVE"; |
|
1101 case PSIF_EVENT_PORT_ERR: |
|
1102 return "PSIF_EVENT_PORT_ERR"; |
|
1103 case PSIF_EVENT_QUEUE_FULL: |
|
1104 return "PSIF_EVENT_QUEUE_FULL"; |
|
1105 case PSIF_EVENT_DEGRADED_MODE: |
|
1106 return "PSIF_EVENT_DEGRADED_MODE"; |
|
1107 case PSIF_EVENT_EPSC_KEEP_ALIVE: |
|
1108 return "PSIF_EVENT_EPSC_KEEP_ALIVE"; |
|
1109 case PSIF_EVENT_EPSC_MMU_FLUSH_DONE: |
|
1110 return "PSIF_EVENT_EPSC_MMU_FLUSH_DONE"; |
|
1111 case PSIF_EVENT_FIELD_MAX: |
|
1112 return "PSIF_EVENT_FIELD_MAX"; |
|
1113 default: |
|
1114 return "UNKNOWN_psif_event"; |
|
1115 } |
|
1116 } |
|
1117 |
|
1118 void write_enum_psif_event(XFILE *fd, |
|
1119 enum psif_event data) |
|
1120 { |
|
1121 xprintf(fd, "%s", string_enum_psif_event(data)); |
|
1122 } /* end write_..._psif_event(psif_event data) */ |
|
1123 |
|
1124 /* Convert enum psif_tsu_error_types to string */ |
|
1125 const char *string_enum_psif_tsu_error_types(enum psif_tsu_error_types val) |
|
1126 { |
|
1127 switch (val) { |
|
1128 case TSU_NO_ERROR: |
|
1129 return "TSU_NO_ERROR"; |
|
1130 case TSU_IBPR_ICRC_ERR: |
|
1131 return "TSU_IBPR_ICRC_ERR"; |
|
1132 case TSU_IBPR_INVALID_PKEY_ERR: |
|
1133 return "TSU_IBPR_INVALID_PKEY_ERR"; |
|
1134 case TSU_IBPR_INVALID_QP_ERR: |
|
1135 return "TSU_IBPR_INVALID_QP_ERR"; |
|
1136 case TSU_IBPR_VSWITCH_UF_ERR: |
|
1137 return "TSU_IBPR_VSWITCH_UF_ERR"; |
|
1138 case TSU_IBPR_PKTLEN_ERR: |
|
1139 return "TSU_IBPR_PKTLEN_ERR"; |
|
1140 case TSU_IBPR_UNDEFINED_OPCODE_ERR: |
|
1141 return "TSU_IBPR_UNDEFINED_OPCODE_ERR"; |
|
1142 case TSU_IBPR_MCAST_NO_GRH_ERR: |
|
1143 return "TSU_IBPR_MCAST_NO_GRH_ERR"; |
|
1144 case TSU_IBPR_MCAST_NO_TARGET_ERR: |
|
1145 return "TSU_IBPR_MCAST_NO_TARGET_ERR"; |
|
1146 case TSU_IBPR_INVALID_DGID_ERR: |
|
1147 return "TSU_IBPR_INVALID_DGID_ERR"; |
|
1148 case TSU_IBPR_BADPKT_ERR: |
|
1149 return "TSU_IBPR_BADPKT_ERR"; |
|
1150 case TSU_RCV_QP_INVALID_ERR: |
|
1151 return "TSU_RCV_QP_INVALID_ERR"; |
|
1152 case TSU_RCV_HDR_BTH_TVER_ERR: |
|
1153 return "TSU_RCV_HDR_BTH_TVER_ERR"; |
|
1154 case TSU_RCV_HDR_BTH_QP_ERR: |
|
1155 return "TSU_RCV_HDR_BTH_QP_ERR"; |
|
1156 case TSU_RCV_HDR_GRH_ERR: |
|
1157 return "TSU_RCV_HDR_GRH_ERR"; |
|
1158 case TSU_RCV_HDR_PKEY_ERR: |
|
1159 return "TSU_RCV_HDR_PKEY_ERR"; |
|
1160 case TSU_RCV_HDR_QKEY_ERR: |
|
1161 return "TSU_RCV_HDR_QKEY_ERR"; |
|
1162 case TSU_RCV_HDR_LID_ERR: |
|
1163 return "TSU_RCV_HDR_LID_ERR"; |
|
1164 case TSU_RCV_HDR_MAD_ERR: |
|
1165 return "TSU_RCV_HDR_MAD_ERR"; |
|
1166 case TSU_RCV_EOIB_MCAST_ERR: |
|
1167 return "TSU_RCV_EOIB_MCAST_ERR"; |
|
1168 case TSU_RCV_EOIB_BCAST_ERR: |
|
1169 return "TSU_RCV_EOIB_BCAST_ERR"; |
|
1170 case TSU_RCV_EOIB_UCAST_ERR: |
|
1171 return "TSU_RCV_EOIB_UCAST_ERR"; |
|
1172 case TSU_RCV_EOIB_TCP_PORT_VIOLATION_ERR: |
|
1173 return "TSU_RCV_EOIB_TCP_PORT_VIOLATION_ERR"; |
|
1174 case TSU_RCV_EOIB_RUNTS_ERR: |
|
1175 return "TSU_RCV_EOIB_RUNTS_ERR"; |
|
1176 case TSU_RCV_EOIB_OUTER_VLAN_ERR: |
|
1177 return "TSU_RCV_EOIB_OUTER_VLAN_ERR"; |
|
1178 case TSU_RCV_EOIB_VLAN_TAG_ERR: |
|
1179 return "TSU_RCV_EOIB_VLAN_TAG_ERR"; |
|
1180 case TSU_RCV_EOIB_VID_ERR: |
|
1181 return "TSU_RCV_EOIB_VID_ERR"; |
|
1182 case TSU_RCV_IPOIB_TCP_PORT_VIOLATION_ERR: |
|
1183 return "TSU_RCV_IPOIB_TCP_PORT_VIOLATION_ERR"; |
|
1184 case TSU_RCV_MCAST_DUP_ERR: |
|
1185 return "TSU_RCV_MCAST_DUP_ERR"; |
|
1186 case TSU_RCV_ECC_ERR: |
|
1187 return "TSU_RCV_ECC_ERR"; |
|
1188 case TSU_DSCR_RESPONDER_RC_PSN_ERR: |
|
1189 return "TSU_DSCR_RESPONDER_RC_PSN_ERR"; |
|
1190 case TSU_DSCR_RESPONDER_RC_DUPLICATE: |
|
1191 return "TSU_DSCR_RESPONDER_RC_DUPLICATE"; |
|
1192 case TSU_DSCR_RESPONDER_RC_OPCODE_SEQ_ERR: |
|
1193 return "TSU_DSCR_RESPONDER_RC_OPCODE_SEQ_ERR"; |
|
1194 case TSU_DSCR_RESPONDER_RC_OPCODE_VAL_ERR: |
|
1195 return "TSU_DSCR_RESPONDER_RC_OPCODE_VAL_ERR"; |
|
1196 case TSU_DSCR_RESPONDER_RC_OPCODE_LEN_ERR: |
|
1197 return "TSU_DSCR_RESPONDER_RC_OPCODE_LEN_ERR"; |
|
1198 case TSU_DSCR_RESPONDER_RC_DMALEN_ERR: |
|
1199 return "TSU_DSCR_RESPONDER_RC_DMALEN_ERR"; |
|
1200 case TSU_DSCR_RESPONDER_XRC_PSN_ERR: |
|
1201 return "TSU_DSCR_RESPONDER_XRC_PSN_ERR"; |
|
1202 case TSU_DSCR_RESPONDER_XRC_DUPLICATE: |
|
1203 return "TSU_DSCR_RESPONDER_XRC_DUPLICATE"; |
|
1204 case TSU_DSCR_RESPONDER_XRC_OPCODE_SEQ_ERR: |
|
1205 return "TSU_DSCR_RESPONDER_XRC_OPCODE_SEQ_ERR"; |
|
1206 case TSU_DSCR_RESPONDER_XRC_OPCODE_VAL_ERR: |
|
1207 return "TSU_DSCR_RESPONDER_XRC_OPCODE_VAL_ERR"; |
|
1208 case TSU_DSCR_RESPONDER_XRC_OPCODE_LEN_ERR: |
|
1209 return "TSU_DSCR_RESPONDER_XRC_OPCODE_LEN_ERR"; |
|
1210 case TSU_DSCR_RESPONDER_XRC_DMALEN_ERR: |
|
1211 return "TSU_DSCR_RESPONDER_XRC_DMALEN_ERR"; |
|
1212 case TSU_DSCR_RESPONDER_UC_PSN_ERR: |
|
1213 return "TSU_DSCR_RESPONDER_UC_PSN_ERR"; |
|
1214 case TSU_DSCR_RESPONDER_UC_OPCODE_SEQ_ERR: |
|
1215 return "TSU_DSCR_RESPONDER_UC_OPCODE_SEQ_ERR"; |
|
1216 case TSU_DSCR_RESPONDER_UC_OPCODE_VAL_ERR: |
|
1217 return "TSU_DSCR_RESPONDER_UC_OPCODE_VAL_ERR"; |
|
1218 case TSU_DSCR_RESPONDER_UC_OPCODE_LEN_ERR: |
|
1219 return "TSU_DSCR_RESPONDER_UC_OPCODE_LEN_ERR"; |
|
1220 case TSU_DSCR_RESPONDER_UC_DMALEN_ERR: |
|
1221 return "TSU_DSCR_RESPONDER_UC_DMALEN_ERR"; |
|
1222 case TSU_DSCR_RESPONDER_UD_OPCODE_LEN_ERR: |
|
1223 return "TSU_DSCR_RESPONDER_UD_OPCODE_LEN_ERR"; |
|
1224 case TSU_DSCR_RESPONDER_DUPLICATE_WITH_ERR: |
|
1225 return "TSU_DSCR_RESPONDER_DUPLICATE_WITH_ERR"; |
|
1226 case TSU_DSCR_QP_CAP_MASKED_ATOMIC_ENABLE_ERR: |
|
1227 return "TSU_DSCR_QP_CAP_MASKED_ATOMIC_ENABLE_ERR"; |
|
1228 case TSU_DSCR_QP_CAP_RDMA_RD_ENABLE_ERR: |
|
1229 return "TSU_DSCR_QP_CAP_RDMA_RD_ENABLE_ERR"; |
|
1230 case TSU_DSCR_QP_CAP_RDMA_WR_ENABLE_ERR: |
|
1231 return "TSU_DSCR_QP_CAP_RDMA_WR_ENABLE_ERR"; |
|
1232 case TSU_DSCR_QP_CAP_ATOMIC_ENABLE_ERR: |
|
1233 return "TSU_DSCR_QP_CAP_ATOMIC_ENABLE_ERR"; |
|
1234 case TSU_DSCR_XRC_DOMAIN_VIOLATION_ERR: |
|
1235 return "TSU_DSCR_XRC_DOMAIN_VIOLATION_ERR"; |
|
1236 case TSU_DSCR_XRCETH_ERR: |
|
1237 return "TSU_DSCR_XRCETH_ERR"; |
|
1238 case TSU_DSCR_RQ_INVALID_ERR: |
|
1239 return "TSU_DSCR_RQ_INVALID_ERR"; |
|
1240 case TSU_DSCR_RQ_PD_CHECK_ERR: |
|
1241 return "TSU_DSCR_RQ_PD_CHECK_ERR"; |
|
1242 case TSU_DSCR_RQ_EMPTY_ERR: |
|
1243 return "TSU_DSCR_RQ_EMPTY_ERR"; |
|
1244 case TSU_DSCR_RQ_IN_ERROR_ERR: |
|
1245 return "TSU_DSCR_RQ_IN_ERROR_ERR"; |
|
1246 case TSU_DSCR_TRANSLATION_TYPE_ERR: |
|
1247 return "TSU_DSCR_TRANSLATION_TYPE_ERR"; |
|
1248 case TSU_DSCR_RQ_DESCRIPTOR_INCONSISTENT_ERR: |
|
1249 return "TSU_DSCR_RQ_DESCRIPTOR_INCONSISTENT_ERR"; |
|
1250 case TSU_DSCR_MISALIGNED_ATOMIC_ERR: |
|
1251 return "TSU_DSCR_MISALIGNED_ATOMIC_ERR"; |
|
1252 case TSU_DSCR_PCIE_ERR: |
|
1253 return "TSU_DSCR_PCIE_ERR"; |
|
1254 case TSU_DSCR_ECC_ERR: |
|
1255 return "TSU_DSCR_ECC_ERR"; |
|
1256 case TSU_RQH_PCIE_ERR: |
|
1257 return "TSU_RQH_PCIE_ERR"; |
|
1258 case TSU_RQH_SGL_LKEY_ERR: |
|
1259 return "TSU_RQH_SGL_LKEY_ERR"; |
|
1260 case TSU_RQH_NOT_ENOUGH_RQ_SPACE_ERR: |
|
1261 return "TSU_RQH_NOT_ENOUGH_RQ_SPACE_ERR"; |
|
1262 case TSU_RQH_ECC_ERR: |
|
1263 return "TSU_RQH_ECC_ERR"; |
|
1264 case TSU_VAL_DUPLICATE_WITH_ERR: |
|
1265 return "TSU_VAL_DUPLICATE_WITH_ERR"; |
|
1266 case TSU_VAL_RKEY_VLD_ERR: |
|
1267 return "TSU_VAL_RKEY_VLD_ERR"; |
|
1268 case TSU_VAL_RKEY_ADDR_RANGE_ERR: |
|
1269 return "TSU_VAL_RKEY_ADDR_RANGE_ERR"; |
|
1270 case TSU_VAL_RKEY_ACCESS_ERR: |
|
1271 return "TSU_VAL_RKEY_ACCESS_ERR"; |
|
1272 case TSU_VAL_RKEY_PD_ERR: |
|
1273 return "TSU_VAL_RKEY_PD_ERR"; |
|
1274 case TSU_VAL_RKEY_RANGE_ERR: |
|
1275 return "TSU_VAL_RKEY_RANGE_ERR"; |
|
1276 case TSU_VAL_LKEY_VLD_ERR: |
|
1277 return "TSU_VAL_LKEY_VLD_ERR"; |
|
1278 case TSU_VAL_LKEY_ADDR_RANGE_ERR: |
|
1279 return "TSU_VAL_LKEY_ADDR_RANGE_ERR"; |
|
1280 case TSU_VAL_LKEY_ACCESS_ERR: |
|
1281 return "TSU_VAL_LKEY_ACCESS_ERR"; |
|
1282 case TSU_VAL_LKEY_PD_ERR: |
|
1283 return "TSU_VAL_LKEY_PD_ERR"; |
|
1284 case TSU_VAL_LKEY_RANGE_ERR: |
|
1285 return "TSU_VAL_LKEY_RANGE_ERR"; |
|
1286 case TSU_VAL_TRANSLATION_TYPE_ERR: |
|
1287 return "TSU_VAL_TRANSLATION_TYPE_ERR"; |
|
1288 case TSU_VAL_PCIE_ERR: |
|
1289 return "TSU_VAL_PCIE_ERR"; |
|
1290 case TSU_VAL_ECC_ERR: |
|
1291 return "TSU_VAL_ECC_ERR"; |
|
1292 case TSU_MMU_DUPLICATE_WITH_ERR: |
|
1293 return "TSU_MMU_DUPLICATE_WITH_ERR"; |
|
1294 case TSU_MMU_PTW_ERR: |
|
1295 return "TSU_MMU_PTW_ERR"; |
|
1296 case TSU_MMU_UF_ERR: |
|
1297 return "TSU_MMU_UF_ERR"; |
|
1298 case TSU_MMU_AC_ERR: |
|
1299 return "TSU_MMU_AC_ERR"; |
|
1300 case TSU_MMU_ECC_ERR: |
|
1301 return "TSU_MMU_ECC_ERR"; |
|
1302 case TSU_CBLD_CQ_INVALID_ERR: |
|
1303 return "TSU_CBLD_CQ_INVALID_ERR"; |
|
1304 case TSU_CBLD_CQ_FULL_ERR: |
|
1305 return "TSU_CBLD_CQ_FULL_ERR"; |
|
1306 case TSU_CBLD_CQ_ALREADY_IN_ERR: |
|
1307 return "TSU_CBLD_CQ_ALREADY_IN_ERR"; |
|
1308 case TSU_CBLD_CQ_IS_PROXY_ERR: |
|
1309 return "TSU_CBLD_CQ_IS_PROXY_ERR"; |
|
1310 case TSU_CBLD_TRANSLATION_TYPE_ERR: |
|
1311 return "TSU_CBLD_TRANSLATION_TYPE_ERR"; |
|
1312 case TSU_CBLD_CQ_DESCRIPTOR_INCONSISTENT_ERR: |
|
1313 return "TSU_CBLD_CQ_DESCRIPTOR_INCONSISTENT_ERR"; |
|
1314 case TSU_CBLD_ECC_ERR: |
|
1315 return "TSU_CBLD_ECC_ERR"; |
|
1316 case TSU_CBLD_PCIE_ERR: |
|
1317 return "TSU_CBLD_PCIE_ERR"; |
|
1318 case TSU_CBLD_QP_ERR: |
|
1319 return "TSU_CBLD_QP_ERR"; |
|
1320 case TSU_RQS_CHECKSUM_ERR: |
|
1321 return "TSU_RQS_CHECKSUM_ERR"; |
|
1322 case TSU_RQS_SEQNUM_ERR: |
|
1323 return "TSU_RQS_SEQNUM_ERR"; |
|
1324 case TSU_RQS_INVALID_REQUEST_ERR: |
|
1325 return "TSU_RQS_INVALID_REQUEST_ERR"; |
|
1326 case TSU_RQS_QP_IN_WRONG_STATE_ERR: |
|
1327 return "TSU_RQS_QP_IN_WRONG_STATE_ERR"; |
|
1328 case TSU_RQS_STOP_TIMER_ERR: |
|
1329 return "TSU_RQS_STOP_TIMER_ERR"; |
|
1330 case TSU_RQS_CMD_FROM_EPS_ERR: |
|
1331 return "TSU_RQS_CMD_FROM_EPS_ERR"; |
|
1332 case TSU_RQS_SQ_FLUSH_ERR: |
|
1333 return "TSU_RQS_SQ_FLUSH_ERR"; |
|
1334 case TSU_RQS_SMP_NOT_AUTH_ERR: |
|
1335 return "TSU_RQS_SMP_NOT_AUTH_ERR"; |
|
1336 case TSU_RQS_REQUEST_FENCED_ERR: |
|
1337 return "TSU_RQS_REQUEST_FENCED_ERR"; |
|
1338 case TSU_RQS_MAX_OUTSTANDING_REACHED_ERR: |
|
1339 return "TSU_RQS_MAX_OUTSTANDING_REACHED_ERR"; |
|
1340 case TSU_RQS_ECC_ERR: |
|
1341 return "TSU_RQS_ECC_ERR"; |
|
1342 case TSU_RQS_EOIB_QKEY_VIOLATION: |
|
1343 return "TSU_RQS_EOIB_QKEY_VIOLATION"; |
|
1344 case TSU_RQS_IPOIB_QKEY_VIOLATION: |
|
1345 return "TSU_RQS_IPOIB_QKEY_VIOLATION"; |
|
1346 case TSU_RQS_EOIB_MODE_VIOLATION: |
|
1347 return "TSU_RQS_EOIB_MODE_VIOLATION"; |
|
1348 case TSU_RQS_MISCONFIGURED_QP: |
|
1349 return "TSU_RQS_MISCONFIGURED_QP"; |
|
1350 case TSU_RQS_PORT_AUTH_VIOLATION: |
|
1351 return "TSU_RQS_PORT_AUTH_VIOLATION"; |
|
1352 case TSU_DMA_SGL_RD_ERR: |
|
1353 return "TSU_DMA_SGL_RD_ERR"; |
|
1354 case TSU_DMA_REQ_PYLD_RD_ERR: |
|
1355 return "TSU_DMA_REQ_PYLD_RD_ERR"; |
|
1356 case TSU_DMA_RESP_PYLD_RD_ERR: |
|
1357 return "TSU_DMA_RESP_PYLD_RD_ERR"; |
|
1358 case TSU_DMA_SGL_LENGTH_ERR: |
|
1359 return "TSU_DMA_SGL_LENGTH_ERR"; |
|
1360 case TSU_DMA_LKEY_ERR: |
|
1361 return "TSU_DMA_LKEY_ERR"; |
|
1362 case TSU_DMA_RKEY_ERR: |
|
1363 return "TSU_DMA_RKEY_ERR"; |
|
1364 case TSU_DMA_LSO_PKTLEN_ERR: |
|
1365 return "TSU_DMA_LSO_PKTLEN_ERR"; |
|
1366 case TSU_DMA_LSO_ILLEGAL_CLASSIFICATION_ERR: |
|
1367 return "TSU_DMA_LSO_ILLEGAL_CLASSIFICATION_ERR"; |
|
1368 case TSU_DMA_PCIE_ERR: |
|
1369 return "TSU_DMA_PCIE_ERR"; |
|
1370 case TSU_DMA_ECC_ERR: |
|
1371 return "TSU_DMA_ECC_ERR"; |
|
1372 case TSU_CMPL_PCIE_ERR: |
|
1373 return "TSU_CMPL_PCIE_ERR"; |
|
1374 case TSU_CMPL_ECC_ERR: |
|
1375 return "TSU_CMPL_ECC_ERR"; |
|
1376 case TSU_CMPL_REQUESTER_PSN_ERR: |
|
1377 return "TSU_CMPL_REQUESTER_PSN_ERR"; |
|
1378 case TSU_CMPL_REQUESTER_SYNDROME_ERR: |
|
1379 return "TSU_CMPL_REQUESTER_SYNDROME_ERR"; |
|
1380 case TSU_CMPL_REQUESTER_OUTSTANDING_MATCH_ERR: |
|
1381 return "TSU_CMPL_REQUESTER_OUTSTANDING_MATCH_ERR"; |
|
1382 case TSU_CMPL_REQUESTER_LEN_ERR: |
|
1383 return "TSU_CMPL_REQUESTER_LEN_ERR"; |
|
1384 case TSU_CMPL_REQUESTER_UNEXP_OPCODE_ERR: |
|
1385 return "TSU_CMPL_REQUESTER_UNEXP_OPCODE_ERR"; |
|
1386 case TSU_CMPL_REQUESTER_DUPLICATE: |
|
1387 return "TSU_CMPL_REQUESTER_DUPLICATE"; |
|
1388 case TSU_CMPL_RC_IN_ERROR_ERR: |
|
1389 return "TSU_CMPL_RC_IN_ERROR_ERR"; |
|
1390 case TSU_CMPL_NAK_RNR_ERR: |
|
1391 return "TSU_CMPL_NAK_RNR_ERR"; |
|
1392 case TSU_CMPL_NAK_SEQUENCE_ERR: |
|
1393 return "TSU_CMPL_NAK_SEQUENCE_ERR"; |
|
1394 case TSU_CMPL_NAK_INVALID_REQUEST_ERR: |
|
1395 return "TSU_CMPL_NAK_INVALID_REQUEST_ERR"; |
|
1396 case TSU_CMPL_NAK_REMOTE_ACCESS_ERR: |
|
1397 return "TSU_CMPL_NAK_REMOTE_ACCESS_ERR"; |
|
1398 case TSU_CMPL_NAK_REMOTE_OPS_ERR: |
|
1399 return "TSU_CMPL_NAK_REMOTE_OPS_ERR"; |
|
1400 case TSU_CMPL_NAK_INVALID_RD_REQUEST_ERR: |
|
1401 return "TSU_CMPL_NAK_INVALID_RD_REQUEST_ERR"; |
|
1402 case TSU_CMPL_TIMEOUT_ERR: |
|
1403 return "TSU_CMPL_TIMEOUT_ERR"; |
|
1404 case TSU_CMPL_IMPLIED_NAK: |
|
1405 return "TSU_CMPL_IMPLIED_NAK"; |
|
1406 case TSU_CMPL_GHOST_RESP_ERR: |
|
1407 return "TSU_CMPL_GHOST_RESP_ERR"; |
|
1408 default: |
|
1409 return "UNKNOWN_psif_tsu_error_types"; |
|
1410 } |
|
1411 } |
|
1412 |
|
1413 void write_enum_psif_tsu_error_types(XFILE *fd, |
|
1414 enum psif_tsu_error_types data) |
|
1415 { |
|
1416 xprintf(fd, "%s", string_enum_psif_tsu_error_types(data)); |
|
1417 } /* end write_..._psif_tsu_error_types(psif_tsu_error_types data) */ |
|
1418 |
|
1419 /* Convert enum psif_eps_core_id to string */ |
|
1420 const char *string_enum_psif_eps_core_id(enum psif_eps_core_id val) |
|
1421 { |
|
1422 switch (val) { |
|
1423 case PSIF_EVENT_CORE_EPS_A_1: |
|
1424 return "PSIF_EVENT_CORE_EPS_A_1"; |
|
1425 case PSIF_EVENT_CORE_EPS_A_2: |
|
1426 return "PSIF_EVENT_CORE_EPS_A_2"; |
|
1427 case PSIF_EVENT_CORE_EPS_A_3: |
|
1428 return "PSIF_EVENT_CORE_EPS_A_3"; |
|
1429 case PSIF_EVENT_CORE_EPS_A_4: |
|
1430 return "PSIF_EVENT_CORE_EPS_A_4"; |
|
1431 case PSIF_EVENT_CORE_EPS_C: |
|
1432 return "PSIF_EVENT_CORE_EPS_C"; |
|
1433 case PSIF_EPS_CORE_ID_FIELD_MAX: |
|
1434 return "PSIF_EPS_CORE_ID_FIELD_MAX"; |
|
1435 default: |
|
1436 return "UNKNOWN_psif_eps_core_id"; |
|
1437 } |
|
1438 } |
|
1439 |
|
1440 void write_enum_psif_eps_core_id(XFILE *fd, |
|
1441 enum psif_eps_core_id data) |
|
1442 { |
|
1443 xprintf(fd, "%s", string_enum_psif_eps_core_id(data)); |
|
1444 } /* end write_..._psif_eps_core_id(psif_eps_core_id data) */ |
|
1445 |
|
1446 /* Convert enum psif_epsc_port_state to string */ |
|
1447 const char *string_enum_psif_epsc_port_state(enum psif_epsc_port_state val) |
|
1448 { |
|
1449 switch (val) { |
|
1450 case EPSC_PORT_NOP: |
|
1451 return "EPSC_PORT_NOP"; |
|
1452 case EPSC_PORT_DOWN: |
|
1453 return "EPSC_PORT_DOWN"; |
|
1454 case EPSC_PORT_INIT: |
|
1455 return "EPSC_PORT_INIT"; |
|
1456 case EPSC_PORT_ARMED: |
|
1457 return "EPSC_PORT_ARMED"; |
|
1458 case EPSC_PORT_ACTIVE: |
|
1459 return "EPSC_PORT_ACTIVE"; |
|
1460 case EPSC_PORT_ACTIVE_DEFER: |
|
1461 return "EPSC_PORT_ACTIVE_DEFER"; |
|
1462 case PSIF_EPSC_PORT_STATE_FIELD_MAX: |
|
1463 return "PSIF_EPSC_PORT_STATE_FIELD_MAX"; |
|
1464 default: |
|
1465 return "UNKNOWN_psif_epsc_port_state"; |
|
1466 } |
|
1467 } |
|
1468 |
|
1469 void write_enum_psif_epsc_port_state(XFILE *fd, |
|
1470 enum psif_epsc_port_state data) |
|
1471 { |
|
1472 xprintf(fd, "%s", string_enum_psif_epsc_port_state(data)); |
|
1473 } /* end write_..._psif_epsc_port_state(psif_epsc_port_state data) */ |
|
1474 |
|
1475 /* Convert enum psif_epsc_log_mode to string */ |
|
1476 const char *string_enum_psif_epsc_log_mode(enum psif_epsc_log_mode val) |
|
1477 { |
|
1478 switch (val) { |
|
1479 case EPSC_LOG_MODE_OFF: |
|
1480 return "EPSC_LOG_MODE_OFF"; |
|
1481 case EPSC_LOG_MODE_SCAT: |
|
1482 return "EPSC_LOG_MODE_SCAT"; |
|
1483 case EPSC_LOG_MODE_MALLOC: |
|
1484 return "EPSC_LOG_MODE_MALLOC"; |
|
1485 case EPSC_LOG_MODE_LOCAL: |
|
1486 return "EPSC_LOG_MODE_LOCAL"; |
|
1487 case EPSC_LOG_MODE_HOST: |
|
1488 return "EPSC_LOG_MODE_HOST"; |
|
1489 case EPSC_LOG_MODE_SAVE: |
|
1490 return "EPSC_LOG_MODE_SAVE"; |
|
1491 case PSIF_EPSC_LOG_MODE_FIELD_MAX: |
|
1492 return "PSIF_EPSC_LOG_MODE_FIELD_MAX"; |
|
1493 default: |
|
1494 return "UNKNOWN_psif_epsc_log_mode"; |
|
1495 } |
|
1496 } |
|
1497 |
|
1498 void write_enum_psif_epsc_log_mode(XFILE *fd, |
|
1499 enum psif_epsc_log_mode data) |
|
1500 { |
|
1501 xprintf(fd, "%s", string_enum_psif_epsc_log_mode(data)); |
|
1502 } /* end write_..._psif_epsc_log_mode(psif_epsc_log_mode data) */ |
|
1503 |
|
1504 /* Convert enum psif_epsc_log_level to string */ |
|
1505 const char *string_enum_psif_epsc_log_level(enum psif_epsc_log_level val) |
|
1506 { |
|
1507 switch (val) { |
|
1508 case EPS_LOG_OFF: |
|
1509 return "EPS_LOG_OFF"; |
|
1510 case EPS_LOG_FATAL: |
|
1511 return "EPS_LOG_FATAL"; |
|
1512 case EPS_LOG_ERROR: |
|
1513 return "EPS_LOG_ERROR"; |
|
1514 case EPS_LOG_WARN: |
|
1515 return "EPS_LOG_WARN"; |
|
1516 case EPS_LOG_INFO: |
|
1517 return "EPS_LOG_INFO"; |
|
1518 case EPS_LOG_DEBUG: |
|
1519 return "EPS_LOG_DEBUG"; |
|
1520 case EPS_LOG_TRACE: |
|
1521 return "EPS_LOG_TRACE"; |
|
1522 case EPS_LOG_ALL: |
|
1523 return "EPS_LOG_ALL"; |
|
1524 case PSIF_EPSC_LOG_LEVEL_FIELD_MAX: |
|
1525 return "PSIF_EPSC_LOG_LEVEL_FIELD_MAX"; |
|
1526 default: |
|
1527 return "UNKNOWN_psif_epsc_log_level"; |
|
1528 } |
|
1529 } |
|
1530 |
|
1531 void write_enum_psif_epsc_log_level(XFILE *fd, |
|
1532 enum psif_epsc_log_level data) |
|
1533 { |
|
1534 xprintf(fd, "%s", string_enum_psif_epsc_log_level(data)); |
|
1535 } /* end write_..._psif_epsc_log_level(psif_epsc_log_level data) */ |
|
1536 |
|
1537 /* Convert enum psif_epsc_interrupt_source to string */ |
|
1538 const char *string_enum_psif_epsc_interrupt_source(enum psif_epsc_interrupt_source val) |
|
1539 { |
|
1540 switch (val) { |
|
1541 case EPSC_INTR_LCSR: |
|
1542 return "EPSC_INTR_LCSR"; |
|
1543 case EPSC_INTR_MBOX: |
|
1544 return "EPSC_INTR_MBOX"; |
|
1545 case EPSC_INTR_XIU: |
|
1546 return "EPSC_INTR_XIU"; |
|
1547 case EPSC_INTR_IBU0: |
|
1548 return "EPSC_INTR_IBU0"; |
|
1549 case EPSC_INTR_IBU1: |
|
1550 return "EPSC_INTR_IBU1"; |
|
1551 case EPSC_INTR_TSU_NCSI: |
|
1552 return "EPSC_INTR_TSU_NCSI"; |
|
1553 case EPSC_INTR_TSU_IBPB: |
|
1554 return "EPSC_INTR_TSU_IBPB"; |
|
1555 case EPSC_INTR_TSU_DMA: |
|
1556 return "EPSC_INTR_TSU_DMA"; |
|
1557 case EPSC_INTR_TSU_RQS: |
|
1558 return "EPSC_INTR_TSU_RQS"; |
|
1559 case EPSC_INTR_TSU_QPS: |
|
1560 return "EPSC_INTR_TSU_QPS"; |
|
1561 case EPSC_INTR_TSU_SQS: |
|
1562 return "EPSC_INTR_TSU_SQS"; |
|
1563 case EPSC_INTR_TSU_ERR: |
|
1564 return "EPSC_INTR_TSU_ERR"; |
|
1565 case EPSC_INTR_TSU_CMPL: |
|
1566 return "EPSC_INTR_TSU_CMPL"; |
|
1567 case EPSC_INTR_TSU_VAL: |
|
1568 return "EPSC_INTR_TSU_VAL"; |
|
1569 case EPSC_INTR_TSU_RQH: |
|
1570 return "EPSC_INTR_TSU_RQH"; |
|
1571 case EPSC_INTR_TSU_DSCR: |
|
1572 return "EPSC_INTR_TSU_DSCR"; |
|
1573 case EPSC_INTR_TSU_RCV: |
|
1574 return "EPSC_INTR_TSU_RCV"; |
|
1575 case EPSC_INTR_TSU_IBPR: |
|
1576 return "EPSC_INTR_TSU_IBPR"; |
|
1577 case EPSC_INTR_TSU_CBU: |
|
1578 return "EPSC_INTR_TSU_CBU"; |
|
1579 case EPSC_INTR_TSU_HOST: |
|
1580 return "EPSC_INTR_TSU_HOST"; |
|
1581 case EPSC_INTR_TSU_MMU: |
|
1582 return "EPSC_INTR_TSU_MMU"; |
|
1583 default: |
|
1584 return "UNKNOWN_psif_epsc_interrupt_source"; |
|
1585 } |
|
1586 } |
|
1587 |
|
1588 void write_enum_psif_epsc_interrupt_source(XFILE *fd, |
|
1589 enum psif_epsc_interrupt_source data) |
|
1590 { |
|
1591 xprintf(fd, "%s", string_enum_psif_epsc_interrupt_source(data)); |
|
1592 } /* end write_..._psif_epsc_interrupt_source(psif_epsc_interrupt_source data) */ |
|
1593 |
|
1594 /* Convert enum psif_epsc_interrupt_pri to string */ |
|
1595 const char *string_enum_psif_epsc_interrupt_pri(enum psif_epsc_interrupt_pri val) |
|
1596 { |
|
1597 switch (val) { |
|
1598 case EPSC_INTR_RESERVED: |
|
1599 return "EPSC_INTR_RESERVED"; |
|
1600 case EPSC_INTR_LOW: |
|
1601 return "EPSC_INTR_LOW"; |
|
1602 case EPSC_INTR_HIGH: |
|
1603 return "EPSC_INTR_HIGH"; |
|
1604 case EPSC_INTR_FATAL: |
|
1605 return "EPSC_INTR_FATAL"; |
|
1606 default: |
|
1607 return "UNKNOWN_psif_epsc_interrupt_pri"; |
|
1608 } |
|
1609 } |
|
1610 |
|
1611 void write_enum_psif_epsc_interrupt_pri(XFILE *fd, |
|
1612 enum psif_epsc_interrupt_pri data) |
|
1613 { |
|
1614 xprintf(fd, "%s", string_enum_psif_epsc_interrupt_pri(data)); |
|
1615 } /* end write_..._psif_epsc_interrupt_pri(psif_epsc_interrupt_pri data) */ |
|
1616 |
|
1617 /* Convert enum psif_epsc_csr_status to string */ |
|
1618 const char *string_enum_psif_epsc_csr_status(enum psif_epsc_csr_status val) |
|
1619 { |
|
1620 switch (val) { |
|
1621 case EPSC_SUCCESS: |
|
1622 return "EPSC_SUCCESS"; |
|
1623 case EPSC_EKEYREJECTED: |
|
1624 return "EPSC_EKEYREJECTED"; |
|
1625 case EPSC_EADDRNOTAVAIL: |
|
1626 return "EPSC_EADDRNOTAVAIL"; |
|
1627 case EPSC_EOPNOTSUPP: |
|
1628 return "EPSC_EOPNOTSUPP"; |
|
1629 case EPSC_ENOMEM: |
|
1630 return "EPSC_ENOMEM"; |
|
1631 case EPSC_ENODATA: |
|
1632 return "EPSC_ENODATA"; |
|
1633 case EPSC_EAGAIN: |
|
1634 return "EPSC_EAGAIN"; |
|
1635 case EPSC_ECANCELED: |
|
1636 return "EPSC_ECANCELED"; |
|
1637 case EPSC_ECONNRESET: |
|
1638 return "EPSC_ECONNRESET"; |
|
1639 case EPSC_ECSR: |
|
1640 return "EPSC_ECSR"; |
|
1641 case EPSC_MODIFY_QP_OUT_OF_RANGE: |
|
1642 return "EPSC_MODIFY_QP_OUT_OF_RANGE"; |
|
1643 case EPSC_MODIFY_QP_INVALID: |
|
1644 return "EPSC_MODIFY_QP_INVALID"; |
|
1645 case EPSC_MODIFY_CANNOT_CHANGE_QP_ATTR: |
|
1646 return "EPSC_MODIFY_CANNOT_CHANGE_QP_ATTR"; |
|
1647 case EPSC_MODIFY_INVALID_QP_STATE: |
|
1648 return "EPSC_MODIFY_INVALID_QP_STATE"; |
|
1649 case EPSC_MODIFY_INVALID_MIG_STATE: |
|
1650 return "EPSC_MODIFY_INVALID_MIG_STATE"; |
|
1651 case EPSC_MODIFY_TIMEOUT: |
|
1652 return "EPSC_MODIFY_TIMEOUT"; |
|
1653 case EPSC_ETEST_HEAD: |
|
1654 return "EPSC_ETEST_HEAD"; |
|
1655 case EPSC_ETEST_TAIL: |
|
1656 return "EPSC_ETEST_TAIL"; |
|
1657 case EPSC_ETEST_PATTERN: |
|
1658 return "EPSC_ETEST_PATTERN"; |
|
1659 case EPSC_EADDRINUSE: |
|
1660 return "EPSC_EADDRINUSE"; |
|
1661 case EPSC_EINVALID_VHCA: |
|
1662 return "EPSC_EINVALID_VHCA"; |
|
1663 case EPSC_EINVALID_PORT: |
|
1664 return "EPSC_EINVALID_PORT"; |
|
1665 case EPSC_EINVALID_ADDRESS: |
|
1666 return "EPSC_EINVALID_ADDRESS"; |
|
1667 case EPSC_EINVALID_PARAMETER: |
|
1668 return "EPSC_EINVALID_PARAMETER"; |
|
1669 case EPSC_FAIL: |
|
1670 return "EPSC_FAIL"; |
|
1671 default: |
|
1672 return "UNKNOWN_psif_epsc_csr_status"; |
|
1673 } |
|
1674 } |
|
1675 |
|
1676 void write_enum_psif_epsc_csr_status(XFILE *fd, |
|
1677 enum psif_epsc_csr_status data) |
|
1678 { |
|
1679 xprintf(fd, "%s", string_enum_psif_epsc_csr_status(data)); |
|
1680 } /* end write_..._psif_epsc_csr_status(psif_epsc_csr_status data) */ |
|
1681 |
|
1682 /* Convert enum psif_epsc_csr_opcode to string */ |
|
1683 const char *string_enum_psif_epsc_csr_opcode(enum psif_epsc_csr_opcode val) |
|
1684 { |
|
1685 switch (val) { |
|
1686 case EPSC_NOOP: |
|
1687 return "EPSC_NOOP"; |
|
1688 case EPSC_MAILBOX_PING: |
|
1689 return "EPSC_MAILBOX_PING"; |
|
1690 case EPSC_KEEP_ALIVE: |
|
1691 return "EPSC_KEEP_ALIVE"; |
|
1692 case EPSC_SETUP: |
|
1693 return "EPSC_SETUP"; |
|
1694 case EPSC_TEARDOWN: |
|
1695 return "EPSC_TEARDOWN"; |
|
1696 case EPSC_SET: |
|
1697 return "EPSC_SET"; |
|
1698 case EPSC_SET_SINGLE: |
|
1699 return "EPSC_SET_SINGLE"; |
|
1700 case EPSC_SET_ONE_CSR: |
|
1701 return "EPSC_SET_ONE_CSR"; |
|
1702 case EPSC_SETUP_BASEADDR: |
|
1703 return "EPSC_SETUP_BASEADDR"; |
|
1704 case EPSC_SET_BASEADDR: |
|
1705 return "EPSC_SET_BASEADDR"; |
|
1706 case EPSC_SET_BASEADDR_EQ: |
|
1707 return "EPSC_SET_BASEADDR_EQ"; |
|
1708 case EPSC_SET_LID: |
|
1709 return "EPSC_SET_LID"; |
|
1710 case OBSOLETE_1: |
|
1711 return "OBSOLETE_1"; |
|
1712 case OBSOLETE_2: |
|
1713 return "OBSOLETE_2"; |
|
1714 case EPSC_SET_GID: |
|
1715 return "EPSC_SET_GID"; |
|
1716 case EPSC_SET_EOIB_MAC: |
|
1717 return "EPSC_SET_EOIB_MAC"; |
|
1718 case EPSC_SET_VLINK_STATE: |
|
1719 return "EPSC_SET_VLINK_STATE"; |
|
1720 case EPSC_QUERY_VLINK_STATE: |
|
1721 return "EPSC_QUERY_VLINK_STATE"; |
|
1722 case EPSC_UF_RESET: |
|
1723 return "EPSC_UF_RESET"; |
|
1724 case EPSC_MODIFY_QP: |
|
1725 return "EPSC_MODIFY_QP"; |
|
1726 case EPSC_GET_SINGLE: |
|
1727 return "EPSC_GET_SINGLE"; |
|
1728 case EPSC_GET_ONE_CSR: |
|
1729 return "EPSC_GET_ONE_CSR"; |
|
1730 case EPSC_QUERY_QP: |
|
1731 return "EPSC_QUERY_QP"; |
|
1732 case EPSC_QUERY_HW_RQ: |
|
1733 return "EPSC_QUERY_HW_RQ"; |
|
1734 case EPSC_QUERY_HW_SQ: |
|
1735 return "EPSC_QUERY_HW_SQ"; |
|
1736 case EPSC_QUERY_DEVICE: |
|
1737 return "EPSC_QUERY_DEVICE"; |
|
1738 case EPSC_QUERY_PORT_1: |
|
1739 return "EPSC_QUERY_PORT_1"; |
|
1740 case EPSC_QUERY_PORT_2: |
|
1741 return "EPSC_QUERY_PORT_2"; |
|
1742 case EPSC_QUERY_PKEY: |
|
1743 return "EPSC_QUERY_PKEY"; |
|
1744 case EPSC_QUERY_GID: |
|
1745 return "EPSC_QUERY_GID"; |
|
1746 case EPSC_MODIFY_DEVICE: |
|
1747 return "EPSC_MODIFY_DEVICE"; |
|
1748 case EPSC_MODIFY_PORT_1: |
|
1749 return "EPSC_MODIFY_PORT_1"; |
|
1750 case EPSC_MODIFY_PORT_2: |
|
1751 return "EPSC_MODIFY_PORT_2"; |
|
1752 case EPSC_MC_ATTACH: |
|
1753 return "EPSC_MC_ATTACH"; |
|
1754 case EPSC_MC_DETACH: |
|
1755 return "EPSC_MC_DETACH"; |
|
1756 case EPSC_MC_QUERY: |
|
1757 return "EPSC_MC_QUERY"; |
|
1758 case EPSC_EVENT_ACK: |
|
1759 return "EPSC_EVENT_ACK"; |
|
1760 case EPSC_EVENT_INDEX: |
|
1761 return "EPSC_EVENT_INDEX"; |
|
1762 case EPSC_FLASH_START: |
|
1763 return "EPSC_FLASH_START"; |
|
1764 case EPSC_FLASH_INFO: |
|
1765 return "EPSC_FLASH_INFO"; |
|
1766 case EPSC_FLASH_ERASE_SECTOR: |
|
1767 return "EPSC_FLASH_ERASE_SECTOR"; |
|
1768 case EPSC_FLASH_RD: |
|
1769 return "EPSC_FLASH_RD"; |
|
1770 case EPSC_FLASH_WR: |
|
1771 return "EPSC_FLASH_WR"; |
|
1772 case EPSC_FLASH_CHECK: |
|
1773 return "EPSC_FLASH_CHECK"; |
|
1774 case EPSC_FLASH_SCAN: |
|
1775 return "EPSC_FLASH_SCAN"; |
|
1776 case EPSC_FLASH_STOP: |
|
1777 return "EPSC_FLASH_STOP"; |
|
1778 case EPSC_UPDATE: |
|
1779 return "EPSC_UPDATE"; |
|
1780 case EPSC_TRACE_STATUS: |
|
1781 return "EPSC_TRACE_STATUS"; |
|
1782 case EPSC_TRACE_SETUP: |
|
1783 return "EPSC_TRACE_SETUP"; |
|
1784 case EPSC_TRACE_START: |
|
1785 return "EPSC_TRACE_START"; |
|
1786 case EPSC_TRACE_STOP: |
|
1787 return "EPSC_TRACE_STOP"; |
|
1788 case EPSC_TRACE_ACQUIRE: |
|
1789 return "EPSC_TRACE_ACQUIRE"; |
|
1790 case EPSC_TEST_HOST_RD: |
|
1791 return "EPSC_TEST_HOST_RD"; |
|
1792 case EPSC_TEST_HOST_WR: |
|
1793 return "EPSC_TEST_HOST_WR"; |
|
1794 case EPSC_FW_VERSION: |
|
1795 return "EPSC_FW_VERSION"; |
|
1796 case EPSC_LOG_CTRL: |
|
1797 return "EPSC_LOG_CTRL"; |
|
1798 case EPSC_LOG_REQ_NOTIFY: |
|
1799 return "EPSC_LOG_REQ_NOTIFY"; |
|
1800 case EPSC_LINK_CNTRL: |
|
1801 return "EPSC_LINK_CNTRL"; |
|
1802 case EPSC_A_CONTROL: |
|
1803 return "EPSC_A_CONTROL"; |
|
1804 case EPSC_A_COMMAND: |
|
1805 return "EPSC_A_COMMAND"; |
|
1806 case EPSC_EXERCISE_MMU: |
|
1807 return "EPSC_EXERCISE_MMU"; |
|
1808 case EPSC_CLI_ACCESS: |
|
1809 return "EPSC_CLI_ACCESS"; |
|
1810 case EPSC_MAD_PROCESS: |
|
1811 return "EPSC_MAD_PROCESS"; |
|
1812 case EPSC_MAD_SEND_WR: |
|
1813 return "EPSC_MAD_SEND_WR"; |
|
1814 case EPSC_QUERY: |
|
1815 return "EPSC_QUERY"; |
|
1816 case EPSC_HOST_INT_COMMON_CTRL: |
|
1817 return "EPSC_HOST_INT_COMMON_CTRL"; |
|
1818 case EPSC_HOST_INT_CHANNEL_CTRL: |
|
1819 return "EPSC_HOST_INT_CHANNEL_CTRL"; |
|
1820 case EPSC_UF_CTRL: |
|
1821 return "EPSC_UF_CTRL"; |
|
1822 case EPSC_FLUSH_CACHES: |
|
1823 return "EPSC_FLUSH_CACHES"; |
|
1824 case EPSC_PMA_COUNTERS: |
|
1825 return "EPSC_PMA_COUNTERS"; |
|
1826 case EPSC_VIMMA_CTRL: |
|
1827 return "EPSC_VIMMA_CTRL"; |
|
1828 case EPSC_BER_DATA: |
|
1829 return "EPSC_BER_DATA"; |
|
1830 case EPSC_LAST_OP: |
|
1831 return "EPSC_LAST_OP"; |
|
1832 case PSIF_EPSC_CSR_OPCODE_FIELD_MAX: |
|
1833 return "PSIF_EPSC_CSR_OPCODE_FIELD_MAX"; |
|
1834 default: |
|
1835 return "UNKNOWN_psif_epsc_csr_opcode"; |
|
1836 } |
|
1837 } |
|
1838 |
|
1839 void write_enum_psif_epsc_csr_opcode(XFILE *fd, |
|
1840 enum psif_epsc_csr_opcode data) |
|
1841 { |
|
1842 xprintf(fd, "%s", string_enum_psif_epsc_csr_opcode(data)); |
|
1843 } /* end write_..._psif_epsc_csr_opcode(psif_epsc_csr_opcode data) */ |
|
1844 |
|
1845 /* Convert enum psif_epsc_csr_flags to string */ |
|
1846 const char *string_enum_psif_epsc_csr_flags(enum psif_epsc_csr_flags val) |
|
1847 { |
|
1848 switch (val) { |
|
1849 case EPSC_FL_NONE: |
|
1850 return "EPSC_FL_NONE"; |
|
1851 case EPSC_FL_NOTIFY: |
|
1852 return "EPSC_FL_NOTIFY"; |
|
1853 case EPSC_FL_PQP: |
|
1854 return "EPSC_FL_PQP"; |
|
1855 case EPSC_FL_IGNORE_ERROR: |
|
1856 return "EPSC_FL_IGNORE_ERROR"; |
|
1857 case PSIF_EPSC_CSR_FLAGS_FIELD_MAX: |
|
1858 return "PSIF_EPSC_CSR_FLAGS_FIELD_MAX"; |
|
1859 default: |
|
1860 return "UNKNOWN_psif_epsc_csr_flags"; |
|
1861 } |
|
1862 } |
|
1863 |
|
1864 void write_enum_psif_epsc_csr_flags(XFILE *fd, |
|
1865 enum psif_epsc_csr_flags data) |
|
1866 { |
|
1867 xprintf(fd, "%s", string_enum_psif_epsc_csr_flags(data)); |
|
1868 } /* end write_..._psif_epsc_csr_flags(psif_epsc_csr_flags data) */ |
|
1869 |
|
1870 /* Convert enum psif_vlink_state to string */ |
|
1871 const char *string_enum_psif_vlink_state(enum psif_vlink_state val) |
|
1872 { |
|
1873 switch (val) { |
|
1874 case PSIF_LINK_DISABLED: |
|
1875 return "PSIF_LINK_DISABLED"; |
|
1876 case PSIF_LINK_DOWN: |
|
1877 return "PSIF_LINK_DOWN"; |
|
1878 case PSIF_LINK_INIT: |
|
1879 return "PSIF_LINK_INIT"; |
|
1880 case PSIF_LINK_ARM: |
|
1881 return "PSIF_LINK_ARM"; |
|
1882 case PSIF_LINK_ACTIVE: |
|
1883 return "PSIF_LINK_ACTIVE"; |
|
1884 default: |
|
1885 return "UNKNOWN_psif_vlink_state"; |
|
1886 } |
|
1887 } |
|
1888 |
|
1889 void write_enum_psif_vlink_state(XFILE *fd, |
|
1890 enum psif_vlink_state data) |
|
1891 { |
|
1892 xprintf(fd, "%s", string_enum_psif_vlink_state(data)); |
|
1893 } /* end write_..._psif_vlink_state(psif_vlink_state data) */ |
|
1894 |
|
1895 /* Convert enum psif_epsc_csr_modify_device_flags to string */ |
|
1896 const char *string_enum_psif_epsc_csr_modify_device_flags(enum psif_epsc_csr_modify_device_flags val) |
|
1897 { |
|
1898 switch (val) { |
|
1899 case PSIF_DEVICE_MODIFY_SYS_IMAGE_GUID: |
|
1900 return "PSIF_DEVICE_MODIFY_SYS_IMAGE_GUID"; |
|
1901 case PSIF_DEVICE_MODIFY_NODE_DESC: |
|
1902 return "PSIF_DEVICE_MODIFY_NODE_DESC"; |
|
1903 case PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_FIELD_MAX: |
|
1904 return "PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_FIELD_MAX"; |
|
1905 default: |
|
1906 return "UNKNOWN_psif_epsc_csr_modify_device_flags"; |
|
1907 } |
|
1908 } |
|
1909 |
|
1910 void write_enum_psif_epsc_csr_modify_device_flags(XFILE *fd, |
|
1911 enum psif_epsc_csr_modify_device_flags data) |
|
1912 { |
|
1913 xprintf(fd, "%s", string_enum_psif_epsc_csr_modify_device_flags(data)); |
|
1914 } /* end write_..._psif_epsc_csr_modify_device_flags(psif_epsc_csr_modify_device_flags data) */ |
|
1915 |
|
1916 /* Convert enum psif_epsc_csr_modify_port_flags to string */ |
|
1917 const char *string_enum_psif_epsc_csr_modify_port_flags(enum psif_epsc_csr_modify_port_flags val) |
|
1918 { |
|
1919 switch (val) { |
|
1920 case PSIF_PORT_SHUTDOWN: |
|
1921 return "PSIF_PORT_SHUTDOWN"; |
|
1922 case PSIF_PORT_INIT_TYPE: |
|
1923 return "PSIF_PORT_INIT_TYPE"; |
|
1924 case PSIF_PORT_RESET_QKEY_CNTR: |
|
1925 return "PSIF_PORT_RESET_QKEY_CNTR"; |
|
1926 case PSIF_PORT_RESET_PKEY_CNTR: |
|
1927 return "PSIF_PORT_RESET_PKEY_CNTR"; |
|
1928 case PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_FIELD_MAX: |
|
1929 return "PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_FIELD_MAX"; |
|
1930 default: |
|
1931 return "UNKNOWN_psif_epsc_csr_modify_port_flags"; |
|
1932 } |
|
1933 } |
|
1934 |
|
1935 void write_enum_psif_epsc_csr_modify_port_flags(XFILE *fd, |
|
1936 enum psif_epsc_csr_modify_port_flags data) |
|
1937 { |
|
1938 xprintf(fd, "%s", string_enum_psif_epsc_csr_modify_port_flags(data)); |
|
1939 } /* end write_..._psif_epsc_csr_modify_port_flags(psif_epsc_csr_modify_port_flags data) */ |
|
1940 |
|
1941 /* Convert enum psif_epsc_csr_epsa_command to string */ |
|
1942 const char *string_enum_psif_epsc_csr_epsa_command(enum psif_epsc_csr_epsa_command val) |
|
1943 { |
|
1944 switch (val) { |
|
1945 case EPSC_A_LOAD: |
|
1946 return "EPSC_A_LOAD"; |
|
1947 case EPSC_A_START: |
|
1948 return "EPSC_A_START"; |
|
1949 case EPSC_A_STOP: |
|
1950 return "EPSC_A_STOP"; |
|
1951 case EPSC_A_STATUS: |
|
1952 return "EPSC_A_STATUS"; |
|
1953 case PSIF_EPSC_CSR_EPSA_COMMAND_FIELD_MAX: |
|
1954 return "PSIF_EPSC_CSR_EPSA_COMMAND_FIELD_MAX"; |
|
1955 default: |
|
1956 return "UNKNOWN_psif_epsc_csr_epsa_command"; |
|
1957 } |
|
1958 } |
|
1959 |
|
1960 void write_enum_psif_epsc_csr_epsa_command(XFILE *fd, |
|
1961 enum psif_epsc_csr_epsa_command data) |
|
1962 { |
|
1963 xprintf(fd, "%s", string_enum_psif_epsc_csr_epsa_command(data)); |
|
1964 } /* end write_..._psif_epsc_csr_epsa_command(psif_epsc_csr_epsa_command data) */ |
|
1965 |
|
1966 /* Convert enum psif_epsa_command to string */ |
|
1967 const char *string_enum_psif_epsa_command(enum psif_epsa_command val) |
|
1968 { |
|
1969 switch (val) { |
|
1970 case EPSA_DYNAMIC_LOAD: |
|
1971 return "EPSA_DYNAMIC_LOAD"; |
|
1972 case EPSA_TEST_FABOUT: |
|
1973 return "EPSA_TEST_FABOUT"; |
|
1974 case EPSA_TEST_FABIN: |
|
1975 return "EPSA_TEST_FABIN"; |
|
1976 case EPSA_TEST_FABIN_FABOUT: |
|
1977 return "EPSA_TEST_FABIN_FABOUT"; |
|
1978 case EPSA_TEST_SKJM_MEMREAD: |
|
1979 return "EPSA_TEST_SKJM_MEMREAD"; |
|
1980 case EPSA_TEST_SKJM_MEMWRITE: |
|
1981 return "EPSA_TEST_SKJM_MEMWRITE"; |
|
1982 case EPSA_TEST_SKJM_MEMLOCK: |
|
1983 return "EPSA_TEST_SKJM_MEMLOCK"; |
|
1984 case EPSA_SKJM_LOAD: |
|
1985 return "EPSA_SKJM_LOAD"; |
|
1986 case EPSA_SKJM_ACC: |
|
1987 return "EPSA_SKJM_ACC"; |
|
1988 case EPSA_SKJM_MEMACC: |
|
1989 return "EPSA_SKJM_MEMACC"; |
|
1990 case EPSA_GET_PROXY_QP_SQ_KEY: |
|
1991 return "EPSA_GET_PROXY_QP_SQ_KEY"; |
|
1992 case EPSA_GENERIC_CMD: |
|
1993 return "EPSA_GENERIC_CMD"; |
|
1994 case PSIF_EPSA_COMMAND_FIELD_MAX: |
|
1995 return "PSIF_EPSA_COMMAND_FIELD_MAX"; |
|
1996 default: |
|
1997 return "UNKNOWN_psif_epsa_command"; |
|
1998 } |
|
1999 } |
|
2000 |
|
2001 void write_enum_psif_epsa_command(XFILE *fd, |
|
2002 enum psif_epsa_command data) |
|
2003 { |
|
2004 xprintf(fd, "%s", string_enum_psif_epsa_command(data)); |
|
2005 } /* end write_..._psif_epsa_command(psif_epsa_command data) */ |
|
2006 |
|
2007 /* Convert enum psif_epsc_query_op to string */ |
|
2008 const char *string_enum_psif_epsc_query_op(enum psif_epsc_query_op val) |
|
2009 { |
|
2010 switch (val) { |
|
2011 case EPSC_QUERY_BLANK: |
|
2012 return "EPSC_QUERY_BLANK"; |
|
2013 case EPSC_QUERY_CAP_VCB: |
|
2014 return "EPSC_QUERY_CAP_VCB"; |
|
2015 case EPSC_QUERY_CAP_PCB: |
|
2016 return "EPSC_QUERY_CAP_PCB"; |
|
2017 case EPSC_QUERY_NUM_UF: |
|
2018 return "EPSC_QUERY_NUM_UF"; |
|
2019 case EPSC_QUERY_GID_HI: |
|
2020 return "EPSC_QUERY_GID_HI"; |
|
2021 case EPSC_QUERY_GID_LO: |
|
2022 return "EPSC_QUERY_GID_LO"; |
|
2023 case EPSC_QUERY_P_KEY: |
|
2024 return "EPSC_QUERY_P_KEY"; |
|
2025 case EPSC_QUERY_Q_KEY: |
|
2026 return "EPSC_QUERY_Q_KEY"; |
|
2027 case EPSC_QUERY_UF: |
|
2028 return "EPSC_QUERY_UF"; |
|
2029 case EPSC_QUERY_LINK_STATE: |
|
2030 return "EPSC_QUERY_LINK_STATE"; |
|
2031 case EPSC_QUERY_VHCA_STATE: |
|
2032 return "EPSC_QUERY_VHCA_STATE"; |
|
2033 case EPSC_QUERY_INT_COMMON: |
|
2034 return "EPSC_QUERY_INT_COMMON"; |
|
2035 case EPSC_QUERY_INT_CHAN_RATE: |
|
2036 return "EPSC_QUERY_INT_CHAN_RATE"; |
|
2037 case EPSC_QUERY_INT_CHAN_AUSEC: |
|
2038 return "EPSC_QUERY_INT_CHAN_AUSEC"; |
|
2039 case EPSC_QUERY_INT_CHAN_PUSEC: |
|
2040 return "EPSC_QUERY_INT_CHAN_PUSEC"; |
|
2041 case EPSC_QUERY_CAP_VCB_LO: |
|
2042 return "EPSC_QUERY_CAP_VCB_LO"; |
|
2043 case EPSC_QUERY_CAP_VCB_HI: |
|
2044 return "EPSC_QUERY_CAP_VCB_HI"; |
|
2045 case EPSC_QUERY_CAP_PCB_LO: |
|
2046 return "EPSC_QUERY_CAP_PCB_LO"; |
|
2047 case EPSC_QUERY_CAP_PCB_HI: |
|
2048 return "EPSC_QUERY_CAP_PCB_HI"; |
|
2049 case EPSC_QUERY_PMA_REDIRECT_QP: |
|
2050 return "EPSC_QUERY_PMA_REDIRECT_QP"; |
|
2051 case EPSC_QUERY_FW_UPTIME: |
|
2052 return "EPSC_QUERY_FW_UPTIME"; |
|
2053 case EPSC_QUERY_FW_PROG_DATE: |
|
2054 return "EPSC_QUERY_FW_PROG_DATE"; |
|
2055 case EPSC_QUERY_FW_BUILD_DATE: |
|
2056 return "EPSC_QUERY_FW_BUILD_DATE"; |
|
2057 case EPSC_QUERY_FW_CURR_IMG: |
|
2058 return "EPSC_QUERY_FW_CURR_IMG"; |
|
2059 case EPSC_QUERY_FW_ONESHOT_IMG: |
|
2060 return "EPSC_QUERY_FW_ONESHOT_IMG"; |
|
2061 case EPSC_QUERY_FW_AUTOSTART_IMG: |
|
2062 return "EPSC_QUERY_FW_AUTOSTART_IMG"; |
|
2063 case EPSC_QUERY_FW_START_CAUSE: |
|
2064 return "EPSC_QUERY_FW_START_CAUSE"; |
|
2065 case EPSC_QUERY_FW_VERSION: |
|
2066 return "EPSC_QUERY_FW_VERSION"; |
|
2067 case EPSC_QUERY_SQ_NUM_BRE: |
|
2068 return "EPSC_QUERY_SQ_NUM_BRE"; |
|
2069 case EPSC_QUERY_NUM_CQOVF: |
|
2070 return "EPSC_QUERY_NUM_CQOVF"; |
|
2071 case EPSC_QUERY_SQ_NUM_WRFE: |
|
2072 return "EPSC_QUERY_SQ_NUM_WRFE"; |
|
2073 case EPSC_QUERY_RQ_NUM_WRFE: |
|
2074 return "EPSC_QUERY_RQ_NUM_WRFE"; |
|
2075 case EPSC_QUERY_RQ_NUM_LAE: |
|
2076 return "EPSC_QUERY_RQ_NUM_LAE"; |
|
2077 case EPSC_QUERY_RQ_NUM_LPE: |
|
2078 return "EPSC_QUERY_RQ_NUM_LPE"; |
|
2079 case EPSC_QUERY_SQ_NUM_LLE: |
|
2080 return "EPSC_QUERY_SQ_NUM_LLE"; |
|
2081 case EPSC_QUERY_RQ_NUM_LLE: |
|
2082 return "EPSC_QUERY_RQ_NUM_LLE"; |
|
2083 case EPSC_QUERY_SQ_NUM_LQPOE: |
|
2084 return "EPSC_QUERY_SQ_NUM_LQPOE"; |
|
2085 case EPSC_QUERY_RQ_NUM_LQPOE: |
|
2086 return "EPSC_QUERY_RQ_NUM_LQPOE"; |
|
2087 case EPSC_QUERY_SQ_NUM_OOS: |
|
2088 return "EPSC_QUERY_SQ_NUM_OOS"; |
|
2089 case EPSC_QUERY_RQ_NUM_OOS: |
|
2090 return "EPSC_QUERY_RQ_NUM_OOS"; |
|
2091 case EPSC_QUERY_SQ_NUM_RREE: |
|
2092 return "EPSC_QUERY_SQ_NUM_RREE"; |
|
2093 case EPSC_QUERY_SQ_NUM_TREE: |
|
2094 return "EPSC_QUERY_SQ_NUM_TREE"; |
|
2095 case EPSC_QUERY_SQ_NUM_ROE: |
|
2096 return "EPSC_QUERY_SQ_NUM_ROE"; |
|
2097 case EPSC_QUERY_RQ_NUM_ROE: |
|
2098 return "EPSC_QUERY_RQ_NUM_ROE"; |
|
2099 case EPSC_QUERY_SQ_NUM_RAE: |
|
2100 return "EPSC_QUERY_SQ_NUM_RAE"; |
|
2101 case EPSC_QUERY_RQ_NUM_RAE: |
|
2102 return "EPSC_QUERY_RQ_NUM_RAE"; |
|
2103 case EPSC_QUERY_RQ_NUM_UDSDPRD: |
|
2104 return "EPSC_QUERY_RQ_NUM_UDSDPRD"; |
|
2105 case EPSC_QUERY_RQ_NUM_UCSDPRD: |
|
2106 return "EPSC_QUERY_RQ_NUM_UCSDPRD"; |
|
2107 case EPSC_QUERY_SQ_NUM_RIRE: |
|
2108 return "EPSC_QUERY_SQ_NUM_RIRE"; |
|
2109 case EPSC_QUERY_RQ_NUM_RIRE: |
|
2110 return "EPSC_QUERY_RQ_NUM_RIRE"; |
|
2111 case EPSC_QUERY_SQ_NUM_RNR: |
|
2112 return "EPSC_QUERY_SQ_NUM_RNR"; |
|
2113 case EPSC_QUERY_RQ_NUM_RNR: |
|
2114 return "EPSC_QUERY_RQ_NUM_RNR"; |
|
2115 case EPSC_QUERY_FW_TWOSHOT_IMG: |
|
2116 return "EPSC_QUERY_FW_TWOSHOT_IMG"; |
|
2117 case EPSC_QUERY_FW_TYPE: |
|
2118 return "EPSC_QUERY_FW_TYPE"; |
|
2119 case EPSC_QUERY_FW_SIZE: |
|
2120 return "EPSC_QUERY_FW_SIZE"; |
|
2121 case EPSC_QUERY_FW_SLOT_SIZE: |
|
2122 return "EPSC_QUERY_FW_SLOT_SIZE"; |
|
2123 case EPSC_QUERY_BL_VERSION: |
|
2124 return "EPSC_QUERY_BL_VERSION"; |
|
2125 case EPSC_QUERY_BL_BUILD_DATE: |
|
2126 return "EPSC_QUERY_BL_BUILD_DATE"; |
|
2127 case EPSC_QUERY_CLEAN_CQ_ID: |
|
2128 return "EPSC_QUERY_CLEAN_CQ_ID"; |
|
2129 case EPSC_QUERY_CAP_TSL_TX: |
|
2130 return "EPSC_QUERY_CAP_TSL_TX"; |
|
2131 case EPSC_QUERY_CAP_TSL_RX: |
|
2132 return "EPSC_QUERY_CAP_TSL_RX"; |
|
2133 case EPSC_QUERY_RESET_CBLD_DIAG_COUNTERS: |
|
2134 return "EPSC_QUERY_RESET_CBLD_DIAG_COUNTERS"; |
|
2135 case EPSC_QUERY_MAX_QP_USED: |
|
2136 return "EPSC_QUERY_MAX_QP_USED"; |
|
2137 case EPSC_QUERY_MODQP_TO_SOURCE: |
|
2138 return "EPSC_QUERY_MODQP_TO_SOURCE"; |
|
2139 case EPSC_QUERY_MODQP_TO_DEBUG: |
|
2140 return "EPSC_QUERY_MODQP_TO_DEBUG"; |
|
2141 case EPSC_QUERY_DEGRADED_CAUSE: |
|
2142 return "EPSC_QUERY_DEGRADED_CAUSE"; |
|
2143 case EPSC_QUERY_SPIN_SET_CONTROL: |
|
2144 return "EPSC_QUERY_SPIN_SET_CONTROL"; |
|
2145 case EPSC_QUERY_VPD_MAC: |
|
2146 return "EPSC_QUERY_VPD_MAC"; |
|
2147 case EPSC_QUERY_VPD_PART_NUMBER: |
|
2148 return "EPSC_QUERY_VPD_PART_NUMBER"; |
|
2149 case EPSC_QUERY_VPD_REVISION: |
|
2150 return "EPSC_QUERY_VPD_REVISION"; |
|
2151 case EPSC_QUERY_VPD_SERIAL_NUMBER: |
|
2152 return "EPSC_QUERY_VPD_SERIAL_NUMBER"; |
|
2153 case EPSC_QUERY_VPD_MANUFACTURER: |
|
2154 return "EPSC_QUERY_VPD_MANUFACTURER"; |
|
2155 case EPSC_QUERY_VPD_PRODUCT_NAME: |
|
2156 return "EPSC_QUERY_VPD_PRODUCT_NAME"; |
|
2157 case EPSC_QUERY_VPD_BASE_GUID: |
|
2158 return "EPSC_QUERY_VPD_BASE_GUID"; |
|
2159 case EPSC_QUERY_MAP_QP0_TO_TSL: |
|
2160 return "EPSC_QUERY_MAP_QP0_TO_TSL"; |
|
2161 case EPSC_QUERY_MAP_PQP_TO_TSL: |
|
2162 return "EPSC_QUERY_MAP_PQP_TO_TSL"; |
|
2163 case EPSC_QUERY_MAP_SL_TO_TSL_LO: |
|
2164 return "EPSC_QUERY_MAP_SL_TO_TSL_LO"; |
|
2165 case EPSC_QUERY_MAP_SL_TO_TSL_HI: |
|
2166 return "EPSC_QUERY_MAP_SL_TO_TSL_HI"; |
|
2167 case EPSC_QUERY_TA_UPPER_TWELVE: |
|
2168 return "EPSC_QUERY_TA_UPPER_TWELVE"; |
|
2169 case EPSC_QUERY_PA_UPPER_TWELVE: |
|
2170 return "EPSC_QUERY_PA_UPPER_TWELVE"; |
|
2171 case EPSC_QUERY_NUM_VFS: |
|
2172 return "EPSC_QUERY_NUM_VFS"; |
|
2173 case EPSC_QUERY_CREDIT_MODE: |
|
2174 return "EPSC_QUERY_CREDIT_MODE"; |
|
2175 case EPSC_QUERY_CPLD_VERSION: |
|
2176 return "EPSC_QUERY_CPLD_VERSION"; |
|
2177 case EPSC_QUERY_EXTERNAL_PORT_INFO: |
|
2178 return "EPSC_QUERY_EXTERNAL_PORT_INFO"; |
|
2179 case EPSC_QUERY_LAST: |
|
2180 return "EPSC_QUERY_LAST"; |
|
2181 case PSIF_EPSC_QUERY_OP_FIELD_MAX: |
|
2182 return "PSIF_EPSC_QUERY_OP_FIELD_MAX"; |
|
2183 default: |
|
2184 return "UNKNOWN_psif_epsc_query_op"; |
|
2185 } |
|
2186 } |
|
2187 |
|
2188 void write_enum_psif_epsc_query_op(XFILE *fd, |
|
2189 enum psif_epsc_query_op data) |
|
2190 { |
|
2191 xprintf(fd, "%s", string_enum_psif_epsc_query_op(data)); |
|
2192 } /* end write_..._psif_epsc_query_op(psif_epsc_query_op data) */ |
|
2193 |
|
2194 /* Convert enum psif_epsc_csr_update_opcode to string */ |
|
2195 const char *string_enum_psif_epsc_csr_update_opcode(enum psif_epsc_csr_update_opcode val) |
|
2196 { |
|
2197 switch (val) { |
|
2198 case EPSC_UPDATE_OP_POLL: |
|
2199 return "EPSC_UPDATE_OP_POLL"; |
|
2200 case EPSC_UPDATE_OP_START: |
|
2201 return "EPSC_UPDATE_OP_START"; |
|
2202 case EPSC_UPDATE_OP_ERASE: |
|
2203 return "EPSC_UPDATE_OP_ERASE"; |
|
2204 case EPSC_UPDATE_OP_WRITE: |
|
2205 return "EPSC_UPDATE_OP_WRITE"; |
|
2206 case EPSC_UPDATE_OP_READ: |
|
2207 return "EPSC_UPDATE_OP_READ"; |
|
2208 case EPSC_UPDATE_OP_STOP: |
|
2209 return "EPSC_UPDATE_OP_STOP"; |
|
2210 case EPSC_UPDATE_OP_SET: |
|
2211 return "EPSC_UPDATE_OP_SET"; |
|
2212 case EPSC_UPDATE_OP_MAX: |
|
2213 return "EPSC_UPDATE_OP_MAX"; |
|
2214 case PSIF_EPSC_CSR_UPDATE_OPCODE_FIELD_MAX: |
|
2215 return "PSIF_EPSC_CSR_UPDATE_OPCODE_FIELD_MAX"; |
|
2216 default: |
|
2217 return "UNKNOWN_psif_epsc_csr_update_opcode"; |
|
2218 } |
|
2219 } |
|
2220 |
|
2221 void write_enum_psif_epsc_csr_update_opcode(XFILE *fd, |
|
2222 enum psif_epsc_csr_update_opcode data) |
|
2223 { |
|
2224 xprintf(fd, "%s", string_enum_psif_epsc_csr_update_opcode(data)); |
|
2225 } /* end write_..._psif_epsc_csr_update_opcode(psif_epsc_csr_update_opcode data) */ |
|
2226 |
|
2227 /* Convert enum psif_epsc_flash_slot to string */ |
|
2228 const char *string_enum_psif_epsc_flash_slot(enum psif_epsc_flash_slot val) |
|
2229 { |
|
2230 switch (val) { |
|
2231 case EPSC_FLASH_SLOT_INVALID: |
|
2232 return "EPSC_FLASH_SLOT_INVALID"; |
|
2233 case EPSC_FLASH_SLOT_EPS_C_IMG_1: |
|
2234 return "EPSC_FLASH_SLOT_EPS_C_IMG_1"; |
|
2235 case EPSC_FLASH_SLOT_EPS_C_IMG_2: |
|
2236 return "EPSC_FLASH_SLOT_EPS_C_IMG_2"; |
|
2237 case EPSC_FLASH_SLOT_EPS_A_IMG: |
|
2238 return "EPSC_FLASH_SLOT_EPS_A_IMG"; |
|
2239 case EPSC_FLASH_SLOT_BOOT_IMG: |
|
2240 return "EPSC_FLASH_SLOT_BOOT_IMG"; |
|
2241 case EPSC_FLASH_SLOT_COUNT: |
|
2242 return "EPSC_FLASH_SLOT_COUNT"; |
|
2243 case PSIF_EPSC_FLASH_SLOT_FIELD_MAX: |
|
2244 return "PSIF_EPSC_FLASH_SLOT_FIELD_MAX"; |
|
2245 default: |
|
2246 return "UNKNOWN_psif_epsc_flash_slot"; |
|
2247 } |
|
2248 } |
|
2249 |
|
2250 void write_enum_psif_epsc_flash_slot(XFILE *fd, |
|
2251 enum psif_epsc_flash_slot data) |
|
2252 { |
|
2253 xprintf(fd, "%s", string_enum_psif_epsc_flash_slot(data)); |
|
2254 } /* end write_..._psif_epsc_flash_slot(psif_epsc_flash_slot data) */ |
|
2255 |
|
2256 /* Convert enum psif_epsc_update_set to string */ |
|
2257 const char *string_enum_psif_epsc_update_set(enum psif_epsc_update_set val) |
|
2258 { |
|
2259 switch (val) { |
|
2260 case EPSC_UPDATE_SET_INVALID: |
|
2261 return "EPSC_UPDATE_SET_INVALID"; |
|
2262 case EPSC_UPDATE_SET_AUTOSTART_IMG: |
|
2263 return "EPSC_UPDATE_SET_AUTOSTART_IMG"; |
|
2264 case EPSC_UPDATE_SET_ONESHOT_IMG: |
|
2265 return "EPSC_UPDATE_SET_ONESHOT_IMG"; |
|
2266 case EPSC_UPDATE_SET_TWOSHOT_IMG: |
|
2267 return "EPSC_UPDATE_SET_TWOSHOT_IMG"; |
|
2268 case EPSC_UPDATE_SET_IMG_VALID: |
|
2269 return "EPSC_UPDATE_SET_IMG_VALID"; |
|
2270 case PSIF_EPSC_UPDATE_SET_FIELD_MAX: |
|
2271 return "PSIF_EPSC_UPDATE_SET_FIELD_MAX"; |
|
2272 default: |
|
2273 return "UNKNOWN_psif_epsc_update_set"; |
|
2274 } |
|
2275 } |
|
2276 |
|
2277 void write_enum_psif_epsc_update_set(XFILE *fd, |
|
2278 enum psif_epsc_update_set data) |
|
2279 { |
|
2280 xprintf(fd, "%s", string_enum_psif_epsc_update_set(data)); |
|
2281 } /* end write_..._psif_epsc_update_set(psif_epsc_update_set data) */ |
|
2282 |
|
2283 /* Convert enum psif_epsc_csr_uf_ctrl_opcode to string */ |
|
2284 const char *string_enum_psif_epsc_csr_uf_ctrl_opcode(enum psif_epsc_csr_uf_ctrl_opcode val) |
|
2285 { |
|
2286 switch (val) { |
|
2287 case EPSC_UF_CTRL_MMU_FLUSH: |
|
2288 return "EPSC_UF_CTRL_MMU_FLUSH"; |
|
2289 case EPSC_UF_CTRL_GET_UF_USED_QP: |
|
2290 return "EPSC_UF_CTRL_GET_UF_USED_QP"; |
|
2291 case EPSC_UF_CTRL_CLEAR_UF_USED_QP: |
|
2292 return "EPSC_UF_CTRL_CLEAR_UF_USED_QP"; |
|
2293 case EPSC_UF_CTRL_SMP_ENABLE: |
|
2294 return "EPSC_UF_CTRL_SMP_ENABLE"; |
|
2295 case EPSC_UF_CTRL_SMP_DISABLE: |
|
2296 return "EPSC_UF_CTRL_SMP_DISABLE"; |
|
2297 case EPSC_UF_CTRL_VLINK_CONNECT: |
|
2298 return "EPSC_UF_CTRL_VLINK_CONNECT"; |
|
2299 case EPSC_UF_CTRL_VLINK_DISCONNECT: |
|
2300 return "EPSC_UF_CTRL_VLINK_DISCONNECT"; |
|
2301 case EPSC_UF_CTRL_GET_HIGHEST_QP_IDX: |
|
2302 return "EPSC_UF_CTRL_GET_HIGHEST_QP_IDX"; |
|
2303 case EPSC_UF_CTRL_RESET_HIGHEST_QP_IDX: |
|
2304 return "EPSC_UF_CTRL_RESET_HIGHEST_QP_IDX"; |
|
2305 case PSIF_EPSC_CSR_UF_CTRL_OPCODE_FIELD_MAX: |
|
2306 return "PSIF_EPSC_CSR_UF_CTRL_OPCODE_FIELD_MAX"; |
|
2307 default: |
|
2308 return "UNKNOWN_psif_epsc_csr_uf_ctrl_opcode"; |
|
2309 } |
|
2310 } |
|
2311 |
|
2312 void write_enum_psif_epsc_csr_uf_ctrl_opcode(XFILE *fd, |
|
2313 enum psif_epsc_csr_uf_ctrl_opcode data) |
|
2314 { |
|
2315 xprintf(fd, "%s", string_enum_psif_epsc_csr_uf_ctrl_opcode(data)); |
|
2316 } /* end write_..._psif_epsc_csr_uf_ctrl_opcode(psif_epsc_csr_uf_ctrl_opcode data) */ |
|
2317 |
|
2318 /* Convert enum psif_epsc_vimma_ctrl_opcode to string */ |
|
2319 const char *string_enum_psif_epsc_vimma_ctrl_opcode(enum psif_epsc_vimma_ctrl_opcode val) |
|
2320 { |
|
2321 switch (val) { |
|
2322 case EPSC_VIMMA_CTRL_GET_VER_AND_COMPAT: |
|
2323 return "EPSC_VIMMA_CTRL_GET_VER_AND_COMPAT"; |
|
2324 case EPSC_VIMMA_CTRL_GET_MISC_INFO: |
|
2325 return "EPSC_VIMMA_CTRL_GET_MISC_INFO"; |
|
2326 case EPSC_VIMMA_CTRL_GET_GUIDS: |
|
2327 return "EPSC_VIMMA_CTRL_GET_GUIDS"; |
|
2328 case EPSC_VIMMA_CTRL_GET_REG_INFO: |
|
2329 return "EPSC_VIMMA_CTRL_GET_REG_INFO"; |
|
2330 case EPSC_VIMMA_CTRL_GET_VHCA_STATS: |
|
2331 return "EPSC_VIMMA_CTRL_GET_VHCA_STATS"; |
|
2332 case EPSC_VIMMA_CTRL_SET_VFP_VHCA_REGISTER: |
|
2333 return "EPSC_VIMMA_CTRL_SET_VFP_VHCA_REGISTER"; |
|
2334 case EPSC_VIMMA_CTRL_SET_VFP_VHCA_DEREGISTER: |
|
2335 return "EPSC_VIMMA_CTRL_SET_VFP_VHCA_DEREGISTER"; |
|
2336 case EPSC_VIMMA_CTRL_SET_ADMIN_MODE: |
|
2337 return "EPSC_VIMMA_CTRL_SET_ADMIN_MODE"; |
|
2338 case PSIF_EPSC_VIMMA_CTRL_OPCODE_FIELD_MAX: |
|
2339 return "PSIF_EPSC_VIMMA_CTRL_OPCODE_FIELD_MAX"; |
|
2340 default: |
|
2341 return "UNKNOWN_psif_epsc_vimma_ctrl_opcode"; |
|
2342 } |
|
2343 } |
|
2344 |
|
2345 void write_enum_psif_epsc_vimma_ctrl_opcode(XFILE *fd, |
|
2346 enum psif_epsc_vimma_ctrl_opcode data) |
|
2347 { |
|
2348 xprintf(fd, "%s", string_enum_psif_epsc_vimma_ctrl_opcode(data)); |
|
2349 } /* end write_..._psif_epsc_vimma_ctrl_opcode(psif_epsc_vimma_ctrl_opcode data) */ |
|
2350 |
|
2351 /* Convert enum psif_epsc_vimma_admmode to string */ |
|
2352 const char *string_enum_psif_epsc_vimma_admmode(enum psif_epsc_vimma_admmode val) |
|
2353 { |
|
2354 switch (val) { |
|
2355 case EPSC_VIMMA_CTRL_IB_ADM_MODE_SM_STANDARD: |
|
2356 return "EPSC_VIMMA_CTRL_IB_ADM_MODE_SM_STANDARD"; |
|
2357 case EPSC_VIMMA_CTRL_IB_ADM_MODE_VM_FABRIC_PROFILE: |
|
2358 return "EPSC_VIMMA_CTRL_IB_ADM_MODE_VM_FABRIC_PROFILE"; |
|
2359 case PSIF_EPSC_VIMMA_ADMMODE_FIELD_MAX: |
|
2360 return "PSIF_EPSC_VIMMA_ADMMODE_FIELD_MAX"; |
|
2361 default: |
|
2362 return "UNKNOWN_psif_epsc_vimma_admmode"; |
|
2363 } |
|
2364 } |
|
2365 |
|
2366 void write_enum_psif_epsc_vimma_admmode(XFILE *fd, |
|
2367 enum psif_epsc_vimma_admmode data) |
|
2368 { |
|
2369 xprintf(fd, "%s", string_enum_psif_epsc_vimma_admmode(data)); |
|
2370 } /* end write_..._psif_epsc_vimma_admmode(psif_epsc_vimma_admmode data) */ |
|
2371 |
|
2372 /* Convert enum psif_cq_state to string */ |
|
2373 const char *string_enum_psif_cq_state(enum psif_cq_state val) |
|
2374 { |
|
2375 switch (val) { |
|
2376 case PSIF_CQ_UNARMED: |
|
2377 return "PSIF_CQ_UNARMED"; |
|
2378 case PSIF_CQ_ARMED_SE: |
|
2379 return "PSIF_CQ_ARMED_SE"; |
|
2380 case PSIF_CQ_ARMED_ALL: |
|
2381 return "PSIF_CQ_ARMED_ALL"; |
|
2382 case PSIF_CQ_TRIGGERED: |
|
2383 return "PSIF_CQ_TRIGGERED"; |
|
2384 default: |
|
2385 return "UNKNOWN_psif_cq_state"; |
|
2386 } |
|
2387 } |
|
2388 |
|
2389 void write_enum_psif_cq_state(XFILE *fd, |
|
2390 enum psif_cq_state data) |
|
2391 { |
|
2392 xprintf(fd, "%s", string_enum_psif_cq_state(data)); |
|
2393 } /* end write_..._psif_cq_state(psif_cq_state data) */ |
|
2394 |
|
2395 /* Convert enum psif_rss_hash_source to string */ |
|
2396 const char *string_enum_psif_rss_hash_source(enum psif_rss_hash_source val) |
|
2397 { |
|
2398 switch (val) { |
|
2399 case RSS_WITHOUT_PORT: |
|
2400 return "RSS_WITHOUT_PORT"; |
|
2401 case RSS_WITH_PORT: |
|
2402 return "RSS_WITH_PORT"; |
|
2403 default: |
|
2404 return "UNKNOWN_psif_rss_hash_source"; |
|
2405 } |
|
2406 } |
|
2407 |
|
2408 void write_enum_psif_rss_hash_source(XFILE *fd, |
|
2409 enum psif_rss_hash_source data) |
|
2410 { |
|
2411 xprintf(fd, "%s", string_enum_psif_rss_hash_source(data)); |
|
2412 } /* end write_..._psif_rss_hash_source(psif_rss_hash_source data) */ |
|
2413 |
|
2414 #if !defined(PSIF_EXCLUDE_WRITE_STRUCTS) |
|
2415 |
|
2416 |
|
2417 void write_struct_psif_csr_mmu_config(XFILE *fd, |
|
2418 int network_order, |
|
2419 const struct psif_csr_mmu_config *data) |
|
2420 { |
|
2421 u64 swap[1]; |
|
2422 |
|
2423 if (network_order) { |
|
2424 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
2425 data = (struct psif_csr_mmu_config *)swap; |
|
2426 } |
|
2427 xprintf(fd, "{"); |
|
2428 xprintf(fd, " .cam_evict_cntr_prescale_sel = "); |
|
2429 write_bits_u8(fd, 3, data->cam_evict_cntr_prescale_sel); |
|
2430 xprintf(fd, ", .cam_evict_cntr_cnt_sel = "); |
|
2431 write_bits_u8(fd, 5, data->cam_evict_cntr_cnt_sel); |
|
2432 xprintf(fd, ", .ptwc_evict_algorithm = "); |
|
2433 write_bits_u8(fd, 1, data->ptwc_evict_algorithm); |
|
2434 xprintf(fd, ", .mmuc_evict_algorithm = "); |
|
2435 write_bits_u8(fd, 1, data->mmuc_evict_algorithm); |
|
2436 xprintf(fd, ", .random_evict = "); |
|
2437 write_bits_u8(fd, 1, data->random_evict); |
|
2438 xprintf(fd, ", .mmuc_hash_select = "); |
|
2439 write_bits_u8(fd, 2, data->mmuc_hash_select); |
|
2440 xprintf(fd, ", .swap_rsp = "); |
|
2441 write_bits_u8(fd, 1, data->swap_rsp); |
|
2442 xprintf(fd, ", .chk_upper_addr_bits = "); |
|
2443 write_bits_u8(fd, 1, data->chk_upper_addr_bits); |
|
2444 xprintf(fd, ", .chk_bit_sixty_three = "); |
|
2445 write_bits_u8(fd, 1, data->chk_bit_sixty_three); |
|
2446 xprintf(fd, ", .bit_sixty_three_value = "); |
|
2447 write_bits_u8(fd, 1, data->bit_sixty_three_value); |
|
2448 xprintf(fd, ", .sparc_pages = "); |
|
2449 write_bits_u8(fd, 1, data->sparc_pages); |
|
2450 xprintf(fd, ", .dma_cnt_mask = "); |
|
2451 write_bits_u8(fd, 8, data->dma_cnt_mask); |
|
2452 xprintf(fd, ", .ptwc_hash_sel = "); |
|
2453 write_bits_u8(fd, 2, data->ptwc_hash_sel); |
|
2454 xprintf(fd, ", .dis_table_ptr_trans = "); |
|
2455 write_bits_u8(fd, 1, data->dis_table_ptr_trans); |
|
2456 xprintf(fd, ", .cam_par_err_fatal = "); |
|
2457 write_bits_u8(fd, 1, data->cam_par_err_fatal); |
|
2458 xprintf(fd, ", .ta_upper_twelve = "); |
|
2459 write_bits_u16(fd, 12, data->ta_upper_twelve); |
|
2460 xprintf(fd, ", .pa_upper_twelve = "); |
|
2461 write_bits_u16(fd, 12, data->pa_upper_twelve); |
|
2462 xprintf(fd, "}"); |
|
2463 } /* end write_..._psif_csr_mmu_config(psif_csr_mmu_config data) */ |
|
2464 |
|
2465 void write_struct_psif_mmu_cntx(XFILE *fd, |
|
2466 int network_order, |
|
2467 const struct psif_mmu_cntx *data) |
|
2468 { |
|
2469 u64 swap[1]; |
|
2470 |
|
2471 if (network_order) { |
|
2472 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
2473 data = (struct psif_mmu_cntx *)swap; |
|
2474 } |
|
2475 xprintf(fd, "{"); |
|
2476 xprintf(fd, " .table_level = "); |
|
2477 write_bits_u8(fd, 3, data->table_level); |
|
2478 xprintf(fd, ", .wr_access = "); |
|
2479 write_bits_u8(fd, 1, data->wr_access); |
|
2480 xprintf(fd, ", .page_size = "); |
|
2481 write_enum_psif_page_size(fd, data->page_size); |
|
2482 xprintf(fd, ", .translation_type = "); |
|
2483 write_enum_psif_mmu_translation(fd, data->translation_type); |
|
2484 xprintf(fd, ", .th = "); |
|
2485 write_bits_u8(fd, 1, data->th); |
|
2486 xprintf(fd, ", .table_ptr = "); |
|
2487 write_bits_u64(fd, 40, data->table_ptr); |
|
2488 xprintf(fd, ", .ro = "); |
|
2489 write_bits_u8(fd, 1, data->ro); |
|
2490 xprintf(fd, ", .tph = "); |
|
2491 write_bits_u8(fd, 2, data->tph); |
|
2492 xprintf(fd, ", .ns = "); |
|
2493 write_bits_u8(fd, 1, data->ns); |
|
2494 xprintf(fd, ", .st = "); |
|
2495 write_bits_u8(fd, 8, data->st); |
|
2496 xprintf(fd, "}"); |
|
2497 } /* end write_..._psif_mmu_cntx(psif_mmu_cntx data) */ |
|
2498 |
|
2499 void write_struct_psif_vlan_union_struct(XFILE *fd, |
|
2500 int network_order, |
|
2501 const struct psif_vlan_union_struct *data) |
|
2502 { |
|
2503 xprintf(fd, "{"); |
|
2504 xprintf(fd, ", .vlan_pri = "); |
|
2505 write_bits_u8(fd, 4, data->vlan_pri); |
|
2506 xprintf(fd, "}"); |
|
2507 } /* end write_..._psif_vlan_union_struct(psif_vlan_union_struct data) */ |
|
2508 |
|
2509 void write_union_psif_cq_desc_vlan_pri(XFILE *fd, |
|
2510 int network_order, |
|
2511 const union psif_cq_desc_vlan_pri *data) |
|
2512 { |
|
2513 xprintf(fd, "{"); |
|
2514 xprintf(fd, " .cqd_id = "); |
|
2515 write_bits_u32(fd, 24, data->cqd_id); |
|
2516 xprintf(fd, ", .vlan_pri = "); |
|
2517 write_struct_psif_vlan_union_struct(fd, 0, &(data->vlan_pri)); |
|
2518 xprintf(fd, "}"); |
|
2519 } /* end write_..._psif_cq_desc_vlan_pri(psif_cq_desc_vlan_pri data) */ |
|
2520 |
|
2521 void write_struct_psif_wr_common(XFILE *fd, |
|
2522 int network_order, |
|
2523 const struct psif_wr_common *data) |
|
2524 { |
|
2525 u64 swap[3]; |
|
2526 |
|
2527 if (network_order) { |
|
2528 copy_convert_to_sw(swap, (volatile void *)data, 24); |
|
2529 data = (struct psif_wr_common *)swap; |
|
2530 } |
|
2531 xprintf(fd, "{"); |
|
2532 xprintf(fd, " .sq_seq = "); |
|
2533 write_bits_u16(fd, 16, data->sq_seq); |
|
2534 xprintf(fd, ", .collect_length = "); |
|
2535 write_bits_u16(fd, 9, data->collect_length); |
|
2536 xprintf(fd, ", .tsu_qosl = "); |
|
2537 write_enum_psif_tsu_qos(fd, data->tsu_qosl); |
|
2538 xprintf(fd, ", .ud_pkt = "); |
|
2539 write_enum_psif_use_ah(fd, data->ud_pkt); |
|
2540 xprintf(fd, ", .port = "); |
|
2541 write_enum_psif_port(fd, data->port); |
|
2542 xprintf(fd, ", .tsu_sl = "); |
|
2543 write_bits_u8(fd, 4, data->tsu_sl); |
|
2544 xprintf(fd, ", .local_qp = "); |
|
2545 write_bits_u32(fd, 24, data->local_qp); |
|
2546 xprintf(fd, ", .op = "); |
|
2547 write_enum_psif_wr_type(fd, data->op); |
|
2548 xprintf(fd, ", .cq_desc_vlan_pri_union = "); |
|
2549 write_union_psif_cq_desc_vlan_pri(fd, 0, &(data->cq_desc_vlan_pri_union)); |
|
2550 xprintf(fd, ", .srcuf = "); |
|
2551 write_bits_u8(fd, 6, data->srcuf); |
|
2552 xprintf(fd, ", .fence = "); |
|
2553 write_bits_u8(fd, 1, data->fence); |
|
2554 xprintf(fd, ", .completion = "); |
|
2555 write_bits_u8(fd, 1, data->completion); |
|
2556 xprintf(fd, ", .eps_tag = "); |
|
2557 write_bits_u16(fd, 16, data->eps_tag); |
|
2558 xprintf(fd, ", .destuf = "); |
|
2559 write_bits_u8(fd, 6, data->destuf); |
|
2560 xprintf(fd, ", .num_sgl = "); |
|
2561 write_bits_u8(fd, 4, data->num_sgl); |
|
2562 xprintf(fd, ", .l4_checksum_en = "); |
|
2563 write_bits_u8(fd, 1, data->l4_checksum_en); |
|
2564 xprintf(fd, ", .l3_checksum_en = "); |
|
2565 write_bits_u8(fd, 1, data->l3_checksum_en); |
|
2566 xprintf(fd, ", .dynamic_mtu_enable = "); |
|
2567 write_bits_u8(fd, 1, data->dynamic_mtu_enable); |
|
2568 xprintf(fd, ", .se = "); |
|
2569 write_bits_u8(fd, 1, data->se); |
|
2570 xprintf(fd, ", .checksum = "); |
|
2571 write_bits_u32(fd, 32, data->checksum); |
|
2572 xprintf(fd, "}"); |
|
2573 } /* end write_..._psif_wr_common(psif_wr_common data) */ |
|
2574 |
|
2575 void write_struct_psif_wr_qp(XFILE *fd, |
|
2576 int network_order, |
|
2577 const struct psif_wr_qp *data) |
|
2578 { |
|
2579 u64 swap[1]; |
|
2580 |
|
2581 if (network_order) { |
|
2582 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
2583 data = (struct psif_wr_qp *)swap; |
|
2584 } |
|
2585 xprintf(fd, "{"); |
|
2586 xprintf(fd, " .qkey = "); |
|
2587 write_bits_u32(fd, 32, data->qkey); |
|
2588 xprintf(fd, ", .remote_qp = "); |
|
2589 write_bits_u32(fd, 24, data->remote_qp); |
|
2590 xprintf(fd, "}"); |
|
2591 } /* end write_..._psif_wr_qp(psif_wr_qp data) */ |
|
2592 |
|
2593 void write_struct_psif_wr_local(XFILE *fd, |
|
2594 int network_order, |
|
2595 const struct psif_wr_local *data) |
|
2596 { |
|
2597 u64 swap[2]; |
|
2598 |
|
2599 if (network_order) { |
|
2600 copy_convert_to_sw(swap, (volatile void *)data, 16); |
|
2601 data = (struct psif_wr_local *)swap; |
|
2602 } |
|
2603 xprintf(fd, "{"); |
|
2604 xprintf(fd, " .addr = "); |
|
2605 write_bits_u64(fd, 64, data->addr); |
|
2606 xprintf(fd, ", .length = "); |
|
2607 write_bits_u32(fd, 32, data->length); |
|
2608 xprintf(fd, ", .lkey = "); |
|
2609 write_bits_u32(fd, 32, data->lkey); |
|
2610 xprintf(fd, "}"); |
|
2611 } /* end write_..._psif_wr_local(psif_wr_local data) */ |
|
2612 |
|
2613 void write_struct_psif_wr_addr(XFILE *fd, |
|
2614 int network_order, |
|
2615 const struct psif_wr_addr *data) |
|
2616 { |
|
2617 xprintf(fd, "{"); |
|
2618 xprintf(fd, " .ah_indx = "); |
|
2619 write_bits_u32(fd, 24, data->ah_indx); |
|
2620 xprintf(fd, "}"); |
|
2621 } /* end write_..._psif_wr_addr(psif_wr_addr data) */ |
|
2622 |
|
2623 void write_struct_psif_wr_send_header_ud(XFILE *fd, |
|
2624 int network_order, |
|
2625 const struct psif_wr_send_header_ud *data) |
|
2626 { |
|
2627 u64 swap[4]; |
|
2628 |
|
2629 if (network_order) { |
|
2630 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
2631 data = (struct psif_wr_send_header_ud *)swap; |
|
2632 } |
|
2633 xprintf(fd, "{"); |
|
2634 xprintf(fd, " .qp = "); |
|
2635 write_struct_psif_wr_qp(fd, 0, &(data->qp)); |
|
2636 xprintf(fd, ", .local_addr = "); |
|
2637 write_struct_psif_wr_local(fd, 0, &(data->local_addr)); |
|
2638 xprintf(fd, ", .mss = "); |
|
2639 write_bits_u16(fd, 14, data->mss); |
|
2640 xprintf(fd, ", .remote_addr = "); |
|
2641 write_struct_psif_wr_addr(fd, 0, &(data->remote_addr)); |
|
2642 xprintf(fd, "}"); |
|
2643 } /* end write_..._psif_wr_send_header_ud(psif_wr_send_header_ud data) */ |
|
2644 |
|
2645 void write_struct_psif_wr_send_header_uc_rc_xrc(XFILE *fd, |
|
2646 int network_order, |
|
2647 const struct psif_wr_send_header_uc_rc_xrc *data) |
|
2648 { |
|
2649 u64 swap[4]; |
|
2650 |
|
2651 if (network_order) { |
|
2652 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
2653 data = (struct psif_wr_send_header_uc_rc_xrc *)swap; |
|
2654 } |
|
2655 xprintf(fd, "{"); |
|
2656 xprintf(fd, " .local_addr = "); |
|
2657 write_struct_psif_wr_local(fd, 0, &(data->local_addr)); |
|
2658 xprintf(fd, ", .mss = "); |
|
2659 write_bits_u16(fd, 14, data->mss); |
|
2660 xprintf(fd, "}"); |
|
2661 } /* end write_..._psif_wr_send_header_uc_rc_xrc(psif_wr_send_header_uc_rc_xrc data) */ |
|
2662 |
|
2663 void write_union_psif_wr_send_header(XFILE *fd, |
|
2664 int network_order, |
|
2665 const union psif_wr_send_header *data) |
|
2666 { |
|
2667 u64 swap[4]; |
|
2668 |
|
2669 if (network_order) { |
|
2670 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
2671 data = (union psif_wr_send_header *)swap; |
|
2672 } |
|
2673 xprintf(fd, "{"); |
|
2674 xprintf(fd, " .ud = "); |
|
2675 write_struct_psif_wr_send_header_ud(fd, 0, &(data->ud)); |
|
2676 xprintf(fd, ", .uc_rc_xrc = "); |
|
2677 write_struct_psif_wr_send_header_uc_rc_xrc(fd, 0, &(data->uc_rc_xrc)); |
|
2678 xprintf(fd, "}"); |
|
2679 } /* end write_..._psif_wr_send_header(psif_wr_send_header data) */ |
|
2680 |
|
2681 void write_struct_psif_wr_remote(XFILE *fd, |
|
2682 int network_order, |
|
2683 const struct psif_wr_remote *data) |
|
2684 { |
|
2685 u64 swap[2]; |
|
2686 |
|
2687 if (network_order) { |
|
2688 copy_convert_to_sw(swap, (volatile void *)data, 16); |
|
2689 data = (struct psif_wr_remote *)swap; |
|
2690 } |
|
2691 xprintf(fd, "{"); |
|
2692 xprintf(fd, " .addr = "); |
|
2693 write_bits_u64(fd, 64, data->addr); |
|
2694 xprintf(fd, ", .length = "); |
|
2695 write_bits_u32(fd, 32, data->length); |
|
2696 xprintf(fd, ", .rkey = "); |
|
2697 write_bits_u32(fd, 32, data->rkey); |
|
2698 xprintf(fd, "}"); |
|
2699 } /* end write_..._psif_wr_remote(psif_wr_remote data) */ |
|
2700 |
|
2701 void write_struct_psif_wr_rdma(XFILE *fd, |
|
2702 int network_order, |
|
2703 const struct psif_wr_rdma *data) |
|
2704 { |
|
2705 u64 swap[4]; |
|
2706 |
|
2707 if (network_order) { |
|
2708 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
2709 data = (struct psif_wr_rdma *)swap; |
|
2710 } |
|
2711 xprintf(fd, "{"); |
|
2712 xprintf(fd, " .local_addr = "); |
|
2713 write_struct_psif_wr_local(fd, 0, &(data->local_addr)); |
|
2714 xprintf(fd, ", .remote_addr = "); |
|
2715 write_struct_psif_wr_remote(fd, 0, &(data->remote_addr)); |
|
2716 xprintf(fd, "}"); |
|
2717 } /* end write_..._psif_wr_rdma(psif_wr_rdma data) */ |
|
2718 |
|
2719 void write_struct_psif_send_completion_id(XFILE *fd, |
|
2720 int network_order, |
|
2721 const struct psif_send_completion_id *data) |
|
2722 { |
|
2723 u64 swap[1]; |
|
2724 |
|
2725 if (network_order) { |
|
2726 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
2727 data = (struct psif_send_completion_id *)swap; |
|
2728 } |
|
2729 xprintf(fd, "{"); |
|
2730 xprintf(fd, " .eps_tag = "); |
|
2731 write_bits_u16(fd, 16, data->eps_tag); |
|
2732 xprintf(fd, ", .sq_seq_num = "); |
|
2733 write_bits_u16(fd, 16, data->sq_seq_num); |
|
2734 xprintf(fd, ", .sequence_number = "); |
|
2735 write_bits_u32(fd, 32, data->sequence_number); |
|
2736 xprintf(fd, "}"); |
|
2737 } /* end write_..._psif_send_completion_id(psif_send_completion_id data) */ |
|
2738 |
|
2739 void write_struct_psif_event_completion_id(XFILE *fd, |
|
2740 int network_order, |
|
2741 const struct psif_event_completion_id *data) |
|
2742 { |
|
2743 u64 swap[1]; |
|
2744 |
|
2745 if (network_order) { |
|
2746 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
2747 data = (struct psif_event_completion_id *)swap; |
|
2748 } |
|
2749 xprintf(fd, "{"); |
|
2750 xprintf(fd, " .cq_id = "); |
|
2751 write_bits_u32(fd, 24, data->cq_id); |
|
2752 xprintf(fd, "}"); |
|
2753 } /* end write_..._psif_event_completion_id(psif_event_completion_id data) */ |
|
2754 |
|
2755 void write_union_psif_completion_wc_id(XFILE *fd, |
|
2756 int network_order, |
|
2757 const union psif_completion_wc_id *data) |
|
2758 { |
|
2759 u64 swap[1]; |
|
2760 |
|
2761 if (network_order) { |
|
2762 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
2763 data = (union psif_completion_wc_id *)swap; |
|
2764 } |
|
2765 xprintf(fd, "{"); |
|
2766 xprintf(fd, " .rq_id = "); |
|
2767 write_bits_u64(fd, 64, data->rq_id); |
|
2768 xprintf(fd, ", .sq_id = "); |
|
2769 write_struct_psif_send_completion_id(fd, 0, &(data->sq_id)); |
|
2770 xprintf(fd, ", .ecq_id = "); |
|
2771 write_struct_psif_event_completion_id(fd, 0, &(data->ecq_id)); |
|
2772 xprintf(fd, "}"); |
|
2773 } /* end write_..._psif_completion_wc_id(psif_completion_wc_id data) */ |
|
2774 |
|
2775 void write_union_psif_descriptor_union(XFILE *fd, |
|
2776 int network_order, |
|
2777 const union psif_descriptor_union *data) |
|
2778 { |
|
2779 xprintf(fd, "{"); |
|
2780 xprintf(fd, " .rq_id = "); |
|
2781 write_bits_u32(fd, 24, data->rq_id); |
|
2782 xprintf(fd, ", .xrq_id = "); |
|
2783 write_bits_u32(fd, 24, data->xrq_id); |
|
2784 xprintf(fd, ", .cq_id = "); |
|
2785 write_bits_u32(fd, 24, data->cq_id); |
|
2786 xprintf(fd, ", .target_qp = "); |
|
2787 write_bits_u32(fd, 24, data->target_qp); |
|
2788 xprintf(fd, "}"); |
|
2789 } /* end write_..._psif_descriptor_union(psif_descriptor_union data) */ |
|
2790 |
|
2791 void write_struct_psif_wr_su(XFILE *fd, |
|
2792 int network_order, |
|
2793 const struct psif_wr_su *data) |
|
2794 { |
|
2795 u64 swap[4]; |
|
2796 |
|
2797 if (network_order) { |
|
2798 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
2799 data = (struct psif_wr_su *)swap; |
|
2800 } |
|
2801 xprintf(fd, "{"); |
|
2802 xprintf(fd, " .wc_id = "); |
|
2803 write_union_psif_completion_wc_id(fd, 0, &(data->wc_id)); |
|
2804 xprintf(fd, ", .addr = "); |
|
2805 write_bits_u64(fd, 64, data->addr); |
|
2806 xprintf(fd, ", .length = "); |
|
2807 write_bits_u32(fd, 32, data->length); |
|
2808 xprintf(fd, ", .key = "); |
|
2809 write_bits_u32(fd, 32, data->key); |
|
2810 xprintf(fd, ", .u2 = "); |
|
2811 write_union_psif_descriptor_union(fd, 0, &(data->u2)); |
|
2812 xprintf(fd, ", .completion_status = "); |
|
2813 write_enum_psif_wc_status(fd, data->completion_status); |
|
2814 xprintf(fd, ", .completion_opcode = "); |
|
2815 write_enum_psif_wc_opcode(fd, data->completion_opcode); |
|
2816 xprintf(fd, ", .srq_lim = "); |
|
2817 write_bits_u16(fd, 14, data->srq_lim); |
|
2818 xprintf(fd, "}"); |
|
2819 } /* end write_..._psif_wr_su(psif_wr_su data) */ |
|
2820 |
|
2821 void write_union_psif_wr_details(XFILE *fd, |
|
2822 int network_order, |
|
2823 const union psif_wr_details *data) |
|
2824 { |
|
2825 u64 swap[4]; |
|
2826 |
|
2827 if (network_order) { |
|
2828 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
2829 data = (union psif_wr_details *)swap; |
|
2830 } |
|
2831 xprintf(fd, "{"); |
|
2832 xprintf(fd, " .send = "); |
|
2833 write_union_psif_wr_send_header(fd, 0, &(data->send)); |
|
2834 xprintf(fd, ", .rdma = "); |
|
2835 write_struct_psif_wr_rdma(fd, 0, &(data->rdma)); |
|
2836 xprintf(fd, ", .atomic = "); |
|
2837 write_struct_psif_wr_rdma(fd, 0, &(data->atomic)); |
|
2838 xprintf(fd, ", .su = "); |
|
2839 write_struct_psif_wr_su(fd, 0, &(data->su)); |
|
2840 xprintf(fd, "}"); |
|
2841 } /* end write_..._psif_wr_details(psif_wr_details data) */ |
|
2842 |
|
2843 void write_struct_psif_wr_xrc(XFILE *fd, |
|
2844 int network_order, |
|
2845 const struct psif_wr_xrc *data) |
|
2846 { |
|
2847 xprintf(fd, "{"); |
|
2848 xprintf(fd, " .xrqd_id = "); |
|
2849 write_bits_u32(fd, 24, data->xrqd_id); |
|
2850 xprintf(fd, "}"); |
|
2851 } /* end write_..._psif_wr_xrc(psif_wr_xrc data) */ |
|
2852 |
|
2853 void write_struct_psif_wr(XFILE *fd, |
|
2854 int network_order, |
|
2855 const struct psif_wr *data) |
|
2856 { |
|
2857 enum psif_wr_type op; |
|
2858 enum psif_use_ah ud; |
|
2859 struct psif_wr swap; |
|
2860 |
|
2861 if (network_order) { |
|
2862 copy_convert_to_sw(&swap, (volatile void *)data, 64); |
|
2863 data = &swap; |
|
2864 } |
|
2865 |
|
2866 op = data->op; |
|
2867 ud = data->ud_pkt; |
|
2868 |
|
2869 /* assertion: offsetof(struct psif_wr, imm) == sizeof(struct psif_wr_common) */ |
|
2870 xprintf(fd, "{"); |
|
2871 write_struct_psif_wr_common(fd, 0, (struct psif_wr_common *)data); |
|
2872 if ((op == PSIF_WR_SEND_IMM) || (op == PSIF_WR_RDMA_WR_IMM)) { |
|
2873 xprintf(fd, " .imm = "); |
|
2874 write_bits_u32(fd, 32, data->imm); |
|
2875 } |
|
2876 |
|
2877 xprintf(fd, " .details = "); |
|
2878 /* write_union_psif_wr_details(fd, 0, &(data->details)); */ |
|
2879 xprintf(fd, "{"); |
|
2880 /* write_union_psif_wr_send_header(fd, 0, &(data->send)); */ |
|
2881 |
|
2882 switch (op) { |
|
2883 case PSIF_WR_SEND: |
|
2884 case PSIF_WR_SEND_IMM: |
|
2885 case PSIF_WR_SPECIAL_QP_SEND: |
|
2886 case PSIF_WR_QP0_SEND_DR_XMIT: |
|
2887 case PSIF_WR_QP0_SEND_DR_LOOPBACK: |
|
2888 case PSIF_WR_EPS_SPECIAL_QP_SEND: |
|
2889 case PSIF_WR_EPS_QP0_SEND_DR_XMIT: |
|
2890 case PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK: |
|
2891 xprintf(fd, " send = "); |
|
2892 xprintf(fd, "{"); |
|
2893 if (ud) { |
|
2894 xprintf(fd, " .ud = "); |
|
2895 write_struct_psif_wr_send_header_ud(fd, 0, &(data->details.send.ud)); |
|
2896 } else { |
|
2897 xprintf(fd, " .uc_rc_xrc = "); |
|
2898 write_struct_psif_wr_send_header_uc_rc_xrc(fd, 0, &(data->details.send.uc_rc_xrc)); |
|
2899 } |
|
2900 xprintf(fd, "}"); |
|
2901 break; |
|
2902 |
|
2903 case PSIF_WR_RDMA_WR: |
|
2904 case PSIF_WR_RDMA_WR_IMM: |
|
2905 case PSIF_WR_RDMA_RD: |
|
2906 xprintf(fd, " .rdma = "); |
|
2907 write_struct_psif_wr_rdma(fd, 0, &(data->details.rdma)); |
|
2908 break; |
|
2909 |
|
2910 case PSIF_WR_CMP_SWAP: |
|
2911 case PSIF_WR_FETCH_ADD: |
|
2912 case PSIF_WR_MASK_CMP_SWAP: |
|
2913 case PSIF_WR_MASK_FETCH_ADD: |
|
2914 xprintf(fd, " .atomic = "); |
|
2915 write_struct_psif_wr_rdma(fd, 0, &(data->details.atomic)); |
|
2916 break; |
|
2917 |
|
2918 case PSIF_WR_INVALIDATE_RKEY: |
|
2919 case PSIF_WR_INVALIDATE_LKEY: |
|
2920 case PSIF_WR_INVALIDATE_BOTH_KEYS: |
|
2921 case PSIF_WR_INVALIDATE_TLB: |
|
2922 case PSIF_WR_RESIZE_CQ: |
|
2923 case PSIF_WR_SET_SRQ_LIM: |
|
2924 case PSIF_WR_SET_XRCSRQ_LIM: |
|
2925 case PSIF_WR_REQ_CMPL_NOTIFY: |
|
2926 case PSIF_WR_CMPL_NOTIFY_RCVD: |
|
2927 case PSIF_WR_REARM_CMPL_EVENT: |
|
2928 case PSIF_WR_INVALIDATE_RQ: |
|
2929 case PSIF_WR_INVALIDATE_CQ: |
|
2930 case PSIF_WR_INVALIDATE_XRCSRQ: |
|
2931 case PSIF_WR_INVALIDATE_SGL_CACHE: |
|
2932 case PSIF_WR_GENERATE_COMPLETION: |
|
2933 xprintf(fd, " .su = "); |
|
2934 write_struct_psif_wr_su(fd, 0, &(data->details.su)); |
|
2935 break; |
|
2936 |
|
2937 case PSIF_WR_LSO: |
|
2938 break; |
|
2939 } |
|
2940 xprintf(fd, "}"); |
|
2941 |
|
2942 xprintf(fd, " .xrc_hdr = "); |
|
2943 write_struct_psif_wr_xrc(fd, 0, &(data->xrc_hdr)); |
|
2944 xprintf(fd, "}"); |
|
2945 } |
|
2946 |
|
2947 void write_struct_psif_wr_expand(XFILE *fd, |
|
2948 int network_order, |
|
2949 const struct psif_wr *data) |
|
2950 { |
|
2951 u64 swap[8]; |
|
2952 |
|
2953 if (network_order) { |
|
2954 copy_convert_to_sw(swap, (volatile void *)data, 64); |
|
2955 data = (struct psif_wr *)swap; |
|
2956 } |
|
2957 xprintf(fd, "{"); |
|
2958 xprintf(fd, " .sq_seq = "); |
|
2959 write_bits_u16(fd, 16, data->sq_seq); |
|
2960 xprintf(fd, ", .collect_length = "); |
|
2961 write_bits_u16(fd, 9, data->collect_length); |
|
2962 xprintf(fd, ", .tsu_qosl = "); |
|
2963 write_enum_psif_tsu_qos(fd, data->tsu_qosl); |
|
2964 xprintf(fd, ", .ud_pkt = "); |
|
2965 write_enum_psif_use_ah(fd, data->ud_pkt); |
|
2966 xprintf(fd, ", .port = "); |
|
2967 write_enum_psif_port(fd, data->port); |
|
2968 xprintf(fd, ", .tsu_sl = "); |
|
2969 write_bits_u8(fd, 4, data->tsu_sl); |
|
2970 xprintf(fd, ", .local_qp = "); |
|
2971 write_bits_u32(fd, 24, data->local_qp); |
|
2972 xprintf(fd, ", .op = "); |
|
2973 write_enum_psif_wr_type(fd, data->op); |
|
2974 xprintf(fd, ", .cq_desc_vlan_pri_union = "); |
|
2975 write_union_psif_cq_desc_vlan_pri(fd, 0, &(data->cq_desc_vlan_pri_union)); |
|
2976 xprintf(fd, ", .srcuf = "); |
|
2977 write_bits_u8(fd, 6, data->srcuf); |
|
2978 xprintf(fd, ", .fence = "); |
|
2979 write_bits_u8(fd, 1, data->fence); |
|
2980 xprintf(fd, ", .completion = "); |
|
2981 write_bits_u8(fd, 1, data->completion); |
|
2982 xprintf(fd, ", .eps_tag = "); |
|
2983 write_bits_u16(fd, 16, data->eps_tag); |
|
2984 xprintf(fd, ", .destuf = "); |
|
2985 write_bits_u8(fd, 6, data->destuf); |
|
2986 xprintf(fd, ", .num_sgl = "); |
|
2987 write_bits_u8(fd, 4, data->num_sgl); |
|
2988 xprintf(fd, ", .l4_checksum_en = "); |
|
2989 write_bits_u8(fd, 1, data->l4_checksum_en); |
|
2990 xprintf(fd, ", .l3_checksum_en = "); |
|
2991 write_bits_u8(fd, 1, data->l3_checksum_en); |
|
2992 xprintf(fd, ", .dynamic_mtu_enable = "); |
|
2993 write_bits_u8(fd, 1, data->dynamic_mtu_enable); |
|
2994 xprintf(fd, ", .se = "); |
|
2995 write_bits_u8(fd, 1, data->se); |
|
2996 xprintf(fd, ", .imm = "); |
|
2997 write_bits_u32(fd, 32, data->imm); |
|
2998 xprintf(fd, ", .checksum = "); |
|
2999 write_bits_u32(fd, 32, data->checksum); |
|
3000 xprintf(fd, ", .details = "); |
|
3001 write_union_psif_wr_details(fd, 0, &(data->details)); |
|
3002 xprintf(fd, ", .xrc_hdr = "); |
|
3003 write_struct_psif_wr_xrc(fd, 0, &(data->xrc_hdr)); |
|
3004 xprintf(fd, "}"); |
|
3005 } /* end write_..._psif_wr(psif_wr data) */ |
|
3006 |
|
3007 void write_struct_psif_next(XFILE *fd, |
|
3008 int network_order, |
|
3009 const struct psif_next *data) |
|
3010 { |
|
3011 xprintf(fd, "{"); |
|
3012 xprintf(fd, " .next_null = "); |
|
3013 write_bits_u8(fd, 8, data->next_null); |
|
3014 xprintf(fd, ", .next_qp_num = "); |
|
3015 write_bits_u32(fd, 24, data->next_qp_num); |
|
3016 xprintf(fd, "}"); |
|
3017 } /* end write_..._psif_next(psif_next data) */ |
|
3018 |
|
3019 void write_struct_psif_sq_sw(XFILE *fd, |
|
3020 int network_order, |
|
3021 const struct psif_sq_sw *data) |
|
3022 { |
|
3023 u64 swap[1]; |
|
3024 |
|
3025 if (network_order) { |
|
3026 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
3027 data = (struct psif_sq_sw *)swap; |
|
3028 } |
|
3029 xprintf(fd, "{"); |
|
3030 xprintf(fd, ", .tail_indx = "); |
|
3031 write_bits_u16(fd, 16, data->tail_indx); |
|
3032 xprintf(fd, "}"); |
|
3033 } /* end write_..._psif_sq_sw(psif_sq_sw data) */ |
|
3034 |
|
3035 void write_struct_psif_sq_hw(XFILE *fd, |
|
3036 int network_order, |
|
3037 const struct psif_sq_hw *data) |
|
3038 { |
|
3039 u64 swap[4]; |
|
3040 |
|
3041 if (network_order) { |
|
3042 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
3043 data = (struct psif_sq_hw *)swap; |
|
3044 } |
|
3045 xprintf(fd, "{"); |
|
3046 xprintf(fd, " .u_1 = "); |
|
3047 write_bits_u16(fd, 16, data->u_1); |
|
3048 xprintf(fd, ", .last_seq = "); |
|
3049 write_bits_u16(fd, 16, data->last_seq); |
|
3050 xprintf(fd, ", .sq_next = "); |
|
3051 write_struct_psif_next(fd, 0, &(data->sq_next)); |
|
3052 xprintf(fd, ", .sq_max_inline = "); |
|
3053 write_bits_u16(fd, 9, data->sq_max_inline); |
|
3054 xprintf(fd, ", .size_log2 = "); |
|
3055 write_bits_u8(fd, 4, data->size_log2); |
|
3056 xprintf(fd, ", .sq_max_sge = "); |
|
3057 write_bits_u8(fd, 5, data->sq_max_sge); |
|
3058 xprintf(fd, ", .extent_log2 = "); |
|
3059 write_bits_u8(fd, 5, data->extent_log2); |
|
3060 xprintf(fd, ", .qos = "); |
|
3061 write_bits_u8(fd, 1, data->qos); |
|
3062 xprintf(fd, ", .sq_timestamp_valid = "); |
|
3063 write_bits_u8(fd, 1, data->sq_timestamp_valid); |
|
3064 xprintf(fd, ", .sq_done = "); |
|
3065 write_bits_u8(fd, 2, data->sq_done); |
|
3066 xprintf(fd, ", .destroyed = "); |
|
3067 write_bits_u8(fd, 1, data->destroyed); |
|
3068 xprintf(fd, ", .u_2 = "); |
|
3069 write_bits_u32(fd, 32, data->u_2); |
|
3070 xprintf(fd, ", .base_addr = "); |
|
3071 write_bits_u64(fd, 64, data->base_addr); |
|
3072 xprintf(fd, ", .mmu_cntx = "); |
|
3073 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
3074 xprintf(fd, "}"); |
|
3075 } /* end write_..._psif_sq_hw(psif_sq_hw data) */ |
|
3076 |
|
3077 void write_struct_psif_sq_entry(XFILE *fd, |
|
3078 int network_order, |
|
3079 const struct psif_sq_entry *data) |
|
3080 { |
|
3081 u64 swap[40]; |
|
3082 |
|
3083 if (network_order) { |
|
3084 copy_convert_to_sw(swap, (volatile void *)data, 320); |
|
3085 data = (struct psif_sq_entry *)swap; |
|
3086 } |
|
3087 xprintf(fd, "{"); |
|
3088 xprintf(fd, " .wr = "); |
|
3089 write_struct_psif_wr(fd, 0, &(data->wr)); |
|
3090 xprintf(fd, ", .payload = "); |
|
3091 { unsigned int i; for (i = 0; i < 32; i++) { |
|
3092 write_bits_u64(fd, 64, data->payload[i]); |
|
3093 xprintf(fd, ","); |
|
3094 } |
|
3095 } |
|
3096 xprintf(fd, "}"); |
|
3097 } /* end write_..._psif_sq_entry(psif_sq_entry data) */ |
|
3098 |
|
3099 void write_struct_psif_rq_scatter(XFILE *fd, |
|
3100 int network_order, |
|
3101 const struct psif_rq_scatter *data) |
|
3102 { |
|
3103 u64 swap[2]; |
|
3104 |
|
3105 if (network_order) { |
|
3106 copy_convert_to_sw(swap, (volatile void *)data, 16); |
|
3107 data = (struct psif_rq_scatter *)swap; |
|
3108 } |
|
3109 xprintf(fd, "{"); |
|
3110 xprintf(fd, " .base_addr = "); |
|
3111 write_bits_u64(fd, 64, data->base_addr); |
|
3112 xprintf(fd, ", .lkey = "); |
|
3113 write_bits_u32(fd, 32, data->lkey); |
|
3114 xprintf(fd, ", .length = "); |
|
3115 write_bits_u32(fd, 32, data->length); |
|
3116 xprintf(fd, "}"); |
|
3117 } /* end write_..._psif_rq_scatter(psif_rq_scatter data) */ |
|
3118 |
|
3119 void write_struct_psif_rq_sw(XFILE *fd, |
|
3120 int network_order, |
|
3121 const struct psif_rq_sw *data) |
|
3122 { |
|
3123 u64 swap[1]; |
|
3124 |
|
3125 if (network_order) { |
|
3126 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
3127 data = (struct psif_rq_sw *)swap; |
|
3128 } |
|
3129 xprintf(fd, "{"); |
|
3130 xprintf(fd, ", .tail_indx = "); |
|
3131 write_bits_u16(fd, 14, data->tail_indx); |
|
3132 xprintf(fd, "}"); |
|
3133 } /* end write_..._psif_rq_sw(psif_rq_sw data) */ |
|
3134 |
|
3135 void write_struct_psif_rq_hw(XFILE *fd, |
|
3136 int network_order, |
|
3137 const struct psif_rq_hw *data) |
|
3138 { |
|
3139 u64 swap[4]; |
|
3140 |
|
3141 if (network_order) { |
|
3142 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
3143 data = (struct psif_rq_hw *)swap; |
|
3144 } |
|
3145 xprintf(fd, "{"); |
|
3146 xprintf(fd, " .srq_lim = "); |
|
3147 write_bits_u16(fd, 14, data->srq_lim); |
|
3148 xprintf(fd, ", .head_indx = "); |
|
3149 write_bits_u16(fd, 14, data->head_indx); |
|
3150 xprintf(fd, ", .extent_log2 = "); |
|
3151 write_bits_u8(fd, 4, data->extent_log2); |
|
3152 xprintf(fd, ", .pd = "); |
|
3153 write_bits_u32(fd, 24, data->pd); |
|
3154 xprintf(fd, ", .scatter = "); |
|
3155 write_bits_u8(fd, 4, data->scatter); |
|
3156 xprintf(fd, ", .srq_err = "); |
|
3157 write_bits_u8(fd, 1, data->srq_err); |
|
3158 xprintf(fd, ", .srq = "); |
|
3159 write_bits_u8(fd, 1, data->srq); |
|
3160 xprintf(fd, ", .sticky = "); |
|
3161 write_bits_u8(fd, 1, data->sticky); |
|
3162 xprintf(fd, ", .base_addr = "); |
|
3163 write_bits_u64(fd, 64, data->base_addr); |
|
3164 xprintf(fd, ", .mmu_cntx = "); |
|
3165 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
3166 xprintf(fd, ", .valid = "); |
|
3167 write_bits_u8(fd, 1, data->valid); |
|
3168 xprintf(fd, ", .prefetch_threshold_log2 = "); |
|
3169 write_bits_u8(fd, 4, data->prefetch_threshold_log2); |
|
3170 xprintf(fd, ", .size_log2 = "); |
|
3171 write_bits_u8(fd, 4, data->size_log2); |
|
3172 xprintf(fd, "}"); |
|
3173 } /* end write_..._psif_rq_hw(psif_rq_hw data) */ |
|
3174 |
|
3175 void write_struct_psif_rq_entry(XFILE *fd, |
|
3176 int network_order, |
|
3177 const struct psif_rq_entry *data) |
|
3178 { |
|
3179 u64 swap[33]; |
|
3180 |
|
3181 if (network_order) { |
|
3182 copy_convert_to_sw(swap, (volatile void *)data, 264); |
|
3183 data = (struct psif_rq_entry *)swap; |
|
3184 } |
|
3185 xprintf(fd, "{"); |
|
3186 xprintf(fd, " .rqe_id = "); |
|
3187 write_bits_u64(fd, 64, data->rqe_id); |
|
3188 xprintf(fd, ", .scatter = "); |
|
3189 { unsigned int i; for (i = 0; i < 16; i++) { |
|
3190 write_struct_psif_rq_scatter(fd, 0, &(data->scatter[i])); |
|
3191 xprintf(fd, ","); |
|
3192 } |
|
3193 } |
|
3194 xprintf(fd, "}"); |
|
3195 } /* end write_..._psif_rq_entry(psif_rq_entry data) */ |
|
3196 |
|
3197 void write_struct_psif_qp_core(XFILE *fd, |
|
3198 int network_order, |
|
3199 const struct psif_qp_core *data) |
|
3200 { |
|
3201 u64 swap[16]; |
|
3202 |
|
3203 if (network_order) { |
|
3204 copy_convert_to_sw(swap, (volatile void *)data, 128); |
|
3205 data = (struct psif_qp_core *)swap; |
|
3206 } |
|
3207 xprintf(fd, "{"); |
|
3208 xprintf(fd, " .retry_tag_committed = "); |
|
3209 write_bits_u8(fd, 3, data->retry_tag_committed); |
|
3210 xprintf(fd, ", .retry_tag_err = "); |
|
3211 write_bits_u8(fd, 3, data->retry_tag_err); |
|
3212 xprintf(fd, ", .req_access_error = "); |
|
3213 write_bits_u8(fd, 1, data->req_access_error); |
|
3214 xprintf(fd, ", .resp_access_error = "); |
|
3215 write_bits_u8(fd, 1, data->resp_access_error); |
|
3216 xprintf(fd, ", .xrc_domain = "); |
|
3217 write_bits_u32(fd, 24, data->xrc_domain); |
|
3218 xprintf(fd, ", .error_retry_init = "); |
|
3219 write_bits_u8(fd, 3, data->error_retry_init); |
|
3220 xprintf(fd, ", .error_retry_count = "); |
|
3221 write_bits_u8(fd, 3, data->error_retry_count); |
|
3222 xprintf(fd, ", .cq_in_err = "); |
|
3223 write_bits_u8(fd, 1, data->cq_in_err); |
|
3224 xprintf(fd, ", .spin_hit = "); |
|
3225 write_bits_u8(fd, 1, data->spin_hit); |
|
3226 xprintf(fd, ", .sq_clog2_extent = "); |
|
3227 write_bits_u8(fd, 5, data->sq_clog2_extent); |
|
3228 xprintf(fd, ", .sq_clog2_size = "); |
|
3229 write_bits_u8(fd, 4, data->sq_clog2_size); |
|
3230 xprintf(fd, ", .current_outstanding = "); |
|
3231 write_bits_u8(fd, 5, data->current_outstanding); |
|
3232 xprintf(fd, ", .current_retired = "); |
|
3233 write_bits_u8(fd, 5, data->current_retired); |
|
3234 xprintf(fd, ", .is_multicast = "); |
|
3235 write_bits_u8(fd, 1, data->is_multicast); |
|
3236 xprintf(fd, ", .dscr_rq_in_progress = "); |
|
3237 write_bits_u8(fd, 1, data->dscr_rq_in_progress); |
|
3238 xprintf(fd, ", .first_at_floor_seen = "); |
|
3239 write_bits_u8(fd, 1, data->first_at_floor_seen); |
|
3240 xprintf(fd, ", .rq_is_srq = "); |
|
3241 write_bits_u8(fd, 1, data->rq_is_srq); |
|
3242 xprintf(fd, ", .do_not_evict = "); |
|
3243 write_bits_u8(fd, 1, data->do_not_evict); |
|
3244 xprintf(fd, ", .min_rnr_nak_time = "); |
|
3245 write_bits_u8(fd, 5, data->min_rnr_nak_time); |
|
3246 xprintf(fd, ", .state = "); |
|
3247 write_enum_psif_qp_state(fd, data->state); |
|
3248 xprintf(fd, ", .remote_qp = "); |
|
3249 write_bits_u32(fd, 24, data->remote_qp); |
|
3250 xprintf(fd, ", .rcv_rkey = "); |
|
3251 write_bits_u32(fd, 32, data->rcv_rkey); |
|
3252 xprintf(fd, ", .rcv_bytes = "); |
|
3253 write_bits_u32(fd, 32, data->rcv_bytes); |
|
3254 xprintf(fd, ", .retry_sq_seq = "); |
|
3255 write_bits_u16(fd, 16, data->retry_sq_seq); |
|
3256 xprintf(fd, ", .sq_seq = "); |
|
3257 write_bits_u16(fd, 16, data->sq_seq); |
|
3258 xprintf(fd, ", .magic = "); |
|
3259 write_bits_u32(fd, 32, data->magic); |
|
3260 xprintf(fd, ", .cq_seq = "); |
|
3261 write_bits_u32(fd, 32, data->cq_seq); |
|
3262 xprintf(fd, ", .qkey = "); |
|
3263 write_bits_u32(fd, 32, data->qkey); |
|
3264 xprintf(fd, ", .ib_retry_outstanding = "); |
|
3265 write_bits_u8(fd, 1, data->ib_retry_outstanding); |
|
3266 xprintf(fd, ", .fence_retry_outstanding = "); |
|
3267 write_bits_u8(fd, 1, data->fence_retry_outstanding); |
|
3268 xprintf(fd, ", .flush_started = "); |
|
3269 write_bits_u8(fd, 1, data->flush_started); |
|
3270 xprintf(fd, ", .request_handled = "); |
|
3271 write_bits_u8(fd, 1, data->request_handled); |
|
3272 xprintf(fd, ", .outstanding_error = "); |
|
3273 write_enum_psif_cmpl_outstanding_error(fd, data->outstanding_error); |
|
3274 xprintf(fd, ", .last_acked_psn = "); |
|
3275 write_bits_u32(fd, 24, data->last_acked_psn); |
|
3276 xprintf(fd, ", .scatter_offs = "); |
|
3277 write_bits_u32(fd, 32, data->scatter_offs); |
|
3278 xprintf(fd, ", .scatter_indx = "); |
|
3279 write_bits_u8(fd, 5, data->scatter_indx); |
|
3280 xprintf(fd, ", .expected_opcode = "); |
|
3281 write_enum_psif_expected_op(fd, data->expected_opcode); |
|
3282 xprintf(fd, ", .psn_nak = "); |
|
3283 write_bits_u8(fd, 1, data->psn_nak); |
|
3284 xprintf(fd, ", .expected_psn = "); |
|
3285 write_bits_u32(fd, 24, data->expected_psn); |
|
3286 xprintf(fd, ", .timeout_time = "); |
|
3287 write_bits_u64(fd, 48, data->timeout_time); |
|
3288 xprintf(fd, ", .nak_sent = "); |
|
3289 write_bits_u8(fd, 1, data->nak_sent); |
|
3290 xprintf(fd, ", .qosl = "); |
|
3291 write_enum_psif_tsu_qos(fd, data->qosl); |
|
3292 xprintf(fd, ", .mstate = "); |
|
3293 write_enum_psif_migration(fd, data->mstate); |
|
3294 xprintf(fd, ", .eoib_enable = "); |
|
3295 write_bits_u8(fd, 1, data->eoib_enable); |
|
3296 xprintf(fd, ", .ipoib_enable = "); |
|
3297 write_bits_u8(fd, 1, data->ipoib_enable); |
|
3298 xprintf(fd, ", .hdr_split_enable = "); |
|
3299 write_bits_u8(fd, 1, data->hdr_split_enable); |
|
3300 xprintf(fd, ", .rcv_dynamic_mtu_enable = "); |
|
3301 write_bits_u8(fd, 1, data->rcv_dynamic_mtu_enable); |
|
3302 xprintf(fd, ", .proxy_qp_enable = "); |
|
3303 write_bits_u8(fd, 1, data->proxy_qp_enable); |
|
3304 xprintf(fd, ", .rss_enable = "); |
|
3305 write_bits_u8(fd, 1, data->rss_enable); |
|
3306 xprintf(fd, ", .masked_atomic_enable = "); |
|
3307 write_bits_u8(fd, 1, data->masked_atomic_enable); |
|
3308 xprintf(fd, ", .atomic_enable = "); |
|
3309 write_bits_u8(fd, 1, data->atomic_enable); |
|
3310 xprintf(fd, ", .rdma_wr_enable = "); |
|
3311 write_bits_u8(fd, 1, data->rdma_wr_enable); |
|
3312 xprintf(fd, ", .rdma_rd_enable = "); |
|
3313 write_bits_u8(fd, 1, data->rdma_rd_enable); |
|
3314 xprintf(fd, ", .xmit_psn = "); |
|
3315 write_bits_u32(fd, 24, data->xmit_psn); |
|
3316 xprintf(fd, ", .retry_xmit_psn = "); |
|
3317 write_bits_u32(fd, 24, data->retry_xmit_psn); |
|
3318 xprintf(fd, ", .resp_scatter_indx = "); |
|
3319 write_bits_u8(fd, 5, data->resp_scatter_indx); |
|
3320 xprintf(fd, ", .rc_in_error = "); |
|
3321 write_bits_u8(fd, 1, data->rc_in_error); |
|
3322 xprintf(fd, ", .timer_running = "); |
|
3323 write_bits_u8(fd, 1, data->timer_running); |
|
3324 xprintf(fd, ", .tsl = "); |
|
3325 write_bits_u8(fd, 4, data->tsl); |
|
3326 xprintf(fd, ", .max_outstanding = "); |
|
3327 write_bits_u8(fd, 5, data->max_outstanding); |
|
3328 xprintf(fd, ", .dmalen = "); |
|
3329 write_bits_u32(fd, 32, data->dmalen); |
|
3330 xprintf(fd, ", .rnr_retry_init = "); |
|
3331 write_bits_u8(fd, 3, data->rnr_retry_init); |
|
3332 xprintf(fd, ", .rnr_retry_count = "); |
|
3333 write_bits_u8(fd, 3, data->rnr_retry_count); |
|
3334 xprintf(fd, ", .no_ordering = "); |
|
3335 write_bits_u8(fd, 1, data->no_ordering); |
|
3336 xprintf(fd, ", .no_checksum = "); |
|
3337 write_bits_u8(fd, 1, data->no_checksum); |
|
3338 xprintf(fd, ", .rq_indx = "); |
|
3339 write_bits_u32(fd, 24, data->rq_indx); |
|
3340 xprintf(fd, ", .transport_type = "); |
|
3341 write_enum_psif_qp_trans(fd, data->transport_type); |
|
3342 xprintf(fd, ", .rcv_cq_indx = "); |
|
3343 write_bits_u32(fd, 24, data->rcv_cq_indx); |
|
3344 xprintf(fd, ", .bytes_received = "); |
|
3345 write_bits_u32(fd, 32, data->bytes_received); |
|
3346 xprintf(fd, ", .eoib_type = "); |
|
3347 write_enum_psif_eoib_type(fd, data->eoib_type); |
|
3348 xprintf(fd, ", .exp_backoff_enable = "); |
|
3349 write_bits_u8(fd, 1, data->exp_backoff_enable); |
|
3350 xprintf(fd, ", .not_so_privileged = "); |
|
3351 write_bits_u8(fd, 1, data->not_so_privileged); |
|
3352 xprintf(fd, ", .send_dynamic_mtu_enable = "); |
|
3353 write_bits_u8(fd, 1, data->send_dynamic_mtu_enable); |
|
3354 xprintf(fd, ", .ipoib = "); |
|
3355 write_bits_u8(fd, 1, data->ipoib); |
|
3356 xprintf(fd, ", .eoib = "); |
|
3357 write_bits_u8(fd, 1, data->eoib); |
|
3358 xprintf(fd, ", .wait_for_psn = "); |
|
3359 write_bits_u8(fd, 1, data->wait_for_psn); |
|
3360 xprintf(fd, ", .resp_sched_count_done = "); |
|
3361 write_bits_u32(fd, 24, data->resp_sched_count_done); |
|
3362 xprintf(fd, ", .resp_sched_count_sched = "); |
|
3363 write_bits_u32(fd, 24, data->resp_sched_count_sched); |
|
3364 xprintf(fd, ", .resp_sched_sched_ptr = "); |
|
3365 write_bits_u8(fd, 5, data->resp_sched_sched_ptr); |
|
3366 xprintf(fd, ", .resp_sched_mode = "); |
|
3367 write_bits_u8(fd, 1, data->resp_sched_mode); |
|
3368 xprintf(fd, ", .swapped = "); |
|
3369 write_enum_psif_bool(fd, data->swapped); |
|
3370 xprintf(fd, ", .retry_needed = "); |
|
3371 write_bits_u8(fd, 1, data->retry_needed); |
|
3372 xprintf(fd, ", .last_received_outstanding_msn = "); |
|
3373 write_bits_u16(fd, 16, data->last_received_outstanding_msn); |
|
3374 xprintf(fd, ", .host_sent_nak = "); |
|
3375 write_bits_u8(fd, 1, data->host_sent_nak); |
|
3376 xprintf(fd, ", .in_safe_mode = "); |
|
3377 write_bits_u8(fd, 1, data->in_safe_mode); |
|
3378 xprintf(fd, ", .atomic_error = "); |
|
3379 write_bits_u8(fd, 1, data->atomic_error); |
|
3380 xprintf(fd, ", .apm_failed_event_sent = "); |
|
3381 write_bits_u8(fd, 1, data->apm_failed_event_sent); |
|
3382 xprintf(fd, ", .apm_success_event_sent = "); |
|
3383 write_bits_u8(fd, 1, data->apm_success_event_sent); |
|
3384 xprintf(fd, ", .apm_failed_event_needed = "); |
|
3385 write_bits_u8(fd, 1, data->apm_failed_event_needed); |
|
3386 xprintf(fd, ", .apm_success_event_needed = "); |
|
3387 write_bits_u8(fd, 1, data->apm_success_event_needed); |
|
3388 xprintf(fd, ", .req_addr = "); |
|
3389 write_bits_u64(fd, 64, data->req_addr); |
|
3390 xprintf(fd, ", .orig_atomic_wr_ptr = "); |
|
3391 write_bits_u8(fd, 4, data->orig_atomic_wr_ptr); |
|
3392 xprintf(fd, ", .path_mtu = "); |
|
3393 write_enum_psif_path_mtu(fd, data->path_mtu); |
|
3394 xprintf(fd, ", .comm_established = "); |
|
3395 write_enum_psif_comm_live(fd, data->comm_established); |
|
3396 xprintf(fd, ", .committed_received_psn = "); |
|
3397 write_bits_u32(fd, 24, data->committed_received_psn); |
|
3398 xprintf(fd, ", .resp_scatter_offs = "); |
|
3399 write_bits_u32(fd, 32, data->resp_scatter_offs); |
|
3400 xprintf(fd, ", .msn = "); |
|
3401 write_bits_u32(fd, 24, data->msn); |
|
3402 xprintf(fd, ", .send_cq_indx = "); |
|
3403 write_bits_u32(fd, 24, data->send_cq_indx); |
|
3404 xprintf(fd, ", .last_committed_msn = "); |
|
3405 write_bits_u16(fd, 16, data->last_committed_msn); |
|
3406 xprintf(fd, ", .srq_pd = "); |
|
3407 write_bits_u32(fd, 24, data->srq_pd); |
|
3408 xprintf(fd, ", .pd = "); |
|
3409 write_bits_u32(fd, 24, data->pd); |
|
3410 xprintf(fd, ", .eps_tag = "); |
|
3411 write_bits_u16(fd, 16, data->eps_tag); |
|
3412 xprintf(fd, "}"); |
|
3413 } /* end write_..._psif_qp_core(psif_qp_core data) */ |
|
3414 |
|
3415 void write_struct_psif_qp_path(XFILE *fd, |
|
3416 int network_order, |
|
3417 const struct psif_qp_path *data) |
|
3418 { |
|
3419 u64 swap[4]; |
|
3420 |
|
3421 if (network_order) { |
|
3422 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
3423 data = (struct psif_qp_path *)swap; |
|
3424 } |
|
3425 xprintf(fd, "{"); |
|
3426 xprintf(fd, " .remote_gid_0 = "); |
|
3427 write_bits_u64(fd, 64, data->remote_gid_0); |
|
3428 xprintf(fd, ", .remote_gid_1 = "); |
|
3429 write_bits_u64(fd, 64, data->remote_gid_1); |
|
3430 xprintf(fd, ", .remote_lid = "); |
|
3431 write_bits_u16(fd, 16, data->remote_lid); |
|
3432 xprintf(fd, ", .gid_indx = "); |
|
3433 write_bits_u8(fd, 1, data->gid_indx); |
|
3434 xprintf(fd, ", .port = "); |
|
3435 write_enum_psif_port(fd, data->port); |
|
3436 xprintf(fd, ", .loopback = "); |
|
3437 write_enum_psif_loopback(fd, data->loopback); |
|
3438 xprintf(fd, ", .use_grh = "); |
|
3439 write_enum_psif_use_grh(fd, data->use_grh); |
|
3440 xprintf(fd, ", .sl = "); |
|
3441 write_bits_u8(fd, 4, data->sl); |
|
3442 xprintf(fd, ", .hoplmt = "); |
|
3443 write_bits_u8(fd, 8, data->hoplmt); |
|
3444 xprintf(fd, ", .tclass = "); |
|
3445 write_bits_u8(fd, 8, data->tclass); |
|
3446 xprintf(fd, ", .flowlabel = "); |
|
3447 write_bits_u32(fd, 20, data->flowlabel); |
|
3448 xprintf(fd, ", .path_invalid = "); |
|
3449 write_bits_u8(fd, 1, data->path_invalid); |
|
3450 xprintf(fd, ", .local_ack_timeout = "); |
|
3451 write_bits_u8(fd, 5, data->local_ack_timeout); |
|
3452 xprintf(fd, ", .ipd = "); |
|
3453 write_bits_u8(fd, 8, data->ipd); |
|
3454 xprintf(fd, ", .local_lid_path = "); |
|
3455 write_bits_u8(fd, 7, data->local_lid_path); |
|
3456 xprintf(fd, ", .pkey_indx = "); |
|
3457 write_bits_u16(fd, 9, data->pkey_indx); |
|
3458 xprintf(fd, "}"); |
|
3459 } /* end write_..._psif_qp_path(psif_qp_path data) */ |
|
3460 |
|
3461 void write_struct_psif_query_qp(XFILE *fd, |
|
3462 int network_order, |
|
3463 const struct psif_query_qp *data) |
|
3464 { |
|
3465 u64 swap[24]; |
|
3466 |
|
3467 if (network_order) { |
|
3468 copy_convert_to_sw(swap, (volatile void *)data, 192); |
|
3469 data = (struct psif_query_qp *)swap; |
|
3470 } |
|
3471 xprintf(fd, "{"); |
|
3472 xprintf(fd, " .qp = "); |
|
3473 write_struct_psif_qp_core(fd, 0, &(data->qp)); |
|
3474 xprintf(fd, ", .primary_path = "); |
|
3475 write_struct_psif_qp_path(fd, 0, &(data->primary_path)); |
|
3476 xprintf(fd, ", .alternate_path = "); |
|
3477 write_struct_psif_qp_path(fd, 0, &(data->alternate_path)); |
|
3478 xprintf(fd, "}"); |
|
3479 } /* end write_..._psif_query_qp(psif_query_qp data) */ |
|
3480 |
|
3481 void write_struct_psif_qp(XFILE *fd, |
|
3482 int network_order, |
|
3483 const struct psif_qp *data) |
|
3484 { |
|
3485 u64 swap[24]; |
|
3486 |
|
3487 if (network_order) { |
|
3488 copy_convert_to_sw(swap, (volatile void *)data, 192); |
|
3489 data = (struct psif_qp *)swap; |
|
3490 } |
|
3491 xprintf(fd, "{"); |
|
3492 xprintf(fd, " .state = "); |
|
3493 write_struct_psif_qp_core(fd, 0, &(data->state)); |
|
3494 xprintf(fd, ", .path_a = "); |
|
3495 write_struct_psif_qp_path(fd, 0, &(data->path_a)); |
|
3496 xprintf(fd, ", .path_b = "); |
|
3497 write_struct_psif_qp_path(fd, 0, &(data->path_b)); |
|
3498 xprintf(fd, "}"); |
|
3499 } /* end write_..._psif_qp(psif_qp data) */ |
|
3500 |
|
3501 void write_struct_psif_cb(XFILE *fd, |
|
3502 int network_order, |
|
3503 const struct psif_cb *data) |
|
3504 { |
|
3505 u64 swap[40]; |
|
3506 |
|
3507 if (network_order) { |
|
3508 copy_convert_to_sw(swap, (volatile void *)data, 320); |
|
3509 data = (struct psif_cb *)swap; |
|
3510 } |
|
3511 xprintf(fd, "{"); |
|
3512 xprintf(fd, " .wr = "); |
|
3513 write_struct_psif_wr(fd, 0, &(data->wr)); |
|
3514 xprintf(fd, ", .payload = "); |
|
3515 { unsigned int i; for (i = 0; i < 32; i++) { |
|
3516 write_bits_u64(fd, 64, data->payload[i]); |
|
3517 xprintf(fd, ","); |
|
3518 } |
|
3519 } |
|
3520 xprintf(fd, "}"); |
|
3521 } /* end write_..._psif_cb(psif_cb data) */ |
|
3522 |
|
3523 void write_struct_psif_modify_qp(XFILE *fd, |
|
3524 int network_order, |
|
3525 const struct psif_modify_qp *data) |
|
3526 { |
|
3527 u64 swap[10]; |
|
3528 |
|
3529 if (network_order) { |
|
3530 copy_convert_to_sw(swap, (volatile void *)data, 80); |
|
3531 data = (struct psif_modify_qp *)swap; |
|
3532 } |
|
3533 xprintf(fd, "{"); |
|
3534 xprintf(fd, " .max_outstanding = "); |
|
3535 write_bits_u8(fd, 5, data->max_outstanding); |
|
3536 xprintf(fd, ", .state = "); |
|
3537 write_enum_psif_qp_state(fd, data->state); |
|
3538 xprintf(fd, ", .min_rnr_nak_time = "); |
|
3539 write_bits_u8(fd, 5, data->min_rnr_nak_time); |
|
3540 xprintf(fd, ", .error_retry_count = "); |
|
3541 write_bits_u8(fd, 3, data->error_retry_count); |
|
3542 xprintf(fd, ", .eoib_enable = "); |
|
3543 write_bits_u8(fd, 1, data->eoib_enable); |
|
3544 xprintf(fd, ", .ipoib_enable = "); |
|
3545 write_bits_u8(fd, 1, data->ipoib_enable); |
|
3546 xprintf(fd, ", .hdr_split_enable = "); |
|
3547 write_bits_u8(fd, 1, data->hdr_split_enable); |
|
3548 xprintf(fd, ", .rcv_dynamic_mtu_enable = "); |
|
3549 write_bits_u8(fd, 1, data->rcv_dynamic_mtu_enable); |
|
3550 xprintf(fd, ", .proxy_qp_enable = "); |
|
3551 write_bits_u8(fd, 1, data->proxy_qp_enable); |
|
3552 xprintf(fd, ", .rss_enable = "); |
|
3553 write_bits_u8(fd, 1, data->rss_enable); |
|
3554 xprintf(fd, ", .masked_atomic_enable = "); |
|
3555 write_bits_u8(fd, 1, data->masked_atomic_enable); |
|
3556 xprintf(fd, ", .atomic_enable = "); |
|
3557 write_bits_u8(fd, 1, data->atomic_enable); |
|
3558 xprintf(fd, ", .rdma_wr_enable = "); |
|
3559 write_bits_u8(fd, 1, data->rdma_wr_enable); |
|
3560 xprintf(fd, ", .rdma_rd_enable = "); |
|
3561 write_bits_u8(fd, 1, data->rdma_rd_enable); |
|
3562 xprintf(fd, ", .rnr_retry_count = "); |
|
3563 write_bits_u8(fd, 3, data->rnr_retry_count); |
|
3564 xprintf(fd, ", .req_access_error = "); |
|
3565 write_bits_u8(fd, 1, data->req_access_error); |
|
3566 xprintf(fd, ", .rx_qkey = "); |
|
3567 write_bits_u32(fd, 32, data->rx_qkey); |
|
3568 xprintf(fd, ", .xmit_psn = "); |
|
3569 write_bits_u32(fd, 24, data->xmit_psn); |
|
3570 xprintf(fd, ", .mstate = "); |
|
3571 write_enum_psif_migration(fd, data->mstate); |
|
3572 xprintf(fd, ", .path_mtu = "); |
|
3573 write_enum_psif_path_mtu(fd, data->path_mtu); |
|
3574 xprintf(fd, ", .expected_psn = "); |
|
3575 write_bits_u32(fd, 24, data->expected_psn); |
|
3576 xprintf(fd, ", .primary_path = "); |
|
3577 write_struct_psif_qp_path(fd, 0, &(data->primary_path)); |
|
3578 xprintf(fd, ", .alternate_path = "); |
|
3579 write_struct_psif_qp_path(fd, 0, &(data->alternate_path)); |
|
3580 xprintf(fd, "}"); |
|
3581 } /* end write_..._psif_modify_qp(psif_modify_qp data) */ |
|
3582 |
|
3583 void write_struct_psif_key(XFILE *fd, |
|
3584 int network_order, |
|
3585 const struct psif_key *data) |
|
3586 { |
|
3587 u64 swap[4]; |
|
3588 |
|
3589 if (network_order) { |
|
3590 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
3591 data = (struct psif_key *)swap; |
|
3592 } |
|
3593 xprintf(fd, "{"); |
|
3594 xprintf(fd, ", .zero_based_addr_en = "); |
|
3595 write_bits_u8(fd, 1, data->zero_based_addr_en); |
|
3596 xprintf(fd, ", .conditional_wr = "); |
|
3597 write_bits_u8(fd, 1, data->conditional_wr); |
|
3598 xprintf(fd, ", .local_access_atomic = "); |
|
3599 write_bits_u8(fd, 1, data->local_access_atomic); |
|
3600 xprintf(fd, ", .local_access_wr = "); |
|
3601 write_bits_u8(fd, 1, data->local_access_wr); |
|
3602 xprintf(fd, ", .local_access_rd = "); |
|
3603 write_bits_u8(fd, 1, data->local_access_rd); |
|
3604 xprintf(fd, ", .remote_access_atomic = "); |
|
3605 write_bits_u8(fd, 1, data->remote_access_atomic); |
|
3606 xprintf(fd, ", .remote_access_wr = "); |
|
3607 write_bits_u8(fd, 1, data->remote_access_wr); |
|
3608 xprintf(fd, ", .remote_access_rd = "); |
|
3609 write_bits_u8(fd, 1, data->remote_access_rd); |
|
3610 xprintf(fd, ", .pd = "); |
|
3611 write_bits_u32(fd, 24, data->pd); |
|
3612 xprintf(fd, ", .lkey_state = "); |
|
3613 write_enum_psif_dma_vt_key_states(fd, data->lkey_state); |
|
3614 xprintf(fd, ", .rkey_state = "); |
|
3615 write_enum_psif_dma_vt_key_states(fd, data->rkey_state); |
|
3616 xprintf(fd, ", .length = "); |
|
3617 write_bits_u64(fd, 64, data->length); |
|
3618 xprintf(fd, ", .mmu_context = "); |
|
3619 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_context)); |
|
3620 xprintf(fd, ", .base_addr = "); |
|
3621 write_bits_u64(fd, 64, data->base_addr); |
|
3622 xprintf(fd, "}"); |
|
3623 } /* end write_..._psif_key(psif_key data) */ |
|
3624 |
|
3625 void write_struct_psif_flash_header_app(XFILE *fd, |
|
3626 int network_order, |
|
3627 const struct psif_flash_header_app *data) |
|
3628 { |
|
3629 u64 swap[12]; |
|
3630 |
|
3631 if (network_order) { |
|
3632 copy_convert_to_sw(swap, (volatile void *)data, 96); |
|
3633 data = (struct psif_flash_header_app *)swap; |
|
3634 } |
|
3635 xprintf(fd, "{"); |
|
3636 xprintf(fd, " .signature = "); |
|
3637 write_bits_u32(fd, 32, data->signature); |
|
3638 xprintf(fd, ", .type = "); |
|
3639 write_enum_psif_flash_image_type(fd, data->type); |
|
3640 xprintf(fd, ", .exec_base = "); |
|
3641 write_bits_u32(fd, 32, data->exec_base); |
|
3642 xprintf(fd, ", .image_length = "); |
|
3643 write_bits_u32(fd, 32, data->image_length); |
|
3644 xprintf(fd, ", .zi_base = "); |
|
3645 write_bits_u32(fd, 32, data->zi_base); |
|
3646 xprintf(fd, ", .zi_length = "); |
|
3647 write_bits_u32(fd, 32, data->zi_length); |
|
3648 xprintf(fd, ", .flash_base = "); |
|
3649 write_bits_u32(fd, 32, data->flash_base); |
|
3650 xprintf(fd, ", .start_addr = "); |
|
3651 write_bits_u32(fd, 32, data->start_addr); |
|
3652 xprintf(fd, ", .low_vec_base = "); |
|
3653 write_bits_u32(fd, 32, data->low_vec_base); |
|
3654 xprintf(fd, ", .low_vec_flash_base = "); |
|
3655 write_bits_u32(fd, 32, data->low_vec_flash_base); |
|
3656 xprintf(fd, ", .low_vec_length = "); |
|
3657 write_bits_u32(fd, 32, data->low_vec_length); |
|
3658 xprintf(fd, ", .date = "); |
|
3659 { unsigned int i; for (i = 0; i < 4; i++) { |
|
3660 write_bits_u8(fd, 8, data->date[i]); |
|
3661 xprintf(fd, ","); |
|
3662 } |
|
3663 } |
|
3664 xprintf(fd, ", .date_1 = "); |
|
3665 { unsigned int i; for (i = 0; i < 8; i++) { |
|
3666 write_bits_u8(fd, 8, data->date_1[i]); |
|
3667 xprintf(fd, ","); |
|
3668 } |
|
3669 } |
|
3670 xprintf(fd, ", .date_2 = "); |
|
3671 { unsigned int i; for (i = 0; i < 4; i++) { |
|
3672 write_bits_u8(fd, 8, data->date_2[i]); |
|
3673 xprintf(fd, ","); |
|
3674 } |
|
3675 } |
|
3676 xprintf(fd, ", .time = "); |
|
3677 { unsigned int i; for (i = 0; i < 4; i++) { |
|
3678 write_bits_u8(fd, 8, data->time[i]); |
|
3679 xprintf(fd, ","); |
|
3680 } |
|
3681 } |
|
3682 xprintf(fd, ", .time_1 = "); |
|
3683 { unsigned int i; for (i = 0; i < 8; i++) { |
|
3684 write_bits_u8(fd, 8, data->time_1[i]); |
|
3685 xprintf(fd, ","); |
|
3686 } |
|
3687 } |
|
3688 xprintf(fd, ", .rev_string = "); |
|
3689 { unsigned int i; for (i = 0; i < 8; i++) { |
|
3690 write_bits_u8(fd, 8, data->rev_string[i]); |
|
3691 xprintf(fd, ","); |
|
3692 } |
|
3693 } |
|
3694 xprintf(fd, ", .checksum_ptr = "); |
|
3695 write_bits_u32(fd, 32, data->checksum_ptr); |
|
3696 xprintf(fd, ", .app_vec_flash_base = "); |
|
3697 write_bits_u32(fd, 32, data->app_vec_flash_base); |
|
3698 xprintf(fd, ", .app_vec_base = "); |
|
3699 write_bits_u32(fd, 32, data->app_vec_base); |
|
3700 xprintf(fd, ", .app_vec_length = "); |
|
3701 write_bits_u32(fd, 32, data->app_vec_length); |
|
3702 xprintf(fd, "}"); |
|
3703 } /* end write_..._psif_flash_header_app(psif_flash_header_app data) */ |
|
3704 |
|
3705 void write_struct_psif_flash_header_all(XFILE *fd, |
|
3706 int network_order, |
|
3707 const struct psif_flash_header_all *data) |
|
3708 { |
|
3709 u64 swap[2]; |
|
3710 |
|
3711 if (network_order) { |
|
3712 copy_convert_to_sw(swap, (volatile void *)data, 16); |
|
3713 data = (struct psif_flash_header_all *)swap; |
|
3714 } |
|
3715 xprintf(fd, "{"); |
|
3716 xprintf(fd, " .signature = "); |
|
3717 write_bits_u32(fd, 32, data->signature); |
|
3718 xprintf(fd, ", .type = "); |
|
3719 write_enum_psif_flash_image_type(fd, data->type); |
|
3720 xprintf(fd, ", .base = "); |
|
3721 write_bits_u32(fd, 32, data->base); |
|
3722 xprintf(fd, ", .length = "); |
|
3723 write_bits_u32(fd, 32, data->length); |
|
3724 xprintf(fd, "}"); |
|
3725 } /* end write_..._psif_flash_header_all(psif_flash_header_all data) */ |
|
3726 |
|
3727 void write_struct_psif_eq_entry(XFILE *fd, |
|
3728 int network_order, |
|
3729 const struct psif_eq_entry *data) |
|
3730 { |
|
3731 u64 swap[8]; |
|
3732 |
|
3733 if (network_order) { |
|
3734 copy_convert_to_sw(swap, (volatile void *)data, 64); |
|
3735 data = (struct psif_eq_entry *)swap; |
|
3736 } |
|
3737 xprintf(fd, "{"); |
|
3738 xprintf(fd, " .eps_core_id = "); |
|
3739 write_enum_psif_eps_core_id(fd, data->eps_core_id); |
|
3740 xprintf(fd, ", .vendor_fields = "); |
|
3741 write_bits_u8(fd, 3, data->vendor_fields); |
|
3742 xprintf(fd, ", .port = "); |
|
3743 write_enum_psif_port(fd, data->port); |
|
3744 xprintf(fd, ", .cqd_id = "); |
|
3745 write_bits_u32(fd, 24, data->cqd_id); |
|
3746 xprintf(fd, ", .vendor_error = "); |
|
3747 write_enum_psif_tsu_error_types(fd, data->vendor_error); |
|
3748 xprintf(fd, ", .port_flags = "); |
|
3749 write_bits_u8(fd, 4, data->port_flags); |
|
3750 xprintf(fd, ", .event_status_eps_a = "); |
|
3751 write_bits_u8(fd, 1, data->event_status_eps_a); |
|
3752 xprintf(fd, ", .event_status_eps_c = "); |
|
3753 write_bits_u8(fd, 1, data->event_status_eps_c); |
|
3754 xprintf(fd, ", .event_status_cmpl_notify = "); |
|
3755 write_bits_u8(fd, 1, data->event_status_cmpl_notify); |
|
3756 xprintf(fd, ", .event_status_port_error = "); |
|
3757 write_bits_u8(fd, 1, data->event_status_port_error); |
|
3758 xprintf(fd, ", .event_status_local_catastrophic_error = "); |
|
3759 write_bits_u8(fd, 1, data->event_status_local_catastrophic_error); |
|
3760 xprintf(fd, ", .event_status_port_changed = "); |
|
3761 write_bits_u8(fd, 1, data->event_status_port_changed); |
|
3762 xprintf(fd, ", .event_status_client_registration = "); |
|
3763 write_bits_u8(fd, 1, data->event_status_client_registration); |
|
3764 xprintf(fd, ", .event_status_port_active = "); |
|
3765 write_bits_u8(fd, 1, data->event_status_port_active); |
|
3766 xprintf(fd, ", .event_status_local_work_queue_catastrophic_error = "); |
|
3767 write_bits_u8(fd, 1, data->event_status_local_work_queue_catastrophic_error); |
|
3768 xprintf(fd, ", .event_status_srq_catastrophic_error = "); |
|
3769 write_bits_u8(fd, 1, data->event_status_srq_catastrophic_error); |
|
3770 xprintf(fd, ", .event_status_invalid_xrceth = "); |
|
3771 write_bits_u8(fd, 1, data->event_status_invalid_xrceth); |
|
3772 xprintf(fd, ", .event_status_xrc_domain_violation = "); |
|
3773 write_bits_u8(fd, 1, data->event_status_xrc_domain_violation); |
|
3774 xprintf(fd, ", .event_status_path_migration_request_error = "); |
|
3775 write_bits_u8(fd, 1, data->event_status_path_migration_request_error); |
|
3776 xprintf(fd, ", .event_status_local_access_violation_wq_error = "); |
|
3777 write_bits_u8(fd, 1, data->event_status_local_access_violation_wq_error); |
|
3778 xprintf(fd, ", .event_status_invalid_request_local_wq_error = "); |
|
3779 write_bits_u8(fd, 1, data->event_status_invalid_request_local_wq_error); |
|
3780 xprintf(fd, ", .event_status_cq_error = "); |
|
3781 write_bits_u8(fd, 1, data->event_status_cq_error); |
|
3782 xprintf(fd, ", .event_status_last_wqe_reached = "); |
|
3783 write_bits_u8(fd, 1, data->event_status_last_wqe_reached); |
|
3784 xprintf(fd, ", .event_status_srq_limit_reached = "); |
|
3785 write_bits_u8(fd, 1, data->event_status_srq_limit_reached); |
|
3786 xprintf(fd, ", .event_status_communication_established = "); |
|
3787 write_bits_u8(fd, 1, data->event_status_communication_established); |
|
3788 xprintf(fd, ", .event_status_path_migrated = "); |
|
3789 write_bits_u8(fd, 1, data->event_status_path_migrated); |
|
3790 xprintf(fd, ", .lid = "); |
|
3791 write_bits_u16(fd, 16, data->lid); |
|
3792 xprintf(fd, ", .qp = "); |
|
3793 write_bits_u32(fd, 24, data->qp); |
|
3794 xprintf(fd, ", .rqd_id = "); |
|
3795 write_bits_u32(fd, 24, data->rqd_id); |
|
3796 xprintf(fd, ", .extension_type = "); |
|
3797 write_enum_psif_event(fd, data->extension_type); |
|
3798 xprintf(fd, ", .cq_sequence_number = "); |
|
3799 write_bits_u32(fd, 32, data->cq_sequence_number); |
|
3800 xprintf(fd, ", .event_info = "); |
|
3801 write_bits_u64(fd, 64, data->event_info); |
|
3802 xprintf(fd, ", .event_data = "); |
|
3803 write_bits_u64(fd, 64, data->event_data); |
|
3804 xprintf(fd, ", .seq_num = "); |
|
3805 write_bits_u32(fd, 32, data->seq_num); |
|
3806 xprintf(fd, "}"); |
|
3807 } /* end write_..._psif_eq_entry(psif_eq_entry data) */ |
|
3808 |
|
3809 void write_struct_psif_epsc_exercise_mmu(XFILE *fd, |
|
3810 int network_order, |
|
3811 const struct psif_epsc_exercise_mmu *data) |
|
3812 { |
|
3813 u64 swap[11]; |
|
3814 |
|
3815 if (network_order) { |
|
3816 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
3817 data = (struct psif_epsc_exercise_mmu *)swap; |
|
3818 } |
|
3819 xprintf(fd, "{"); |
|
3820 xprintf(fd, " .host_addr = "); |
|
3821 write_bits_u64(fd, 64, data->host_addr); |
|
3822 xprintf(fd, ", .mmu_cntx = "); |
|
3823 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
3824 xprintf(fd, ", .length = "); |
|
3825 write_bits_u64(fd, 64, data->length); |
|
3826 xprintf(fd, ", .stride = "); |
|
3827 write_bits_u64(fd, 64, data->stride); |
|
3828 xprintf(fd, "}"); |
|
3829 } /* end write_..._psif_epsc_exercise_mmu(psif_epsc_exercise_mmu data) */ |
|
3830 |
|
3831 void write_struct_psif_epsc_csr_rsp(XFILE *fd, |
|
3832 int network_order, |
|
3833 const struct psif_epsc_csr_rsp *data) |
|
3834 { |
|
3835 u64 swap[4]; |
|
3836 |
|
3837 if (network_order) { |
|
3838 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
3839 data = (struct psif_epsc_csr_rsp *)swap; |
|
3840 } |
|
3841 xprintf(fd, "{"); |
|
3842 xprintf(fd, " .addr = "); |
|
3843 write_bits_u32(fd, 32, data->addr); |
|
3844 xprintf(fd, ", .crc = "); |
|
3845 write_bits_u16(fd, 16, data->crc); |
|
3846 xprintf(fd, ", .opcode = "); |
|
3847 write_enum_psif_epsc_csr_opcode(fd, data->opcode); |
|
3848 xprintf(fd, ", .status = "); |
|
3849 write_enum_psif_epsc_csr_status(fd, data->status); |
|
3850 xprintf(fd, ", .data = "); |
|
3851 write_bits_u64(fd, 64, data->data); |
|
3852 xprintf(fd, ", .info = "); |
|
3853 write_bits_u64(fd, 64, data->info); |
|
3854 xprintf(fd, ", .seq_num = "); |
|
3855 write_bits_u64(fd, 64, data->seq_num); |
|
3856 xprintf(fd, "}"); |
|
3857 } /* end write_..._psif_epsc_csr_rsp(psif_epsc_csr_rsp data) */ |
|
3858 |
|
3859 void write_struct_psif_epsc_csr_opaque(XFILE *fd, |
|
3860 int network_order, |
|
3861 const struct psif_epsc_csr_opaque *data) |
|
3862 { |
|
3863 u64 swap[11]; |
|
3864 |
|
3865 if (network_order) { |
|
3866 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
3867 data = (struct psif_epsc_csr_opaque *)swap; |
|
3868 } |
|
3869 xprintf(fd, "{"); |
|
3870 xprintf(fd, " .data = "); |
|
3871 { unsigned int i; for (i = 0; i < 11; i++) { |
|
3872 write_bits_u64(fd, 64, data->data[i]); |
|
3873 xprintf(fd, ","); |
|
3874 } |
|
3875 } |
|
3876 xprintf(fd, "}"); |
|
3877 } /* end write_..._psif_epsc_csr_opaque(psif_epsc_csr_opaque data) */ |
|
3878 |
|
3879 void write_struct_psif_epsc_csr_single(XFILE *fd, |
|
3880 int network_order, |
|
3881 const struct psif_epsc_csr_single *data) |
|
3882 { |
|
3883 u64 swap[11]; |
|
3884 |
|
3885 if (network_order) { |
|
3886 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
3887 data = (struct psif_epsc_csr_single *)swap; |
|
3888 } |
|
3889 xprintf(fd, "{"); |
|
3890 xprintf(fd, " .data = "); |
|
3891 write_bits_u64(fd, 64, data->data); |
|
3892 xprintf(fd, "}"); |
|
3893 } /* end write_..._psif_epsc_csr_single(psif_epsc_csr_single data) */ |
|
3894 |
|
3895 void write_struct_psif_epsc_csr_base_addr(XFILE *fd, |
|
3896 int network_order, |
|
3897 const struct psif_epsc_csr_base_addr *data) |
|
3898 { |
|
3899 u64 swap[11]; |
|
3900 |
|
3901 if (network_order) { |
|
3902 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
3903 data = (struct psif_epsc_csr_base_addr *)swap; |
|
3904 } |
|
3905 xprintf(fd, "{"); |
|
3906 xprintf(fd, " .address = "); |
|
3907 write_bits_u64(fd, 64, data->address); |
|
3908 xprintf(fd, ", .mmu_context = "); |
|
3909 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_context)); |
|
3910 xprintf(fd, ", .extent_log2 = "); |
|
3911 write_bits_u8(fd, 5, data->extent_log2); |
|
3912 xprintf(fd, ", .num_entries = "); |
|
3913 write_bits_u32(fd, 32, data->num_entries); |
|
3914 xprintf(fd, ", .msix_index = "); |
|
3915 write_bits_u32(fd, 32, data->msix_index); |
|
3916 xprintf(fd, ", .padding = "); |
|
3917 { unsigned int i; for (i = 0; i < 7; i++) { |
|
3918 write_bits_u64(fd, 64, data->padding[i]); |
|
3919 xprintf(fd, ","); |
|
3920 } |
|
3921 } |
|
3922 xprintf(fd, "}"); |
|
3923 } /* end write_..._psif_epsc_csr_base_addr(psif_epsc_csr_base_addr data) */ |
|
3924 |
|
3925 void write_struct_psif_csr_modify_qp_ctrl(XFILE *fd, |
|
3926 int network_order, |
|
3927 const struct psif_csr_modify_qp_ctrl *data) |
|
3928 { |
|
3929 u64 swap[1]; |
|
3930 |
|
3931 if (network_order) { |
|
3932 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
3933 data = (struct psif_csr_modify_qp_ctrl *)swap; |
|
3934 } |
|
3935 xprintf(fd, "{"); |
|
3936 xprintf(fd, " .use_current_state = "); |
|
3937 write_bits_u8(fd, 1, data->use_current_state); |
|
3938 xprintf(fd, ", .max_outstanding = "); |
|
3939 write_bits_u8(fd, 1, data->max_outstanding); |
|
3940 xprintf(fd, ", .xmit_psn = "); |
|
3941 write_bits_u8(fd, 1, data->xmit_psn); |
|
3942 xprintf(fd, ", .rnr_retry_count = "); |
|
3943 write_bits_u8(fd, 1, data->rnr_retry_count); |
|
3944 xprintf(fd, ", .error_retry_count = "); |
|
3945 write_bits_u8(fd, 1, data->error_retry_count); |
|
3946 xprintf(fd, ", .min_rnr_nak_time = "); |
|
3947 write_bits_u8(fd, 1, data->min_rnr_nak_time); |
|
3948 xprintf(fd, ", .local_ack_timeout = "); |
|
3949 write_bits_u8(fd, 1, data->local_ack_timeout); |
|
3950 xprintf(fd, ", .pkey_index = "); |
|
3951 write_bits_u8(fd, 1, data->pkey_index); |
|
3952 xprintf(fd, ", .qkey = "); |
|
3953 write_bits_u8(fd, 1, data->qkey); |
|
3954 xprintf(fd, ", .qp_rcv_cap = "); |
|
3955 write_bits_u8(fd, 1, data->qp_rcv_cap); |
|
3956 xprintf(fd, ", .qp_state = "); |
|
3957 write_bits_u8(fd, 1, data->qp_state); |
|
3958 xprintf(fd, ", .alt_path = "); |
|
3959 write_bits_u8(fd, 1, data->alt_path); |
|
3960 xprintf(fd, ", .mig_state = "); |
|
3961 write_bits_u8(fd, 1, data->mig_state); |
|
3962 xprintf(fd, ", .prim_path = "); |
|
3963 write_bits_u8(fd, 1, data->prim_path); |
|
3964 xprintf(fd, ", .expected_psn = "); |
|
3965 write_bits_u8(fd, 1, data->expected_psn); |
|
3966 xprintf(fd, ", .path_mtu = "); |
|
3967 write_bits_u8(fd, 1, data->path_mtu); |
|
3968 xprintf(fd, ", .req_access_error = "); |
|
3969 write_bits_u8(fd, 1, data->req_access_error); |
|
3970 xprintf(fd, ", .notify_when_zero = "); |
|
3971 write_bits_u8(fd, 1, data->notify_when_zero); |
|
3972 xprintf(fd, ", .qp_num = "); |
|
3973 write_bits_u32(fd, 24, data->qp_num); |
|
3974 xprintf(fd, ", .current_state = "); |
|
3975 write_enum_psif_qp_state(fd, data->current_state); |
|
3976 xprintf(fd, ", .port_num = "); |
|
3977 write_enum_psif_port(fd, data->port_num); |
|
3978 xprintf(fd, ", .uf = "); |
|
3979 write_bits_u8(fd, 6, data->uf); |
|
3980 xprintf(fd, ", .cmd = "); |
|
3981 write_enum_psif_qp_command(fd, data->cmd); |
|
3982 xprintf(fd, "}"); |
|
3983 } /* end write_..._psif_csr_modify_qp_ctrl(psif_csr_modify_qp_ctrl data) */ |
|
3984 |
|
3985 void write_struct_psif_epsc_csr_modify_qp(XFILE *fd, |
|
3986 int network_order, |
|
3987 const struct psif_epsc_csr_modify_qp *data) |
|
3988 { |
|
3989 u64 swap[11]; |
|
3990 |
|
3991 if (network_order) { |
|
3992 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
3993 data = (struct psif_epsc_csr_modify_qp *)swap; |
|
3994 } |
|
3995 xprintf(fd, "{"); |
|
3996 xprintf(fd, " .ctrl = "); |
|
3997 write_struct_psif_csr_modify_qp_ctrl(fd, 0, &(data->ctrl)); |
|
3998 xprintf(fd, ", .data = "); |
|
3999 write_struct_psif_modify_qp(fd, 0, &(data->data)); |
|
4000 xprintf(fd, "}"); |
|
4001 } /* end write_..._psif_epsc_csr_modify_qp(psif_epsc_csr_modify_qp data) */ |
|
4002 |
|
4003 void write_struct_psif_epsc_csr_query_qp(XFILE *fd, |
|
4004 int network_order, |
|
4005 const struct psif_epsc_csr_query_qp *data) |
|
4006 { |
|
4007 u64 swap[11]; |
|
4008 |
|
4009 if (network_order) { |
|
4010 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4011 data = (struct psif_epsc_csr_query_qp *)swap; |
|
4012 } |
|
4013 xprintf(fd, "{"); |
|
4014 xprintf(fd, " .address = "); |
|
4015 write_bits_u64(fd, 64, data->address); |
|
4016 xprintf(fd, ", .ctrl = "); |
|
4017 write_struct_psif_csr_modify_qp_ctrl(fd, 0, &(data->ctrl)); |
|
4018 xprintf(fd, ", .mmu_cntx = "); |
|
4019 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4020 xprintf(fd, ", .padding = "); |
|
4021 { unsigned int i; for (i = 0; i < 8; i++) { |
|
4022 write_bits_u64(fd, 64, data->padding[i]); |
|
4023 xprintf(fd, ","); |
|
4024 } |
|
4025 } |
|
4026 xprintf(fd, "}"); |
|
4027 } /* end write_..._psif_epsc_csr_query_qp(psif_epsc_csr_query_qp data) */ |
|
4028 |
|
4029 void write_struct_psif_csr_own_lid_base(XFILE *fd, |
|
4030 int network_order, |
|
4031 const struct psif_csr_own_lid_base *data) |
|
4032 { |
|
4033 u64 swap[1]; |
|
4034 |
|
4035 if (network_order) { |
|
4036 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
4037 data = (struct psif_csr_own_lid_base *)swap; |
|
4038 } |
|
4039 xprintf(fd, "{"); |
|
4040 xprintf(fd, " .gid_flag = "); |
|
4041 write_bits_u8(fd, 1, data->gid_flag); |
|
4042 xprintf(fd, ", .lmc = "); |
|
4043 write_bits_u8(fd, 3, data->lmc); |
|
4044 xprintf(fd, ", .lid_base = "); |
|
4045 write_bits_u16(fd, 16, data->lid_base); |
|
4046 xprintf(fd, "}"); |
|
4047 } /* end write_..._psif_csr_own_lid_base(psif_csr_own_lid_base data) */ |
|
4048 |
|
4049 void write_struct_psif_csr_snd_lid(XFILE *fd, |
|
4050 int network_order, |
|
4051 const struct psif_csr_snd_lid *data) |
|
4052 { |
|
4053 u64 swap[1]; |
|
4054 |
|
4055 if (network_order) { |
|
4056 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
4057 data = (struct psif_csr_snd_lid *)swap; |
|
4058 } |
|
4059 xprintf(fd, "{"); |
|
4060 xprintf(fd, " .lmc = "); |
|
4061 write_bits_u8(fd, 3, data->lmc); |
|
4062 xprintf(fd, ", .lid_base = "); |
|
4063 write_bits_u16(fd, 16, data->lid_base); |
|
4064 xprintf(fd, "}"); |
|
4065 } /* end write_..._psif_csr_snd_lid(psif_csr_snd_lid data) */ |
|
4066 |
|
4067 void write_struct_psif_csr_rcv_lid(XFILE *fd, |
|
4068 int network_order, |
|
4069 const struct psif_csr_rcv_lid *data) |
|
4070 { |
|
4071 u64 swap[1]; |
|
4072 |
|
4073 if (network_order) { |
|
4074 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
4075 data = (struct psif_csr_rcv_lid *)swap; |
|
4076 } |
|
4077 xprintf(fd, "{"); |
|
4078 xprintf(fd, " .gid_flag = "); |
|
4079 write_bits_u8(fd, 1, data->gid_flag); |
|
4080 xprintf(fd, ", .lmc = "); |
|
4081 write_bits_u8(fd, 3, data->lmc); |
|
4082 xprintf(fd, ", .lid_base = "); |
|
4083 write_bits_u16(fd, 16, data->lid_base); |
|
4084 xprintf(fd, "}"); |
|
4085 } /* end write_..._psif_csr_rcv_lid(psif_csr_rcv_lid data) */ |
|
4086 |
|
4087 void write_struct_psif_epsc_csr_set_lid(XFILE *fd, |
|
4088 int network_order, |
|
4089 const struct psif_epsc_csr_set_lid *data) |
|
4090 { |
|
4091 u64 swap[11]; |
|
4092 |
|
4093 if (network_order) { |
|
4094 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4095 data = (struct psif_epsc_csr_set_lid *)swap; |
|
4096 } |
|
4097 xprintf(fd, "{"); |
|
4098 xprintf(fd, " .lid_rqs = "); |
|
4099 write_struct_psif_csr_own_lid_base(fd, 0, &(data->lid_rqs)); |
|
4100 xprintf(fd, ", .lid_snd = "); |
|
4101 write_struct_psif_csr_snd_lid(fd, 0, &(data->lid_snd)); |
|
4102 xprintf(fd, ", .lid_rcv = "); |
|
4103 write_struct_psif_csr_rcv_lid(fd, 0, &(data->lid_rcv)); |
|
4104 xprintf(fd, ", .index = "); |
|
4105 write_bits_u8(fd, 8, data->index); |
|
4106 xprintf(fd, ", .port = "); |
|
4107 write_bits_u8(fd, 8, data->port); |
|
4108 xprintf(fd, ", .padding = "); |
|
4109 { unsigned int i; for (i = 0; i < 7; i++) { |
|
4110 write_bits_u64(fd, 64, data->padding[i]); |
|
4111 xprintf(fd, ","); |
|
4112 } |
|
4113 } |
|
4114 xprintf(fd, "}"); |
|
4115 } /* end write_..._psif_epsc_csr_set_lid(psif_epsc_csr_set_lid data) */ |
|
4116 |
|
4117 void write_struct_psif_epsc_csr_set_gid(XFILE *fd, |
|
4118 int network_order, |
|
4119 const struct psif_epsc_csr_set_gid *data) |
|
4120 { |
|
4121 u64 swap[11]; |
|
4122 |
|
4123 if (network_order) { |
|
4124 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4125 data = (struct psif_epsc_csr_set_gid *)swap; |
|
4126 } |
|
4127 xprintf(fd, "{"); |
|
4128 xprintf(fd, " .gid_0 = "); |
|
4129 write_bits_u64(fd, 64, data->gid_0); |
|
4130 xprintf(fd, ", .gid_1 = "); |
|
4131 write_bits_u64(fd, 64, data->gid_1); |
|
4132 xprintf(fd, ", .index = "); |
|
4133 write_bits_u8(fd, 8, data->index); |
|
4134 xprintf(fd, ", .port = "); |
|
4135 write_bits_u8(fd, 8, data->port); |
|
4136 xprintf(fd, ", .padding = "); |
|
4137 { unsigned int i; for (i = 0; i < 8; i++) { |
|
4138 write_bits_u64(fd, 64, data->padding[i]); |
|
4139 xprintf(fd, ","); |
|
4140 } |
|
4141 } |
|
4142 xprintf(fd, "}"); |
|
4143 } /* end write_..._psif_epsc_csr_set_gid(psif_epsc_csr_set_gid data) */ |
|
4144 |
|
4145 void write_struct_psif_epsc_csr_set_eoib_mac(XFILE *fd, |
|
4146 int network_order, |
|
4147 const struct psif_epsc_csr_set_eoib_mac *data) |
|
4148 { |
|
4149 u64 swap[11]; |
|
4150 |
|
4151 if (network_order) { |
|
4152 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4153 data = (struct psif_epsc_csr_set_eoib_mac *)swap; |
|
4154 } |
|
4155 xprintf(fd, "{"); |
|
4156 xprintf(fd, " .mac = "); |
|
4157 write_bits_u64(fd, 64, data->mac); |
|
4158 xprintf(fd, ", .index = "); |
|
4159 write_bits_u8(fd, 8, data->index); |
|
4160 xprintf(fd, ", .port = "); |
|
4161 write_bits_u8(fd, 8, data->port); |
|
4162 xprintf(fd, ", .padding = "); |
|
4163 { unsigned int i; for (i = 0; i < 9; i++) { |
|
4164 write_bits_u64(fd, 64, data->padding[i]); |
|
4165 xprintf(fd, ","); |
|
4166 } |
|
4167 } |
|
4168 xprintf(fd, "}"); |
|
4169 } /* end write_..._psif_epsc_csr_set_eoib_mac(psif_epsc_csr_set_eoib_mac data) */ |
|
4170 |
|
4171 void write_struct_psif_epsc_csr_vlink_state(XFILE *fd, |
|
4172 int network_order, |
|
4173 const struct psif_epsc_csr_vlink_state *data) |
|
4174 { |
|
4175 u64 swap[11]; |
|
4176 |
|
4177 if (network_order) { |
|
4178 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4179 data = (struct psif_epsc_csr_vlink_state *)swap; |
|
4180 } |
|
4181 xprintf(fd, "{"); |
|
4182 xprintf(fd, ", .vlink_state = "); |
|
4183 write_enum_psif_vlink_state(fd, data->vlink_state); |
|
4184 xprintf(fd, ", .port = "); |
|
4185 write_enum_psif_port(fd, data->port); |
|
4186 xprintf(fd, ", .uf = "); |
|
4187 write_bits_u8(fd, 6, data->uf); |
|
4188 xprintf(fd, ", .padding = "); |
|
4189 { unsigned int i; for (i = 0; i < 10; i++) { |
|
4190 write_bits_u64(fd, 64, data->padding[i]); |
|
4191 xprintf(fd, ","); |
|
4192 } |
|
4193 } |
|
4194 xprintf(fd, "}"); |
|
4195 } /* end write_..._psif_epsc_csr_vlink_state(psif_epsc_csr_vlink_state data) */ |
|
4196 |
|
4197 void write_struct_psif_epsc_csr_query_hw(XFILE *fd, |
|
4198 int network_order, |
|
4199 const struct psif_epsc_csr_query_hw *data) |
|
4200 { |
|
4201 u64 swap[11]; |
|
4202 |
|
4203 if (network_order) { |
|
4204 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4205 data = (struct psif_epsc_csr_query_hw *)swap; |
|
4206 } |
|
4207 xprintf(fd, "{"); |
|
4208 xprintf(fd, " .address = "); |
|
4209 write_bits_u64(fd, 64, data->address); |
|
4210 xprintf(fd, ", .mmu_cntx = "); |
|
4211 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4212 xprintf(fd, ", .padding = "); |
|
4213 { unsigned int i; for (i = 0; i < 9; i++) { |
|
4214 write_bits_u64(fd, 64, data->padding[i]); |
|
4215 xprintf(fd, ","); |
|
4216 } |
|
4217 } |
|
4218 xprintf(fd, "}"); |
|
4219 } /* end write_..._psif_epsc_csr_query_hw(psif_epsc_csr_query_hw data) */ |
|
4220 |
|
4221 void write_struct_psif_epsc_csr_query_table(XFILE *fd, |
|
4222 int network_order, |
|
4223 const struct psif_epsc_csr_query_table *data) |
|
4224 { |
|
4225 u64 swap[11]; |
|
4226 |
|
4227 if (network_order) { |
|
4228 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4229 data = (struct psif_epsc_csr_query_table *)swap; |
|
4230 } |
|
4231 xprintf(fd, "{"); |
|
4232 xprintf(fd, ", .index = "); |
|
4233 write_bits_u16(fd, 16, data->index); |
|
4234 xprintf(fd, ", .port = "); |
|
4235 write_bits_u8(fd, 8, data->port); |
|
4236 xprintf(fd, ", .padding = "); |
|
4237 { unsigned int i; for (i = 0; i < 10; i++) { |
|
4238 write_bits_u64(fd, 64, data->padding[i]); |
|
4239 xprintf(fd, ","); |
|
4240 } |
|
4241 } |
|
4242 xprintf(fd, "}"); |
|
4243 } /* end write_..._psif_epsc_csr_query_table(psif_epsc_csr_query_table data) */ |
|
4244 |
|
4245 void write_struct_psif_epsc_csr_mc(XFILE *fd, |
|
4246 int network_order, |
|
4247 const struct psif_epsc_csr_mc *data) |
|
4248 { |
|
4249 u64 swap[11]; |
|
4250 |
|
4251 if (network_order) { |
|
4252 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4253 data = (struct psif_epsc_csr_mc *)swap; |
|
4254 } |
|
4255 xprintf(fd, "{"); |
|
4256 xprintf(fd, ", .qp = "); |
|
4257 write_bits_u32(fd, 24, data->qp); |
|
4258 xprintf(fd, ", .port = "); |
|
4259 write_bits_u8(fd, 8, data->port); |
|
4260 xprintf(fd, ", .mgid_0 = "); |
|
4261 write_bits_u64(fd, 64, data->mgid_0); |
|
4262 xprintf(fd, ", .mgid_1 = "); |
|
4263 write_bits_u64(fd, 64, data->mgid_1); |
|
4264 xprintf(fd, ", .padding = "); |
|
4265 { unsigned int i; for (i = 0; i < 8; i++) { |
|
4266 write_bits_u64(fd, 64, data->padding[i]); |
|
4267 xprintf(fd, ","); |
|
4268 } |
|
4269 } |
|
4270 xprintf(fd, "}"); |
|
4271 } /* end write_..._psif_epsc_csr_mc(psif_epsc_csr_mc data) */ |
|
4272 |
|
4273 void write_struct_psif_epsc_csr_event(XFILE *fd, |
|
4274 int network_order, |
|
4275 const struct psif_epsc_csr_event *data) |
|
4276 { |
|
4277 u64 swap[11]; |
|
4278 |
|
4279 if (network_order) { |
|
4280 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4281 data = (struct psif_epsc_csr_event *)swap; |
|
4282 } |
|
4283 xprintf(fd, "{"); |
|
4284 xprintf(fd, " .eq_index = "); |
|
4285 write_bits_u32(fd, 32, data->eq_index); |
|
4286 xprintf(fd, ", .eq_num = "); |
|
4287 write_bits_u8(fd, 8, data->eq_num); |
|
4288 xprintf(fd, ", .port = "); |
|
4289 write_bits_u8(fd, 8, data->port); |
|
4290 xprintf(fd, ", .event = "); |
|
4291 { unsigned int i; for (i = 0; i < 8; i++) { |
|
4292 write_bits_u64(fd, 64, data->event[i]); |
|
4293 xprintf(fd, ","); |
|
4294 } |
|
4295 } |
|
4296 xprintf(fd, ", .padding = "); |
|
4297 { unsigned int i; for (i = 0; i < 2; i++) { |
|
4298 write_bits_u64(fd, 64, data->padding[i]); |
|
4299 xprintf(fd, ","); |
|
4300 } |
|
4301 } |
|
4302 xprintf(fd, "}"); |
|
4303 } /* end write_..._psif_epsc_csr_event(psif_epsc_csr_event data) */ |
|
4304 |
|
4305 void write_struct_psif_epsc_csr_modify_device(XFILE *fd, |
|
4306 int network_order, |
|
4307 const struct psif_epsc_csr_modify_device *data) |
|
4308 { |
|
4309 u64 swap[11]; |
|
4310 |
|
4311 if (network_order) { |
|
4312 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4313 data = (struct psif_epsc_csr_modify_device *)swap; |
|
4314 } |
|
4315 xprintf(fd, "{"); |
|
4316 xprintf(fd, ", .modify_mask = "); |
|
4317 write_enum_psif_epsc_csr_modify_device_flags(fd, data->modify_mask); |
|
4318 xprintf(fd, ", .sys_image_guid = "); |
|
4319 write_bits_u64(fd, 64, data->sys_image_guid); |
|
4320 xprintf(fd, ", .node_desc = "); |
|
4321 { unsigned int i; for (i = 0; i < 64; i++) { |
|
4322 write_bits_u8(fd, 8, data->node_desc[i]); |
|
4323 xprintf(fd, ","); |
|
4324 } |
|
4325 } |
|
4326 xprintf(fd, ", .padding = "); |
|
4327 write_bits_u64(fd, 64, data->padding); |
|
4328 xprintf(fd, "}"); |
|
4329 } /* end write_..._psif_epsc_csr_modify_device(psif_epsc_csr_modify_device data) */ |
|
4330 |
|
4331 void write_struct_psif_epsc_csr_modify_port(XFILE *fd, |
|
4332 int network_order, |
|
4333 const struct psif_epsc_csr_modify_port *data) |
|
4334 { |
|
4335 u64 swap[11]; |
|
4336 |
|
4337 if (network_order) { |
|
4338 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4339 data = (struct psif_epsc_csr_modify_port *)swap; |
|
4340 } |
|
4341 xprintf(fd, "{"); |
|
4342 xprintf(fd, ", .init_type = "); |
|
4343 write_bits_u8(fd, 8, data->init_type); |
|
4344 xprintf(fd, ", .port = "); |
|
4345 write_bits_u8(fd, 8, data->port); |
|
4346 xprintf(fd, ", .modify_mask = "); |
|
4347 write_enum_psif_epsc_csr_modify_port_flags(fd, data->modify_mask); |
|
4348 xprintf(fd, ", .clr_port_cap_mask = "); |
|
4349 write_bits_u32(fd, 32, data->clr_port_cap_mask); |
|
4350 xprintf(fd, ", .set_port_cap_mask = "); |
|
4351 write_bits_u32(fd, 32, data->set_port_cap_mask); |
|
4352 xprintf(fd, "}"); |
|
4353 } /* end write_..._psif_epsc_csr_modify_port(psif_epsc_csr_modify_port data) */ |
|
4354 |
|
4355 void write_struct_psif_epsc_csr_test_host_wrd(XFILE *fd, |
|
4356 int network_order, |
|
4357 const struct psif_epsc_csr_test_host_wrd *data) |
|
4358 { |
|
4359 u64 swap[11]; |
|
4360 |
|
4361 if (network_order) { |
|
4362 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4363 data = (struct psif_epsc_csr_test_host_wrd *)swap; |
|
4364 } |
|
4365 xprintf(fd, "{"); |
|
4366 xprintf(fd, " .host_addr = "); |
|
4367 write_bits_u64(fd, 64, data->host_addr); |
|
4368 xprintf(fd, ", .epsc_offs = "); |
|
4369 write_bits_u32(fd, 32, data->epsc_offs); |
|
4370 xprintf(fd, ", .key = "); |
|
4371 write_bits_u32(fd, 32, data->key); |
|
4372 xprintf(fd, ", .pattern = "); |
|
4373 write_bits_u32(fd, 32, data->pattern); |
|
4374 xprintf(fd, ", .length = "); |
|
4375 write_bits_u32(fd, 32, data->length); |
|
4376 xprintf(fd, "}"); |
|
4377 } /* end write_..._psif_epsc_csr_test_host_wrd(psif_epsc_csr_test_host_wrd data) */ |
|
4378 |
|
4379 void write_struct_psif_epsc_csr_flash_access(XFILE *fd, |
|
4380 int network_order, |
|
4381 const struct psif_epsc_csr_flash_access *data) |
|
4382 { |
|
4383 u64 swap[11]; |
|
4384 |
|
4385 if (network_order) { |
|
4386 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4387 data = (struct psif_epsc_csr_flash_access *)swap; |
|
4388 } |
|
4389 xprintf(fd, "{"); |
|
4390 xprintf(fd, " .length = "); |
|
4391 write_bits_u32(fd, 32, data->length); |
|
4392 xprintf(fd, ", .offset = "); |
|
4393 write_bits_u32(fd, 32, data->offset); |
|
4394 xprintf(fd, ", .mmu_cntx = "); |
|
4395 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4396 xprintf(fd, ", .host_addr = "); |
|
4397 write_bits_u64(fd, 64, data->host_addr); |
|
4398 xprintf(fd, ", .crc = "); |
|
4399 write_bits_u64(fd, 64, data->crc); |
|
4400 xprintf(fd, "}"); |
|
4401 } /* end write_..._psif_epsc_csr_flash_access(psif_epsc_csr_flash_access data) */ |
|
4402 |
|
4403 void write_struct_psif_epsc_csr_trace_acquire(XFILE *fd, |
|
4404 int network_order, |
|
4405 const struct psif_epsc_csr_trace_acquire *data) |
|
4406 { |
|
4407 u64 swap[11]; |
|
4408 |
|
4409 if (network_order) { |
|
4410 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4411 data = (struct psif_epsc_csr_trace_acquire *)swap; |
|
4412 } |
|
4413 xprintf(fd, "{"); |
|
4414 xprintf(fd, " .host_addr = "); |
|
4415 write_bits_u64(fd, 64, data->host_addr); |
|
4416 xprintf(fd, ", .maxtrace = "); |
|
4417 write_bits_u32(fd, 32, data->maxtrace); |
|
4418 xprintf(fd, ", .offset = "); |
|
4419 write_bits_u32(fd, 32, data->offset); |
|
4420 xprintf(fd, ", .mmu_cntx = "); |
|
4421 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4422 xprintf(fd, ", .padding = "); |
|
4423 { unsigned int i; for (i = 0; i < 8; i++) { |
|
4424 write_bits_u64(fd, 64, data->padding[i]); |
|
4425 xprintf(fd, ","); |
|
4426 } |
|
4427 } |
|
4428 xprintf(fd, "}"); |
|
4429 } /* end write_..._psif_epsc_csr_trace_acquire(psif_epsc_csr_trace_acquire data) */ |
|
4430 |
|
4431 void write_struct_psif_epsc_csr_fw_version(XFILE *fd, |
|
4432 int network_order, |
|
4433 const struct psif_epsc_csr_fw_version *data) |
|
4434 { |
|
4435 u64 swap[11]; |
|
4436 |
|
4437 if (network_order) { |
|
4438 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4439 data = (struct psif_epsc_csr_fw_version *)swap; |
|
4440 } |
|
4441 xprintf(fd, "{"); |
|
4442 xprintf(fd, " .mmu_cntx = "); |
|
4443 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4444 xprintf(fd, ", .host_addr = "); |
|
4445 write_bits_u64(fd, 64, data->host_addr); |
|
4446 xprintf(fd, ", .data = "); |
|
4447 write_bits_u64(fd, 64, data->data); |
|
4448 xprintf(fd, "}"); |
|
4449 } /* end write_..._psif_epsc_csr_fw_version(psif_epsc_csr_fw_version data) */ |
|
4450 |
|
4451 void write_struct_psif_epsc_csr_log_ctrl(XFILE *fd, |
|
4452 int network_order, |
|
4453 const struct psif_epsc_csr_log_ctrl *data) |
|
4454 { |
|
4455 u64 swap[11]; |
|
4456 |
|
4457 if (network_order) { |
|
4458 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4459 data = (struct psif_epsc_csr_log_ctrl *)swap; |
|
4460 } |
|
4461 xprintf(fd, "{"); |
|
4462 xprintf(fd, " .mmu_cntx = "); |
|
4463 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4464 xprintf(fd, ", .mode = "); |
|
4465 write_enum_psif_epsc_log_mode(fd, data->mode); |
|
4466 xprintf(fd, ", .level = "); |
|
4467 write_enum_psif_epsc_log_level(fd, data->level); |
|
4468 xprintf(fd, ", .base = "); |
|
4469 write_bits_u64(fd, 64, data->base); |
|
4470 xprintf(fd, ", .stat_base = "); |
|
4471 write_bits_u64(fd, 64, data->stat_base); |
|
4472 xprintf(fd, ", .length = "); |
|
4473 write_bits_u64(fd, 64, data->length); |
|
4474 xprintf(fd, "}"); |
|
4475 } /* end write_..._psif_epsc_csr_log_ctrl(psif_epsc_csr_log_ctrl data) */ |
|
4476 |
|
4477 void write_struct_psif_epsc_csr_epsa_cntrl(XFILE *fd, |
|
4478 int network_order, |
|
4479 const struct psif_epsc_csr_epsa_cntrl *data) |
|
4480 { |
|
4481 u64 swap[11]; |
|
4482 |
|
4483 if (network_order) { |
|
4484 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4485 data = (struct psif_epsc_csr_epsa_cntrl *)swap; |
|
4486 } |
|
4487 xprintf(fd, "{"); |
|
4488 xprintf(fd, ", .epsa = "); |
|
4489 write_enum_psif_eps_a_core(fd, data->epsa); |
|
4490 xprintf(fd, ", .command = "); |
|
4491 write_enum_psif_epsc_csr_epsa_command(fd, data->command); |
|
4492 xprintf(fd, ", .flash_addr = "); |
|
4493 write_bits_u64(fd, 64, data->flash_addr); |
|
4494 xprintf(fd, ", .epsa_addr = "); |
|
4495 write_bits_u64(fd, 64, data->epsa_addr); |
|
4496 xprintf(fd, "}"); |
|
4497 } /* end write_..._psif_epsc_csr_epsa_cntrl(psif_epsc_csr_epsa_cntrl data) */ |
|
4498 |
|
4499 void write_struct_psif_epsc_csr_epsa_cmd(XFILE *fd, |
|
4500 int network_order, |
|
4501 const struct psif_epsc_csr_epsa_cmd *data) |
|
4502 { |
|
4503 u64 swap[11]; |
|
4504 |
|
4505 if (network_order) { |
|
4506 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4507 data = (struct psif_epsc_csr_epsa_cmd *)swap; |
|
4508 } |
|
4509 xprintf(fd, "{"); |
|
4510 xprintf(fd, " .length = "); |
|
4511 write_bits_u32(fd, 32, data->length); |
|
4512 xprintf(fd, ", .cmd = "); |
|
4513 write_enum_psif_epsa_command(fd, data->cmd); |
|
4514 xprintf(fd, ", .host_addr = "); |
|
4515 write_bits_u64(fd, 64, data->host_addr); |
|
4516 xprintf(fd, ", .entry_point = "); |
|
4517 { unsigned int i; for (i = 0; i < 16; i++) { |
|
4518 write_bits_u8(fd, 8, data->entry_point[i]); |
|
4519 xprintf(fd, ","); |
|
4520 } |
|
4521 } |
|
4522 xprintf(fd, ", .qpnum = "); |
|
4523 write_bits_u32(fd, 32, data->qpnum); |
|
4524 xprintf(fd, ", .key = "); |
|
4525 write_bits_u32(fd, 32, data->key); |
|
4526 xprintf(fd, "}"); |
|
4527 } /* end write_..._psif_epsc_csr_epsa_cmd(psif_epsc_csr_epsa_cmd data) */ |
|
4528 |
|
4529 void write_struct_psif_epsc_csr_cli_access(XFILE *fd, |
|
4530 int network_order, |
|
4531 const struct psif_epsc_csr_cli_access *data) |
|
4532 { |
|
4533 u64 swap[11]; |
|
4534 |
|
4535 if (network_order) { |
|
4536 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4537 data = (struct psif_epsc_csr_cli_access *)swap; |
|
4538 } |
|
4539 xprintf(fd, "{"); |
|
4540 xprintf(fd, " .host_addr = "); |
|
4541 write_bits_u64(fd, 64, data->host_addr); |
|
4542 xprintf(fd, ", .mmu_cntx = "); |
|
4543 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4544 xprintf(fd, ", .command = "); |
|
4545 { unsigned int i; for (i = 0; i < 72; i++) { |
|
4546 write_bits_u8(fd, 8, data->command[i]); |
|
4547 xprintf(fd, ","); |
|
4548 } |
|
4549 } |
|
4550 xprintf(fd, "}"); |
|
4551 } /* end write_..._psif_epsc_csr_cli_access(psif_epsc_csr_cli_access data) */ |
|
4552 |
|
4553 void write_struct_psif_epsc_csr_mad_process(XFILE *fd, |
|
4554 int network_order, |
|
4555 const struct psif_epsc_csr_mad_process *data) |
|
4556 { |
|
4557 u64 swap[11]; |
|
4558 |
|
4559 if (network_order) { |
|
4560 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4561 data = (struct psif_epsc_csr_mad_process *)swap; |
|
4562 } |
|
4563 xprintf(fd, "{"); |
|
4564 xprintf(fd, " .host_addr = "); |
|
4565 write_bits_u64(fd, 64, data->host_addr); |
|
4566 xprintf(fd, ", .mmu_cntx = "); |
|
4567 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4568 xprintf(fd, ", .qp = "); |
|
4569 write_bits_u32(fd, 24, data->qp); |
|
4570 xprintf(fd, ", .opcode = "); |
|
4571 write_enum_psif_wc_opcode(fd, data->opcode); |
|
4572 xprintf(fd, ", .byte_len = "); |
|
4573 write_bits_u32(fd, 32, data->byte_len); |
|
4574 xprintf(fd, ", .slid = "); |
|
4575 write_bits_u16(fd, 16, data->slid); |
|
4576 xprintf(fd, ", .port = "); |
|
4577 write_enum_psif_port(fd, data->port); |
|
4578 xprintf(fd, ", .sl = "); |
|
4579 write_bits_u8(fd, 4, data->sl); |
|
4580 xprintf(fd, ", .pkey_indx = "); |
|
4581 write_bits_u16(fd, 9, data->pkey_indx); |
|
4582 xprintf(fd, ", .wc_flags_with_imm = "); |
|
4583 write_bits_u8(fd, 1, data->wc_flags_with_imm); |
|
4584 xprintf(fd, ", .wc_flags_grh = "); |
|
4585 write_bits_u8(fd, 1, data->wc_flags_grh); |
|
4586 xprintf(fd, ", .src_qp = "); |
|
4587 write_bits_u32(fd, 24, data->src_qp); |
|
4588 xprintf(fd, ", .status = "); |
|
4589 write_enum_psif_wc_status(fd, data->status); |
|
4590 xprintf(fd, ", .dlid_path_bits = "); |
|
4591 write_bits_u8(fd, 7, data->dlid_path_bits); |
|
4592 xprintf(fd, "}"); |
|
4593 } /* end write_..._psif_epsc_csr_mad_process(psif_epsc_csr_mad_process data) */ |
|
4594 |
|
4595 void write_struct_psif_epsc_csr_mad_send_wr(XFILE *fd, |
|
4596 int network_order, |
|
4597 const struct psif_epsc_csr_mad_send_wr *data) |
|
4598 { |
|
4599 u64 swap[11]; |
|
4600 |
|
4601 if (network_order) { |
|
4602 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4603 data = (struct psif_epsc_csr_mad_send_wr *)swap; |
|
4604 } |
|
4605 xprintf(fd, "{"); |
|
4606 xprintf(fd, " .host_addr = "); |
|
4607 write_bits_u64(fd, 64, data->host_addr); |
|
4608 xprintf(fd, ", .mmu_cntx = "); |
|
4609 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4610 xprintf(fd, "}"); |
|
4611 } /* end write_..._psif_epsc_csr_mad_send_wr(psif_epsc_csr_mad_send_wr data) */ |
|
4612 |
|
4613 void write_struct_psif_epsc_query_req(XFILE *fd, |
|
4614 int network_order, |
|
4615 const struct psif_epsc_query_req *data) |
|
4616 { |
|
4617 u64 swap[2]; |
|
4618 |
|
4619 if (network_order) { |
|
4620 copy_convert_to_sw(swap, (volatile void *)data, 16); |
|
4621 data = (struct psif_epsc_query_req *)swap; |
|
4622 } |
|
4623 xprintf(fd, "{"); |
|
4624 xprintf(fd, " .index = "); |
|
4625 write_bits_u32(fd, 32, data->index); |
|
4626 xprintf(fd, ", .op = "); |
|
4627 write_enum_psif_epsc_query_op(fd, data->op); |
|
4628 xprintf(fd, ", .value = "); |
|
4629 write_bits_u64(fd, 64, data->value); |
|
4630 xprintf(fd, "}"); |
|
4631 } /* end write_..._psif_epsc_query_req(psif_epsc_query_req data) */ |
|
4632 |
|
4633 void write_struct_psif_epsc_csr_query(XFILE *fd, |
|
4634 int network_order, |
|
4635 const struct psif_epsc_csr_query *data) |
|
4636 { |
|
4637 u64 swap[11]; |
|
4638 |
|
4639 if (network_order) { |
|
4640 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4641 data = (struct psif_epsc_csr_query *)swap; |
|
4642 } |
|
4643 xprintf(fd, "{"); |
|
4644 xprintf(fd, ", .uf = "); |
|
4645 write_bits_u32(fd, 32, data->uf); |
|
4646 xprintf(fd, ", .data = "); |
|
4647 write_struct_psif_epsc_query_req(fd, 0, &(data->data)); |
|
4648 xprintf(fd, ", .info = "); |
|
4649 write_struct_psif_epsc_query_req(fd, 0, &(data->info)); |
|
4650 xprintf(fd, "}"); |
|
4651 } /* end write_..._psif_epsc_csr_query(psif_epsc_csr_query data) */ |
|
4652 |
|
4653 void write_struct_psif_epsc_csr_set(XFILE *fd, |
|
4654 int network_order, |
|
4655 const struct psif_epsc_csr_set *data) |
|
4656 { |
|
4657 u64 swap[11]; |
|
4658 |
|
4659 if (network_order) { |
|
4660 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4661 data = (struct psif_epsc_csr_set *)swap; |
|
4662 } |
|
4663 xprintf(fd, "{"); |
|
4664 xprintf(fd, ", .uf = "); |
|
4665 write_bits_u32(fd, 32, data->uf); |
|
4666 xprintf(fd, ", .data = "); |
|
4667 write_struct_psif_epsc_query_req(fd, 0, &(data->data)); |
|
4668 xprintf(fd, ", .info = "); |
|
4669 write_struct_psif_epsc_query_req(fd, 0, &(data->info)); |
|
4670 xprintf(fd, "}"); |
|
4671 } /* end write_..._psif_epsc_csr_set(psif_epsc_csr_set data) */ |
|
4672 |
|
4673 void write_struct_psif_epsc_csr_interrupt_common(XFILE *fd, |
|
4674 int network_order, |
|
4675 const struct psif_epsc_csr_interrupt_common *data) |
|
4676 { |
|
4677 u64 swap[11]; |
|
4678 |
|
4679 if (network_order) { |
|
4680 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4681 data = (struct psif_epsc_csr_interrupt_common *)swap; |
|
4682 } |
|
4683 xprintf(fd, "{"); |
|
4684 xprintf(fd, ", .total_usec = "); |
|
4685 write_bits_u16(fd, 16, data->total_usec); |
|
4686 xprintf(fd, "}"); |
|
4687 } /* end write_..._psif_epsc_csr_interrupt_common(psif_epsc_csr_interrupt_common data) */ |
|
4688 |
|
4689 void write_struct_psif_interrupt_attributes(XFILE *fd, |
|
4690 int network_order, |
|
4691 const struct psif_interrupt_attributes *data) |
|
4692 { |
|
4693 u64 swap[1]; |
|
4694 |
|
4695 if (network_order) { |
|
4696 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
4697 data = (struct psif_interrupt_attributes *)swap; |
|
4698 } |
|
4699 xprintf(fd, "{"); |
|
4700 xprintf(fd, ", .channel_pusec_high = "); |
|
4701 write_bits_u8(fd, 1, data->channel_pusec_high); |
|
4702 xprintf(fd, ", .channel_pusec_low = "); |
|
4703 write_bits_u8(fd, 1, data->channel_pusec_low); |
|
4704 xprintf(fd, ", .channel_pusec = "); |
|
4705 write_bits_u8(fd, 1, data->channel_pusec); |
|
4706 xprintf(fd, ", .channel_ausec_high = "); |
|
4707 write_bits_u8(fd, 1, data->channel_ausec_high); |
|
4708 xprintf(fd, ", .channel_ausec_low = "); |
|
4709 write_bits_u8(fd, 1, data->channel_ausec_low); |
|
4710 xprintf(fd, ", .channel_ausec = "); |
|
4711 write_bits_u8(fd, 1, data->channel_ausec); |
|
4712 xprintf(fd, ", .channel_rate_high = "); |
|
4713 write_bits_u8(fd, 1, data->channel_rate_high); |
|
4714 xprintf(fd, ", .channel_rate_low = "); |
|
4715 write_bits_u8(fd, 1, data->channel_rate_low); |
|
4716 xprintf(fd, ", .channel_rx_scale = "); |
|
4717 write_bits_u8(fd, 1, data->channel_rx_scale); |
|
4718 xprintf(fd, ", .enable_adaptive = "); |
|
4719 write_bits_u8(fd, 1, data->enable_adaptive); |
|
4720 xprintf(fd, "}"); |
|
4721 } /* end write_..._psif_interrupt_attributes(psif_interrupt_attributes data) */ |
|
4722 |
|
4723 void write_struct_psif_epsc_csr_interrupt_channel(XFILE *fd, |
|
4724 int network_order, |
|
4725 const struct psif_epsc_csr_interrupt_channel *data) |
|
4726 { |
|
4727 u64 swap[11]; |
|
4728 |
|
4729 if (network_order) { |
|
4730 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4731 data = (struct psif_epsc_csr_interrupt_channel *)swap; |
|
4732 } |
|
4733 xprintf(fd, "{"); |
|
4734 xprintf(fd, " .attributes = "); |
|
4735 write_struct_psif_interrupt_attributes(fd, 0, &(data->attributes)); |
|
4736 xprintf(fd, ", .channel_rx_scale = "); |
|
4737 write_bits_u16(fd, 16, data->channel_rx_scale); |
|
4738 xprintf(fd, ", .enable_adaptive = "); |
|
4739 write_bits_u8(fd, 1, data->enable_adaptive); |
|
4740 xprintf(fd, ", .int_channel = "); |
|
4741 write_bits_u16(fd, 16, data->int_channel); |
|
4742 xprintf(fd, ", .channel_rate_high = "); |
|
4743 write_bits_u32(fd, 32, data->channel_rate_high); |
|
4744 xprintf(fd, ", .channel_rate_low = "); |
|
4745 write_bits_u32(fd, 32, data->channel_rate_low); |
|
4746 xprintf(fd, ", .channel_pusec = "); |
|
4747 write_bits_u16(fd, 16, data->channel_pusec); |
|
4748 xprintf(fd, ", .channel_ausec_high = "); |
|
4749 write_bits_u16(fd, 16, data->channel_ausec_high); |
|
4750 xprintf(fd, ", .channel_ausec_low = "); |
|
4751 write_bits_u16(fd, 16, data->channel_ausec_low); |
|
4752 xprintf(fd, ", .channel_ausec = "); |
|
4753 write_bits_u16(fd, 16, data->channel_ausec); |
|
4754 xprintf(fd, ", .channel_pusec_high = "); |
|
4755 write_bits_u16(fd, 16, data->channel_pusec_high); |
|
4756 xprintf(fd, ", .channel_pusec_low = "); |
|
4757 write_bits_u16(fd, 16, data->channel_pusec_low); |
|
4758 xprintf(fd, "}"); |
|
4759 } /* end write_..._psif_epsc_csr_interrupt_channel(psif_epsc_csr_interrupt_channel data) */ |
|
4760 |
|
4761 void write_union_psif_epsc_update_set_or_offset(XFILE *fd, |
|
4762 int network_order, |
|
4763 const union psif_epsc_update_set_or_offset *data) |
|
4764 { |
|
4765 xprintf(fd, "{"); |
|
4766 xprintf(fd, " .offset = "); |
|
4767 write_bits_u32(fd, 32, data->offset); |
|
4768 xprintf(fd, ", .set = "); |
|
4769 write_enum_psif_epsc_update_set(fd, data->set); |
|
4770 xprintf(fd, "}"); |
|
4771 } /* end write_..._psif_epsc_update_set_or_offset(psif_epsc_update_set_or_offset data) */ |
|
4772 |
|
4773 void write_struct_psif_epsc_csr_update(XFILE *fd, |
|
4774 int network_order, |
|
4775 const struct psif_epsc_csr_update *data) |
|
4776 { |
|
4777 u64 swap[11]; |
|
4778 |
|
4779 if (network_order) { |
|
4780 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4781 data = (struct psif_epsc_csr_update *)swap; |
|
4782 } |
|
4783 xprintf(fd, "{"); |
|
4784 xprintf(fd, " .u = "); |
|
4785 write_union_psif_epsc_update_set_or_offset(fd, 0, &(data->u)); |
|
4786 xprintf(fd, ", .slot = "); |
|
4787 write_enum_psif_epsc_flash_slot(fd, data->slot); |
|
4788 xprintf(fd, ", .opcode = "); |
|
4789 write_enum_psif_epsc_csr_update_opcode(fd, data->opcode); |
|
4790 xprintf(fd, ", .id = "); |
|
4791 write_bits_u32(fd, 32, data->id); |
|
4792 xprintf(fd, ", .length = "); |
|
4793 write_bits_u32(fd, 32, data->length); |
|
4794 xprintf(fd, ", .mmu_cntx = "); |
|
4795 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4796 xprintf(fd, ", .host_addr = "); |
|
4797 write_bits_u64(fd, 64, data->host_addr); |
|
4798 xprintf(fd, "}"); |
|
4799 } /* end write_..._psif_epsc_csr_update(psif_epsc_csr_update data) */ |
|
4800 |
|
4801 void write_struct_psif_epsc_csr_uf_ctrl(XFILE *fd, |
|
4802 int network_order, |
|
4803 const struct psif_epsc_csr_uf_ctrl *data) |
|
4804 { |
|
4805 u64 swap[11]; |
|
4806 |
|
4807 if (network_order) { |
|
4808 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4809 data = (struct psif_epsc_csr_uf_ctrl *)swap; |
|
4810 } |
|
4811 xprintf(fd, "{"); |
|
4812 xprintf(fd, " .flags = "); |
|
4813 write_bits_u32(fd, 32, data->flags); |
|
4814 xprintf(fd, ", .opcode = "); |
|
4815 write_enum_psif_epsc_csr_uf_ctrl_opcode(fd, data->opcode); |
|
4816 xprintf(fd, ", .uf_vector = "); |
|
4817 write_bits_u64(fd, 64, data->uf_vector); |
|
4818 xprintf(fd, "}"); |
|
4819 } /* end write_..._psif_epsc_csr_uf_ctrl(psif_epsc_csr_uf_ctrl data) */ |
|
4820 |
|
4821 void write_struct_psif_csr_mmu_flush_caches(XFILE *fd, |
|
4822 int network_order, |
|
4823 const struct psif_csr_mmu_flush_caches *data) |
|
4824 { |
|
4825 u64 swap[1]; |
|
4826 |
|
4827 if (network_order) { |
|
4828 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
4829 data = (struct psif_csr_mmu_flush_caches *)swap; |
|
4830 } |
|
4831 xprintf(fd, "{"); |
|
4832 xprintf(fd, " .flush_mmu_cache = "); |
|
4833 write_bits_u8(fd, 1, data->flush_mmu_cache); |
|
4834 xprintf(fd, ", .flush_ptw_cache = "); |
|
4835 write_bits_u8(fd, 1, data->flush_ptw_cache); |
|
4836 xprintf(fd, ", .mmu_cache_flushed = "); |
|
4837 write_bits_u8(fd, 1, data->mmu_cache_flushed); |
|
4838 xprintf(fd, ", .ptw_cache_flushed = "); |
|
4839 write_bits_u8(fd, 1, data->ptw_cache_flushed); |
|
4840 xprintf(fd, "}"); |
|
4841 } /* end write_..._psif_csr_mmu_flush_caches(psif_csr_mmu_flush_caches data) */ |
|
4842 |
|
4843 void write_struct_psif_epsc_flush_caches(XFILE *fd, |
|
4844 int network_order, |
|
4845 const struct psif_epsc_flush_caches *data) |
|
4846 { |
|
4847 u64 swap[11]; |
|
4848 |
|
4849 if (network_order) { |
|
4850 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
4851 data = (struct psif_epsc_flush_caches *)swap; |
|
4852 } |
|
4853 xprintf(fd, "{"); |
|
4854 xprintf(fd, " .flush_mmu_caches = "); |
|
4855 write_struct_psif_csr_mmu_flush_caches(fd, 0, &(data->flush_mmu_caches)); |
|
4856 xprintf(fd, "}"); |
|
4857 } /* end write_..._psif_epsc_flush_caches(psif_epsc_flush_caches data) */ |
|
4858 |
|
4859 void write_struct_psif_epsc_csr_pma_counters(XFILE *fd, |
|
4860 int network_order, |
|
4861 const struct psif_epsc_csr_pma_counters *data) |
|
4862 { |
|
4863 u64 swap[4]; |
|
4864 |
|
4865 if (network_order) { |
|
4866 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
4867 data = (struct psif_epsc_csr_pma_counters *)swap; |
|
4868 } |
|
4869 xprintf(fd, "{"); |
|
4870 xprintf(fd, " .port = "); |
|
4871 write_bits_u32(fd, 32, data->port); |
|
4872 xprintf(fd, ", .uf = "); |
|
4873 write_bits_u32(fd, 32, data->uf); |
|
4874 xprintf(fd, ", .host_addr = "); |
|
4875 write_bits_u64(fd, 64, data->host_addr); |
|
4876 xprintf(fd, ", .mmu_cntx = "); |
|
4877 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
4878 xprintf(fd, ", .clear_mask = "); |
|
4879 write_bits_u64(fd, 64, data->clear_mask); |
|
4880 xprintf(fd, "}"); |
|
4881 } /* end write_..._psif_epsc_csr_pma_counters(psif_epsc_csr_pma_counters data) */ |
|
4882 |
|
4883 void write_struct_psif_epsc_vimma_dereg(XFILE *fd, |
|
4884 int network_order, |
|
4885 const struct psif_epsc_vimma_dereg *data) |
|
4886 { |
|
4887 u64 swap[5]; |
|
4888 |
|
4889 if (network_order) { |
|
4890 copy_convert_to_sw(swap, (volatile void *)data, 40); |
|
4891 data = (struct psif_epsc_vimma_dereg *)swap; |
|
4892 } |
|
4893 xprintf(fd, "{"); |
|
4894 xprintf(fd, " .high_uf = "); |
|
4895 write_bits_u16(fd, 16, data->high_uf); |
|
4896 xprintf(fd, ", .low_uf = "); |
|
4897 write_bits_u16(fd, 16, data->low_uf); |
|
4898 xprintf(fd, ", .uf_vector = "); |
|
4899 { unsigned int i; for (i = 0; i < 4; i++) { |
|
4900 write_bits_u64(fd, 64, data->uf_vector[i]); |
|
4901 xprintf(fd, ","); |
|
4902 } |
|
4903 } |
|
4904 xprintf(fd, "}"); |
|
4905 } /* end write_..._psif_epsc_vimma_dereg(psif_epsc_vimma_dereg data) */ |
|
4906 |
|
4907 void write_struct_psif_epsc_vimma_vfp_reg(XFILE *fd, |
|
4908 int network_order, |
|
4909 const struct psif_epsc_vimma_vfp_reg *data) |
|
4910 { |
|
4911 u64 swap[5]; |
|
4912 |
|
4913 if (network_order) { |
|
4914 copy_convert_to_sw(swap, (volatile void *)data, 40); |
|
4915 data = (struct psif_epsc_vimma_vfp_reg *)swap; |
|
4916 } |
|
4917 xprintf(fd, "{"); |
|
4918 xprintf(fd, " .vm_context = "); |
|
4919 write_bits_u32(fd, 32, data->vm_context); |
|
4920 xprintf(fd, ", .uf = "); |
|
4921 write_bits_u16(fd, 16, data->uf); |
|
4922 xprintf(fd, ", .vm_id = "); |
|
4923 { unsigned int i; for (i = 0; i < 16; i++) { |
|
4924 write_bits_u8(fd, 8, data->vm_id[i]); |
|
4925 xprintf(fd, ","); |
|
4926 } |
|
4927 } |
|
4928 xprintf(fd, ", .vhca_instance = "); |
|
4929 write_bits_u16(fd, 16, data->vhca_instance); |
|
4930 xprintf(fd, ", .vm_incarnation = "); |
|
4931 write_bits_u32(fd, 32, data->vm_incarnation); |
|
4932 xprintf(fd, "}"); |
|
4933 } /* end write_..._psif_epsc_vimma_vfp_reg(psif_epsc_vimma_vfp_reg data) */ |
|
4934 |
|
4935 void write_struct_psif_epsc_vimma_set_admmode(XFILE *fd, |
|
4936 int network_order, |
|
4937 const struct psif_epsc_vimma_set_admmode *data) |
|
4938 { |
|
4939 u64 swap[5]; |
|
4940 |
|
4941 if (network_order) { |
|
4942 copy_convert_to_sw(swap, (volatile void *)data, 40); |
|
4943 data = (struct psif_epsc_vimma_set_admmode *)swap; |
|
4944 } |
|
4945 xprintf(fd, "{"); |
|
4946 xprintf(fd, " .high_uf = "); |
|
4947 write_bits_u16(fd, 16, data->high_uf); |
|
4948 xprintf(fd, ", .low_uf = "); |
|
4949 write_bits_u16(fd, 16, data->low_uf); |
|
4950 xprintf(fd, ", .mode = "); |
|
4951 write_enum_psif_epsc_vimma_admmode(fd, data->mode); |
|
4952 xprintf(fd, ", .uf_vector = "); |
|
4953 { unsigned int i; for (i = 0; i < 4; i++) { |
|
4954 write_bits_u64(fd, 64, data->uf_vector[i]); |
|
4955 xprintf(fd, ","); |
|
4956 } |
|
4957 } |
|
4958 xprintf(fd, "}"); |
|
4959 } /* end write_..._psif_epsc_vimma_set_admmode(psif_epsc_vimma_set_admmode data) */ |
|
4960 |
|
4961 void write_struct_psif_epsc_vimma_reg_info(XFILE *fd, |
|
4962 int network_order, |
|
4963 const struct psif_epsc_vimma_reg_info *data) |
|
4964 { |
|
4965 u64 swap[5]; |
|
4966 |
|
4967 if (network_order) { |
|
4968 copy_convert_to_sw(swap, (volatile void *)data, 40); |
|
4969 data = (struct psif_epsc_vimma_reg_info *)swap; |
|
4970 } |
|
4971 xprintf(fd, "{"); |
|
4972 xprintf(fd, " .high_uf = "); |
|
4973 write_bits_u16(fd, 16, data->high_uf); |
|
4974 xprintf(fd, ", .low_uf = "); |
|
4975 write_bits_u16(fd, 16, data->low_uf); |
|
4976 xprintf(fd, ", .uf_vector = "); |
|
4977 { unsigned int i; for (i = 0; i < 4; i++) { |
|
4978 write_bits_u64(fd, 64, data->uf_vector[i]); |
|
4979 xprintf(fd, ","); |
|
4980 } |
|
4981 } |
|
4982 xprintf(fd, "}"); |
|
4983 } /* end write_..._psif_epsc_vimma_reg_info(psif_epsc_vimma_reg_info data) */ |
|
4984 |
|
4985 void write_union_psif_epsc_vimma_ctrl_cmd(XFILE *fd, |
|
4986 int network_order, |
|
4987 const union psif_epsc_vimma_ctrl_cmd *data) |
|
4988 { |
|
4989 u64 swap[5]; |
|
4990 |
|
4991 if (network_order) { |
|
4992 copy_convert_to_sw(swap, (volatile void *)data, 40); |
|
4993 data = (union psif_epsc_vimma_ctrl_cmd *)swap; |
|
4994 } |
|
4995 xprintf(fd, "{"); |
|
4996 xprintf(fd, " .dereg = "); |
|
4997 write_struct_psif_epsc_vimma_dereg(fd, 0, &(data->dereg)); |
|
4998 xprintf(fd, ", .vfp_reg = "); |
|
4999 write_struct_psif_epsc_vimma_vfp_reg(fd, 0, &(data->vfp_reg)); |
|
5000 xprintf(fd, ", .adm_mode = "); |
|
5001 write_struct_psif_epsc_vimma_set_admmode(fd, 0, &(data->adm_mode)); |
|
5002 xprintf(fd, ", .reg_info = "); |
|
5003 write_struct_psif_epsc_vimma_reg_info(fd, 0, &(data->reg_info)); |
|
5004 xprintf(fd, "}"); |
|
5005 } /* end write_..._psif_epsc_vimma_ctrl_cmd(psif_epsc_vimma_ctrl_cmd data) */ |
|
5006 |
|
5007 void write_struct_psif_epsc_csr_vimma_ctrl(XFILE *fd, |
|
5008 int network_order, |
|
5009 const struct psif_epsc_csr_vimma_ctrl *data) |
|
5010 { |
|
5011 u64 swap[11]; |
|
5012 |
|
5013 if (network_order) { |
|
5014 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
5015 data = (struct psif_epsc_csr_vimma_ctrl *)swap; |
|
5016 } |
|
5017 xprintf(fd, "{"); |
|
5018 xprintf(fd, " .length = "); |
|
5019 write_bits_u32(fd, 32, data->length); |
|
5020 xprintf(fd, ", .opcode = "); |
|
5021 write_enum_psif_epsc_vimma_ctrl_opcode(fd, data->opcode); |
|
5022 xprintf(fd, ", .u = "); |
|
5023 write_union_psif_epsc_vimma_ctrl_cmd(fd, 0, &(data->u)); |
|
5024 xprintf(fd, ", .mmu_cntx = "); |
|
5025 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
5026 xprintf(fd, ", .host_addr = "); |
|
5027 write_bits_u64(fd, 64, data->host_addr); |
|
5028 xprintf(fd, "}"); |
|
5029 } /* end write_..._psif_epsc_csr_vimma_ctrl(psif_epsc_csr_vimma_ctrl data) */ |
|
5030 |
|
5031 void write_struct_psif_epsc_csr_ber_data(XFILE *fd, |
|
5032 int network_order, |
|
5033 const struct psif_epsc_csr_ber_data *data) |
|
5034 { |
|
5035 u64 swap[3]; |
|
5036 |
|
5037 if (network_order) { |
|
5038 copy_convert_to_sw(swap, (volatile void *)data, 24); |
|
5039 data = (struct psif_epsc_csr_ber_data *)swap; |
|
5040 } |
|
5041 xprintf(fd, "{"); |
|
5042 xprintf(fd, " .host_addr = "); |
|
5043 write_bits_u64(fd, 64, data->host_addr); |
|
5044 xprintf(fd, ", .mmu_cntx = "); |
|
5045 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
5046 xprintf(fd, ", .len = "); |
|
5047 write_bits_u32(fd, 32, data->len); |
|
5048 xprintf(fd, ", .port = "); |
|
5049 write_bits_u32(fd, 32, data->port); |
|
5050 xprintf(fd, "}"); |
|
5051 } /* end write_..._psif_epsc_csr_ber_data(psif_epsc_csr_ber_data data) */ |
|
5052 |
|
5053 void write_union_psif_epsc_csr_details(XFILE *fd, |
|
5054 int network_order, |
|
5055 const union psif_epsc_csr_details *data) |
|
5056 { |
|
5057 u64 swap[11]; |
|
5058 |
|
5059 if (network_order) { |
|
5060 copy_convert_to_sw(swap, (volatile void *)data, 88); |
|
5061 data = (union psif_epsc_csr_details *)swap; |
|
5062 } |
|
5063 xprintf(fd, "{"); |
|
5064 xprintf(fd, " .opaque = "); |
|
5065 write_struct_psif_epsc_csr_opaque(fd, 0, &(data->opaque)); |
|
5066 xprintf(fd, ", .single = "); |
|
5067 write_struct_psif_epsc_csr_single(fd, 0, &(data->single)); |
|
5068 xprintf(fd, ", .base_addr = "); |
|
5069 write_struct_psif_epsc_csr_base_addr(fd, 0, &(data->base_addr)); |
|
5070 xprintf(fd, ", .modify_qp = "); |
|
5071 write_struct_psif_epsc_csr_modify_qp(fd, 0, &(data->modify_qp)); |
|
5072 xprintf(fd, ", .query_qp = "); |
|
5073 write_struct_psif_epsc_csr_query_qp(fd, 0, &(data->query_qp)); |
|
5074 xprintf(fd, ", .set_lid = "); |
|
5075 write_struct_psif_epsc_csr_set_lid(fd, 0, &(data->set_lid)); |
|
5076 xprintf(fd, ", .set_gid = "); |
|
5077 write_struct_psif_epsc_csr_set_gid(fd, 0, &(data->set_gid)); |
|
5078 xprintf(fd, ", .set_eoib_mac = "); |
|
5079 write_struct_psif_epsc_csr_set_eoib_mac(fd, 0, &(data->set_eoib_mac)); |
|
5080 xprintf(fd, ", .set_vlink = "); |
|
5081 write_struct_psif_epsc_csr_vlink_state(fd, 0, &(data->set_vlink)); |
|
5082 xprintf(fd, ", .query_hw = "); |
|
5083 write_struct_psif_epsc_csr_query_hw(fd, 0, &(data->query_hw)); |
|
5084 xprintf(fd, ", .query_table = "); |
|
5085 write_struct_psif_epsc_csr_query_table(fd, 0, &(data->query_table)); |
|
5086 xprintf(fd, ", .mc = "); |
|
5087 write_struct_psif_epsc_csr_mc(fd, 0, &(data->mc)); |
|
5088 xprintf(fd, ", .event = "); |
|
5089 write_struct_psif_epsc_csr_event(fd, 0, &(data->event)); |
|
5090 xprintf(fd, ", .device = "); |
|
5091 write_struct_psif_epsc_csr_modify_device(fd, 0, &(data->device)); |
|
5092 xprintf(fd, ", .port = "); |
|
5093 write_struct_psif_epsc_csr_modify_port(fd, 0, &(data->port)); |
|
5094 xprintf(fd, ", .host_wrd = "); |
|
5095 write_struct_psif_epsc_csr_test_host_wrd(fd, 0, &(data->host_wrd)); |
|
5096 xprintf(fd, ", .flash = "); |
|
5097 write_struct_psif_epsc_csr_flash_access(fd, 0, &(data->flash)); |
|
5098 xprintf(fd, ", .trace_acquire = "); |
|
5099 write_struct_psif_epsc_csr_trace_acquire(fd, 0, &(data->trace_acquire)); |
|
5100 xprintf(fd, ", .fw_version = "); |
|
5101 write_struct_psif_epsc_csr_fw_version(fd, 0, &(data->fw_version)); |
|
5102 xprintf(fd, ", .log_ctrl = "); |
|
5103 write_struct_psif_epsc_csr_log_ctrl(fd, 0, &(data->log_ctrl)); |
|
5104 xprintf(fd, ", .epsa_cntrl = "); |
|
5105 write_struct_psif_epsc_csr_epsa_cntrl(fd, 0, &(data->epsa_cntrl)); |
|
5106 xprintf(fd, ", .epsa_cmd = "); |
|
5107 write_struct_psif_epsc_csr_epsa_cmd(fd, 0, &(data->epsa_cmd)); |
|
5108 xprintf(fd, ", .cli = "); |
|
5109 write_struct_psif_epsc_csr_cli_access(fd, 0, &(data->cli)); |
|
5110 xprintf(fd, ", .mad_process = "); |
|
5111 write_struct_psif_epsc_csr_mad_process(fd, 0, &(data->mad_process)); |
|
5112 xprintf(fd, ", .mad_send_wr = "); |
|
5113 write_struct_psif_epsc_csr_mad_send_wr(fd, 0, &(data->mad_send_wr)); |
|
5114 xprintf(fd, ", .query = "); |
|
5115 write_struct_psif_epsc_csr_query(fd, 0, &(data->query)); |
|
5116 xprintf(fd, ", .set = "); |
|
5117 write_struct_psif_epsc_csr_set(fd, 0, &(data->set)); |
|
5118 xprintf(fd, ", .int_common = "); |
|
5119 write_struct_psif_epsc_csr_interrupt_common(fd, 0, &(data->int_common)); |
|
5120 xprintf(fd, ", .int_channel = "); |
|
5121 write_struct_psif_epsc_csr_interrupt_channel(fd, 0, &(data->int_channel)); |
|
5122 xprintf(fd, ", .update = "); |
|
5123 write_struct_psif_epsc_csr_update(fd, 0, &(data->update)); |
|
5124 xprintf(fd, ", .uf_ctrl = "); |
|
5125 write_struct_psif_epsc_csr_uf_ctrl(fd, 0, &(data->uf_ctrl)); |
|
5126 xprintf(fd, ", .flush_caches = "); |
|
5127 write_struct_psif_epsc_flush_caches(fd, 0, &(data->flush_caches)); |
|
5128 xprintf(fd, ", .pma_counters = "); |
|
5129 write_struct_psif_epsc_csr_pma_counters(fd, 0, &(data->pma_counters)); |
|
5130 xprintf(fd, ", .vimma_ctrl = "); |
|
5131 write_struct_psif_epsc_csr_vimma_ctrl(fd, 0, &(data->vimma_ctrl)); |
|
5132 xprintf(fd, ", .ber = "); |
|
5133 write_struct_psif_epsc_csr_ber_data(fd, 0, &(data->ber)); |
|
5134 xprintf(fd, "}"); |
|
5135 } /* end write_..._psif_epsc_csr_details(psif_epsc_csr_details data) */ |
|
5136 |
|
5137 void write_struct_psif_epsc_csr_req(XFILE *fd, |
|
5138 int network_order, |
|
5139 const struct psif_epsc_csr_req *data) |
|
5140 { |
|
5141 u64 swap[16]; |
|
5142 |
|
5143 if (network_order) { |
|
5144 copy_convert_to_sw(swap, (volatile void *)data, 128); |
|
5145 data = (struct psif_epsc_csr_req *)swap; |
|
5146 network_order = 0; |
|
5147 } |
|
5148 xprintf(fd, "{"); |
|
5149 xprintf(fd, " .crc = "); |
|
5150 write_bits_u16(fd, 16, data->crc); |
|
5151 xprintf(fd, ", .uf = "); |
|
5152 write_bits_u16(fd, 16, data->uf); |
|
5153 xprintf(fd, ", .seq_num = "); |
|
5154 write_bits_u16(fd, 16, data->seq_num); |
|
5155 xprintf(fd, ", .flags = "); |
|
5156 write_enum_psif_epsc_csr_flags(fd, data->flags); |
|
5157 xprintf(fd, ", .opcode = "); |
|
5158 write_enum_psif_epsc_csr_opcode(fd, data->opcode); |
|
5159 xprintf(fd, ", .addr = "); |
|
5160 write_bits_u64(fd, 64, data->addr); |
|
5161 xprintf(fd, ", .u."); |
|
5162 switch (data->opcode) { |
|
5163 case EPSC_SETUP_BASEADDR: |
|
5164 case EPSC_SET_BASEADDR: |
|
5165 case EPSC_SET_BASEADDR_EQ: |
|
5166 xprintf(fd, "base_addr = "); |
|
5167 write_struct_psif_epsc_csr_base_addr(fd, network_order, &(data->u.base_addr)); |
|
5168 break; |
|
5169 case EPSC_MODIFY_QP: |
|
5170 xprintf(fd, "modify_qp = "); |
|
5171 write_struct_psif_epsc_csr_modify_qp(fd, network_order, &(data->u.modify_qp)); |
|
5172 break; |
|
5173 case EPSC_QUERY_QP: |
|
5174 xprintf(fd, "query_qp = "); |
|
5175 write_struct_psif_epsc_csr_query_qp(fd, network_order, &(data->u.query_qp)); |
|
5176 break; |
|
5177 case EPSC_SET_LID: |
|
5178 xprintf(fd, "set_lid = "); |
|
5179 write_struct_psif_epsc_csr_set_lid(fd, network_order, &(data->u.set_lid)); |
|
5180 break; |
|
5181 case EPSC_SET_GID: |
|
5182 xprintf(fd, "set_gid = "); |
|
5183 write_struct_psif_epsc_csr_set_gid(fd, network_order, &(data->u.set_gid)); |
|
5184 break; |
|
5185 case EPSC_SET_EOIB_MAC: |
|
5186 xprintf(fd, "set_eoib_mac = "); |
|
5187 write_struct_psif_epsc_csr_set_eoib_mac(fd, network_order, &(data->u.set_eoib_mac)); |
|
5188 break; |
|
5189 case EPSC_SET_VLINK_STATE: |
|
5190 case EPSC_QUERY_VLINK_STATE: |
|
5191 xprintf(fd, "set_vlink = "); |
|
5192 write_struct_psif_epsc_csr_vlink_state(fd, network_order, &(data->u.set_vlink)); |
|
5193 break; |
|
5194 case EPSC_QUERY_DEVICE: |
|
5195 case EPSC_QUERY_PORT_1: |
|
5196 case EPSC_QUERY_PORT_2: |
|
5197 case EPSC_QUERY_HW_RQ: |
|
5198 case EPSC_QUERY_HW_SQ: |
|
5199 xprintf(fd, "query_hw = "); |
|
5200 write_struct_psif_epsc_csr_query_hw(fd, network_order, &(data->u.query_hw)); |
|
5201 break; |
|
5202 case EPSC_QUERY_PKEY: |
|
5203 case EPSC_QUERY_GID: |
|
5204 xprintf(fd, "query_table = "); |
|
5205 write_struct_psif_epsc_csr_query_table(fd, network_order, &(data->u.query_table)); |
|
5206 break; |
|
5207 case EPSC_MC_ATTACH: |
|
5208 case EPSC_MC_DETACH: |
|
5209 case EPSC_MC_QUERY: |
|
5210 xprintf(fd, "mc = "); |
|
5211 write_struct_psif_epsc_csr_mc(fd, network_order, &(data->u.mc)); |
|
5212 break; |
|
5213 case EPSC_EVENT_ACK: |
|
5214 xprintf(fd, "event = "); |
|
5215 write_struct_psif_epsc_csr_event(fd, network_order, &(data->u.event)); |
|
5216 break; |
|
5217 case EPSC_MODIFY_DEVICE: |
|
5218 xprintf(fd, "device = "); |
|
5219 write_struct_psif_epsc_csr_modify_device(fd, network_order, &(data->u.device)); |
|
5220 break; |
|
5221 case EPSC_MODIFY_PORT_1: |
|
5222 case EPSC_MODIFY_PORT_2: |
|
5223 xprintf(fd, "port = "); |
|
5224 write_struct_psif_epsc_csr_modify_port(fd, network_order, &(data->u.port)); |
|
5225 break; |
|
5226 case EPSC_FW_VERSION: |
|
5227 xprintf(fd, "fw_version = "); |
|
5228 write_struct_psif_epsc_csr_fw_version(fd, network_order, &(data->u.fw_version)); |
|
5229 break; |
|
5230 case EPSC_LOG_CTRL: |
|
5231 xprintf(fd, "log_ctrl = "); |
|
5232 write_struct_psif_epsc_csr_log_ctrl(fd, network_order, &(data->u.log_ctrl)); |
|
5233 break; |
|
5234 case EPSC_A_CONTROL: |
|
5235 xprintf(fd, "epsa_cntrl = "); |
|
5236 write_struct_psif_epsc_csr_epsa_cntrl(fd, network_order, &(data->u.epsa_cntrl)); |
|
5237 break; |
|
5238 case EPSC_A_COMMAND: |
|
5239 xprintf(fd, "epsa_cmd = "); |
|
5240 write_struct_psif_epsc_csr_epsa_cmd(fd, network_order, &(data->u.epsa_cmd)); |
|
5241 break; |
|
5242 case EPSC_CLI_ACCESS: |
|
5243 xprintf(fd, "cli = "); |
|
5244 write_struct_psif_epsc_csr_cli_access(fd, network_order, &(data->u.cli)); |
|
5245 break; |
|
5246 case EPSC_MAD_PROCESS: |
|
5247 xprintf(fd, "mad_process = "); |
|
5248 write_struct_psif_epsc_csr_mad_process(fd, network_order, &(data->u.mad_process)); |
|
5249 break; |
|
5250 case EPSC_MAD_SEND_WR: |
|
5251 xprintf(fd, "mad_send_wr = "); |
|
5252 write_struct_psif_epsc_csr_mad_send_wr(fd, network_order, &(data->u.mad_send_wr)); |
|
5253 break; |
|
5254 case EPSC_QUERY: |
|
5255 xprintf(fd, "query = "); |
|
5256 write_struct_psif_epsc_csr_query(fd, network_order, &(data->u.query)); |
|
5257 break; |
|
5258 case EPSC_SET: |
|
5259 xprintf(fd, "set = "); |
|
5260 write_struct_psif_epsc_csr_set(fd, network_order, &(data->u.set)); |
|
5261 break; |
|
5262 case EPSC_HOST_INT_COMMON_CTRL: |
|
5263 xprintf(fd, "int_common = "); |
|
5264 write_struct_psif_epsc_csr_interrupt_common(fd, network_order, &(data->u.int_common)); |
|
5265 break; |
|
5266 case EPSC_HOST_INT_CHANNEL_CTRL: |
|
5267 xprintf(fd, "int_channel = "); |
|
5268 write_struct_psif_epsc_csr_interrupt_channel(fd, network_order, &(data->u.int_channel)); |
|
5269 break; |
|
5270 case EPSC_UF_CTRL: |
|
5271 xprintf(fd, "uf_ctrl = "); |
|
5272 write_struct_psif_epsc_csr_uf_ctrl(fd, network_order, &(data->u.uf_ctrl)); |
|
5273 break; |
|
5274 case EPSC_FLUSH_CACHES: |
|
5275 xprintf(fd, "flush_caches = "); |
|
5276 write_struct_psif_epsc_flush_caches(fd, network_order, &(data->u.flush_caches)); |
|
5277 break; |
|
5278 case EPSC_PMA_COUNTERS: |
|
5279 xprintf(fd, "pma_counters = "); |
|
5280 write_struct_psif_epsc_csr_pma_counters(fd, network_order, &(data->u.pma_counters)); |
|
5281 break; |
|
5282 case EPSC_NOOP: |
|
5283 case EPSC_TEARDOWN: |
|
5284 case EPSC_TRACE_STATUS: |
|
5285 case EPSC_TRACE_START: |
|
5286 case EPSC_TRACE_STOP: |
|
5287 case EPSC_FLASH_START: |
|
5288 case EPSC_FLASH_INFO: |
|
5289 case EPSC_FLASH_STOP: |
|
5290 case EPSC_GET_SINGLE: |
|
5291 case EPSC_GET_ONE_CSR: |
|
5292 case EPSC_LOG_REQ_NOTIFY: |
|
5293 xprintf(fd, "nodata"); |
|
5294 break; |
|
5295 case EPSC_SET_SINGLE: |
|
5296 case EPSC_SET_ONE_CSR: |
|
5297 case EPSC_UF_RESET: |
|
5298 case EPSC_EVENT_INDEX: |
|
5299 case EPSC_LINK_CNTRL: |
|
5300 xprintf(fd, "single = "); |
|
5301 write_struct_psif_epsc_csr_single(fd, network_order, &(data->u.single)); |
|
5302 break; |
|
5303 default: |
|
5304 xprintf(fd, "opaque = "); |
|
5305 write_struct_psif_epsc_csr_opaque(fd, network_order, &(data->u.opaque)); |
|
5306 break; |
|
5307 } |
|
5308 xprintf(fd, "}"); |
|
5309 } /* end write_..._psif_epsc_csr_req(psif_epsc_csr_req data) */ |
|
5310 |
|
5311 void write_struct_psif_epsc_csr_req_expand(XFILE *fd, |
|
5312 int network_order, |
|
5313 const struct psif_epsc_csr_req *data) |
|
5314 { |
|
5315 u64 swap[16]; |
|
5316 |
|
5317 if (network_order) { |
|
5318 copy_convert_to_sw(swap, (volatile void *)data, 128); |
|
5319 data = (struct psif_epsc_csr_req *)swap; |
|
5320 } |
|
5321 xprintf(fd, "{"); |
|
5322 xprintf(fd, " .crc = "); |
|
5323 write_bits_u16(fd, 16, data->crc); |
|
5324 xprintf(fd, ", .uf = "); |
|
5325 write_bits_u16(fd, 16, data->uf); |
|
5326 xprintf(fd, ", .seq_num = "); |
|
5327 write_bits_u16(fd, 16, data->seq_num); |
|
5328 xprintf(fd, ", .flags = "); |
|
5329 write_enum_psif_epsc_csr_flags(fd, data->flags); |
|
5330 xprintf(fd, ", .opcode = "); |
|
5331 write_enum_psif_epsc_csr_opcode(fd, data->opcode); |
|
5332 xprintf(fd, ", .addr = "); |
|
5333 write_bits_u64(fd, 64, data->addr); |
|
5334 xprintf(fd, ", .u = "); |
|
5335 write_union_psif_epsc_csr_details(fd, 0, &(data->u)); |
|
5336 xprintf(fd, "}"); |
|
5337 } /* end write_..._psif_epsc_csr_req(psif_epsc_csr_req data) */ |
|
5338 |
|
5339 void write_struct_psif_epsc_csr_doorbell(XFILE *fd, |
|
5340 int network_order, |
|
5341 const struct psif_epsc_csr_doorbell *data) |
|
5342 { |
|
5343 u64 swap[1]; |
|
5344 |
|
5345 if (network_order) { |
|
5346 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
5347 data = (struct psif_epsc_csr_doorbell *)swap; |
|
5348 } |
|
5349 xprintf(fd, "{"); |
|
5350 xprintf(fd, " .tail = "); |
|
5351 write_bits_u16(fd, 16, data->tail); |
|
5352 xprintf(fd, ", .data = "); |
|
5353 write_bits_u32(fd, 32, data->data); |
|
5354 xprintf(fd, ", .head = "); |
|
5355 write_bits_u16(fd, 16, data->head); |
|
5356 xprintf(fd, "}"); |
|
5357 } /* end write_..._psif_epsc_csr_doorbell(psif_epsc_csr_doorbell data) */ |
|
5358 |
|
5359 void write_struct_psif_cq_sw(XFILE *fd, |
|
5360 int network_order, |
|
5361 const struct psif_cq_sw *data) |
|
5362 { |
|
5363 u64 swap[1]; |
|
5364 |
|
5365 if (network_order) { |
|
5366 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
5367 data = (struct psif_cq_sw *)swap; |
|
5368 } |
|
5369 xprintf(fd, "{"); |
|
5370 xprintf(fd, ", .head_indx = "); |
|
5371 write_bits_u32(fd, 32, data->head_indx); |
|
5372 xprintf(fd, "}"); |
|
5373 } /* end write_..._psif_cq_sw(psif_cq_sw data) */ |
|
5374 |
|
5375 void write_struct_psif_cq_hw(XFILE *fd, |
|
5376 int network_order, |
|
5377 const struct psif_cq_hw *data) |
|
5378 { |
|
5379 u64 swap[4]; |
|
5380 |
|
5381 if (network_order) { |
|
5382 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
5383 data = (struct psif_cq_hw *)swap; |
|
5384 } |
|
5385 xprintf(fd, "{"); |
|
5386 xprintf(fd, " .max_size = "); |
|
5387 write_bits_u32(fd, 32, data->max_size); |
|
5388 xprintf(fd, ", .int_channel = "); |
|
5389 write_bits_u8(fd, 7, data->int_channel); |
|
5390 xprintf(fd, ", .cq_overrun_event_sent = "); |
|
5391 write_bits_u8(fd, 1, data->cq_overrun_event_sent); |
|
5392 xprintf(fd, ", .prefetch_threshold_log2 = "); |
|
5393 write_bits_u8(fd, 5, data->prefetch_threshold_log2); |
|
5394 xprintf(fd, ", .eps_core = "); |
|
5395 write_enum_psif_eps_a_core(fd, data->eps_core); |
|
5396 xprintf(fd, ", .proxy_en = "); |
|
5397 write_bits_u8(fd, 1, data->proxy_en); |
|
5398 xprintf(fd, ", .size_log2 = "); |
|
5399 write_bits_u8(fd, 5, data->size_log2); |
|
5400 xprintf(fd, ", .valid = "); |
|
5401 write_bits_u8(fd, 1, data->valid); |
|
5402 xprintf(fd, ", .cq_not_state = "); |
|
5403 write_enum_psif_cq_state(fd, data->cq_not_state); |
|
5404 xprintf(fd, ", .sticky = "); |
|
5405 write_bits_u8(fd, 1, data->sticky); |
|
5406 xprintf(fd, ", .mmu_cntx = "); |
|
5407 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx)); |
|
5408 xprintf(fd, ", .base_addr = "); |
|
5409 write_bits_u64(fd, 64, data->base_addr); |
|
5410 xprintf(fd, ", .sequence_number = "); |
|
5411 write_bits_u32(fd, 32, data->sequence_number); |
|
5412 xprintf(fd, ", .tail_indx = "); |
|
5413 write_bits_u32(fd, 32, data->tail_indx); |
|
5414 xprintf(fd, "}"); |
|
5415 } /* end write_..._psif_cq_hw(psif_cq_hw data) */ |
|
5416 |
|
5417 void write_union_psif_seq_num_immdt(XFILE *fd, |
|
5418 int network_order, |
|
5419 const union psif_seq_num_immdt *data) |
|
5420 { |
|
5421 xprintf(fd, "{"); |
|
5422 xprintf(fd, " .cq_sequence_number = "); |
|
5423 write_bits_u32(fd, 32, data->cq_sequence_number); |
|
5424 xprintf(fd, ", .imm = "); |
|
5425 write_bits_u32(fd, 32, data->imm); |
|
5426 xprintf(fd, "}"); |
|
5427 } /* end write_..._psif_seq_num_immdt(psif_seq_num_immdt data) */ |
|
5428 |
|
5429 void write_struct_psif_offload_info(XFILE *fd, |
|
5430 int network_order, |
|
5431 const struct psif_offload_info *data) |
|
5432 { |
|
5433 u64 swap[1]; |
|
5434 |
|
5435 if (network_order) { |
|
5436 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
5437 data = (struct psif_offload_info *)swap; |
|
5438 } |
|
5439 xprintf(fd, "{"); |
|
5440 xprintf(fd, ", .not_written = "); |
|
5441 write_bits_u8(fd, 1, data->not_written); |
|
5442 xprintf(fd, ", .rtp = "); |
|
5443 write_bits_u8(fd, 1, data->rtp); |
|
5444 xprintf(fd, ", .hdr_split_hdr_length = "); |
|
5445 write_bits_u16(fd, 9, data->hdr_split_hdr_length); |
|
5446 xprintf(fd, ", .hdr_split_valid = "); |
|
5447 write_bits_u8(fd, 1, data->hdr_split_valid); |
|
5448 xprintf(fd, ", .is_dr = "); |
|
5449 write_bits_u8(fd, 1, data->is_dr); |
|
5450 xprintf(fd, ", .orig_uf = "); |
|
5451 write_bits_u8(fd, 6, data->orig_uf); |
|
5452 xprintf(fd, ", .l4_checksum_ok = "); |
|
5453 write_bits_u8(fd, 1, data->l4_checksum_ok); |
|
5454 xprintf(fd, ", .l3_checksum_ok = "); |
|
5455 write_bits_u8(fd, 1, data->l3_checksum_ok); |
|
5456 xprintf(fd, ", .packet_classification_udp = "); |
|
5457 write_bits_u8(fd, 1, data->packet_classification_udp); |
|
5458 xprintf(fd, ", .packet_classification_tcp = "); |
|
5459 write_bits_u8(fd, 1, data->packet_classification_tcp); |
|
5460 xprintf(fd, ", .packet_classification_ip6_unsupported_exthdr = "); |
|
5461 write_bits_u8(fd, 1, data->packet_classification_ip6_unsupported_exthdr); |
|
5462 xprintf(fd, ", .packet_classification_arp_reply = "); |
|
5463 write_bits_u8(fd, 1, data->packet_classification_arp_reply); |
|
5464 xprintf(fd, ", .packet_classification_arp = "); |
|
5465 write_bits_u8(fd, 1, data->packet_classification_arp); |
|
5466 xprintf(fd, ", .packet_classification_ip_options = "); |
|
5467 write_bits_u8(fd, 1, data->packet_classification_ip_options); |
|
5468 xprintf(fd, ", .packet_classification_ip_frag = "); |
|
5469 write_bits_u8(fd, 1, data->packet_classification_ip_frag); |
|
5470 xprintf(fd, ", .packet_classification_ipv6 = "); |
|
5471 write_bits_u8(fd, 1, data->packet_classification_ipv6); |
|
5472 xprintf(fd, ", .packet_classification_ipv4 = "); |
|
5473 write_bits_u8(fd, 1, data->packet_classification_ipv4); |
|
5474 xprintf(fd, ", .packet_classification_eth2 = "); |
|
5475 write_bits_u8(fd, 1, data->packet_classification_eth2); |
|
5476 xprintf(fd, ", .rss_hash = "); |
|
5477 write_bits_u32(fd, 32, data->rss_hash); |
|
5478 xprintf(fd, "}"); |
|
5479 } /* end write_..._psif_offload_info(psif_offload_info data) */ |
|
5480 |
|
5481 void write_union_psif_offload_wc_id(XFILE *fd, |
|
5482 int network_order, |
|
5483 const union psif_offload_wc_id *data) |
|
5484 { |
|
5485 u64 swap[1]; |
|
5486 |
|
5487 if (network_order) { |
|
5488 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
5489 data = (union psif_offload_wc_id *)swap; |
|
5490 } |
|
5491 xprintf(fd, "{"); |
|
5492 xprintf(fd, " .wc_id = "); |
|
5493 write_union_psif_completion_wc_id(fd, 0, &(data->wc_id)); |
|
5494 xprintf(fd, ", .offload = "); |
|
5495 write_struct_psif_offload_info(fd, 0, &(data->offload)); |
|
5496 xprintf(fd, "}"); |
|
5497 } /* end write_..._psif_offload_wc_id(psif_offload_wc_id data) */ |
|
5498 |
|
5499 void write_struct_psif_cq_entry(XFILE *fd, |
|
5500 int network_order, |
|
5501 const struct psif_cq_entry *data) |
|
5502 { |
|
5503 u64 swap[8]; |
|
5504 |
|
5505 if (network_order) { |
|
5506 copy_convert_to_sw(swap, (volatile void *)data, 64); |
|
5507 data = (struct psif_cq_entry *)swap; |
|
5508 } |
|
5509 xprintf(fd, "{"); |
|
5510 xprintf(fd, " .wc_id = "); |
|
5511 write_union_psif_completion_wc_id(fd, 0, &(data->wc_id)); |
|
5512 xprintf(fd, ", .qp = "); |
|
5513 write_bits_u32(fd, 24, data->qp); |
|
5514 xprintf(fd, ", .opcode = "); |
|
5515 write_enum_psif_wc_opcode(fd, data->opcode); |
|
5516 xprintf(fd, ", .byte_len = "); |
|
5517 write_bits_u32(fd, 32, data->byte_len); |
|
5518 xprintf(fd, ", .src_qp = "); |
|
5519 write_bits_u32(fd, 24, data->src_qp); |
|
5520 xprintf(fd, ", .status = "); |
|
5521 write_enum_psif_wc_status(fd, data->status); |
|
5522 xprintf(fd, ", .seq_num_imm = "); |
|
5523 write_union_psif_seq_num_immdt(fd, 0, &(data->seq_num_imm)); |
|
5524 xprintf(fd, ", .rss_hash_src = "); |
|
5525 write_enum_psif_rss_hash_source(fd, data->rss_hash_src); |
|
5526 xprintf(fd, ", .vendor_err = "); |
|
5527 write_enum_psif_tsu_error_types(fd, data->vendor_err); |
|
5528 xprintf(fd, ", .error_checksum = "); |
|
5529 write_bits_u16(fd, 16, data->error_checksum); |
|
5530 xprintf(fd, ", .dlid_path_bits = "); |
|
5531 write_bits_u8(fd, 7, data->dlid_path_bits); |
|
5532 xprintf(fd, ", .slid = "); |
|
5533 write_bits_u16(fd, 16, data->slid); |
|
5534 xprintf(fd, ", .port = "); |
|
5535 write_enum_psif_port(fd, data->port); |
|
5536 xprintf(fd, ", .sl = "); |
|
5537 write_bits_u8(fd, 4, data->sl); |
|
5538 xprintf(fd, ", .pkey_indx = "); |
|
5539 write_bits_u16(fd, 9, data->pkey_indx); |
|
5540 xprintf(fd, ", .with_imm = "); |
|
5541 write_bits_u8(fd, 1, data->with_imm); |
|
5542 xprintf(fd, ", .grh = "); |
|
5543 write_bits_u8(fd, 1, data->grh); |
|
5544 xprintf(fd, ", .offload_wc_id = "); |
|
5545 write_union_psif_offload_wc_id(fd, 0, &(data->offload_wc_id)); |
|
5546 xprintf(fd, ", .seq_num = "); |
|
5547 write_bits_u32(fd, 32, data->seq_num); |
|
5548 xprintf(fd, "}"); |
|
5549 } /* end write_..._psif_cq_entry(psif_cq_entry data) */ |
|
5550 |
|
5551 void write_struct_psif_csr_generic(XFILE *fd, |
|
5552 int network_order, |
|
5553 const struct psif_csr_generic *data) |
|
5554 { |
|
5555 u64 swap[1]; |
|
5556 |
|
5557 if (network_order) { |
|
5558 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
5559 data = (struct psif_csr_generic *)swap; |
|
5560 } |
|
5561 xprintf(fd, "{"); |
|
5562 xprintf(fd, " .data = "); |
|
5563 write_bits_u64(fd, 64, data->data); |
|
5564 xprintf(fd, "}"); |
|
5565 } /* end write_..._psif_csr_generic(psif_csr_generic data) */ |
|
5566 |
|
5567 void write_struct_psif_base_addr(XFILE *fd, |
|
5568 int network_order, |
|
5569 const struct psif_base_addr *data) |
|
5570 { |
|
5571 u64 swap[3]; |
|
5572 |
|
5573 if (network_order) { |
|
5574 copy_convert_to_sw(swap, (volatile void *)data, 24); |
|
5575 data = (struct psif_base_addr *)swap; |
|
5576 } |
|
5577 xprintf(fd, "{"); |
|
5578 xprintf(fd, " .address = "); |
|
5579 write_bits_u64(fd, 64, data->address); |
|
5580 xprintf(fd, ", .mmu_context = "); |
|
5581 write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_context)); |
|
5582 xprintf(fd, ", .extent_log2 = "); |
|
5583 write_bits_u8(fd, 5, data->extent_log2); |
|
5584 xprintf(fd, ", .num_entries = "); |
|
5585 write_bits_u32(fd, 32, data->num_entries); |
|
5586 xprintf(fd, "}"); |
|
5587 } /* end write_..._psif_base_addr(psif_base_addr data) */ |
|
5588 |
|
5589 void write_struct_psif_ah(XFILE *fd, |
|
5590 int network_order, |
|
5591 const struct psif_ah *data) |
|
5592 { |
|
5593 u64 swap[4]; |
|
5594 |
|
5595 if (network_order) { |
|
5596 copy_convert_to_sw(swap, (volatile void *)data, 32); |
|
5597 data = (struct psif_ah *)swap; |
|
5598 } |
|
5599 xprintf(fd, "{"); |
|
5600 xprintf(fd, " .grh_remote_gid_0 = "); |
|
5601 write_bits_u64(fd, 64, data->grh_remote_gid_0); |
|
5602 xprintf(fd, ", .grh_remote_gid_1 = "); |
|
5603 write_bits_u64(fd, 64, data->grh_remote_gid_1); |
|
5604 xprintf(fd, ", .remote_lid = "); |
|
5605 write_bits_u16(fd, 16, data->remote_lid); |
|
5606 xprintf(fd, ", .gid_indx = "); |
|
5607 write_bits_u8(fd, 1, data->gid_indx); |
|
5608 xprintf(fd, ", .port = "); |
|
5609 write_enum_psif_port(fd, data->port); |
|
5610 xprintf(fd, ", .loopback = "); |
|
5611 write_enum_psif_loopback(fd, data->loopback); |
|
5612 xprintf(fd, ", .use_grh = "); |
|
5613 write_enum_psif_use_grh(fd, data->use_grh); |
|
5614 xprintf(fd, ", .sl = "); |
|
5615 write_bits_u8(fd, 4, data->sl); |
|
5616 xprintf(fd, ", .grh_hoplmt = "); |
|
5617 write_bits_u8(fd, 8, data->grh_hoplmt); |
|
5618 xprintf(fd, ", .grh_tclass = "); |
|
5619 write_bits_u8(fd, 8, data->grh_tclass); |
|
5620 xprintf(fd, ", .grh_flowlabel = "); |
|
5621 write_bits_u32(fd, 20, data->grh_flowlabel); |
|
5622 xprintf(fd, ", .pd = "); |
|
5623 write_bits_u32(fd, 24, data->pd); |
|
5624 xprintf(fd, ", .ipd = "); |
|
5625 write_bits_u8(fd, 8, data->ipd); |
|
5626 xprintf(fd, ", .local_lid_path = "); |
|
5627 write_bits_u8(fd, 7, data->local_lid_path); |
|
5628 xprintf(fd, "}"); |
|
5629 } /* end write_..._psif_ah(psif_ah data) */ |
|
5630 |
|
5631 void write_struct_psif_csr_ibpr_eoib_mac1(XFILE *fd, |
|
5632 int network_order, |
|
5633 const struct psif_csr_ibpr_eoib_mac1 *data) |
|
5634 { |
|
5635 u64 swap[1]; |
|
5636 |
|
5637 if (network_order) { |
|
5638 copy_convert_to_sw(swap, (volatile void *)data, 8); |
|
5639 data = (struct psif_csr_ibpr_eoib_mac1 *)swap; |
|
5640 } |
|
5641 xprintf(fd, "{"); |
|
5642 xprintf(fd, " .mac1 = "); |
|
5643 write_bits_u64(fd, 48, data->mac1); |
|
5644 xprintf(fd, ", .valid = "); |
|
5645 write_bits_u8(fd, 1, data->valid); |
|
5646 xprintf(fd, "}"); |
|
5647 } /* end write_..._psif_csr_ibpr_eoib_mac1(psif_csr_ibpr_eoib_mac1 data) */ |
|
5648 |
|
5649 #endif /* !defined(PSIF_EXCLUDE_WRITE_STRUCTS) */ |
|
5650 |
|
5651 |
|
5652 #endif /* _PSIF_HW_PRINT_C */ |