components/libusb/ugen/Makefile
changeset 4252 891a844655c4
parent 4196 d697072a92f5
child 4339 6501cf9c29f9
--- a/components/libusb/ugen/Makefile	Mon May 04 18:32:20 2015 -0500
+++ b/components/libusb/ugen/Makefile	Mon May 04 18:34:05 2015 -0500
@@ -46,8 +46,7 @@
 
 ASLR_MODE = $(ASLR_NOT_APPLICABLE)
 
-clobber::
-	$(RM) $(SOURCE_DIR)/.prep
+CLEAN_PATHS +=	$(SOURCE_DIR)/.prep
 
 build:		$(BUILD_32_and_64)