components/python/pylxml/Makefile
changeset 1434 c782e620dd26
parent 1071 cc3ecf7b3dec
child 1890 5a4ef66c42bf
--- a/components/python/pylxml/Makefile	Wed Aug 14 11:12:36 2013 -0600
+++ b/components/python/pylxml/Makefile	Wed Aug 14 10:54:58 2013 -0700
@@ -18,7 +18,7 @@
 #
 # CDDL HEADER END
 #
-# Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved.
 #
 include ../../../make-rules/shared-macros.mk
 
@@ -41,6 +41,8 @@
 include $(WS_TOP)/make-rules/setup.py.mk
 include $(WS_TOP)/make-rules/ips.mk
 
+ASLR_MODE = $(ASLR_NOT_APPLICABLE)
+
 # common targets
 build:		$(BUILD_32_and_64)