24303011 libsif needs sync-up till 1.1 version
authorsreynata <sreyas.natarajan@oracle.com>
Mon, 17 Oct 2016 23:20:28 -0700
changeset 7120 b01185225eaa
parent 7119 2f82d964b8be
child 7121 02252aa4d56c
24303011 libsif needs sync-up till 1.1 version
components/open-fabrics/libsif/Makefile
components/open-fabrics/libsif/include/psifapi/os_header.h
components/open-fabrics/libsif/include/psifapi/psif_api.h
components/open-fabrics/libsif/include/psifapi/psif_endian.h
components/open-fabrics/libsif/include/psifapi/psif_fw_addr.h
components/open-fabrics/libsif/include/psifapi/psif_hw_csr.h
components/open-fabrics/libsif/include/psifapi/psif_hw_data.h
components/open-fabrics/libsif/include/psifapi/psif_hw_data_be.h
components/open-fabrics/libsif/include/psifapi/psif_hw_macro.h
components/open-fabrics/libsif/include/psifapi/psif_hw_print.h
components/open-fabrics/libsif/include/psifapi/psif_hw_setget.h
components/open-fabrics/libsif/include/psifapi/solaris.h
components/open-fabrics/libsif/include/sif/psif_hw_print.c
components/open-fabrics/libsif/include/sif/sif_int_user.h
components/open-fabrics/libsif/include/sif/sif_user.h
components/open-fabrics/libsif/patches/001-libsif-config.patch
components/open-fabrics/libsif/patches/002-libsif-src.patch
components/open-fabrics/libsif/patches/003-Bug23188922.patch
components/open-fabrics/libsif/patches/003-Bug23743649.patch
components/open-fabrics/libsif/patches/004-Bug23743649.patch
--- a/components/open-fabrics/libsif/Makefile	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/Makefile	Mon Oct 17 23:20:28 2016 -0700
@@ -27,19 +27,20 @@
 COMPILER= gcc
 include ../../../make-rules/shared-macros.mk
 
-COMPONENT_NAME=		libsif
-COMPONENT_VERSION=	1.0
-COMPONENT_SRC=		$(COMPONENT_NAME)-$(COMPONENT_VERSION)
-COMPONENT_ARCHIVE=	$(COMPONENT_SRC).tar.gz
+COMPONENT_NAME=         libsif
+COMPONENT_VERSION=      1.1
+COMPONENT_SRC=          $(COMPONENT_NAME)-$(COMPONENT_VERSION)
+COMPONENT_ARCHIVE=      $(COMPONENT_SRC).tar.gz
 COMPONENT_ARCHIVE_HASH= \
-	sha256:501858b4b9d45ebe163d9136f7fb4d08708aaf91cc97c40059ae2a1b4737239d
-COMPONENT_SERVER=      download.oracle.com
+	sha256:ffa472db19614ff27988875ed474e6dcd233273c14dec3ad589ff149288d44b3
+COMPONENT_SERVER=       download.oracle.com
 COMPONENT_ARCHIVE_URL= http://$(COMPONENT_SERVER)/otn-pub/oss/networking/$(COMPONENT_ARCHIVE)
 COMPONENT_BUGDB=	library/ofuv_psif
 
 include ../ofed-component.mk
 
-REMOVE_OLD_SRC= sif.h sif_user.h sif_int_user.h os_header.h psif_api.h psif_endian.h psif_hw_print.h psif_hw_data* psif_hw_setget* psif_hw_macro* kernel_types.h
+REMOVE_OLD_SRC= sif.h sif_user.h sif_int_user.h os_header.h psif_api.h psif_endian.h psif_hw_print.c psif_hw_print.h psif_hw_data* \
+	       	psif_hw_setget* psif_hw_macro* kernel_types.h
 # --disable-libcheck is not a supported option for this component
 DISABLE_LIBCHECK=
 
--- a/components/open-fabrics/libsif/include/psifapi/os_header.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/os_header.h	Mon Oct 17 23:20:28 2016 -0700
@@ -3,8 +3,8 @@
  */
 
 /*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimer.
@@ -14,19 +14,20 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef _OS_HEADER_H
@@ -59,9 +60,37 @@
 #if defined HAVE_DECL_BE64TOH_HTOBE64 && !HAVE_DECL_BE64TOH_HTOBE64
 #define be64toh(x) htonll(x)
 #define htobe64(x) ntohll(x)
+#define be32toh(x) htonl(x)
+#define htobe32(x) ntohl(x)
+#define be16toh(x) htons(x)
+#define htobe16(x) ntohs(x)
+
+#define be64_to_cpu(x) htonll(x)
+#define cpu_to_be64(x) ntohll(x)
+#define be32_to_cpu(x) htonl(x)
+#define cpu_to_be32(x) ntohl(x)
+#define be16_to_cpu(x) htons(x)
+#define cpu_to_be16(x) ntohs(x)
+
+#else
+
+#define be64_to_cpu(x) be64toh(x)
+#define cpu_to_be64(x) htobe64(x)
+#define be32_to_cpu(x) be32toh(x)
+#define cpu_to_be32(x) htobe32(x)
+#define be16_to_cpu(x) be16toh(x)
+#define cpu_to_be16(x) htobe16(x)
+
+#define le64_to_cpu(x) le64toh(x)
+#define cpu_to_le64(x) htole64(x)
+#define le32_to_cpu(x) le32toh(x)
+#define cpu_to_le32(x) htole32(x)
+#define le16_to_cpu(x) le16toh(x)
+#define cpu_to_le16(x) htole16(x)
+
 #endif
 
-#if defined (OS_PRIx64)
+#if defined(OS_PRIx64)
 /* Do not override... */
 #elif defined(_STDINT_H)
 #include <inttypes.h>
--- a/components/open-fabrics/libsif/include/psifapi/psif_api.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/psif_api.h	Mon Oct 17 23:20:28 2016 -0700
@@ -3,8 +3,8 @@
  */
 
 /*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimer.
@@ -14,19 +14,20 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef	_PSIF_API_H
@@ -42,15 +43,15 @@
 #define u16 uint16_t
 #define u32 uint32_t
 #define u64 uint64_t
-typedef uint64_t __be64 ;
-#endif /* __arm__ */ 
+typedef uint64_t __be64;
+#endif /* __arm__ */
 
 #define PSIF_RELEASE_STR "PSIF.ARCH.05.68 revB"
 #define PSIF_MAJOR_VERSION  5
 #define PSIF_MINOR_VERSION 68
 #define PSIF_CHIP_VERSION  2
-#define PSIF_VERSION ((PSIF_MAJOR_VERSION<<8)+PSIF_MINOR_VERSION)
-#define PSIF_API_VERSION(x,y) ((x<<8)+y)
+#define PSIF_VERSION ((PSIF_MAJOR_VERSION<<16)+PSIF_MINOR_VERSION)
+#define PSIF_API_VERSION(x, y) ((x<<16)+y)
 
 #define PSIF_REV2
 
@@ -61,34 +62,33 @@
 /*
  * Update if protocol changes in a backward incompatible way
  */
-#define EPSC_MAJOR_VERSION 0
+#define EPSC_MAJOR_VERSION 2
 
 /*
  * Update when new operations are added or otherwise
  * backward compatible changes are made
  */
-#define EPSC_MINOR_VERSION 101
+#define EPSC_MINOR_VERSION 4
 
 /*
  * Macros for EPSC API #if checking in code
  */
 #define EPSC_VERSION ((EPSC_MAJOR_VERSION<<16)+EPSC_MINOR_VERSION)
-#define EPSC_API_VERSION(x,y) ((x<<16)+y)
+#define EPSC_API_VERSION(x, y) ((x<<16)+y)
 
 /*
  * Macro to conver 16 bit sequence number to 64 bit wire format
  */
 #define EPSC_STATUS_16_to_64(s) ((((u64)(s)) <<  0) | (((u64)(s)) << 16) | \
-                                 (((u64)(s)) << 32) | ((((u64)s)) << 48))
+								(((u64)(s)) << 32) | ((((u64)s)) << 48))
 /*
  * Macros to force layout to match HW implementation
  */
 #define PSIF_PACKED           __attribute__((packed))
-#define PSIF_PACKED_ALIGNED 
-#define PSIF_PACKED_ALIGNED32 
+#define PSIF_PACKED_ALIGNED
+#define PSIF_PACKED_ALIGNED32
 #define PSIF_ALIGNED 
 #define PSIF_ALIGNED8 
-
 #define PSIF_ALIGNED32 
 
 #define PSIF_PF PSIF_VF0
@@ -152,17 +152,30 @@
 /* Index to the error QP. */
 #define QPS_ERROR_INDEX 0
 
+/** \brief Bit definition for degraded mode reporting
+ *  \hideinitializer
+ *  \details
+ *  In the response structure for the mailbox online request from the driver
+ *  this bit is set in the `info` member if the PSIF firmware is already in
+ *  degraded mode. That means that the driver should refrain from doing more
+ *  than just the bare minimum needed to allow updating of the firmware.
+ */
+#define PSIF_INFO_FLAG_DEGRADED (1 << 16)
+
 /** Request value for mailbox register to restart */
 #define MAILBOX_RESTART ((u64)0)
 
 /** Response value for mailbox register on error */
-#define MAILBOX_IN_ERROR 0x0000ffffffff0000
+#define MAILBOX_IN_ERROR 0x0000ffffffff0000ULL
 
 /** Mailbox (response) value for unused VFs */
-#define MAILBOX_NOT_IN_USE 0x0000ffeeeeff0000
+#define MAILBOX_NOT_IN_USE 0x0000ffeeeeff0000ULL
 
 /** Mailbox response value for busy UFs (QP cleanup ongoing) */
-#define MAILBOX_NOT_READY 0x0000ffddddff0000
+#define MAILBOX_NOT_READY 0x0000ffddddff0000ULL
+
+/** Mailbox response value that the doorbell needs to be rung again */
+#define MAILBOX_AGAIN 0x0000ffeddeff0000ULL
 
 /** Highes non-online mailbox sequence number - applied directly after reset */
 #define MAILBOX_SEQ_SET_PROTOCOL ((u16)0x7fff)
--- a/components/open-fabrics/libsif/include/psifapi/psif_endian.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/psif_endian.h	Mon Oct 17 23:20:28 2016 -0700
@@ -3,8 +3,8 @@
  */
 
 /*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimer.
@@ -14,19 +14,20 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef	_PSIF_ENDIAN_H
@@ -45,7 +46,6 @@
 #    error "could not determine byte order"
 #  endif
 #else /* defined(__KERNEL__) */
-#  include <assert.h>
 #  include "os_header.h"
 #  if defined(__BYTE_ORDER)
 #    if __BYTE_ORDER == __BIG_ENDIAN
@@ -61,7 +61,7 @@
 #endif /* defined(__KERNEL__) */
 #endif
 
-#if !defined (__KERNEL__)
+#if !defined(__KERNEL__)
 
 #if !defined(__arm__)
 #include <stdlib.h>
@@ -69,41 +69,60 @@
 
 #if defined(HOST_BIG_ENDIAN)
 
-#define copy_convert(dest,src,n) { memcpy((void *)dest, (void const *)(src), n); wmb(); }
-#define copy_convert_to_hw(dest,src,n) copy_convert(dest,src,n)
-#define copy_convert_to_sw(dest,src,n) copy_convert(dest,src,n)
+#define copy_convert(dest, src, n) { memcpy((void *)dest, (void const *)(src), n); wmb(); }
+#define copy_convert_to_hw(dest, src, n) copy_convert(dest, src, n)
+#define copy_convert_to_sw(dest, src, n) copy_convert(dest, src, n)
 
 #else /* HOST_LITTLE_ENDIAN */
 
 #if defined(__arm__)
-#include <assert.h>
 #include <stdint.h>
 #include "epsfw_misc.h"
 #define htobe64(x) eps_htobe64(x)
+#define htobe32(x) eps_htobe32(x)
+#define htobe16(x) eps_htobe16(x)
+#define be64toh(x) eps_be64toh(x)
+#define be32toh(x) eps_be32toh(x)
+#define be16toh(x) eps_be16toh(x)
+
+#define cpu_to_be64(x) htobe64(x)
+#define cpu_to_be32(x) htobe32(x)
+#define cpu_to_be16(x) htobe16(x)
+#define be64_to_cpu(x) be64toh(x)
+#define be32_to_cpu(x) be32toh(x)
+#define be16_to_cpu(x) be16toh(x)
+
 #define u64 uint64_t
 
-static inline void __DSB(void) {
-    /* __dsb() doesn't serve as sequence point in armcc so adding
-     * __schedule_barrier() around it to force the compiler to see it as a
-     * sequence point */
-    __schedule_barrier();
-    __dsb(0xf);
-    __schedule_barrier();
+static inline void __DSB(void)
+{
+/* __dsb() doesn't serve as sequence point in armcc so adding
+ * __schedule_barrier() around it to force the compiler to see it as a
+ * sequence point
+ */
+__schedule_barrier();
+__dsb(0xf);
+__schedule_barrier();
 }
-#define wmb() __DSB();
+#define wmb() __DSB()
 
 /*
  * Alternatively, use this one as barrier?
- * #define wmb() __memory_changed();
+ * #define wmb() __memory_changed()
  */
 #endif /* __arm__ */
 
+/*
+ * assertions:
+ * - dest and src are 8 bytes aligned
+ * - n is an integer multiple of 8
+ */
 static inline void _copy_convert(void *dest, void const *src, size_t n)
 {
-	int           i, words = n / 8;
-	assert((n % 8) == 0);
+	int i, words = n / 8;
 	volatile u64       *dp = (volatile u64       *) dest;
 	const volatile u64 *sp = (const volatile u64 *) src;
+
 	for (i = 0; i < words; i++) {
 		*dp++ = htobe64(*sp);
 		sp++;
@@ -111,12 +130,17 @@
 	wmb();
 }
 
+/*
+ * assertions:
+ * - dest and src are 8 bytes aligned
+ * - n is an integer multiple of 8
+ */
 static inline void _copy_convert_to_hw(volatile void *dest, void const *src, size_t n)
 {
-	int           i, words = n / 8;
-	assert((n % 8) == 0);
+	int i, words = n / 8;
 	volatile u64 *dp = (volatile u64 *) dest;
 	const u64    *sp = (const u64    *) src;
+
 	for (i = 0; i < words; i++) {
 		*dp++ = htobe64(*sp);
 		sp++;
@@ -124,12 +148,17 @@
 	wmb();
 }
 
+/*
+ * assertions:
+ * - dest and src are 8 bytes aligned
+ * - n is an integer multiple of 8
+ */
 static inline void _copy_convert_to_sw(void *dest, volatile void const *src, size_t n)
 {
-	int           i, words = n / 8;
-	assert((n % 8) == 0);
+	int i, words = n / 8;
 	u64                *dp = (u64                *) dest;
 	const volatile u64 *sp = (const volatile u64 *) src;
+
 	for (i = 0; i < words; i++) {
 		*dp++ = htobe64(*sp);
 		sp++;
@@ -137,9 +166,9 @@
 	wmb();
 }
 
-#define copy_convert(dest,src,n) _copy_convert(dest,src,n)
-#define copy_convert_to_hw(dest,src,n) _copy_convert_to_hw(dest,src,n)
-#define copy_convert_to_sw(dest,src,n) _copy_convert_to_sw(dest,src,n)
+#define copy_convert(dest, src, n) _copy_convert(dest, src, n)
+#define copy_convert_to_hw(dest, src, n) _copy_convert_to_hw(dest, src, n)
+#define copy_convert_to_sw(dest, src, n) _copy_convert_to_sw(dest, src, n)
 
 #endif /* HOST_ENDIAN */
 #endif /* !__KERNEL__ */
--- a/components/open-fabrics/libsif/include/psifapi/psif_fw_addr.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/psif_fw_addr.h	Mon Oct 17 23:20:28 2016 -0700
@@ -3,8 +3,8 @@
  */
 
 /*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimer.
@@ -14,19 +14,20 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef	_PSIF_FW_ADDR_H
--- a/components/open-fabrics/libsif/include/psifapi/psif_hw_csr.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_csr.h	Mon Oct 17 23:20:28 2016 -0700
@@ -3,8 +3,8 @@
  */
 
 /*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimer.
@@ -14,19 +14,20 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef	_PSIF_HW_CSR_H
@@ -41,7 +42,7 @@
 enum psif_csr_map {
 	PSIF_CSR_ADDR_BASE_ADDR_ATSP                 = 0x5248,
 	PSIF_CSR_ADDR_BASE_ADDR_AH                   = 0x55948,
-	PSIF_CSR_ADDR_BASE_ADDR_QP	             = 0x55960,
+	PSIF_CSR_ADDR_BASE_ADDR_QP                   = 0x55960,
 	PSIF_CSR_ADDR_BASE_ADDR_SQ_CMPL              = 0x59d68,
 	PSIF_CSR_ADDR_BASE_ADDR_KEY                  = 0x59d80,
 	PSIF_CSR_ADDR_BASE_ADDR_RQSP                 = 0x59e08,
@@ -54,7 +55,7 @@
 	PSIF_CSR_ADDR_BASE_ADDR_SQ_TVL               = 0xc5388,
 	PSIF_CSR_ADDR_BASE_ADDR_CQ_SW                = 0xcd7a0,
 	PSIF_CSR_ADDR_BASE_ADDR_CQ_HW                = 0xcd7b8,
-    PSIF_CSR_ADDR_END                            = 0xce9f0
+	PSIF_CSR_ADDR_END                            = 0xce9f0
 }; /* enum psif_csr_map */
 
 /* The psif base address setup access ids as offset in a struct */
@@ -84,20 +85,27 @@
 	/* HW:TSU_DSCR_RQ_BASE_ADDR_HW_0 -> struct base_addr_rq_hw [165 bits] */
 	__be64 ingenting_09[((0x59e38 - 0x59e20) / sizeof(__be64)) - 3];
 	__be64 base_addr_rq_hw[3];	 /* Offset  0x59e38 */
-	/* HW:TSU_IBPR_P1_EOIB_MAC1 SW:ibpr_p1_eoib_mac1
-	 * -> struct psif_csr_ibpr_p1_eoib_mac1 [64 bits] */
+	/*
+	 * HW:TSU_IBPR_P1_EOIB_MAC1 SW:ibpr_p1_eoib_mac1
+	 * -> struct psif_csr_ibpr_p1_eoib_mac1 [64 bits]
+	 */
 	__be64 ingenting_10[((0xbfcb8 - 0x59e38) / sizeof(__be64)) - 1];
 	__be64 ibpr_p1_eoib_mac1;	 /* Offset  0xbfcb8 */
-	/* HW:TSU_IBPR_P1_EOIB_MAC2 SW:ibpr_p1_eoib_mac2
-	 * -> struct psif_csr_ibpr_p1_eoib_mac2 [64 bits] */
+	/*
+	 * HW:TSU_IBPR_P1_EOIB_MAC2 SW:ibpr_p1_eoib_mac2
+	 * -> struct psif_csr_ibpr_p1_eoib_mac2 [64 bits]
+	 */
 	__be64 ingenting_11[((0xbfcc0 - 0xbfcb8) / sizeof(__be64)) - 1];
 	__be64 ibpr_p1_eoib_mac2;	 /* Offset  0xbfcc0 */
-	/* HW:TSU_IBPR_P2_EOIB_MAC1 SW:ibpr_p2_eoib_mac1
-	 * -> struct psif_csr_ibpr_p2_eoib_mac1 [64 bits] */
+	/*
+	 * HW:TSU_IBPR_P2_EOIB_MAC1 SW:ibpr_p2_eoib_mac1
+	 * -> struct psif_csr_ibpr_p2_eoib_mac1 [64 bits]
+	 */
 	__be64 ingenting_12[((0xbfcc8 - 0xbfcc0) / sizeof(__be64)) - 1];
 	__be64 ibpr_p2_eoib_mac1;	 /* Offset  0xbfcc8 */
 	/* HW:TSU_IBPR_P2_EOIB_MAC2 SW:ibpr_p2_eoib_mac2
-	 * -> struct psif_csr_ibpr_p2_eoib_mac2 [64 bits] */
+	 * -> struct psif_csr_ibpr_p2_eoib_mac2 [64 bits]
+	 */
 	__be64 ingenting_13[((0xbfcd0 - 0xbfcc8) / sizeof(__be64)) - 1];
 	__be64 ibpr_p2_eoib_mac2;	 /* Offset  0xbfcd0 */
 	/* HW:TSU_SQS_SQ_BASE_ADDR_SW_0 -> struct base_addr_sq_sw [165 bits] */
--- a/components/open-fabrics/libsif/include/psifapi/psif_hw_data.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_data.h	Mon Oct 17 23:20:28 2016 -0700
@@ -3,8 +3,8 @@
  */
 
 /*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimer.
@@ -14,19 +14,20 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef	_PSIF_HW_DATA_H
@@ -47,72 +48,122 @@
 
 /* Extent of all psif enums */
 enum psif_enum_extent {
-	PSIF_MMU_TRANSLATION_EXTENT	 = 0x8,
-	PSIF_PAGE_SIZE_EXTENT	 = 0xf,
-	PSIF_WR_TYPE_EXTENT	 = 0x8f,
-	PSIF_PORT_EXTENT	 = 0x2,
-	PSIF_USE_AH_EXTENT	 = 0x2,
-	PSIF_TSU_QOS_EXTENT	 = 0x2,
-	PSIF_WC_OPCODE_EXTENT	 = 0x83,
-	PSIF_WC_STATUS_EXTENT	 = 0x16,
-	PSIF_TSL_QP_WR_EXTENT	 = 0x10,
-	PSIF_TABLE_LEVEL_EXTENT	 = 0x6,
-	IB_OPCODE_EXTENT	 = 0xca,
-	PSIF_RB_TYPE_EXTENT	 = 0x7,
-	PSIF_EPS_A_CORE_EXTENT	 = 0x4,
-	PSIF_QP_STATE_EXTENT	 = 0x8,
-	PSIF_CMPL_OUTSTANDING_ERROR_EXTENT	 = 0xa,
-	PSIF_EXPECTED_OP_EXTENT	 = 0x4,
-	PSIF_MIGRATION_EXTENT	 = 0x4,
-	PSIF_QP_TRANS_EXTENT	 = 0x8,
-	PSIF_BOOL_EXTENT	 = 0x2,
-	PSIF_EOIB_TYPE_EXTENT	 = 0x4,
-	PSIF_COMM_LIVE_EXTENT	 = 0x2,
-	PSIF_PATH_MTU_EXTENT	 = 0x8,
-	PSIF_USE_GRH_EXTENT	 = 0x2,
-	PSIF_LOOPBACK_EXTENT	 = 0x2,
-	PSIF_PORT_SPEED_EXTENT	 = 0x21,
-	PSIF_PCIE_WR_OFFS_EXTENT	 = 0x1000,
-	PSIF_QP_COMMAND_EXTENT	 = 0x4,
-	PSIF_SIBS_MBOX_TYPE_EXTENT	 = 0x2,
-	PSIF_MBOX_TYPE_EXTENT	 = 0x6,
-	PSIF_DMA_VT_KEY_STATES_EXTENT	 = 0x4,
-	PSIF_FLASH_IMAGE_TYPE_EXTENT	 = 0x5,
-	PSIF_EVENT_EXTENT	 = 0x11,
-	PSIF_TSU_ERROR_TYPES_EXTENT	 = 0x8c,
-	PSIF_EPS_CORE_ID_EXTENT	 = 0x5,
-	PSIF_EPSC_LOG_MODE_EXTENT	 = 0x11,
-	PSIF_EPSC_LOG_LEVEL_EXTENT	 = 0x8,
-	PSIF_EPSC_PORT_STATE_EXTENT	 = 0x6,
-	PSIF_EPSC_PATH_MTU_EXTENT	 = 0x8,
-	PSIF_EPSC_MONITOR_EXTENT	 = 0x5,
-	PSIF_EPSC_INTERRUPT_SOURCE_EXTENT	 = 0x15,
-	PSIF_EPSC_INTERRUPT_PRI_EXTENT	 = 0x4,
-	PSIF_EPSC_ATOMIC_CAP_EXTENT	 = 0x3,
-	PSIF_EPSC_CSR_STATUS_EXTENT	 = 0x100,
-	PSIF_EPSC_CSR_OPCODE_EXTENT	 = 0x4f,
-	PSIF_EPSC_CSR_FLAGS_EXTENT	 = 0x5,
-	PSIF_VLINK_STATE_EXTENT	 = 0x11,
-	PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_EXTENT	 = 0x3,
-	PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_EXTENT	 = 0x11,
-	PSIF_EPSC_CSR_EPSA_COMMAND_EXTENT	 = 0x4,
-	PSIF_EPSA_COMMAND_EXTENT	 = 0xb,
-	PSIF_EPSC_QUERY_OP_EXTENT	 = 0x4b,
-	PSIF_EPSC_CSR_UPDATE_OPCODE_EXTENT	 = 0x8,
-	PSIF_EPSC_FLASH_SLOT_EXTENT	 = 0x6,
-	PSIF_EPSC_UPDATE_SET_EXTENT	 = 0x5,
-	PSIF_EPSC_CSR_UF_CTRL_OPCODE_EXTENT	 = 0x9,
-	PSIF_EPSC_VIMMA_CTRL_OPCODE_EXTENT	 = 0x8,
-	PSIF_EPSC_VIMMA_ADMMODE_EXTENT	 = 0x2,
-	PSIF_EPSC_CSR_PMA_COUNTERS_ENUM_EXTENT	 = 0x17,
-	PSIF_EPSC_CSR_ATOMIC_OP_EXTENT	 = 0x4,
-	PSIF_CQ_STATE_EXTENT	 = 0x4,
-	PSIF_RSS_HASH_SOURCE_EXTENT	 = 0x2
+	PSIF_PORT_SPEED_EXTENT	 = 0x21u,
+	PSIF_EPSC_DEGRADE_CAUSE_EXTENT	 = 0x7u,
+	PSIF_MMU_TRANSLATION_EXTENT	 = 0x8u,
+	PSIF_PAGE_SIZE_EXTENT	 = 0xfu,
+	PSIF_WR_TYPE_EXTENT	 = 0x8fu,
+	PSIF_PORT_EXTENT	 = 0x2u,
+	PSIF_USE_AH_EXTENT	 = 0x2u,
+	PSIF_TSU_QOS_EXTENT	 = 0x2u,
+	PSIF_WC_OPCODE_EXTENT	 = 0x83u,
+	PSIF_WC_STATUS_EXTENT	 = 0x16u,
+	PSIF_TSL_QP_WR_EXTENT	 = 0x10u,
+	PSIF_TABLE_LEVEL_EXTENT	 = 0x6u,
+	IB_OPCODE_EXTENT	 = 0xcau,
+	PSIF_RB_TYPE_EXTENT	 = 0x7u,
+	PSIF_EPS_A_CORE_EXTENT	 = 0x4u,
+	PSIF_QP_STATE_EXTENT	 = 0x8u,
+	PSIF_CMPL_OUTSTANDING_ERROR_EXTENT	 = 0xau,
+	PSIF_EXPECTED_OP_EXTENT	 = 0x4u,
+	PSIF_MIGRATION_EXTENT	 = 0x4u,
+	PSIF_QP_TRANS_EXTENT	 = 0x8u,
+	PSIF_BOOL_EXTENT	 = 0x2u,
+	PSIF_EOIB_TYPE_EXTENT	 = 0x4u,
+	PSIF_COMM_LIVE_EXTENT	 = 0x2u,
+	PSIF_PATH_MTU_EXTENT	 = 0x8u,
+	PSIF_USE_GRH_EXTENT	 = 0x2u,
+	PSIF_LOOPBACK_EXTENT	 = 0x2u,
+	PSIF_PCIE_WR_OFFS_EXTENT	 = 0x1000u,
+	PSIF_QP_COMMAND_EXTENT	 = 0x4u,
+	PSIF_SIBS_MBOX_TYPE_EXTENT	 = 0x2u,
+	PSIF_MBOX_TYPE_EXTENT	 = 0x6u,
+	PSIF_DMA_VT_KEY_STATES_EXTENT	 = 0x4u,
+	PSIF_FLASH_IMAGE_TYPE_EXTENT	 = 0x5u,
+	PSIF_EVENT_EXTENT	 = 0x13u,
+	PSIF_TSU_ERROR_TYPES_EXTENT	 = 0x8cu,
+	PSIF_EPS_CORE_ID_EXTENT	 = 0x5u,
+	PSIF_EPSC_QUERY_PERSISTENT_EXTENT	 = 0x3u,
+	PSIF_EPSC_QUERY_NUM_VFS_MODE_EXTENT	 = 0x3u,
+	PSIF_EPSC_PORT_STATE_EXTENT	 = 0x6u,
+	PSIF_EPSC_PATH_MTU_EXTENT	 = 0x8u,
+	PSIF_EPSC_MONITOR_EXTENT	 = 0x5u,
+	PSIF_EPSC_LOG_MODE_EXTENT	 = 0x11u,
+	PSIF_EPSC_LOG_LEVEL_EXTENT	 = 0x8u,
+	PSIF_EPSC_INTERRUPT_SOURCE_EXTENT	 = 0x15u,
+	PSIF_EPSC_INTERRUPT_PRI_EXTENT	 = 0x4u,
+	PSIF_EPSC_ATOMIC_CAP_EXTENT	 = 0x3u,
+	PSIF_EPSC_CSR_STATUS_EXTENT	 = 0x100u,
+	PSIF_EPSC_CSR_OPCODE_EXTENT	 = 0x50u,
+	PSIF_EPSC_CSR_FLAGS_EXTENT	 = 0x5u,
+	PSIF_VLINK_STATE_EXTENT	 = 0x11u,
+	PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_EXTENT	 = 0x3u,
+	PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_EXTENT	 = 0x11u,
+	PSIF_EPSC_CSR_EPSA_COMMAND_EXTENT	 = 0x4u,
+	PSIF_EPSA_COMMAND_EXTENT	 = 0xcu,
+	PSIF_EPSC_QUERY_OP_EXTENT	 = 0x55u,
+	PSIF_EPSC_CSR_UPDATE_OPCODE_EXTENT	 = 0x8u,
+	PSIF_EPSC_FLASH_SLOT_EXTENT	 = 0x6u,
+	PSIF_EPSC_UPDATE_SET_EXTENT	 = 0x5u,
+	PSIF_EPSC_CSR_UF_CTRL_OPCODE_EXTENT	 = 0x9u,
+	PSIF_EPSC_VIMMA_CTRL_OPCODE_EXTENT	 = 0x8u,
+	PSIF_EPSC_VIMMA_ADMMODE_EXTENT	 = 0x2u,
+	PSIF_EPSC_CSR_PMA_COUNTERS_ENUM_EXTENT	 = 0x17u,
+	PSIF_EPSC_CSR_ATOMIC_OP_EXTENT	 = 0x4u,
+	PSIF_EPSC_CSR_BER_COUNTERS_ENUM_EXTENT	 = 0x5u,
+	PSIF_CQ_STATE_EXTENT	 = 0x4u,
+	PSIF_RSS_HASH_SOURCE_EXTENT	 = 0x2u
 }; /* enum psif_enum_extent [16 bits] */
 
+/*
+ * Should match definitions in ib_verbs.h
+ */
+enum psif_port_speed {
+	PSIF_SPEED_SDR	 = 0x1u,
+	PSIF_SPEED_DDR	 = 0x2u,
+	PSIF_SPEED_QDR	 = 0x4u,
+	PSIF_SPEED_FDR10	 = 0x8u,
+	PSIF_SPEED_FDR	 = 0x10u,
+	PSIF_SPEED_EDR	 = 0x20u,
+	/* Padding out to required bits allocated */
+	PSIF_PORT_SPEED_FIELD_MAX	 = 0xffu
+}; /* enum psif_port_speed [ 8 bits] */
+
+/** Bits describing the cause(s) for EPSC to have entered degraded mode
+ * \par Used in
+ *      response to `EPSC_QUERY_DEGRADED_MODE` and `psif_eq_entry::event_data`
+ * \par Classification
+ *      driver
+ */
+enum psif_epsc_degrade_cause {
+/**< degrade cause: no GUID programmed or not readable */
+
+	DEGRADE_CAUSE_FLAG_MISSING_GUID,
+/**< degrade cause: invalid function name in VPD */
+
+	DEGRADE_CAUSE_FLAG_VPD_INVALID_NAME,
+/**< degrade cause: HW not supported by FW */
+
+	DEGRADE_CAUSE_FLAG_HW_UNSUPPORTED,
+/**< degrade cause: failed MDIO access */
+
+	DEGRADE_CAUSE_FLAG_HW_MDIO_ERROR,
+/**< degrade cause: modify QP timeout */
+
+	DEGRADE_CAUSE_FLAG_MODIFY_QP_TIMEOUT,
+/**< degrade cause: Virtualization mode reconfigured, reset needed */
+
+	DEGRADE_CAUSE_FLAG_VIRTMODE_RECONF,
+/**< degrade cause: no credits for sending multicast packets */
+
+	DEGRADE_CAUSE_FLAG_MCAST_LACK_OF_CREDIT,
+	/* Padding out to required bits allocated */
+	PSIF_EPSC_DEGRADE_CAUSE_FIELD_MAX	 = 0x1fu
+}; /* enum psif_epsc_degrade_cause [ 5 bits] */
+
 /* MMU operation modes. */
 enum psif_mmu_translation {
-	MMU_PASS_THROUGH0,
+	MMU_PASS_THROUGH0	 = 0u,
 	MMU_PASS_THROUGH_PAD,
 	MMU_GVA2GPA_MODE,
 	MMU_GVA2GPA_MODE_PAD,
@@ -127,16 +178,16 @@
  * sizes
  */
 enum psif_page_size {
-	PAGE_SIZE_IA32E_4KB	 = 0,
-	PAGE_SIZE_IA32E_2MB	 = 0x1,
-	PAGE_SIZE_IA32E_1GB	 = 0x2,
-	PAGE_SIZE_S64_8KB	 = 0x8,
-	PAGE_SIZE_S64_64KB	 = 0x9,
-	PAGE_SIZE_S64_512KB	 = 0xa,
-	PAGE_SIZE_S64_4MB	 = 0xb,
-	PAGE_SIZE_S64_32MB	 = 0xc,
-	PAGE_SIZE_S64_2GB	 = 0xd,
-	PAGE_SIZE_S64_16GB	 = 0xe
+	PAGE_SIZE_IA32E_4KB	 = 0u,
+	PAGE_SIZE_IA32E_2MB	 = 0x1u,
+	PAGE_SIZE_IA32E_1GB	 = 0x2u,
+	PAGE_SIZE_S64_8KB	 = 0x8u,
+	PAGE_SIZE_S64_64KB	 = 0x9u,
+	PAGE_SIZE_S64_512KB	 = 0xau,
+	PAGE_SIZE_S64_4MB	 = 0xbu,
+	PAGE_SIZE_S64_32MB	 = 0xcu,
+	PAGE_SIZE_S64_2GB	 = 0xdu,
+	PAGE_SIZE_S64_16GB	 = 0xeu
 }; /* enum psif_page_size [ 4 bits] */
 
 /*
@@ -147,7 +198,7 @@
  * must report the source of a WR to RQS.
  */
 enum psif_wr_type {
-	PSIF_WR_SEND,
+	PSIF_WR_SEND	 = 0u,
 	PSIF_WR_SEND_IMM,
 	PSIF_WR_SPECIAL_QP_SEND,
 	PSIF_WR_QP0_SEND_DR_XMIT,
@@ -163,7 +214,7 @@
 	PSIF_WR_MASK_CMP_SWAP,
 	PSIF_WR_MASK_FETCH_ADD,
 	PSIF_WR_LSO,
-	PSIF_WR_INVALIDATE_RKEY	 = 0x80,
+	PSIF_WR_INVALIDATE_RKEY	 = 0x80u,
 	PSIF_WR_INVALIDATE_LKEY,
 	PSIF_WR_INVALIDATE_BOTH_KEYS,
 	PSIF_WR_INVALIDATE_TLB,
@@ -182,8 +233,8 @@
 
 /* Port number the IB packet is transimitted on. */
 enum psif_port {
-	PORT_1	 = 0,
-	PORT_2	 = 0x1
+	PORT_1	 = 0u,
+	PORT_2	 = 0x1u
 }; /* enum psif_port [ 1 bits] */
 
 /*
@@ -191,8 +242,8 @@
  * information from the QP state in appropriate places.
  */
 enum psif_use_ah {
-	NO_AHA	 = 0,
-	USE_AHA	 = 0x1
+	NO_AHA	 = 0u,
+	USE_AHA	 = 0x1u
 }; /* enum psif_use_ah [ 1 bits] */
 
 /*
@@ -200,8 +251,8 @@
  * QP.
  */
 enum psif_tsu_qos {
-	QOSL_HIGH_BANDWIDTH	 = 0,
-	QOSL_LOW_LATENCY	 = 0x1
+	QOSL_HIGH_BANDWIDTH	 = 0u,
+	QOSL_LOW_LATENCY	 = 0x1u
 }; /* enum psif_tsu_qos [ 1 bits] */
 
 /*
@@ -209,15 +260,15 @@
  * entry is completed.
  */
 enum psif_wc_opcode {
-	PSIF_WC_OPCODE_SEND	 = 0,
-	PSIF_WC_OPCODE_RDMA_WR	 = 0x1,
-	PSIF_WC_OPCODE_RDMA_READ	 = 0x2,
-	PSIF_WC_OPCODE_CMP_SWAP	 = 0x3,
-	PSIF_WC_OPCODE_FETCH_ADD	 = 0x4,
-	PSIF_WC_OPCODE_LSO	 = 0x6,
-	PSIF_WC_OPCODE_MASKED_CMP_SWAP	 = 0x9,
+	PSIF_WC_OPCODE_SEND	 = 0u,
+	PSIF_WC_OPCODE_RDMA_WR	 = 0x1u,
+	PSIF_WC_OPCODE_RDMA_READ	 = 0x2u,
+	PSIF_WC_OPCODE_CMP_SWAP	 = 0x3u,
+	PSIF_WC_OPCODE_FETCH_ADD	 = 0x4u,
+	PSIF_WC_OPCODE_LSO	 = 0x6u,
+	PSIF_WC_OPCODE_MASKED_CMP_SWAP	 = 0x9u,
 	PSIF_WC_OPCODE_MASKED_FETCH_ADD,
-	PSIF_WC_OPCODE_INVALIDATE_RKEY	 = 0x40,
+	PSIF_WC_OPCODE_INVALIDATE_RKEY	 = 0x40u,
 	PSIF_WC_OPCODE_INVALIDATE_LKEY,
 	PSIF_WC_OPCODE_INVALIDATE_BOTH_KEYS,
 	PSIF_WC_OPCODE_INVALIDATE_TLB,
@@ -233,14 +284,14 @@
 	PSIF_WC_OPCODE_INVALIDATE_RB,
 	PSIF_WC_OPCODE_INVALIDATE_XRCSRQ,
 	PSIF_WC_OPCODE_INVALIDATE_SGL_CACHE,
-	PSIF_WC_OPCODE_RECEIVE_SEND	 = 0x80,
+	PSIF_WC_OPCODE_RECEIVE_SEND	 = 0x80u,
 	PSIF_WC_OPCODE_RECEIVE_RDMA_WR_IMM,
 	PSIF_WC_OPCODE_RECEIVE_CONDITIONAL_WR_IMM
 }; /* enum psif_wc_opcode [ 8 bits] */
 
 /* Completion status for this completion. */
 enum psif_wc_status {
-	PSIF_WC_STATUS_SUCCESS,
+	PSIF_WC_STATUS_SUCCESS	 = 0u,
 	PSIF_WC_STATUS_LOC_LEN_ERR,
 	PSIF_WC_STATUS_LOC_QP_OP_ERR,
 	PSIF_WC_STATUS_LOC_EEC_OP_ERR,
@@ -263,20 +314,20 @@
 	PSIF_WC_STATUS_RESP_TIMEOUT_ERR,
 	PSIF_WC_STATUS_GENERAL_ERR,
 	/* Padding out to required bits allocated */
-	PSIF_WC_STATUS_FIELD_MAX	 = 0xff
+	PSIF_WC_STATUS_FIELD_MAX	 = 0xffu
 }; /* enum psif_wc_status [ 8 bits] */
 
 /* TSU Service level required in the QP and WR */
 enum psif_tsl_qp_wr {
 	/* Dataplane traffic separated in 4 TSLs */
-	TSL_DATA,
+	TSL_DATA	 = 0u,
 	TSL_DATA_1,
 	TSL_DATA_2,
 	TSL_DATA_3,
 	/* TSL for privelidge QP */
-	TSL_PRIV	 = 0xe,
+	TSL_PRIV	 = 0xeu,
 	/* Strapped down TSL for testing */
-	TSL_JUNK	 = 0xf
+	TSL_JUNK	 = 0xfu
 }; /* enum psif_tsl_qp_wr [ 4 bits] */
 
 /* MMU table level definition
@@ -285,7 +336,7 @@
  */
 enum psif_table_level {
 	/* */
-	PAGE_LEVEL0	 = 0,
+	PAGE_LEVEL0	 = 0u,
 	PAGE_LEVEL1,
 	PAGE_LEVEL2,
 	PAGE_LEVEL3,
@@ -296,105 +347,105 @@
 
 
 enum ib_opcode {
-	RC_SEND_First	 = 0,
-	RC_SEND_Middle	 = 0x1,
-	RC_SEND_Last	 = 0x2,
-	RC_SEND_Last_Imm	 = 0x3,
-	RC_SEND_Only	 = 0x4,
-	RC_SEND_Only_Imm	 = 0x5,
-	RC_RDMA_WR_First	 = 0x6,
-	RC_RDMA_WR_Middle	 = 0x7,
-	RC_RDMA_WR_Last	 = 0x8,
-	RC_RDMA_WR_Last_Imm	 = 0x9,
-	RC_RDMA_WR_Only	 = 0xa,
-	RC_RDMA_WR_Only_Imm	 = 0xb,
-	RC_RDMA_RD_Req	 = 0xc,
-	RC_RDMA_RD_Resp_First	 = 0xd,
-	RC_RDMA_RD_Resp_Middle	 = 0xe,
-	RC_RDMA_RD_Resp_Last	 = 0xf,
-	RC_RDMA_RD_Resp_Only	 = 0x10,
-	RC_ACK	 = 0x11,
-	RC_Atomic_ACK	 = 0x12,
-	RC_CmpSwap	 = 0x13,
-	RC_FetchAdd	 = 0x14,
-	RC_Reserved	 = 0x15,
-	RC_SEND_Last_Invalid	 = 0x16,
-	RC_SEND_Only_Invalid	 = 0x17,
-	RC_MaskCmpSwap	 = 0x18,
-	RC_MaskFetchAdd	 = 0x19,
-	UC_SEND_First	 = 0x20,
-	UC_SEND_Middle	 = 0x21,
-	UC_SEND_Last	 = 0x22,
-	UC_SEND_Last_Imm	 = 0x23,
-	UC_SEND_Only	 = 0x24,
-	UC_SEND_Only_Imm	 = 0x25,
-	UC_RDMA_WR_First	 = 0x26,
-	UC_RDMA_WR_Middle	 = 0x27,
-	UC_RDMA_WR_Last	 = 0x28,
-	UC_RDMA_WR_Last_Imm	 = 0x29,
-	UC_RDMA_WR_Only	 = 0x2a,
-	UC_RDMA_WR_Only_Imm	 = 0x2b,
-	RD_SEND_First	 = 0x40,
-	RD_SEND_Middle	 = 0x41,
-	RD_SEND_Last	 = 0x42,
-	RD_SEND_Last_Imm	 = 0x43,
-	RD_SEND_Only	 = 0x44,
-	RD_SEND_Only_Imm	 = 0x45,
-	RD_RDMA_WR_First	 = 0x46,
-	RD_RDMA_WR_Middle	 = 0x47,
-	RD_RDMA_WR_Last	 = 0x48,
-	RD_RDMA_WR_Last_Imm	 = 0x49,
-	RD_RDMA_WR_Only	 = 0x4a,
-	RD_RDMA_WR_Only_Imm	 = 0x4b,
-	RD_RDMA_RD_Req	 = 0x4c,
-	RD_RDMA_RD_Resp_First	 = 0x4d,
-	RD_RDMA_RD_Resp_Middle	 = 0x4e,
-	RD_RDMA_RD_Resp_Last	 = 0x4f,
-	RD_RDMA_RD_Resp_Only	 = 0x50,
-	RD_ACK	 = 0x51,
-	RD_Atomic_ACK	 = 0x52,
-	RD_CmpSwap	 = 0x53,
-	RD_FetchAdd	 = 0x54,
-	RD_RESYNC	 = 0x55,
-	UD_SEND_Only	 = 0x64,
-	UD_SEND_Only_Imm	 = 0x65,
-	CNP	 = 0x80,
-	XRC_SEND_First	 = 0xa0,
-	XRC_SEND_Middle	 = 0xa1,
-	XRC_SEND_Last	 = 0xa2,
-	XRC_SEND_Last_Imm	 = 0xa3,
-	XRC_SEND_Only	 = 0xa4,
-	XRC_SEND_Only_Imm	 = 0xa5,
-	XRC_RDMA_WR_First	 = 0xa6,
-	XRC_RDMA_WR_Middle	 = 0xa7,
-	XRC_RDMA_WR_Last	 = 0xa8,
-	XRC_RDMA_WR_Last_Imm	 = 0xa9,
-	XRC_RDMA_WR_Only	 = 0xaa,
-	XRC_RDMA_WR_Only_Imm	 = 0xab,
-	XRC_RDMA_RD_Req	 = 0xac,
-	XRC_RDMA_RD_Resp_First	 = 0xad,
-	XRC_RDMA_RD_Resp_Middle	 = 0xae,
-	XRC_RDMA_RD_Resp_Last	 = 0xaf,
-	XRC_RDMA_RD_Resp_Only	 = 0xb0,
-	XRC_ACK	 = 0xb1,
-	XRC_Atomic_ACK	 = 0xb2,
-	XRC_CmpSwap	 = 0xb3,
-	XRC_FetchAdd	 = 0xb4,
-	XRC_Reserved	 = 0xb5,
-	XRC_SEND_Last_Invalid	 = 0xb6,
-	XRC_SEND_Only_Invalid	 = 0xb7,
-	XRC_MaskCmpSwap	 = 0xb8,
-	XRC_MaskFetchAdd	 = 0xb9,
-	MANSP1_INVALID	 = 0xc0,
-	MANSP1_HOST_READ	 = 0xc1,
-	MANSP1_HOST_WRITE	 = 0xc2,
-	MANSP1_HOST_READ_NO_DMAVT	 = 0xc3,
-	MANSP1_HOST_WRITE_NO_DMAVT	 = 0xc4,
-	MANSP1_INTERNAL_TYPE	 = 0xc5,
-	MANSP1_INTERNAL_TYPE_MMU_BYPASS	 = 0xc6,
-	MANSP1_HOST_CMP_SWAP	 = 0xc7,
-	MANSP1_DR_LOOPBACK	 = 0xc8,
-	MANSP1_ARP_LOOPBACK	 = 0xc9
+	RC_SEND_First	 = 0u,
+	RC_SEND_Middle	 = 0x1u,
+	RC_SEND_Last	 = 0x2u,
+	RC_SEND_Last_Imm	 = 0x3u,
+	RC_SEND_Only	 = 0x4u,
+	RC_SEND_Only_Imm	 = 0x5u,
+	RC_RDMA_WR_First	 = 0x6u,
+	RC_RDMA_WR_Middle	 = 0x7u,
+	RC_RDMA_WR_Last	 = 0x8u,
+	RC_RDMA_WR_Last_Imm	 = 0x9u,
+	RC_RDMA_WR_Only	 = 0xau,
+	RC_RDMA_WR_Only_Imm	 = 0xbu,
+	RC_RDMA_RD_Req	 = 0xcu,
+	RC_RDMA_RD_Resp_First	 = 0xdu,
+	RC_RDMA_RD_Resp_Middle	 = 0xeu,
+	RC_RDMA_RD_Resp_Last	 = 0xfu,
+	RC_RDMA_RD_Resp_Only	 = 0x10u,
+	RC_ACK	 = 0x11u,
+	RC_Atomic_ACK	 = 0x12u,
+	RC_CmpSwap	 = 0x13u,
+	RC_FetchAdd	 = 0x14u,
+	RC_Reserved	 = 0x15u,
+	RC_SEND_Last_Invalid	 = 0x16u,
+	RC_SEND_Only_Invalid	 = 0x17u,
+	RC_MaskCmpSwap	 = 0x18u,
+	RC_MaskFetchAdd	 = 0x19u,
+	UC_SEND_First	 = 0x20u,
+	UC_SEND_Middle	 = 0x21u,
+	UC_SEND_Last	 = 0x22u,
+	UC_SEND_Last_Imm	 = 0x23u,
+	UC_SEND_Only	 = 0x24u,
+	UC_SEND_Only_Imm	 = 0x25u,
+	UC_RDMA_WR_First	 = 0x26u,
+	UC_RDMA_WR_Middle	 = 0x27u,
+	UC_RDMA_WR_Last	 = 0x28u,
+	UC_RDMA_WR_Last_Imm	 = 0x29u,
+	UC_RDMA_WR_Only	 = 0x2au,
+	UC_RDMA_WR_Only_Imm	 = 0x2bu,
+	RD_SEND_First	 = 0x40u,
+	RD_SEND_Middle	 = 0x41u,
+	RD_SEND_Last	 = 0x42u,
+	RD_SEND_Last_Imm	 = 0x43u,
+	RD_SEND_Only	 = 0x44u,
+	RD_SEND_Only_Imm	 = 0x45u,
+	RD_RDMA_WR_First	 = 0x46u,
+	RD_RDMA_WR_Middle	 = 0x47u,
+	RD_RDMA_WR_Last	 = 0x48u,
+	RD_RDMA_WR_Last_Imm	 = 0x49u,
+	RD_RDMA_WR_Only	 = 0x4au,
+	RD_RDMA_WR_Only_Imm	 = 0x4bu,
+	RD_RDMA_RD_Req	 = 0x4cu,
+	RD_RDMA_RD_Resp_First	 = 0x4du,
+	RD_RDMA_RD_Resp_Middle	 = 0x4eu,
+	RD_RDMA_RD_Resp_Last	 = 0x4fu,
+	RD_RDMA_RD_Resp_Only	 = 0x50u,
+	RD_ACK	 = 0x51u,
+	RD_Atomic_ACK	 = 0x52u,
+	RD_CmpSwap	 = 0x53u,
+	RD_FetchAdd	 = 0x54u,
+	RD_RESYNC	 = 0x55u,
+	UD_SEND_Only	 = 0x64u,
+	UD_SEND_Only_Imm	 = 0x65u,
+	CNP	 = 0x80u,
+	XRC_SEND_First	 = 0xa0u,
+	XRC_SEND_Middle	 = 0xa1u,
+	XRC_SEND_Last	 = 0xa2u,
+	XRC_SEND_Last_Imm	 = 0xa3u,
+	XRC_SEND_Only	 = 0xa4u,
+	XRC_SEND_Only_Imm	 = 0xa5u,
+	XRC_RDMA_WR_First	 = 0xa6u,
+	XRC_RDMA_WR_Middle	 = 0xa7u,
+	XRC_RDMA_WR_Last	 = 0xa8u,
+	XRC_RDMA_WR_Last_Imm	 = 0xa9u,
+	XRC_RDMA_WR_Only	 = 0xaau,
+	XRC_RDMA_WR_Only_Imm	 = 0xabu,
+	XRC_RDMA_RD_Req	 = 0xacu,
+	XRC_RDMA_RD_Resp_First	 = 0xadu,
+	XRC_RDMA_RD_Resp_Middle	 = 0xaeu,
+	XRC_RDMA_RD_Resp_Last	 = 0xafu,
+	XRC_RDMA_RD_Resp_Only	 = 0xb0u,
+	XRC_ACK	 = 0xb1u,
+	XRC_Atomic_ACK	 = 0xb2u,
+	XRC_CmpSwap	 = 0xb3u,
+	XRC_FetchAdd	 = 0xb4u,
+	XRC_Reserved	 = 0xb5u,
+	XRC_SEND_Last_Invalid	 = 0xb6u,
+	XRC_SEND_Only_Invalid	 = 0xb7u,
+	XRC_MaskCmpSwap	 = 0xb8u,
+	XRC_MaskFetchAdd	 = 0xb9u,
+	MANSP1_INVALID	 = 0xc0u,
+	MANSP1_HOST_READ	 = 0xc1u,
+	MANSP1_HOST_WRITE	 = 0xc2u,
+	MANSP1_HOST_READ_NO_DMAVT	 = 0xc3u,
+	MANSP1_HOST_WRITE_NO_DMAVT	 = 0xc4u,
+	MANSP1_INTERNAL_TYPE	 = 0xc5u,
+	MANSP1_INTERNAL_TYPE_MMU_BYPASS	 = 0xc6u,
+	MANSP1_HOST_CMP_SWAP	 = 0xc7u,
+	MANSP1_DR_LOOPBACK	 = 0xc8u,
+	MANSP1_ARP_LOOPBACK	 = 0xc9u
 }; /* enum ib_opcode [ 8 bits] */
 
 /*
@@ -402,7 +453,7 @@
  * represents.
  */
 enum psif_rb_type {
-	PSIF_RB_TYPE_INVALID,
+	PSIF_RB_TYPE_INVALID	 = 0u,
 	PSIF_RB_TYPE_DM_PUT,
 	PSIF_RB_TYPE_DM_GET_RESP,
 	PSIF_RB_TYPE_RCV_PROXY_COMPLETION,
@@ -416,7 +467,7 @@
  * PSIF_EPS_A_4
  */
 enum psif_eps_a_core {
-	PSIF_EPS_A_1,
+	PSIF_EPS_A_1	 = 0u,
 	PSIF_EPS_A_2,
 	PSIF_EPS_A_3,
 	PSIF_EPS_A_4
@@ -424,13 +475,13 @@
 
 /* This is the state this QP is in. */
 enum psif_qp_state {
-	PSIF_QP_STATE_RESET	 = 0,
-	PSIF_QP_STATE_INIT	 = 0x1,
-	PSIF_QP_STATE_RTR	 = 0x2,
-	PSIF_QP_STATE_RTS	 = 0x3,
-	PSIF_QP_STATE_SQERR	 = 0x5,
-	PSIF_QP_STATE_ERROR	 = 0x6,
-	PSIF_QP_STATE_INVALID	 = 0x7
+	PSIF_QP_STATE_RESET	 = 0u,
+	PSIF_QP_STATE_INIT	 = 0x1u,
+	PSIF_QP_STATE_RTR	 = 0x2u,
+	PSIF_QP_STATE_RTS	 = 0x3u,
+	PSIF_QP_STATE_SQERR	 = 0x5u,
+	PSIF_QP_STATE_ERROR	 = 0x6u,
+	PSIF_QP_STATE_INVALID	 = 0x7u
 }; /* enum psif_qp_state [ 3 bits] */
 
 /*
@@ -458,10 +509,10 @@
  * last
  */
 enum psif_expected_op {
-	NO_OPERATION_IN_PROGRESS	 = 0,
-	EXPECT_SEND_MIDDLE_LAST	 = 0x1,
-	EXPECT_RDMA_WR_MIDDLE_LAST	 = 0x2,
-	EXPECT_DM_PUT_MIDDLE_LAST	 = 0x3
+	NO_OPERATION_IN_PROGRESS	 = 0u,
+	EXPECT_SEND_MIDDLE_LAST	 = 0x1u,
+	EXPECT_RDMA_WR_MIDDLE_LAST	 = 0x2u,
+	EXPECT_DM_PUT_MIDDLE_LAST	 = 0x3u
 }; /* enum psif_expected_op [ 2 bits] */
 
 /*
@@ -469,7 +520,7 @@
  * states.
  */
 enum psif_migration {
-	APM_OFF,
+	APM_OFF	 = 0u,
 	APM_MIGRATED,
 	APM_REARM,
 	APM_ARMED
@@ -483,20 +534,20 @@
  * specific opcodes.
  */
 enum psif_qp_trans {
-	PSIF_QP_TRANSPORT_RC	 = 0,
-	PSIF_QP_TRANSPORT_UC	 = 0x1,
-	PSIF_QP_TRANSPORT_RD	 = 0x2,
-	PSIF_QP_TRANSPORT_UD	 = 0x3,
-	PSIF_QP_TRANSPORT_RSVD1	 = 0x4,
-	PSIF_QP_TRANSPORT_XRC	 = 0x5,
-	PSIF_QP_TRANSPORT_MANSP1	 = 0x6,
-	PSIF_QP_TRANSPORT_MANSP2	 = 0x7
+	PSIF_QP_TRANSPORT_RC	 = 0u,
+	PSIF_QP_TRANSPORT_UC	 = 0x1u,
+	PSIF_QP_TRANSPORT_RD	 = 0x2u,
+	PSIF_QP_TRANSPORT_UD	 = 0x3u,
+	PSIF_QP_TRANSPORT_RSVD1	 = 0x4u,
+	PSIF_QP_TRANSPORT_XRC	 = 0x5u,
+	PSIF_QP_TRANSPORT_MANSP1	 = 0x6u,
+	PSIF_QP_TRANSPORT_MANSP2	 = 0x7u
 }; /* enum psif_qp_trans [ 3 bits] */
 
 
 enum psif_bool {
-	FALSE	 = 0,
-	TRUE	 = 0x1
+	FALSE	 = 0u,
+	TRUE	 = 0x1u
 }; /* enum psif_bool [ 1 bits] */
 
 /*
@@ -504,7 +555,7 @@
  * EOIB_PARTIAL, EOIB_QKEY_ONLY, EOIB_NONE.
  */
 enum psif_eoib_type {
-	EOIB_FULL,
+	EOIB_FULL	 = 0u,
 	EOIB_PARTIAL,
 	EOIB_QKEY_ONLY,
 	EOIB_NONE
@@ -515,63 +566,49 @@
  * error free when in RTR state.
  */
 enum psif_comm_live {
-	NO_COMM_ESTABLISHED	 = 0,
-	COMM_ESTABLISHED	 = 0x1
+	NO_COMM_ESTABLISHED	 = 0u,
+	COMM_ESTABLISHED	 = 0x1u
 }; /* enum psif_comm_live [ 1 bits] */
 
 /* Definitions for the different supported MTU sizes. */
 enum psif_path_mtu {
-	MTU_INVALID	 = 0,
-	MTU_256B	 = 0x1,
-	MTU_512B	 = 0x2,
-	MTU_1024B	 = 0x3,
-	MTU_2048B	 = 0x4,
-	MTU_4096B	 = 0x5,
-	MTU_10240B	 = 0x6,
-	MTU_XXX	 = 0x7
+	MTU_INVALID	 = 0u,
+	MTU_256B	 = 0x1u,
+	MTU_512B	 = 0x2u,
+	MTU_1024B	 = 0x3u,
+	MTU_2048B	 = 0x4u,
+	MTU_4096B	 = 0x5u,
+	MTU_10240B	 = 0x6u,
+	MTU_XXX	 = 0x7u
 }; /* enum psif_path_mtu [ 3 bits] */
 
 /* Enumeration for using GRH or not. When set GRH should be used. */
 enum psif_use_grh {
-	NO_GRH	 = 0,
-	USE_GRH	 = 0x1
+	NO_GRH	 = 0u,
+	USE_GRH	 = 0x1u
 }; /* enum psif_use_grh [ 1 bits] */
 
 /* Enumeration for loopback indication NO_LOOPBACK = 0 LOOPBACK = 1. */
 enum psif_loopback {
-	NO_LOOPBACK	 = 0,
-	LOOPBACK	 = 0x1
+	NO_LOOPBACK	 = 0u,
+	LOOPBACK	 = 0x1u
 }; /* enum psif_loopback [ 1 bits] */
 
-/*
- * Should match definitions in ib_verbs.h
- */
-enum psif_port_speed {
-	PSIF_SPEED_SDR	 = 0x1,
-	PSIF_SPEED_DDR	 = 0x2,
-	PSIF_SPEED_QDR	 = 0x4,
-	PSIF_SPEED_FDR10	 = 0x8,
-	PSIF_SPEED_FDR	 = 0x10,
-	PSIF_SPEED_EDR	 = 0x20,
-	/* Padding out to required bits allocated */
-	PSIF_PORT_SPEED_FIELD_MAX	 = 0xff
-}; /* enum psif_port_speed [ 8 bits] */
-
 /* Depricated data type... */
 enum psif_pcie_wr_offs {
-	WR_CB_START_OFFS	 = 0,
-	WR_CB_LAST_OFFS	 = 0x140,
-	WR_SQS_DOORBELL_OFFS	 = 0xfc0,
-	WR_CB_CLEAR_OFFS	 = 0xff8,
-	WR_MAX_BAR_OFFS	 = 0xfff
+	WR_CB_START_OFFS	 = 0u,
+	WR_CB_LAST_OFFS	 = 0x140u,
+	WR_SQS_DOORBELL_OFFS	 = 0xfc0u,
+	WR_CB_CLEAR_OFFS	 = 0xff8u,
+	WR_MAX_BAR_OFFS	 = 0xfffu
 }; /* enum psif_pcie_wr_offs [12 bits] */
 
 /* Commands used for modify/query QP. */
 enum psif_qp_command {
-	QP_CMD_INVALID	 = 0,
-	QP_CMD_MODIFY	 = 0x1,
-	QP_CMD_QUERY	 = 0x2,
-	QP_CMD_CHECK_TIMEOUT	 = 0x3
+	QP_CMD_INVALID	 = 0u,
+	QP_CMD_MODIFY	 = 0x1u,
+	QP_CMD_QUERY	 = 0x2u,
+	QP_CMD_CHECK_TIMEOUT	 = 0x3u
 }; /* enum psif_qp_command [ 2 bits] */
 
 
@@ -579,7 +616,7 @@
 	SIBS_MBOX_EPSC,
 	SIBS_MBOX_EPS_MAX,
 	/* Padding out to required bits allocated */
-	PSIF_SIBS_MBOX_TYPE_FIELD_MAX	 = 0xff
+	PSIF_SIBS_MBOX_TYPE_FIELD_MAX	 = 0xffu
 }; /* enum psif_sibs_mbox_type [ 8 bits] */
 
 
@@ -591,7 +628,7 @@
 	MBOX_EPSC,
 	MBOX_EPS_MAX,
 	/* Padding out to required bits allocated */
-	PSIF_MBOX_TYPE_FIELD_MAX	 = 0xff
+	PSIF_MBOX_TYPE_FIELD_MAX	 = 0xffu
 }; /* enum psif_mbox_type [ 8 bits] */
 
 /*
@@ -599,23 +636,23 @@
  * PSIF_DMA_KEY_FREE = 1 PSIF_DMA_KEY_VALID = 2 PSIF_DMA_KEY_MMU_VALID
  */
 enum psif_dma_vt_key_states {
-	PSIF_DMA_KEY_INVALID	 = 0,
-	PSIF_DMA_KEY_FREE	 = 0x1,
-	PSIF_DMA_KEY_VALID	 = 0x2,
-	PSIF_DMA_KEY_MMU_VALID	 = 0x3
+	PSIF_DMA_KEY_INVALID	 = 0u,
+	PSIF_DMA_KEY_FREE	 = 0x1u,
+	PSIF_DMA_KEY_VALID	 = 0x2u,
+	PSIF_DMA_KEY_MMU_VALID	 = 0x3u
 }; /* enum psif_dma_vt_key_states [ 2 bits] */
 
 /**
  * Flash image types. More comming...
  */
 enum psif_flash_image_type {
-	PSIF_IMAGE_INVALID	 = 0,
-	PSIF_IMAGE_BOOT_LOADER	 = 0x1,
-	PSIF_IMAGE_EPS_C_APPLICATION	 = 0x2,
-	PSIF_IMAGE_EPS_A_APPLICATION	 = 0x3,
-	PSIF_IMAGE_DIAGNOSTICS	 = 0x4,
+	PSIF_IMAGE_INVALID	 = 0u,
+	PSIF_IMAGE_BOOT_LOADER	 = 0x1u,
+	PSIF_IMAGE_EPS_C_APPLICATION	 = 0x2u,
+	PSIF_IMAGE_EPS_A_APPLICATION	 = 0x3u,
+	PSIF_IMAGE_DIAGNOSTICS	 = 0x4u,
 	/* Padding out to required bits allocated */
-	PSIF_FLASH_IMAGE_TYPE_FIELD_MAX	 = 0x7fffffff
+	PSIF_FLASH_IMAGE_TYPE_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_flash_image_type [32 bits] */
 
 /** \brief SW EQ event type
@@ -637,7 +674,7 @@
  */
 enum psif_event {
 	/** Event without a reason... */
-	PSIF_EVENT_NO_CHANGE	 = 0,
+	PSIF_EVENT_NO_CHANGE	 = 0u,
 	/** GID table have been updated */
 	PSIF_EVENT_SGID_TABLE_CHANGED,
 	/** PKEY table have been updated by the SM */
@@ -670,8 +707,12 @@
 	PSIF_EVENT_QUEUE_FULL,
 	/** FW entered degraded mode */
 	PSIF_EVENT_DEGRADED_MODE,
+	/** Request a keep-alive message */
+	PSIF_EVENT_EPSC_KEEP_ALIVE,
+	/** FW finished flushing MMU */
+	PSIF_EVENT_EPSC_MMU_FLUSH_DONE,
 	/* Padding out to required bits allocated */
-	PSIF_EVENT_FIELD_MAX	 = 0x7fffffff
+	PSIF_EVENT_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_event [32 bits] */
 
 /*
@@ -733,7 +774,7 @@
  * TSU_CMPL_TIMEOUT_ERR TSU_CMPL_IMPLIED_NAK TSU_CMPL_GHOST_RESP_ERR
  */
 enum psif_tsu_error_types {
-	TSU_NO_ERROR	 = 0,
+	TSU_NO_ERROR	 = 0u,
 	TSU_IBPR_ICRC_ERR,
 	TSU_IBPR_INVALID_PKEY_ERR,
 	TSU_IBPR_INVALID_QP_ERR,
@@ -880,50 +921,50 @@
  * PSIF_EVENT_EPS_A_3 PSIF_EVENT_EPS_A_4 PSIF_EVENT_EPS_C
  */
 enum psif_eps_core_id {
-	PSIF_EVENT_CORE_EPS_A_1,
+	PSIF_EVENT_CORE_EPS_A_1	 = 0u,
 	PSIF_EVENT_CORE_EPS_A_2,
 	PSIF_EVENT_CORE_EPS_A_3,
 	PSIF_EVENT_CORE_EPS_A_4,
 	PSIF_EVENT_CORE_EPS_C,
 	/* Padding out to required bits allocated */
-	PSIF_EPS_CORE_ID_FIELD_MAX	 = 0xf
+	PSIF_EPS_CORE_ID_FIELD_MAX	 = 0xfu
 }; /* enum psif_eps_core_id [ 4 bits] */
 
-
-enum psif_epsc_log_mode {
-/* Logging completely disabled */
-
-	EPSC_LOG_MODE_OFF	 = 0,
-/* See epsfw/src/include/logging.h */
-
-	EPSC_LOG_MODE_SCAT	 = 0x1,
-	EPSC_LOG_MODE_MALLOC	 = 0x2,
-	EPSC_LOG_MODE_LOCAL	 = 0x3,
-/* Redirect logging to host (dma) */
-
-	EPSC_LOG_MODE_HOST	 = 0x4,
-/* Save the set log mode in the flash */
-
-	EPSC_LOG_MODE_SAVE	 = 0x10,
+/**
+ * \brief Discriminator for PSIF_QUERY of persistent values
+ * \details
+ * \par Width
+ *      32 bit
+ * \par Used in
+ * the parameter for the PSIF_QUERY sub-operation EPSC_QUERY_NUM_VFS and EPS_QUERY_JUMBO - set in the index field
+ * \par Classification
+ *      driver
+ */
+enum psif_epsc_query_persistent {
+	EPSC_QUERY_PERSISTENT_STORED,
+	EPSC_QUERY_PERSISTENT_ACTIVE,
+	EPSC_QUERY_PERSISTENT_HW_CAP,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_LOG_MODE_FIELD_MAX	 = 0x7fffffff
-}; /* enum psif_epsc_log_mode [32 bits] */
+	PSIF_EPSC_QUERY_PERSISTENT_FIELD_MAX	 = 0x7fffffffu
+}; /* enum psif_epsc_query_persistent [32 bits] */
 
 /**
- * EPSC_LOG_CTRL
+ * \brief Discriminator for the PSIF_QUER sub-operation EPSC_QUERY_NUM_VFS - obsolete interface
+ * \details
+ * \par Width
+ *      32 bit
+ * \par Used in
+ * the parameter for the PSIF_QUERY sub-operation EPSC_QUERY_NUM_VFS - set in the index field
+ * \par Classification
+ *      driver
  */
-enum psif_epsc_log_level {
-	EPS_LOG_OFF	 = 0,
-	EPS_LOG_FATAL	 = 0x1,
-	EPS_LOG_ERROR	 = 0x2,
-	EPS_LOG_WARN	 = 0x3,
-	EPS_LOG_INFO	 = 0x4,
-	EPS_LOG_DEBUG	 = 0x5,
-	EPS_LOG_TRACE	 = 0x6,
-	EPS_LOG_ALL	 = 0x7,
+enum psif_epsc_query_num_vfs_mode {
+	EPSC_QUERY_NUM_VFS_MODE_PERSISTENT,
+	EPSC_QUERY_NUM_VFS_MODE_CURRENT,
+	EPSC_QUERY_NUM_VFS_MODE_HW_CAP,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_LOG_LEVEL_FIELD_MAX	 = 0x7fffffff
-}; /* enum psif_epsc_log_level [32 bits] */
+	PSIF_EPSC_QUERY_NUM_VFS_MODE_FIELD_MAX	 = 0x7fffffffu
+}; /* enum psif_epsc_query_num_vfs_mode [32 bits] */
 
 /**
  * \brief Port state
@@ -946,19 +987,19 @@
  */
 enum psif_epsc_port_state {
 	/** No change */
-	EPSC_PORT_NOP	 = 0,
+	EPSC_PORT_NOP	 = 0u,
 	/** The port is down. */
-	EPSC_PORT_DOWN	 = 0x1,
+	EPSC_PORT_DOWN	 = 0x1u,
 	/** The port is in init state. */
-	EPSC_PORT_INIT	 = 0x2,
+	EPSC_PORT_INIT	 = 0x2u,
 	/** The port state is armed. */
-	EPSC_PORT_ARMED	 = 0x3,
+	EPSC_PORT_ARMED	 = 0x3u,
 	/** The port is active. */
-	EPSC_PORT_ACTIVE	 = 0x4,
+	EPSC_PORT_ACTIVE	 = 0x4u,
 	/** The port is in deferred active state. */
-	EPSC_PORT_ACTIVE_DEFER	 = 0x5,
+	EPSC_PORT_ACTIVE_DEFER	 = 0x5u,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_PORT_STATE_FIELD_MAX	 = 0x7fffffff
+	PSIF_EPSC_PORT_STATE_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_epsc_port_state [32 bits] */
 
 /**
@@ -980,23 +1021,23 @@
  */
 enum psif_epsc_path_mtu {
 	/** Not a valid MTU. */
-	EPSC_MTU_INVALID	 = 0,
+	EPSC_MTU_INVALID	 = 0u,
 	/** The MTU is 256 bytes. */
-	EPSC_MTU_256B	 = 0x1,
+	EPSC_MTU_256B	 = 0x1u,
 	/** The MTU is 512 bytes. */
-	EPSC_MTU_512B	 = 0x2,
+	EPSC_MTU_512B	 = 0x2u,
 	/** The MTU is 1024 bytes. */
-	EPSC_MTU_1024B	 = 0x3,
+	EPSC_MTU_1024B	 = 0x3u,
 	/** The MTU is 2048 bytes. */
-	EPSC_MTU_2048B	 = 0x4,
+	EPSC_MTU_2048B	 = 0x4u,
 	/** The MTU is 4069 bytes. */
-	EPSC_MTU_4096B	 = 0x5,
+	EPSC_MTU_4096B	 = 0x5u,
 	/** The MTU is 10240 bytes. */
-	EPSC_MTU_10240B	 = 0x6,
+	EPSC_MTU_10240B	 = 0x6u,
 	/** Not a specific MTU. */
-	EPSC_MTU_XXX	 = 0x7,
+	EPSC_MTU_XXX	 = 0x7u,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_PATH_MTU_FIELD_MAX	 = 0x7fffffff
+	PSIF_EPSC_PATH_MTU_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_epsc_path_mtu [32 bits] */
 
 /**
@@ -1021,9 +1062,45 @@
 	PSIF_MONITOR_INACTIVE,
 	PSIF_MONITOR_ERROR,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_MONITOR_FIELD_MAX	 = 0xf
+	PSIF_EPSC_MONITOR_FIELD_MAX	 = 0xfu
 }; /* enum psif_epsc_monitor [ 4 bits] */
 
+
+enum psif_epsc_log_mode {
+/* Logging completely disabled */
+
+	EPSC_LOG_MODE_OFF	 = 0u,
+/* See epsfw/src/include/logging.h */
+
+	EPSC_LOG_MODE_SCAT	 = 0x1u,
+	EPSC_LOG_MODE_MALLOC	 = 0x2u,
+	EPSC_LOG_MODE_LOCAL	 = 0x3u,
+/* Redirect logging to host (dma) */
+
+	EPSC_LOG_MODE_HOST	 = 0x4u,
+/* Save the set log mode in the flash */
+
+	EPSC_LOG_MODE_SAVE	 = 0x10u,
+	/* Padding out to required bits allocated */
+	PSIF_EPSC_LOG_MODE_FIELD_MAX	 = 0x7fffffffu
+}; /* enum psif_epsc_log_mode [32 bits] */
+
+/**
+ * EPSC_LOG_CTRL
+ */
+enum psif_epsc_log_level {
+	EPS_LOG_OFF	 = 0u,
+	EPS_LOG_FATAL	 = 0x1u,
+	EPS_LOG_ERROR	 = 0x2u,
+	EPS_LOG_WARN	 = 0x3u,
+	EPS_LOG_INFO	 = 0x4u,
+	EPS_LOG_DEBUG	 = 0x5u,
+	EPS_LOG_TRACE	 = 0x6u,
+	EPS_LOG_ALL	 = 0x7u,
+	/* Padding out to required bits allocated */
+	PSIF_EPSC_LOG_LEVEL_FIELD_MAX	 = 0x7fffffffu
+}; /* enum psif_epsc_log_level [32 bits] */
+
 /**
  * \brief Interrupt sources definitions as bit indexes.
  * \details
@@ -1128,7 +1205,7 @@
 	/** global atomicity guarantee */
 	EPSC_ATOMIC_GLOB,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_ATOMIC_CAP_FIELD_MAX	 = 0x7fffffff
+	PSIF_EPSC_ATOMIC_CAP_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_epsc_atomic_cap [32 bits] */
 
 /**
@@ -1143,55 +1220,55 @@
  */
 enum psif_epsc_csr_status {
 	/** Successful exit status. */
-	EPSC_SUCCESS	 = 0,
+	EPSC_SUCCESS	 = 0u,
 	/** Key was rejected by service. */
-	EPSC_EKEYREJECTED	 = 0x1,
+	EPSC_EKEYREJECTED	 = 0x1u,
 	/** Cannot assign requested address. */
-	EPSC_EADDRNOTAVAIL	 = 0x2,
+	EPSC_EADDRNOTAVAIL	 = 0x2u,
 	/** Operation not supported on transport endpoint. */
-	EPSC_EOPNOTSUPP	 = 0x3,
+	EPSC_EOPNOTSUPP	 = 0x3u,
 	/** Out of memory. */
-	EPSC_ENOMEM	 = 0x4,
+	EPSC_ENOMEM	 = 0x4u,
 	/** No data available. */
-	EPSC_ENODATA	 = 0x5,
+	EPSC_ENODATA	 = 0x5u,
 	/** Try again. */
-	EPSC_EAGAIN	 = 0x6,
+	EPSC_EAGAIN	 = 0x6u,
 	/** Operation canceled. */
-	EPSC_ECANCELED	 = 0x7,
+	EPSC_ECANCELED	 = 0x7u,
 	/** Connection reset by peer. */
-	EPSC_ECONNRESET	 = 0x8,
+	EPSC_ECONNRESET	 = 0x8u,
 	/** CSR operation failed. */
-	EPSC_ECSR	 = 0x9,
+	EPSC_ECSR	 = 0x9u,
 	/** Modify queue pair error: QP index out of range. */
-	EPSC_MODIFY_QP_OUT_OF_RANGE	 = 0xa,
+	EPSC_MODIFY_QP_OUT_OF_RANGE	 = 0xau,
 	/** Modify queue pair error: QP is invalid. */
-	EPSC_MODIFY_QP_INVALID	 = 0xb,
+	EPSC_MODIFY_QP_INVALID	 = 0xbu,
 	/** Modify queue pair error: failed to change QP attribute. */
-	EPSC_MODIFY_CANNOT_CHANGE_QP_ATTR	 = 0xc,
+	EPSC_MODIFY_CANNOT_CHANGE_QP_ATTR	 = 0xcu,
 	/** Modify queue pair error: failed to change QP due to invalid or not matching state. */
-	EPSC_MODIFY_INVALID_QP_STATE	 = 0xd,
+	EPSC_MODIFY_INVALID_QP_STATE	 = 0xdu,
 	/** Modify queue pair error: failed to change QP due to invalid or not matching migration state. */
-	EPSC_MODIFY_INVALID_MIG_STATE	 = 0xe,
+	EPSC_MODIFY_INVALID_MIG_STATE	 = 0xeu,
 	/** Modify queue pair error: the operation timed out. */
-	EPSC_MODIFY_TIMEOUT	 = 0xf,
+	EPSC_MODIFY_TIMEOUT	 = 0xfu,
 	/** DMA test failure in HEAD. */
-	EPSC_ETEST_HEAD	 = 0x10,
+	EPSC_ETEST_HEAD	 = 0x10u,
 	/** DMA test failure in TAIL. */
-	EPSC_ETEST_TAIL	 = 0x11,
+	EPSC_ETEST_TAIL	 = 0x11u,
 	/** DMA test failure in PATTERN. */
-	EPSC_ETEST_PATTERN	 = 0x12,
+	EPSC_ETEST_PATTERN	 = 0x12u,
 	/** Multicast address already exist. */
-	EPSC_EADDRINUSE	 = 0x13,
+	EPSC_EADDRINUSE	 = 0x13u,
 	/** vHCA out of range */
-	EPSC_EINVALID_VHCA	 = 0x14,
+	EPSC_EINVALID_VHCA	 = 0x14u,
 	/** Port out of range */
-	EPSC_EINVALID_PORT	 = 0x15,
+	EPSC_EINVALID_PORT	 = 0x15u,
 	/** Address out of range */
-	EPSC_EINVALID_ADDRESS	 = 0x16,
+	EPSC_EINVALID_ADDRESS	 = 0x16u,
 	/** Parameter out of range */
-	EPSC_EINVALID_PARAMETER	 = 0x17,
+	EPSC_EINVALID_PARAMETER	 = 0x17u,
 	/** General failure. */
-	EPSC_FAIL	 = 0xff
+	EPSC_FAIL	 = 0xffu
 }; /* enum psif_epsc_csr_status [ 8 bits] */
 
 /**
@@ -1226,11 +1303,11 @@
  */
 enum psif_epsc_csr_opcode {
 	/** Not a valid operation code. */
-	EPSC_NOOP	 = 0,
+	EPSC_NOOP	 = 0u,
 	/** EPS-C ping over mailbox. */
-	EPSC_MAILBOX_PING	 = 0x4c,
+	EPSC_MAILBOX_PING	 = 0x4cu,
 	/** Host patting of EPS-C SW watch-dog. */
-	EPSC_KEEP_ALIVE	 = 0x4d,
+	EPSC_KEEP_ALIVE	 = 0x4du,
 	/** Initial configuration request per UF.
 	 * This request is transferred from the host to the epsc at driver
 	 * attach using an encoding of the physical mailbox register. It
@@ -1263,7 +1340,7 @@
 	 * \par Classification
 	 *      driver
 	 */
-	EPSC_SETUP	 = 0x1,
+	EPSC_SETUP	 = 0x1u,
 	/** Final de-configuration request.
 	 * This request is sent from the host driver to indicate that it has
 	 * cleaned up all queues and flushed caches associated with the current
@@ -1281,10 +1358,10 @@
 	 * \par Classification
 	 *      driver
 	 */
-	EPSC_TEARDOWN	 = 0x36,
+	EPSC_TEARDOWN	 = 0x36u,
 	/** Operation code for a general set request.
 	 * The request usees the same parameter structure as the \ref EPSC_QUERY
-	 * request. Upon recieve the mailbox thread first processes the set request
+	 * request. Upon receive the mailbox thread first processes the set request
 	 * in \ref psif_epsc_csr_query_t::info and then the request in
 	 * \ref psif_epsc_csr_query_t::data. Both members are of type
 	 * \ref psif_epsc_query_req_t and have their own sub-operation codes in
@@ -1306,7 +1383,7 @@
 	 * \par Classification
 	 *      external
 	 */
-	EPSC_SET	 = 0x46,
+	EPSC_SET	 = 0x46u,
 	/** Operation code for a single CSR write request.
 	 * \note
 	 * The request is deprecated and will be removed as soon as all
@@ -1314,7 +1391,7 @@
 	 * \par Return Codes
 	 *      \ref EPSC_EADDRNOTAVAIL
 	 */
-	EPSC_SET_SINGLE	 = 0x2,
+	EPSC_SET_SINGLE	 = 0x2u,
 	/** Operation code for setting an arbitrary CSR.
 	 * \note
 	 * The request is used mainly for debugging tools and will be either removed
@@ -1340,7 +1417,7 @@
 	 * \par Classification
 	 *      driver, development
 	 */
-	EPSC_SET_ONE_CSR	 = 0x3,
+	EPSC_SET_ONE_CSR	 = 0x3u,
 	/** Old operation code to set up a descriptor base address.
 	 * \note
 	 * The request is deprecated and will be removed as soon as all
@@ -1351,7 +1428,7 @@
 	 * \par Classification
 	 *      driver
 	 */
-	EPSC_SETUP_BASEADDR	 = 0x4,
+	EPSC_SETUP_BASEADDR	 = 0x4u,
 	/** Operation code to set up a descriptor base address.
 	 * With this request the driver configures the descriptor base addresses
 	 * of queues, queue pairs and address handles.
@@ -1370,7 +1447,7 @@
 	 * \par Classification
 	 *      driver, development
 	 */
-	EPSC_SET_BASEADDR	 = 0x5,
+	EPSC_SET_BASEADDR	 = 0x5u,
 	/** Operation code to set up an event queue (EQ).
 	 * With this request the driver configures an EQ descriptor base address
 	 * as well as the associated interrupt.
@@ -1389,122 +1466,124 @@
 	 * \par Classification
 	 *      driver
 	 */
-	EPSC_SET_BASEADDR_EQ	 = 0x6,
+	EPSC_SET_BASEADDR_EQ	 = 0x6u,
 	/* Set Local ID for UF (backdoor) */
-	EPSC_SET_LID	 = 0x7,
-	OBSOLETE_1	 = 0x8,
-	OBSOLETE_2	 = 0x9,
+	EPSC_SET_LID	 = 0x7u,
+	OBSOLETE_1	 = 0x8u,
+	OBSOLETE_2	 = 0x9u,
 	/* Set Global ID for UF (backdoor) */
-	EPSC_SET_GID	 = 0xa,
+	EPSC_SET_GID	 = 0xau,
 	/* Set EoIB MAC address (backdoor) */
-	EPSC_SET_EOIB_MAC	 = 0x40,
+	EPSC_SET_EOIB_MAC	 = 0x40u,
 	/* Set Vlink state */
-	EPSC_SET_VLINK_STATE	 = 0xb,
+	EPSC_SET_VLINK_STATE	 = 0xbu,
 	/* Get Vlink state */
-	EPSC_QUERY_VLINK_STATE	 = 0xc,
+	EPSC_QUERY_VLINK_STATE	 = 0xcu,
 	/* Reset UF at startup */
-	EPSC_UF_RESET	 = 0xd,
+	EPSC_UF_RESET	 = 0xdu,
 	/* Modify QP complete w/kick */
-	EPSC_MODIFY_QP	 = 0xe,
-	/* Get single 64bit register - depricated */
-	EPSC_GET_SINGLE	 = 0xf,
+	EPSC_MODIFY_QP	 = 0xeu,
+	/* Get single 64bit register - deprecated */
+	EPSC_GET_SINGLE	 = 0xfu,
 	/* Get one 64bit register using CSR addr */
-	EPSC_GET_ONE_CSR	 = 0x10,
+	EPSC_GET_ONE_CSR	 = 0x10u,
 	/* Query QP sub-entry */
-	EPSC_QUERY_QP	 = 0x11,
+	EPSC_QUERY_QP	 = 0x11u,
 	/** Query HW receive queue. */
-	EPSC_QUERY_HW_RQ	 = 0x42,
+	EPSC_QUERY_HW_RQ	 = 0x42u,
 	/** Query HW SQ. */
-	EPSC_QUERY_HW_SQ	 = 0x43,
+	EPSC_QUERY_HW_SQ	 = 0x43u,
 	/* Non-MAD query device */
-	EPSC_QUERY_DEVICE	 = 0x12,
+	EPSC_QUERY_DEVICE	 = 0x12u,
 	/* Non-MAD query port */
-	EPSC_QUERY_PORT_1	 = 0x13,
-	EPSC_QUERY_PORT_2	 = 0x14,
+	EPSC_QUERY_PORT_1	 = 0x13u,
+	EPSC_QUERY_PORT_2	 = 0x14u,
 	/* Non-MAD SMA attribute query */
-	EPSC_QUERY_PKEY	 = 0x15,
-	EPSC_QUERY_GID	 = 0x16,
+	EPSC_QUERY_PKEY	 = 0x15u,
+	EPSC_QUERY_GID	 = 0x16u,
 	/* Non-MAD SMA attribute setting */
-	EPSC_MODIFY_DEVICE	 = 0x17,
-	EPSC_MODIFY_PORT_1	 = 0x18,
-	EPSC_MODIFY_PORT_2	 = 0x19,
+	EPSC_MODIFY_DEVICE	 = 0x17u,
+	EPSC_MODIFY_PORT_1	 = 0x18u,
+	EPSC_MODIFY_PORT_2	 = 0x19u,
 	/* Local MC subscription handling */
-	EPSC_MC_ATTACH	 = 0x1a,
-	EPSC_MC_DETACH	 = 0x1b,
-	EPSC_MC_QUERY	 = 0x1c,
+	EPSC_MC_ATTACH	 = 0x1au,
+	EPSC_MC_DETACH	 = 0x1bu,
+	EPSC_MC_QUERY	 = 0x1cu,
 	/* Handle asynchronous events */
-	EPSC_EVENT_ACK	 = 0x1d,
-	EPSC_EVENT_INDEX	 = 0x1e,
+	EPSC_EVENT_ACK	 = 0x1du,
+	EPSC_EVENT_INDEX	 = 0x1eu,
 	/* Program flash content */
-	EPSC_FLASH_START	 = 0x1f,
-	EPSC_FLASH_INFO	 = 0x20,
-	EPSC_FLASH_ERASE_SECTOR	 = 0x21,
-	EPSC_FLASH_RD	 = 0x22,
-	EPSC_FLASH_WR	 = 0x23,
-	EPSC_FLASH_CHECK	 = 0x24,
-	EPSC_FLASH_SCAN	 = 0x25,
-	EPSC_FLASH_STOP	 = 0x26,
+	EPSC_FLASH_START	 = 0x1fu,
+	EPSC_FLASH_INFO	 = 0x20u,
+	EPSC_FLASH_ERASE_SECTOR	 = 0x21u,
+	EPSC_FLASH_RD	 = 0x22u,
+	EPSC_FLASH_WR	 = 0x23u,
+	EPSC_FLASH_CHECK	 = 0x24u,
+	EPSC_FLASH_SCAN	 = 0x25u,
+	EPSC_FLASH_STOP	 = 0x26u,
 	/* new update handling */
-	EPSC_UPDATE	 = 0x47,
+	EPSC_UPDATE	 = 0x47u,
 	/* IB packet tracer */
-	EPSC_TRACE_STATUS	 = 0x27,
-	EPSC_TRACE_SETUP	 = 0x28,
-	EPSC_TRACE_START	 = 0x29,
-	EPSC_TRACE_STOP	 = 0x2a,
-	EPSC_TRACE_ACQUIRE	 = 0x2b,
+	EPSC_TRACE_STATUS	 = 0x27u,
+	EPSC_TRACE_SETUP	 = 0x28u,
+	EPSC_TRACE_START	 = 0x29u,
+	EPSC_TRACE_STOP	 = 0x2au,
+	EPSC_TRACE_ACQUIRE	 = 0x2bu,
 	/* Test operations */
-	EPSC_TEST_HOST_RD	 = 0x2c,
-	EPSC_TEST_HOST_WR	 = 0x2d,
+	EPSC_TEST_HOST_RD	 = 0x2cu,
+	EPSC_TEST_HOST_WR	 = 0x2du,
 	/* Get EPS-C version details */
-	EPSC_FW_VERSION	 = 0x2e,
+	EPSC_FW_VERSION	 = 0x2eu,
 	/* Redirection/configuration of EPSC's internal log subsystem */
-	EPSC_LOG_CTRL	 = 0x2f,
-	EPSC_LOG_REQ_NOTIFY	 = 0x30,
+	EPSC_LOG_CTRL	 = 0x2fu,
+	EPSC_LOG_REQ_NOTIFY	 = 0x30u,
 	/* Force & read back link speed */
-	EPSC_LINK_CNTRL	 = 0x31,
+	EPSC_LINK_CNTRL	 = 0x31u,
 	/* EPS-A control & communication (to EPS-C) */
-	EPSC_A_CONTROL	 = 0x33,
+	EPSC_A_CONTROL	 = 0x33u,
 	/* EPS-A targeted commands (to EPS-A) */
-	EPSC_A_COMMAND	 = 0x35,
+	EPSC_A_COMMAND	 = 0x35u,
 	/* Exercise mmu with access from epsc */
-	EPSC_EXERCISE_MMU	 = 0x34,
+	EPSC_EXERCISE_MMU	 = 0x34u,
 	/* Access to EPS-C CLI */
-	EPSC_CLI_ACCESS	 = 0x37,
+	EPSC_CLI_ACCESS	 = 0x37u,
 	/* IB packet proxy to/from host */
-	EPSC_MAD_PROCESS	 = 0x38,
-	EPSC_MAD_SEND_WR	 = 0x39,
+	EPSC_MAD_PROCESS	 = 0x38u,
+	EPSC_MAD_SEND_WR	 = 0x39u,
 	/** Generic query epsc interface. */
-	EPSC_QUERY	 = 0x41,
+	EPSC_QUERY	 = 0x41u,
 	/* Setup interrupt coalescing etc. */
-	EPSC_HOST_INT_COMMON_CTRL	 = 0x44,
-	EPSC_HOST_INT_CHANNEL_CTRL	 = 0x45,
+	EPSC_HOST_INT_COMMON_CTRL	 = 0x44u,
+	EPSC_HOST_INT_CHANNEL_CTRL	 = 0x45u,
 	/** UF control depends on \ref psif_epsc_csr_uf_ctrl_t::opcode. */
-	EPSC_UF_CTRL	 = 0x48,
+	EPSC_UF_CTRL	 = 0x48u,
 	/* Flush MMU and-or PTW Caches */
-	EPSC_FLUSH_CACHES	 = 0x49,
+	EPSC_FLUSH_CACHES	 = 0x49u,
 	/* Query PMA counters - alternative path to sending MAD's */
-	EPSC_PMA_COUNTERS	 = 0x4a,
+	EPSC_PMA_COUNTERS	 = 0x4au,
 	/** VIMMA operations depends on \ref psif_epsc_csr_vimma_ctrl_t::opcode. */
-	EPSC_VIMMA_CTRL	 = 0x4b,
+	EPSC_VIMMA_CTRL	 = 0x4bu,
+	/* EPSC BER (Bit Error Report) Data */
+	EPSC_BER_DATA	 = 0x4eu,
 	/** EOF marker - must be last and highest in this enum type. */
-	EPSC_LAST_OP	 = 0x4e,
+	EPSC_LAST_OP	 = 0x4fu,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_CSR_OPCODE_FIELD_MAX	 = 0xff
+	PSIF_EPSC_CSR_OPCODE_FIELD_MAX	 = 0xffu
 }; /* enum psif_epsc_csr_opcode [ 8 bits] */
 
 /**
  * The eps-c fw csr flags
  */
 enum psif_epsc_csr_flags {
-	EPSC_FL_NONE	 = 0,
+	EPSC_FL_NONE	 = 0u,
 	/* Request notification (interrupt) when completion is ready */
-	EPSC_FL_NOTIFY	 = 0x1,
+	EPSC_FL_NOTIFY	 = 0x1u,
 	/* Privileged QP indicator only valid for query and modify QP */
-	EPSC_FL_PQP	 = 0x2,
+	EPSC_FL_PQP	 = 0x2u,
 	/* Allways report opertion success */
-	EPSC_FL_IGNORE_ERROR	 = 0x4,
+	EPSC_FL_IGNORE_ERROR	 = 0x4u,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_CSR_FLAGS_FIELD_MAX	 = 0xff
+	PSIF_EPSC_CSR_FLAGS_FIELD_MAX	 = 0xffu
 }; /* enum psif_epsc_csr_flags [ 8 bits] */
 
 /*
@@ -1513,33 +1592,33 @@
  * PSIF_LINK_ARM = 8 PSIF_LINK_ACTIVE = 16
  */
 enum psif_vlink_state {
-	PSIF_LINK_DISABLED	 = 0x1,
-	PSIF_LINK_DOWN	 = 0x2,
-	PSIF_LINK_INIT	 = 0x4,
-	PSIF_LINK_ARM	 = 0x8,
-	PSIF_LINK_ACTIVE	 = 0x10
+	PSIF_LINK_DISABLED	 = 0x1u,
+	PSIF_LINK_DOWN	 = 0x2u,
+	PSIF_LINK_INIT	 = 0x4u,
+	PSIF_LINK_ARM	 = 0x8u,
+	PSIF_LINK_ACTIVE	 = 0x10u
 }; /* enum psif_vlink_state [ 5 bits] */
 
 /**
  * EPSC_MODIFY_DEVICE operations
  */
 enum psif_epsc_csr_modify_device_flags {
-	PSIF_DEVICE_MODIFY_SYS_IMAGE_GUID	 = 0x1,
-	PSIF_DEVICE_MODIFY_NODE_DESC	 = 0x2,
+	PSIF_DEVICE_MODIFY_SYS_IMAGE_GUID	 = 0x1u,
+	PSIF_DEVICE_MODIFY_NODE_DESC	 = 0x2u,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_FIELD_MAX	 = 0xffff
+	PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_FIELD_MAX	 = 0xffffu
 }; /* enum psif_epsc_csr_modify_device_flags [16 bits] */
 
 /**
  * EPSC_MODIFY_PORT_{1,2} operations
  */
 enum psif_epsc_csr_modify_port_flags {
-	PSIF_PORT_SHUTDOWN	 = 0x1,
-	PSIF_PORT_INIT_TYPE	 = 0x4,
-	PSIF_PORT_RESET_QKEY_CNTR	 = 0x8,
-	PSIF_PORT_RESET_PKEY_CNTR	 = 0x10,
+	PSIF_PORT_SHUTDOWN	 = 0x1u,
+	PSIF_PORT_INIT_TYPE	 = 0x4u,
+	PSIF_PORT_RESET_QKEY_CNTR	 = 0x8u,
+	PSIF_PORT_RESET_PKEY_CNTR	 = 0x10u,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_FIELD_MAX	 = 0xffff
+	PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_FIELD_MAX	 = 0xffffu
 }; /* enum psif_epsc_csr_modify_port_flags [16 bits] */
 
 
@@ -1549,7 +1628,7 @@
 	EPSC_A_STOP,
 	EPSC_A_STATUS,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_CSR_EPSA_COMMAND_FIELD_MAX	 = 0x7fffffff
+	PSIF_EPSC_CSR_EPSA_COMMAND_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_epsc_csr_epsa_command [32 bits] */
 
 /*
@@ -1566,8 +1645,9 @@
 	EPSA_SKJM_ACC,
 	EPSA_SKJM_MEMACC,
 	EPSA_GET_PROXY_QP_SQ_KEY,
+	EPSA_GENERIC_CMD,
 	/* Padding out to required bits allocated */
-	PSIF_EPSA_COMMAND_FIELD_MAX	 = 0x7fffffff
+	PSIF_EPSA_COMMAND_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_epsa_command [32 bits] */
 
 /**
@@ -1581,86 +1661,90 @@
  *      internal, development
  */
 enum psif_epsc_query_op {
-	/** If initiated from a EPSC_QUERY this operation code will always return zero and report success.
-	 *  In case of a intended set request (EPSC_SET) this operation code ignore the request and return success.
+	/** If initiated from a EPSC_QUERY this operation code will always return zero
+	 *  and report success. In case of a intended set request (EPSC_SET) this
+	 *  operation code ignore the request and return success.
 	 */
-	EPSC_QUERY_BLANK	 = 0,
+	EPSC_QUERY_BLANK	 = 0u,
 	/* Obsolete - use EPSC_QUERY_CAP_VCB_{LO HI} */
-	EPSC_QUERY_CAP_VCB	 = 0x1,
+	EPSC_QUERY_CAP_VCB	 = 0x1u,
 	/* Obsolete - use EPSC_QUERY_CAP_PCB_{LO HI} */
-	EPSC_QUERY_CAP_PCB	 = 0x2,
-	EPSC_QUERY_NUM_UF	 = 0x3,
-	EPSC_QUERY_GID_HI	 = 0x4,
-	EPSC_QUERY_GID_LO	 = 0x5,
-	EPSC_QUERY_P_KEY	 = 0x6,
-	EPSC_QUERY_Q_KEY	 = 0x7,
-	EPSC_QUERY_UF	 = 0x8,
-	EPSC_QUERY_LINK_STATE	 = 0x9,
-	EPSC_QUERY_VHCA_STATE	 = 0xa,
+	EPSC_QUERY_CAP_PCB	 = 0x2u,
+	EPSC_QUERY_NUM_UF	 = 0x3u,
+	EPSC_QUERY_GID_HI	 = 0x4u,
+	EPSC_QUERY_GID_LO	 = 0x5u,
+	EPSC_QUERY_P_KEY	 = 0x6u,
+	EPSC_QUERY_Q_KEY	 = 0x7u,
+	EPSC_QUERY_UF	 = 0x8u,
+	EPSC_QUERY_LINK_STATE	 = 0x9u,
+	EPSC_QUERY_VHCA_STATE	 = 0xau,
 	/* Corresponds to register TSU_HOST_INT_CTRL_ADDR */
-	EPSC_QUERY_INT_COMMON	 = 0xb,
+	EPSC_QUERY_INT_COMMON	 = 0xbu,
 	/* Corresponds to register TSU_HOST_INT_CHAN_CTRL_0 */
-	EPSC_QUERY_INT_CHAN_RATE	 = 0xc,
+	EPSC_QUERY_INT_CHAN_RATE	 = 0xcu,
 	/* Corresponds to register TSU_HOST_INT_CHAN_CTRL_1 */
-	EPSC_QUERY_INT_CHAN_AUSEC	 = 0xd,
+	EPSC_QUERY_INT_CHAN_AUSEC	 = 0xdu,
 	/* Corresponds to register TSU_HOST_INT_CHAN_CTRL_2 */
-	EPSC_QUERY_INT_CHAN_PUSEC	 = 0xe,
+	EPSC_QUERY_INT_CHAN_PUSEC	 = 0xeu,
 	/* Number of VCBs in PCI lo BAR */
-	EPSC_QUERY_CAP_VCB_LO	 = 0xf,
+	EPSC_QUERY_CAP_VCB_LO	 = 0xfu,
 	/* Number of VCBs in PCI hi BAR */
-	EPSC_QUERY_CAP_VCB_HI	 = 0x10,
+	EPSC_QUERY_CAP_VCB_HI	 = 0x10u,
 	/* Number of PCBs mapped to lo BAR VCBs */
-	EPSC_QUERY_CAP_PCB_LO	 = 0x11,
+	EPSC_QUERY_CAP_PCB_LO	 = 0x11u,
 	/* Number of PCBs mapped to hi BAR VCBs */
-	EPSC_QUERY_CAP_PCB_HI	 = 0x12,
-	/* psif_epsc_query_req.index = IB port number [1 2] */
-	EPSC_QUERY_PMA_REDIRECT_QP	 = 0x13,
+	EPSC_QUERY_CAP_PCB_HI	 = 0x12u,
+	/*
+	 * QP number for EPS-C to forward PMA responces to host
+	 * psif_epsc_query_req.index = IB port number [1,2]
+	 */
+	EPSC_QUERY_PMA_REDIRECT_QP	 = 0x13u,
 	/* uptime in seconds */
-	EPSC_QUERY_FW_UPTIME	 = 0x14,
+	EPSC_QUERY_FW_UPTIME	 = 0x14u,
 	/* date the firmware was programmed in epoch time */
-	EPSC_QUERY_FW_PROG_DATE	 = 0x15,
+	EPSC_QUERY_FW_PROG_DATE	 = 0x15u,
 	/* date the firmware was built in epoch time */
-	EPSC_QUERY_FW_BUILD_DATE	 = 0x16,
+	EPSC_QUERY_FW_BUILD_DATE	 = 0x16u,
 	/* current firmware image number (flash slot) */
-	EPSC_QUERY_FW_CURR_IMG	 = 0x17,
+	EPSC_QUERY_FW_CURR_IMG	 = 0x17u,
 	/* oneshot firmware image number (flash slot) */
-	EPSC_QUERY_FW_ONESHOT_IMG	 = 0x18,
+	EPSC_QUERY_FW_ONESHOT_IMG	 = 0x18u,
 	/* autostart firmware image number (flash slot) */
-	EPSC_QUERY_FW_AUTOSTART_IMG	 = 0x19,
+	EPSC_QUERY_FW_AUTOSTART_IMG	 = 0x19u,
 	/* bit field encoding why the FW image was booted */
-	EPSC_QUERY_FW_START_CAUSE	 = 0x1a,
+	EPSC_QUERY_FW_START_CAUSE	 = 0x1au,
 	/* firmware version */
-	EPSC_QUERY_FW_VERSION	 = 0x1b,
+	EPSC_QUERY_FW_VERSION	 = 0x1bu,
 	/* Requester - number of bad response errors. */
-	EPSC_QUERY_SQ_NUM_BRE	 = 0x1c,
+	EPSC_QUERY_SQ_NUM_BRE	 = 0x1cu,
 	/* Requester - number of bad response errors. */
-	EPSC_QUERY_NUM_CQOVF	 = 0x1d,
+	EPSC_QUERY_NUM_CQOVF	 = 0x1du,
 	/* Requester - number of CQEs with status flushed in error. */
-	EPSC_QUERY_SQ_NUM_WRFE	 = 0x1e,
+	EPSC_QUERY_SQ_NUM_WRFE	 = 0x1eu,
 	/* Responder - number of CQEs with status flushed in error. */
-	EPSC_QUERY_RQ_NUM_WRFE	 = 0x1f,
+	EPSC_QUERY_RQ_NUM_WRFE	 = 0x1fu,
 	/* Responder - number of local access errors. */
-	EPSC_QUERY_RQ_NUM_LAE	 = 0x20,
+	EPSC_QUERY_RQ_NUM_LAE	 = 0x20u,
 	/* Responder - number of local protection errors. */
-	EPSC_QUERY_RQ_NUM_LPE	 = 0x21,
+	EPSC_QUERY_RQ_NUM_LPE	 = 0x21u,
 	/* Requester - number of local length errors. */
-	EPSC_QUERY_SQ_NUM_LLE	 = 0x22,
+	EPSC_QUERY_SQ_NUM_LLE	 = 0x22u,
 	/* Responder - number of local length errors. */
-	EPSC_QUERY_RQ_NUM_LLE	 = 0x23,
+	EPSC_QUERY_RQ_NUM_LLE	 = 0x23u,
 	/* Requester - number local QP operation error. */
-	EPSC_QUERY_SQ_NUM_LQPOE	 = 0x24,
+	EPSC_QUERY_SQ_NUM_LQPOE	 = 0x24u,
 	/* Responder - number local QP operation error. */
-	EPSC_QUERY_RQ_NUM_LQPOE	 = 0x25,
+	EPSC_QUERY_RQ_NUM_LQPOE	 = 0x25u,
 	/* Requester - number of NAK-Sequence Error received. */
-	EPSC_QUERY_SQ_NUM_OOS	 = 0x26,
+	EPSC_QUERY_SQ_NUM_OOS	 = 0x26u,
 	/* Responder - number of NAK-Sequence Error sent. */
-	EPSC_QUERY_RQ_NUM_OOS	 = 0x27,
+	EPSC_QUERY_RQ_NUM_OOS	 = 0x27u,
 	/* Requester - number of RNR nak retries exceeded errors. */
-	EPSC_QUERY_SQ_NUM_RREE	 = 0x28,
+	EPSC_QUERY_SQ_NUM_RREE	 = 0x28u,
 	/* Requester - number of transport retries exceeded errors. */
-	EPSC_QUERY_SQ_NUM_TREE	 = 0x29,
+	EPSC_QUERY_SQ_NUM_TREE	 = 0x29u,
 	/* Requester - number of NAK-Remote Access Error received. */
-	EPSC_QUERY_SQ_NUM_ROE	 = 0x2a,
+	EPSC_QUERY_SQ_NUM_ROE	 = 0x2au,
 	/*
 	 * Responder - number of NAK-Remote Access Error sent. NAK-Remote Operation
 	 * Error on: 1. Malformed WQE: Responder detected a malformed Receive Queue
@@ -1668,34 +1752,34 @@
 	 * encountered an error, (local to the responder), which prevented it from
 	 * completing the request.
 	 */
-	EPSC_QUERY_RQ_NUM_ROE	 = 0x2b,
+	EPSC_QUERY_RQ_NUM_ROE	 = 0x2bu,
 	/*
 	 * Requester - number of NAK-Remote Access Error received. R_Key Violation:
 	 * Responder detected an invalid R_Key while executing an RDMA Request.
 	 */
-	EPSC_QUERY_SQ_NUM_RAE	 = 0x2c,
+	EPSC_QUERY_SQ_NUM_RAE	 = 0x2cu,
 	/*
 	 * Responder - number of NAK-Remote Access Error sent. R_Key Violation
 	 * Responder detected an R_Key violation while executing an RDMA request.
 	 */
-	EPSC_QUERY_RQ_NUM_RAE	 = 0x2d,
+	EPSC_QUERY_RQ_NUM_RAE	 = 0x2du,
 	/*
 	 * The number of UD packets silently discarded on the receive queue due to
 	 * lack of receive descriptor.
 	 */
-	EPSC_QUERY_RQ_NUM_UDSDPRD	 = 0x2e,
+	EPSC_QUERY_RQ_NUM_UDSDPRD	 = 0x2eu,
 	/*
 	 * The number of UC packets silently discarded on the receive queue due to
 	 * lack of receive descriptor.
 	 */
-	EPSC_QUERY_RQ_NUM_UCSDPRD	 = 0x2f,
+	EPSC_QUERY_RQ_NUM_UCSDPRD	 = 0x2fu,
 	/*
 	 * Requester - number of remote invalid request errors NAK-Invalid Request
 	 * on: 1. Unsupported OpCode: Responder detected an unsupported OpCode. 2.
 	 * Unexpected OpCode: Responder detected an error in the sequence of OpCodes,
 	 * such as a missing Last packet.
 	 */
-	EPSC_QUERY_SQ_NUM_RIRE	 = 0x30,
+	EPSC_QUERY_SQ_NUM_RIRE	 = 0x30u,
 	/*
 	 * Responder - number of remote invalid request errors. NAK may or may not be
 	 * sent. 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD
@@ -1717,67 +1801,91 @@
 	 * bytes 9. Length error: Inbound message exceeded the size supported by the
 	 * CA port.
 	 */
-	EPSC_QUERY_RQ_NUM_RIRE	 = 0x31,
+	EPSC_QUERY_RQ_NUM_RIRE	 = 0x31u,
 	/* Requester - the number of RNR Naks received. */
-	EPSC_QUERY_SQ_NUM_RNR	 = 0x32,
+	EPSC_QUERY_SQ_NUM_RNR	 = 0x32u,
 	/* Responder - the number of RNR Naks sent. */
-	EPSC_QUERY_RQ_NUM_RNR	 = 0x33,
+	EPSC_QUERY_RQ_NUM_RNR	 = 0x33u,
 	/* twoshot firmware image number (flash slot) */
-	EPSC_QUERY_FW_TWOSHOT_IMG	 = 0x34,
+	EPSC_QUERY_FW_TWOSHOT_IMG	 = 0x34u,
 	/* firmware type */
-	EPSC_QUERY_FW_TYPE	 = 0x35,
+	EPSC_QUERY_FW_TYPE	 = 0x35u,
 	/* firmware size */
-	EPSC_QUERY_FW_SIZE	 = 0x36,
+	EPSC_QUERY_FW_SIZE	 = 0x36u,
 	/* firmware slot size (available space for an image) */
-	EPSC_QUERY_FW_SLOT_SIZE	 = 0x37,
+	EPSC_QUERY_FW_SLOT_SIZE	 = 0x37u,
 	/* version of boot loader that has started the application */
-	EPSC_QUERY_BL_VERSION	 = 0x38,
+	EPSC_QUERY_BL_VERSION	 = 0x38u,
 	/* boot loader build date in epoch time format */
-	EPSC_QUERY_BL_BUILD_DATE	 = 0x39,
+	EPSC_QUERY_BL_BUILD_DATE	 = 0x39u,
 	/* only used by EPSC_SET mark a PQP CQ ID as clean (WA bug 3769) */
-	EPSC_QUERY_CLEAN_CQ_ID	 = 0x3a,
+	EPSC_QUERY_CLEAN_CQ_ID	 = 0x3au,
 	/* Number of TSL supported by FW */
-	EPSC_QUERY_CAP_TSL_TX	 = 0x3b,
-	EPSC_QUERY_CAP_TSL_RX	 = 0x3c,
+	EPSC_QUERY_CAP_TSL_TX	 = 0x3bu,
+	EPSC_QUERY_CAP_TSL_RX	 = 0x3cu,
 	/* Reset CBLD Diag counters. Only used by EPSC_SET */
-	EPSC_QUERY_RESET_CBLD_DIAG_COUNTERS	 = 0x3d,
+	EPSC_QUERY_RESET_CBLD_DIAG_COUNTERS	 = 0x3du,
 	/* Max QP index used since power-on or host reset - to optimize WA for HW bug 3251 */
-	EPSC_QUERY_MAX_QP_USED	 = 0x3e,
+	EPSC_QUERY_MAX_QP_USED	 = 0x3eu,
 	/** the UF and QP where modify QP timed out ((uf << 32) | (qp)) */
-	EPSC_QUERY_MODQP_TO_SOURCE	 = 0x3f,
+	EPSC_QUERY_MODQP_TO_SOURCE	 = 0x3fu,
 	/** the debug register when modify QP timed out */
-	EPSC_QUERY_MODQP_TO_DEBUG	 = 0x40,
+	EPSC_QUERY_MODQP_TO_DEBUG	 = 0x40u,
 	/** the bit vector containing the reasons for entering degraded mode */
-	EPSC_QUERY_DEGRADED_CAUSE	 = 0x41,
+	EPSC_QUERY_DEGRADED_CAUSE	 = 0x41u,
 	/** CMPL spin set mode (safe = 1 fast = 0) */
-	EPSC_QUERY_SPIN_SET_CONTROL	 = 0x42,
+	EPSC_QUERY_SPIN_SET_CONTROL	 = 0x42u,
 	/** VPD MAC address */
-	EPSC_QUERY_VPD_MAC	 = 0x43,
+	EPSC_QUERY_VPD_MAC	 = 0x43u,
 	/** VPD part number */
-	EPSC_QUERY_VPD_PART_NUMBER	 = 0x44,
+	EPSC_QUERY_VPD_PART_NUMBER	 = 0x44u,
 	/** VPD revision */
-	EPSC_QUERY_VPD_REVISION	 = 0x45,
+	EPSC_QUERY_VPD_REVISION	 = 0x45u,
 	/** VPD serial number (big endian sub-string) - 8 byte offset in query index */
-	EPSC_QUERY_VPD_SERIAL_NUMBER	 = 0x46,
+	EPSC_QUERY_VPD_SERIAL_NUMBER	 = 0x46u,
 	/** VPD manufacturer = = Oracle Corporation - 8 byte offset in query index */
-	EPSC_QUERY_VPD_MANUFACTURER	 = 0x47,
+	EPSC_QUERY_VPD_MANUFACTURER	 = 0x47u,
+	/** VPD product name (big endian sub-string) - 8 byte offset in query index */
+	EPSC_QUERY_VPD_PRODUCT_NAME	 = 0x4bu,
+	/** VPD Base GUID */
+	EPSC_QUERY_VPD_BASE_GUID	 = 0x4eu,
+	/** PSIF TSU SL and QoS mapping for for QP 0 - port number in query index */
+	EPSC_QUERY_MAP_QP0_TO_TSL	 = 0x52u,
 	/** PSIF TSU SL and QoS mapping for priv QP - port number in query index */
-	EPSC_QUERY_MAP_PQP_TO_TSL	 = 0x48,
+	EPSC_QUERY_MAP_PQP_TO_TSL	 = 0x48u,
 	/** PSIF TSU SL and QoS mapping for IB SL 0-7 - port number in query index */
-	EPSC_QUERY_MAP_SL_TO_TSL_LO	 = 0x49,
+	EPSC_QUERY_MAP_SL_TO_TSL_LO	 = 0x49u,
 	/** PSIF TSU SL and QoS mapping for IB SL 8-15 - port number in query index */
-	EPSC_QUERY_MAP_SL_TO_TSL_HI	 = 0x4a,
-	/** VPD Product Name - 8 byte offset in query index */
-	EPSC_QUERY_VPD_PRODUCT_NAME	 = 0x4b,
+	EPSC_QUERY_MAP_SL_TO_TSL_HI	 = 0x4au,
+	/** MMU static configuration of TA_UPPER_TWELVE bits (SPARC only) */
+	EPSC_QUERY_TA_UPPER_TWELVE	 = 0x4cu,
+	/** MMU static configuration of PA_UPPER_TWELVE bits (SPARC only) */
+	EPSC_QUERY_PA_UPPER_TWELVE	 = 0x4du,
+	/** Number of VFs configured - valid values limited to power-of-two.
+	 * For BARE_METAL mode, number of VFs is -1 i.e. not applicable.
+	 * PSIF_QUERY index as defined in psif_epsc_query_num_vfs_mode
+	 * PSIF_SET   index = #VFs for next restart
+	 */
+	EPSC_QUERY_NUM_VFS	 = 0x4fu,
+	/** Development debug only operation: SET and QUERY the TSU credit
+	 * mode setup as defined by epsc_cli: cfg tsu_credit
+	 */
+	EPSC_QUERY_CREDIT_MODE	 = 0x50u,
+	/** Query version on onboard CPLD (Titan only Other platforms will return EPSC_ENODATA) */
+	EPSC_QUERY_CPLD_VERSION	 = 0x51u,
+	/** Query portinfo on exernal port (defined in psif_epsc_query_external_port_info_t) */
+	EPSC_QUERY_EXTERNAL_PORT_INFO	 = 0x53u,
+	/* EOF marker - must be last and highest in this enum type. */
+	EPSC_QUERY_LAST	 = 0x54u,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_QUERY_OP_FIELD_MAX	 = 0x7fffffff
+	PSIF_EPSC_QUERY_OP_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_epsc_query_op [32 bits] */
 
 /**
  * Valid values for struct psif_epsc_csr_update::opcode
  */
 enum psif_epsc_csr_update_opcode {
-	EPSC_UPDATE_OP_POLL	 = 0,
+	EPSC_UPDATE_OP_POLL	 = 0u,
 	EPSC_UPDATE_OP_START,
 	EPSC_UPDATE_OP_ERASE,
 	EPSC_UPDATE_OP_WRITE,
@@ -1786,7 +1894,7 @@
 	EPSC_UPDATE_OP_SET,
 	EPSC_UPDATE_OP_MAX,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_CSR_UPDATE_OPCODE_FIELD_MAX	 = 0xffff
+	PSIF_EPSC_CSR_UPDATE_OPCODE_FIELD_MAX	 = 0xffffu
 }; /* enum psif_epsc_csr_update_opcode [16 bits] */
 
 /**
@@ -1801,7 +1909,7 @@
 	/* always last */
 	EPSC_FLASH_SLOT_COUNT,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_FLASH_SLOT_FIELD_MAX	 = 0xffff
+	PSIF_EPSC_FLASH_SLOT_FIELD_MAX	 = 0xffffu
 }; /* enum psif_epsc_flash_slot [16 bits] */
 
 /**
@@ -1814,7 +1922,7 @@
 	EPSC_UPDATE_SET_TWOSHOT_IMG,
 	EPSC_UPDATE_SET_IMG_VALID,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_UPDATE_SET_FIELD_MAX	 = 0x7fffffff
+	PSIF_EPSC_UPDATE_SET_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_epsc_update_set [32 bits] */
 
 /**
@@ -1824,10 +1932,14 @@
 	EPSC_UF_CTRL_MMU_FLUSH,
 	EPSC_UF_CTRL_GET_UF_USED_QP,
 	EPSC_UF_CTRL_CLEAR_UF_USED_QP,
-	/** For SMP {en dis}able is the flag param a bitvector for which ports to update 0x6 hence indicate P1 and P2. */
+	/** For SMP {en dis}able is the flag param a bitvector for which ports
+	 *  to update, 0x6 hence indicate P1 and P2.
+	 */
 	EPSC_UF_CTRL_SMP_ENABLE,
 	EPSC_UF_CTRL_SMP_DISABLE,
-	/** For Vlink {dis }connect is the flag param a bitvector for which ports to update 0x6 hence indicate P1 and P2. */
+	/** For Vlink {dis }connect is the flag param a bitvector for which ports
+	 * to update, 0x6 hence indicate P1 and P2.
+	 */
 	EPSC_UF_CTRL_VLINK_CONNECT,
 	EPSC_UF_CTRL_VLINK_DISCONNECT,
 	/** Retrieve the highest QP number used by the given UF */
@@ -1835,7 +1947,7 @@
 	/** Reset the highest QP number cache for the given UF */
 	EPSC_UF_CTRL_RESET_HIGHEST_QP_IDX,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_CSR_UF_CTRL_OPCODE_FIELD_MAX	 = 0x7fffffff
+	PSIF_EPSC_CSR_UF_CTRL_OPCODE_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_epsc_csr_uf_ctrl_opcode [32 bits] */
 
 /**
@@ -1911,7 +2023,7 @@
 	/* no DMA or DMA if multiple UFs */
 	EPSC_VIMMA_CTRL_SET_ADMIN_MODE,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_VIMMA_CTRL_OPCODE_FIELD_MAX	 = 0x7fffffff
+	PSIF_EPSC_VIMMA_CTRL_OPCODE_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_epsc_vimma_ctrl_opcode [32 bits] */
 
 
@@ -1920,7 +2032,7 @@
 	/* VFP used as short for VM Fabric Profile */
 	EPSC_VIMMA_CTRL_IB_ADM_MODE_VM_FABRIC_PROFILE,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_VIMMA_ADMMODE_FIELD_MAX	 = 0xffff
+	PSIF_EPSC_VIMMA_ADMMODE_FIELD_MAX	 = 0xffffu
 }; /* enum psif_epsc_vimma_admmode [16 bits] */
 
 /**
@@ -1929,7 +2041,7 @@
  */
 enum psif_epsc_csr_pma_counters_enum {
 	/** Regular counters - IB Spec chapter 16.1.3.5 */
-	EPSC_PMA_SYMBOL_ERR_CNTR	 = 0,
+	EPSC_PMA_SYMBOL_ERR_CNTR	 = 0u,
 	EPSC_PMA_LINK_ERR_RECOVERY_CNTR,
 	EPSC_PMA_LINK_DOWNED_CNTR,
 	EPSC_PMA_PORT_RCV_ERR,
@@ -1961,7 +2073,7 @@
 	/* Keep this in End */
 	EPSC_PMA_COUNTERS_TOTAL,
 	/* Padding out to required bits allocated */
-	PSIF_EPSC_CSR_PMA_COUNTERS_ENUM_FIELD_MAX	 = 0x7fffffff
+	PSIF_EPSC_CSR_PMA_COUNTERS_ENUM_FIELD_MAX	 = 0x7fffffffu
 }; /* enum psif_epsc_csr_pma_counters_enum [32 bits] */
 
 /**
@@ -1976,7 +2088,7 @@
  */
 enum psif_epsc_csr_atomic_op {
 	/** PSIF requests atomic operations for IB and SQS. */
-	PSIF_PCIE_ATOMIC_OP_BOTH	 = 0,
+	PSIF_PCIE_ATOMIC_OP_BOTH	 = 0u,
 	/** PSIF requests atomic operations for IB. */
 	PSIF_PCIE_ATOMIC_OP_IB,
 	/** PSIF requests atomic operations for SQS. */
@@ -1985,12 +2097,28 @@
 	PSIF_PCIE_ATOMIC_OP_NONE
 }; /* enum psif_epsc_csr_atomic_op [ 2 bits] */
 
+/**
+ * For data in response structure of EPSC_BER_DATA Op.
+ */
+enum psif_epsc_csr_ber_counters_enum {
+	/* IBU_P1_STATUS_ADDR */
+	EPSC_BER_PORT_STATUS	 = 0u,
+	/* IBU_P1_LINK_SPEED_ACTIVE_ADDR */
+	EPSC_BER_LINK_SPEED_ACTIVE,
+	/* IBU_P1_LINK_WIDTH_ACTIVE_ADDR */
+	EPSC_BER_LINKWIDTH_ACTIVE,
+	/* IBU_P1_PCLINK_ERR_REC_CNT_ADDR */
+	EPSC_BER_PCLINK_ERR_REC_CNT,
+	/* IBU_P1_PCLINK_DOWNED_CNT_ADDR */
+	EPSC_BER_PCLINK_DOWNED_CNT
+}; /* enum psif_epsc_csr_ber_counters_enum [ 3 bits] */
+
 /*
  * Completion notification states. Could take any of these values:
  * PSIF_CQ_UNARMED PSIF_CQ_ARMED_SE PSIF_CQ_ARMED_ALL PSIF_CQ_TRIGGERED
  */
 enum psif_cq_state {
-	PSIF_CQ_UNARMED,
+	PSIF_CQ_UNARMED	 = 0u,
 	PSIF_CQ_ARMED_SE,
 	PSIF_CQ_ARMED_ALL,
 	PSIF_CQ_TRIGGERED
@@ -2001,13 +2129,13 @@
  * not.
  */
 enum psif_rss_hash_source {
-	RSS_WITHOUT_PORT,
+	RSS_WITHOUT_PORT	 = 0u,
 	RSS_WITH_PORT
 }; /* enum psif_rss_hash_source [ 1 bits] */
 
-#if defined (HOST_LITTLE_ENDIAN)
+#if defined(HOST_LITTLE_ENDIAN)
 #include "psif_hw_data_le.h"
-#elif defined (HOST_BIG_ENDIAN)
+#elif defined(HOST_BIG_ENDIAN)
 #include "psif_hw_data_be.h"
 #else
 #error "Could not determine byte order in psif_hw_data.h !?"
--- a/components/open-fabrics/libsif/include/psifapi/psif_hw_data_be.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_data_be.h	Mon Oct 17 23:20:28 2016 -0700
@@ -3,8 +3,8 @@
  */
 
 /*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimer.
@@ -14,24 +14,96 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef	_PSIF_HW_DATA_H_BE
 #define	_PSIF_HW_DATA_H_BE
 
+/* CSR automated type for TSU_MMU_MMU_CONFIG */
+/* MMU Static-Configuration and Status */
+struct psif_csr_mmu_config {
+	u16	noname:4;
+	u16	pa_upper_twelve:12;
+	u16	noname1:4;
+	u16	ta_upper_twelve:12;
+	u16	cam_par_err_fatal:1;
+	u16	dis_table_ptr_trans:1;
+	u16	noname2:2;
+	u16	ptwc_hash_sel:2;
+	u16	dma_cnt_mask:8;
+	u16	sparc_pages:1;
+	u16	bit_sixty_three_value:1;
+	u16	chk_bit_sixty_three:1;
+	u16	chk_upper_addr_bits:1;
+	u16	swap_rsp:1;
+	u16	mmuc_hash_select:2;
+	u16	random_evict:1;
+	u16	mmuc_evict_algorithm:1;
+	u16	ptwc_evict_algorithm:1;
+	u16	cam_evict_cntr_cnt_sel:5;
+	u16	cam_evict_cntr_prescale_sel:3;
+} PSIF_PACKED_ALIGNED; /* struct psif_csr_mmu_config [ 8 byte] */
+
+/**
+ * \brief Definition of struct returned by EPSC_QUERY_EXTERNAL_PORT_INFO
+ * \details
+ * This struct is returning several attributes of the external IB port. The vHCA IB portnumber
+ * is set in the index field. Values returned maches description in PortInfo (See IB specification
+ * 1.3 vol1 chapter 14.2.5.6), except for active speed which will return values as defined in
+ * psif_port_speed.
+ * \par Width
+ *      64 bit
+ * \par Used in
+ * the parameter for the PSIF_QUERY sub-operation EPSC_QUERY_PORT_INFO - vHCA IB portnumber set in index field
+ * \par Classification
+ *      internal, development
+ */
+
+struct psif_epsc_query_external_port_info {
+	/**< LID of the IB device connected to the external port */
+
+	u16	lid;
+	/**< IB port number of external port (on the IB device above) */
+
+	u16	portnumber:8;
+	/**< IB port state of external port values will match psif_epsc_port_state_t */
+
+	u16	port_state:4;
+	/**< Physical port state of IB port */
+
+	u16	port_physical_state:4;
+	/**< IB LinkSpeedActive of external port */
+
+	enum psif_port_speed	active_speed:8;
+
+	/**< IB LinkWidthActive of external port */
+
+	u16	active_width:8;
+	/**< Active MTU of external port (values will match psif_epsc_path_mtu_t */
+
+	u16	active_mtu:4;
+	/**< Number of operational Data VLs */
+
+	u16	operational_vls:4;
+	/**< Reserved */
+
+	u16	noname:8;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_query_external_port_info [ 8 byte] */
+
 /*
  * Context used by tsu_mmu when performing address translation. The structure
  * is follows: [63:56] st [55:55] no_snoop [54:53] tph [52:52] ro [51:12]
@@ -810,7 +882,7 @@
 	u64	something;
 } PSIF_PACKED_ALIGNED; /* struct psif_sq_ring [ 8 byte] */
 
-/* Temp.definition of the send queue entry cache for the completion block 
+/* Temp. definition of the send queue entry cache for the completion block.
  * The only info used by the driver is the size of this struct,
  * when allocating space for the cache in memory:
  */
@@ -1583,7 +1655,7 @@
  */
 struct psif_qp_attributes {
 	/* Manually added spacing to pad outpsif_qp_attributes */
-	u8	:7;
+	u8	pad92:7;
 	/* Change path req_access error if set. */
 	u8	req_access_error:1;
 	/* Change path MTU if set. */
@@ -1838,7 +1910,7 @@
 	 */
 	u32	notify_when_zero:1;
 	/* Manually added spacing to pad out psif_modify_command */
-	u32	:3;
+	u32	pad93:3;
 } PSIF_PACKED; /* struct psif_modify_command [ 5 byte] */
 
 /*
@@ -1901,7 +1973,7 @@
 
 /**
  * Flash image header format for application image
- * extention of struct psif_flash_header_all
+ * extension of struct psif_flash_header_all
  */
 struct psif_flash_header_app {
 	/* byte[4:7] image type */
@@ -2100,17 +2172,6 @@
 	u32	seq_num;
 } PSIF_PACKED_ALIGNED32; /* struct psif_eq_entry [64 byte] */
 
-struct psif_epsc_log_stat {
-	/* Owned by epsc runs all the way to 64 bit */
-	u64	produce_offset;
-	/* Owned by host */
-	u64	consume_offset;
-	/* Owned by host real offset modulo sz */
-	u64	size;
-	/* Allign to 32 byte */
-	u64	pad;
-} PSIF_PACKED_ALIGNED; /* struct psif_epsc_log_stat [32 byte] */
-
 /**
  * CSR Query port structure
  */
@@ -2147,6 +2208,17 @@
 	u64	pad;
 } PSIF_PACKED_ALIGNED32; /* struct psif_epsc_port_attr [64 byte] */
 
+struct psif_epsc_log_stat {
+	/* Owned by epsc runs all the way to 64 bit */
+	u64	produce_offset;
+	/* Owned by host */
+	u64	consume_offset;
+	/* Owned by host real offset modulo sz */
+	u64	size;
+	/* Allign to 32 byte */
+	u64	pad;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_log_stat [32 byte] */
+
 /**
  * Query GID response in host memory
  */
@@ -2159,7 +2231,7 @@
  * Populate MMU table
  */
 struct psif_epsc_exercise_mmu {
-	/* Start adress */
+	/* Start address */
 	u64	host_addr;
 	/* MMU context supplied by driver */
 	struct psif_mmu_cntx	mmu_cntx;
@@ -2223,6 +2295,17 @@
 } PSIF_PACKED_ALIGNED32; /* struct psif_epsc_device_attr [192 byte] */
 
 /**
+ * For data in response structure of EPSC_BER_DATA Op.
+ */
+struct psif_epsc_csr_rsp_ber_data {
+	/* Received signal values (H0 values) for each Serdes Channel per port.
+	 status_rxd_reg0 in Sonoma PRM */
+	u64	received_signal_values[4];
+	/* Number of elements is same as psif_epsc_csr_ber_counters enum */
+	u64	ber_counters[5];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_rsp_ber_data [72 byte] */
+
+/**
  * The eps-c fw csr to host sw completion
  * Response to a CSR request
  */
@@ -2275,8 +2358,10 @@
 	u32	num_entries;
 	/** unused (padding) */
 	u32	noname:27;
-	/** size of an entry as log2 value. The address to an entry is calculated
-	 *  as host_addr + entry_num*(1 << extent_log2) */
+	/**
+	 * Size of an entry as log2 value. The address to an entry is calculated
+	 * as host_addr + entry_num*(1 << extent_log2).
+	 */
 	u32	extent_log2:5;
 	/** MSI-X interrupt index only valid for EQ setup */
 	u32	msix_index;
@@ -2320,10 +2405,10 @@
 	 */
 	u64	notify_when_zero:1;
 	/* Manually added spacing to pad out psif_modify_command */
-	u64	:3;
+	u64	pad97:3;
 	/* Inlined cmd_attributes : struct psif_qp_attributes (24 bits) */
 	/* Manually added spacing to pad outpsif_qp_attributes */
-	u64	:7;
+	u64	pad98:7;
 	/* Change path req_access error if set. */
 	u64	req_access_error:1;
 	/* Change path MTU if set. */
@@ -2567,14 +2652,13 @@
  * Test operations : EPSC_TEST_HOST_RD & EPSC_TEST_HOST_WR
  */
 struct psif_epsc_csr_test_host_wrd {
-	struct psif_mmu_cntx	mmu_cntx;
 	u64	host_addr;
+	u32	key;
 	u32	epsc_offs;
 	u32	length;
 	/* pattern number 0..xxx */
 	u32	pattern;
-	u32	noname:32;
-	u64	reserved_2[7];
+	u64	reserved_1[8];
 } PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_test_host_wrd [88 byte] */
 
 /**
@@ -2592,7 +2676,6 @@
 
 /**
  * IB packet trace acquire : EPSC_TRACE_ACQUIRE
- *
  */
 struct psif_epsc_csr_trace_acquire {
 	/* Pointer to trace buffer */
@@ -2624,8 +2707,10 @@
 	/* Log mode to use */
 	enum psif_epsc_log_mode	mode:32;
 
-	/* Fields only used by log mode EPSC_LOG_MODE_HOST:
-	 Start address of the data area to write to */
+	/*
+	 * Fields only used by log mode EPSC_LOG_MODE_HOST:
+	 * Start address of the data area to write to.
+	 */
 	u64	base;
 	/* pointer to a log_stat data area */
 	u64	stat_base;
@@ -2653,24 +2738,22 @@
 } PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_epsa_cntrl [88 byte] */
 
 /**
- * EPS-A to EPS-A
+ * host to EPS-A
  */
 struct psif_epsc_csr_epsa_cmd {
 	enum psif_epsa_command	cmd:32;
 
 	u32	length;
-	/* MMU context supplied by driver */
-	struct psif_mmu_cntx	mmu_cntx;
-	/* Buffer adress in host memory */
+	/* Buffer address in host memory */
 	u64	host_addr;
 	u8	entry_point[16];
 	u32	key;
 	u32	qpnum;
-	u64	reserved[5];
+	u64	reserved[6];
 } PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_epsa_cmd [88 byte] */
 
 /**
- * EPSC_CLI_ACCESS - buffer size is assumed to be 4K
+ * EPSC_CLI_ACCESS - buffer size is presumed to be 2K
  */
 struct psif_epsc_csr_cli_access {
 	u64	host_addr;
@@ -2754,7 +2837,6 @@
 
 /**
  * Structure for EPSC_SET
- *
  */
 struct psif_epsc_csr_set {
 	/* UF number */
@@ -2902,10 +2984,9 @@
 } PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_pma_counters [32 byte] */
 
 /** \brief Command params for opcode EPSC_VIMMA_CTRL_SET_VFP_VHCA_DEREGISTER
- \note
- This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
- \par Classification
- external
+ *  \note This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
+ *  \par Classification
+ *       external
  */
 struct psif_epsc_vimma_dereg {
 	/* size 5*u64 */
@@ -2919,10 +3000,9 @@
 } PSIF_PACKED_ALIGNED; /* struct psif_epsc_vimma_dereg [40 byte] */
 
 /** \brief Struct defintion for vHCA registration details
- \note
- This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
- \par Classification
- external
+ * \note This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
+ * \par Classification
+ *      external
  */
 struct psif_epsc_vimma_vfp_reg {
 	/* size 5*u64 */
@@ -2937,10 +3017,9 @@
 } PSIF_PACKED_ALIGNED; /* struct psif_epsc_vimma_vfp_reg [40 byte] */
 
 /** \brief Command params for opcode EPSC_VIMMA_CTRL_SET_ADMIN_MODE
- \note
- This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
- \par Classification
- external
+ *  \note This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
+ *  \par Classification
+ *       external
  */
 struct psif_epsc_vimma_set_admmode {
 	/* size 5*u64 */
@@ -2956,10 +3035,9 @@
 } PSIF_PACKED_ALIGNED; /* struct psif_epsc_vimma_set_admmode [40 byte] */
 
 /** \brief Command params for opcode EPSC_VIMMA_CTRL_SET_VFP_VHCA_REGISTER
- \note
- This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
- \par Classification
- external
+ *  \note This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
+ *  \par Classification
+ *       external
  */
 struct psif_epsc_vimma_reg_info {
 	u32	noname:32;
@@ -2972,8 +3050,8 @@
 } PSIF_PACKED_ALIGNED; /* struct psif_epsc_vimma_reg_info [40 byte] */
 
 /** \brief Defining params for VIMMA opcodes
- \par Classification
- external
+ *  \par Classification
+ *       external
  */
 union psif_epsc_vimma_ctrl_cmd {
 	/* all union elements are size 5*u64 */
@@ -2984,11 +3062,10 @@
 } PSIF_PACKED; /* union psif_epsc_vimma_ctrl_cmd [40 byte] */
 
 /** \brief Defines the complete command params for VIMMA opcodes
- \note
- This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_BASIC_CAPS
- and should never change in an incompatible way.
- \par Classification
- external
+ *  \note This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_BASIC_CAPS
+ *   and should never change in an incompatible way.
+ *  \par Classification
+ *       external
  */
 struct psif_epsc_csr_vimma_ctrl {
 	/* VIMMA sub-opcodes triggered by EPSC_VIMMA_CTRL */
@@ -3006,6 +3083,20 @@
 	u64	reserved[3];
 } PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_vimma_ctrl [88 byte] */
 
+/**
+ * Structure for EPSC_BER_DATA
+ */
+struct psif_epsc_csr_ber_data {
+	/* Buffer address in host memory */
+	u64	host_addr;
+	/* MMU supplied by the driver */
+	struct psif_mmu_cntx	mmu_cntx;
+	/* IBU port number */
+	u32	port;
+	/* Buffer length in bytes */
+	u32	len;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_ber_data [24 byte] */
+
 /* Public API for mailbox requests details */
 union psif_epsc_csr_details {
 	/* Anonymous data */
@@ -3074,6 +3165,8 @@
 	struct psif_epsc_csr_pma_counters	pma_counters;
 	/* EPSC_VIMMA_CTRL: VIMMA functions */
 	struct psif_epsc_csr_vimma_ctrl	vimma_ctrl;
+	/* BER data query */
+	struct psif_epsc_csr_ber_data	ber;
 } PSIF_PACKED; /* union psif_epsc_csr_details [88 byte] */
 
 /**
@@ -3116,10 +3209,14 @@
  * Basic configuration data for each UF
  */
 struct psif_epsc_csr_config {
-	/** Minor protocol version identifier. */
-	u32	minor_ver;
-	/** Major protocol version identifier. */
-	u32	major_ver;
+	/** Major EPS API version identifier. */
+	u16	epsapi_major_ver;
+	/** Minor EPS API version identifier. */
+	u16	epsapi_minor_ver;
+	/** Major HW API version identifier. */
+	u16	hwapi_major_ver;
+	/** Minor HW API version identifier. */
+	u16	hwapi_minor_ver;
 	/** Request base address. */
 	u64	request;
 	/** Respose base address. */
@@ -3420,7 +3517,7 @@
 	/* Number of entries in table. */
 	u32	num_entries;
 	/* Manually added spacing to pad out base addr */
-	u32	:27;
+	u32	pad104:27;
 	/*
 	 * clog2_extent used for entry alignment. This field used to calculate
 	 * address for a particular entry. Address to an entry is calculated as
@@ -3437,8 +3534,10 @@
 	u32	zero:8;
 	/* [183:160] psn */
 	u32	psn:24;
-	/* [159] When set to one entry has been used. When set to zero 
-	 no duplicate has been written in this entry. */
+	/*
+	 * [159] When set to one, entry has been used. When set to zero,
+	 * no duplicate has been written in this entry.
+	 */
 	u32	used:1;
 	/* [158] This atomic response was in error. */
 	u32	response_error:1;
@@ -3447,7 +3546,8 @@
 	u64	reserved[2];
 } PSIF_PACKED_ALIGNED; /* struct psif_atomic_retry_element [32 byte] */
 
-/* Data type for TSU_HOST_QP_BASE_ADDR - atomic replay scratch pad
+/*
+ * Data type for TSU_HOST_QP_BASE_ADDR - atomic replay scratch pad
  *  Layout as of 16 deep atomic queue - elements padded to 32 byte
  */
 struct psif_atsp {
--- a/components/open-fabrics/libsif/include/psifapi/psif_hw_macro.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_macro.h	Mon Oct 17 23:20:28 2016 -0700
@@ -3,8 +3,8 @@
  */
 
 /*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimer.
@@ -14,19 +14,20 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef	_PSIF_HW_MACRO_H
@@ -44,6 +45,16 @@
 #endif
 
 
+#define PSIF_CSR_MMU_CONFIG_TA_UPPER_TWELVE_OFFSET	0
+#define PSIF_CSR_MMU_CONFIG_TA_UPPER_TWELVE_SHIFT	32
+#define PSIF_CSR_MMU_CONFIG_TA_UPPER_TWELVE_BITS	12
+#define PSIF_CSR_MMU_CONFIG_TA_UPPER_TWELVE_MASK	0x00000fff00000000ull
+
+#define PSIF_CSR_MMU_CONFIG_PA_UPPER_TWELVE_OFFSET	0
+#define PSIF_CSR_MMU_CONFIG_PA_UPPER_TWELVE_SHIFT	48
+#define PSIF_CSR_MMU_CONFIG_PA_UPPER_TWELVE_BITS	12
+#define PSIF_CSR_MMU_CONFIG_PA_UPPER_TWELVE_MASK	0x0fff000000000000ull
+
 /*
  * PSIF_WR_INVALIDATE_LKEY: key to invalidate/flush from the DMA VT cache.
  * PSIF_WR_INVALIDATE_RKEY: key to invalidate/flush from the DMA VT cache.
@@ -380,6 +391,18 @@
 #define PSIF_QP_CORE_9_TRANSPORT_TYPE_MASK	0x0000000000000007ull
 
 /*
+ * This is an index to completion queue descriptor. The descriptor points to
+ * a receive completion queue, which may or may not be the same as the send
+ * completion queue. For XRC QPs, this field is written by the CQ descriptor
+ * received by the XRCSRQ on the first packet. This way we don't need to look
+ * up the XRCSRQ for every packet. of the message.
+ */
+#define PSIF_QP_CORE_RCV_CQ_INDX_OFFSET	9
+#define PSIF_QP_CORE_9_RCV_CQ_INDX_SHIFT	8
+#define PSIF_QP_CORE_9_RCV_CQ_INDX_BITS	24
+#define PSIF_QP_CORE_9_RCV_CQ_INDX_MASK	0x00000000ffffff00ull
+
+/*
  * Number of bytes received of in progress RDMA Write or SEND. The data
  * received for SENDs and RDMA WR w/Imm are needed for completions. This
  * should be added to the msg_length.
@@ -658,8 +681,8 @@
 #define PSIF_AH_2_SL_SHIFT	20
 #define PSIF_AH_2_SL_BITS	4
 #define PSIF_AH_2_SL_MASK	0x0000000000f00000ull
-#if defined (HOST_LITTLE_ENDIAN)
-#elif defined (HOST_BIG_ENDIAN)
+#if defined(HOST_LITTLE_ENDIAN)
+#elif defined(HOST_BIG_ENDIAN)
 #else
 #error "Could not determine byte order in psif_hw_macro.h !?"
 #endif
--- a/components/open-fabrics/libsif/include/psifapi/psif_hw_print.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_print.h	Mon Oct 17 23:20:28 2016 -0700
@@ -3,8 +3,8 @@
  */
 
 /*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimer.
@@ -14,19 +14,20 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef	_PSIF_HW_PRINT_H
@@ -47,211 +48,474 @@
 void write_bits_u16(XFILE *fd, int extent, u16 data);
 void write_bits_u32(XFILE *fd, int extent, u32 data);
 void write_bits_u64(XFILE *fd, int extent, u64 data);
-const char* string_enum_psif_mmu_translation(enum psif_mmu_translation val);
-void write_enum_psif_mmu_translation(XFILE *fd, enum psif_mmu_translation data);
-const char* string_enum_psif_page_size(enum psif_page_size val);
-void write_enum_psif_page_size(XFILE *fd, enum psif_page_size data);
-const char* string_enum_psif_wr_type(enum psif_wr_type val);
-void write_enum_psif_wr_type(XFILE *fd, enum psif_wr_type data);
-const char* string_enum_psif_port(enum psif_port val);
-void write_enum_psif_port(XFILE *fd, enum psif_port data);
-const char* string_enum_psif_use_ah(enum psif_use_ah val);
-void write_enum_psif_use_ah(XFILE *fd, enum psif_use_ah data);
-const char* string_enum_psif_tsu_qos(enum psif_tsu_qos val);
-void write_enum_psif_tsu_qos(XFILE *fd, enum psif_tsu_qos data);
-const char* string_enum_psif_wc_opcode(enum psif_wc_opcode val);
-void write_enum_psif_wc_opcode(XFILE *fd, enum psif_wc_opcode data);
-const char* string_enum_psif_wc_status(enum psif_wc_status val);
-void write_enum_psif_wc_status(XFILE *fd, enum psif_wc_status data);
-const char* string_enum_ib_opcode(enum ib_opcode val);
-void write_enum_ib_opcode(XFILE *fd, enum ib_opcode data);
-const char* string_enum_psif_eps_a_core(enum psif_eps_a_core val);
-void write_enum_psif_eps_a_core(XFILE *fd, enum psif_eps_a_core data);
-const char* string_enum_psif_qp_state(enum psif_qp_state val);
-void write_enum_psif_qp_state(XFILE *fd, enum psif_qp_state data);
-const char* string_enum_psif_cmpl_outstanding_error(enum psif_cmpl_outstanding_error val);
-void write_enum_psif_cmpl_outstanding_error(XFILE *fd, enum psif_cmpl_outstanding_error data);
-const char* string_enum_psif_expected_op(enum psif_expected_op val);
-void write_enum_psif_expected_op(XFILE *fd, enum psif_expected_op data);
-const char* string_enum_psif_migration(enum psif_migration val);
-void write_enum_psif_migration(XFILE *fd, enum psif_migration data);
-const char* string_enum_psif_qp_trans(enum psif_qp_trans val);
-void write_enum_psif_qp_trans(XFILE *fd, enum psif_qp_trans data);
-const char* string_enum_psif_bool(enum psif_bool val);
-void write_enum_psif_bool(XFILE *fd, enum psif_bool data);
-const char* string_enum_psif_eoib_type(enum psif_eoib_type val);
-void write_enum_psif_eoib_type(XFILE *fd, enum psif_eoib_type data);
-const char* string_enum_psif_comm_live(enum psif_comm_live val);
-void write_enum_psif_comm_live(XFILE *fd, enum psif_comm_live data);
-const char* string_enum_psif_path_mtu(enum psif_path_mtu val);
-void write_enum_psif_path_mtu(XFILE *fd, enum psif_path_mtu data);
-const char* string_enum_psif_use_grh(enum psif_use_grh val);
-void write_enum_psif_use_grh(XFILE *fd, enum psif_use_grh data);
-const char* string_enum_psif_loopback(enum psif_loopback val);
-void write_enum_psif_loopback(XFILE *fd, enum psif_loopback data);
-const char* string_enum_psif_qp_command(enum psif_qp_command val);
-void write_enum_psif_qp_command(XFILE *fd, enum psif_qp_command data);
-const char* string_enum_psif_mbox_type(enum psif_mbox_type val);
-void write_enum_psif_mbox_type(XFILE *fd, enum psif_mbox_type data);
-const char* string_enum_psif_dma_vt_key_states(enum psif_dma_vt_key_states val);
-void write_enum_psif_dma_vt_key_states(XFILE *fd, enum psif_dma_vt_key_states data);
-const char* string_enum_psif_flash_image_type(enum psif_flash_image_type val);
-void write_enum_psif_flash_image_type(XFILE *fd, enum psif_flash_image_type data);
-const char* string_enum_psif_event(enum psif_event val);
-void write_enum_psif_event(XFILE *fd, enum psif_event data);
-const char* string_enum_psif_tsu_error_types(enum psif_tsu_error_types val);
-void write_enum_psif_tsu_error_types(XFILE *fd, enum psif_tsu_error_types data);
-const char* string_enum_psif_eps_core_id(enum psif_eps_core_id val);
-void write_enum_psif_eps_core_id(XFILE *fd, enum psif_eps_core_id data);
-const char* string_enum_psif_epsc_log_mode(enum psif_epsc_log_mode val);
-void write_enum_psif_epsc_log_mode(XFILE *fd, enum psif_epsc_log_mode data);
-const char* string_enum_psif_epsc_log_level(enum psif_epsc_log_level val);
-void write_enum_psif_epsc_log_level(XFILE *fd, enum psif_epsc_log_level data);
-const char* string_enum_psif_epsc_port_state(enum psif_epsc_port_state val);
-void write_enum_psif_epsc_port_state(XFILE *fd, enum psif_epsc_port_state data);
-const char* string_enum_psif_epsc_interrupt_source(enum psif_epsc_interrupt_source val);
-void write_enum_psif_epsc_interrupt_source(XFILE *fd, enum psif_epsc_interrupt_source data);
-const char* string_enum_psif_epsc_interrupt_pri(enum psif_epsc_interrupt_pri val);
-void write_enum_psif_epsc_interrupt_pri(XFILE *fd, enum psif_epsc_interrupt_pri data);
-const char* string_enum_psif_epsc_csr_status(enum psif_epsc_csr_status val);
-void write_enum_psif_epsc_csr_status(XFILE *fd, enum psif_epsc_csr_status data);
-const char* string_enum_psif_epsc_csr_opcode(enum psif_epsc_csr_opcode val);
-void write_enum_psif_epsc_csr_opcode(XFILE *fd, enum psif_epsc_csr_opcode data);
-const char* string_enum_psif_epsc_csr_flags(enum psif_epsc_csr_flags val);
-void write_enum_psif_epsc_csr_flags(XFILE *fd, enum psif_epsc_csr_flags data);
-const char* string_enum_psif_vlink_state(enum psif_vlink_state val);
-void write_enum_psif_vlink_state(XFILE *fd, enum psif_vlink_state data);
-const char* string_enum_psif_epsc_csr_modify_device_flags(enum psif_epsc_csr_modify_device_flags val);
-void write_enum_psif_epsc_csr_modify_device_flags(XFILE *fd, enum psif_epsc_csr_modify_device_flags data);
-const char* string_enum_psif_epsc_csr_modify_port_flags(enum psif_epsc_csr_modify_port_flags val);
-void write_enum_psif_epsc_csr_modify_port_flags(XFILE *fd, enum psif_epsc_csr_modify_port_flags data);
-const char* string_enum_psif_epsc_csr_epsa_command(enum psif_epsc_csr_epsa_command val);
-void write_enum_psif_epsc_csr_epsa_command(XFILE *fd, enum psif_epsc_csr_epsa_command data);
-const char* string_enum_psif_epsa_command(enum psif_epsa_command val);
-void write_enum_psif_epsa_command(XFILE *fd, enum psif_epsa_command data);
-const char* string_enum_psif_epsc_query_op(enum psif_epsc_query_op val);
-void write_enum_psif_epsc_query_op(XFILE *fd, enum psif_epsc_query_op data);
-const char* string_enum_psif_epsc_csr_update_opcode(enum psif_epsc_csr_update_opcode val);
-void write_enum_psif_epsc_csr_update_opcode(XFILE *fd, enum psif_epsc_csr_update_opcode data);
-const char* string_enum_psif_epsc_flash_slot(enum psif_epsc_flash_slot val);
-void write_enum_psif_epsc_flash_slot(XFILE *fd, enum psif_epsc_flash_slot data);
-const char* string_enum_psif_epsc_update_set(enum psif_epsc_update_set val);
-void write_enum_psif_epsc_update_set(XFILE *fd, enum psif_epsc_update_set data);
-const char* string_enum_psif_epsc_csr_uf_ctrl_opcode(enum psif_epsc_csr_uf_ctrl_opcode val);
-void write_enum_psif_epsc_csr_uf_ctrl_opcode(XFILE *fd, enum psif_epsc_csr_uf_ctrl_opcode data);
-const char* string_enum_psif_epsc_vimma_ctrl_opcode(enum psif_epsc_vimma_ctrl_opcode val);
-void write_enum_psif_epsc_vimma_ctrl_opcode(XFILE *fd, enum psif_epsc_vimma_ctrl_opcode data);
-const char* string_enum_psif_epsc_vimma_admmode(enum psif_epsc_vimma_admmode val);
-void write_enum_psif_epsc_vimma_admmode(XFILE *fd, enum psif_epsc_vimma_admmode data);
-const char* string_enum_psif_cq_state(enum psif_cq_state val);
-void write_enum_psif_cq_state(XFILE *fd, enum psif_cq_state data);
-const char* string_enum_psif_rss_hash_source(enum psif_rss_hash_source val);
-void write_enum_psif_rss_hash_source(XFILE *fd, enum psif_rss_hash_source data);
+const char *string_enum_psif_epsc_degrade_cause(enum psif_epsc_degrade_cause val);
+void write_enum_psif_epsc_degrade_cause(XFILE *fd,
+	enum psif_epsc_degrade_cause data);
+const char *string_enum_psif_mmu_translation(enum psif_mmu_translation val);
+void write_enum_psif_mmu_translation(XFILE *fd,
+	enum psif_mmu_translation data);
+const char *string_enum_psif_page_size(enum psif_page_size val);
+void write_enum_psif_page_size(XFILE *fd,
+	enum psif_page_size data);
+const char *string_enum_psif_wr_type(enum psif_wr_type val);
+void write_enum_psif_wr_type(XFILE *fd,
+	enum psif_wr_type data);
+const char *string_enum_psif_port(enum psif_port val);
+void write_enum_psif_port(XFILE *fd,
+	enum psif_port data);
+const char *string_enum_psif_use_ah(enum psif_use_ah val);
+void write_enum_psif_use_ah(XFILE *fd,
+	enum psif_use_ah data);
+const char *string_enum_psif_tsu_qos(enum psif_tsu_qos val);
+void write_enum_psif_tsu_qos(XFILE *fd,
+	enum psif_tsu_qos data);
+const char *string_enum_psif_wc_opcode(enum psif_wc_opcode val);
+void write_enum_psif_wc_opcode(XFILE *fd,
+	enum psif_wc_opcode data);
+const char *string_enum_psif_wc_status(enum psif_wc_status val);
+void write_enum_psif_wc_status(XFILE *fd,
+	enum psif_wc_status data);
+const char *string_enum_ib_opcode(enum ib_opcode val);
+void write_enum_ib_opcode(XFILE *fd,
+	enum ib_opcode data);
+const char *string_enum_psif_eps_a_core(enum psif_eps_a_core val);
+void write_enum_psif_eps_a_core(XFILE *fd,
+	enum psif_eps_a_core data);
+const char *string_enum_psif_qp_state(enum psif_qp_state val);
+void write_enum_psif_qp_state(XFILE *fd,
+	enum psif_qp_state data);
+const char *string_enum_psif_cmpl_outstanding_error(enum psif_cmpl_outstanding_error val);
+void write_enum_psif_cmpl_outstanding_error(XFILE *fd,
+	enum psif_cmpl_outstanding_error data);
+const char *string_enum_psif_expected_op(enum psif_expected_op val);
+void write_enum_psif_expected_op(XFILE *fd,
+	enum psif_expected_op data);
+const char *string_enum_psif_migration(enum psif_migration val);
+void write_enum_psif_migration(XFILE *fd,
+	enum psif_migration data);
+const char *string_enum_psif_qp_trans(enum psif_qp_trans val);
+void write_enum_psif_qp_trans(XFILE *fd,
+	enum psif_qp_trans data);
+const char *string_enum_psif_bool(enum psif_bool val);
+void write_enum_psif_bool(XFILE *fd,
+	enum psif_bool data);
+const char *string_enum_psif_eoib_type(enum psif_eoib_type val);
+void write_enum_psif_eoib_type(XFILE *fd,
+	enum psif_eoib_type data);
+const char *string_enum_psif_comm_live(enum psif_comm_live val);
+void write_enum_psif_comm_live(XFILE *fd,
+	enum psif_comm_live data);
+const char *string_enum_psif_path_mtu(enum psif_path_mtu val);
+void write_enum_psif_path_mtu(XFILE *fd,
+	enum psif_path_mtu data);
+const char *string_enum_psif_use_grh(enum psif_use_grh val);
+void write_enum_psif_use_grh(XFILE *fd,
+	enum psif_use_grh data);
+const char *string_enum_psif_loopback(enum psif_loopback val);
+void write_enum_psif_loopback(XFILE *fd,
+	enum psif_loopback data);
+const char *string_enum_psif_qp_command(enum psif_qp_command val);
+void write_enum_psif_qp_command(XFILE *fd,
+	enum psif_qp_command data);
+const char *string_enum_psif_mbox_type(enum psif_mbox_type val);
+void write_enum_psif_mbox_type(XFILE *fd,
+	enum psif_mbox_type data);
+const char *string_enum_psif_dma_vt_key_states(enum psif_dma_vt_key_states val);
+void write_enum_psif_dma_vt_key_states(XFILE *fd,
+	enum psif_dma_vt_key_states data);
+const char *string_enum_psif_flash_image_type(enum psif_flash_image_type val);
+void write_enum_psif_flash_image_type(XFILE *fd,
+	enum psif_flash_image_type data);
+const char *string_enum_psif_event(enum psif_event val);
+void write_enum_psif_event(XFILE *fd,
+	enum psif_event data);
+const char *string_enum_psif_tsu_error_types(enum psif_tsu_error_types val);
+void write_enum_psif_tsu_error_types(XFILE *fd,
+	enum psif_tsu_error_types data);
+const char *string_enum_psif_eps_core_id(enum psif_eps_core_id val);
+void write_enum_psif_eps_core_id(XFILE *fd,
+	enum psif_eps_core_id data);
+const char *string_enum_psif_epsc_port_state(enum psif_epsc_port_state val);
+void write_enum_psif_epsc_port_state(XFILE *fd,
+	enum psif_epsc_port_state data);
+const char *string_enum_psif_epsc_log_mode(enum psif_epsc_log_mode val);
+void write_enum_psif_epsc_log_mode(XFILE *fd,
+	enum psif_epsc_log_mode data);
+const char *string_enum_psif_epsc_log_level(enum psif_epsc_log_level val);
+void write_enum_psif_epsc_log_level(XFILE *fd,
+	enum psif_epsc_log_level data);
+const char *string_enum_psif_epsc_interrupt_source(enum psif_epsc_interrupt_source val);
+void write_enum_psif_epsc_interrupt_source(XFILE *fd,
+	enum psif_epsc_interrupt_source data);
+const char *string_enum_psif_epsc_interrupt_pri(enum psif_epsc_interrupt_pri val);
+void write_enum_psif_epsc_interrupt_pri(XFILE *fd,
+	enum psif_epsc_interrupt_pri data);
+const char *string_enum_psif_epsc_csr_status(enum psif_epsc_csr_status val);
+void write_enum_psif_epsc_csr_status(XFILE *fd,
+	enum psif_epsc_csr_status data);
+const char *string_enum_psif_epsc_csr_opcode(enum psif_epsc_csr_opcode val);
+void write_enum_psif_epsc_csr_opcode(XFILE *fd,
+	enum psif_epsc_csr_opcode data);
+const char *string_enum_psif_epsc_csr_flags(enum psif_epsc_csr_flags val);
+void write_enum_psif_epsc_csr_flags(XFILE *fd,
+	enum psif_epsc_csr_flags data);
+const char *string_enum_psif_vlink_state(enum psif_vlink_state val);
+void write_enum_psif_vlink_state(XFILE *fd,
+	enum psif_vlink_state data);
+const char *string_enum_psif_epsc_csr_modify_device_flags(enum psif_epsc_csr_modify_device_flags val);
+void write_enum_psif_epsc_csr_modify_device_flags(XFILE *fd,
+	enum psif_epsc_csr_modify_device_flags data);
+const char *string_enum_psif_epsc_csr_modify_port_flags(enum psif_epsc_csr_modify_port_flags val);
+void write_enum_psif_epsc_csr_modify_port_flags(XFILE *fd,
+	enum psif_epsc_csr_modify_port_flags data);
+const char *string_enum_psif_epsc_csr_epsa_command(enum psif_epsc_csr_epsa_command val);
+void write_enum_psif_epsc_csr_epsa_command(XFILE *fd,
+	enum psif_epsc_csr_epsa_command data);
+const char *string_enum_psif_epsa_command(enum psif_epsa_command val);
+void write_enum_psif_epsa_command(XFILE *fd,
+	enum psif_epsa_command data);
+const char *string_enum_psif_epsc_query_op(enum psif_epsc_query_op val);
+void write_enum_psif_epsc_query_op(XFILE *fd,
+	enum psif_epsc_query_op data);
+const char *string_enum_psif_epsc_csr_update_opcode(enum psif_epsc_csr_update_opcode val);
+void write_enum_psif_epsc_csr_update_opcode(XFILE *fd,
+	enum psif_epsc_csr_update_opcode data);
+const char *string_enum_psif_epsc_flash_slot(enum psif_epsc_flash_slot val);
+void write_enum_psif_epsc_flash_slot(XFILE *fd,
+	enum psif_epsc_flash_slot data);
+const char *string_enum_psif_epsc_update_set(enum psif_epsc_update_set val);
+void write_enum_psif_epsc_update_set(XFILE *fd,
+	enum psif_epsc_update_set data);
+const char *string_enum_psif_epsc_csr_uf_ctrl_opcode(enum psif_epsc_csr_uf_ctrl_opcode val);
+void write_enum_psif_epsc_csr_uf_ctrl_opcode(XFILE *fd,
+	enum psif_epsc_csr_uf_ctrl_opcode data);
+const char *string_enum_psif_epsc_vimma_ctrl_opcode(enum psif_epsc_vimma_ctrl_opcode val);
+void write_enum_psif_epsc_vimma_ctrl_opcode(XFILE *fd,
+	enum psif_epsc_vimma_ctrl_opcode data);
+const char *string_enum_psif_epsc_vimma_admmode(enum psif_epsc_vimma_admmode val);
+void write_enum_psif_epsc_vimma_admmode(XFILE *fd,
+	enum psif_epsc_vimma_admmode data);
+const char *string_enum_psif_cq_state(enum psif_cq_state val);
+void write_enum_psif_cq_state(XFILE *fd,
+	enum psif_cq_state data);
+const char *string_enum_psif_rss_hash_source(enum psif_rss_hash_source val);
+void write_enum_psif_rss_hash_source(XFILE *fd,
+	enum psif_rss_hash_source data);
 
 #if !defined(PSIF_EXCLUDE_WRITE_STRUCTS)
 
-void write_struct_psif_mmu_cntx(XFILE *fd, int network_order, const struct psif_mmu_cntx *data);
-void write_struct_psif_vlan_union_struct(XFILE *fd, int network_order, const struct psif_vlan_union_struct *data);
-void write_union_psif_cq_desc_vlan_pri(XFILE *fd, int network_order, const union psif_cq_desc_vlan_pri *data);
-void write_struct_psif_wr_common(XFILE *fd, int network_order, const struct psif_wr_common *data);
-void write_struct_psif_wr_qp(XFILE *fd, int network_order, const struct psif_wr_qp *data);
-void write_struct_psif_wr_local(XFILE *fd, int network_order, const struct psif_wr_local *data);
-void write_struct_psif_wr_addr(XFILE *fd, int network_order, const struct psif_wr_addr *data);
-void write_struct_psif_wr_send_header_ud(XFILE *fd, int network_order, const struct psif_wr_send_header_ud *data);
-void write_struct_psif_wr_send_header_uc_rc_xrc(XFILE *fd, int network_order, const struct psif_wr_send_header_uc_rc_xrc *data);
-void write_union_psif_wr_send_header(XFILE *fd, int network_order, const union psif_wr_send_header *data);
-void write_struct_psif_wr_remote(XFILE *fd, int network_order, const struct psif_wr_remote *data);
-void write_struct_psif_wr_rdma(XFILE *fd, int network_order, const struct psif_wr_rdma *data);
-void write_struct_psif_send_completion_id(XFILE *fd, int network_order, const struct psif_send_completion_id *data);
-void write_struct_psif_event_completion_id(XFILE *fd, int network_order, const struct psif_event_completion_id *data);
-void write_union_psif_completion_wc_id(XFILE *fd, int network_order, const union psif_completion_wc_id *data);
-void write_union_psif_descriptor_union(XFILE *fd, int network_order, const union psif_descriptor_union *data);
-void write_struct_psif_wr_su(XFILE *fd, int network_order, const struct psif_wr_su *data);
-void write_union_psif_wr_details(XFILE *fd, int network_order, const union psif_wr_details *data);
-void write_struct_psif_wr_xrc(XFILE *fd, int network_order, const struct psif_wr_xrc *data);
-void write_struct_psif_wr(XFILE *fd, int network_order, const struct psif_wr *data);
-void write_struct_psif_wr_expand(XFILE *fd, int network_order, const struct psif_wr *data);
-void write_struct_psif_next(XFILE *fd, int network_order, const struct psif_next *data);
-void write_struct_psif_sq_sw(XFILE *fd, int network_order, const struct psif_sq_sw *data);
-void write_struct_psif_sq_hw(XFILE *fd, int network_order, const struct psif_sq_hw *data);
-void write_struct_psif_sq_entry(XFILE *fd, int network_order, const struct psif_sq_entry *data);
-void write_struct_psif_rq_scatter(XFILE *fd, int network_order, const struct psif_rq_scatter *data);
-void write_struct_psif_rq_sw(XFILE *fd, int network_order, const struct psif_rq_sw *data);
-void write_struct_psif_rq_hw(XFILE *fd, int network_order, const struct psif_rq_hw *data);
-void write_struct_psif_rq_entry(XFILE *fd, int network_order, const struct psif_rq_entry *data);
-void write_struct_psif_qp_core(XFILE *fd, int network_order, const struct psif_qp_core *data);
-void write_struct_psif_qp_path(XFILE *fd, int network_order, const struct psif_qp_path *data);
-void write_struct_psif_query_qp(XFILE *fd, int network_order, const struct psif_query_qp *data);
-void write_struct_psif_qp(XFILE *fd, int network_order, const struct psif_qp *data);
-void write_struct_psif_cb(XFILE *fd, int network_order, const struct psif_cb *data);
-void write_struct_psif_modify_qp(XFILE *fd, int network_order, const struct psif_modify_qp *data);
-void write_struct_psif_key(XFILE *fd, int network_order, const struct psif_key *data);
-void write_struct_psif_flash_header_app(XFILE *fd, int network_order, const struct psif_flash_header_app *data);
-void write_struct_psif_flash_header_all(XFILE *fd, int network_order, const struct psif_flash_header_all *data);
-void write_struct_psif_eq_entry(XFILE *fd, int network_order, const struct psif_eq_entry *data);
-void write_struct_psif_epsc_exercise_mmu(XFILE *fd, int network_order, const struct psif_epsc_exercise_mmu *data);
-void write_struct_psif_epsc_csr_rsp(XFILE *fd, int network_order, const struct psif_epsc_csr_rsp *data);
-void write_struct_psif_epsc_csr_opaque(XFILE *fd, int network_order, const struct psif_epsc_csr_opaque *data);
-void write_struct_psif_epsc_csr_single(XFILE *fd, int network_order, const struct psif_epsc_csr_single *data);
-void write_struct_psif_epsc_csr_base_addr(XFILE *fd, int network_order, const struct psif_epsc_csr_base_addr *data);
-void write_struct_psif_csr_modify_qp_ctrl(XFILE *fd, int network_order, const struct psif_csr_modify_qp_ctrl *data);
-void write_struct_psif_epsc_csr_modify_qp(XFILE *fd, int network_order, const struct psif_epsc_csr_modify_qp *data);
-void write_struct_psif_epsc_csr_query_qp(XFILE *fd, int network_order, const struct psif_epsc_csr_query_qp *data);
-void write_struct_psif_csr_own_lid_base(XFILE *fd, int network_order, const struct psif_csr_own_lid_base *data);
-void write_struct_psif_csr_snd_lid(XFILE *fd, int network_order, const struct psif_csr_snd_lid *data);
-void write_struct_psif_csr_rcv_lid(XFILE *fd, int network_order, const struct psif_csr_rcv_lid *data);
-void write_struct_psif_epsc_csr_set_lid(XFILE *fd, int network_order, const struct psif_epsc_csr_set_lid *data);
-void write_struct_psif_epsc_csr_set_gid(XFILE *fd, int network_order, const struct psif_epsc_csr_set_gid *data);
-void write_struct_psif_epsc_csr_set_eoib_mac(XFILE *fd, int network_order, const struct psif_epsc_csr_set_eoib_mac *data);
-void write_struct_psif_epsc_csr_vlink_state(XFILE *fd, int network_order, const struct psif_epsc_csr_vlink_state *data);
-void write_struct_psif_epsc_csr_query_hw(XFILE *fd, int network_order, const struct psif_epsc_csr_query_hw *data);
-void write_struct_psif_epsc_csr_query_table(XFILE *fd, int network_order, const struct psif_epsc_csr_query_table *data);
-void write_struct_psif_epsc_csr_mc(XFILE *fd, int network_order, const struct psif_epsc_csr_mc *data);
-void write_struct_psif_epsc_csr_event(XFILE *fd, int network_order, const struct psif_epsc_csr_event *data);
-void write_struct_psif_epsc_csr_modify_device(XFILE *fd, int network_order, const struct psif_epsc_csr_modify_device *data);
-void write_struct_psif_epsc_csr_modify_port(XFILE *fd, int network_order, const struct psif_epsc_csr_modify_port *data);
-void write_struct_psif_epsc_csr_test_host_wrd(XFILE *fd, int network_order, const struct psif_epsc_csr_test_host_wrd *data);
-void write_struct_psif_epsc_csr_flash_access(XFILE *fd, int network_order, const struct psif_epsc_csr_flash_access *data);
-void write_struct_psif_epsc_csr_trace_acquire(XFILE *fd, int network_order, const struct psif_epsc_csr_trace_acquire *data);
-void write_struct_psif_epsc_csr_fw_version(XFILE *fd, int network_order, const struct psif_epsc_csr_fw_version *data);
-void write_struct_psif_epsc_csr_log_ctrl(XFILE *fd, int network_order, const struct psif_epsc_csr_log_ctrl *data);
-void write_struct_psif_epsc_csr_epsa_cntrl(XFILE *fd, int network_order, const struct psif_epsc_csr_epsa_cntrl *data);
-void write_struct_psif_epsc_csr_epsa_cmd(XFILE *fd, int network_order, const struct psif_epsc_csr_epsa_cmd *data);
-void write_struct_psif_epsc_csr_cli_access(XFILE *fd, int network_order, const struct psif_epsc_csr_cli_access *data);
-void write_struct_psif_epsc_csr_mad_process(XFILE *fd, int network_order, const struct psif_epsc_csr_mad_process *data);
-void write_struct_psif_epsc_csr_mad_send_wr(XFILE *fd, int network_order, const struct psif_epsc_csr_mad_send_wr *data);
-void write_struct_psif_epsc_query_req(XFILE *fd, int network_order, const struct psif_epsc_query_req *data);
-void write_struct_psif_epsc_csr_query(XFILE *fd, int network_order, const struct psif_epsc_csr_query *data);
-void write_struct_psif_epsc_csr_set(XFILE *fd, int network_order, const struct psif_epsc_csr_set *data);
-void write_struct_psif_epsc_csr_interrupt_common(XFILE *fd, int network_order, const struct psif_epsc_csr_interrupt_common *data);
-void write_struct_psif_interrupt_attributes(XFILE *fd, int network_order, const struct psif_interrupt_attributes *data);
-void write_struct_psif_epsc_csr_interrupt_channel(XFILE *fd, int network_order, const struct psif_epsc_csr_interrupt_channel *data);
-void write_union_psif_epsc_update_set_or_offset(XFILE *fd, int network_order, const union psif_epsc_update_set_or_offset *data);
-void write_struct_psif_epsc_csr_update(XFILE *fd, int network_order, const struct psif_epsc_csr_update *data);
-void write_struct_psif_epsc_csr_uf_ctrl(XFILE *fd, int network_order, const struct psif_epsc_csr_uf_ctrl *data);
-void write_struct_psif_csr_mmu_flush_caches(XFILE *fd, int network_order, const struct psif_csr_mmu_flush_caches *data);
-void write_struct_psif_epsc_flush_caches(XFILE *fd, int network_order, const struct psif_epsc_flush_caches *data);
-void write_struct_psif_epsc_csr_pma_counters(XFILE *fd, int network_order, const struct psif_epsc_csr_pma_counters *data);
-void write_struct_psif_epsc_vimma_dereg(XFILE *fd, int network_order, const struct psif_epsc_vimma_dereg *data);
-void write_struct_psif_epsc_vimma_vfp_reg(XFILE *fd, int network_order, const struct psif_epsc_vimma_vfp_reg *data);
-void write_struct_psif_epsc_vimma_set_admmode(XFILE *fd, int network_order, const struct psif_epsc_vimma_set_admmode *data);
-void write_struct_psif_epsc_vimma_reg_info(XFILE *fd, int network_order, const struct psif_epsc_vimma_reg_info *data);
-void write_union_psif_epsc_vimma_ctrl_cmd(XFILE *fd, int network_order, const union psif_epsc_vimma_ctrl_cmd *data);
-void write_struct_psif_epsc_csr_vimma_ctrl(XFILE *fd, int network_order, const struct psif_epsc_csr_vimma_ctrl *data);
-void write_union_psif_epsc_csr_details(XFILE *fd, int network_order, const union psif_epsc_csr_details *data);
-void write_struct_psif_epsc_csr_req(XFILE *fd, int network_order, const struct psif_epsc_csr_req *data);
-void write_struct_psif_epsc_csr_req_expand(XFILE *fd, int network_order, const struct psif_epsc_csr_req *data);
-void write_struct_psif_epsc_csr_doorbell(XFILE *fd, int network_order, const struct psif_epsc_csr_doorbell *data);
-void write_struct_psif_cq_sw(XFILE *fd, int network_order, const struct psif_cq_sw *data);
-void write_struct_psif_cq_hw(XFILE *fd, int network_order, const struct psif_cq_hw *data);
-void write_union_psif_seq_num_immdt(XFILE *fd, int network_order, const union psif_seq_num_immdt *data);
-void write_struct_psif_offload_info(XFILE *fd, int network_order, const struct psif_offload_info *data);
-void write_union_psif_offload_wc_id(XFILE *fd, int network_order, const union psif_offload_wc_id *data);
-void write_struct_psif_cq_entry(XFILE *fd, int network_order, const struct psif_cq_entry *data);
-void write_struct_psif_csr_generic(XFILE *fd, int network_order, const struct psif_csr_generic *data);
-void write_struct_psif_base_addr(XFILE *fd, int network_order, const struct psif_base_addr *data);
-void write_struct_psif_ah(XFILE *fd, int network_order, const struct psif_ah *data);
-void write_struct_psif_csr_ibpr_eoib_mac1(XFILE *fd, int network_order, const struct psif_csr_ibpr_eoib_mac1 *data);
+void write_struct_psif_csr_mmu_config(XFILE *fd,
+	int network_order,
+	const struct psif_csr_mmu_config *data);
+void write_struct_psif_mmu_cntx(XFILE *fd,
+	int network_order,
+	const struct psif_mmu_cntx *data);
+void write_struct_psif_vlan_union_struct(XFILE *fd,
+	int network_order,
+	const struct psif_vlan_union_struct *data);
+void write_union_psif_cq_desc_vlan_pri(XFILE *fd,
+	int network_order,
+	const union psif_cq_desc_vlan_pri *data);
+void write_struct_psif_wr_common(XFILE *fd,
+	int network_order,
+	const struct psif_wr_common *data);
+void write_struct_psif_wr_qp(XFILE *fd,
+	int network_order,
+	const struct psif_wr_qp *data);
+void write_struct_psif_wr_local(XFILE *fd,
+	int network_order,
+	const struct psif_wr_local *data);
+void write_struct_psif_wr_addr(XFILE *fd,
+	int network_order,
+	const struct psif_wr_addr *data);
+void write_struct_psif_wr_send_header_ud(XFILE *fd,
+	int network_order,
+	const struct psif_wr_send_header_ud *data);
+void write_struct_psif_wr_send_header_uc_rc_xrc(XFILE *fd,
+	int network_order,
+	const struct psif_wr_send_header_uc_rc_xrc *data);
+void write_union_psif_wr_send_header(XFILE *fd,
+	int network_order,
+	const union psif_wr_send_header *data);
+void write_struct_psif_wr_remote(XFILE *fd,
+	int network_order,
+	const struct psif_wr_remote *data);
+void write_struct_psif_wr_rdma(XFILE *fd,
+	int network_order,
+	const struct psif_wr_rdma *data);
+void write_struct_psif_send_completion_id(XFILE *fd,
+	int network_order,
+	const struct psif_send_completion_id *data);
+void write_struct_psif_event_completion_id(XFILE *fd,
+	int network_order,
+	const struct psif_event_completion_id *data);
+void write_union_psif_completion_wc_id(XFILE *fd,
+	int network_order,
+	const union psif_completion_wc_id *data);
+void write_union_psif_descriptor_union(XFILE *fd,
+	int network_order,
+	const union psif_descriptor_union *data);
+void write_struct_psif_wr_su(XFILE *fd,
+	int network_order,
+	const struct psif_wr_su *data);
+void write_union_psif_wr_details(XFILE *fd,
+	int network_order,
+	const union psif_wr_details *data);
+void write_struct_psif_wr_xrc(XFILE *fd,
+	int network_order,
+	const struct psif_wr_xrc *data);
+void write_struct_psif_wr(XFILE *fd,
+	int network_order,
+	const struct psif_wr *data);
+void write_struct_psif_wr_expand(XFILE *fd,
+	int network_order,
+	const struct psif_wr *data);
+void write_struct_psif_next(XFILE *fd,
+	int network_order,
+	const struct psif_next *data);
+void write_struct_psif_sq_sw(XFILE *fd,
+	int network_order,
+	const struct psif_sq_sw *data);
+void write_struct_psif_sq_hw(XFILE *fd,
+	int network_order,
+	const struct psif_sq_hw *data);
+void write_struct_psif_sq_entry(XFILE *fd,
+	int network_order,
+	const struct psif_sq_entry *data);
+void write_struct_psif_rq_scatter(XFILE *fd,
+	int network_order,
+	const struct psif_rq_scatter *data);
+void write_struct_psif_rq_sw(XFILE *fd,
+	int network_order,
+	const struct psif_rq_sw *data);
+void write_struct_psif_rq_hw(XFILE *fd,
+	int network_order,
+	const struct psif_rq_hw *data);
+void write_struct_psif_rq_entry(XFILE *fd,
+	int network_order,
+	const struct psif_rq_entry *data);
+void write_struct_psif_qp_core(XFILE *fd,
+	int network_order,
+	const struct psif_qp_core *data);
+void write_struct_psif_qp_path(XFILE *fd,
+	int network_order,
+	const struct psif_qp_path *data);
+void write_struct_psif_query_qp(XFILE *fd,
+	int network_order,
+	const struct psif_query_qp *data);
+void write_struct_psif_qp(XFILE *fd,
+	int network_order,
+	const struct psif_qp *data);
+void write_struct_psif_cb(XFILE *fd,
+	int network_order,
+	const struct psif_cb *data);
+void write_struct_psif_modify_qp(XFILE *fd,
+	int network_order,
+	const struct psif_modify_qp *data);
+void write_struct_psif_key(XFILE *fd,
+	int network_order,
+	const struct psif_key *data);
+void write_struct_psif_flash_header_app(XFILE *fd,
+	int network_order,
+	const struct psif_flash_header_app *data);
+void write_struct_psif_flash_header_all(XFILE *fd,
+	int network_order,
+	const struct psif_flash_header_all *data);
+void write_struct_psif_eq_entry(XFILE *fd,
+	int network_order,
+	const struct psif_eq_entry *data);
+void write_struct_psif_epsc_exercise_mmu(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_exercise_mmu *data);
+void write_struct_psif_epsc_csr_rsp(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_rsp *data);
+void write_struct_psif_epsc_csr_opaque(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_opaque *data);
+void write_struct_psif_epsc_csr_single(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_single *data);
+void write_struct_psif_epsc_csr_base_addr(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_base_addr *data);
+void write_struct_psif_csr_modify_qp_ctrl(XFILE *fd,
+	int network_order,
+	const struct psif_csr_modify_qp_ctrl *data);
+void write_struct_psif_epsc_csr_modify_qp(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_modify_qp *data);
+void write_struct_psif_epsc_csr_query_qp(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_query_qp *data);
+void write_struct_psif_csr_own_lid_base(XFILE *fd,
+	int network_order,
+	const struct psif_csr_own_lid_base *data);
+void write_struct_psif_csr_snd_lid(XFILE *fd,
+	int network_order,
+	const struct psif_csr_snd_lid *data);
+void write_struct_psif_csr_rcv_lid(XFILE *fd,
+	int network_order,
+	const struct psif_csr_rcv_lid *data);
+void write_struct_psif_epsc_csr_set_lid(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_set_lid *data);
+void write_struct_psif_epsc_csr_set_gid(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_set_gid *data);
+void write_struct_psif_epsc_csr_set_eoib_mac(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_set_eoib_mac *data);
+void write_struct_psif_epsc_csr_vlink_state(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_vlink_state *data);
+void write_struct_psif_epsc_csr_query_hw(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_query_hw *data);
+void write_struct_psif_epsc_csr_query_table(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_query_table *data);
+void write_struct_psif_epsc_csr_mc(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_mc *data);
+void write_struct_psif_epsc_csr_event(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_event *data);
+void write_struct_psif_epsc_csr_modify_device(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_modify_device *data);
+void write_struct_psif_epsc_csr_modify_port(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_modify_port *data);
+void write_struct_psif_epsc_csr_test_host_wrd(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_test_host_wrd *data);
+void write_struct_psif_epsc_csr_flash_access(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_flash_access *data);
+void write_struct_psif_epsc_csr_trace_acquire(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_trace_acquire *data);
+void write_struct_psif_epsc_csr_fw_version(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_fw_version *data);
+void write_struct_psif_epsc_csr_log_ctrl(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_log_ctrl *data);
+void write_struct_psif_epsc_csr_epsa_cntrl(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_epsa_cntrl *data);
+void write_struct_psif_epsc_csr_epsa_cmd(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_epsa_cmd *data);
+void write_struct_psif_epsc_csr_cli_access(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_cli_access *data);
+void write_struct_psif_epsc_csr_mad_process(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_mad_process *data);
+void write_struct_psif_epsc_csr_mad_send_wr(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_mad_send_wr *data);
+void write_struct_psif_epsc_query_req(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_query_req *data);
+void write_struct_psif_epsc_csr_query(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_query *data);
+void write_struct_psif_epsc_csr_set(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_set *data);
+void write_struct_psif_epsc_csr_interrupt_common(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_interrupt_common *data);
+void write_struct_psif_interrupt_attributes(XFILE *fd,
+	int network_order,
+	const struct psif_interrupt_attributes *data);
+void write_struct_psif_epsc_csr_interrupt_channel(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_interrupt_channel *data);
+void write_union_psif_epsc_update_set_or_offset(XFILE *fd,
+	int network_order,
+	const union psif_epsc_update_set_or_offset *data);
+void write_struct_psif_epsc_csr_update(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_update *data);
+void write_struct_psif_epsc_csr_uf_ctrl(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_uf_ctrl *data);
+void write_struct_psif_csr_mmu_flush_caches(XFILE *fd,
+	int network_order,
+	const struct psif_csr_mmu_flush_caches *data);
+void write_struct_psif_epsc_flush_caches(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_flush_caches *data);
+void write_struct_psif_epsc_csr_pma_counters(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_pma_counters *data);
+void write_struct_psif_epsc_vimma_dereg(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_vimma_dereg *data);
+void write_struct_psif_epsc_vimma_vfp_reg(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_vimma_vfp_reg *data);
+void write_struct_psif_epsc_vimma_set_admmode(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_vimma_set_admmode *data);
+void write_struct_psif_epsc_vimma_reg_info(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_vimma_reg_info *data);
+void write_union_psif_epsc_vimma_ctrl_cmd(XFILE *fd,
+	int network_order,
+	const union psif_epsc_vimma_ctrl_cmd *data);
+void write_struct_psif_epsc_csr_vimma_ctrl(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_vimma_ctrl *data);
+void write_struct_psif_epsc_csr_ber_data(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_ber_data *data);
+void write_union_psif_epsc_csr_details(XFILE *fd,
+	int network_order,
+	const union psif_epsc_csr_details *data);
+void write_struct_psif_epsc_csr_req(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_req *data);
+void write_struct_psif_epsc_csr_req_expand(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_req *data);
+void write_struct_psif_epsc_csr_doorbell(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_doorbell *data);
+void write_struct_psif_cq_sw(XFILE *fd,
+	int network_order,
+	const struct psif_cq_sw *data);
+void write_struct_psif_cq_hw(XFILE *fd,
+	int network_order,
+	const struct psif_cq_hw *data);
+void write_union_psif_seq_num_immdt(XFILE *fd,
+	int network_order,
+	const union psif_seq_num_immdt *data);
+void write_struct_psif_offload_info(XFILE *fd,
+	int network_order,
+	const struct psif_offload_info *data);
+void write_union_psif_offload_wc_id(XFILE *fd,
+	int network_order,
+	const union psif_offload_wc_id *data);
+void write_struct_psif_cq_entry(XFILE *fd,
+	int network_order,
+	const struct psif_cq_entry *data);
+void write_struct_psif_csr_generic(XFILE *fd,
+	int network_order,
+	const struct psif_csr_generic *data);
+void write_struct_psif_base_addr(XFILE *fd,
+	int network_order,
+	const struct psif_base_addr *data);
+void write_struct_psif_ah(XFILE *fd,
+	int network_order,
+	const struct psif_ah *data);
+void write_struct_psif_csr_ibpr_eoib_mac1(XFILE *fd,
+	int network_order,
+	const struct psif_csr_ibpr_eoib_mac1 *data);
 
 #endif /* !defined(PSIF_EXCLUDE_WRITE_STRUCTS) */
 
--- a/components/open-fabrics/libsif/include/psifapi/psif_hw_setget.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_setget.h	Mon Oct 17 23:20:28 2016 -0700
@@ -3,8 +3,8 @@
  */
 
 /*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimer.
@@ -14,19 +14,20 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef	_PSIF_HW_SETGET_H
@@ -42,12 +43,51 @@
 #include "epsfw_misc.h"
 #  define htobe64(x) eps_htobe64(x)
 #  define be64toh(x) eps_be64toh(x)
+#  define htobe32(x) eps_htobe32(x)
+#  define be32toh(x) eps_be32toh(x)
+#  define htobe16(x) eps_htobe16(x)
+#  define be16toh(x) eps_be16toh(x)
+#  define cpu_to_be64(x) htobe64(x)
+#  define be64_to_cpu(x) be64toh(x)
+#  define cpu_to_be32(x) htobe32(x)
+#  define be32_to_cpu(x) be32toh(x)
+#  define cpu_to_be16(x) htobe16(x)
+#  define be16_to_cpu(x) be16toh(x)
 #endif /* __arm__ */
 #include "psif_endian.h"
-#if !defined(__KERNEL__)
 #include "os_header.h"
-#endif
 
+static inline void set_psif_csr_mmu_config__ta_upper_twelve(
+	volatile struct psif_csr_mmu_config *ptr,
+	u16 data)
+{
+	/* group=0 shift=32 bits=12 */
+	volatile __be64 *const pte = (__be64 *)ptr;
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xfffff000ffffffffull) |
+		((((u64)(data)) & 0x0000000000000fffull) << 32));
+}
+static inline u16 get_psif_csr_mmu_config__ta_upper_twelve(volatile struct psif_csr_mmu_config *ptr)
+{
+	/* group=0 shift=32 bits=12 */
+	volatile __be64 *const pte = (__be64 *)ptr;
+	return((u16)((be64_to_cpu(pte[0]) >> 32) & 0x0000000000000fffull));
+}
+
+static inline void set_psif_csr_mmu_config__pa_upper_twelve(
+	volatile struct psif_csr_mmu_config *ptr,
+	u16 data)
+{
+	/* group=0 shift=48 bits=12 */
+	volatile __be64 *const pte = (__be64 *)ptr;
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xf000ffffffffffffull) |
+		((((u64)(data)) & 0x0000000000000fffull) << 48));
+}
+static inline u16 get_psif_csr_mmu_config__pa_upper_twelve(volatile struct psif_csr_mmu_config *ptr)
+{
+	/* group=0 shift=48 bits=12 */
+	volatile __be64 *const pte = (__be64 *)ptr;
+	return((u16)((be64_to_cpu(pte[0]) >> 48) & 0x0000000000000fffull));
+}
 
 /*
  * PSIF_WR_INVALIDATE_LKEY: key to invalidate/flush from the DMA VT cache.
@@ -56,87 +96,94 @@
  * cache. PSIF_WR_INVALIDATE_TLB: this is the address vector to invalidate in
  * the TLB.
  */
-static inline void set_psif_wr_su__key(volatile struct psif_wr_su *ptr, u32 data)
+static inline void set_psif_wr_su__key(
+	volatile struct psif_wr_su *ptr,
+	u32 data)
 {
 	/* group=2 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0x00000000ffffffffull) | 
-		((((u64)(data)) & 0x00000000ffffffffull) << 32));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 2) + 0);
+	*pte = cpu_to_be32(data);
 }
 static inline u32 get_psif_wr_su__key(volatile struct psif_wr_su *ptr)
 {
 	/* group=2 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[2]) >> 32) & 0x00000000ffffffffull));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 2) + 0);
+	return((u32)be32_to_cpu(*pte));
 }
 
 /*
  * Send queue sequence number. Used to map request to a particular work
  * request in the send queue.
  */
-static inline void set_psif_wr__sq_seq(volatile struct psif_wr *ptr, u16 data)
+static inline void set_psif_wr__sq_seq(
+	volatile struct psif_wr *ptr,
+	u16 data)
 {
 	/* group=0 shift=0 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xffffffffffff0000ull) | 
-		((((u64)(data)) & 0x000000000000ffffull) << 0));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 0) + 6);
+	*pte = cpu_to_be16(data);
 }
 static inline u16 get_psif_wr__sq_seq(volatile struct psif_wr *ptr)
 {
 	/* group=0 shift=0 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[0]) >> 0) & 0x000000000000ffffull));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 0) + 6);
+	return((u16)be16_to_cpu(*pte));
 }
 
 /*
  * QP sending this request. XXX: Should name be own_qp_num as defined in QP
  * state?
  */
-static inline void set_psif_wr__local_qp(volatile struct psif_wr *ptr, u32 data)
+static inline void set_psif_wr__local_qp(
+	volatile struct psif_wr *ptr,
+	u32 data)
 {
 	/* group=0 shift=32 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xff000000ffffffffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xff000000ffffffffull) |
 		((((u64)(data)) & 0x0000000000ffffffull) << 32));
 }
 static inline u32 get_psif_wr__local_qp(volatile struct psif_wr *ptr)
 {
 	/* group=0 shift=32 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[0]) >> 32) & 0x0000000000ffffffull));
+	return((u32)((be64_to_cpu(pte[0]) >> 32) & 0x0000000000ffffffull));
 }
 
 /* Completion notification identifier. */
-static inline void set_psif_wr__completion(volatile struct psif_wr *ptr, u8 data)
+static inline void set_psif_wr__completion(
+	volatile struct psif_wr *ptr,
+	u8 data)
 {
 	/* group=1 shift=31 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[1] = htobe64((be64toh(pte[1]) & 0xffffffff7fffffffull) | 
+	pte[1] = cpu_to_be64((be64_to_cpu(pte[1]) & 0xffffffff7fffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 31));
 }
 static inline u8 get_psif_wr__completion(volatile struct psif_wr *ptr)
 {
 	/* group=1 shift=31 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[1]) >> 31) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[1]) >> 31) & 0x0000000000000001ull));
 }
 
 /*
  * Checksum used for data protection and consistency between work request and
  * QP state.
  */
-static inline void set_psif_wr__checksum(volatile struct psif_wr *ptr, u32 data)
+static inline void set_psif_wr__checksum(
+	volatile struct psif_wr *ptr,
+	u32 data)
 {
 	/* group=2 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0x00000000ffffffffull) | 
-		((((u64)(data)) & 0x00000000ffffffffull) << 32));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 2) + 0);
+	*pte = cpu_to_be32(data);
 }
 static inline u32 get_psif_wr__checksum(volatile struct psif_wr *ptr)
 {
 	/* group=2 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[2]) >> 32) & 0x00000000ffffffffull));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 2) + 0);
+	return((u32)be32_to_cpu(*pte));
 }
 
 /*
@@ -145,18 +192,19 @@
  * queue. I.e. SW needs to keep track of the head_index so it doesn't
  * overwrite entries in the send queue which is not yet completed.
  */
-static inline void set_psif_sq_sw__tail_indx(volatile struct psif_sq_sw *ptr, u16 data)
+static inline void set_psif_sq_sw__tail_indx(
+	volatile struct psif_sq_sw *ptr,
+	u16 data)
 {
 	/* group=0 shift=32 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xffff0000ffffffffull) | 
-		((((u64)(data)) & 0x000000000000ffffull) << 32));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 0) + 2);
+	*pte = cpu_to_be16(data);
 }
 static inline u16 get_psif_sq_sw__tail_indx(volatile struct psif_sq_sw *ptr)
 {
 	/* group=0 shift=32 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[0]) >> 32) & 0x000000000000ffffull));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 0) + 2);
+	return((u16)be16_to_cpu(*pte));
 }
 
 /*
@@ -167,116 +215,128 @@
  * This is also used as tail_index when checking if there are more elements
  * in the send queue.
  */
-static inline void set_psif_sq_hw__last_seq(volatile struct psif_sq_hw *ptr, u16 data)
+static inline void set_psif_sq_hw__last_seq(
+	volatile struct psif_sq_hw *ptr,
+	u16 data)
 {
 	/* group=0 shift=16 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xffffffff0000ffffull) | 
-		((((u64)(data)) & 0x000000000000ffffull) << 16));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 0) + 4);
+	*pte = cpu_to_be16(data);
 }
 static inline u16 get_psif_sq_hw__last_seq(volatile struct psif_sq_hw *ptr)
 {
 	/* group=0 shift=16 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[0]) >> 16) & 0x000000000000ffffull));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 0) + 4);
+	return((u16)be16_to_cpu(*pte));
 }
 
 /* QP and UF to be processed next. */
-static inline void set_psif_sq_hw__sq_next(volatile struct psif_sq_hw *ptr, u32 data)
+static inline void set_psif_sq_hw__sq_next(
+	volatile struct psif_sq_hw *ptr,
+	u32 data)
 {
 	/* group=0 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0x00000000ffffffffull) | 
-		((((u64)(data)) & 0x00000000ffffffffull) << 32));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	*pte = cpu_to_be32(data);
 }
 static inline u32 get_psif_sq_hw__sq_next(volatile struct psif_sq_hw *ptr)
 {
 	/* group=0 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[0]) >> 32) & 0x00000000ffffffffull));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	return((u32)be32_to_cpu(*pte));
 }
 
 /*
  * This bit is set through the doorbell. SW should check this bit plus
  * psif_next = null to ensure SW can own the SQ descriptor.
  */
-static inline void set_psif_sq_hw__destroyed(volatile struct psif_sq_hw *ptr, u8 data)
+static inline void set_psif_sq_hw__destroyed(
+	volatile struct psif_sq_hw *ptr,
+	u8 data)
 {
 	/* group=1 shift=27 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[1] = htobe64((be64toh(pte[1]) & 0xfffffffff7ffffffull) | 
+	pte[1] = cpu_to_be64((be64_to_cpu(pte[1]) & 0xfffffffff7ffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 27));
 }
 static inline u8 get_psif_sq_hw__destroyed(volatile struct psif_sq_hw *ptr)
 {
 	/* group=1 shift=27 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[1]) >> 27) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[1]) >> 27) & 0x0000000000000001ull));
 }
 
 /* Software modified index pointing to the tail reecive entry in host memory. */
-static inline void set_psif_rq_sw__tail_indx(volatile struct psif_rq_sw *ptr, u16 data)
+static inline void set_psif_rq_sw__tail_indx(
+	volatile struct psif_rq_sw *ptr,
+	u16 data)
 {
 	/* group=0 shift=32 bits=14 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xffffc000ffffffffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xffffc000ffffffffull) |
 		((((u64)(data)) & 0x0000000000003fffull) << 32));
 }
 static inline u16 get_psif_rq_sw__tail_indx(volatile struct psif_rq_sw *ptr)
 {
 	/* group=0 shift=32 bits=14 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[0]) >> 32) & 0x0000000000003fffull));
+	return((u16)((be64_to_cpu(pte[0]) >> 32) & 0x0000000000003fffull));
 }
 
 /*
  * Hardware modified index pointing to the head of the receive queue. TSU is
  * using this to find the address of the receive queue entry.
  */
-static inline void set_psif_rq_hw__head_indx(volatile struct psif_rq_hw *ptr, u16 data)
+static inline void set_psif_rq_hw__head_indx(
+	volatile struct psif_rq_hw *ptr,
+	u16 data)
 {
 	/* group=0 shift=14 bits=14 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xfffffffff0003fffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xfffffffff0003fffull) |
 		((((u64)(data)) & 0x0000000000003fffull) << 14));
 }
 static inline u16 get_psif_rq_hw__head_indx(volatile struct psif_rq_hw *ptr)
 {
 	/* group=0 shift=14 bits=14 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[0]) >> 14) & 0x0000000000003fffull));
+	return((u16)((be64_to_cpu(pte[0]) >> 14) & 0x0000000000003fffull));
 }
 
 /* The desciptor is valid. */
-static inline void set_psif_rq_hw__valid(volatile struct psif_rq_hw *ptr, u8 data)
+static inline void set_psif_rq_hw__valid(
+	volatile struct psif_rq_hw *ptr,
+	u8 data)
 {
 	/* group=3 shift=55 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[3] = htobe64((be64toh(pte[3]) & 0xff7fffffffffffffull) | 
+	pte[3] = cpu_to_be64((be64_to_cpu(pte[3]) & 0xff7fffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 55));
 }
 static inline u8 get_psif_rq_hw__valid(volatile struct psif_rq_hw *ptr)
 {
 	/* group=3 shift=55 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[3]) >> 55) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[3]) >> 55) & 0x0000000000000001ull));
 }
 
 /*
  * Receive queue entry ID. This is added to the receive completion using this
  * receive queue entry.
  */
-static inline void set_psif_rq_entry__rqe_id(volatile struct psif_rq_entry *ptr, u64 data)
+static inline void set_psif_rq_entry__rqe_id(
+	volatile struct psif_rq_entry *ptr,
+	u64 data)
 {
 	/* group=0 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((__be64)data);
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	*pte = cpu_to_be64(data);
 }
 static inline u64 get_psif_rq_entry__rqe_id(volatile struct psif_rq_entry *ptr)
 {
 	/* group=0 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u64)be64toh(pte[0]));
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	return((u64)be64_to_cpu(*pte));
 }
 
 /*
@@ -285,18 +345,20 @@
  * whenever the sq_sequence_number in QP state is equal to the one in the
  * request.
  */
-static inline void set_psif_qp_core__retry_tag_committed(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__retry_tag_committed(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=0 shift=0 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xfffffffffffffff8ull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xfffffffffffffff8ull) |
 		((((u64)(data)) & 0x0000000000000007ull) << 0));
 }
 static inline u8 get_psif_qp_core__retry_tag_committed(volatile struct psif_qp_core *ptr)
 {
 	/* group=0 shift=0 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[0]) >> 0) & 0x0000000000000007ull));
+	return((u8)((be64_to_cpu(pte[0]) >> 0) & 0x0000000000000007ull));
 }
 
 /*
@@ -307,36 +369,40 @@
  * request. The sq_sequence_number has been updated by tsu_err at the same
  * time the retry_tag_err is updated.
  */
-static inline void set_psif_qp_core__retry_tag_err(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__retry_tag_err(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=0 shift=3 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xffffffffffffffc7ull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xffffffffffffffc7ull) |
 		((((u64)(data)) & 0x0000000000000007ull) << 3));
 }
 static inline u8 get_psif_qp_core__retry_tag_err(volatile struct psif_qp_core *ptr)
 {
 	/* group=0 shift=3 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[0]) >> 3) & 0x0000000000000007ull));
+	return((u8)((be64_to_cpu(pte[0]) >> 3) & 0x0000000000000007ull));
 }
 
 /*
  * Error retry counter initial value. Read by tsu_dma and used by tsu_cmpl to
  * calculate exp_backoff etc..
  */
-static inline void set_psif_qp_core__error_retry_init(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__error_retry_init(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=0 shift=32 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xfffffff8ffffffffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xfffffff8ffffffffull) |
 		((((u64)(data)) & 0x0000000000000007ull) << 32));
 }
 static inline u8 get_psif_qp_core__error_retry_init(volatile struct psif_qp_core *ptr)
 {
 	/* group=0 shift=32 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[0]) >> 32) & 0x0000000000000007ull));
+	return((u8)((be64_to_cpu(pte[0]) >> 32) & 0x0000000000000007ull));
 }
 
 /*
@@ -344,33 +410,37 @@
  * it expires, a path migration will be attempted if it is armed, or the QP
  * will go to error state. Read by tsu_dma and used by tsu_cmpl.
  */
-static inline void set_psif_qp_core__error_retry_count(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__error_retry_count(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=0 shift=35 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xffffffc7ffffffffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xffffffc7ffffffffull) |
 		((((u64)(data)) & 0x0000000000000007ull) << 35));
 }
 static inline u8 get_psif_qp_core__error_retry_count(volatile struct psif_qp_core *ptr)
 {
 	/* group=0 shift=35 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[0]) >> 35) & 0x0000000000000007ull));
+	return((u8)((be64_to_cpu(pte[0]) >> 35) & 0x0000000000000007ull));
 }
 
 /* A hit in the set locally spun out of tsu_cmpl is found. */
-static inline void set_psif_qp_core__spin_hit(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__spin_hit(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=0 shift=39 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xffffff7fffffffffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xffffff7fffffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 39));
 }
 static inline u8 get_psif_qp_core__spin_hit(volatile struct psif_qp_core *ptr)
 {
 	/* group=0 shift=39 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[0]) >> 39) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[0]) >> 39) & 0x0000000000000001ull));
 }
 
 /*
@@ -378,76 +448,84 @@
  * receiving the RNR NAK must wait until the timer has expired before the
  * retry is sent.
  */
-static inline void set_psif_qp_core__min_rnr_nak_time(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__min_rnr_nak_time(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=1 shift=0 bits=5 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[1] = htobe64((be64toh(pte[1]) & 0xffffffffffffffe0ull) | 
+	pte[1] = cpu_to_be64((be64_to_cpu(pte[1]) & 0xffffffffffffffe0ull) |
 		((((u64)(data)) & 0x000000000000001full) << 0));
 }
 static inline u8 get_psif_qp_core__min_rnr_nak_time(volatile struct psif_qp_core *ptr)
 {
 	/* group=1 shift=0 bits=5 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[1]) >> 0) & 0x000000000000001full));
+	return((u8)((be64_to_cpu(pte[1]) >> 0) & 0x000000000000001full));
 }
 
 /* QP State for this QP. */
-static inline void set_psif_qp_core__state(volatile struct psif_qp_core *ptr, enum psif_qp_state data)
+static inline void set_psif_qp_core__state(
+	volatile struct psif_qp_core *ptr,
+	enum psif_qp_state data)
 {
 	/* group=1 shift=5 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[1] = htobe64((be64toh(pte[1]) & 0xffffffffffffff1full) | 
+	pte[1] = cpu_to_be64((be64_to_cpu(pte[1]) & 0xffffffffffffff1full) |
 		((((u64)(data)) & 0x0000000000000007ull) << 5));
 }
 static inline enum psif_qp_state get_psif_qp_core__state(volatile struct psif_qp_core *ptr)
 {
 	/* group=1 shift=5 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_qp_state)((be64toh(pte[1]) >> 5) & 0x0000000000000007ull));
+	return((enum psif_qp_state)((be64_to_cpu(pte[1]) >> 5) & 0x0000000000000007ull));
 }
 
 /* QP number for the remote node. */
-static inline void set_psif_qp_core__remote_qp(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__remote_qp(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=1 shift=8 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[1] = htobe64((be64toh(pte[1]) & 0xffffffff000000ffull) | 
+	pte[1] = cpu_to_be64((be64_to_cpu(pte[1]) & 0xffffffff000000ffull) |
 		((((u64)(data)) & 0x0000000000ffffffull) << 8));
 }
 static inline u32 get_psif_qp_core__remote_qp(volatile struct psif_qp_core *ptr)
 {
 	/* group=1 shift=8 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[1]) >> 8) & 0x0000000000ffffffull));
+	return((u32)((be64_to_cpu(pte[1]) >> 8) & 0x0000000000ffffffull));
 }
 
-static inline void set_psif_qp_core__retry_sq_seq(volatile struct psif_qp_core *ptr, u16 data)
+static inline void set_psif_qp_core__retry_sq_seq(
+	volatile struct psif_qp_core *ptr,
+	u16 data)
 {
 	/* group=2 shift=32 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0xffff0000ffffffffull) | 
-		((((u64)(data)) & 0x000000000000ffffull) << 32));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 2) + 2);
+	*pte = cpu_to_be16(data);
 }
 static inline u16 get_psif_qp_core__retry_sq_seq(volatile struct psif_qp_core *ptr)
 {
 	/* group=2 shift=32 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[2]) >> 32) & 0x000000000000ffffull));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 2) + 2);
+	return((u16)be16_to_cpu(*pte));
 }
 
-static inline void set_psif_qp_core__sq_seq(volatile struct psif_qp_core *ptr, u16 data)
+static inline void set_psif_qp_core__sq_seq(
+	volatile struct psif_qp_core *ptr,
+	u16 data)
 {
 	/* group=2 shift=48 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0x0000ffffffffffffull) | 
-		((((u64)(data)) & 0x000000000000ffffull) << 48));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 2) + 0);
+	*pte = cpu_to_be16(data);
 }
 static inline u16 get_psif_qp_core__sq_seq(volatile struct psif_qp_core *ptr)
 {
 	/* group=2 shift=48 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[2]) >> 48) & 0x000000000000ffffull));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 2) + 0);
+	return((u16)be16_to_cpu(*pte));
 }
 
 /*
@@ -455,86 +533,94 @@
  * checksum of the work request incorporating the magic number. This checksum
  * is checked against the checksum in the work request.
  */
-static inline void set_psif_qp_core__magic(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__magic(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=3 shift=0 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[3] = htobe64((be64toh(pte[3]) & 0xffffffff00000000ull) | 
-		((((u64)(data)) & 0x00000000ffffffffull) << 0));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 3) + 4);
+	*pte = cpu_to_be32(data);
 }
 static inline u32 get_psif_qp_core__magic(volatile struct psif_qp_core *ptr)
 {
 	/* group=3 shift=0 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[3]) >> 0) & 0x00000000ffffffffull));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 3) + 4);
+	return((u32)be32_to_cpu(*pte));
 }
 
 /*
  * Q-Key received in incoming IB packet is checked towards this Q-Key. Q-Key
  * used on transmit if top bit of Q-Key in WR is set.
  */
-static inline void set_psif_qp_core__qkey(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__qkey(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=4 shift=0 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[4] = htobe64((be64toh(pte[4]) & 0xffffffff00000000ull) | 
-		((((u64)(data)) & 0x00000000ffffffffull) << 0));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 4) + 4);
+	*pte = cpu_to_be32(data);
 }
 static inline u32 get_psif_qp_core__qkey(volatile struct psif_qp_core *ptr)
 {
 	/* group=4 shift=0 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[4]) >> 0) & 0x00000000ffffffffull));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 4) + 4);
+	return((u32)be32_to_cpu(*pte));
 }
 
 /*
  * Sequence number of the last ACK received. Read and written by tsu_cmpl.
  * Used to verify that the received response packet is a valid response.
  */
-static inline void set_psif_qp_core__last_acked_psn(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__last_acked_psn(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=4 shift=40 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[4] = htobe64((be64toh(pte[4]) & 0x000000ffffffffffull) | 
+	pte[4] = cpu_to_be64((be64_to_cpu(pte[4]) & 0x000000ffffffffffull) |
 		((((u64)(data)) & 0x0000000000ffffffull) << 40));
 }
 static inline u32 get_psif_qp_core__last_acked_psn(volatile struct psif_qp_core *ptr)
 {
 	/* group=4 shift=40 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[4]) >> 40) & 0x0000000000ffffffull));
+	return((u32)((be64_to_cpu(pte[4]) >> 40) & 0x0000000000ffffffull));
 }
 
 /* Index to scatter element of in progress SEND. */
-static inline void set_psif_qp_core__scatter_indx(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__scatter_indx(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=5 shift=32 bits=5 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[5] = htobe64((be64toh(pte[5]) & 0xffffffe0ffffffffull) | 
+	pte[5] = cpu_to_be64((be64_to_cpu(pte[5]) & 0xffffffe0ffffffffull) |
 		((((u64)(data)) & 0x000000000000001full) << 32));
 }
 static inline u8 get_psif_qp_core__scatter_indx(volatile struct psif_qp_core *ptr)
 {
 	/* group=5 shift=32 bits=5 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[5]) >> 32) & 0x000000000000001full));
+	return((u8)((be64_to_cpu(pte[5]) >> 32) & 0x000000000000001full));
 }
 
 /*
  * Expected packet sequence number: Sequence number on next expected packet.
  */
-static inline void set_psif_qp_core__expected_psn(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__expected_psn(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=5 shift=40 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[5] = htobe64((be64toh(pte[5]) & 0x000000ffffffffffull) | 
+	pte[5] = cpu_to_be64((be64_to_cpu(pte[5]) & 0x000000ffffffffffull) |
 		((((u64)(data)) & 0x0000000000ffffffull) << 40));
 }
 static inline u32 get_psif_qp_core__expected_psn(volatile struct psif_qp_core *ptr)
 {
 	/* group=5 shift=40 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[5]) >> 40) & 0x0000000000ffffffull));
+	return((u32)((be64_to_cpu(pte[5]) >> 40) & 0x0000000000ffffffull));
 }
 
 /*
@@ -544,18 +630,20 @@
  * QP state, otherwise the QP must be put in error. This check only applies
  * to tsu_rqs.
  */
-static inline void set_psif_qp_core__qosl(volatile struct psif_qp_core *ptr, enum psif_tsu_qos data)
+static inline void set_psif_qp_core__qosl(
+	volatile struct psif_qp_core *ptr,
+	enum psif_tsu_qos data)
 {
 	/* group=6 shift=49 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[6] = htobe64((be64toh(pte[6]) & 0xfffdffffffffffffull) | 
+	pte[6] = cpu_to_be64((be64_to_cpu(pte[6]) & 0xfffdffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 49));
 }
 static inline enum psif_tsu_qos get_psif_qp_core__qosl(volatile struct psif_qp_core *ptr)
 {
 	/* group=6 shift=49 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_tsu_qos)((be64toh(pte[6]) >> 49) & 0x0000000000000001ull));
+	return((enum psif_tsu_qos)((be64_to_cpu(pte[6]) >> 49) & 0x0000000000000001ull));
 }
 
 /*
@@ -563,147 +651,165 @@
  * handled by tsu_qps, this is controlled by tsu_qps. XXX: Should error
  * handler also be able to change the path?
  */
-static inline void set_psif_qp_core__mstate(volatile struct psif_qp_core *ptr, enum psif_migration data)
+static inline void set_psif_qp_core__mstate(
+	volatile struct psif_qp_core *ptr,
+	enum psif_migration data)
 {
 	/* group=6 shift=50 bits=2 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[6] = htobe64((be64toh(pte[6]) & 0xfff3ffffffffffffull) | 
+	pte[6] = cpu_to_be64((be64_to_cpu(pte[6]) & 0xfff3ffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000003ull) << 50));
 }
 static inline enum psif_migration get_psif_qp_core__mstate(volatile struct psif_qp_core *ptr)
 {
 	/* group=6 shift=50 bits=2 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_migration)((be64toh(pte[6]) >> 50) & 0x0000000000000003ull));
+	return((enum psif_migration)((be64_to_cpu(pte[6]) >> 50) & 0x0000000000000003ull));
 }
 
 /* This is an IB over IB QP. */
-static inline void set_psif_qp_core__ipoib_enable(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__ipoib_enable(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=6 shift=53 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[6] = htobe64((be64toh(pte[6]) & 0xffdfffffffffffffull) | 
+	pte[6] = cpu_to_be64((be64_to_cpu(pte[6]) & 0xffdfffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 53));
 }
 static inline u8 get_psif_qp_core__ipoib_enable(volatile struct psif_qp_core *ptr)
 {
 	/* group=6 shift=53 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[6]) >> 53) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[6]) >> 53) & 0x0000000000000001ull));
 }
 
 /* IB defined capability enable for receiving Atomic operations. */
-static inline void set_psif_qp_core__atomic_enable(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__atomic_enable(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=6 shift=61 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[6] = htobe64((be64toh(pte[6]) & 0xdfffffffffffffffull) | 
+	pte[6] = cpu_to_be64((be64_to_cpu(pte[6]) & 0xdfffffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 61));
 }
 static inline u8 get_psif_qp_core__atomic_enable(volatile struct psif_qp_core *ptr)
 {
 	/* group=6 shift=61 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[6]) >> 61) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[6]) >> 61) & 0x0000000000000001ull));
 }
 
 /* IB defined capability enable for receiving RDMA WR. */
-static inline void set_psif_qp_core__rdma_wr_enable(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__rdma_wr_enable(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=6 shift=62 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[6] = htobe64((be64toh(pte[6]) & 0xbfffffffffffffffull) | 
+	pte[6] = cpu_to_be64((be64_to_cpu(pte[6]) & 0xbfffffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 62));
 }
 static inline u8 get_psif_qp_core__rdma_wr_enable(volatile struct psif_qp_core *ptr)
 {
 	/* group=6 shift=62 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[6]) >> 62) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[6]) >> 62) & 0x0000000000000001ull));
 }
 
 /* IB defined capability enable for receiving RDMA RD. */
-static inline void set_psif_qp_core__rdma_rd_enable(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__rdma_rd_enable(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=6 shift=63 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[6] = htobe64((be64toh(pte[6]) & 0x7fffffffffffffffull) | 
+	pte[6] = cpu_to_be64((be64_to_cpu(pte[6]) & 0x7fffffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 63));
 }
 static inline u8 get_psif_qp_core__rdma_rd_enable(volatile struct psif_qp_core *ptr)
 {
 	/* group=6 shift=63 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[6]) >> 63) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[6]) >> 63) & 0x0000000000000001ull));
 }
 
 /*
  * Transmit packet sequence number. Read and updated by tsu_dma before
  * sending packets to tsu_ibpb and tsu_cmpl.
  */
-static inline void set_psif_qp_core__xmit_psn(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__xmit_psn(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=7 shift=0 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[7] = htobe64((be64toh(pte[7]) & 0xffffffffff000000ull) | 
+	pte[7] = cpu_to_be64((be64_to_cpu(pte[7]) & 0xffffffffff000000ull) |
 		((((u64)(data)) & 0x0000000000ffffffull) << 0));
 }
 static inline u32 get_psif_qp_core__xmit_psn(volatile struct psif_qp_core *ptr)
 {
 	/* group=7 shift=0 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[7]) >> 0) & 0x0000000000ffffffull));
+	return((u32)((be64_to_cpu(pte[7]) >> 0) & 0x0000000000ffffffull));
 }
 
 /*
  * TSU Service Level used to decide the TSU VL for requests associated with
  * this QP.
  */
-static inline void set_psif_qp_core__tsl(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__tsl(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=7 shift=55 bits=4 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[7] = htobe64((be64toh(pte[7]) & 0xf87fffffffffffffull) | 
+	pte[7] = cpu_to_be64((be64_to_cpu(pte[7]) & 0xf87fffffffffffffull) |
 		((((u64)(data)) & 0x000000000000000full) << 55));
 }
 static inline u8 get_psif_qp_core__tsl(volatile struct psif_qp_core *ptr)
 {
 	/* group=7 shift=55 bits=4 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[7]) >> 55) & 0x000000000000000full));
+	return((u8)((be64_to_cpu(pte[7]) >> 55) & 0x000000000000000full));
 }
 
 /*
  * Maximum number of outstanding read or atomic requests allowed by the
  * remote HCA. Initialized by software.
  */
-static inline void set_psif_qp_core__max_outstanding(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__max_outstanding(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=7 shift=59 bits=5 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[7] = htobe64((be64toh(pte[7]) & 0x07ffffffffffffffull) | 
+	pte[7] = cpu_to_be64((be64_to_cpu(pte[7]) & 0x07ffffffffffffffull) |
 		((((u64)(data)) & 0x000000000000001full) << 59));
 }
 static inline u8 get_psif_qp_core__max_outstanding(volatile struct psif_qp_core *ptr)
 {
 	/* group=7 shift=59 bits=5 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[7]) >> 59) & 0x000000000000001full));
+	return((u8)((be64_to_cpu(pte[7]) >> 59) & 0x000000000000001full));
 }
 
 /* Send Queue RNR retry count initialization value. */
-static inline void set_psif_qp_core__rnr_retry_init(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__rnr_retry_init(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=8 shift=32 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[8] = htobe64((be64toh(pte[8]) & 0xfffffff8ffffffffull) | 
+	pte[8] = cpu_to_be64((be64_to_cpu(pte[8]) & 0xfffffff8ffffffffull) |
 		((((u64)(data)) & 0x0000000000000007ull) << 32));
 }
 static inline u8 get_psif_qp_core__rnr_retry_init(volatile struct psif_qp_core *ptr)
 {
 	/* group=8 shift=32 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[8]) >> 32) & 0x0000000000000007ull));
+	return((u8)((be64_to_cpu(pte[8]) >> 32) & 0x0000000000000007ull));
 }
 
 /*
@@ -711,18 +817,20 @@
  * migration will be attempted if it is armed, or the QP will go to error
  * state.
  */
-static inline void set_psif_qp_core__rnr_retry_count(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__rnr_retry_count(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=8 shift=35 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[8] = htobe64((be64toh(pte[8]) & 0xffffffc7ffffffffull) | 
+	pte[8] = cpu_to_be64((be64_to_cpu(pte[8]) & 0xffffffc7ffffffffull) |
 		((((u64)(data)) & 0x0000000000000007ull) << 35));
 }
 static inline u8 get_psif_qp_core__rnr_retry_count(volatile struct psif_qp_core *ptr)
 {
 	/* group=8 shift=35 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[8]) >> 35) & 0x0000000000000007ull));
+	return((u8)((be64_to_cpu(pte[8]) >> 35) & 0x0000000000000007ull));
 }
 
 /*
@@ -730,36 +838,63 @@
  * number. When not set, RQS should perform the checksum check towards the
  * checksum in the psif_wr.
  */
-static inline void set_psif_qp_core__no_checksum(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__no_checksum(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=8 shift=39 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[8] = htobe64((be64toh(pte[8]) & 0xffffff7fffffffffull) | 
+	pte[8] = cpu_to_be64((be64_to_cpu(pte[8]) & 0xffffff7fffffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 39));
 }
 static inline u8 get_psif_qp_core__no_checksum(volatile struct psif_qp_core *ptr)
 {
 	/* group=8 shift=39 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[8]) >> 39) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[8]) >> 39) & 0x0000000000000001ull));
 }
 
 /*
  * Transport type of the QP (RC, UC, UD, XRC, MANSP1). MANSP1 is set for
  * privileged QPs.
  */
-static inline void set_psif_qp_core__transport_type(volatile struct psif_qp_core *ptr, enum psif_qp_trans data)
+static inline void set_psif_qp_core__transport_type(
+	volatile struct psif_qp_core *ptr,
+	enum psif_qp_trans data)
 {
 	/* group=9 shift=0 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[9] = htobe64((be64toh(pte[9]) & 0xfffffffffffffff8ull) | 
+	pte[9] = cpu_to_be64((be64_to_cpu(pte[9]) & 0xfffffffffffffff8ull) |
 		((((u64)(data)) & 0x0000000000000007ull) << 0));
 }
 static inline enum psif_qp_trans get_psif_qp_core__transport_type(volatile struct psif_qp_core *ptr)
 {
 	/* group=9 shift=0 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_qp_trans)((be64toh(pte[9]) >> 0) & 0x0000000000000007ull));
+	return((enum psif_qp_trans)((be64_to_cpu(pte[9]) >> 0) & 0x0000000000000007ull));
+}
+
+/*
+ * This is an index to completion queue descriptor. The descriptor points to
+ * a receive completion queue, which may or may not be the same as the send
+ * completion queue. For XRC QPs, this field is written by the CQ descriptor
+ * received by the XRCSRQ on the first packet. This way we don't need to look
+ * up the XRCSRQ for every packet. of the message.
+ */
+static inline void set_psif_qp_core__rcv_cq_indx(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
+{
+	/* group=9 shift=8 bits=24 */
+	volatile __be64 *const pte = (__be64 *)ptr;
+	pte[9] = cpu_to_be64((be64_to_cpu(pte[9]) & 0xffffffff000000ffull) |
+		((((u64)(data)) & 0x0000000000ffffffull) << 8));
+}
+static inline u32 get_psif_qp_core__rcv_cq_indx(volatile struct psif_qp_core *ptr)
+{
+	/* group=9 shift=8 bits=24 */
+	volatile __be64 *const pte = (__be64 *)ptr;
+	return((u32)((be64_to_cpu(pte[9]) >> 8) & 0x0000000000ffffffull));
 }
 
 /*
@@ -767,98 +902,108 @@
  * received for SENDs and RDMA WR w/Imm are needed for completions. This
  * should be added to the msg_length.
  */
-static inline void set_psif_qp_core__bytes_received(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__bytes_received(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=9 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[9] = htobe64((be64toh(pte[9]) & 0x00000000ffffffffull) | 
-		((((u64)(data)) & 0x00000000ffffffffull) << 32));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 9) + 0);
+	*pte = cpu_to_be32(data);
 }
 static inline u32 get_psif_qp_core__bytes_received(volatile struct psif_qp_core *ptr)
 {
 	/* group=9 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[9]) >> 32) & 0x00000000ffffffffull));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 9) + 0);
+	return((u32)be32_to_cpu(*pte));
 }
 
 /* This QP is running IP over IB. */
-static inline void set_psif_qp_core__ipoib(volatile struct psif_qp_core *ptr, u8 data)
+static inline void set_psif_qp_core__ipoib(
+	volatile struct psif_qp_core *ptr,
+	u8 data)
 {
 	/* group=10 shift=5 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[10] = htobe64((be64toh(pte[10]) & 0xffffffffffffffdfull) | 
+	pte[10] = cpu_to_be64((be64_to_cpu(pte[10]) & 0xffffffffffffffdfull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 5));
 }
 static inline u8 get_psif_qp_core__ipoib(volatile struct psif_qp_core *ptr)
 {
 	/* group=10 shift=5 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[10]) >> 5) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[10]) >> 5) & 0x0000000000000001ull));
 }
 
 /*
  * Combined 'Last Received MSN' and 'Last Outstanding MSN', used to maintain
  * 'spin set floor' and indicate 'all retries completed', respectively.
  */
-static inline void set_psif_qp_core__last_received_outstanding_msn(volatile struct psif_qp_core *ptr, u16 data)
+static inline void set_psif_qp_core__last_received_outstanding_msn(
+	volatile struct psif_qp_core *ptr,
+	u16 data)
 {
 	/* group=11 shift=0 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[11] = htobe64((be64toh(pte[11]) & 0xffffffffffff0000ull) | 
-		((((u64)(data)) & 0x000000000000ffffull) << 0));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 11) + 6);
+	*pte = cpu_to_be16(data);
 }
 static inline u16 get_psif_qp_core__last_received_outstanding_msn(volatile struct psif_qp_core *ptr)
 {
 	/* group=11 shift=0 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[11]) >> 0) & 0x000000000000ffffull));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 11) + 6);
+	return((u16)be16_to_cpu(*pte));
 }
 
-static inline void set_psif_qp_core__path_mtu(volatile struct psif_qp_core *ptr, enum psif_path_mtu data)
+static inline void set_psif_qp_core__path_mtu(
+	volatile struct psif_qp_core *ptr,
+	enum psif_path_mtu data)
 {
 	/* group=13 shift=4 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[13] = htobe64((be64toh(pte[13]) & 0xffffffffffffff8full) | 
+	pte[13] = cpu_to_be64((be64_to_cpu(pte[13]) & 0xffffffffffffff8full) |
 		((((u64)(data)) & 0x0000000000000007ull) << 4));
 }
 static inline enum psif_path_mtu get_psif_qp_core__path_mtu(volatile struct psif_qp_core *ptr)
 {
 	/* group=13 shift=4 bits=3 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_path_mtu)((be64toh(pte[13]) >> 4) & 0x0000000000000007ull));
+	return((enum psif_path_mtu)((be64_to_cpu(pte[13]) >> 4) & 0x0000000000000007ull));
 }
 
 /* This PSN is committed - ACKs sent will contain this PSN. */
-static inline void set_psif_qp_core__committed_received_psn(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__committed_received_psn(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=13 shift=8 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[13] = htobe64((be64toh(pte[13]) & 0xffffffff000000ffull) | 
+	pte[13] = cpu_to_be64((be64_to_cpu(pte[13]) & 0xffffffff000000ffull) |
 		((((u64)(data)) & 0x0000000000ffffffull) << 8));
 }
 static inline u32 get_psif_qp_core__committed_received_psn(volatile struct psif_qp_core *ptr)
 {
 	/* group=13 shift=8 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[13]) >> 8) & 0x0000000000ffffffull));
+	return((u32)((be64_to_cpu(pte[13]) >> 8) & 0x0000000000ffffffull));
 }
 
 /*
  * Message sequence number used in AETH when sending ACKs. The number is
  * incremented every time a new inbound message is processed.
  */
-static inline void set_psif_qp_core__msn(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__msn(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=14 shift=0 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[14] = htobe64((be64toh(pte[14]) & 0xffffffffff000000ull) | 
+	pte[14] = cpu_to_be64((be64_to_cpu(pte[14]) & 0xffffffffff000000ull) |
 		((((u64)(data)) & 0x0000000000ffffffull) << 0));
 }
 static inline u32 get_psif_qp_core__msn(volatile struct psif_qp_core *ptr)
 {
 	/* group=14 shift=0 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[14]) >> 0) & 0x0000000000ffffffull));
+	return((u32)((be64_to_cpu(pte[14]) >> 0) & 0x0000000000ffffffull));
 }
 
 /*
@@ -866,443 +1011,495 @@
  * points to a send completion queue, which may or may not be the same as the
  * send completion queue.
  */
-static inline void set_psif_qp_core__send_cq_indx(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__send_cq_indx(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=14 shift=24 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[14] = htobe64((be64toh(pte[14]) & 0xffff000000ffffffull) | 
+	pte[14] = cpu_to_be64((be64_to_cpu(pte[14]) & 0xffff000000ffffffull) |
 		((((u64)(data)) & 0x0000000000ffffffull) << 24));
 }
 static inline u32 get_psif_qp_core__send_cq_indx(volatile struct psif_qp_core *ptr)
 {
 	/* group=14 shift=24 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[14]) >> 24) & 0x0000000000ffffffull));
+	return((u32)((be64_to_cpu(pte[14]) >> 24) & 0x0000000000ffffffull));
 }
 
 /*
  * Committed MSN - the MSN of the newest committed request for this QP. Only
  * the bottom 16 bits of the MSN is used.
  */
-static inline void set_psif_qp_core__last_committed_msn(volatile struct psif_qp_core *ptr, u16 data)
+static inline void set_psif_qp_core__last_committed_msn(
+	volatile struct psif_qp_core *ptr,
+	u16 data)
 {
 	/* group=14 shift=48 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[14] = htobe64((be64toh(pte[14]) & 0x0000ffffffffffffull) | 
-		((((u64)(data)) & 0x000000000000ffffull) << 48));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 14) + 0);
+	*pte = cpu_to_be16(data);
 }
 static inline u16 get_psif_qp_core__last_committed_msn(volatile struct psif_qp_core *ptr)
 {
 	/* group=14 shift=48 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[14]) >> 48) & 0x000000000000ffffull));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 14) + 0);
+	return((u16)be16_to_cpu(*pte));
 }
 
-static inline void set_psif_qp_core__srq_pd(volatile struct psif_qp_core *ptr, u32 data)
+static inline void set_psif_qp_core__srq_pd(
+	volatile struct psif_qp_core *ptr,
+	u32 data)
 {
 	/* group=15 shift=0 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[15] = htobe64((be64toh(pte[15]) & 0xffffffffff000000ull) | 
+	pte[15] = cpu_to_be64((be64_to_cpu(pte[15]) & 0xffffffffff000000ull) |
 		((((u64)(data)) & 0x0000000000ffffffull) << 0));
 }
 static inline u32 get_psif_qp_core__srq_pd(volatile struct psif_qp_core *ptr)
 {
 	/* group=15 shift=0 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[15]) >> 0) & 0x0000000000ffffffull));
+	return((u32)((be64_to_cpu(pte[15]) >> 0) & 0x0000000000ffffffull));
 }
 
-static inline void set_psif_qp_path__remote_gid_0(volatile struct psif_qp_path *ptr, u64 data)
+static inline void set_psif_qp_path__remote_gid_0(
+	volatile struct psif_qp_path *ptr,
+	u64 data)
 {
 	/* group=0 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((__be64)data);
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	*pte = cpu_to_be64(data);
 }
 static inline u64 get_psif_qp_path__remote_gid_0(volatile struct psif_qp_path *ptr)
 {
 	/* group=0 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u64)be64toh(pte[0]));
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	return((u64)be64_to_cpu(*pte));
 }
 
-static inline void set_psif_qp_path__remote_gid_1(volatile struct psif_qp_path *ptr, u64 data)
+static inline void set_psif_qp_path__remote_gid_1(
+	volatile struct psif_qp_path *ptr,
+	u64 data)
 {
 	/* group=1 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[1] = htobe64((__be64)data);
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 1) + 0);
+	*pte = cpu_to_be64(data);
 }
 static inline u64 get_psif_qp_path__remote_gid_1(volatile struct psif_qp_path *ptr)
 {
 	/* group=1 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u64)be64toh(pte[1]));
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 1) + 0);
+	return((u64)be64_to_cpu(*pte));
 }
 
-static inline void set_psif_qp_path__remote_lid(volatile struct psif_qp_path *ptr, u16 data)
+static inline void set_psif_qp_path__remote_lid(
+	volatile struct psif_qp_path *ptr,
+	u16 data)
 {
 	/* group=2 shift=0 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0xffffffffffff0000ull) | 
-		((((u64)(data)) & 0x000000000000ffffull) << 0));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 2) + 6);
+	*pte = cpu_to_be16(data);
 }
 static inline u16 get_psif_qp_path__remote_lid(volatile struct psif_qp_path *ptr)
 {
 	/* group=2 shift=0 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[2]) >> 0) & 0x000000000000ffffull));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 2) + 6);
+	return((u16)be16_to_cpu(*pte));
 }
 
-static inline void set_psif_qp_path__port(volatile struct psif_qp_path *ptr, enum psif_port data)
+static inline void set_psif_qp_path__port(
+	volatile struct psif_qp_path *ptr,
+	enum psif_port data)
 {
 	/* group=2 shift=17 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0xfffffffffffdffffull) | 
+	pte[2] = cpu_to_be64((be64_to_cpu(pte[2]) & 0xfffffffffffdffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 17));
 }
 static inline enum psif_port get_psif_qp_path__port(volatile struct psif_qp_path *ptr)
 {
 	/* group=2 shift=17 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_port)((be64toh(pte[2]) >> 17) & 0x0000000000000001ull));
+	return((enum psif_port)((be64_to_cpu(pte[2]) >> 17) & 0x0000000000000001ull));
 }
 
-static inline void set_psif_qp_path__loopback(volatile struct psif_qp_path *ptr, enum psif_loopback data)
+static inline void set_psif_qp_path__loopback(
+	volatile struct psif_qp_path *ptr,
+	enum psif_loopback data)
 {
 	/* group=2 shift=18 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0xfffffffffffbffffull) | 
+	pte[2] = cpu_to_be64((be64_to_cpu(pte[2]) & 0xfffffffffffbffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 18));
 }
 static inline enum psif_loopback get_psif_qp_path__loopback(volatile struct psif_qp_path *ptr)
 {
 	/* group=2 shift=18 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_loopback)((be64toh(pte[2]) >> 18) & 0x0000000000000001ull));
+	return((enum psif_loopback)((be64_to_cpu(pte[2]) >> 18) & 0x0000000000000001ull));
 }
 
-static inline void set_psif_qp_path__use_grh(volatile struct psif_qp_path *ptr, enum psif_use_grh data)
+static inline void set_psif_qp_path__use_grh(
+	volatile struct psif_qp_path *ptr,
+	enum psif_use_grh data)
 {
 	/* group=2 shift=19 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0xfffffffffff7ffffull) | 
+	pte[2] = cpu_to_be64((be64_to_cpu(pte[2]) & 0xfffffffffff7ffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 19));
 }
 static inline enum psif_use_grh get_psif_qp_path__use_grh(volatile struct psif_qp_path *ptr)
 {
 	/* group=2 shift=19 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_use_grh)((be64toh(pte[2]) >> 19) & 0x0000000000000001ull));
+	return((enum psif_use_grh)((be64_to_cpu(pte[2]) >> 19) & 0x0000000000000001ull));
 }
 
-static inline void set_psif_qp_path__sl(volatile struct psif_qp_path *ptr, u8 data)
+static inline void set_psif_qp_path__sl(
+	volatile struct psif_qp_path *ptr,
+	u8 data)
 {
 	/* group=2 shift=20 bits=4 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0xffffffffff0fffffull) | 
+	pte[2] = cpu_to_be64((be64_to_cpu(pte[2]) & 0xffffffffff0fffffull) |
 		((((u64)(data)) & 0x000000000000000full) << 20));
 }
 static inline u8 get_psif_qp_path__sl(volatile struct psif_qp_path *ptr)
 {
 	/* group=2 shift=20 bits=4 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[2]) >> 20) & 0x000000000000000full));
+	return((u8)((be64_to_cpu(pte[2]) >> 20) & 0x000000000000000full));
 }
 
-static inline void set_psif_qp_path__hoplmt(volatile struct psif_qp_path *ptr, u8 data)
+static inline void set_psif_qp_path__hoplmt(
+	volatile struct psif_qp_path *ptr,
+	u8 data)
 {
 	/* group=2 shift=28 bits=8 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0xfffffff00fffffffull) | 
+	pte[2] = cpu_to_be64((be64_to_cpu(pte[2]) & 0xfffffff00fffffffull) |
 		((((u64)(data)) & 0x00000000000000ffull) << 28));
 }
 static inline u8 get_psif_qp_path__hoplmt(volatile struct psif_qp_path *ptr)
 {
 	/* group=2 shift=28 bits=8 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[2]) >> 28) & 0x00000000000000ffull));
+	return((u8)((be64_to_cpu(pte[2]) >> 28) & 0x00000000000000ffull));
 }
 
-static inline void set_psif_qp_path__flowlabel(volatile struct psif_qp_path *ptr, u32 data)
+static inline void set_psif_qp_path__flowlabel(
+	volatile struct psif_qp_path *ptr,
+	u32 data)
 {
 	/* group=2 shift=44 bits=20 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0x00000fffffffffffull) | 
+	pte[2] = cpu_to_be64((be64_to_cpu(pte[2]) & 0x00000fffffffffffull) |
 		((((u64)(data)) & 0x00000000000fffffull) << 44));
 }
 static inline u32 get_psif_qp_path__flowlabel(volatile struct psif_qp_path *ptr)
 {
 	/* group=2 shift=44 bits=20 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[2]) >> 44) & 0x00000000000fffffull));
+	return((u32)((be64_to_cpu(pte[2]) >> 44) & 0x00000000000fffffull));
 }
 
-static inline void set_psif_qp_path__local_ack_timeout(volatile struct psif_qp_path *ptr, u8 data)
+static inline void set_psif_qp_path__local_ack_timeout(
+	volatile struct psif_qp_path *ptr,
+	u8 data)
 {
 	/* group=3 shift=27 bits=5 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[3] = htobe64((be64toh(pte[3]) & 0xffffffff07ffffffull) | 
+	pte[3] = cpu_to_be64((be64_to_cpu(pte[3]) & 0xffffffff07ffffffull) |
 		((((u64)(data)) & 0x000000000000001full) << 27));
 }
 static inline u8 get_psif_qp_path__local_ack_timeout(volatile struct psif_qp_path *ptr)
 {
 	/* group=3 shift=27 bits=5 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[3]) >> 27) & 0x000000000000001full));
+	return((u8)((be64_to_cpu(pte[3]) >> 27) & 0x000000000000001full));
 }
 
-static inline void set_psif_qp_path__ipd(volatile struct psif_qp_path *ptr, u8 data)
+static inline void set_psif_qp_path__ipd(
+	volatile struct psif_qp_path *ptr,
+	u8 data)
 {
 	/* group=3 shift=32 bits=8 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[3] = htobe64((be64toh(pte[3]) & 0xffffff00ffffffffull) | 
-		((((u64)(data)) & 0x00000000000000ffull) << 32));
+	volatile u8 * const pte = (u8 *)((u8 *)((__be64 *)ptr + 3) + 3);
+	*pte = (data);
 }
 static inline u8 get_psif_qp_path__ipd(volatile struct psif_qp_path *ptr)
 {
 	/* group=3 shift=32 bits=8 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[3]) >> 32) & 0x00000000000000ffull));
+	volatile u8 * const pte = (u8 *)((u8 *)((__be64 *)ptr + 3) + 3);
+	return((u8)(*pte));
 }
 
 /*
  * This is the LID path bits. This is used by tsu_ibpb when generating the
  * SLID in the packet, and it is used by tsu_rcv when checking the DLID.
  */
-static inline void set_psif_qp_path__local_lid_path(volatile struct psif_qp_path *ptr, u8 data)
+static inline void set_psif_qp_path__local_lid_path(
+	volatile struct psif_qp_path *ptr,
+	u8 data)
 {
 	/* group=3 shift=48 bits=7 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[3] = htobe64((be64toh(pte[3]) & 0xff80ffffffffffffull) | 
+	pte[3] = cpu_to_be64((be64_to_cpu(pte[3]) & 0xff80ffffffffffffull) |
 		((((u64)(data)) & 0x000000000000007full) << 48));
 }
 static inline u8 get_psif_qp_path__local_lid_path(volatile struct psif_qp_path *ptr)
 {
 	/* group=3 shift=48 bits=7 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[3]) >> 48) & 0x000000000000007full));
+	return((u8)((be64_to_cpu(pte[3]) >> 48) & 0x000000000000007full));
 }
 
-static inline void set_psif_qp_path__pkey_indx(volatile struct psif_qp_path *ptr, u16 data)
+static inline void set_psif_qp_path__pkey_indx(
+	volatile struct psif_qp_path *ptr,
+	u16 data)
 {
 	/* group=3 shift=55 bits=9 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[3] = htobe64((be64toh(pte[3]) & 0x007fffffffffffffull) | 
+	pte[3] = cpu_to_be64((be64_to_cpu(pte[3]) & 0x007fffffffffffffull) |
 		((((u64)(data)) & 0x00000000000001ffull) << 55));
 }
 static inline u16 get_psif_qp_path__pkey_indx(volatile struct psif_qp_path *ptr)
 {
 	/* group=3 shift=55 bits=9 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[3]) >> 55) & 0x00000000000001ffull));
+	return((u16)((be64_to_cpu(pte[3]) >> 55) & 0x00000000000001ffull));
 }
 
 /* L-key state for this DMA validation entry */
-static inline void set_psif_key__lkey_state(volatile struct psif_key *ptr, enum psif_dma_vt_key_states data)
+static inline void set_psif_key__lkey_state(
+	volatile struct psif_key *ptr,
+	enum psif_dma_vt_key_states data)
 {
 	/* group=0 shift=60 bits=2 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xcfffffffffffffffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xcfffffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000003ull) << 60));
 }
 static inline enum psif_dma_vt_key_states get_psif_key__lkey_state(volatile struct psif_key *ptr)
 {
 	/* group=0 shift=60 bits=2 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_dma_vt_key_states)((be64toh(pte[0]) >> 60) & 0x0000000000000003ull));
+	return((enum psif_dma_vt_key_states)((be64_to_cpu(pte[0]) >> 60) & 0x0000000000000003ull));
 }
 
 /* R-key state for this DMA validation entry */
-static inline void set_psif_key__rkey_state(volatile struct psif_key *ptr, enum psif_dma_vt_key_states data)
+static inline void set_psif_key__rkey_state(
+	volatile struct psif_key *ptr,
+	enum psif_dma_vt_key_states data)
 {
 	/* group=0 shift=62 bits=2 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0x3fffffffffffffffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0x3fffffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000003ull) << 62));
 }
 static inline enum psif_dma_vt_key_states get_psif_key__rkey_state(volatile struct psif_key *ptr)
 {
 	/* group=0 shift=62 bits=2 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_dma_vt_key_states)((be64toh(pte[0]) >> 62) & 0x0000000000000003ull));
+	return((enum psif_dma_vt_key_states)((be64_to_cpu(pte[0]) >> 62) & 0x0000000000000003ull));
 }
 
 /* Length of memory region this validation entry is associated with. */
-static inline void set_psif_key__length(volatile struct psif_key *ptr, u64 data)
+static inline void set_psif_key__length(
+	volatile struct psif_key *ptr,
+	u64 data)
 {
 	/* group=1 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[1] = htobe64((__be64)data);
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 1) + 0);
+	*pte = cpu_to_be64(data);
 }
 static inline u64 get_psif_key__length(volatile struct psif_key *ptr)
 {
 	/* group=1 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u64)be64toh(pte[1]));
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 1) + 0);
+	return((u64)be64_to_cpu(*pte));
 }
 
-static inline void set_psif_key__mmu_context(volatile struct psif_key *ptr, u64 data)
+static inline void set_psif_key__mmu_context(
+	volatile struct psif_key *ptr,
+	u64 data)
 {
 	/* group=2 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((__be64)data);
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 2) + 0);
+	*pte = cpu_to_be64(data);
 }
 static inline u64 get_psif_key__mmu_context(volatile struct psif_key *ptr)
 {
 	/* group=2 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u64)be64toh(pte[2]));
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 2) + 0);
+	return((u64)be64_to_cpu(*pte));
 }
 
-static inline void set_psif_key__base_addr(volatile struct psif_key *ptr, u64 data)
+static inline void set_psif_key__base_addr(
+	volatile struct psif_key *ptr,
+	u64 data)
 {
 	/* group=3 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[3] = htobe64((__be64)data);
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 3) + 0);
+	*pte = cpu_to_be64(data);
 }
 static inline u64 get_psif_key__base_addr(volatile struct psif_key *ptr)
 {
 	/* group=3 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u64)be64toh(pte[3]));
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 3) + 0);
+	return((u64)be64_to_cpu(*pte));
 }
 
 /* sequence number for sanity checking */
-static inline void set_psif_eq_entry__seq_num(volatile struct psif_eq_entry *ptr, u32 data)
+static inline void set_psif_eq_entry__seq_num(
+	volatile struct psif_eq_entry *ptr,
+	u32 data)
 {
 	/* group=7 shift=0 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[7] = htobe64((be64toh(pte[7]) & 0xffffffff00000000ull) | 
-		((((u64)(data)) & 0x00000000ffffffffull) << 0));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 7) + 4);
+	*pte = cpu_to_be32(data);
 }
 static inline u32 get_psif_eq_entry__seq_num(volatile struct psif_eq_entry *ptr)
 {
 	/* group=7 shift=0 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[7]) >> 0) & 0x00000000ffffffffull));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 7) + 4);
+	return((u32)be32_to_cpu(*pte));
 }
 
 /* enum psif_epsc_csr_opcode from request */
-static inline void set_psif_epsc_csr_rsp__opcode(volatile struct psif_epsc_csr_rsp *ptr, enum psif_epsc_csr_opcode data)
+static inline void set_psif_epsc_csr_rsp__opcode(
+	volatile struct psif_epsc_csr_rsp *ptr,
+	enum psif_epsc_csr_opcode data)
 {
 	/* group=0 shift=48 bits=8 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xff00ffffffffffffull) | 
-		((((u64)(data)) & 0x00000000000000ffull) << 48));
+	volatile u8 * const pte = (u8 *)((u8 *)((__be64 *)ptr + 0) + 1);
+	*pte = (data);
 }
 static inline enum psif_epsc_csr_opcode get_psif_epsc_csr_rsp__opcode(volatile struct psif_epsc_csr_rsp *ptr)
 {
 	/* group=0 shift=48 bits=8 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_epsc_csr_opcode)((be64toh(pte[0]) >> 48) & 0x00000000000000ffull));
+	volatile u8 * const pte = (u8 *)((u8 *)((__be64 *)ptr + 0) + 1);
+	return((enum psif_epsc_csr_opcode)(*pte));
 }
 
 /* Sequence number from request */
-static inline void set_psif_epsc_csr_rsp__seq_num(volatile struct psif_epsc_csr_rsp *ptr, u64 data)
+static inline void set_psif_epsc_csr_rsp__seq_num(
+	volatile struct psif_epsc_csr_rsp *ptr,
+	u64 data)
 {
 	/* group=3 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[3] = htobe64((__be64)data);
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 3) + 0);
+	*pte = cpu_to_be64(data);
 }
 static inline u64 get_psif_epsc_csr_rsp__seq_num(volatile struct psif_epsc_csr_rsp *ptr)
 {
 	/* group=3 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u64)be64toh(pte[3]));
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 3) + 0);
+	return((u64)be64_to_cpu(*pte));
 }
 
 /* Sequence number - included in response */
-static inline void set_psif_epsc_csr_req__seq_num(volatile struct psif_epsc_csr_req *ptr, u16 data)
+static inline void set_psif_epsc_csr_req__seq_num(
+	volatile struct psif_epsc_csr_req *ptr,
+	u16 data)
 {
 	/* group=0 shift=32 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xffff0000ffffffffull) | 
-		((((u64)(data)) & 0x000000000000ffffull) << 32));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 0) + 2);
+	*pte = cpu_to_be16(data);
 }
 static inline u16 get_psif_epsc_csr_req__seq_num(volatile struct psif_epsc_csr_req *ptr)
 {
 	/* group=0 shift=32 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[0]) >> 32) & 0x000000000000ffffull));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 0) + 2);
+	return((u16)be16_to_cpu(*pte));
 }
 
-static inline void set_psif_epsc_csr_req__opcode(volatile struct psif_epsc_csr_req *ptr, enum psif_epsc_csr_opcode data)
+static inline void set_psif_epsc_csr_req__opcode(
+	volatile struct psif_epsc_csr_req *ptr,
+	enum psif_epsc_csr_opcode data)
 {
 	/* group=0 shift=56 bits=8 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0x00ffffffffffffffull) | 
-		((((u64)(data)) & 0x00000000000000ffull) << 56));
+	volatile u8 * const pte = (u8 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	*pte = (data);
 }
 static inline enum psif_epsc_csr_opcode get_psif_epsc_csr_req__opcode(volatile struct psif_epsc_csr_req *ptr)
 {
 	/* group=0 shift=56 bits=8 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_epsc_csr_opcode)((be64toh(pte[0]) >> 56) & 0x00000000000000ffull));
+	volatile u8 * const pte = (u8 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	return((enum psif_epsc_csr_opcode)(*pte));
 }
 
 /* Index to completion elements added by SW. */
-static inline void set_psif_cq_sw__head_indx(volatile struct psif_cq_sw *ptr, u32 data)
+static inline void set_psif_cq_sw__head_indx(
+	volatile struct psif_cq_sw *ptr,
+	u32 data)
 {
 	/* group=0 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0x00000000ffffffffull) | 
-		((((u64)(data)) & 0x00000000ffffffffull) << 32));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	*pte = cpu_to_be32(data);
 }
 static inline u32 get_psif_cq_sw__head_indx(volatile struct psif_cq_sw *ptr)
 {
 	/* group=0 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[0]) >> 32) & 0x00000000ffffffffull));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	return((u32)be32_to_cpu(*pte));
 }
 
 /*
  * EPS-A core number completions are forwarded to if the proxy_enabled bit is
  * set.
  */
-static inline void set_psif_cq_hw__eps_core(volatile struct psif_cq_hw *ptr, enum psif_eps_a_core data)
+static inline void set_psif_cq_hw__eps_core(
+	volatile struct psif_cq_hw *ptr,
+	enum psif_eps_a_core data)
 {
 	/* group=0 shift=52 bits=2 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xffcfffffffffffffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xffcfffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000003ull) << 52));
 }
 static inline enum psif_eps_a_core get_psif_cq_hw__eps_core(volatile struct psif_cq_hw *ptr)
 {
 	/* group=0 shift=52 bits=2 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_eps_a_core)((be64toh(pte[0]) >> 52) & 0x0000000000000003ull));
+	return((enum psif_eps_a_core)((be64_to_cpu(pte[0]) >> 52) & 0x0000000000000003ull));
 }
 
 /*
  * If set, this completion queue is proxy enabled and should send completions
  * to EPS core indicated by the eps_core field.
  */
-static inline void set_psif_cq_hw__proxy_en(volatile struct psif_cq_hw *ptr, u8 data)
+static inline void set_psif_cq_hw__proxy_en(
+	volatile struct psif_cq_hw *ptr,
+	u8 data)
 {
 	/* group=0 shift=54 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xffbfffffffffffffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xffbfffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 54));
 }
 static inline u8 get_psif_cq_hw__proxy_en(volatile struct psif_cq_hw *ptr)
 {
 	/* group=0 shift=54 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[0]) >> 54) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[0]) >> 54) & 0x0000000000000001ull));
 }
 
 /* The descriptor is valid. */
-static inline void set_psif_cq_hw__valid(volatile struct psif_cq_hw *ptr, u8 data)
+static inline void set_psif_cq_hw__valid(
+	volatile struct psif_cq_hw *ptr,
+	u8 data)
 {
 	/* group=0 shift=60 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((be64toh(pte[0]) & 0xefffffffffffffffull) | 
+	pte[0] = cpu_to_be64((be64_to_cpu(pte[0]) & 0xefffffffffffffffull) |
 		((((u64)(data)) & 0x0000000000000001ull) << 60));
 }
 static inline u8 get_psif_cq_hw__valid(volatile struct psif_cq_hw *ptr)
 {
 	/* group=0 shift=60 bits=1 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[0]) >> 60) & 0x0000000000000001ull));
+	return((u8)((be64_to_cpu(pte[0]) >> 60) & 0x0000000000000001ull));
 }
 
 /*
@@ -1314,32 +1511,35 @@
  * address space, or all need to be PA. In typical use, to allow direct user
  * access to the head and tail pointer VAs are used.
  */
-static inline void set_psif_cq_hw__base_addr(volatile struct psif_cq_hw *ptr, u64 data)
+static inline void set_psif_cq_hw__base_addr(
+	volatile struct psif_cq_hw *ptr,
+	u64 data)
 {
 	/* group=2 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((__be64)data);
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 2) + 0);
+	*pte = cpu_to_be64(data);
 }
 static inline u64 get_psif_cq_hw__base_addr(volatile struct psif_cq_hw *ptr)
 {
 	/* group=2 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u64)be64toh(pte[2]));
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 2) + 0);
+	return((u64)be64_to_cpu(*pte));
 }
 
 /* Index to completion elements to be consumed by HW. */
-static inline void set_psif_cq_hw__tail_indx(volatile struct psif_cq_hw *ptr, u32 data)
+static inline void set_psif_cq_hw__tail_indx(
+	volatile struct psif_cq_hw *ptr,
+	u32 data)
 {
 	/* group=3 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[3] = htobe64((be64toh(pte[3]) & 0x00000000ffffffffull) | 
-		((((u64)(data)) & 0x00000000ffffffffull) << 32));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 3) + 0);
+	*pte = cpu_to_be32(data);
 }
 static inline u32 get_psif_cq_hw__tail_indx(volatile struct psif_cq_hw *ptr)
 {
 	/* group=3 shift=32 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[3]) >> 32) & 0x00000000ffffffffull));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 3) + 0);
+	return((u32)be32_to_cpu(*pte));
 }
 
 /*
@@ -1347,120 +1547,115 @@
  * in the receive queue and the receive queue descriptor index. For send
  * completions this is the sq_sequence number.
  */
-static inline void set_psif_cq_entry__wc_id(volatile struct psif_cq_entry *ptr, u64 data)
+static inline void set_psif_cq_entry__wc_id(
+	volatile struct psif_cq_entry *ptr,
+	u64 data)
 {
 	/* group=0 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[0] = htobe64((__be64)data);
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	*pte = cpu_to_be64(data);
 }
 static inline u64 get_psif_cq_entry__wc_id(volatile struct psif_cq_entry *ptr)
 {
 	/* group=0 shift=0 bits=64 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u64)be64toh(pte[0]));
+	volatile u64 * const pte = (u64 *)((u8 *)((__be64 *)ptr + 0) + 0);
+	return((u64)be64_to_cpu(*pte));
 }
 
-static inline void set_psif_cq_entry__qp(volatile struct psif_cq_entry *ptr, u32 data)
+static inline void set_psif_cq_entry__qp(
+	volatile struct psif_cq_entry *ptr,
+	u32 data)
 {
 	/* group=1 shift=0 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[1] = htobe64((be64toh(pte[1]) & 0xffffffffff000000ull) | 
+	pte[1] = cpu_to_be64((be64_to_cpu(pte[1]) & 0xffffffffff000000ull) |
 		((((u64)(data)) & 0x0000000000ffffffull) << 0));
 }
 static inline u32 get_psif_cq_entry__qp(volatile struct psif_cq_entry *ptr)
 {
 	/* group=1 shift=0 bits=24 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[1]) >> 0) & 0x0000000000ffffffull));
+	return((u32)((be64_to_cpu(pte[1]) >> 0) & 0x0000000000ffffffull));
 }
 
-static inline void set_psif_cq_entry__opcode(volatile struct psif_cq_entry *ptr, enum psif_wc_opcode data)
+static inline void set_psif_cq_entry__opcode(
+	volatile struct psif_cq_entry *ptr,
+	enum psif_wc_opcode data)
 {
 	/* group=1 shift=24 bits=8 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[1] = htobe64((be64toh(pte[1]) & 0xffffffff00ffffffull) | 
-		((((u64)(data)) & 0x00000000000000ffull) << 24));
+	volatile u8 * const pte = (u8 *)((u8 *)((__be64 *)ptr + 1) + 4);
+	*pte = (data);
 }
 static inline enum psif_wc_opcode get_psif_cq_entry__opcode(volatile struct psif_cq_entry *ptr)
 {
 	/* group=1 shift=24 bits=8 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_wc_opcode)((be64toh(pte[1]) >> 24) & 0x00000000000000ffull));
+	volatile u8 * const pte = (u8 *)((u8 *)((__be64 *)ptr + 1) + 4);
+	return((enum psif_wc_opcode)(*pte));
 }
 
-static inline void set_psif_cq_entry__status(volatile struct psif_cq_entry *ptr, enum psif_wc_status data)
+static inline void set_psif_cq_entry__status(
+	volatile struct psif_cq_entry *ptr,
+	enum psif_wc_status data)
 {
 	/* group=2 shift=24 bits=8 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0xffffffff00ffffffull) | 
-		((((u64)(data)) & 0x00000000000000ffull) << 24));
+	volatile u8 * const pte = (u8 *)((u8 *)((__be64 *)ptr + 2) + 4);
+	*pte = (data);
 }
 static inline enum psif_wc_status get_psif_cq_entry__status(volatile struct psif_cq_entry *ptr)
 {
 	/* group=2 shift=24 bits=8 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((enum psif_wc_status)((be64toh(pte[2]) >> 24) & 0x00000000000000ffull));
+	volatile u8 * const pte = (u8 *)((u8 *)((__be64 *)ptr + 2) + 4);
+	return((enum psif_wc_status)(*pte));
 }
 
 /* sequence number for sanity checking */
-static inline void set_psif_cq_entry__seq_num(volatile struct psif_cq_entry *ptr, u32 data)
+static inline void set_psif_cq_entry__seq_num(
+	volatile struct psif_cq_entry *ptr,
+	u32 data)
 {
 	/* group=7 shift=0 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[7] = htobe64((be64toh(pte[7]) & 0xffffffff00000000ull) | 
-		((((u64)(data)) & 0x00000000ffffffffull) << 0));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 7) + 4);
+	*pte = cpu_to_be32(data);
 }
 static inline u32 get_psif_cq_entry__seq_num(volatile struct psif_cq_entry *ptr)
 {
 	/* group=7 shift=0 bits=32 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u32)((be64toh(pte[7]) >> 0) & 0x00000000ffffffffull));
+	volatile u32 * const pte = (u32 *)((u8 *)((__be64 *)ptr + 7) + 4);
+	return((u32)be32_to_cpu(*pte));
 }
 
-static inline void set_psif_ah__remote_lid(volatile struct psif_ah *ptr, u16 data)
+static inline void set_psif_ah__remote_lid(
+	volatile struct psif_ah *ptr,
+	u16 data)
 {
 	/* group=2 shift=0 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0xffffffffffff0000ull) | 
-		((((u64)(data)) & 0x000000000000ffffull) << 0));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 2) + 6);
+	*pte = cpu_to_be16(data);
 }
 static inline u16 get_psif_ah__remote_lid(volatile struct psif_ah *ptr)
 {
 	/* group=2 shift=0 bits=16 */
-	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u16)((be64toh(pte[2]) >> 0) & 0x000000000000ffffull));
+	volatile u16 * const pte = (u16 *)((u8 *)((__be64 *)ptr + 2) + 6);
+	return((u16)be16_to_cpu(*pte));
 }
 
-static inline void set_psif_ah__sl(volatile struct psif_ah *ptr, u8 data)
+static inline void set_psif_ah__sl(
+	volatile struct psif_ah *ptr,
+	u8 data)
 {
 	/* group=2 shift=20 bits=4 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	pte[2] = htobe64((be64toh(pte[2]) & 0xffffffffff0fffffull) | 
+	pte[2] = cpu_to_be64((be64_to_cpu(pte[2]) & 0xffffffffff0fffffull) |
 		((((u64)(data)) & 0x000000000000000full) << 20));
 }
 static inline u8 get_psif_ah__sl(volatile struct psif_ah *ptr)
 {
 	/* group=2 shift=20 bits=4 */
 	volatile __be64 *const pte = (__be64 *)ptr;
-	return((u8)((be64toh(pte[2]) >> 20) & 0x000000000000000full));
-}
-static inline void set_psif_csr_mmu_config__ta_upper_twelve(volatile void *ptr, u16 data)
-{
-	        /* group=0 shift=32 bits=12 */
-	        volatile __be64 *pte = (__be64 *)ptr;
-		        pte[0] = htobe64((be64toh(pte[0]) & 0xfffff000ffffffffull) |
-			                    ((((u64)(data)) & 0x0000000000000fffull) << 32));
+	return((u8)((be64_to_cpu(pte[2]) >> 20) & 0x000000000000000full));
 }
-static inline void set_psif_csr_mmu_config__pa_upper_twelve(volatile void *ptr, u16 data)
-{
-	        /* group=0 shift=48 bits=12 */
-	        volatile __be64 *pte = (__be64 *)ptr;
-		        pte[0] = htobe64((be64toh(pte[0]) & 0xf000ffffffffffffull) |
-			                    ((((u64)(data)) & 0x0000000000000fffull) << 48));
-}
-
-#if defined (HOST_LITTLE_ENDIAN)
-#elif defined (HOST_BIG_ENDIAN)
+#if defined(HOST_LITTLE_ENDIAN)
+#elif defined(HOST_BIG_ENDIAN)
 #else
 #error "Could not determine byte order in psif_hw_setget.h !?"
 #endif
--- a/components/open-fabrics/libsif/include/psifapi/solaris.h	Mon Oct 17 16:13:44 2016 -0700
+++ b/components/open-fabrics/libsif/include/psifapi/solaris.h	Mon Oct 17 23:20:28 2016 -0700
@@ -1,8 +1,5 @@
 /*
- * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
- *
- * THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT
- * 
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
  */
 
 /*
@@ -17,41 +14,47 @@
  *    and/or other materials provided with the distribution.
  *
  * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software without
- *    specific prior written permission.
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef _SOLARIS_H
 #define _SOLARIS_H
 
 /*
- * Definitions of __* types
- */
-typedef uint64_t __u64;
-typedef uint32_t __u32;
-typedef uint16_t __u16;
-typedef uint8_t __u8;
-
-/*
  * Endian specific conversion macros
  */
 #if defined(_LITTLE_ENDIAN)
 #define htobe64(x)		htonll(x)
 #define be64toh(x)		htonll(x)
+#define        be64_to_cpu(x)          BSWAP_64(x)
+#define        cpu_to_be64(x)          BSWAP_64(x)
+#define        be32_to_cpu(x)          BSWAP_32(x)
+#define        cpu_to_be32(x)          BSWAP_32(x)
+#define        be16_to_cpu(x)          BSWAP_16(x)
+#define        cpu_to_be16(x)          BSWAP_16(x)
 #else /* BIG_ENDIAN */
 #define htobe64(x)		(x)
 #define be64toh(x)		(x)
+#define        be64_to_cpu(x)          BMASK_64(x)
+#define        cpu_to_be64(x)          BMASK_64(x)
+#define        be32_to_cpu(x)          BMASK_32(x)
+#define        cpu_to_be32(x)          BMASK_32(x)
+#define        be16_to_cpu(x)          BMASK_16(x)
+#define        cpu_to_be16(x)          BMASK_16(x)
+
 #endif /* BIG_ENDIAN */
 
 #endif /* _SOLARIS_H */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/sif/psif_hw_print.c	Mon Oct 17 23:20:28 2016 -0700
@@ -0,0 +1,5652 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef	_PSIF_HW_PRINT_C
+#define	_PSIF_HW_PRINT_C
+
+#if defined(__arm__)
+
+#include <stdio.h>
+#include <stdint.h>
+#include "psif_endian.h"
+typedef uint64_t __be64;
+
+#else /* virtualized  */
+#if !defined(__KERNEL__)
+#include <stdio.h>
+#include <string.h>
+#if !defined(_PSIFAPI_KERNEL_TYPES_H)
+#define _PSIFAPI_KERNEL_TYPES_H
+#include <stdint.h>
+typedef uint64_t u64;
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+#endif /* (_PSIFAPI_KERNEL_TYPES_H) */
+#include "os_header.h"
+#endif /* !defined(__KERNEL__) */
+
+#endif /* __arm__ */
+
+#include "psif_api.h"
+#include "psif_hw_data.h"
+#include "psif_hw_macro.h"
+#include "psif_hw_setget.h"
+#include "psif_hw_print.h"
+#include "psif_api.h"
+
+#if !defined(xprintf)
+#define xprintf fprintf
+#endif
+#if !defined(OS_PRIx64)
+#define OS_PRIx64 "llx"
+#endif
+
+/* Write fixed size bit field represented as unsigned int types */
+void write_bits_u8(XFILE *fd, int extent, u8 data)
+{
+	xprintf(fd, "%#04x", data);
+} /* end write_bits_u8(u8 data) */
+
+/* Write fixed size bit field represented as unsigned int types */
+void write_bits_u16(XFILE *fd, int extent, u16 data)
+{
+	xprintf(fd, "%#06x", data);
+} /* end write_bits_u16(u16 data) */
+
+/* Write fixed size bit field represented as unsigned int types */
+void write_bits_u32(XFILE *fd, int extent, u32 data)
+{
+	xprintf(fd, "%#010x", data);
+} /* end write_bits_u32(u32 data) */
+
+/* Write fixed size bit field represented as unsigned int types */
+void write_bits_u64(XFILE *fd, int extent, u64 data)
+{
+	xprintf(fd, "%#018" OS_PRIx64 "", data);
+} /* end write_bits_u64(u64 data) */
+
+
+/* Convert enum psif_epsc_degrade_cause to string */
+const char *string_enum_psif_epsc_degrade_cause(enum psif_epsc_degrade_cause val)
+{
+	switch (val) {
+	case DEGRADE_CAUSE_FLAG_MISSING_GUID:
+		return "DEGRADE_CAUSE_FLAG_MISSING_GUID";
+	case DEGRADE_CAUSE_FLAG_VPD_INVALID_NAME:
+		return "DEGRADE_CAUSE_FLAG_VPD_INVALID_NAME";
+	case DEGRADE_CAUSE_FLAG_HW_UNSUPPORTED:
+		return "DEGRADE_CAUSE_FLAG_HW_UNSUPPORTED";
+	case DEGRADE_CAUSE_FLAG_HW_MDIO_ERROR:
+		return "DEGRADE_CAUSE_FLAG_HW_MDIO_ERROR";
+	case DEGRADE_CAUSE_FLAG_MODIFY_QP_TIMEOUT:
+		return "DEGRADE_CAUSE_FLAG_MODIFY_QP_TIMEOUT";
+	case DEGRADE_CAUSE_FLAG_VIRTMODE_RECONF:
+		return "DEGRADE_CAUSE_FLAG_VIRTMODE_RECONF";
+	case DEGRADE_CAUSE_FLAG_MCAST_LACK_OF_CREDIT:
+		return "DEGRADE_CAUSE_FLAG_MCAST_LACK_OF_CREDIT";
+	case PSIF_EPSC_DEGRADE_CAUSE_FIELD_MAX:
+		return "PSIF_EPSC_DEGRADE_CAUSE_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_degrade_cause";
+	}
+}
+
+void write_enum_psif_epsc_degrade_cause(XFILE *fd,
+	enum psif_epsc_degrade_cause data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_degrade_cause(data));
+} /* end write_..._psif_epsc_degrade_cause(psif_epsc_degrade_cause data) */
+
+/* Convert enum psif_mmu_translation to string */
+const char *string_enum_psif_mmu_translation(enum psif_mmu_translation val)
+{
+	switch (val) {
+	case MMU_PASS_THROUGH0:
+		return "MMU_PASS_THROUGH0";
+	case MMU_PASS_THROUGH_PAD:
+		return "MMU_PASS_THROUGH_PAD";
+	case MMU_GVA2GPA_MODE:
+		return "MMU_GVA2GPA_MODE";
+	case MMU_GVA2GPA_MODE_PAD:
+		return "MMU_GVA2GPA_MODE_PAD";
+	case MMU_PRETRANSLATED:
+		return "MMU_PRETRANSLATED";
+	case MMU_PRETRANSLATED_PAD:
+		return "MMU_PRETRANSLATED_PAD";
+	case MMU_EPSA_MODE:
+		return "MMU_EPSA_MODE";
+	case MMU_EPSC_MODE:
+		return "MMU_EPSC_MODE";
+	default:
+		return "UNKNOWN_psif_mmu_translation";
+	}
+}
+
+void write_enum_psif_mmu_translation(XFILE *fd,
+	enum psif_mmu_translation data)
+{
+	xprintf(fd, "%s", string_enum_psif_mmu_translation(data));
+} /* end write_..._psif_mmu_translation(psif_mmu_translation data) */
+
+/* Convert enum psif_page_size to string */
+const char *string_enum_psif_page_size(enum psif_page_size val)
+{
+	switch (val) {
+	case PAGE_SIZE_IA32E_4KB:
+		return "PAGE_SIZE_IA32E_4KB";
+	case PAGE_SIZE_IA32E_2MB:
+		return "PAGE_SIZE_IA32E_2MB";
+	case PAGE_SIZE_IA32E_1GB:
+		return "PAGE_SIZE_IA32E_1GB";
+	case PAGE_SIZE_S64_8KB:
+		return "PAGE_SIZE_S64_8KB";
+	case PAGE_SIZE_S64_64KB:
+		return "PAGE_SIZE_S64_64KB";
+	case PAGE_SIZE_S64_512KB:
+		return "PAGE_SIZE_S64_512KB";
+	case PAGE_SIZE_S64_4MB:
+		return "PAGE_SIZE_S64_4MB";
+	case PAGE_SIZE_S64_32MB:
+		return "PAGE_SIZE_S64_32MB";
+	case PAGE_SIZE_S64_2GB:
+		return "PAGE_SIZE_S64_2GB";
+	case PAGE_SIZE_S64_16GB:
+		return "PAGE_SIZE_S64_16GB";
+	default:
+		return "UNKNOWN_psif_page_size";
+	}
+}
+
+void write_enum_psif_page_size(XFILE *fd,
+	enum psif_page_size data)
+{
+	xprintf(fd, "%s", string_enum_psif_page_size(data));
+} /* end write_..._psif_page_size(psif_page_size data) */
+
+/* Convert enum psif_wr_type to string */
+const char *string_enum_psif_wr_type(enum psif_wr_type val)
+{
+	switch (val) {
+	case PSIF_WR_SEND:
+		return "PSIF_WR_SEND";
+	case PSIF_WR_SEND_IMM:
+		return "PSIF_WR_SEND_IMM";
+	case PSIF_WR_SPECIAL_QP_SEND:
+		return "PSIF_WR_SPECIAL_QP_SEND";
+	case PSIF_WR_QP0_SEND_DR_XMIT:
+		return "PSIF_WR_QP0_SEND_DR_XMIT";
+	case PSIF_WR_QP0_SEND_DR_LOOPBACK:
+		return "PSIF_WR_QP0_SEND_DR_LOOPBACK";
+	case PSIF_WR_EPS_SPECIAL_QP_SEND:
+		return "PSIF_WR_EPS_SPECIAL_QP_SEND";
+	case PSIF_WR_EPS_QP0_SEND_DR_XMIT:
+		return "PSIF_WR_EPS_QP0_SEND_DR_XMIT";
+	case PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK:
+		return "PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK";
+	case PSIF_WR_RDMA_WR:
+		return "PSIF_WR_RDMA_WR";
+	case PSIF_WR_RDMA_WR_IMM:
+		return "PSIF_WR_RDMA_WR_IMM";
+	case PSIF_WR_RDMA_RD:
+		return "PSIF_WR_RDMA_RD";
+	case PSIF_WR_CMP_SWAP:
+		return "PSIF_WR_CMP_SWAP";
+	case PSIF_WR_FETCH_ADD:
+		return "PSIF_WR_FETCH_ADD";
+	case PSIF_WR_MASK_CMP_SWAP:
+		return "PSIF_WR_MASK_CMP_SWAP";
+	case PSIF_WR_MASK_FETCH_ADD:
+		return "PSIF_WR_MASK_FETCH_ADD";
+	case PSIF_WR_LSO:
+		return "PSIF_WR_LSO";
+	case PSIF_WR_INVALIDATE_RKEY:
+		return "PSIF_WR_INVALIDATE_RKEY";
+	case PSIF_WR_INVALIDATE_LKEY:
+		return "PSIF_WR_INVALIDATE_LKEY";
+	case PSIF_WR_INVALIDATE_BOTH_KEYS:
+		return "PSIF_WR_INVALIDATE_BOTH_KEYS";
+	case PSIF_WR_INVALIDATE_TLB:
+		return "PSIF_WR_INVALIDATE_TLB";
+	case PSIF_WR_RESIZE_CQ:
+		return "PSIF_WR_RESIZE_CQ";
+	case PSIF_WR_SET_SRQ_LIM:
+		return "PSIF_WR_SET_SRQ_LIM";
+	case PSIF_WR_SET_XRCSRQ_LIM:
+		return "PSIF_WR_SET_XRCSRQ_LIM";
+	case PSIF_WR_REQ_CMPL_NOTIFY:
+		return "PSIF_WR_REQ_CMPL_NOTIFY";
+	case PSIF_WR_CMPL_NOTIFY_RCVD:
+		return "PSIF_WR_CMPL_NOTIFY_RCVD";
+	case PSIF_WR_REARM_CMPL_EVENT:
+		return "PSIF_WR_REARM_CMPL_EVENT";
+	case PSIF_WR_GENERATE_COMPLETION:
+		return "PSIF_WR_GENERATE_COMPLETION";
+	case PSIF_WR_INVALIDATE_RQ:
+		return "PSIF_WR_INVALIDATE_RQ";
+	case PSIF_WR_INVALIDATE_CQ:
+		return "PSIF_WR_INVALIDATE_CQ";
+	case PSIF_WR_INVALIDATE_XRCSRQ:
+		return "PSIF_WR_INVALIDATE_XRCSRQ";
+	case PSIF_WR_INVALIDATE_SGL_CACHE:
+		return "PSIF_WR_INVALIDATE_SGL_CACHE";
+	default:
+		return "UNKNOWN_psif_wr_type";
+	}
+}
+
+void write_enum_psif_wr_type(XFILE *fd,
+	enum psif_wr_type data)
+{
+	xprintf(fd, "%s", string_enum_psif_wr_type(data));
+} /* end write_..._psif_wr_type(psif_wr_type data) */
+
+/* Convert enum psif_port to string */
+const char *string_enum_psif_port(enum psif_port val)
+{
+	switch (val) {
+	case PORT_1:
+		return "PORT_1";
+	case PORT_2:
+		return "PORT_2";
+	default:
+		return "UNKNOWN_psif_port";
+	}
+}
+
+void write_enum_psif_port(XFILE *fd,
+	enum psif_port data)
+{
+	xprintf(fd, "%s", string_enum_psif_port(data));
+} /* end write_..._psif_port(psif_port data) */
+
+/* Convert enum psif_use_ah to string */
+const char *string_enum_psif_use_ah(enum psif_use_ah val)
+{
+	switch (val) {
+	case NO_AHA:
+		return "NO_AHA";
+	case USE_AHA:
+		return "USE_AHA";
+	default:
+		return "UNKNOWN_psif_use_ah";
+	}
+}
+
+void write_enum_psif_use_ah(XFILE *fd,
+	enum psif_use_ah data)
+{
+	xprintf(fd, "%s", string_enum_psif_use_ah(data));
+} /* end write_..._psif_use_ah(psif_use_ah data) */
+
+/* Convert enum psif_tsu_qos to string */
+const char *string_enum_psif_tsu_qos(enum psif_tsu_qos val)
+{
+	switch (val) {
+	case QOSL_HIGH_BANDWIDTH:
+		return "QOSL_HIGH_BANDWIDTH";
+	case QOSL_LOW_LATENCY:
+		return "QOSL_LOW_LATENCY";
+	default:
+		return "UNKNOWN_psif_tsu_qos";
+	}
+}
+
+void write_enum_psif_tsu_qos(XFILE *fd,
+	enum psif_tsu_qos data)
+{
+	xprintf(fd, "%s", string_enum_psif_tsu_qos(data));
+} /* end write_..._psif_tsu_qos(psif_tsu_qos data) */
+
+/* Convert enum psif_wc_opcode to string */
+const char *string_enum_psif_wc_opcode(enum psif_wc_opcode val)
+{
+	switch (val) {
+	case PSIF_WC_OPCODE_SEND:
+		return "PSIF_WC_OPCODE_SEND";
+	case PSIF_WC_OPCODE_RDMA_WR:
+		return "PSIF_WC_OPCODE_RDMA_WR";
+	case PSIF_WC_OPCODE_RDMA_READ:
+		return "PSIF_WC_OPCODE_RDMA_READ";
+	case PSIF_WC_OPCODE_CMP_SWAP:
+		return "PSIF_WC_OPCODE_CMP_SWAP";
+	case PSIF_WC_OPCODE_FETCH_ADD:
+		return "PSIF_WC_OPCODE_FETCH_ADD";
+	case PSIF_WC_OPCODE_LSO:
+		return "PSIF_WC_OPCODE_LSO";
+	case PSIF_WC_OPCODE_MASKED_CMP_SWAP:
+		return "PSIF_WC_OPCODE_MASKED_CMP_SWAP";
+	case PSIF_WC_OPCODE_MASKED_FETCH_ADD:
+		return "PSIF_WC_OPCODE_MASKED_FETCH_ADD";
+	case PSIF_WC_OPCODE_INVALIDATE_RKEY:
+		return "PSIF_WC_OPCODE_INVALIDATE_RKEY";
+	case PSIF_WC_OPCODE_INVALIDATE_LKEY:
+		return "PSIF_WC_OPCODE_INVALIDATE_LKEY";
+	case PSIF_WC_OPCODE_INVALIDATE_BOTH_KEYS:
+		return "PSIF_WC_OPCODE_INVALIDATE_BOTH_KEYS";
+	case PSIF_WC_OPCODE_INVALIDATE_TLB:
+		return "PSIF_WC_OPCODE_INVALIDATE_TLB";
+	case PSIF_WC_OPCODE_RESIZE_CQ:
+		return "PSIF_WC_OPCODE_RESIZE_CQ";
+	case PSIF_WC_OPCODE_SET_SRQ_LIM:
+		return "PSIF_WC_OPCODE_SET_SRQ_LIM";
+	case PSIF_WC_OPCODE_SET_XRCSRQ_LIM:
+		return "PSIF_WC_OPCODE_SET_XRCSRQ_LIM";
+	case PSIF_WC_OPCODE_REQ_CMPL_NOTIFY:
+		return "PSIF_WC_OPCODE_REQ_CMPL_NOTIFY";
+	case PSIF_WC_OPCODE_CMPL_NOTIFY_RCVD:
+		return "PSIF_WC_OPCODE_CMPL_NOTIFY_RCVD";
+	case PSIF_WC_OPCODE_REARM_CMPL_EVENT:
+		return "PSIF_WC_OPCODE_REARM_CMPL_EVENT";
+	case PSIF_WC_OPCODE_GENERATE_COMPLETION:
+		return "PSIF_WC_OPCODE_GENERATE_COMPLETION";
+	case PSIF_WC_OPCODE_INVALIDATE_RQ:
+		return "PSIF_WC_OPCODE_INVALIDATE_RQ";
+	case PSIF_WC_OPCODE_INVALIDATE_CQ:
+		return "PSIF_WC_OPCODE_INVALIDATE_CQ";
+	case PSIF_WC_OPCODE_INVALIDATE_RB:
+		return "PSIF_WC_OPCODE_INVALIDATE_RB";
+	case PSIF_WC_OPCODE_INVALIDATE_XRCSRQ:
+		return "PSIF_WC_OPCODE_INVALIDATE_XRCSRQ";
+	case PSIF_WC_OPCODE_INVALIDATE_SGL_CACHE:
+		return "PSIF_WC_OPCODE_INVALIDATE_SGL_CACHE";
+	case PSIF_WC_OPCODE_RECEIVE_SEND:
+		return "PSIF_WC_OPCODE_RECEIVE_SEND";
+	case PSIF_WC_OPCODE_RECEIVE_RDMA_WR_IMM:
+		return "PSIF_WC_OPCODE_RECEIVE_RDMA_WR_IMM";
+	case PSIF_WC_OPCODE_RECEIVE_CONDITIONAL_WR_IMM:
+		return "PSIF_WC_OPCODE_RECEIVE_CONDITIONAL_WR_IMM";
+	default:
+		return "UNKNOWN_psif_wc_opcode";
+	}
+}
+
+void write_enum_psif_wc_opcode(XFILE *fd,
+	enum psif_wc_opcode data)
+{
+	xprintf(fd, "%s", string_enum_psif_wc_opcode(data));
+} /* end write_..._psif_wc_opcode(psif_wc_opcode data) */
+
+/* Convert enum psif_wc_status to string */
+const char *string_enum_psif_wc_status(enum psif_wc_status val)
+{
+	switch (val) {
+	case PSIF_WC_STATUS_SUCCESS:
+		return "PSIF_WC_STATUS_SUCCESS";
+	case PSIF_WC_STATUS_LOC_LEN_ERR:
+		return "PSIF_WC_STATUS_LOC_LEN_ERR";
+	case PSIF_WC_STATUS_LOC_QP_OP_ERR:
+		return "PSIF_WC_STATUS_LOC_QP_OP_ERR";
+	case PSIF_WC_STATUS_LOC_EEC_OP_ERR:
+		return "PSIF_WC_STATUS_LOC_EEC_OP_ERR";
+	case PSIF_WC_STATUS_LOC_PROT_ERR:
+		return "PSIF_WC_STATUS_LOC_PROT_ERR";
+	case PSIF_WC_STATUS_WR_FLUSH_ERR:
+		return "PSIF_WC_STATUS_WR_FLUSH_ERR";
+	case PSIF_WC_STATUS_MW_BIND_ERR:
+		return "PSIF_WC_STATUS_MW_BIND_ERR";
+	case PSIF_WC_STATUS_BAD_RESP_ERR:
+		return "PSIF_WC_STATUS_BAD_RESP_ERR";
+	case PSIF_WC_STATUS_LOC_ACCESS_ERR:
+		return "PSIF_WC_STATUS_LOC_ACCESS_ERR";
+	case PSIF_WC_STATUS_REM_INV_REQ_ERR:
+		return "PSIF_WC_STATUS_REM_INV_REQ_ERR";
+	case PSIF_WC_STATUS_REM_ACCESS_ERR:
+		return "PSIF_WC_STATUS_REM_ACCESS_ERR";
+	case PSIF_WC_STATUS_REM_OP_ERR:
+		return "PSIF_WC_STATUS_REM_OP_ERR";
+	case PSIF_WC_STATUS_RETRY_EXC_ERR:
+		return "PSIF_WC_STATUS_RETRY_EXC_ERR";
+	case PSIF_WC_STATUS_RNR_RETRY_EXC_ERR:
+		return "PSIF_WC_STATUS_RNR_RETRY_EXC_ERR";
+	case PSIF_WC_STATUS_LOC_RDD_VIOL_ERR:
+		return "PSIF_WC_STATUS_LOC_RDD_VIOL_ERR";
+	case PSIF_WC_STATUS_REM_INV_RD_REQ_ERR:
+		return "PSIF_WC_STATUS_REM_INV_RD_REQ_ERR";
+	case PSIF_WC_STATUS_REM_ABORT_ERR:
+		return "PSIF_WC_STATUS_REM_ABORT_ERR";
+	case PSIF_WC_STATUS_INV_EECN_ERR:
+		return "PSIF_WC_STATUS_INV_EECN_ERR";
+	case PSIF_WC_STATUS_INV_EEC_STATE_ERR:
+		return "PSIF_WC_STATUS_INV_EEC_STATE_ERR";
+	case PSIF_WC_STATUS_FATAL_ERR:
+		return "PSIF_WC_STATUS_FATAL_ERR";
+	case PSIF_WC_STATUS_RESP_TIMEOUT_ERR:
+		return "PSIF_WC_STATUS_RESP_TIMEOUT_ERR";
+	case PSIF_WC_STATUS_GENERAL_ERR:
+		return "PSIF_WC_STATUS_GENERAL_ERR";
+	case PSIF_WC_STATUS_FIELD_MAX:
+		return "PSIF_WC_STATUS_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_wc_status";
+	}
+}
+
+void write_enum_psif_wc_status(XFILE *fd,
+	enum psif_wc_status data)
+{
+	xprintf(fd, "%s", string_enum_psif_wc_status(data));
+} /* end write_..._psif_wc_status(psif_wc_status data) */
+
+/* Convert enum ib_opcode to string */
+const char *string_enum_ib_opcode(enum ib_opcode val)
+{
+	switch (val) {
+	case RC_SEND_First:
+		return "RC_SEND_First";
+	case RC_SEND_Middle:
+		return "RC_SEND_Middle";
+	case RC_SEND_Last:
+		return "RC_SEND_Last";
+	case RC_SEND_Last_Imm:
+		return "RC_SEND_Last_Imm";
+	case RC_SEND_Only:
+		return "RC_SEND_Only";
+	case RC_SEND_Only_Imm:
+		return "RC_SEND_Only_Imm";
+	case RC_RDMA_WR_First:
+		return "RC_RDMA_WR_First";
+	case RC_RDMA_WR_Middle:
+		return "RC_RDMA_WR_Middle";
+	case RC_RDMA_WR_Last:
+		return "RC_RDMA_WR_Last";
+	case RC_RDMA_WR_Last_Imm:
+		return "RC_RDMA_WR_Last_Imm";
+	case RC_RDMA_WR_Only:
+		return "RC_RDMA_WR_Only";
+	case RC_RDMA_WR_Only_Imm:
+		return "RC_RDMA_WR_Only_Imm";
+	case RC_RDMA_RD_Req:
+		return "RC_RDMA_RD_Req";
+	case RC_RDMA_RD_Resp_First:
+		return "RC_RDMA_RD_Resp_First";
+	case RC_RDMA_RD_Resp_Middle:
+		return "RC_RDMA_RD_Resp_Middle";
+	case RC_RDMA_RD_Resp_Last:
+		return "RC_RDMA_RD_Resp_Last";
+	case RC_RDMA_RD_Resp_Only:
+		return "RC_RDMA_RD_Resp_Only";
+	case RC_ACK:
+		return "RC_ACK";
+	case RC_Atomic_ACK:
+		return "RC_Atomic_ACK";
+	case RC_CmpSwap:
+		return "RC_CmpSwap";
+	case RC_FetchAdd:
+		return "RC_FetchAdd";
+	case RC_Reserved:
+		return "RC_Reserved";
+	case RC_SEND_Last_Invalid:
+		return "RC_SEND_Last_Invalid";
+	case RC_SEND_Only_Invalid:
+		return "RC_SEND_Only_Invalid";
+	case RC_MaskCmpSwap:
+		return "RC_MaskCmpSwap";
+	case RC_MaskFetchAdd:
+		return "RC_MaskFetchAdd";
+	case UC_SEND_First:
+		return "UC_SEND_First";
+	case UC_SEND_Middle:
+		return "UC_SEND_Middle";
+	case UC_SEND_Last:
+		return "UC_SEND_Last";
+	case UC_SEND_Last_Imm:
+		return "UC_SEND_Last_Imm";
+	case UC_SEND_Only:
+		return "UC_SEND_Only";
+	case UC_SEND_Only_Imm:
+		return "UC_SEND_Only_Imm";
+	case UC_RDMA_WR_First:
+		return "UC_RDMA_WR_First";
+	case UC_RDMA_WR_Middle:
+		return "UC_RDMA_WR_Middle";
+	case UC_RDMA_WR_Last:
+		return "UC_RDMA_WR_Last";
+	case UC_RDMA_WR_Last_Imm:
+		return "UC_RDMA_WR_Last_Imm";
+	case UC_RDMA_WR_Only:
+		return "UC_RDMA_WR_Only";
+	case UC_RDMA_WR_Only_Imm:
+		return "UC_RDMA_WR_Only_Imm";
+	case RD_SEND_First:
+		return "RD_SEND_First";
+	case RD_SEND_Middle:
+		return "RD_SEND_Middle";
+	case RD_SEND_Last:
+		return "RD_SEND_Last";
+	case RD_SEND_Last_Imm:
+		return "RD_SEND_Last_Imm";
+	case RD_SEND_Only:
+		return "RD_SEND_Only";
+	case RD_SEND_Only_Imm:
+		return "RD_SEND_Only_Imm";
+	case RD_RDMA_WR_First:
+		return "RD_RDMA_WR_First";
+	case RD_RDMA_WR_Middle:
+		return "RD_RDMA_WR_Middle";
+	case RD_RDMA_WR_Last:
+		return "RD_RDMA_WR_Last";
+	case RD_RDMA_WR_Last_Imm:
+		return "RD_RDMA_WR_Last_Imm";
+	case RD_RDMA_WR_Only:
+		return "RD_RDMA_WR_Only";
+	case RD_RDMA_WR_Only_Imm:
+		return "RD_RDMA_WR_Only_Imm";
+	case RD_RDMA_RD_Req:
+		return "RD_RDMA_RD_Req";
+	case RD_RDMA_RD_Resp_First:
+		return "RD_RDMA_RD_Resp_First";
+	case RD_RDMA_RD_Resp_Middle:
+		return "RD_RDMA_RD_Resp_Middle";
+	case RD_RDMA_RD_Resp_Last:
+		return "RD_RDMA_RD_Resp_Last";
+	case RD_RDMA_RD_Resp_Only:
+		return "RD_RDMA_RD_Resp_Only";
+	case RD_ACK:
+		return "RD_ACK";
+	case RD_Atomic_ACK:
+		return "RD_Atomic_ACK";
+	case RD_CmpSwap:
+		return "RD_CmpSwap";
+	case RD_FetchAdd:
+		return "RD_FetchAdd";
+	case RD_RESYNC:
+		return "RD_RESYNC";
+	case UD_SEND_Only:
+		return "UD_SEND_Only";
+	case UD_SEND_Only_Imm:
+		return "UD_SEND_Only_Imm";
+	case CNP:
+		return "CNP";
+	case XRC_SEND_First:
+		return "XRC_SEND_First";
+	case XRC_SEND_Middle:
+		return "XRC_SEND_Middle";
+	case XRC_SEND_Last:
+		return "XRC_SEND_Last";
+	case XRC_SEND_Last_Imm:
+		return "XRC_SEND_Last_Imm";
+	case XRC_SEND_Only:
+		return "XRC_SEND_Only";
+	case XRC_SEND_Only_Imm:
+		return "XRC_SEND_Only_Imm";
+	case XRC_RDMA_WR_First:
+		return "XRC_RDMA_WR_First";
+	case XRC_RDMA_WR_Middle:
+		return "XRC_RDMA_WR_Middle";
+	case XRC_RDMA_WR_Last:
+		return "XRC_RDMA_WR_Last";
+	case XRC_RDMA_WR_Last_Imm:
+		return "XRC_RDMA_WR_Last_Imm";
+	case XRC_RDMA_WR_Only:
+		return "XRC_RDMA_WR_Only";
+	case XRC_RDMA_WR_Only_Imm:
+		return "XRC_RDMA_WR_Only_Imm";
+	case XRC_RDMA_RD_Req:
+		return "XRC_RDMA_RD_Req";
+	case XRC_RDMA_RD_Resp_First:
+		return "XRC_RDMA_RD_Resp_First";
+	case XRC_RDMA_RD_Resp_Middle:
+		return "XRC_RDMA_RD_Resp_Middle";
+	case XRC_RDMA_RD_Resp_Last:
+		return "XRC_RDMA_RD_Resp_Last";
+	case XRC_RDMA_RD_Resp_Only:
+		return "XRC_RDMA_RD_Resp_Only";
+	case XRC_ACK:
+		return "XRC_ACK";
+	case XRC_Atomic_ACK:
+		return "XRC_Atomic_ACK";
+	case XRC_CmpSwap:
+		return "XRC_CmpSwap";
+	case XRC_FetchAdd:
+		return "XRC_FetchAdd";
+	case XRC_Reserved:
+		return "XRC_Reserved";
+	case XRC_SEND_Last_Invalid:
+		return "XRC_SEND_Last_Invalid";
+	case XRC_SEND_Only_Invalid:
+		return "XRC_SEND_Only_Invalid";
+	case XRC_MaskCmpSwap:
+		return "XRC_MaskCmpSwap";
+	case XRC_MaskFetchAdd:
+		return "XRC_MaskFetchAdd";
+	case MANSP1_INVALID:
+		return "MANSP1_INVALID";
+	case MANSP1_HOST_READ:
+		return "MANSP1_HOST_READ";
+	case MANSP1_HOST_WRITE:
+		return "MANSP1_HOST_WRITE";
+	case MANSP1_HOST_READ_NO_DMAVT:
+		return "MANSP1_HOST_READ_NO_DMAVT";
+	case MANSP1_HOST_WRITE_NO_DMAVT:
+		return "MANSP1_HOST_WRITE_NO_DMAVT";
+	case MANSP1_INTERNAL_TYPE:
+		return "MANSP1_INTERNAL_TYPE";
+	case MANSP1_INTERNAL_TYPE_MMU_BYPASS:
+		return "MANSP1_INTERNAL_TYPE_MMU_BYPASS";
+	case MANSP1_HOST_CMP_SWAP:
+		return "MANSP1_HOST_CMP_SWAP";
+	case MANSP1_DR_LOOPBACK:
+		return "MANSP1_DR_LOOPBACK";
+	case MANSP1_ARP_LOOPBACK:
+		return "MANSP1_ARP_LOOPBACK";
+	default:
+		return "UNKNOWN_ib_opcode";
+	}
+}
+
+void write_enum_ib_opcode(XFILE *fd,
+	enum ib_opcode data)
+{
+	xprintf(fd, "%s", string_enum_ib_opcode(data));
+} /* end write_..._ib_opcode(ib_opcode data) */
+
+/* Convert enum psif_eps_a_core to string */
+const char *string_enum_psif_eps_a_core(enum psif_eps_a_core val)
+{
+	switch (val) {
+	case PSIF_EPS_A_1:
+		return "PSIF_EPS_A_1";
+	case PSIF_EPS_A_2:
+		return "PSIF_EPS_A_2";
+	case PSIF_EPS_A_3:
+		return "PSIF_EPS_A_3";
+	case PSIF_EPS_A_4:
+		return "PSIF_EPS_A_4";
+	default:
+		return "UNKNOWN_psif_eps_a_core";
+	}
+}
+
+void write_enum_psif_eps_a_core(XFILE *fd,
+	enum psif_eps_a_core data)
+{
+	xprintf(fd, "%s", string_enum_psif_eps_a_core(data));
+} /* end write_..._psif_eps_a_core(psif_eps_a_core data) */
+
+/* Convert enum psif_qp_state to string */
+const char *string_enum_psif_qp_state(enum psif_qp_state val)
+{
+	switch (val) {
+	case PSIF_QP_STATE_RESET:
+		return "PSIF_QP_STATE_RESET";
+	case PSIF_QP_STATE_INIT:
+		return "PSIF_QP_STATE_INIT";
+	case PSIF_QP_STATE_RTR:
+		return "PSIF_QP_STATE_RTR";
+	case PSIF_QP_STATE_RTS:
+		return "PSIF_QP_STATE_RTS";
+	case PSIF_QP_STATE_SQERR:
+		return "PSIF_QP_STATE_SQERR";
+	case PSIF_QP_STATE_ERROR:
+		return "PSIF_QP_STATE_ERROR";
+	case PSIF_QP_STATE_INVALID:
+		return "PSIF_QP_STATE_INVALID";
+	default:
+		return "UNKNOWN_psif_qp_state";
+	}
+}
+
+void write_enum_psif_qp_state(XFILE *fd,
+	enum psif_qp_state data)
+{
+	xprintf(fd, "%s", string_enum_psif_qp_state(data));
+} /* end write_..._psif_qp_state(psif_qp_state data) */
+
+/* Convert enum psif_cmpl_outstanding_error to string */
+const char *string_enum_psif_cmpl_outstanding_error(enum psif_cmpl_outstanding_error val)
+{
+	switch (val) {
+	case CMPL_NO_ERROR:
+		return "CMPL_NO_ERROR";
+	case CMPL_RQS_INVALID_REQUEST_ERR:
+		return "CMPL_RQS_INVALID_REQUEST_ERR";
+	case CMPL_RQS_QP_IN_WRONG_STATE_ERR:
+		return "CMPL_RQS_QP_IN_WRONG_STATE_ERR";
+	case CMPL_RQS_MAX_OUTSTANDING_REACHED_ERR:
+		return "CMPL_RQS_MAX_OUTSTANDING_REACHED_ERR";
+	case CMPL_RQS_REQUEST_FENCED_ERR:
+		return "CMPL_RQS_REQUEST_FENCED_ERR";
+	case CMPL_RQS_CMD_FROM_EPS_ERR:
+		return "CMPL_RQS_CMD_FROM_EPS_ERR";
+	case CMPL_DMA_SGL_RD_ERR:
+		return "CMPL_DMA_SGL_RD_ERR";
+	case CMPL_DMA_PYLD_RD_ERR:
+		return "CMPL_DMA_PYLD_RD_ERR";
+	case CMPL_DMA_SGL_LENGTH_ERR:
+		return "CMPL_DMA_SGL_LENGTH_ERR";
+	case CMPL_DMA_LKEY_ERR:
+		return "CMPL_DMA_LKEY_ERR";
+	default:
+		return "UNKNOWN_psif_cmpl_outstanding_error";
+	}
+}
+
+void write_enum_psif_cmpl_outstanding_error(XFILE *fd,
+	enum psif_cmpl_outstanding_error data)
+{
+	xprintf(fd, "%s", string_enum_psif_cmpl_outstanding_error(data));
+} /* end write_..._psif_cmpl_outstanding_error(psif_cmpl_outstanding_error data) */
+
+/* Convert enum psif_expected_op to string */
+const char *string_enum_psif_expected_op(enum psif_expected_op val)
+{
+	switch (val) {
+	case NO_OPERATION_IN_PROGRESS:
+		return "NO_OPERATION_IN_PROGRESS";
+	case EXPECT_SEND_MIDDLE_LAST:
+		return "EXPECT_SEND_MIDDLE_LAST";
+	case EXPECT_RDMA_WR_MIDDLE_LAST:
+		return "EXPECT_RDMA_WR_MIDDLE_LAST";
+	case EXPECT_DM_PUT_MIDDLE_LAST:
+		return "EXPECT_DM_PUT_MIDDLE_LAST";
+	default:
+		return "UNKNOWN_psif_expected_op";
+	}
+}
+
+void write_enum_psif_expected_op(XFILE *fd,
+	enum psif_expected_op data)
+{
+	xprintf(fd, "%s", string_enum_psif_expected_op(data));
+} /* end write_..._psif_expected_op(psif_expected_op data) */
+
+/* Convert enum psif_migration to string */
+const char *string_enum_psif_migration(enum psif_migration val)
+{
+	switch (val) {
+	case APM_OFF:
+		return "APM_OFF";
+	case APM_MIGRATED:
+		return "APM_MIGRATED";
+	case APM_REARM:
+		return "APM_REARM";
+	case APM_ARMED:
+		return "APM_ARMED";
+	default:
+		return "UNKNOWN_psif_migration";
+	}
+}
+
+void write_enum_psif_migration(XFILE *fd,
+	enum psif_migration data)
+{
+	xprintf(fd, "%s", string_enum_psif_migration(data));
+} /* end write_..._psif_migration(psif_migration data) */
+
+/* Convert enum psif_qp_trans to string */
+const char *string_enum_psif_qp_trans(enum psif_qp_trans val)
+{
+	switch (val) {
+	case PSIF_QP_TRANSPORT_RC:
+		return "PSIF_QP_TRANSPORT_RC";
+	case PSIF_QP_TRANSPORT_UC:
+		return "PSIF_QP_TRANSPORT_UC";
+	case PSIF_QP_TRANSPORT_RD:
+		return "PSIF_QP_TRANSPORT_RD";
+	case PSIF_QP_TRANSPORT_UD:
+		return "PSIF_QP_TRANSPORT_UD";
+	case PSIF_QP_TRANSPORT_RSVD1:
+		return "PSIF_QP_TRANSPORT_RSVD1";
+	case PSIF_QP_TRANSPORT_XRC:
+		return "PSIF_QP_TRANSPORT_XRC";
+	case PSIF_QP_TRANSPORT_MANSP1:
+		return "PSIF_QP_TRANSPORT_MANSP1";
+	case PSIF_QP_TRANSPORT_MANSP2:
+		return "PSIF_QP_TRANSPORT_MANSP2";
+	default:
+		return "UNKNOWN_psif_qp_trans";
+	}
+}
+
+void write_enum_psif_qp_trans(XFILE *fd,
+	enum psif_qp_trans data)
+{
+	xprintf(fd, "%s", string_enum_psif_qp_trans(data));
+} /* end write_..._psif_qp_trans(psif_qp_trans data) */
+
+/* Convert enum psif_bool to string */
+const char *string_enum_psif_bool(enum psif_bool val)
+{
+	switch (val) {
+	case FALSE:
+		return "FALSE";
+	case TRUE:
+		return "TRUE";
+	default:
+		return "UNKNOWN_psif_bool";
+	}
+}
+
+void write_enum_psif_bool(XFILE *fd,
+	enum psif_bool data)
+{
+	xprintf(fd, "%s", string_enum_psif_bool(data));
+} /* end write_..._psif_bool(psif_bool data) */
+
+/* Convert enum psif_eoib_type to string */
+const char *string_enum_psif_eoib_type(enum psif_eoib_type val)
+{
+	switch (val) {
+	case EOIB_FULL:
+		return "EOIB_FULL";
+	case EOIB_PARTIAL:
+		return "EOIB_PARTIAL";
+	case EOIB_QKEY_ONLY:
+		return "EOIB_QKEY_ONLY";
+	case EOIB_NONE:
+		return "EOIB_NONE";
+	default:
+		return "UNKNOWN_psif_eoib_type";
+	}
+}
+
+void write_enum_psif_eoib_type(XFILE *fd,
+	enum psif_eoib_type data)
+{
+	xprintf(fd, "%s", string_enum_psif_eoib_type(data));
+} /* end write_..._psif_eoib_type(psif_eoib_type data) */
+
+/* Convert enum psif_comm_live to string */
+const char *string_enum_psif_comm_live(enum psif_comm_live val)
+{
+	switch (val) {
+	case NO_COMM_ESTABLISHED:
+		return "NO_COMM_ESTABLISHED";
+	case COMM_ESTABLISHED:
+		return "COMM_ESTABLISHED";
+	default:
+		return "UNKNOWN_psif_comm_live";
+	}
+}
+
+void write_enum_psif_comm_live(XFILE *fd,
+	enum psif_comm_live data)
+{
+	xprintf(fd, "%s", string_enum_psif_comm_live(data));
+} /* end write_..._psif_comm_live(psif_comm_live data) */
+
+/* Convert enum psif_path_mtu to string */
+const char *string_enum_psif_path_mtu(enum psif_path_mtu val)
+{
+	switch (val) {
+	case MTU_INVALID:
+		return "MTU_INVALID";
+	case MTU_256B:
+		return "MTU_256B";
+	case MTU_512B:
+		return "MTU_512B";
+	case MTU_1024B:
+		return "MTU_1024B";
+	case MTU_2048B:
+		return "MTU_2048B";
+	case MTU_4096B:
+		return "MTU_4096B";
+	case MTU_10240B:
+		return "MTU_10240B";
+	case MTU_XXX:
+		return "MTU_XXX";
+	default:
+		return "UNKNOWN_psif_path_mtu";
+	}
+}
+
+void write_enum_psif_path_mtu(XFILE *fd,
+	enum psif_path_mtu data)
+{
+	xprintf(fd, "%s", string_enum_psif_path_mtu(data));
+} /* end write_..._psif_path_mtu(psif_path_mtu data) */
+
+/* Convert enum psif_use_grh to string */
+const char *string_enum_psif_use_grh(enum psif_use_grh val)
+{
+	switch (val) {
+	case NO_GRH:
+		return "NO_GRH";
+	case USE_GRH:
+		return "USE_GRH";
+	default:
+		return "UNKNOWN_psif_use_grh";
+	}
+}
+
+void write_enum_psif_use_grh(XFILE *fd,
+	enum psif_use_grh data)
+{
+	xprintf(fd, "%s", string_enum_psif_use_grh(data));
+} /* end write_..._psif_use_grh(psif_use_grh data) */
+
+/* Convert enum psif_loopback to string */
+const char *string_enum_psif_loopback(enum psif_loopback val)
+{
+	switch (val) {
+	case NO_LOOPBACK:
+		return "NO_LOOPBACK";
+	case LOOPBACK:
+		return "LOOPBACK";
+	default:
+		return "UNKNOWN_psif_loopback";
+	}
+}
+
+void write_enum_psif_loopback(XFILE *fd,
+	enum psif_loopback data)
+{
+	xprintf(fd, "%s", string_enum_psif_loopback(data));
+} /* end write_..._psif_loopback(psif_loopback data) */
+
+/* Convert enum psif_qp_command to string */
+const char *string_enum_psif_qp_command(enum psif_qp_command val)
+{
+	switch (val) {
+	case QP_CMD_INVALID:
+		return "QP_CMD_INVALID";
+	case QP_CMD_MODIFY:
+		return "QP_CMD_MODIFY";
+	case QP_CMD_QUERY:
+		return "QP_CMD_QUERY";
+	case QP_CMD_CHECK_TIMEOUT:
+		return "QP_CMD_CHECK_TIMEOUT";
+	default:
+		return "UNKNOWN_psif_qp_command";
+	}
+}
+
+void write_enum_psif_qp_command(XFILE *fd,
+	enum psif_qp_command data)
+{
+	xprintf(fd, "%s", string_enum_psif_qp_command(data));
+} /* end write_..._psif_qp_command(psif_qp_command data) */
+
+/* Convert enum psif_mbox_type to string */
+const char *string_enum_psif_mbox_type(enum psif_mbox_type val)
+{
+	switch (val) {
+	case MBOX_EPSA0:
+		return "MBOX_EPSA0";
+	case MBOX_EPSA1:
+		return "MBOX_EPSA1";
+	case MBOX_EPSA2:
+		return "MBOX_EPSA2";
+	case MBOX_EPSA3:
+		return "MBOX_EPSA3";
+	case MBOX_EPSC:
+		return "MBOX_EPSC";
+	case MBOX_EPS_MAX:
+		return "MBOX_EPS_MAX";
+	case PSIF_MBOX_TYPE_FIELD_MAX:
+		return "PSIF_MBOX_TYPE_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_mbox_type";
+	}
+}
+
+void write_enum_psif_mbox_type(XFILE *fd,
+	enum psif_mbox_type data)
+{
+	xprintf(fd, "%s", string_enum_psif_mbox_type(data));
+} /* end write_..._psif_mbox_type(psif_mbox_type data) */
+
+/* Convert enum psif_dma_vt_key_states to string */
+const char *string_enum_psif_dma_vt_key_states(enum psif_dma_vt_key_states val)
+{
+	switch (val) {
+	case PSIF_DMA_KEY_INVALID:
+		return "PSIF_DMA_KEY_INVALID";
+	case PSIF_DMA_KEY_FREE:
+		return "PSIF_DMA_KEY_FREE";
+	case PSIF_DMA_KEY_VALID:
+		return "PSIF_DMA_KEY_VALID";
+	case PSIF_DMA_KEY_MMU_VALID:
+		return "PSIF_DMA_KEY_MMU_VALID";
+	default:
+		return "UNKNOWN_psif_dma_vt_key_states";
+	}
+}
+
+void write_enum_psif_dma_vt_key_states(XFILE *fd,
+	enum psif_dma_vt_key_states data)
+{
+	xprintf(fd, "%s", string_enum_psif_dma_vt_key_states(data));
+} /* end write_..._psif_dma_vt_key_states(psif_dma_vt_key_states data) */
+
+/* Convert enum psif_flash_image_type to string */
+const char *string_enum_psif_flash_image_type(enum psif_flash_image_type val)
+{
+	switch (val) {
+	case PSIF_IMAGE_INVALID:
+		return "PSIF_IMAGE_INVALID";
+	case PSIF_IMAGE_BOOT_LOADER:
+		return "PSIF_IMAGE_BOOT_LOADER";
+	case PSIF_IMAGE_EPS_C_APPLICATION:
+		return "PSIF_IMAGE_EPS_C_APPLICATION";
+	case PSIF_IMAGE_EPS_A_APPLICATION:
+		return "PSIF_IMAGE_EPS_A_APPLICATION";
+	case PSIF_IMAGE_DIAGNOSTICS:
+		return "PSIF_IMAGE_DIAGNOSTICS";
+	case PSIF_FLASH_IMAGE_TYPE_FIELD_MAX:
+		return "PSIF_FLASH_IMAGE_TYPE_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_flash_image_type";
+	}
+}
+
+void write_enum_psif_flash_image_type(XFILE *fd,
+	enum psif_flash_image_type data)
+{
+	xprintf(fd, "%s", string_enum_psif_flash_image_type(data));
+} /* end write_..._psif_flash_image_type(psif_flash_image_type data) */
+
+/* Convert enum psif_event to string */
+const char *string_enum_psif_event(enum psif_event val)
+{
+	switch (val) {
+	case PSIF_EVENT_NO_CHANGE:
+		return "PSIF_EVENT_NO_CHANGE";
+	case PSIF_EVENT_SGID_TABLE_CHANGED:
+		return "PSIF_EVENT_SGID_TABLE_CHANGED";
+	case PSIF_EVENT_PKEY_TABLE_CHANGED:
+		return "PSIF_EVENT_PKEY_TABLE_CHANGED";
+	case PSIF_EVENT_MASTER_SM_LID_CHANGED:
+		return "PSIF_EVENT_MASTER_SM_LID_CHANGED";
+	case PSIF_EVENT_MASTER_SM_SL_CHANGED:
+		return "PSIF_EVENT_MASTER_SM_SL_CHANGED";
+	case PSIF_EVENT_SUBNET_TIMEOUT_CHANGED:
+		return "PSIF_EVENT_SUBNET_TIMEOUT_CHANGED";
+	case PSIF_EVENT_IS_SM_DISABLED_CHANGED:
+		return "PSIF_EVENT_IS_SM_DISABLED_CHANGED";
+	case PSIF_EVENT_CLIENT_REREGISTER:
+		return "PSIF_EVENT_CLIENT_REREGISTER";
+	case PSIF_EVENT_LID_TABLE_CHANGED:
+		return "PSIF_EVENT_LID_TABLE_CHANGED";
+	case PSIF_EVENT_EPSC_COMPLETION:
+		return "PSIF_EVENT_EPSC_COMPLETION";
+	case PSIF_EVENT_MAILBOX:
+		return "PSIF_EVENT_MAILBOX";
+	case PSIF_EVENT_EXTENSION:
+		return "PSIF_EVENT_EXTENSION";
+	case PSIF_EVENT_LOG:
+		return "PSIF_EVENT_LOG";
+	case PSIF_EVENT_PORT_ACTIVE:
+		return "PSIF_EVENT_PORT_ACTIVE";
+	case PSIF_EVENT_PORT_ERR:
+		return "PSIF_EVENT_PORT_ERR";
+	case PSIF_EVENT_QUEUE_FULL:
+		return "PSIF_EVENT_QUEUE_FULL";
+	case PSIF_EVENT_DEGRADED_MODE:
+		return "PSIF_EVENT_DEGRADED_MODE";
+	case PSIF_EVENT_EPSC_KEEP_ALIVE:
+		return "PSIF_EVENT_EPSC_KEEP_ALIVE";
+	case PSIF_EVENT_EPSC_MMU_FLUSH_DONE:
+		return "PSIF_EVENT_EPSC_MMU_FLUSH_DONE";
+	case PSIF_EVENT_FIELD_MAX:
+		return "PSIF_EVENT_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_event";
+	}
+}
+
+void write_enum_psif_event(XFILE *fd,
+	enum psif_event data)
+{
+	xprintf(fd, "%s", string_enum_psif_event(data));
+} /* end write_..._psif_event(psif_event data) */
+
+/* Convert enum psif_tsu_error_types to string */
+const char *string_enum_psif_tsu_error_types(enum psif_tsu_error_types val)
+{
+	switch (val) {
+	case TSU_NO_ERROR:
+		return "TSU_NO_ERROR";
+	case TSU_IBPR_ICRC_ERR:
+		return "TSU_IBPR_ICRC_ERR";
+	case TSU_IBPR_INVALID_PKEY_ERR:
+		return "TSU_IBPR_INVALID_PKEY_ERR";
+	case TSU_IBPR_INVALID_QP_ERR:
+		return "TSU_IBPR_INVALID_QP_ERR";
+	case TSU_IBPR_VSWITCH_UF_ERR:
+		return "TSU_IBPR_VSWITCH_UF_ERR";
+	case TSU_IBPR_PKTLEN_ERR:
+		return "TSU_IBPR_PKTLEN_ERR";
+	case TSU_IBPR_UNDEFINED_OPCODE_ERR:
+		return "TSU_IBPR_UNDEFINED_OPCODE_ERR";
+	case TSU_IBPR_MCAST_NO_GRH_ERR:
+		return "TSU_IBPR_MCAST_NO_GRH_ERR";
+	case TSU_IBPR_MCAST_NO_TARGET_ERR:
+		return "TSU_IBPR_MCAST_NO_TARGET_ERR";
+	case TSU_IBPR_INVALID_DGID_ERR:
+		return "TSU_IBPR_INVALID_DGID_ERR";
+	case TSU_IBPR_BADPKT_ERR:
+		return "TSU_IBPR_BADPKT_ERR";
+	case TSU_RCV_QP_INVALID_ERR:
+		return "TSU_RCV_QP_INVALID_ERR";
+	case TSU_RCV_HDR_BTH_TVER_ERR:
+		return "TSU_RCV_HDR_BTH_TVER_ERR";
+	case TSU_RCV_HDR_BTH_QP_ERR:
+		return "TSU_RCV_HDR_BTH_QP_ERR";
+	case TSU_RCV_HDR_GRH_ERR:
+		return "TSU_RCV_HDR_GRH_ERR";
+	case TSU_RCV_HDR_PKEY_ERR:
+		return "TSU_RCV_HDR_PKEY_ERR";
+	case TSU_RCV_HDR_QKEY_ERR:
+		return "TSU_RCV_HDR_QKEY_ERR";
+	case TSU_RCV_HDR_LID_ERR:
+		return "TSU_RCV_HDR_LID_ERR";
+	case TSU_RCV_HDR_MAD_ERR:
+		return "TSU_RCV_HDR_MAD_ERR";
+	case TSU_RCV_EOIB_MCAST_ERR:
+		return "TSU_RCV_EOIB_MCAST_ERR";
+	case TSU_RCV_EOIB_BCAST_ERR:
+		return "TSU_RCV_EOIB_BCAST_ERR";
+	case TSU_RCV_EOIB_UCAST_ERR:
+		return "TSU_RCV_EOIB_UCAST_ERR";
+	case TSU_RCV_EOIB_TCP_PORT_VIOLATION_ERR:
+		return "TSU_RCV_EOIB_TCP_PORT_VIOLATION_ERR";
+	case TSU_RCV_EOIB_RUNTS_ERR:
+		return "TSU_RCV_EOIB_RUNTS_ERR";
+	case TSU_RCV_EOIB_OUTER_VLAN_ERR:
+		return "TSU_RCV_EOIB_OUTER_VLAN_ERR";
+	case TSU_RCV_EOIB_VLAN_TAG_ERR:
+		return "TSU_RCV_EOIB_VLAN_TAG_ERR";
+	case TSU_RCV_EOIB_VID_ERR:
+		return "TSU_RCV_EOIB_VID_ERR";
+	case TSU_RCV_IPOIB_TCP_PORT_VIOLATION_ERR:
+		return "TSU_RCV_IPOIB_TCP_PORT_VIOLATION_ERR";
+	case TSU_RCV_MCAST_DUP_ERR:
+		return "TSU_RCV_MCAST_DUP_ERR";
+	case TSU_RCV_ECC_ERR:
+		return "TSU_RCV_ECC_ERR";
+	case TSU_DSCR_RESPONDER_RC_PSN_ERR:
+		return "TSU_DSCR_RESPONDER_RC_PSN_ERR";
+	case TSU_DSCR_RESPONDER_RC_DUPLICATE:
+		return "TSU_DSCR_RESPONDER_RC_DUPLICATE";
+	case TSU_DSCR_RESPONDER_RC_OPCODE_SEQ_ERR:
+		return "TSU_DSCR_RESPONDER_RC_OPCODE_SEQ_ERR";
+	case TSU_DSCR_RESPONDER_RC_OPCODE_VAL_ERR:
+		return "TSU_DSCR_RESPONDER_RC_OPCODE_VAL_ERR";
+	case TSU_DSCR_RESPONDER_RC_OPCODE_LEN_ERR:
+		return "TSU_DSCR_RESPONDER_RC_OPCODE_LEN_ERR";
+	case TSU_DSCR_RESPONDER_RC_DMALEN_ERR:
+		return "TSU_DSCR_RESPONDER_RC_DMALEN_ERR";
+	case TSU_DSCR_RESPONDER_XRC_PSN_ERR:
+		return "TSU_DSCR_RESPONDER_XRC_PSN_ERR";
+	case TSU_DSCR_RESPONDER_XRC_DUPLICATE:
+		return "TSU_DSCR_RESPONDER_XRC_DUPLICATE";
+	case TSU_DSCR_RESPONDER_XRC_OPCODE_SEQ_ERR:
+		return "TSU_DSCR_RESPONDER_XRC_OPCODE_SEQ_ERR";
+	case TSU_DSCR_RESPONDER_XRC_OPCODE_VAL_ERR:
+		return "TSU_DSCR_RESPONDER_XRC_OPCODE_VAL_ERR";
+	case TSU_DSCR_RESPONDER_XRC_OPCODE_LEN_ERR:
+		return "TSU_DSCR_RESPONDER_XRC_OPCODE_LEN_ERR";
+	case TSU_DSCR_RESPONDER_XRC_DMALEN_ERR:
+		return "TSU_DSCR_RESPONDER_XRC_DMALEN_ERR";
+	case TSU_DSCR_RESPONDER_UC_PSN_ERR:
+		return "TSU_DSCR_RESPONDER_UC_PSN_ERR";
+	case TSU_DSCR_RESPONDER_UC_OPCODE_SEQ_ERR:
+		return "TSU_DSCR_RESPONDER_UC_OPCODE_SEQ_ERR";
+	case TSU_DSCR_RESPONDER_UC_OPCODE_VAL_ERR:
+		return "TSU_DSCR_RESPONDER_UC_OPCODE_VAL_ERR";
+	case TSU_DSCR_RESPONDER_UC_OPCODE_LEN_ERR:
+		return "TSU_DSCR_RESPONDER_UC_OPCODE_LEN_ERR";
+	case TSU_DSCR_RESPONDER_UC_DMALEN_ERR:
+		return "TSU_DSCR_RESPONDER_UC_DMALEN_ERR";
+	case TSU_DSCR_RESPONDER_UD_OPCODE_LEN_ERR:
+		return "TSU_DSCR_RESPONDER_UD_OPCODE_LEN_ERR";
+	case TSU_DSCR_RESPONDER_DUPLICATE_WITH_ERR:
+		return "TSU_DSCR_RESPONDER_DUPLICATE_WITH_ERR";
+	case TSU_DSCR_QP_CAP_MASKED_ATOMIC_ENABLE_ERR:
+		return "TSU_DSCR_QP_CAP_MASKED_ATOMIC_ENABLE_ERR";
+	case TSU_DSCR_QP_CAP_RDMA_RD_ENABLE_ERR:
+		return "TSU_DSCR_QP_CAP_RDMA_RD_ENABLE_ERR";
+	case TSU_DSCR_QP_CAP_RDMA_WR_ENABLE_ERR:
+		return "TSU_DSCR_QP_CAP_RDMA_WR_ENABLE_ERR";
+	case TSU_DSCR_QP_CAP_ATOMIC_ENABLE_ERR:
+		return "TSU_DSCR_QP_CAP_ATOMIC_ENABLE_ERR";
+	case TSU_DSCR_XRC_DOMAIN_VIOLATION_ERR:
+		return "TSU_DSCR_XRC_DOMAIN_VIOLATION_ERR";
+	case TSU_DSCR_XRCETH_ERR:
+		return "TSU_DSCR_XRCETH_ERR";
+	case TSU_DSCR_RQ_INVALID_ERR:
+		return "TSU_DSCR_RQ_INVALID_ERR";
+	case TSU_DSCR_RQ_PD_CHECK_ERR:
+		return "TSU_DSCR_RQ_PD_CHECK_ERR";
+	case TSU_DSCR_RQ_EMPTY_ERR:
+		return "TSU_DSCR_RQ_EMPTY_ERR";
+	case TSU_DSCR_RQ_IN_ERROR_ERR:
+		return "TSU_DSCR_RQ_IN_ERROR_ERR";
+	case TSU_DSCR_TRANSLATION_TYPE_ERR:
+		return "TSU_DSCR_TRANSLATION_TYPE_ERR";
+	case TSU_DSCR_RQ_DESCRIPTOR_INCONSISTENT_ERR:
+		return "TSU_DSCR_RQ_DESCRIPTOR_INCONSISTENT_ERR";
+	case TSU_DSCR_MISALIGNED_ATOMIC_ERR:
+		return "TSU_DSCR_MISALIGNED_ATOMIC_ERR";
+	case TSU_DSCR_PCIE_ERR:
+		return "TSU_DSCR_PCIE_ERR";
+	case TSU_DSCR_ECC_ERR:
+		return "TSU_DSCR_ECC_ERR";
+	case TSU_RQH_PCIE_ERR:
+		return "TSU_RQH_PCIE_ERR";
+	case TSU_RQH_SGL_LKEY_ERR:
+		return "TSU_RQH_SGL_LKEY_ERR";
+	case TSU_RQH_NOT_ENOUGH_RQ_SPACE_ERR:
+		return "TSU_RQH_NOT_ENOUGH_RQ_SPACE_ERR";
+	case TSU_RQH_ECC_ERR:
+		return "TSU_RQH_ECC_ERR";
+	case TSU_VAL_DUPLICATE_WITH_ERR:
+		return "TSU_VAL_DUPLICATE_WITH_ERR";
+	case TSU_VAL_RKEY_VLD_ERR:
+		return "TSU_VAL_RKEY_VLD_ERR";
+	case TSU_VAL_RKEY_ADDR_RANGE_ERR:
+		return "TSU_VAL_RKEY_ADDR_RANGE_ERR";
+	case TSU_VAL_RKEY_ACCESS_ERR:
+		return "TSU_VAL_RKEY_ACCESS_ERR";
+	case TSU_VAL_RKEY_PD_ERR:
+		return "TSU_VAL_RKEY_PD_ERR";
+	case TSU_VAL_RKEY_RANGE_ERR:
+		return "TSU_VAL_RKEY_RANGE_ERR";
+	case TSU_VAL_LKEY_VLD_ERR:
+		return "TSU_VAL_LKEY_VLD_ERR";
+	case TSU_VAL_LKEY_ADDR_RANGE_ERR:
+		return "TSU_VAL_LKEY_ADDR_RANGE_ERR";
+	case TSU_VAL_LKEY_ACCESS_ERR:
+		return "TSU_VAL_LKEY_ACCESS_ERR";
+	case TSU_VAL_LKEY_PD_ERR:
+		return "TSU_VAL_LKEY_PD_ERR";
+	case TSU_VAL_LKEY_RANGE_ERR:
+		return "TSU_VAL_LKEY_RANGE_ERR";
+	case TSU_VAL_TRANSLATION_TYPE_ERR:
+		return "TSU_VAL_TRANSLATION_TYPE_ERR";
+	case TSU_VAL_PCIE_ERR:
+		return "TSU_VAL_PCIE_ERR";
+	case TSU_VAL_ECC_ERR:
+		return "TSU_VAL_ECC_ERR";
+	case TSU_MMU_DUPLICATE_WITH_ERR:
+		return "TSU_MMU_DUPLICATE_WITH_ERR";
+	case TSU_MMU_PTW_ERR:
+		return "TSU_MMU_PTW_ERR";
+	case TSU_MMU_UF_ERR:
+		return "TSU_MMU_UF_ERR";
+	case TSU_MMU_AC_ERR:
+		return "TSU_MMU_AC_ERR";
+	case TSU_MMU_ECC_ERR:
+		return "TSU_MMU_ECC_ERR";
+	case TSU_CBLD_CQ_INVALID_ERR:
+		return "TSU_CBLD_CQ_INVALID_ERR";
+	case TSU_CBLD_CQ_FULL_ERR:
+		return "TSU_CBLD_CQ_FULL_ERR";
+	case TSU_CBLD_CQ_ALREADY_IN_ERR:
+		return "TSU_CBLD_CQ_ALREADY_IN_ERR";
+	case TSU_CBLD_CQ_IS_PROXY_ERR:
+		return "TSU_CBLD_CQ_IS_PROXY_ERR";
+	case TSU_CBLD_TRANSLATION_TYPE_ERR:
+		return "TSU_CBLD_TRANSLATION_TYPE_ERR";
+	case TSU_CBLD_CQ_DESCRIPTOR_INCONSISTENT_ERR:
+		return "TSU_CBLD_CQ_DESCRIPTOR_INCONSISTENT_ERR";
+	case TSU_CBLD_ECC_ERR:
+		return "TSU_CBLD_ECC_ERR";
+	case TSU_CBLD_PCIE_ERR:
+		return "TSU_CBLD_PCIE_ERR";
+	case TSU_CBLD_QP_ERR:
+		return "TSU_CBLD_QP_ERR";
+	case TSU_RQS_CHECKSUM_ERR:
+		return "TSU_RQS_CHECKSUM_ERR";
+	case TSU_RQS_SEQNUM_ERR:
+		return "TSU_RQS_SEQNUM_ERR";
+	case TSU_RQS_INVALID_REQUEST_ERR:
+		return "TSU_RQS_INVALID_REQUEST_ERR";
+	case TSU_RQS_QP_IN_WRONG_STATE_ERR:
+		return "TSU_RQS_QP_IN_WRONG_STATE_ERR";
+	case TSU_RQS_STOP_TIMER_ERR:
+		return "TSU_RQS_STOP_TIMER_ERR";
+	case TSU_RQS_CMD_FROM_EPS_ERR:
+		return "TSU_RQS_CMD_FROM_EPS_ERR";
+	case TSU_RQS_SQ_FLUSH_ERR:
+		return "TSU_RQS_SQ_FLUSH_ERR";
+	case TSU_RQS_SMP_NOT_AUTH_ERR:
+		return "TSU_RQS_SMP_NOT_AUTH_ERR";
+	case TSU_RQS_REQUEST_FENCED_ERR:
+		return "TSU_RQS_REQUEST_FENCED_ERR";
+	case TSU_RQS_MAX_OUTSTANDING_REACHED_ERR:
+		return "TSU_RQS_MAX_OUTSTANDING_REACHED_ERR";
+	case TSU_RQS_ECC_ERR:
+		return "TSU_RQS_ECC_ERR";
+	case TSU_RQS_EOIB_QKEY_VIOLATION:
+		return "TSU_RQS_EOIB_QKEY_VIOLATION";
+	case TSU_RQS_IPOIB_QKEY_VIOLATION:
+		return "TSU_RQS_IPOIB_QKEY_VIOLATION";
+	case TSU_RQS_EOIB_MODE_VIOLATION:
+		return "TSU_RQS_EOIB_MODE_VIOLATION";
+	case TSU_RQS_MISCONFIGURED_QP:
+		return "TSU_RQS_MISCONFIGURED_QP";
+	case TSU_RQS_PORT_AUTH_VIOLATION:
+		return "TSU_RQS_PORT_AUTH_VIOLATION";
+	case TSU_DMA_SGL_RD_ERR:
+		return "TSU_DMA_SGL_RD_ERR";
+	case TSU_DMA_REQ_PYLD_RD_ERR:
+		return "TSU_DMA_REQ_PYLD_RD_ERR";
+	case TSU_DMA_RESP_PYLD_RD_ERR:
+		return "TSU_DMA_RESP_PYLD_RD_ERR";
+	case TSU_DMA_SGL_LENGTH_ERR:
+		return "TSU_DMA_SGL_LENGTH_ERR";
+	case TSU_DMA_LKEY_ERR:
+		return "TSU_DMA_LKEY_ERR";
+	case TSU_DMA_RKEY_ERR:
+		return "TSU_DMA_RKEY_ERR";
+	case TSU_DMA_LSO_PKTLEN_ERR:
+		return "TSU_DMA_LSO_PKTLEN_ERR";
+	case TSU_DMA_LSO_ILLEGAL_CLASSIFICATION_ERR:
+		return "TSU_DMA_LSO_ILLEGAL_CLASSIFICATION_ERR";
+	case TSU_DMA_PCIE_ERR:
+		return "TSU_DMA_PCIE_ERR";
+	case TSU_DMA_ECC_ERR:
+		return "TSU_DMA_ECC_ERR";
+	case TSU_CMPL_PCIE_ERR:
+		return "TSU_CMPL_PCIE_ERR";
+	case TSU_CMPL_ECC_ERR:
+		return "TSU_CMPL_ECC_ERR";
+	case TSU_CMPL_REQUESTER_PSN_ERR:
+		return "TSU_CMPL_REQUESTER_PSN_ERR";
+	case TSU_CMPL_REQUESTER_SYNDROME_ERR:
+		return "TSU_CMPL_REQUESTER_SYNDROME_ERR";
+	case TSU_CMPL_REQUESTER_OUTSTANDING_MATCH_ERR:
+		return "TSU_CMPL_REQUESTER_OUTSTANDING_MATCH_ERR";
+	case TSU_CMPL_REQUESTER_LEN_ERR:
+		return "TSU_CMPL_REQUESTER_LEN_ERR";
+	case TSU_CMPL_REQUESTER_UNEXP_OPCODE_ERR:
+		return "TSU_CMPL_REQUESTER_UNEXP_OPCODE_ERR";
+	case TSU_CMPL_REQUESTER_DUPLICATE:
+		return "TSU_CMPL_REQUESTER_DUPLICATE";
+	case TSU_CMPL_RC_IN_ERROR_ERR:
+		return "TSU_CMPL_RC_IN_ERROR_ERR";
+	case TSU_CMPL_NAK_RNR_ERR:
+		return "TSU_CMPL_NAK_RNR_ERR";
+	case TSU_CMPL_NAK_SEQUENCE_ERR:
+		return "TSU_CMPL_NAK_SEQUENCE_ERR";
+	case TSU_CMPL_NAK_INVALID_REQUEST_ERR:
+		return "TSU_CMPL_NAK_INVALID_REQUEST_ERR";
+	case TSU_CMPL_NAK_REMOTE_ACCESS_ERR:
+		return "TSU_CMPL_NAK_REMOTE_ACCESS_ERR";
+	case TSU_CMPL_NAK_REMOTE_OPS_ERR:
+		return "TSU_CMPL_NAK_REMOTE_OPS_ERR";
+	case TSU_CMPL_NAK_INVALID_RD_REQUEST_ERR:
+		return "TSU_CMPL_NAK_INVALID_RD_REQUEST_ERR";
+	case TSU_CMPL_TIMEOUT_ERR:
+		return "TSU_CMPL_TIMEOUT_ERR";
+	case TSU_CMPL_IMPLIED_NAK:
+		return "TSU_CMPL_IMPLIED_NAK";
+	case TSU_CMPL_GHOST_RESP_ERR:
+		return "TSU_CMPL_GHOST_RESP_ERR";
+	default:
+		return "UNKNOWN_psif_tsu_error_types";
+	}
+}
+
+void write_enum_psif_tsu_error_types(XFILE *fd,
+	enum psif_tsu_error_types data)
+{
+	xprintf(fd, "%s", string_enum_psif_tsu_error_types(data));
+} /* end write_..._psif_tsu_error_types(psif_tsu_error_types data) */
+
+/* Convert enum psif_eps_core_id to string */
+const char *string_enum_psif_eps_core_id(enum psif_eps_core_id val)
+{
+	switch (val) {
+	case PSIF_EVENT_CORE_EPS_A_1:
+		return "PSIF_EVENT_CORE_EPS_A_1";
+	case PSIF_EVENT_CORE_EPS_A_2:
+		return "PSIF_EVENT_CORE_EPS_A_2";
+	case PSIF_EVENT_CORE_EPS_A_3:
+		return "PSIF_EVENT_CORE_EPS_A_3";
+	case PSIF_EVENT_CORE_EPS_A_4:
+		return "PSIF_EVENT_CORE_EPS_A_4";
+	case PSIF_EVENT_CORE_EPS_C:
+		return "PSIF_EVENT_CORE_EPS_C";
+	case PSIF_EPS_CORE_ID_FIELD_MAX:
+		return "PSIF_EPS_CORE_ID_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_eps_core_id";
+	}
+}
+
+void write_enum_psif_eps_core_id(XFILE *fd,
+	enum psif_eps_core_id data)
+{
+	xprintf(fd, "%s", string_enum_psif_eps_core_id(data));
+} /* end write_..._psif_eps_core_id(psif_eps_core_id data) */
+
+/* Convert enum psif_epsc_port_state to string */
+const char *string_enum_psif_epsc_port_state(enum psif_epsc_port_state val)
+{
+	switch (val) {
+	case EPSC_PORT_NOP:
+		return "EPSC_PORT_NOP";
+	case EPSC_PORT_DOWN:
+		return "EPSC_PORT_DOWN";
+	case EPSC_PORT_INIT:
+		return "EPSC_PORT_INIT";
+	case EPSC_PORT_ARMED:
+		return "EPSC_PORT_ARMED";
+	case EPSC_PORT_ACTIVE:
+		return "EPSC_PORT_ACTIVE";
+	case EPSC_PORT_ACTIVE_DEFER:
+		return "EPSC_PORT_ACTIVE_DEFER";
+	case PSIF_EPSC_PORT_STATE_FIELD_MAX:
+		return "PSIF_EPSC_PORT_STATE_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_port_state";
+	}
+}
+
+void write_enum_psif_epsc_port_state(XFILE *fd,
+	enum psif_epsc_port_state data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_port_state(data));
+} /* end write_..._psif_epsc_port_state(psif_epsc_port_state data) */
+
+/* Convert enum psif_epsc_log_mode to string */
+const char *string_enum_psif_epsc_log_mode(enum psif_epsc_log_mode val)
+{
+	switch (val) {
+	case EPSC_LOG_MODE_OFF:
+		return "EPSC_LOG_MODE_OFF";
+	case EPSC_LOG_MODE_SCAT:
+		return "EPSC_LOG_MODE_SCAT";
+	case EPSC_LOG_MODE_MALLOC:
+		return "EPSC_LOG_MODE_MALLOC";
+	case EPSC_LOG_MODE_LOCAL:
+		return "EPSC_LOG_MODE_LOCAL";
+	case EPSC_LOG_MODE_HOST:
+		return "EPSC_LOG_MODE_HOST";
+	case EPSC_LOG_MODE_SAVE:
+		return "EPSC_LOG_MODE_SAVE";
+	case PSIF_EPSC_LOG_MODE_FIELD_MAX:
+		return "PSIF_EPSC_LOG_MODE_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_log_mode";
+	}
+}
+
+void write_enum_psif_epsc_log_mode(XFILE *fd,
+	enum psif_epsc_log_mode data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_log_mode(data));
+} /* end write_..._psif_epsc_log_mode(psif_epsc_log_mode data) */
+
+/* Convert enum psif_epsc_log_level to string */
+const char *string_enum_psif_epsc_log_level(enum psif_epsc_log_level val)
+{
+	switch (val) {
+	case EPS_LOG_OFF:
+		return "EPS_LOG_OFF";
+	case EPS_LOG_FATAL:
+		return "EPS_LOG_FATAL";
+	case EPS_LOG_ERROR:
+		return "EPS_LOG_ERROR";
+	case EPS_LOG_WARN:
+		return "EPS_LOG_WARN";
+	case EPS_LOG_INFO:
+		return "EPS_LOG_INFO";
+	case EPS_LOG_DEBUG:
+		return "EPS_LOG_DEBUG";
+	case EPS_LOG_TRACE:
+		return "EPS_LOG_TRACE";
+	case EPS_LOG_ALL:
+		return "EPS_LOG_ALL";
+	case PSIF_EPSC_LOG_LEVEL_FIELD_MAX:
+		return "PSIF_EPSC_LOG_LEVEL_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_log_level";
+	}
+}
+
+void write_enum_psif_epsc_log_level(XFILE *fd,
+	enum psif_epsc_log_level data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_log_level(data));
+} /* end write_..._psif_epsc_log_level(psif_epsc_log_level data) */
+
+/* Convert enum psif_epsc_interrupt_source to string */
+const char *string_enum_psif_epsc_interrupt_source(enum psif_epsc_interrupt_source val)
+{
+	switch (val) {
+	case EPSC_INTR_LCSR:
+		return "EPSC_INTR_LCSR";
+	case EPSC_INTR_MBOX:
+		return "EPSC_INTR_MBOX";
+	case EPSC_INTR_XIU:
+		return "EPSC_INTR_XIU";
+	case EPSC_INTR_IBU0:
+		return "EPSC_INTR_IBU0";
+	case EPSC_INTR_IBU1:
+		return "EPSC_INTR_IBU1";
+	case EPSC_INTR_TSU_NCSI:
+		return "EPSC_INTR_TSU_NCSI";
+	case EPSC_INTR_TSU_IBPB:
+		return "EPSC_INTR_TSU_IBPB";
+	case EPSC_INTR_TSU_DMA:
+		return "EPSC_INTR_TSU_DMA";
+	case EPSC_INTR_TSU_RQS:
+		return "EPSC_INTR_TSU_RQS";
+	case EPSC_INTR_TSU_QPS:
+		return "EPSC_INTR_TSU_QPS";
+	case EPSC_INTR_TSU_SQS:
+		return "EPSC_INTR_TSU_SQS";
+	case EPSC_INTR_TSU_ERR:
+		return "EPSC_INTR_TSU_ERR";
+	case EPSC_INTR_TSU_CMPL:
+		return "EPSC_INTR_TSU_CMPL";
+	case EPSC_INTR_TSU_VAL:
+		return "EPSC_INTR_TSU_VAL";
+	case EPSC_INTR_TSU_RQH:
+		return "EPSC_INTR_TSU_RQH";
+	case EPSC_INTR_TSU_DSCR:
+		return "EPSC_INTR_TSU_DSCR";
+	case EPSC_INTR_TSU_RCV:
+		return "EPSC_INTR_TSU_RCV";
+	case EPSC_INTR_TSU_IBPR:
+		return "EPSC_INTR_TSU_IBPR";
+	case EPSC_INTR_TSU_CBU:
+		return "EPSC_INTR_TSU_CBU";
+	case EPSC_INTR_TSU_HOST:
+		return "EPSC_INTR_TSU_HOST";
+	case EPSC_INTR_TSU_MMU:
+		return "EPSC_INTR_TSU_MMU";
+	default:
+		return "UNKNOWN_psif_epsc_interrupt_source";
+	}
+}
+
+void write_enum_psif_epsc_interrupt_source(XFILE *fd,
+	enum psif_epsc_interrupt_source data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_interrupt_source(data));
+} /* end write_..._psif_epsc_interrupt_source(psif_epsc_interrupt_source data) */
+
+/* Convert enum psif_epsc_interrupt_pri to string */
+const char *string_enum_psif_epsc_interrupt_pri(enum psif_epsc_interrupt_pri val)
+{
+	switch (val) {
+	case EPSC_INTR_RESERVED:
+		return "EPSC_INTR_RESERVED";
+	case EPSC_INTR_LOW:
+		return "EPSC_INTR_LOW";
+	case EPSC_INTR_HIGH:
+		return "EPSC_INTR_HIGH";
+	case EPSC_INTR_FATAL:
+		return "EPSC_INTR_FATAL";
+	default:
+		return "UNKNOWN_psif_epsc_interrupt_pri";
+	}
+}
+
+void write_enum_psif_epsc_interrupt_pri(XFILE *fd,
+	enum psif_epsc_interrupt_pri data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_interrupt_pri(data));
+} /* end write_..._psif_epsc_interrupt_pri(psif_epsc_interrupt_pri data) */
+
+/* Convert enum psif_epsc_csr_status to string */
+const char *string_enum_psif_epsc_csr_status(enum psif_epsc_csr_status val)
+{
+	switch (val) {
+	case EPSC_SUCCESS:
+		return "EPSC_SUCCESS";
+	case EPSC_EKEYREJECTED:
+		return "EPSC_EKEYREJECTED";
+	case EPSC_EADDRNOTAVAIL:
+		return "EPSC_EADDRNOTAVAIL";
+	case EPSC_EOPNOTSUPP:
+		return "EPSC_EOPNOTSUPP";
+	case EPSC_ENOMEM:
+		return "EPSC_ENOMEM";
+	case EPSC_ENODATA:
+		return "EPSC_ENODATA";
+	case EPSC_EAGAIN:
+		return "EPSC_EAGAIN";
+	case EPSC_ECANCELED:
+		return "EPSC_ECANCELED";
+	case EPSC_ECONNRESET:
+		return "EPSC_ECONNRESET";
+	case EPSC_ECSR:
+		return "EPSC_ECSR";
+	case EPSC_MODIFY_QP_OUT_OF_RANGE:
+		return "EPSC_MODIFY_QP_OUT_OF_RANGE";
+	case EPSC_MODIFY_QP_INVALID:
+		return "EPSC_MODIFY_QP_INVALID";
+	case EPSC_MODIFY_CANNOT_CHANGE_QP_ATTR:
+		return "EPSC_MODIFY_CANNOT_CHANGE_QP_ATTR";
+	case EPSC_MODIFY_INVALID_QP_STATE:
+		return "EPSC_MODIFY_INVALID_QP_STATE";
+	case EPSC_MODIFY_INVALID_MIG_STATE:
+		return "EPSC_MODIFY_INVALID_MIG_STATE";
+	case EPSC_MODIFY_TIMEOUT:
+		return "EPSC_MODIFY_TIMEOUT";
+	case EPSC_ETEST_HEAD:
+		return "EPSC_ETEST_HEAD";
+	case EPSC_ETEST_TAIL:
+		return "EPSC_ETEST_TAIL";
+	case EPSC_ETEST_PATTERN:
+		return "EPSC_ETEST_PATTERN";
+	case EPSC_EADDRINUSE:
+		return "EPSC_EADDRINUSE";
+	case EPSC_EINVALID_VHCA:
+		return "EPSC_EINVALID_VHCA";
+	case EPSC_EINVALID_PORT:
+		return "EPSC_EINVALID_PORT";
+	case EPSC_EINVALID_ADDRESS:
+		return "EPSC_EINVALID_ADDRESS";
+	case EPSC_EINVALID_PARAMETER:
+		return "EPSC_EINVALID_PARAMETER";
+	case EPSC_FAIL:
+		return "EPSC_FAIL";
+	default:
+		return "UNKNOWN_psif_epsc_csr_status";
+	}
+}
+
+void write_enum_psif_epsc_csr_status(XFILE *fd,
+	enum psif_epsc_csr_status data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_csr_status(data));
+} /* end write_..._psif_epsc_csr_status(psif_epsc_csr_status data) */
+
+/* Convert enum psif_epsc_csr_opcode to string */
+const char *string_enum_psif_epsc_csr_opcode(enum psif_epsc_csr_opcode val)
+{
+	switch (val) {
+	case EPSC_NOOP:
+		return "EPSC_NOOP";
+	case EPSC_MAILBOX_PING:
+		return "EPSC_MAILBOX_PING";
+	case EPSC_KEEP_ALIVE:
+		return "EPSC_KEEP_ALIVE";
+	case EPSC_SETUP:
+		return "EPSC_SETUP";
+	case EPSC_TEARDOWN:
+		return "EPSC_TEARDOWN";
+	case EPSC_SET:
+		return "EPSC_SET";
+	case EPSC_SET_SINGLE:
+		return "EPSC_SET_SINGLE";
+	case EPSC_SET_ONE_CSR:
+		return "EPSC_SET_ONE_CSR";
+	case EPSC_SETUP_BASEADDR:
+		return "EPSC_SETUP_BASEADDR";
+	case EPSC_SET_BASEADDR:
+		return "EPSC_SET_BASEADDR";
+	case EPSC_SET_BASEADDR_EQ:
+		return "EPSC_SET_BASEADDR_EQ";
+	case EPSC_SET_LID:
+		return "EPSC_SET_LID";
+	case OBSOLETE_1:
+		return "OBSOLETE_1";
+	case OBSOLETE_2:
+		return "OBSOLETE_2";
+	case EPSC_SET_GID:
+		return "EPSC_SET_GID";
+	case EPSC_SET_EOIB_MAC:
+		return "EPSC_SET_EOIB_MAC";
+	case EPSC_SET_VLINK_STATE:
+		return "EPSC_SET_VLINK_STATE";
+	case EPSC_QUERY_VLINK_STATE:
+		return "EPSC_QUERY_VLINK_STATE";
+	case EPSC_UF_RESET:
+		return "EPSC_UF_RESET";
+	case EPSC_MODIFY_QP:
+		return "EPSC_MODIFY_QP";
+	case EPSC_GET_SINGLE:
+		return "EPSC_GET_SINGLE";
+	case EPSC_GET_ONE_CSR:
+		return "EPSC_GET_ONE_CSR";
+	case EPSC_QUERY_QP:
+		return "EPSC_QUERY_QP";
+	case EPSC_QUERY_HW_RQ:
+		return "EPSC_QUERY_HW_RQ";
+	case EPSC_QUERY_HW_SQ:
+		return "EPSC_QUERY_HW_SQ";
+	case EPSC_QUERY_DEVICE:
+		return "EPSC_QUERY_DEVICE";
+	case EPSC_QUERY_PORT_1:
+		return "EPSC_QUERY_PORT_1";
+	case EPSC_QUERY_PORT_2:
+		return "EPSC_QUERY_PORT_2";
+	case EPSC_QUERY_PKEY:
+		return "EPSC_QUERY_PKEY";
+	case EPSC_QUERY_GID:
+		return "EPSC_QUERY_GID";
+	case EPSC_MODIFY_DEVICE:
+		return "EPSC_MODIFY_DEVICE";
+	case EPSC_MODIFY_PORT_1:
+		return "EPSC_MODIFY_PORT_1";
+	case EPSC_MODIFY_PORT_2:
+		return "EPSC_MODIFY_PORT_2";
+	case EPSC_MC_ATTACH:
+		return "EPSC_MC_ATTACH";
+	case EPSC_MC_DETACH:
+		return "EPSC_MC_DETACH";
+	case EPSC_MC_QUERY:
+		return "EPSC_MC_QUERY";
+	case EPSC_EVENT_ACK:
+		return "EPSC_EVENT_ACK";
+	case EPSC_EVENT_INDEX:
+		return "EPSC_EVENT_INDEX";
+	case EPSC_FLASH_START:
+		return "EPSC_FLASH_START";
+	case EPSC_FLASH_INFO:
+		return "EPSC_FLASH_INFO";
+	case EPSC_FLASH_ERASE_SECTOR:
+		return "EPSC_FLASH_ERASE_SECTOR";
+	case EPSC_FLASH_RD:
+		return "EPSC_FLASH_RD";
+	case EPSC_FLASH_WR:
+		return "EPSC_FLASH_WR";
+	case EPSC_FLASH_CHECK:
+		return "EPSC_FLASH_CHECK";
+	case EPSC_FLASH_SCAN:
+		return "EPSC_FLASH_SCAN";
+	case EPSC_FLASH_STOP:
+		return "EPSC_FLASH_STOP";
+	case EPSC_UPDATE:
+		return "EPSC_UPDATE";
+	case EPSC_TRACE_STATUS:
+		return "EPSC_TRACE_STATUS";
+	case EPSC_TRACE_SETUP:
+		return "EPSC_TRACE_SETUP";
+	case EPSC_TRACE_START:
+		return "EPSC_TRACE_START";
+	case EPSC_TRACE_STOP:
+		return "EPSC_TRACE_STOP";
+	case EPSC_TRACE_ACQUIRE:
+		return "EPSC_TRACE_ACQUIRE";
+	case EPSC_TEST_HOST_RD:
+		return "EPSC_TEST_HOST_RD";
+	case EPSC_TEST_HOST_WR:
+		return "EPSC_TEST_HOST_WR";
+	case EPSC_FW_VERSION:
+		return "EPSC_FW_VERSION";
+	case EPSC_LOG_CTRL:
+		return "EPSC_LOG_CTRL";
+	case EPSC_LOG_REQ_NOTIFY:
+		return "EPSC_LOG_REQ_NOTIFY";
+	case EPSC_LINK_CNTRL:
+		return "EPSC_LINK_CNTRL";
+	case EPSC_A_CONTROL:
+		return "EPSC_A_CONTROL";
+	case EPSC_A_COMMAND:
+		return "EPSC_A_COMMAND";
+	case EPSC_EXERCISE_MMU:
+		return "EPSC_EXERCISE_MMU";
+	case EPSC_CLI_ACCESS:
+		return "EPSC_CLI_ACCESS";
+	case EPSC_MAD_PROCESS:
+		return "EPSC_MAD_PROCESS";
+	case EPSC_MAD_SEND_WR:
+		return "EPSC_MAD_SEND_WR";
+	case EPSC_QUERY:
+		return "EPSC_QUERY";
+	case EPSC_HOST_INT_COMMON_CTRL:
+		return "EPSC_HOST_INT_COMMON_CTRL";
+	case EPSC_HOST_INT_CHANNEL_CTRL:
+		return "EPSC_HOST_INT_CHANNEL_CTRL";
+	case EPSC_UF_CTRL:
+		return "EPSC_UF_CTRL";
+	case EPSC_FLUSH_CACHES:
+		return "EPSC_FLUSH_CACHES";
+	case EPSC_PMA_COUNTERS:
+		return "EPSC_PMA_COUNTERS";
+	case EPSC_VIMMA_CTRL:
+		return "EPSC_VIMMA_CTRL";
+	case EPSC_BER_DATA:
+		return "EPSC_BER_DATA";
+	case EPSC_LAST_OP:
+		return "EPSC_LAST_OP";
+	case PSIF_EPSC_CSR_OPCODE_FIELD_MAX:
+		return "PSIF_EPSC_CSR_OPCODE_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_csr_opcode";
+	}
+}
+
+void write_enum_psif_epsc_csr_opcode(XFILE *fd,
+	enum psif_epsc_csr_opcode data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_csr_opcode(data));
+} /* end write_..._psif_epsc_csr_opcode(psif_epsc_csr_opcode data) */
+
+/* Convert enum psif_epsc_csr_flags to string */
+const char *string_enum_psif_epsc_csr_flags(enum psif_epsc_csr_flags val)
+{
+	switch (val) {
+	case EPSC_FL_NONE:
+		return "EPSC_FL_NONE";
+	case EPSC_FL_NOTIFY:
+		return "EPSC_FL_NOTIFY";
+	case EPSC_FL_PQP:
+		return "EPSC_FL_PQP";
+	case EPSC_FL_IGNORE_ERROR:
+		return "EPSC_FL_IGNORE_ERROR";
+	case PSIF_EPSC_CSR_FLAGS_FIELD_MAX:
+		return "PSIF_EPSC_CSR_FLAGS_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_csr_flags";
+	}
+}
+
+void write_enum_psif_epsc_csr_flags(XFILE *fd,
+	enum psif_epsc_csr_flags data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_csr_flags(data));
+} /* end write_..._psif_epsc_csr_flags(psif_epsc_csr_flags data) */
+
+/* Convert enum psif_vlink_state to string */
+const char *string_enum_psif_vlink_state(enum psif_vlink_state val)
+{
+	switch (val) {
+	case PSIF_LINK_DISABLED:
+		return "PSIF_LINK_DISABLED";
+	case PSIF_LINK_DOWN:
+		return "PSIF_LINK_DOWN";
+	case PSIF_LINK_INIT:
+		return "PSIF_LINK_INIT";
+	case PSIF_LINK_ARM:
+		return "PSIF_LINK_ARM";
+	case PSIF_LINK_ACTIVE:
+		return "PSIF_LINK_ACTIVE";
+	default:
+		return "UNKNOWN_psif_vlink_state";
+	}
+}
+
+void write_enum_psif_vlink_state(XFILE *fd,
+	enum psif_vlink_state data)
+{
+	xprintf(fd, "%s", string_enum_psif_vlink_state(data));
+} /* end write_..._psif_vlink_state(psif_vlink_state data) */
+
+/* Convert enum psif_epsc_csr_modify_device_flags to string */
+const char *string_enum_psif_epsc_csr_modify_device_flags(enum psif_epsc_csr_modify_device_flags val)
+{
+	switch (val) {
+	case PSIF_DEVICE_MODIFY_SYS_IMAGE_GUID:
+		return "PSIF_DEVICE_MODIFY_SYS_IMAGE_GUID";
+	case PSIF_DEVICE_MODIFY_NODE_DESC:
+		return "PSIF_DEVICE_MODIFY_NODE_DESC";
+	case PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_FIELD_MAX:
+		return "PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_csr_modify_device_flags";
+	}
+}
+
+void write_enum_psif_epsc_csr_modify_device_flags(XFILE *fd,
+	enum psif_epsc_csr_modify_device_flags data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_csr_modify_device_flags(data));
+} /* end write_..._psif_epsc_csr_modify_device_flags(psif_epsc_csr_modify_device_flags data) */
+
+/* Convert enum psif_epsc_csr_modify_port_flags to string */
+const char *string_enum_psif_epsc_csr_modify_port_flags(enum psif_epsc_csr_modify_port_flags val)
+{
+	switch (val) {
+	case PSIF_PORT_SHUTDOWN:
+		return "PSIF_PORT_SHUTDOWN";
+	case PSIF_PORT_INIT_TYPE:
+		return "PSIF_PORT_INIT_TYPE";
+	case PSIF_PORT_RESET_QKEY_CNTR:
+		return "PSIF_PORT_RESET_QKEY_CNTR";
+	case PSIF_PORT_RESET_PKEY_CNTR:
+		return "PSIF_PORT_RESET_PKEY_CNTR";
+	case PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_FIELD_MAX:
+		return "PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_csr_modify_port_flags";
+	}
+}
+
+void write_enum_psif_epsc_csr_modify_port_flags(XFILE *fd,
+	enum psif_epsc_csr_modify_port_flags data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_csr_modify_port_flags(data));
+} /* end write_..._psif_epsc_csr_modify_port_flags(psif_epsc_csr_modify_port_flags data) */
+
+/* Convert enum psif_epsc_csr_epsa_command to string */
+const char *string_enum_psif_epsc_csr_epsa_command(enum psif_epsc_csr_epsa_command val)
+{
+	switch (val) {
+	case EPSC_A_LOAD:
+		return "EPSC_A_LOAD";
+	case EPSC_A_START:
+		return "EPSC_A_START";
+	case EPSC_A_STOP:
+		return "EPSC_A_STOP";
+	case EPSC_A_STATUS:
+		return "EPSC_A_STATUS";
+	case PSIF_EPSC_CSR_EPSA_COMMAND_FIELD_MAX:
+		return "PSIF_EPSC_CSR_EPSA_COMMAND_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_csr_epsa_command";
+	}
+}
+
+void write_enum_psif_epsc_csr_epsa_command(XFILE *fd,
+	enum psif_epsc_csr_epsa_command data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_csr_epsa_command(data));
+} /* end write_..._psif_epsc_csr_epsa_command(psif_epsc_csr_epsa_command data) */
+
+/* Convert enum psif_epsa_command to string */
+const char *string_enum_psif_epsa_command(enum psif_epsa_command val)
+{
+	switch (val) {
+	case EPSA_DYNAMIC_LOAD:
+		return "EPSA_DYNAMIC_LOAD";
+	case EPSA_TEST_FABOUT:
+		return "EPSA_TEST_FABOUT";
+	case EPSA_TEST_FABIN:
+		return "EPSA_TEST_FABIN";
+	case EPSA_TEST_FABIN_FABOUT:
+		return "EPSA_TEST_FABIN_FABOUT";
+	case EPSA_TEST_SKJM_MEMREAD:
+		return "EPSA_TEST_SKJM_MEMREAD";
+	case EPSA_TEST_SKJM_MEMWRITE:
+		return "EPSA_TEST_SKJM_MEMWRITE";
+	case EPSA_TEST_SKJM_MEMLOCK:
+		return "EPSA_TEST_SKJM_MEMLOCK";
+	case EPSA_SKJM_LOAD:
+		return "EPSA_SKJM_LOAD";
+	case EPSA_SKJM_ACC:
+		return "EPSA_SKJM_ACC";
+	case EPSA_SKJM_MEMACC:
+		return "EPSA_SKJM_MEMACC";
+	case EPSA_GET_PROXY_QP_SQ_KEY:
+		return "EPSA_GET_PROXY_QP_SQ_KEY";
+	case EPSA_GENERIC_CMD:
+		return "EPSA_GENERIC_CMD";
+	case PSIF_EPSA_COMMAND_FIELD_MAX:
+		return "PSIF_EPSA_COMMAND_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsa_command";
+	}
+}
+
+void write_enum_psif_epsa_command(XFILE *fd,
+	enum psif_epsa_command data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsa_command(data));
+} /* end write_..._psif_epsa_command(psif_epsa_command data) */
+
+/* Convert enum psif_epsc_query_op to string */
+const char *string_enum_psif_epsc_query_op(enum psif_epsc_query_op val)
+{
+	switch (val) {
+	case EPSC_QUERY_BLANK:
+		return "EPSC_QUERY_BLANK";
+	case EPSC_QUERY_CAP_VCB:
+		return "EPSC_QUERY_CAP_VCB";
+	case EPSC_QUERY_CAP_PCB:
+		return "EPSC_QUERY_CAP_PCB";
+	case EPSC_QUERY_NUM_UF:
+		return "EPSC_QUERY_NUM_UF";
+	case EPSC_QUERY_GID_HI:
+		return "EPSC_QUERY_GID_HI";
+	case EPSC_QUERY_GID_LO:
+		return "EPSC_QUERY_GID_LO";
+	case EPSC_QUERY_P_KEY:
+		return "EPSC_QUERY_P_KEY";
+	case EPSC_QUERY_Q_KEY:
+		return "EPSC_QUERY_Q_KEY";
+	case EPSC_QUERY_UF:
+		return "EPSC_QUERY_UF";
+	case EPSC_QUERY_LINK_STATE:
+		return "EPSC_QUERY_LINK_STATE";
+	case EPSC_QUERY_VHCA_STATE:
+		return "EPSC_QUERY_VHCA_STATE";
+	case EPSC_QUERY_INT_COMMON:
+		return "EPSC_QUERY_INT_COMMON";
+	case EPSC_QUERY_INT_CHAN_RATE:
+		return "EPSC_QUERY_INT_CHAN_RATE";
+	case EPSC_QUERY_INT_CHAN_AUSEC:
+		return "EPSC_QUERY_INT_CHAN_AUSEC";
+	case EPSC_QUERY_INT_CHAN_PUSEC:
+		return "EPSC_QUERY_INT_CHAN_PUSEC";
+	case EPSC_QUERY_CAP_VCB_LO:
+		return "EPSC_QUERY_CAP_VCB_LO";
+	case EPSC_QUERY_CAP_VCB_HI:
+		return "EPSC_QUERY_CAP_VCB_HI";
+	case EPSC_QUERY_CAP_PCB_LO:
+		return "EPSC_QUERY_CAP_PCB_LO";
+	case EPSC_QUERY_CAP_PCB_HI:
+		return "EPSC_QUERY_CAP_PCB_HI";
+	case EPSC_QUERY_PMA_REDIRECT_QP:
+		return "EPSC_QUERY_PMA_REDIRECT_QP";
+	case EPSC_QUERY_FW_UPTIME:
+		return "EPSC_QUERY_FW_UPTIME";
+	case EPSC_QUERY_FW_PROG_DATE:
+		return "EPSC_QUERY_FW_PROG_DATE";
+	case EPSC_QUERY_FW_BUILD_DATE:
+		return "EPSC_QUERY_FW_BUILD_DATE";
+	case EPSC_QUERY_FW_CURR_IMG:
+		return "EPSC_QUERY_FW_CURR_IMG";
+	case EPSC_QUERY_FW_ONESHOT_IMG:
+		return "EPSC_QUERY_FW_ONESHOT_IMG";
+	case EPSC_QUERY_FW_AUTOSTART_IMG:
+		return "EPSC_QUERY_FW_AUTOSTART_IMG";
+	case EPSC_QUERY_FW_START_CAUSE:
+		return "EPSC_QUERY_FW_START_CAUSE";
+	case EPSC_QUERY_FW_VERSION:
+		return "EPSC_QUERY_FW_VERSION";
+	case EPSC_QUERY_SQ_NUM_BRE:
+		return "EPSC_QUERY_SQ_NUM_BRE";
+	case EPSC_QUERY_NUM_CQOVF:
+		return "EPSC_QUERY_NUM_CQOVF";
+	case EPSC_QUERY_SQ_NUM_WRFE:
+		return "EPSC_QUERY_SQ_NUM_WRFE";
+	case EPSC_QUERY_RQ_NUM_WRFE:
+		return "EPSC_QUERY_RQ_NUM_WRFE";
+	case EPSC_QUERY_RQ_NUM_LAE:
+		return "EPSC_QUERY_RQ_NUM_LAE";
+	case EPSC_QUERY_RQ_NUM_LPE:
+		return "EPSC_QUERY_RQ_NUM_LPE";
+	case EPSC_QUERY_SQ_NUM_LLE:
+		return "EPSC_QUERY_SQ_NUM_LLE";
+	case EPSC_QUERY_RQ_NUM_LLE:
+		return "EPSC_QUERY_RQ_NUM_LLE";
+	case EPSC_QUERY_SQ_NUM_LQPOE:
+		return "EPSC_QUERY_SQ_NUM_LQPOE";
+	case EPSC_QUERY_RQ_NUM_LQPOE:
+		return "EPSC_QUERY_RQ_NUM_LQPOE";
+	case EPSC_QUERY_SQ_NUM_OOS:
+		return "EPSC_QUERY_SQ_NUM_OOS";
+	case EPSC_QUERY_RQ_NUM_OOS:
+		return "EPSC_QUERY_RQ_NUM_OOS";
+	case EPSC_QUERY_SQ_NUM_RREE:
+		return "EPSC_QUERY_SQ_NUM_RREE";
+	case EPSC_QUERY_SQ_NUM_TREE:
+		return "EPSC_QUERY_SQ_NUM_TREE";
+	case EPSC_QUERY_SQ_NUM_ROE:
+		return "EPSC_QUERY_SQ_NUM_ROE";
+	case EPSC_QUERY_RQ_NUM_ROE:
+		return "EPSC_QUERY_RQ_NUM_ROE";
+	case EPSC_QUERY_SQ_NUM_RAE:
+		return "EPSC_QUERY_SQ_NUM_RAE";
+	case EPSC_QUERY_RQ_NUM_RAE:
+		return "EPSC_QUERY_RQ_NUM_RAE";
+	case EPSC_QUERY_RQ_NUM_UDSDPRD:
+		return "EPSC_QUERY_RQ_NUM_UDSDPRD";
+	case EPSC_QUERY_RQ_NUM_UCSDPRD:
+		return "EPSC_QUERY_RQ_NUM_UCSDPRD";
+	case EPSC_QUERY_SQ_NUM_RIRE:
+		return "EPSC_QUERY_SQ_NUM_RIRE";
+	case EPSC_QUERY_RQ_NUM_RIRE:
+		return "EPSC_QUERY_RQ_NUM_RIRE";
+	case EPSC_QUERY_SQ_NUM_RNR:
+		return "EPSC_QUERY_SQ_NUM_RNR";
+	case EPSC_QUERY_RQ_NUM_RNR:
+		return "EPSC_QUERY_RQ_NUM_RNR";
+	case EPSC_QUERY_FW_TWOSHOT_IMG:
+		return "EPSC_QUERY_FW_TWOSHOT_IMG";
+	case EPSC_QUERY_FW_TYPE:
+		return "EPSC_QUERY_FW_TYPE";
+	case EPSC_QUERY_FW_SIZE:
+		return "EPSC_QUERY_FW_SIZE";
+	case EPSC_QUERY_FW_SLOT_SIZE:
+		return "EPSC_QUERY_FW_SLOT_SIZE";
+	case EPSC_QUERY_BL_VERSION:
+		return "EPSC_QUERY_BL_VERSION";
+	case EPSC_QUERY_BL_BUILD_DATE:
+		return "EPSC_QUERY_BL_BUILD_DATE";
+	case EPSC_QUERY_CLEAN_CQ_ID:
+		return "EPSC_QUERY_CLEAN_CQ_ID";
+	case EPSC_QUERY_CAP_TSL_TX:
+		return "EPSC_QUERY_CAP_TSL_TX";
+	case EPSC_QUERY_CAP_TSL_RX:
+		return "EPSC_QUERY_CAP_TSL_RX";
+	case EPSC_QUERY_RESET_CBLD_DIAG_COUNTERS:
+		return "EPSC_QUERY_RESET_CBLD_DIAG_COUNTERS";
+	case EPSC_QUERY_MAX_QP_USED:
+		return "EPSC_QUERY_MAX_QP_USED";
+	case EPSC_QUERY_MODQP_TO_SOURCE:
+		return "EPSC_QUERY_MODQP_TO_SOURCE";
+	case EPSC_QUERY_MODQP_TO_DEBUG:
+		return "EPSC_QUERY_MODQP_TO_DEBUG";
+	case EPSC_QUERY_DEGRADED_CAUSE:
+		return "EPSC_QUERY_DEGRADED_CAUSE";
+	case EPSC_QUERY_SPIN_SET_CONTROL:
+		return "EPSC_QUERY_SPIN_SET_CONTROL";
+	case EPSC_QUERY_VPD_MAC:
+		return "EPSC_QUERY_VPD_MAC";
+	case EPSC_QUERY_VPD_PART_NUMBER:
+		return "EPSC_QUERY_VPD_PART_NUMBER";
+	case EPSC_QUERY_VPD_REVISION:
+		return "EPSC_QUERY_VPD_REVISION";
+	case EPSC_QUERY_VPD_SERIAL_NUMBER:
+		return "EPSC_QUERY_VPD_SERIAL_NUMBER";
+	case EPSC_QUERY_VPD_MANUFACTURER:
+		return "EPSC_QUERY_VPD_MANUFACTURER";
+	case EPSC_QUERY_VPD_PRODUCT_NAME:
+		return "EPSC_QUERY_VPD_PRODUCT_NAME";
+	case EPSC_QUERY_VPD_BASE_GUID:
+		return "EPSC_QUERY_VPD_BASE_GUID";
+	case EPSC_QUERY_MAP_QP0_TO_TSL:
+		return "EPSC_QUERY_MAP_QP0_TO_TSL";
+	case EPSC_QUERY_MAP_PQP_TO_TSL:
+		return "EPSC_QUERY_MAP_PQP_TO_TSL";
+	case EPSC_QUERY_MAP_SL_TO_TSL_LO:
+		return "EPSC_QUERY_MAP_SL_TO_TSL_LO";
+	case EPSC_QUERY_MAP_SL_TO_TSL_HI:
+		return "EPSC_QUERY_MAP_SL_TO_TSL_HI";
+	case EPSC_QUERY_TA_UPPER_TWELVE:
+		return "EPSC_QUERY_TA_UPPER_TWELVE";
+	case EPSC_QUERY_PA_UPPER_TWELVE:
+		return "EPSC_QUERY_PA_UPPER_TWELVE";
+	case EPSC_QUERY_NUM_VFS:
+		return "EPSC_QUERY_NUM_VFS";
+	case EPSC_QUERY_CREDIT_MODE:
+		return "EPSC_QUERY_CREDIT_MODE";
+	case EPSC_QUERY_CPLD_VERSION:
+		return "EPSC_QUERY_CPLD_VERSION";
+	case EPSC_QUERY_EXTERNAL_PORT_INFO:
+		return "EPSC_QUERY_EXTERNAL_PORT_INFO";
+	case EPSC_QUERY_LAST:
+		return "EPSC_QUERY_LAST";
+	case PSIF_EPSC_QUERY_OP_FIELD_MAX:
+		return "PSIF_EPSC_QUERY_OP_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_query_op";
+	}
+}
+
+void write_enum_psif_epsc_query_op(XFILE *fd,
+	enum psif_epsc_query_op data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_query_op(data));
+} /* end write_..._psif_epsc_query_op(psif_epsc_query_op data) */
+
+/* Convert enum psif_epsc_csr_update_opcode to string */
+const char *string_enum_psif_epsc_csr_update_opcode(enum psif_epsc_csr_update_opcode val)
+{
+	switch (val) {
+	case EPSC_UPDATE_OP_POLL:
+		return "EPSC_UPDATE_OP_POLL";
+	case EPSC_UPDATE_OP_START:
+		return "EPSC_UPDATE_OP_START";
+	case EPSC_UPDATE_OP_ERASE:
+		return "EPSC_UPDATE_OP_ERASE";
+	case EPSC_UPDATE_OP_WRITE:
+		return "EPSC_UPDATE_OP_WRITE";
+	case EPSC_UPDATE_OP_READ:
+		return "EPSC_UPDATE_OP_READ";
+	case EPSC_UPDATE_OP_STOP:
+		return "EPSC_UPDATE_OP_STOP";
+	case EPSC_UPDATE_OP_SET:
+		return "EPSC_UPDATE_OP_SET";
+	case EPSC_UPDATE_OP_MAX:
+		return "EPSC_UPDATE_OP_MAX";
+	case PSIF_EPSC_CSR_UPDATE_OPCODE_FIELD_MAX:
+		return "PSIF_EPSC_CSR_UPDATE_OPCODE_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_csr_update_opcode";
+	}
+}
+
+void write_enum_psif_epsc_csr_update_opcode(XFILE *fd,
+	enum psif_epsc_csr_update_opcode data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_csr_update_opcode(data));
+} /* end write_..._psif_epsc_csr_update_opcode(psif_epsc_csr_update_opcode data) */
+
+/* Convert enum psif_epsc_flash_slot to string */
+const char *string_enum_psif_epsc_flash_slot(enum psif_epsc_flash_slot val)
+{
+	switch (val) {
+	case EPSC_FLASH_SLOT_INVALID:
+		return "EPSC_FLASH_SLOT_INVALID";
+	case EPSC_FLASH_SLOT_EPS_C_IMG_1:
+		return "EPSC_FLASH_SLOT_EPS_C_IMG_1";
+	case EPSC_FLASH_SLOT_EPS_C_IMG_2:
+		return "EPSC_FLASH_SLOT_EPS_C_IMG_2";
+	case EPSC_FLASH_SLOT_EPS_A_IMG:
+		return "EPSC_FLASH_SLOT_EPS_A_IMG";
+	case EPSC_FLASH_SLOT_BOOT_IMG:
+		return "EPSC_FLASH_SLOT_BOOT_IMG";
+	case EPSC_FLASH_SLOT_COUNT:
+		return "EPSC_FLASH_SLOT_COUNT";
+	case PSIF_EPSC_FLASH_SLOT_FIELD_MAX:
+		return "PSIF_EPSC_FLASH_SLOT_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_flash_slot";
+	}
+}
+
+void write_enum_psif_epsc_flash_slot(XFILE *fd,
+	enum psif_epsc_flash_slot data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_flash_slot(data));
+} /* end write_..._psif_epsc_flash_slot(psif_epsc_flash_slot data) */
+
+/* Convert enum psif_epsc_update_set to string */
+const char *string_enum_psif_epsc_update_set(enum psif_epsc_update_set val)
+{
+	switch (val) {
+	case EPSC_UPDATE_SET_INVALID:
+		return "EPSC_UPDATE_SET_INVALID";
+	case EPSC_UPDATE_SET_AUTOSTART_IMG:
+		return "EPSC_UPDATE_SET_AUTOSTART_IMG";
+	case EPSC_UPDATE_SET_ONESHOT_IMG:
+		return "EPSC_UPDATE_SET_ONESHOT_IMG";
+	case EPSC_UPDATE_SET_TWOSHOT_IMG:
+		return "EPSC_UPDATE_SET_TWOSHOT_IMG";
+	case EPSC_UPDATE_SET_IMG_VALID:
+		return "EPSC_UPDATE_SET_IMG_VALID";
+	case PSIF_EPSC_UPDATE_SET_FIELD_MAX:
+		return "PSIF_EPSC_UPDATE_SET_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_update_set";
+	}
+}
+
+void write_enum_psif_epsc_update_set(XFILE *fd,
+	enum psif_epsc_update_set data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_update_set(data));
+} /* end write_..._psif_epsc_update_set(psif_epsc_update_set data) */
+
+/* Convert enum psif_epsc_csr_uf_ctrl_opcode to string */
+const char *string_enum_psif_epsc_csr_uf_ctrl_opcode(enum psif_epsc_csr_uf_ctrl_opcode val)
+{
+	switch (val) {
+	case EPSC_UF_CTRL_MMU_FLUSH:
+		return "EPSC_UF_CTRL_MMU_FLUSH";
+	case EPSC_UF_CTRL_GET_UF_USED_QP:
+		return "EPSC_UF_CTRL_GET_UF_USED_QP";
+	case EPSC_UF_CTRL_CLEAR_UF_USED_QP:
+		return "EPSC_UF_CTRL_CLEAR_UF_USED_QP";
+	case EPSC_UF_CTRL_SMP_ENABLE:
+		return "EPSC_UF_CTRL_SMP_ENABLE";
+	case EPSC_UF_CTRL_SMP_DISABLE:
+		return "EPSC_UF_CTRL_SMP_DISABLE";
+	case EPSC_UF_CTRL_VLINK_CONNECT:
+		return "EPSC_UF_CTRL_VLINK_CONNECT";
+	case EPSC_UF_CTRL_VLINK_DISCONNECT:
+		return "EPSC_UF_CTRL_VLINK_DISCONNECT";
+	case EPSC_UF_CTRL_GET_HIGHEST_QP_IDX:
+		return "EPSC_UF_CTRL_GET_HIGHEST_QP_IDX";
+	case EPSC_UF_CTRL_RESET_HIGHEST_QP_IDX:
+		return "EPSC_UF_CTRL_RESET_HIGHEST_QP_IDX";
+	case PSIF_EPSC_CSR_UF_CTRL_OPCODE_FIELD_MAX:
+		return "PSIF_EPSC_CSR_UF_CTRL_OPCODE_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_csr_uf_ctrl_opcode";
+	}
+}
+
+void write_enum_psif_epsc_csr_uf_ctrl_opcode(XFILE *fd,
+	enum psif_epsc_csr_uf_ctrl_opcode data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_csr_uf_ctrl_opcode(data));
+} /* end write_..._psif_epsc_csr_uf_ctrl_opcode(psif_epsc_csr_uf_ctrl_opcode data) */
+
+/* Convert enum psif_epsc_vimma_ctrl_opcode to string */
+const char *string_enum_psif_epsc_vimma_ctrl_opcode(enum psif_epsc_vimma_ctrl_opcode val)
+{
+	switch (val) {
+	case EPSC_VIMMA_CTRL_GET_VER_AND_COMPAT:
+		return "EPSC_VIMMA_CTRL_GET_VER_AND_COMPAT";
+	case EPSC_VIMMA_CTRL_GET_MISC_INFO:
+		return "EPSC_VIMMA_CTRL_GET_MISC_INFO";
+	case EPSC_VIMMA_CTRL_GET_GUIDS:
+		return "EPSC_VIMMA_CTRL_GET_GUIDS";
+	case EPSC_VIMMA_CTRL_GET_REG_INFO:
+		return "EPSC_VIMMA_CTRL_GET_REG_INFO";
+	case EPSC_VIMMA_CTRL_GET_VHCA_STATS:
+		return "EPSC_VIMMA_CTRL_GET_VHCA_STATS";
+	case EPSC_VIMMA_CTRL_SET_VFP_VHCA_REGISTER:
+		return "EPSC_VIMMA_CTRL_SET_VFP_VHCA_REGISTER";
+	case EPSC_VIMMA_CTRL_SET_VFP_VHCA_DEREGISTER:
+		return "EPSC_VIMMA_CTRL_SET_VFP_VHCA_DEREGISTER";
+	case EPSC_VIMMA_CTRL_SET_ADMIN_MODE:
+		return "EPSC_VIMMA_CTRL_SET_ADMIN_MODE";
+	case PSIF_EPSC_VIMMA_CTRL_OPCODE_FIELD_MAX:
+		return "PSIF_EPSC_VIMMA_CTRL_OPCODE_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_vimma_ctrl_opcode";
+	}
+}
+
+void write_enum_psif_epsc_vimma_ctrl_opcode(XFILE *fd,
+	enum psif_epsc_vimma_ctrl_opcode data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_vimma_ctrl_opcode(data));
+} /* end write_..._psif_epsc_vimma_ctrl_opcode(psif_epsc_vimma_ctrl_opcode data) */
+
+/* Convert enum psif_epsc_vimma_admmode to string */
+const char *string_enum_psif_epsc_vimma_admmode(enum psif_epsc_vimma_admmode val)
+{
+	switch (val) {
+	case EPSC_VIMMA_CTRL_IB_ADM_MODE_SM_STANDARD:
+		return "EPSC_VIMMA_CTRL_IB_ADM_MODE_SM_STANDARD";
+	case EPSC_VIMMA_CTRL_IB_ADM_MODE_VM_FABRIC_PROFILE:
+		return "EPSC_VIMMA_CTRL_IB_ADM_MODE_VM_FABRIC_PROFILE";
+	case PSIF_EPSC_VIMMA_ADMMODE_FIELD_MAX:
+		return "PSIF_EPSC_VIMMA_ADMMODE_FIELD_MAX";
+	default:
+		return "UNKNOWN_psif_epsc_vimma_admmode";
+	}
+}
+
+void write_enum_psif_epsc_vimma_admmode(XFILE *fd,
+	enum psif_epsc_vimma_admmode data)
+{
+	xprintf(fd, "%s", string_enum_psif_epsc_vimma_admmode(data));
+} /* end write_..._psif_epsc_vimma_admmode(psif_epsc_vimma_admmode data) */
+
+/* Convert enum psif_cq_state to string */
+const char *string_enum_psif_cq_state(enum psif_cq_state val)
+{
+	switch (val) {
+	case PSIF_CQ_UNARMED:
+		return "PSIF_CQ_UNARMED";
+	case PSIF_CQ_ARMED_SE:
+		return "PSIF_CQ_ARMED_SE";
+	case PSIF_CQ_ARMED_ALL:
+		return "PSIF_CQ_ARMED_ALL";
+	case PSIF_CQ_TRIGGERED:
+		return "PSIF_CQ_TRIGGERED";
+	default:
+		return "UNKNOWN_psif_cq_state";
+	}
+}
+
+void write_enum_psif_cq_state(XFILE *fd,
+	enum psif_cq_state data)
+{
+	xprintf(fd, "%s", string_enum_psif_cq_state(data));
+} /* end write_..._psif_cq_state(psif_cq_state data) */
+
+/* Convert enum psif_rss_hash_source to string */
+const char *string_enum_psif_rss_hash_source(enum psif_rss_hash_source val)
+{
+	switch (val) {
+	case RSS_WITHOUT_PORT:
+		return "RSS_WITHOUT_PORT";
+	case RSS_WITH_PORT:
+		return "RSS_WITH_PORT";
+	default:
+		return "UNKNOWN_psif_rss_hash_source";
+	}
+}
+
+void write_enum_psif_rss_hash_source(XFILE *fd,
+	enum psif_rss_hash_source data)
+{
+	xprintf(fd, "%s", string_enum_psif_rss_hash_source(data));
+} /* end write_..._psif_rss_hash_source(psif_rss_hash_source data) */
+
+#if !defined(PSIF_EXCLUDE_WRITE_STRUCTS)
+
+
+void write_struct_psif_csr_mmu_config(XFILE *fd,
+	int network_order,
+	const struct psif_csr_mmu_config *data)
+{
+	u64 swap[1];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 8);
+		data = (struct psif_csr_mmu_config *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .cam_evict_cntr_prescale_sel = ");
+	write_bits_u8(fd, 3, data->cam_evict_cntr_prescale_sel);
+	xprintf(fd, ", .cam_evict_cntr_cnt_sel = ");
+	write_bits_u8(fd, 5, data->cam_evict_cntr_cnt_sel);
+	xprintf(fd, ", .ptwc_evict_algorithm = ");
+	write_bits_u8(fd, 1, data->ptwc_evict_algorithm);
+	xprintf(fd, ", .mmuc_evict_algorithm = ");
+	write_bits_u8(fd, 1, data->mmuc_evict_algorithm);
+	xprintf(fd, ", .random_evict = ");
+	write_bits_u8(fd, 1, data->random_evict);
+	xprintf(fd, ", .mmuc_hash_select = ");
+	write_bits_u8(fd, 2, data->mmuc_hash_select);
+	xprintf(fd, ", .swap_rsp = ");
+	write_bits_u8(fd, 1, data->swap_rsp);
+	xprintf(fd, ", .chk_upper_addr_bits = ");
+	write_bits_u8(fd, 1, data->chk_upper_addr_bits);
+	xprintf(fd, ", .chk_bit_sixty_three = ");
+	write_bits_u8(fd, 1, data->chk_bit_sixty_three);
+	xprintf(fd, ", .bit_sixty_three_value = ");
+	write_bits_u8(fd, 1, data->bit_sixty_three_value);
+	xprintf(fd, ", .sparc_pages = ");
+	write_bits_u8(fd, 1, data->sparc_pages);
+	xprintf(fd, ", .dma_cnt_mask = ");
+	write_bits_u8(fd, 8, data->dma_cnt_mask);
+	xprintf(fd, ", .ptwc_hash_sel = ");
+	write_bits_u8(fd, 2, data->ptwc_hash_sel);
+	xprintf(fd, ", .dis_table_ptr_trans = ");
+	write_bits_u8(fd, 1, data->dis_table_ptr_trans);
+	xprintf(fd, ", .cam_par_err_fatal = ");
+	write_bits_u8(fd, 1, data->cam_par_err_fatal);
+	xprintf(fd, ", .ta_upper_twelve = ");
+	write_bits_u16(fd, 12, data->ta_upper_twelve);
+	xprintf(fd, ", .pa_upper_twelve = ");
+	write_bits_u16(fd, 12, data->pa_upper_twelve);
+	xprintf(fd, "}");
+} /* end write_..._psif_csr_mmu_config(psif_csr_mmu_config data) */
+
+void write_struct_psif_mmu_cntx(XFILE *fd,
+	int network_order,
+	const struct psif_mmu_cntx *data)
+{
+	u64 swap[1];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 8);
+		data = (struct psif_mmu_cntx *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .table_level = ");
+	write_bits_u8(fd, 3, data->table_level);
+	xprintf(fd, ", .wr_access = ");
+	write_bits_u8(fd, 1, data->wr_access);
+	xprintf(fd, ", .page_size = ");
+	write_enum_psif_page_size(fd, data->page_size);
+	xprintf(fd, ", .translation_type = ");
+	write_enum_psif_mmu_translation(fd, data->translation_type);
+	xprintf(fd, ", .th = ");
+	write_bits_u8(fd, 1, data->th);
+	xprintf(fd, ", .table_ptr = ");
+	write_bits_u64(fd, 40, data->table_ptr);
+	xprintf(fd, ", .ro = ");
+	write_bits_u8(fd, 1, data->ro);
+	xprintf(fd, ", .tph = ");
+	write_bits_u8(fd, 2, data->tph);
+	xprintf(fd, ", .ns = ");
+	write_bits_u8(fd, 1, data->ns);
+	xprintf(fd, ", .st = ");
+	write_bits_u8(fd, 8, data->st);
+	xprintf(fd, "}");
+} /* end write_..._psif_mmu_cntx(psif_mmu_cntx data) */
+
+void write_struct_psif_vlan_union_struct(XFILE *fd,
+	int network_order,
+	const struct psif_vlan_union_struct *data)
+{
+	xprintf(fd, "{");
+	xprintf(fd, ", .vlan_pri = ");
+	write_bits_u8(fd, 4, data->vlan_pri);
+	xprintf(fd, "}");
+} /* end write_..._psif_vlan_union_struct(psif_vlan_union_struct data) */
+
+void write_union_psif_cq_desc_vlan_pri(XFILE *fd,
+	int network_order,
+	const union psif_cq_desc_vlan_pri *data)
+{
+	xprintf(fd, "{");
+	xprintf(fd, " .cqd_id = ");
+	write_bits_u32(fd, 24, data->cqd_id);
+	xprintf(fd, ", .vlan_pri = ");
+	write_struct_psif_vlan_union_struct(fd, 0, &(data->vlan_pri));
+	xprintf(fd, "}");
+} /* end write_..._psif_cq_desc_vlan_pri(psif_cq_desc_vlan_pri data) */
+
+void write_struct_psif_wr_common(XFILE *fd,
+	int network_order,
+	const struct psif_wr_common *data)
+{
+	u64 swap[3];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 24);
+		data = (struct psif_wr_common *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .sq_seq = ");
+	write_bits_u16(fd, 16, data->sq_seq);
+	xprintf(fd, ", .collect_length = ");
+	write_bits_u16(fd, 9, data->collect_length);
+	xprintf(fd, ", .tsu_qosl = ");
+	write_enum_psif_tsu_qos(fd, data->tsu_qosl);
+	xprintf(fd, ", .ud_pkt = ");
+	write_enum_psif_use_ah(fd, data->ud_pkt);
+	xprintf(fd, ", .port = ");
+	write_enum_psif_port(fd, data->port);
+	xprintf(fd, ", .tsu_sl = ");
+	write_bits_u8(fd, 4, data->tsu_sl);
+	xprintf(fd, ", .local_qp = ");
+	write_bits_u32(fd, 24, data->local_qp);
+	xprintf(fd, ", .op = ");
+	write_enum_psif_wr_type(fd, data->op);
+	xprintf(fd, ", .cq_desc_vlan_pri_union = ");
+	write_union_psif_cq_desc_vlan_pri(fd, 0, &(data->cq_desc_vlan_pri_union));
+	xprintf(fd, ", .srcuf = ");
+	write_bits_u8(fd, 6, data->srcuf);
+	xprintf(fd, ", .fence = ");
+	write_bits_u8(fd, 1, data->fence);
+	xprintf(fd, ", .completion = ");
+	write_bits_u8(fd, 1, data->completion);
+	xprintf(fd, ", .eps_tag = ");
+	write_bits_u16(fd, 16, data->eps_tag);
+	xprintf(fd, ", .destuf = ");
+	write_bits_u8(fd, 6, data->destuf);
+	xprintf(fd, ", .num_sgl = ");
+	write_bits_u8(fd, 4, data->num_sgl);
+	xprintf(fd, ", .l4_checksum_en = ");
+	write_bits_u8(fd, 1, data->l4_checksum_en);
+	xprintf(fd, ", .l3_checksum_en = ");
+	write_bits_u8(fd, 1, data->l3_checksum_en);
+	xprintf(fd, ", .dynamic_mtu_enable = ");
+	write_bits_u8(fd, 1, data->dynamic_mtu_enable);
+	xprintf(fd, ", .se = ");
+	write_bits_u8(fd, 1, data->se);
+	xprintf(fd, ", .checksum = ");
+	write_bits_u32(fd, 32, data->checksum);
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_common(psif_wr_common data) */
+
+void write_struct_psif_wr_qp(XFILE *fd,
+	int network_order,
+	const struct psif_wr_qp *data)
+{
+	u64 swap[1];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 8);
+		data = (struct psif_wr_qp *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .qkey = ");
+	write_bits_u32(fd, 32, data->qkey);
+	xprintf(fd, ", .remote_qp = ");
+	write_bits_u32(fd, 24, data->remote_qp);
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_qp(psif_wr_qp data) */
+
+void write_struct_psif_wr_local(XFILE *fd,
+	int network_order,
+	const struct psif_wr_local *data)
+{
+	u64 swap[2];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 16);
+		data = (struct psif_wr_local *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .addr = ");
+	write_bits_u64(fd, 64, data->addr);
+	xprintf(fd, ", .length = ");
+	write_bits_u32(fd, 32, data->length);
+	xprintf(fd, ", .lkey = ");
+	write_bits_u32(fd, 32, data->lkey);
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_local(psif_wr_local data) */
+
+void write_struct_psif_wr_addr(XFILE *fd,
+	int network_order,
+	const struct psif_wr_addr *data)
+{
+	xprintf(fd, "{");
+	xprintf(fd, " .ah_indx = ");
+	write_bits_u32(fd, 24, data->ah_indx);
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_addr(psif_wr_addr data) */
+
+void write_struct_psif_wr_send_header_ud(XFILE *fd,
+	int network_order,
+	const struct psif_wr_send_header_ud *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (struct psif_wr_send_header_ud *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .qp = ");
+	write_struct_psif_wr_qp(fd, 0, &(data->qp));
+	xprintf(fd, ", .local_addr = ");
+	write_struct_psif_wr_local(fd, 0, &(data->local_addr));
+	xprintf(fd, ", .mss = ");
+	write_bits_u16(fd, 14, data->mss);
+	xprintf(fd, ", .remote_addr = ");
+	write_struct_psif_wr_addr(fd, 0, &(data->remote_addr));
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_send_header_ud(psif_wr_send_header_ud data) */
+
+void write_struct_psif_wr_send_header_uc_rc_xrc(XFILE *fd,
+	int network_order,
+	const struct psif_wr_send_header_uc_rc_xrc *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (struct psif_wr_send_header_uc_rc_xrc *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .local_addr = ");
+	write_struct_psif_wr_local(fd, 0, &(data->local_addr));
+	xprintf(fd, ", .mss = ");
+	write_bits_u16(fd, 14, data->mss);
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_send_header_uc_rc_xrc(psif_wr_send_header_uc_rc_xrc data) */
+
+void write_union_psif_wr_send_header(XFILE *fd,
+	int network_order,
+	const union psif_wr_send_header *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (union psif_wr_send_header *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .ud = ");
+	write_struct_psif_wr_send_header_ud(fd, 0, &(data->ud));
+	xprintf(fd, ", .uc_rc_xrc = ");
+	write_struct_psif_wr_send_header_uc_rc_xrc(fd, 0, &(data->uc_rc_xrc));
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_send_header(psif_wr_send_header data) */
+
+void write_struct_psif_wr_remote(XFILE *fd,
+	int network_order,
+	const struct psif_wr_remote *data)
+{
+	u64 swap[2];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 16);
+		data = (struct psif_wr_remote *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .addr = ");
+	write_bits_u64(fd, 64, data->addr);
+	xprintf(fd, ", .length = ");
+	write_bits_u32(fd, 32, data->length);
+	xprintf(fd, ", .rkey = ");
+	write_bits_u32(fd, 32, data->rkey);
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_remote(psif_wr_remote data) */
+
+void write_struct_psif_wr_rdma(XFILE *fd,
+	int network_order,
+	const struct psif_wr_rdma *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (struct psif_wr_rdma *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .local_addr = ");
+	write_struct_psif_wr_local(fd, 0, &(data->local_addr));
+	xprintf(fd, ", .remote_addr = ");
+	write_struct_psif_wr_remote(fd, 0, &(data->remote_addr));
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_rdma(psif_wr_rdma data) */
+
+void write_struct_psif_send_completion_id(XFILE *fd,
+	int network_order,
+	const struct psif_send_completion_id *data)
+{
+	u64 swap[1];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 8);
+		data = (struct psif_send_completion_id *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .eps_tag = ");
+	write_bits_u16(fd, 16, data->eps_tag);
+	xprintf(fd, ", .sq_seq_num = ");
+	write_bits_u16(fd, 16, data->sq_seq_num);
+	xprintf(fd, ", .sequence_number = ");
+	write_bits_u32(fd, 32, data->sequence_number);
+	xprintf(fd, "}");
+} /* end write_..._psif_send_completion_id(psif_send_completion_id data) */
+
+void write_struct_psif_event_completion_id(XFILE *fd,
+	int network_order,
+	const struct psif_event_completion_id *data)
+{
+	u64 swap[1];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 8);
+		data = (struct psif_event_completion_id *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .cq_id = ");
+	write_bits_u32(fd, 24, data->cq_id);
+	xprintf(fd, "}");
+} /* end write_..._psif_event_completion_id(psif_event_completion_id data) */
+
+void write_union_psif_completion_wc_id(XFILE *fd,
+	int network_order,
+	const union psif_completion_wc_id *data)
+{
+	u64 swap[1];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 8);
+		data = (union psif_completion_wc_id *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .rq_id = ");
+	write_bits_u64(fd, 64, data->rq_id);
+	xprintf(fd, ", .sq_id = ");
+	write_struct_psif_send_completion_id(fd, 0, &(data->sq_id));
+	xprintf(fd, ", .ecq_id = ");
+	write_struct_psif_event_completion_id(fd, 0, &(data->ecq_id));
+	xprintf(fd, "}");
+} /* end write_..._psif_completion_wc_id(psif_completion_wc_id data) */
+
+void write_union_psif_descriptor_union(XFILE *fd,
+	int network_order,
+	const union psif_descriptor_union *data)
+{
+	xprintf(fd, "{");
+	xprintf(fd, " .rq_id = ");
+	write_bits_u32(fd, 24, data->rq_id);
+	xprintf(fd, ", .xrq_id = ");
+	write_bits_u32(fd, 24, data->xrq_id);
+	xprintf(fd, ", .cq_id = ");
+	write_bits_u32(fd, 24, data->cq_id);
+	xprintf(fd, ", .target_qp = ");
+	write_bits_u32(fd, 24, data->target_qp);
+	xprintf(fd, "}");
+} /* end write_..._psif_descriptor_union(psif_descriptor_union data) */
+
+void write_struct_psif_wr_su(XFILE *fd,
+	int network_order,
+	const struct psif_wr_su *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (struct psif_wr_su *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .wc_id = ");
+	write_union_psif_completion_wc_id(fd, 0, &(data->wc_id));
+	xprintf(fd, ", .addr = ");
+	write_bits_u64(fd, 64, data->addr);
+	xprintf(fd, ", .length = ");
+	write_bits_u32(fd, 32, data->length);
+	xprintf(fd, ", .key = ");
+	write_bits_u32(fd, 32, data->key);
+	xprintf(fd, ", .u2 = ");
+	write_union_psif_descriptor_union(fd, 0, &(data->u2));
+	xprintf(fd, ", .completion_status = ");
+	write_enum_psif_wc_status(fd, data->completion_status);
+	xprintf(fd, ", .completion_opcode = ");
+	write_enum_psif_wc_opcode(fd, data->completion_opcode);
+	xprintf(fd, ", .srq_lim = ");
+	write_bits_u16(fd, 14, data->srq_lim);
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_su(psif_wr_su data) */
+
+void write_union_psif_wr_details(XFILE *fd,
+	int network_order,
+	const union psif_wr_details *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (union psif_wr_details *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .send = ");
+	write_union_psif_wr_send_header(fd, 0, &(data->send));
+	xprintf(fd, ", .rdma = ");
+	write_struct_psif_wr_rdma(fd, 0, &(data->rdma));
+	xprintf(fd, ", .atomic = ");
+	write_struct_psif_wr_rdma(fd, 0, &(data->atomic));
+	xprintf(fd, ", .su = ");
+	write_struct_psif_wr_su(fd, 0, &(data->su));
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_details(psif_wr_details data) */
+
+void write_struct_psif_wr_xrc(XFILE *fd,
+	int network_order,
+	const struct psif_wr_xrc *data)
+{
+	xprintf(fd, "{");
+	xprintf(fd, " .xrqd_id = ");
+	write_bits_u32(fd, 24, data->xrqd_id);
+	xprintf(fd, "}");
+} /* end write_..._psif_wr_xrc(psif_wr_xrc data) */
+
+void write_struct_psif_wr(XFILE *fd,
+	int network_order,
+	const struct psif_wr *data)
+{
+	enum psif_wr_type op;
+	enum psif_use_ah  ud;
+	struct psif_wr    swap;
+
+	if (network_order) {
+		copy_convert_to_sw(&swap, (volatile void *)data, 64);
+		data = &swap;
+	}
+
+	op = data->op;
+	ud = data->ud_pkt;
+
+	/* assertion: offsetof(struct psif_wr, imm) == sizeof(struct psif_wr_common) */
+	xprintf(fd, "{");
+	write_struct_psif_wr_common(fd, 0, (struct psif_wr_common *)data);
+	if ((op == PSIF_WR_SEND_IMM) || (op == PSIF_WR_RDMA_WR_IMM)) {
+		xprintf(fd, "  .imm = ");
+		write_bits_u32(fd, 32, data->imm);
+	}
+
+	xprintf(fd, "  .details = ");
+	/*   write_union_psif_wr_details(fd, 0, &(data->details)); */
+	xprintf(fd, "{");
+	/* write_union_psif_wr_send_header(fd, 0, &(data->send)); */
+
+	switch (op) {
+	case PSIF_WR_SEND:
+	case PSIF_WR_SEND_IMM:
+	case PSIF_WR_SPECIAL_QP_SEND:
+	case PSIF_WR_QP0_SEND_DR_XMIT:
+	case PSIF_WR_QP0_SEND_DR_LOOPBACK:
+	case PSIF_WR_EPS_SPECIAL_QP_SEND:
+	case PSIF_WR_EPS_QP0_SEND_DR_XMIT:
+	case PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK:
+		xprintf(fd, " send = ");
+		xprintf(fd, "{");
+		if (ud) {
+		xprintf(fd, " .ud = ");
+		write_struct_psif_wr_send_header_ud(fd, 0, &(data->details.send.ud));
+		} else {
+		xprintf(fd, "  .uc_rc_xrc = ");
+		write_struct_psif_wr_send_header_uc_rc_xrc(fd, 0, &(data->details.send.uc_rc_xrc));
+		}
+		xprintf(fd, "}");
+		break;
+
+	case PSIF_WR_RDMA_WR:
+	case PSIF_WR_RDMA_WR_IMM:
+	case PSIF_WR_RDMA_RD:
+		xprintf(fd, "  .rdma = ");
+		write_struct_psif_wr_rdma(fd, 0, &(data->details.rdma));
+		break;
+
+	case PSIF_WR_CMP_SWAP:
+	case PSIF_WR_FETCH_ADD:
+	case PSIF_WR_MASK_CMP_SWAP:
+	case PSIF_WR_MASK_FETCH_ADD:
+		xprintf(fd, "  .atomic = ");
+		write_struct_psif_wr_rdma(fd, 0, &(data->details.atomic));
+		break;
+
+	case PSIF_WR_INVALIDATE_RKEY:
+	case PSIF_WR_INVALIDATE_LKEY:
+	case PSIF_WR_INVALIDATE_BOTH_KEYS:
+	case PSIF_WR_INVALIDATE_TLB:
+	case PSIF_WR_RESIZE_CQ:
+	case PSIF_WR_SET_SRQ_LIM:
+	case PSIF_WR_SET_XRCSRQ_LIM:
+	case PSIF_WR_REQ_CMPL_NOTIFY:
+	case PSIF_WR_CMPL_NOTIFY_RCVD:
+	case PSIF_WR_REARM_CMPL_EVENT:
+	case PSIF_WR_INVALIDATE_RQ:
+	case PSIF_WR_INVALIDATE_CQ:
+	case PSIF_WR_INVALIDATE_XRCSRQ:
+	case PSIF_WR_INVALIDATE_SGL_CACHE:
+	case PSIF_WR_GENERATE_COMPLETION:
+		xprintf(fd, "  .su = ");
+		write_struct_psif_wr_su(fd, 0, &(data->details.su));
+		break;
+
+	case PSIF_WR_LSO:
+		break;
+	}
+	xprintf(fd, "}");
+
+	xprintf(fd, "  .xrc_hdr = ");
+	write_struct_psif_wr_xrc(fd, 0, &(data->xrc_hdr));
+	xprintf(fd, "}");
+		}
+
+void write_struct_psif_wr_expand(XFILE *fd,
+	int network_order,
+	const struct psif_wr *data)
+{
+	u64 swap[8];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 64);
+		data = (struct psif_wr *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .sq_seq = ");
+	write_bits_u16(fd, 16, data->sq_seq);
+	xprintf(fd, ", .collect_length = ");
+	write_bits_u16(fd, 9, data->collect_length);
+	xprintf(fd, ", .tsu_qosl = ");
+	write_enum_psif_tsu_qos(fd, data->tsu_qosl);
+	xprintf(fd, ", .ud_pkt = ");
+	write_enum_psif_use_ah(fd, data->ud_pkt);
+	xprintf(fd, ", .port = ");
+	write_enum_psif_port(fd, data->port);
+	xprintf(fd, ", .tsu_sl = ");
+	write_bits_u8(fd, 4, data->tsu_sl);
+	xprintf(fd, ", .local_qp = ");
+	write_bits_u32(fd, 24, data->local_qp);
+	xprintf(fd, ", .op = ");
+	write_enum_psif_wr_type(fd, data->op);
+	xprintf(fd, ", .cq_desc_vlan_pri_union = ");
+	write_union_psif_cq_desc_vlan_pri(fd, 0, &(data->cq_desc_vlan_pri_union));
+	xprintf(fd, ", .srcuf = ");
+	write_bits_u8(fd, 6, data->srcuf);
+	xprintf(fd, ", .fence = ");
+	write_bits_u8(fd, 1, data->fence);
+	xprintf(fd, ", .completion = ");
+	write_bits_u8(fd, 1, data->completion);
+	xprintf(fd, ", .eps_tag = ");
+	write_bits_u16(fd, 16, data->eps_tag);
+	xprintf(fd, ", .destuf = ");
+	write_bits_u8(fd, 6, data->destuf);
+	xprintf(fd, ", .num_sgl = ");
+	write_bits_u8(fd, 4, data->num_sgl);
+	xprintf(fd, ", .l4_checksum_en = ");
+	write_bits_u8(fd, 1, data->l4_checksum_en);
+	xprintf(fd, ", .l3_checksum_en = ");
+	write_bits_u8(fd, 1, data->l3_checksum_en);
+	xprintf(fd, ", .dynamic_mtu_enable = ");
+	write_bits_u8(fd, 1, data->dynamic_mtu_enable);
+	xprintf(fd, ", .se = ");
+	write_bits_u8(fd, 1, data->se);
+	xprintf(fd, ", .imm = ");
+	write_bits_u32(fd, 32, data->imm);
+	xprintf(fd, ", .checksum = ");
+	write_bits_u32(fd, 32, data->checksum);
+	xprintf(fd, ", .details = ");
+	write_union_psif_wr_details(fd, 0, &(data->details));
+	xprintf(fd, ", .xrc_hdr = ");
+	write_struct_psif_wr_xrc(fd, 0, &(data->xrc_hdr));
+	xprintf(fd, "}");
+} /* end write_..._psif_wr(psif_wr data) */
+
+void write_struct_psif_next(XFILE *fd,
+	int network_order,
+	const struct psif_next *data)
+{
+	xprintf(fd, "{");
+	xprintf(fd, " .next_null = ");
+	write_bits_u8(fd, 8, data->next_null);
+	xprintf(fd, ", .next_qp_num = ");
+	write_bits_u32(fd, 24, data->next_qp_num);
+	xprintf(fd, "}");
+} /* end write_..._psif_next(psif_next data) */
+
+void write_struct_psif_sq_sw(XFILE *fd,
+	int network_order,
+	const struct psif_sq_sw *data)
+{
+	u64 swap[1];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 8);
+		data = (struct psif_sq_sw *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, ", .tail_indx = ");
+	write_bits_u16(fd, 16, data->tail_indx);
+	xprintf(fd, "}");
+} /* end write_..._psif_sq_sw(psif_sq_sw data) */
+
+void write_struct_psif_sq_hw(XFILE *fd,
+	int network_order,
+	const struct psif_sq_hw *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (struct psif_sq_hw *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .u_1 = ");
+	write_bits_u16(fd, 16, data->u_1);
+	xprintf(fd, ", .last_seq = ");
+	write_bits_u16(fd, 16, data->last_seq);
+	xprintf(fd, ", .sq_next = ");
+	write_struct_psif_next(fd, 0, &(data->sq_next));
+	xprintf(fd, ", .sq_max_inline = ");
+	write_bits_u16(fd, 9, data->sq_max_inline);
+	xprintf(fd, ", .size_log2 = ");
+	write_bits_u8(fd, 4, data->size_log2);
+	xprintf(fd, ", .sq_max_sge = ");
+	write_bits_u8(fd, 5, data->sq_max_sge);
+	xprintf(fd, ", .extent_log2 = ");
+	write_bits_u8(fd, 5, data->extent_log2);
+	xprintf(fd, ", .qos = ");
+	write_bits_u8(fd, 1, data->qos);
+	xprintf(fd, ", .sq_timestamp_valid = ");
+	write_bits_u8(fd, 1, data->sq_timestamp_valid);
+	xprintf(fd, ", .sq_done = ");
+	write_bits_u8(fd, 2, data->sq_done);
+	xprintf(fd, ", .destroyed = ");
+	write_bits_u8(fd, 1, data->destroyed);
+	xprintf(fd, ", .u_2 = ");
+	write_bits_u32(fd, 32, data->u_2);
+	xprintf(fd, ", .base_addr = ");
+	write_bits_u64(fd, 64, data->base_addr);
+	xprintf(fd, ", .mmu_cntx = ");
+	write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx));
+	xprintf(fd, "}");
+} /* end write_..._psif_sq_hw(psif_sq_hw data) */
+
+void write_struct_psif_sq_entry(XFILE *fd,
+	int network_order,
+	const struct psif_sq_entry *data)
+{
+	u64 swap[40];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 320);
+		data = (struct psif_sq_entry *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .wr = ");
+	write_struct_psif_wr(fd, 0, &(data->wr));
+	xprintf(fd, ", .payload = ");
+	{ unsigned int i; for (i = 0; i < 32; i++) {
+		write_bits_u64(fd, 64, data->payload[i]);
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, "}");
+} /* end write_..._psif_sq_entry(psif_sq_entry data) */
+
+void write_struct_psif_rq_scatter(XFILE *fd,
+	int network_order,
+	const struct psif_rq_scatter *data)
+{
+	u64 swap[2];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 16);
+		data = (struct psif_rq_scatter *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .base_addr = ");
+	write_bits_u64(fd, 64, data->base_addr);
+	xprintf(fd, ", .lkey = ");
+	write_bits_u32(fd, 32, data->lkey);
+	xprintf(fd, ", .length = ");
+	write_bits_u32(fd, 32, data->length);
+	xprintf(fd, "}");
+} /* end write_..._psif_rq_scatter(psif_rq_scatter data) */
+
+void write_struct_psif_rq_sw(XFILE *fd,
+	int network_order,
+	const struct psif_rq_sw *data)
+{
+	u64 swap[1];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 8);
+		data = (struct psif_rq_sw *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, ", .tail_indx = ");
+	write_bits_u16(fd, 14, data->tail_indx);
+	xprintf(fd, "}");
+} /* end write_..._psif_rq_sw(psif_rq_sw data) */
+
+void write_struct_psif_rq_hw(XFILE *fd,
+	int network_order,
+	const struct psif_rq_hw *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (struct psif_rq_hw *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .srq_lim = ");
+	write_bits_u16(fd, 14, data->srq_lim);
+	xprintf(fd, ", .head_indx = ");
+	write_bits_u16(fd, 14, data->head_indx);
+	xprintf(fd, ", .extent_log2 = ");
+	write_bits_u8(fd, 4, data->extent_log2);
+	xprintf(fd, ", .pd = ");
+	write_bits_u32(fd, 24, data->pd);
+	xprintf(fd, ", .scatter = ");
+	write_bits_u8(fd, 4, data->scatter);
+	xprintf(fd, ", .srq_err = ");
+	write_bits_u8(fd, 1, data->srq_err);
+	xprintf(fd, ", .srq = ");
+	write_bits_u8(fd, 1, data->srq);
+	xprintf(fd, ", .sticky = ");
+	write_bits_u8(fd, 1, data->sticky);
+	xprintf(fd, ", .base_addr = ");
+	write_bits_u64(fd, 64, data->base_addr);
+	xprintf(fd, ", .mmu_cntx = ");
+	write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx));
+	xprintf(fd, ", .valid = ");
+	write_bits_u8(fd, 1, data->valid);
+	xprintf(fd, ", .prefetch_threshold_log2 = ");
+	write_bits_u8(fd, 4, data->prefetch_threshold_log2);
+	xprintf(fd, ", .size_log2 = ");
+	write_bits_u8(fd, 4, data->size_log2);
+	xprintf(fd, "}");
+} /* end write_..._psif_rq_hw(psif_rq_hw data) */
+
+void write_struct_psif_rq_entry(XFILE *fd,
+	int network_order,
+	const struct psif_rq_entry *data)
+{
+	u64 swap[33];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 264);
+		data = (struct psif_rq_entry *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .rqe_id = ");
+	write_bits_u64(fd, 64, data->rqe_id);
+	xprintf(fd, ", .scatter = ");
+	{ unsigned int i; for (i = 0; i < 16; i++) {
+		write_struct_psif_rq_scatter(fd, 0, &(data->scatter[i]));
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, "}");
+} /* end write_..._psif_rq_entry(psif_rq_entry data) */
+
+void write_struct_psif_qp_core(XFILE *fd,
+	int network_order,
+	const struct psif_qp_core *data)
+{
+	u64 swap[16];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 128);
+		data = (struct psif_qp_core *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .retry_tag_committed = ");
+	write_bits_u8(fd, 3, data->retry_tag_committed);
+	xprintf(fd, ", .retry_tag_err = ");
+	write_bits_u8(fd, 3, data->retry_tag_err);
+	xprintf(fd, ", .req_access_error = ");
+	write_bits_u8(fd, 1, data->req_access_error);
+	xprintf(fd, ", .resp_access_error = ");
+	write_bits_u8(fd, 1, data->resp_access_error);
+	xprintf(fd, ", .xrc_domain = ");
+	write_bits_u32(fd, 24, data->xrc_domain);
+	xprintf(fd, ", .error_retry_init = ");
+	write_bits_u8(fd, 3, data->error_retry_init);
+	xprintf(fd, ", .error_retry_count = ");
+	write_bits_u8(fd, 3, data->error_retry_count);
+	xprintf(fd, ", .cq_in_err = ");
+	write_bits_u8(fd, 1, data->cq_in_err);
+	xprintf(fd, ", .spin_hit = ");
+	write_bits_u8(fd, 1, data->spin_hit);
+	xprintf(fd, ", .sq_clog2_extent = ");
+	write_bits_u8(fd, 5, data->sq_clog2_extent);
+	xprintf(fd, ", .sq_clog2_size = ");
+	write_bits_u8(fd, 4, data->sq_clog2_size);
+	xprintf(fd, ", .current_outstanding = ");
+	write_bits_u8(fd, 5, data->current_outstanding);
+	xprintf(fd, ", .current_retired = ");
+	write_bits_u8(fd, 5, data->current_retired);
+	xprintf(fd, ", .is_multicast = ");
+	write_bits_u8(fd, 1, data->is_multicast);
+	xprintf(fd, ", .dscr_rq_in_progress = ");
+	write_bits_u8(fd, 1, data->dscr_rq_in_progress);
+	xprintf(fd, ", .first_at_floor_seen = ");
+	write_bits_u8(fd, 1, data->first_at_floor_seen);
+	xprintf(fd, ", .rq_is_srq = ");
+	write_bits_u8(fd, 1, data->rq_is_srq);
+	xprintf(fd, ", .do_not_evict = ");
+	write_bits_u8(fd, 1, data->do_not_evict);
+	xprintf(fd, ", .min_rnr_nak_time = ");
+	write_bits_u8(fd, 5, data->min_rnr_nak_time);
+	xprintf(fd, ", .state = ");
+	write_enum_psif_qp_state(fd, data->state);
+	xprintf(fd, ", .remote_qp = ");
+	write_bits_u32(fd, 24, data->remote_qp);
+	xprintf(fd, ", .rcv_rkey = ");
+	write_bits_u32(fd, 32, data->rcv_rkey);
+	xprintf(fd, ", .rcv_bytes = ");
+	write_bits_u32(fd, 32, data->rcv_bytes);
+	xprintf(fd, ", .retry_sq_seq = ");
+	write_bits_u16(fd, 16, data->retry_sq_seq);
+	xprintf(fd, ", .sq_seq = ");
+	write_bits_u16(fd, 16, data->sq_seq);
+	xprintf(fd, ", .magic = ");
+	write_bits_u32(fd, 32, data->magic);
+	xprintf(fd, ", .cq_seq = ");
+	write_bits_u32(fd, 32, data->cq_seq);
+	xprintf(fd, ", .qkey = ");
+	write_bits_u32(fd, 32, data->qkey);
+	xprintf(fd, ", .ib_retry_outstanding = ");
+	write_bits_u8(fd, 1, data->ib_retry_outstanding);
+	xprintf(fd, ", .fence_retry_outstanding = ");
+	write_bits_u8(fd, 1, data->fence_retry_outstanding);
+	xprintf(fd, ", .flush_started = ");
+	write_bits_u8(fd, 1, data->flush_started);
+	xprintf(fd, ", .request_handled = ");
+	write_bits_u8(fd, 1, data->request_handled);
+	xprintf(fd, ", .outstanding_error = ");
+	write_enum_psif_cmpl_outstanding_error(fd, data->outstanding_error);
+	xprintf(fd, ", .last_acked_psn = ");
+	write_bits_u32(fd, 24, data->last_acked_psn);
+	xprintf(fd, ", .scatter_offs = ");
+	write_bits_u32(fd, 32, data->scatter_offs);
+	xprintf(fd, ", .scatter_indx = ");
+	write_bits_u8(fd, 5, data->scatter_indx);
+	xprintf(fd, ", .expected_opcode = ");
+	write_enum_psif_expected_op(fd, data->expected_opcode);
+	xprintf(fd, ", .psn_nak = ");
+	write_bits_u8(fd, 1, data->psn_nak);
+	xprintf(fd, ", .expected_psn = ");
+	write_bits_u32(fd, 24, data->expected_psn);
+	xprintf(fd, ", .timeout_time = ");
+	write_bits_u64(fd, 48, data->timeout_time);
+	xprintf(fd, ", .nak_sent = ");
+	write_bits_u8(fd, 1, data->nak_sent);
+	xprintf(fd, ", .qosl = ");
+	write_enum_psif_tsu_qos(fd, data->qosl);
+	xprintf(fd, ", .mstate = ");
+	write_enum_psif_migration(fd, data->mstate);
+	xprintf(fd, ", .eoib_enable = ");
+	write_bits_u8(fd, 1, data->eoib_enable);
+	xprintf(fd, ", .ipoib_enable = ");
+	write_bits_u8(fd, 1, data->ipoib_enable);
+	xprintf(fd, ", .hdr_split_enable = ");
+	write_bits_u8(fd, 1, data->hdr_split_enable);
+	xprintf(fd, ", .rcv_dynamic_mtu_enable = ");
+	write_bits_u8(fd, 1, data->rcv_dynamic_mtu_enable);
+	xprintf(fd, ", .proxy_qp_enable = ");
+	write_bits_u8(fd, 1, data->proxy_qp_enable);
+	xprintf(fd, ", .rss_enable = ");
+	write_bits_u8(fd, 1, data->rss_enable);
+	xprintf(fd, ", .masked_atomic_enable = ");
+	write_bits_u8(fd, 1, data->masked_atomic_enable);
+	xprintf(fd, ", .atomic_enable = ");
+	write_bits_u8(fd, 1, data->atomic_enable);
+	xprintf(fd, ", .rdma_wr_enable = ");
+	write_bits_u8(fd, 1, data->rdma_wr_enable);
+	xprintf(fd, ", .rdma_rd_enable = ");
+	write_bits_u8(fd, 1, data->rdma_rd_enable);
+	xprintf(fd, ", .xmit_psn = ");
+	write_bits_u32(fd, 24, data->xmit_psn);
+	xprintf(fd, ", .retry_xmit_psn = ");
+	write_bits_u32(fd, 24, data->retry_xmit_psn);
+	xprintf(fd, ", .resp_scatter_indx = ");
+	write_bits_u8(fd, 5, data->resp_scatter_indx);
+	xprintf(fd, ", .rc_in_error = ");
+	write_bits_u8(fd, 1, data->rc_in_error);
+	xprintf(fd, ", .timer_running = ");
+	write_bits_u8(fd, 1, data->timer_running);
+	xprintf(fd, ", .tsl = ");
+	write_bits_u8(fd, 4, data->tsl);
+	xprintf(fd, ", .max_outstanding = ");
+	write_bits_u8(fd, 5, data->max_outstanding);
+	xprintf(fd, ", .dmalen = ");
+	write_bits_u32(fd, 32, data->dmalen);
+	xprintf(fd, ", .rnr_retry_init = ");
+	write_bits_u8(fd, 3, data->rnr_retry_init);
+	xprintf(fd, ", .rnr_retry_count = ");
+	write_bits_u8(fd, 3, data->rnr_retry_count);
+	xprintf(fd, ", .no_ordering = ");
+	write_bits_u8(fd, 1, data->no_ordering);
+	xprintf(fd, ", .no_checksum = ");
+	write_bits_u8(fd, 1, data->no_checksum);
+	xprintf(fd, ", .rq_indx = ");
+	write_bits_u32(fd, 24, data->rq_indx);
+	xprintf(fd, ", .transport_type = ");
+	write_enum_psif_qp_trans(fd, data->transport_type);
+	xprintf(fd, ", .rcv_cq_indx = ");
+	write_bits_u32(fd, 24, data->rcv_cq_indx);
+	xprintf(fd, ", .bytes_received = ");
+	write_bits_u32(fd, 32, data->bytes_received);
+	xprintf(fd, ", .eoib_type = ");
+	write_enum_psif_eoib_type(fd, data->eoib_type);
+	xprintf(fd, ", .exp_backoff_enable = ");
+	write_bits_u8(fd, 1, data->exp_backoff_enable);
+	xprintf(fd, ", .not_so_privileged = ");
+	write_bits_u8(fd, 1, data->not_so_privileged);
+	xprintf(fd, ", .send_dynamic_mtu_enable = ");
+	write_bits_u8(fd, 1, data->send_dynamic_mtu_enable);
+	xprintf(fd, ", .ipoib = ");
+	write_bits_u8(fd, 1, data->ipoib);
+	xprintf(fd, ", .eoib = ");
+	write_bits_u8(fd, 1, data->eoib);
+	xprintf(fd, ", .wait_for_psn = ");
+	write_bits_u8(fd, 1, data->wait_for_psn);
+	xprintf(fd, ", .resp_sched_count_done = ");
+	write_bits_u32(fd, 24, data->resp_sched_count_done);
+	xprintf(fd, ", .resp_sched_count_sched = ");
+	write_bits_u32(fd, 24, data->resp_sched_count_sched);
+	xprintf(fd, ", .resp_sched_sched_ptr = ");
+	write_bits_u8(fd, 5, data->resp_sched_sched_ptr);
+	xprintf(fd, ", .resp_sched_mode = ");
+	write_bits_u8(fd, 1, data->resp_sched_mode);
+	xprintf(fd, ", .swapped = ");
+	write_enum_psif_bool(fd, data->swapped);
+	xprintf(fd, ", .retry_needed = ");
+	write_bits_u8(fd, 1, data->retry_needed);
+	xprintf(fd, ", .last_received_outstanding_msn = ");
+	write_bits_u16(fd, 16, data->last_received_outstanding_msn);
+	xprintf(fd, ", .host_sent_nak = ");
+	write_bits_u8(fd, 1, data->host_sent_nak);
+	xprintf(fd, ", .in_safe_mode = ");
+	write_bits_u8(fd, 1, data->in_safe_mode);
+	xprintf(fd, ", .atomic_error = ");
+	write_bits_u8(fd, 1, data->atomic_error);
+	xprintf(fd, ", .apm_failed_event_sent = ");
+	write_bits_u8(fd, 1, data->apm_failed_event_sent);
+	xprintf(fd, ", .apm_success_event_sent = ");
+	write_bits_u8(fd, 1, data->apm_success_event_sent);
+	xprintf(fd, ", .apm_failed_event_needed = ");
+	write_bits_u8(fd, 1, data->apm_failed_event_needed);
+	xprintf(fd, ", .apm_success_event_needed = ");
+	write_bits_u8(fd, 1, data->apm_success_event_needed);
+	xprintf(fd, ", .req_addr = ");
+	write_bits_u64(fd, 64, data->req_addr);
+	xprintf(fd, ", .orig_atomic_wr_ptr = ");
+	write_bits_u8(fd, 4, data->orig_atomic_wr_ptr);
+	xprintf(fd, ", .path_mtu = ");
+	write_enum_psif_path_mtu(fd, data->path_mtu);
+	xprintf(fd, ", .comm_established = ");
+	write_enum_psif_comm_live(fd, data->comm_established);
+	xprintf(fd, ", .committed_received_psn = ");
+	write_bits_u32(fd, 24, data->committed_received_psn);
+	xprintf(fd, ", .resp_scatter_offs = ");
+	write_bits_u32(fd, 32, data->resp_scatter_offs);
+	xprintf(fd, ", .msn = ");
+	write_bits_u32(fd, 24, data->msn);
+	xprintf(fd, ", .send_cq_indx = ");
+	write_bits_u32(fd, 24, data->send_cq_indx);
+	xprintf(fd, ", .last_committed_msn = ");
+	write_bits_u16(fd, 16, data->last_committed_msn);
+	xprintf(fd, ", .srq_pd = ");
+	write_bits_u32(fd, 24, data->srq_pd);
+	xprintf(fd, ", .pd = ");
+	write_bits_u32(fd, 24, data->pd);
+	xprintf(fd, ", .eps_tag = ");
+	write_bits_u16(fd, 16, data->eps_tag);
+	xprintf(fd, "}");
+} /* end write_..._psif_qp_core(psif_qp_core data) */
+
+void write_struct_psif_qp_path(XFILE *fd,
+	int network_order,
+	const struct psif_qp_path *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (struct psif_qp_path *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .remote_gid_0 = ");
+	write_bits_u64(fd, 64, data->remote_gid_0);
+	xprintf(fd, ", .remote_gid_1 = ");
+	write_bits_u64(fd, 64, data->remote_gid_1);
+	xprintf(fd, ", .remote_lid = ");
+	write_bits_u16(fd, 16, data->remote_lid);
+	xprintf(fd, ", .gid_indx = ");
+	write_bits_u8(fd, 1, data->gid_indx);
+	xprintf(fd, ", .port = ");
+	write_enum_psif_port(fd, data->port);
+	xprintf(fd, ", .loopback = ");
+	write_enum_psif_loopback(fd, data->loopback);
+	xprintf(fd, ", .use_grh = ");
+	write_enum_psif_use_grh(fd, data->use_grh);
+	xprintf(fd, ", .sl = ");
+	write_bits_u8(fd, 4, data->sl);
+	xprintf(fd, ", .hoplmt = ");
+	write_bits_u8(fd, 8, data->hoplmt);
+	xprintf(fd, ", .tclass = ");
+	write_bits_u8(fd, 8, data->tclass);
+	xprintf(fd, ", .flowlabel = ");
+	write_bits_u32(fd, 20, data->flowlabel);
+	xprintf(fd, ", .path_invalid = ");
+	write_bits_u8(fd, 1, data->path_invalid);
+	xprintf(fd, ", .local_ack_timeout = ");
+	write_bits_u8(fd, 5, data->local_ack_timeout);
+	xprintf(fd, ", .ipd = ");
+	write_bits_u8(fd, 8, data->ipd);
+	xprintf(fd, ", .local_lid_path = ");
+	write_bits_u8(fd, 7, data->local_lid_path);
+	xprintf(fd, ", .pkey_indx = ");
+	write_bits_u16(fd, 9, data->pkey_indx);
+	xprintf(fd, "}");
+} /* end write_..._psif_qp_path(psif_qp_path data) */
+
+void write_struct_psif_query_qp(XFILE *fd,
+	int network_order,
+	const struct psif_query_qp *data)
+{
+	u64 swap[24];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 192);
+		data = (struct psif_query_qp *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .qp = ");
+	write_struct_psif_qp_core(fd, 0, &(data->qp));
+	xprintf(fd, ", .primary_path = ");
+	write_struct_psif_qp_path(fd, 0, &(data->primary_path));
+	xprintf(fd, ", .alternate_path = ");
+	write_struct_psif_qp_path(fd, 0, &(data->alternate_path));
+	xprintf(fd, "}");
+} /* end write_..._psif_query_qp(psif_query_qp data) */
+
+void write_struct_psif_qp(XFILE *fd,
+	int network_order,
+	const struct psif_qp *data)
+{
+	u64 swap[24];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 192);
+		data = (struct psif_qp *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .state = ");
+	write_struct_psif_qp_core(fd, 0, &(data->state));
+	xprintf(fd, ", .path_a = ");
+	write_struct_psif_qp_path(fd, 0, &(data->path_a));
+	xprintf(fd, ", .path_b = ");
+	write_struct_psif_qp_path(fd, 0, &(data->path_b));
+	xprintf(fd, "}");
+} /* end write_..._psif_qp(psif_qp data) */
+
+void write_struct_psif_cb(XFILE *fd,
+	int network_order,
+	const struct psif_cb *data)
+{
+	u64 swap[40];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 320);
+		data = (struct psif_cb *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .wr = ");
+	write_struct_psif_wr(fd, 0, &(data->wr));
+	xprintf(fd, ", .payload = ");
+	{ unsigned int i; for (i = 0; i < 32; i++) {
+		write_bits_u64(fd, 64, data->payload[i]);
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, "}");
+} /* end write_..._psif_cb(psif_cb data) */
+
+void write_struct_psif_modify_qp(XFILE *fd,
+	int network_order,
+	const struct psif_modify_qp *data)
+{
+	u64 swap[10];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 80);
+		data = (struct psif_modify_qp *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .max_outstanding = ");
+	write_bits_u8(fd, 5, data->max_outstanding);
+	xprintf(fd, ", .state = ");
+	write_enum_psif_qp_state(fd, data->state);
+	xprintf(fd, ", .min_rnr_nak_time = ");
+	write_bits_u8(fd, 5, data->min_rnr_nak_time);
+	xprintf(fd, ", .error_retry_count = ");
+	write_bits_u8(fd, 3, data->error_retry_count);
+	xprintf(fd, ", .eoib_enable = ");
+	write_bits_u8(fd, 1, data->eoib_enable);
+	xprintf(fd, ", .ipoib_enable = ");
+	write_bits_u8(fd, 1, data->ipoib_enable);
+	xprintf(fd, ", .hdr_split_enable = ");
+	write_bits_u8(fd, 1, data->hdr_split_enable);
+	xprintf(fd, ", .rcv_dynamic_mtu_enable = ");
+	write_bits_u8(fd, 1, data->rcv_dynamic_mtu_enable);
+	xprintf(fd, ", .proxy_qp_enable = ");
+	write_bits_u8(fd, 1, data->proxy_qp_enable);
+	xprintf(fd, ", .rss_enable = ");
+	write_bits_u8(fd, 1, data->rss_enable);
+	xprintf(fd, ", .masked_atomic_enable = ");
+	write_bits_u8(fd, 1, data->masked_atomic_enable);
+	xprintf(fd, ", .atomic_enable = ");
+	write_bits_u8(fd, 1, data->atomic_enable);
+	xprintf(fd, ", .rdma_wr_enable = ");
+	write_bits_u8(fd, 1, data->rdma_wr_enable);
+	xprintf(fd, ", .rdma_rd_enable = ");
+	write_bits_u8(fd, 1, data->rdma_rd_enable);
+	xprintf(fd, ", .rnr_retry_count = ");
+	write_bits_u8(fd, 3, data->rnr_retry_count);
+	xprintf(fd, ", .req_access_error = ");
+	write_bits_u8(fd, 1, data->req_access_error);
+	xprintf(fd, ", .rx_qkey = ");
+	write_bits_u32(fd, 32, data->rx_qkey);
+	xprintf(fd, ", .xmit_psn = ");
+	write_bits_u32(fd, 24, data->xmit_psn);
+	xprintf(fd, ", .mstate = ");
+	write_enum_psif_migration(fd, data->mstate);
+	xprintf(fd, ", .path_mtu = ");
+	write_enum_psif_path_mtu(fd, data->path_mtu);
+	xprintf(fd, ", .expected_psn = ");
+	write_bits_u32(fd, 24, data->expected_psn);
+	xprintf(fd, ", .primary_path = ");
+	write_struct_psif_qp_path(fd, 0, &(data->primary_path));
+	xprintf(fd, ", .alternate_path = ");
+	write_struct_psif_qp_path(fd, 0, &(data->alternate_path));
+	xprintf(fd, "}");
+} /* end write_..._psif_modify_qp(psif_modify_qp data) */
+
+void write_struct_psif_key(XFILE *fd,
+	int network_order,
+	const struct psif_key *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (struct psif_key *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, ", .zero_based_addr_en = ");
+	write_bits_u8(fd, 1, data->zero_based_addr_en);
+	xprintf(fd, ", .conditional_wr = ");
+	write_bits_u8(fd, 1, data->conditional_wr);
+	xprintf(fd, ", .local_access_atomic = ");
+	write_bits_u8(fd, 1, data->local_access_atomic);
+	xprintf(fd, ", .local_access_wr = ");
+	write_bits_u8(fd, 1, data->local_access_wr);
+	xprintf(fd, ", .local_access_rd = ");
+	write_bits_u8(fd, 1, data->local_access_rd);
+	xprintf(fd, ", .remote_access_atomic = ");
+	write_bits_u8(fd, 1, data->remote_access_atomic);
+	xprintf(fd, ", .remote_access_wr = ");
+	write_bits_u8(fd, 1, data->remote_access_wr);
+	xprintf(fd, ", .remote_access_rd = ");
+	write_bits_u8(fd, 1, data->remote_access_rd);
+	xprintf(fd, ", .pd = ");
+	write_bits_u32(fd, 24, data->pd);
+	xprintf(fd, ", .lkey_state = ");
+	write_enum_psif_dma_vt_key_states(fd, data->lkey_state);
+	xprintf(fd, ", .rkey_state = ");
+	write_enum_psif_dma_vt_key_states(fd, data->rkey_state);
+	xprintf(fd, ", .length = ");
+	write_bits_u64(fd, 64, data->length);
+	xprintf(fd, ", .mmu_context = ");
+	write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_context));
+	xprintf(fd, ", .base_addr = ");
+	write_bits_u64(fd, 64, data->base_addr);
+	xprintf(fd, "}");
+} /* end write_..._psif_key(psif_key data) */
+
+void write_struct_psif_flash_header_app(XFILE *fd,
+	int network_order,
+	const struct psif_flash_header_app *data)
+{
+	u64 swap[12];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 96);
+		data = (struct psif_flash_header_app *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .signature = ");
+	write_bits_u32(fd, 32, data->signature);
+	xprintf(fd, ", .type = ");
+	write_enum_psif_flash_image_type(fd, data->type);
+	xprintf(fd, ", .exec_base = ");
+	write_bits_u32(fd, 32, data->exec_base);
+	xprintf(fd, ", .image_length = ");
+	write_bits_u32(fd, 32, data->image_length);
+	xprintf(fd, ", .zi_base = ");
+	write_bits_u32(fd, 32, data->zi_base);
+	xprintf(fd, ", .zi_length = ");
+	write_bits_u32(fd, 32, data->zi_length);
+	xprintf(fd, ", .flash_base = ");
+	write_bits_u32(fd, 32, data->flash_base);
+	xprintf(fd, ", .start_addr = ");
+	write_bits_u32(fd, 32, data->start_addr);
+	xprintf(fd, ", .low_vec_base = ");
+	write_bits_u32(fd, 32, data->low_vec_base);
+	xprintf(fd, ", .low_vec_flash_base = ");
+	write_bits_u32(fd, 32, data->low_vec_flash_base);
+	xprintf(fd, ", .low_vec_length = ");
+	write_bits_u32(fd, 32, data->low_vec_length);
+	xprintf(fd, ", .date = ");
+	{ unsigned int i; for (i = 0; i < 4; i++) {
+		write_bits_u8(fd, 8, data->date[i]);
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, ", .date_1 = ");
+	{ unsigned int i; for (i = 0; i < 8; i++) {
+		write_bits_u8(fd, 8, data->date_1[i]);
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, ", .date_2 = ");
+	{ unsigned int i; for (i = 0; i < 4; i++) {
+		write_bits_u8(fd, 8, data->date_2[i]);
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, ", .time = ");
+	{ unsigned int i; for (i = 0; i < 4; i++) {
+		write_bits_u8(fd, 8, data->time[i]);
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, ", .time_1 = ");
+	{ unsigned int i; for (i = 0; i < 8; i++) {
+		write_bits_u8(fd, 8, data->time_1[i]);
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, ", .rev_string = ");
+	{ unsigned int i; for (i = 0; i < 8; i++) {
+		write_bits_u8(fd, 8, data->rev_string[i]);
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, ", .checksum_ptr = ");
+	write_bits_u32(fd, 32, data->checksum_ptr);
+	xprintf(fd, ", .app_vec_flash_base = ");
+	write_bits_u32(fd, 32, data->app_vec_flash_base);
+	xprintf(fd, ", .app_vec_base = ");
+	write_bits_u32(fd, 32, data->app_vec_base);
+	xprintf(fd, ", .app_vec_length = ");
+	write_bits_u32(fd, 32, data->app_vec_length);
+	xprintf(fd, "}");
+} /* end write_..._psif_flash_header_app(psif_flash_header_app data) */
+
+void write_struct_psif_flash_header_all(XFILE *fd,
+	int network_order,
+	const struct psif_flash_header_all *data)
+{
+	u64 swap[2];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 16);
+		data = (struct psif_flash_header_all *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .signature = ");
+	write_bits_u32(fd, 32, data->signature);
+	xprintf(fd, ", .type = ");
+	write_enum_psif_flash_image_type(fd, data->type);
+	xprintf(fd, ", .base = ");
+	write_bits_u32(fd, 32, data->base);
+	xprintf(fd, ", .length = ");
+	write_bits_u32(fd, 32, data->length);
+	xprintf(fd, "}");
+} /* end write_..._psif_flash_header_all(psif_flash_header_all data) */
+
+void write_struct_psif_eq_entry(XFILE *fd,
+	int network_order,
+	const struct psif_eq_entry *data)
+{
+	u64 swap[8];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 64);
+		data = (struct psif_eq_entry *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .eps_core_id = ");
+	write_enum_psif_eps_core_id(fd, data->eps_core_id);
+	xprintf(fd, ", .vendor_fields = ");
+	write_bits_u8(fd, 3, data->vendor_fields);
+	xprintf(fd, ", .port = ");
+	write_enum_psif_port(fd, data->port);
+	xprintf(fd, ", .cqd_id = ");
+	write_bits_u32(fd, 24, data->cqd_id);
+	xprintf(fd, ", .vendor_error = ");
+	write_enum_psif_tsu_error_types(fd, data->vendor_error);
+	xprintf(fd, ", .port_flags = ");
+	write_bits_u8(fd, 4, data->port_flags);
+	xprintf(fd, ", .event_status_eps_a = ");
+	write_bits_u8(fd, 1, data->event_status_eps_a);
+	xprintf(fd, ", .event_status_eps_c = ");
+	write_bits_u8(fd, 1, data->event_status_eps_c);
+	xprintf(fd, ", .event_status_cmpl_notify = ");
+	write_bits_u8(fd, 1, data->event_status_cmpl_notify);
+	xprintf(fd, ", .event_status_port_error = ");
+	write_bits_u8(fd, 1, data->event_status_port_error);
+	xprintf(fd, ", .event_status_local_catastrophic_error = ");
+	write_bits_u8(fd, 1, data->event_status_local_catastrophic_error);
+	xprintf(fd, ", .event_status_port_changed = ");
+	write_bits_u8(fd, 1, data->event_status_port_changed);
+	xprintf(fd, ", .event_status_client_registration = ");
+	write_bits_u8(fd, 1, data->event_status_client_registration);
+	xprintf(fd, ", .event_status_port_active = ");
+	write_bits_u8(fd, 1, data->event_status_port_active);
+	xprintf(fd, ", .event_status_local_work_queue_catastrophic_error = ");
+	write_bits_u8(fd, 1, data->event_status_local_work_queue_catastrophic_error);
+	xprintf(fd, ", .event_status_srq_catastrophic_error = ");
+	write_bits_u8(fd, 1, data->event_status_srq_catastrophic_error);
+	xprintf(fd, ", .event_status_invalid_xrceth = ");
+	write_bits_u8(fd, 1, data->event_status_invalid_xrceth);
+	xprintf(fd, ", .event_status_xrc_domain_violation = ");
+	write_bits_u8(fd, 1, data->event_status_xrc_domain_violation);
+	xprintf(fd, ", .event_status_path_migration_request_error = ");
+	write_bits_u8(fd, 1, data->event_status_path_migration_request_error);
+	xprintf(fd, ", .event_status_local_access_violation_wq_error = ");
+	write_bits_u8(fd, 1, data->event_status_local_access_violation_wq_error);
+	xprintf(fd, ", .event_status_invalid_request_local_wq_error = ");
+	write_bits_u8(fd, 1, data->event_status_invalid_request_local_wq_error);
+	xprintf(fd, ", .event_status_cq_error = ");
+	write_bits_u8(fd, 1, data->event_status_cq_error);
+	xprintf(fd, ", .event_status_last_wqe_reached = ");
+	write_bits_u8(fd, 1, data->event_status_last_wqe_reached);
+	xprintf(fd, ", .event_status_srq_limit_reached = ");
+	write_bits_u8(fd, 1, data->event_status_srq_limit_reached);
+	xprintf(fd, ", .event_status_communication_established = ");
+	write_bits_u8(fd, 1, data->event_status_communication_established);
+	xprintf(fd, ", .event_status_path_migrated = ");
+	write_bits_u8(fd, 1, data->event_status_path_migrated);
+	xprintf(fd, ", .lid = ");
+	write_bits_u16(fd, 16, data->lid);
+	xprintf(fd, ", .qp = ");
+	write_bits_u32(fd, 24, data->qp);
+	xprintf(fd, ", .rqd_id = ");
+	write_bits_u32(fd, 24, data->rqd_id);
+	xprintf(fd, ", .extension_type = ");
+	write_enum_psif_event(fd, data->extension_type);
+	xprintf(fd, ", .cq_sequence_number = ");
+	write_bits_u32(fd, 32, data->cq_sequence_number);
+	xprintf(fd, ", .event_info = ");
+	write_bits_u64(fd, 64, data->event_info);
+	xprintf(fd, ", .event_data = ");
+	write_bits_u64(fd, 64, data->event_data);
+	xprintf(fd, ", .seq_num = ");
+	write_bits_u32(fd, 32, data->seq_num);
+	xprintf(fd, "}");
+} /* end write_..._psif_eq_entry(psif_eq_entry data) */
+
+void write_struct_psif_epsc_exercise_mmu(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_exercise_mmu *data)
+{
+	u64 swap[11];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 88);
+		data = (struct psif_epsc_exercise_mmu *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .host_addr = ");
+	write_bits_u64(fd, 64, data->host_addr);
+	xprintf(fd, ", .mmu_cntx = ");
+	write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_cntx));
+	xprintf(fd, ", .length = ");
+	write_bits_u64(fd, 64, data->length);
+	xprintf(fd, ", .stride = ");
+	write_bits_u64(fd, 64, data->stride);
+	xprintf(fd, "}");
+} /* end write_..._psif_epsc_exercise_mmu(psif_epsc_exercise_mmu data) */
+
+void write_struct_psif_epsc_csr_rsp(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_rsp *data)
+{
+	u64 swap[4];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 32);
+		data = (struct psif_epsc_csr_rsp *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .addr = ");
+	write_bits_u32(fd, 32, data->addr);
+	xprintf(fd, ", .crc = ");
+	write_bits_u16(fd, 16, data->crc);
+	xprintf(fd, ", .opcode = ");
+	write_enum_psif_epsc_csr_opcode(fd, data->opcode);
+	xprintf(fd, ", .status = ");
+	write_enum_psif_epsc_csr_status(fd, data->status);
+	xprintf(fd, ", .data = ");
+	write_bits_u64(fd, 64, data->data);
+	xprintf(fd, ", .info = ");
+	write_bits_u64(fd, 64, data->info);
+	xprintf(fd, ", .seq_num = ");
+	write_bits_u64(fd, 64, data->seq_num);
+	xprintf(fd, "}");
+} /* end write_..._psif_epsc_csr_rsp(psif_epsc_csr_rsp data) */
+
+void write_struct_psif_epsc_csr_opaque(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_opaque *data)
+{
+	u64 swap[11];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 88);
+		data = (struct psif_epsc_csr_opaque *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .data = ");
+	{ unsigned int i; for (i = 0; i < 11; i++) {
+		write_bits_u64(fd, 64, data->data[i]);
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, "}");
+} /* end write_..._psif_epsc_csr_opaque(psif_epsc_csr_opaque data) */
+
+void write_struct_psif_epsc_csr_single(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_single *data)
+{
+	u64 swap[11];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 88);
+		data = (struct psif_epsc_csr_single *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .data = ");
+	write_bits_u64(fd, 64, data->data);
+	xprintf(fd, "}");
+} /* end write_..._psif_epsc_csr_single(psif_epsc_csr_single data) */
+
+void write_struct_psif_epsc_csr_base_addr(XFILE *fd,
+	int network_order,
+	const struct psif_epsc_csr_base_addr *data)
+{
+	u64 swap[11];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 88);
+		data = (struct psif_epsc_csr_base_addr *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .address = ");
+	write_bits_u64(fd, 64, data->address);
+	xprintf(fd, ", .mmu_context = ");
+	write_struct_psif_mmu_cntx(fd, 0, &(data->mmu_context));
+	xprintf(fd, ", .extent_log2 = ");
+	write_bits_u8(fd, 5, data->extent_log2);
+	xprintf(fd, ", .num_entries = ");
+	write_bits_u32(fd, 32, data->num_entries);
+	xprintf(fd, ", .msix_index = ");
+	write_bits_u32(fd, 32, data->msix_index);
+	xprintf(fd, ", .padding = ");
+	{ unsigned int i; for (i = 0; i < 7; i++) {
+		write_bits_u64(fd, 64, data->padding[i]);
+		xprintf(fd, ",");
+	}
+}
+	xprintf(fd, "}");
+} /* end write_..._psif_epsc_csr_base_addr(psif_epsc_csr_base_addr data) */
+
+void write_struct_psif_csr_modify_qp_ctrl(XFILE *fd,
+	int network_order,
+	const struct psif_csr_modify_qp_ctrl *data)
+{
+	u64 swap[1];
+
+	if (network_order) {
+		copy_convert_to_sw(swap, (volatile void *)data, 8);
+		data = (struct psif_csr_modify_qp_ctrl *)swap;
+	}
+	xprintf(fd, "{");
+	xprintf(fd, " .use_current_state = ");
+	write_bits_u8(fd, 1, data->use_current_state);
+	xprintf(fd, ", .max_outstanding = ");
+	write_bits_u8(fd, 1, data->max_outstanding);
+	xprintf(fd, ", .xmit_psn = ");
+	write_bits_u8(fd, 1, data->xmit_psn);
+	xprintf(fd, ", .rnr_retry_count = ");
+	write_bits_u8(fd, 1, data->rnr_retry_count);
+	xprintf(fd, ", .error_retry_count = ");
+	write_bits_u8(fd, 1, data->error_retry_count);
+	xprintf(fd, ", .min_rnr_nak_time = ");
+	write_bits_u8(fd, 1, data->min_rnr_nak_time);
+	xprintf(fd, ", .local_ack_timeout = ");
+	write_bits_u8(fd, 1, data->local_ack_timeout);
+	xprintf(fd, ", .pkey_index = ");
+	write_bits_u8(fd, 1, data->pkey_index);
+	xprintf(fd, ", .qkey = ");
+	write_bits_u8(fd, 1, data->qkey);
+	xprintf(fd, ", .qp_rcv_cap = ");
+	write_bits_u8(fd, 1, data->qp_rcv_cap);
+	xprintf(fd, ", .qp_state = ");
+	write_bits_u8(fd, 1, data->qp_state);
+	xprintf(fd, ", .alt_path = ");
+	write_bits_u8(fd, 1, data->alt_path);
+	xprintf(fd, ", .mig_state = ");
+	write_bits_u8(fd, 1, data->mig_state);
+	xprintf(fd, ", .prim_path = ");
+	write_bits_u8(fd, 1, data->prim_path);
+	xprintf(fd, ", .expected_psn = ");
+	write_bits_u8(fd, 1, data->expected_psn);
+	xprintf(fd, ", .path_mtu = ");
+	write_bits_u8(fd, 1, data->path_mtu);
+	xprintf(fd, ", .req_access_error = ");
+	write_bits_u8(fd, 1, data->req_access_error);
+	xprintf(fd, ", .notify_when_zero = ");
+	w