PSARC/2015/479 PSIF Solaris IB HCA Driver
22111504 RFE for libsif integration into userland gate
--- a/components/open-fabrics/Makefile Tue Mar 08 15:34:08 2016 -0800
+++ b/components/open-fabrics/Makefile Tue Mar 08 21:43:23 2016 -0800
@@ -18,7 +18,7 @@
#
# CDDL HEADER END
#
-# Copyright (c) 2010, 2015, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2010, 2016, Oracle and/or its affiliates. All rights reserved.
#
LD_Z_IGNORE =
@@ -27,7 +27,7 @@
COMPONENT_VERSION=1.5.3
COMPONENT_PROJECT_URL= http://www.openfabrics.org/
-COMPONENT_BUGDB= library/ofuv_lib utility/ofuv_tools
+COMPONENT_BUGDB= library/ofuv_lib utility/ofuv_tools library/ofuv_psif
TPNO_OPEN_FABRICS= 3369
TPNO_IBUTILS= 5084
@@ -104,6 +104,7 @@
opensm: libibumad libibmad
ibutils: opensm
infiniband-diags: libibverbs opensm
+libsif: libibverbs
FORCE:
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/Makefile Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,86 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+# Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved.
+#
+COMPILER = gcc
+include ../../../make-rules/shared-macros.mk
+
+COMPONENT_NAME= libsif
+COMPONENT_VERSION= 1.0
+COMPONENT_SRC= $(COMPONENT_NAME)-$(COMPONENT_VERSION)
+COMPONENT_ARCHIVE= $(COMPONENT_SRC).tar.gz
+COMPONENT_ARCHIVE_HASH= \
+ sha256:501858b4b9d45ebe163d9136f7fb4d08708aaf91cc97c40059ae2a1b4737239d
+COMPONENT_SERVER= download.oracle.com
+COMPONENT_ARCHIVE_URL= http://$(COMPONENT_SERVER)/otn-pub/oss/networking/$(COMPONENT_ARCHIVE)
+
+include $(WS_TOP)/make-rules/prep.mk
+include $(WS_TOP)/make-rules/configure.mk
+include ../ofed.mk
+
+REMOVE_OLD_SRC= sif.h sif_user.h sif_int_user.h os_header.h psif_api.h psif_endian.h psif_hw_print.h psif_hw_data* psif_hw_setget* psif_hw_macro* kernel_types.h
+# --disable-libcheck is not a supported option for this component
+DISABLE_LIBCHECK=
+
+LIBS += -libverbs
+LDFLAGS += -L$(PROTO_DIR)/$(CONFIGURE_LIBDIR.$(BITS))
+
+CONFIGURE_ENV += CPPFLAGS=" -DSOLARIS $(CPPFLAGS) -I../../include/sif/ -I../../include/psifapi/ -I../../$(COMPONENT_SRC)/src/ "
+
+CONFIGURE_OPTIONS += LDFLAGS="$(LDFLAGS)"
+
+COMPONENT_PREP_ACTION += cd $(COMPONENT_SRC)/src/ ; rm $(REMOVE_OLD_SRC) ; cd - ; \
+ (cd $(@D); \
+ autoreconf -ivf ; \
+ aclocal --force ; \
+ libtoolize --copy --force --ltdl ; \
+ autoconf --force ; \
+ autoheader --force)
+
+COMPONENT_POST_INSTALL_ACTION =\
+ $(RM) $(PROTO_DIR)/$(CONFIGURE_LIBDIR.32)/$(COMPONENT_NAME).la;\
+ $(RM) $(PROTO_DIR)/$(CONFIGURE_LIBDIR.64)/$(COMPONENT_NAME).la;\
+
+# common targets
+configure: $(CONFIGURE_64)
+
+build_sparc: $(BUILD_64)
+
+build_i386:
+ @echo "Not available."
+
+build: build_$(MACH)
+
+install_sparc: $(INSTALL_64)
+
+install_i386:
+ @echo "Not available."
+
+install: install_$(MACH)
+
+# we're sparc-only
+ifeq ($(MACH), i386)
+PUBLISH_STAMP=
+endif
+
+test: $(NO_TESTS)
+
+system-test: $(NO_TESTS)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/os_header.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _OS_HEADER_H
+#define _OS_HEADER_H
+/*
+ * os_header.h
+ *
+ * Operating system specific defines.
+ */
+#if defined(THREADX) || defined(NO_OS_ARM)
+
+/* THREADX/ARM is 32 bit */
+#define OS_PRIx64 "llx"
+#define OS_U64DEF "unsigned long long"
+
+#else /* !THREADX */
+
+#ifdef SOLARIS
+
+#include "solaris.h"
+
+#define OS_PRIx64 PRIx64
+#define OS_U64DEF "unsigned long"
+
+#else /* LINUX */
+
+#include <asm-generic/int-ll64.h>
+#include <endian.h>
+
+#if defined HAVE_DECL_BE64TOH_HTOBE64 && !HAVE_DECL_BE64TOH_HTOBE64
+#define be64toh(x) htonll(x)
+#define htobe64(x) ntohll(x)
+#endif
+
+#if defined (OS_PRIx64)
+/* Do not override... */
+#elif defined(_STDINT_H)
+#include <inttypes.h>
+#define OS_PRIx64 PRIx64
+#else
+/*
+ * Linux statically defines 64 bit words as type 'long long'
+ * regardless of 64 bit vs 32 bit compilation. However,
+ * the PRIx64 macro expands to 'lx' (type long) on 64 bit
+ * compilation, which is incompatible with the Linux 64 bit
+ * word definition.
+ */
+#define OS_PRIx64 "llx"
+#define OS_U64DEF "unsigned long long"
+#endif
+#endif /* LINUX */
+#endif /* !THREADX */
+
+#endif /* _OS_HEADER_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/psif_api.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PSIF_API_H
+#define _PSIF_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__arm__)
+#include <stdint.h>
+#define u8 uint8_t
+#define u16 uint16_t
+#define u32 uint32_t
+#define u64 uint64_t
+typedef uint64_t __be64 ;
+#endif /* __arm__ */
+
+#define PSIF_RELEASE_STR "PSIF.ARCH.05.68 revB"
+#define PSIF_MAJOR_VERSION 5
+#define PSIF_MINOR_VERSION 68
+#define PSIF_CHIP_VERSION 2
+#define PSIF_VERSION ((PSIF_MAJOR_VERSION<<8)+PSIF_MINOR_VERSION)
+#define PSIF_API_VERSION(x,y) ((x<<8)+y)
+
+#define PSIF_REV2
+
+#define PSIF1V0 (0x00D4206D)
+#define PSIF2V0 (0x10D4206D)
+#define PSIF2V1 (0x30D4206D)
+
+/*
+ * Update if protocol changes in a backward incompatible way
+ */
+#define EPSC_MAJOR_VERSION 0
+
+/*
+ * Update when new operations are added or otherwise
+ * backward compatible changes are made
+ */
+#define EPSC_MINOR_VERSION 101
+
+/*
+ * Macros for EPSC API #if checking in code
+ */
+#define EPSC_VERSION ((EPSC_MAJOR_VERSION<<16)+EPSC_MINOR_VERSION)
+#define EPSC_API_VERSION(x,y) ((x<<16)+y)
+
+/*
+ * Macro to conver 16 bit sequence number to 64 bit wire format
+ */
+#define EPSC_STATUS_16_to_64(s) ((((u64)(s)) << 0) | (((u64)(s)) << 16) | \
+ (((u64)(s)) << 32) | ((((u64)s)) << 48))
+/*
+ * Macros to force layout to match HW implementation
+ */
+#define PSIF_PACKED __attribute__((packed))
+#define PSIF_PACKED_ALIGNED
+#define PSIF_PACKED_ALIGNED32
+#define PSIF_ALIGNED
+#define PSIF_ALIGNED8
+
+#define PSIF_ALIGNED32
+
+#define PSIF_PF PSIF_VF0
+
+/* IPVer is a constant 6 */
+#define IB_GRH_IPVER 0x6
+
+/* No raw packets are supported so set nxthdr to 0x1B */
+#define IB_GRH_NXTHDR 0x1b
+
+/* ICRC - 4 bytes */
+#define IB_ICRC_WIDTH 32
+
+/* AUTOMATICALLY GENERATED from address_group. Width of the CSR data bus. */
+#define CSR_DATA_WIDTH 64
+
+/* Number of universal functions. */
+#define NUM_UF 34
+
+/* Number of vSwitch ports. */
+#define NUM_VSWITCH_PORTS 35
+
+/* Number of vHCAs. */
+#define NUM_VHCA 33
+
+/* Number of host ports. */
+#define NUM_HOST_PORTS 1
+
+/* Number of IB ports */
+#define NUM_IB_PORTS 2
+
+/* Number of GIDs per physical IB port (2*NUM_VHCA+1) */
+#define NUM_GIDS_PER_PORT 67
+
+#define NUM_SQ_EPS_CB 256
+
+/* Number of SQ scheduler lists */
+#define NUM_SQS_LIST 68
+
+/* Number of scatter elements. */
+#define NUM_SCATTER_ELEM 16
+
+/* XXX Based on what? */
+#define NUM_TVL 128
+
+/*
+ * Invalid UF number. Used in multicast handling for indicating end of
+ * multicast request from EPS.
+ */
+#define INVALID_UF_NUM 255
+
+/* Gid Inedxes per UF. */
+#define NUM_GID_INDEXES 2
+
+/* Number of physical collect buffers. */
+#define CBU_NUM_PCB 1024
+
+/* Number of virtual collect buffers. */
+#define CBU_NUM_VCB 16384
+
+/* Index to the error QP. */
+#define QPS_ERROR_INDEX 0
+
+/** Request value for mailbox register to restart */
+#define MAILBOX_RESTART ((u64)0)
+
+/** Response value for mailbox register on error */
+#define MAILBOX_IN_ERROR 0x0000ffffffff0000
+
+/** Mailbox (response) value for unused VFs */
+#define MAILBOX_NOT_IN_USE 0x0000ffeeeeff0000
+
+/** Mailbox response value for busy UFs (QP cleanup ongoing) */
+#define MAILBOX_NOT_READY 0x0000ffddddff0000
+
+/** Highes non-online mailbox sequence number - applied directly after reset */
+#define MAILBOX_SEQ_SET_PROTOCOL ((u16)0x7fff)
+
+/** MSB of mailbox sequence number */
+#define MAILBOX_SEQ_ONLINE_MASK ((u16)0x8000)
+
+/* Images will always be aligned on 32k boundaries */
+#define PSIF_IMAGE_ALIGNMENT 0x008000
+
+/* */
+#define PSIF_IMAGE_HEADER_OFFSET 0x800
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _PSIF_API_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/psif_endian.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PSIF_ENDIAN_H
+#define _PSIF_ENDIAN_H
+
+#if defined(__arm__)
+#undef HOST_BIG_ENDIAN
+#define HOST_LITTLE_ENDIAN
+#else /* __arm__ */
+#if defined(__KERNEL__)
+# if defined(__BIG_ENDIAN) || defined(_BIG_ENDIAN)
+# define HOST_BIG_ENDIAN
+# elif defined(__LITTLE_ENDIAN) || defined(_LITTLE_ENDIAN)
+# define HOST_LITTLE_ENDIAN
+# else
+# error "could not determine byte order"
+# endif
+#else /* defined(__KERNEL__) */
+# include <assert.h>
+# include "os_header.h"
+# if defined(__BYTE_ORDER)
+# if __BYTE_ORDER == __BIG_ENDIAN
+# define HOST_BIG_ENDIAN
+# elif __BYTE_ORDER == __LITTLE_ENDIAN
+# define HOST_LITTLE_ENDIAN
+# else
+# error "could not determine byte order"
+# endif
+# else /* defined(__BYTE_ORDER) */
+# error "could not determine byte order"
+# endif
+#endif /* defined(__KERNEL__) */
+#endif
+
+#if !defined (__KERNEL__)
+
+#if !defined(__arm__)
+#include <stdlib.h>
+#endif /* !__arm__ */
+
+#if defined(HOST_BIG_ENDIAN)
+
+#define copy_convert(dest,src,n) { memcpy((void *)dest, (void const *)(src), n); wmb(); }
+#define copy_convert_to_hw(dest,src,n) copy_convert(dest,src,n)
+#define copy_convert_to_sw(dest,src,n) copy_convert(dest,src,n)
+
+#else /* HOST_LITTLE_ENDIAN */
+
+#if defined(__arm__)
+#include <assert.h>
+#include <stdint.h>
+#include "epsfw_misc.h"
+#define htobe64(x) eps_htobe64(x)
+#define u64 uint64_t
+
+static inline void __DSB(void) {
+ /* __dsb() doesn't serve as sequence point in armcc so adding
+ * __schedule_barrier() around it to force the compiler to see it as a
+ * sequence point */
+ __schedule_barrier();
+ __dsb(0xf);
+ __schedule_barrier();
+}
+#define wmb() __DSB();
+
+/*
+ * Alternatively, use this one as barrier?
+ * #define wmb() __memory_changed();
+ */
+#endif /* __arm__ */
+
+static inline void _copy_convert(void *dest, void const *src, size_t n)
+{
+ int i, words = n / 8;
+ assert((n % 8) == 0);
+ volatile u64 *dp = (volatile u64 *) dest;
+ const volatile u64 *sp = (const volatile u64 *) src;
+ for (i = 0; i < words; i++) {
+ *dp++ = htobe64(*sp);
+ sp++;
+ }
+ wmb();
+}
+
+static inline void _copy_convert_to_hw(volatile void *dest, void const *src, size_t n)
+{
+ int i, words = n / 8;
+ assert((n % 8) == 0);
+ volatile u64 *dp = (volatile u64 *) dest;
+ const u64 *sp = (const u64 *) src;
+ for (i = 0; i < words; i++) {
+ *dp++ = htobe64(*sp);
+ sp++;
+ }
+ wmb();
+}
+
+static inline void _copy_convert_to_sw(void *dest, volatile void const *src, size_t n)
+{
+ int i, words = n / 8;
+ assert((n % 8) == 0);
+ u64 *dp = (u64 *) dest;
+ const volatile u64 *sp = (const volatile u64 *) src;
+ for (i = 0; i < words; i++) {
+ *dp++ = htobe64(*sp);
+ sp++;
+ }
+ wmb();
+}
+
+#define copy_convert(dest,src,n) _copy_convert(dest,src,n)
+#define copy_convert_to_hw(dest,src,n) _copy_convert_to_hw(dest,src,n)
+#define copy_convert_to_sw(dest,src,n) _copy_convert_to_sw(dest,src,n)
+
+#endif /* HOST_ENDIAN */
+#endif /* !__KERNEL__ */
+#endif /* _PSIF_ENDIAN_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/psif_fw_addr.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,14279 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PSIF_FW_ADDR_H
+#define _PSIF_FW_ADDR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "psif_api.h"
+
+
+ /*
+ * TSU VL mapping table for requests. Inputs/addressing to this table are
+ * {UF(35 UFs), tsu_qosl (High/Low BAR), tsu_sl, port}.
+ */
+#define TSU_HOST_TVL_TABLE_ADDR 0x00100000L
+#define TSU_HOST_TVL_TABLE_STRIDE 1
+#define TSU_HOST_TVL_TABLE_DEPTH 2240
+
+ /* Per TVL register.Maximum global credits a particular TVL can get. */
+#define TSU_HOST_MAX_GLOBAL_TVL_CRDTS_ADDR 0x00101000L
+#define TSU_HOST_MAX_GLOBAL_TVL_CRDTS_STRIDE 1
+#define TSU_HOST_MAX_GLOBAL_TVL_CRDTS_DEPTH 128
+
+ /*
+ * Per TVL register.Maximum private credits a particular TVL can get. The
+ * amount of credits dedicated to this TVL.
+ */
+#define TSU_HOST_PRIVATE_TVL_CRDTS_ADDR 0x00101080L
+#define TSU_HOST_PRIVATE_TVL_CRDTS_STRIDE 1
+#define TSU_HOST_PRIVATE_TVL_CRDTS_DEPTH 128
+
+ /* Total number of global credits assign to TVLs. */
+#define TSU_HOST_TOTAL_GLOBAL_TVL_CRDTS_ADDR 0x00101100L
+#define TSU_HOST_TOTAL_GLOBAL_TVL_CRDTS_STRIDE 1
+#define TSU_HOST_TOTAL_GLOBAL_TVL_CRDTS_DEPTH 1
+
+ /* weight given for round robin arbitration for xiu commands. */
+#define TSU_HOST_XIU_ARBITER_ADDR 0x00101101L
+#define TSU_HOST_XIU_ARBITER_STRIDE 1
+#define TSU_HOST_XIU_ARBITER_DEPTH 1
+
+ /* weight given for round robin arbitration for eps commands. */
+#define TSU_HOST_EPS_ARBITER_ADDR 0x00101102L
+#define TSU_HOST_EPS_ARBITER_STRIDE 1
+#define TSU_HOST_EPS_ARBITER_DEPTH 1
+
+ /* Data Latency skew from all clients to tsu_host. */
+#define TSU_HOST_DATA_LATENCY_ADDR 0x00101104L
+#define TSU_HOST_DATA_LATENCY_STRIDE 1
+#define TSU_HOST_DATA_LATENCY_DEPTH 1
+
+ /*
+ * Per TVL register. The amount of private and global credits used to this
+ * TVL.
+ */
+#define TSU_HOST_TVL_CRDTS_USED_ADDR 0x00101108L
+#define TSU_HOST_TVL_CRDTS_USED_STRIDE 1
+#define TSU_HOST_TVL_CRDTS_USED_DEPTH 128
+
+ /* Amount of global credits used shared among all TVLs. */
+#define TSU_HOST_GLOBAL_CRDTS_USED_ADDR 0x00101188L
+#define TSU_HOST_GLOBAL_CRDTS_USED_STRIDE 1
+#define TSU_HOST_GLOBAL_CRDTS_USED_DEPTH 1
+
+ /* when set puts the tsu_host in hca mode for Atomics. */
+#define TSU_HOST_HCA_MODE_ADDR 0x0010118aL
+#define TSU_HOST_HCA_MODE_STRIDE 1
+#define TSU_HOST_HCA_MODE_DEPTH 1
+
+ /*
+ * when set flips the compare and swap field in xiu meta_data bus in PCIe
+ * mode.
+ */
+#define TSU_HOST_ENABLE_PCIE_SWAP_ADDR 0x0010118bL
+#define TSU_HOST_ENABLE_PCIE_SWAP_STRIDE 1
+#define TSU_HOST_ENABLE_PCIE_SWAP_DEPTH 1
+
+ /* Handling Endianness of host Processor. */
+#define TSU_HOST_LITTLE_ENDIAN_MODE_ADDR 0x0010118cL
+#define TSU_HOST_LITTLE_ENDIAN_MODE_STRIDE 1
+#define TSU_HOST_LITTLE_ENDIAN_MODE_DEPTH 1
+
+ /* allocating global credits to llq in XIU */
+#define TSU_HOST_XIU_LLQ_GLOBAL_CREDITS_ADDR 0x0010118dL
+#define TSU_HOST_XIU_LLQ_GLOBAL_CREDITS_STRIDE 1
+#define TSU_HOST_XIU_LLQ_GLOBAL_CREDITS_DEPTH 1
+
+#define TSU_HOST_QP_BASE_ADDR_0_ADDR 0x00101194L
+#define TSU_HOST_QP_BASE_ADDR_0_STRIDE 1
+#define TSU_HOST_QP_BASE_ADDR_0_DEPTH 34
+
+#define TSU_HOST_QP_BASE_ADDR_1_ADDR 0x001011d4L
+#define TSU_HOST_QP_BASE_ADDR_1_STRIDE 1
+#define TSU_HOST_QP_BASE_ADDR_1_DEPTH 34
+
+#define TSU_HOST_QP_BASE_ADDR_2_ADDR 0x00101214L
+#define TSU_HOST_QP_BASE_ADDR_2_STRIDE 1
+#define TSU_HOST_QP_BASE_ADDR_2_DEPTH 34
+
+ /* MRS credit debug counter. */
+#define TSU_HOST_MRS_CREDIT_CNT_ADDR 0x00101256L
+#define TSU_HOST_MRS_CREDIT_CNT_STRIDE 1
+#define TSU_HOST_MRS_CREDIT_CNT_DEPTH 1
+
+ /* ERR credit debug counter. */
+#define TSU_HOST_ERR_CREDIT_CNT_ADDR 0x00101257L
+#define TSU_HOST_ERR_CREDIT_CNT_STRIDE 1
+#define TSU_HOST_ERR_CREDIT_CNT_DEPTH 1
+
+ /* LLQ debug counter. */
+#define TSU_HOST_LLQ_CNT_ADDR 0x00101258L
+#define TSU_HOST_LLQ_CNT_STRIDE 1
+#define TSU_HOST_LLQ_CNT_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_HOST_INT_STATUS_ADDR 0x00101259L
+#define TSU_HOST_INT_STATUS_STRIDE 1
+#define TSU_HOST_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_HOST_INT_MASK_ADDR 0x0010125aL
+#define TSU_HOST_INT_MASK_STRIDE 1
+#define TSU_HOST_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_HOST_INT_PRI_ADDR 0x0010125bL
+#define TSU_HOST_INT_PRI_STRIDE 1
+#define TSU_HOST_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_HOST_INT_STATUS_CLEAR_ADDR 0x0010125cL
+#define TSU_HOST_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_HOST_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_HOST_INT_STATUS_CLEAR_KICK_ADDR 0x0010125dL
+#define TSU_HOST_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_HOST_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /*
+ * Set when an MMU translation error occur for a write. This feeds into the
+ * interrupt status register.
+ */
+#define TSU_HOST_MMU_TRANSLATION_ERROR_ADDR 0x0010125eL
+#define TSU_HOST_MMU_TRANSLATION_ERROR_STRIDE 1
+#define TSU_HOST_MMU_TRANSLATION_ERROR_DEPTH 1
+
+ /* Used to clear bits in the mmu_translation_error register. */
+#define TSU_HOST_MMU_TRANSLATION_ERROR_CLEAR_ADDR 0x0010125fL
+#define TSU_HOST_MMU_TRANSLATION_ERROR_CLEAR_STRIDE 1
+#define TSU_HOST_MMU_TRANSLATION_ERROR_CLEAR_DEPTH 1
+
+ /* . This feeds into the interrupt status register. */
+#define TSU_HOST_ATOMIC_ERROR_ADDR 0x00101260L
+#define TSU_HOST_ATOMIC_ERROR_STRIDE 1
+#define TSU_HOST_ATOMIC_ERROR_DEPTH 1
+
+ /* Used to clear bits in the atomic_error register. */
+#define TSU_HOST_ATOMIC_ERROR_CLEAR_ADDR 0x00101261L
+#define TSU_HOST_ATOMIC_ERROR_CLEAR_STRIDE 1
+#define TSU_HOST_ATOMIC_ERROR_CLEAR_DEPTH 1
+
+ /*
+ * EPS address which caused the int_status.eps_address_invalid to get set.
+ */
+#define TSU_HOST_EPS_ADDRESS_ADDR 0x00101400L
+#define TSU_HOST_EPS_ADDRESS_STRIDE 1
+#define TSU_HOST_EPS_ADDRESS_DEPTH 2
+
+ /* ECC and Parity Errors status register. */
+#define TSU_HOST_ECC_ERRS_ADDR 0x00101440L
+#define TSU_HOST_ECC_ERRS_STRIDE 1
+#define TSU_HOST_ECC_ERRS_DEPTH 2
+
+ /* Setting tsu_host in memory Dynamic Reconfiguration. */
+#define TSU_HOST_DR_MODE_ADDR 0x00101442L
+#define TSU_HOST_DR_MODE_STRIDE 1
+#define TSU_HOST_DR_MODE_DEPTH 1
+
+ /* UF where memory Dynamic Reconfiguration is being performed. */
+#define TSU_HOST_RELOC_UF_ADDR 0x00101443L
+#define TSU_HOST_RELOC_UF_STRIDE 1
+#define TSU_HOST_RELOC_UF_DEPTH 1
+
+ /* Base address[51:12] where current data is being stored. */
+#define TSU_HOST_RELOC_BASE_ADDR 0x00101444L
+#define TSU_HOST_RELOC_BASE_STRIDE 1
+#define TSU_HOST_RELOC_BASE_DEPTH 1
+
+ /*
+ * relocation bound pointer[51:12] to enable translation for addresses
+ * between reloc_base and reloc_bound1.Stalls commands between reloc_bound1
+ * and reloc_bound2.
+ */
+#define TSU_HOST_RELOC_BOUND1_ADDR 0x00101445L
+#define TSU_HOST_RELOC_BOUND1_STRIDE 1
+#define TSU_HOST_RELOC_BOUND1_DEPTH 1
+
+ /*
+ * relocation bound pointer[51:12] to stall commands between reloc_bound1 and
+ * reloc_bound2.
+ */
+#define TSU_HOST_RELOC_BOUND2_ADDR 0x00101446L
+#define TSU_HOST_RELOC_BOUND2_STRIDE 1
+#define TSU_HOST_RELOC_BOUND2_DEPTH 1
+
+ /* Base address[51:12] where data is being relocated to when dr_mode is set. */
+#define TSU_HOST_RELOC_NEW_ADDR 0x00101447L
+#define TSU_HOST_RELOC_NEW_STRIDE 1
+#define TSU_HOST_RELOC_NEW_DEPTH 1
+
+ /*
+ * Page size enable bits[31:12].This is to set the corresponding bits in the
+ * address starting at address[12]. If all bits are zero the page size is
+ * 4KBytes. If all bits set page size is 4GBytes.
+ */
+#define TSU_HOST_PAGE_SIZE_BITS_ENBL_ADDR 0x00101448L
+#define TSU_HOST_PAGE_SIZE_BITS_ENBL_STRIDE 1
+#define TSU_HOST_PAGE_SIZE_BITS_ENBL_DEPTH 1
+
+ /* Provides information when a region is being stalled when dr_mode is set. */
+#define TSU_HOST_SEND_MESSAGE_ADDR 0x00101449L
+#define TSU_HOST_SEND_MESSAGE_STRIDE 1
+#define TSU_HOST_SEND_MESSAGE_DEPTH 1
+
+ /*
+ * This is the data sent when send_message is sent in the send_message
+ * completion command.
+ */
+#define TSU_HOST_RELOC_SEND_MSG_DATA_ADDR 0x0010144aL
+#define TSU_HOST_RELOC_SEND_MSG_DATA_STRIDE 1
+#define TSU_HOST_RELOC_SEND_MSG_DATA_DEPTH 4
+
+ /* This is the address where the send_message needs to go. */
+#define TSU_HOST_RELOC_SEND_MSG_ADD_ADDR 0x0010144eL
+#define TSU_HOST_RELOC_SEND_MSG_ADD_STRIDE 1
+#define TSU_HOST_RELOC_SEND_MSG_ADD_DEPTH 1
+
+ /*
+ * This is to use the same llq index in XIU for commands being sent to the
+ * relocation region.
+ */
+#define TSU_HOST_RELOC_XIU_INDEX_ADDR 0x0010144fL
+#define TSU_HOST_RELOC_XIU_INDEX_STRIDE 1
+#define TSU_HOST_RELOC_XIU_INDEX_DEPTH 1
+
+ /* This is to set the value for tph ns ro st. */
+#define TSU_HOST_PCIE_BITS_ADDR 0x00101450L
+#define TSU_HOST_PCIE_BITS_STRIDE 1
+#define TSU_HOST_PCIE_BITS_DEPTH 1
+
+ /* Configuration bits when putting the chip in sonoma mode. */
+#define TSU_HOST_SONOMA_CONFIG_ADDR 0x00101451L
+#define TSU_HOST_SONOMA_CONFIG_STRIDE 1
+#define TSU_HOST_SONOMA_CONFIG_DEPTH 1
+
+ /*
+ * Fatal Interrupt and Stop Mask register1b per source. stop-masks: 1=error
+ * does not cause host to stop processing) ECC, or CAM Parity error if
+ * enabled, will cause a fatal interrupt. Decide whether or not to stop all
+ * host processing when this error occurs.
+ */
+#define TSU_HOST_FATAL_INT_MASK_ADDR 0x00101480L
+#define TSU_HOST_FATAL_INT_MASK_STRIDE 1
+#define TSU_HOST_FATAL_INT_MASK_DEPTH 1
+
+ /* Received count per UF for completions and events. */
+#define TSU_HOST_EVENT_CQ_RECEIVED_ADDR 0x001014c0L
+#define TSU_HOST_EVENT_CQ_RECEIVED_STRIDE 1
+#define TSU_HOST_EVENT_CQ_RECEIVED_DEPTH 34
+
+ /* Interrupt Total Moderation */
+#define TSU_HOST_INT_CTRL_ADDR 0x00102000L
+#define TSU_HOST_INT_CTRL_STRIDE 1
+#define TSU_HOST_INT_CTRL_DEPTH 1
+
+ /* Interrupt Channel Control 0 */
+#define TSU_HOST_INT_CHAN_CTRL_0_ADDR 0x00102100L
+#define TSU_HOST_INT_CHAN_CTRL_0_STRIDE 1
+#define TSU_HOST_INT_CHAN_CTRL_0_DEPTH 128
+
+ /* Interrupt Channel Control 1 */
+#define TSU_HOST_INT_CHAN_CTRL_1_ADDR 0x00102180L
+#define TSU_HOST_INT_CHAN_CTRL_1_STRIDE 1
+#define TSU_HOST_INT_CHAN_CTRL_1_DEPTH 128
+
+ /* Interrupt Channel Control 2 */
+#define TSU_HOST_INT_CHAN_CTRL_2_ADDR 0x00102200L
+#define TSU_HOST_INT_CHAN_CTRL_2_STRIDE 1
+#define TSU_HOST_INT_CHAN_CTRL_2_DEPTH 128
+
+ /* MMU context per UF - containing the failing MMU context */
+#define TSU_HOST_MMU_TRANSLATION_ERROR_MMU_CONTEXT_ADDR 0x00104000L
+#define TSU_HOST_MMU_TRANSLATION_ERROR_MMU_CONTEXT_STRIDE 1
+#define TSU_HOST_MMU_TRANSLATION_ERROR_MMU_CONTEXT_DEPTH 34
+
+ /* Address per UF - containing the failing address. */
+#define TSU_HOST_MMU_TRANSLATION_ERROR_ADDRESS_ADDR 0x00104040L
+#define TSU_HOST_MMU_TRANSLATION_ERROR_ADDRESS_STRIDE 1
+#define TSU_HOST_MMU_TRANSLATION_ERROR_ADDRESS_DEPTH 34
+
+ /* MMU Static-Configuration and Status */
+#define TSU_MMU_MMU_CONFIG_ADDR 0x00200000L
+#define TSU_MMU_MMU_CONFIG_STRIDE 1
+#define TSU_MMU_MMU_CONFIG_DEPTH 1
+
+ /* MMU Credit Configuration */
+#define TSU_MMU_CREDIT_CONFIG_ADDR 0x00200001L
+#define TSU_MMU_CREDIT_CONFIG_STRIDE 1
+#define TSU_MMU_CREDIT_CONFIG_DEPTH 1
+
+ /* PA Address Size Configuration */
+#define TSU_MMU_PA_MASK_ADDR 0x00200002L
+#define TSU_MMU_PA_MASK_STRIDE 1
+#define TSU_MMU_PA_MASK_DEPTH 1
+
+ /* Flush MMU and-or PTW Caches. */
+#define TSU_MMU_FLUSH_CACHES_ADDR 0x00200003L
+#define TSU_MMU_FLUSH_CACHES_STRIDE 1
+#define TSU_MMU_FLUSH_CACHES_DEPTH 1
+
+ /* Statistic Counters. */
+#define TSU_MMU_STAT_COUNTERS_ADDR 0x00200004L
+#define TSU_MMU_STAT_COUNTERS_STRIDE 1
+#define TSU_MMU_STAT_COUNTERS_DEPTH 1
+
+ /* ECC and Parity Errors. */
+#define TSU_MMU_ECC_PARITY_ERRS_ADDR 0x00200008L
+#define TSU_MMU_ECC_PARITY_ERRS_STRIDE 1
+#define TSU_MMU_ECC_PARITY_ERRS_DEPTH 2
+
+ /*
+ * This register must be set and the kick register is written in order to
+ * start the operation.
+ */
+#define TSU_MMU_UF_CONTROL_ADDR 0x00200040L
+#define TSU_MMU_UF_CONTROL_STRIDE 1
+#define TSU_MMU_UF_CONTROL_DEPTH 1
+
+ /* Starts operation defined in uf_control. */
+#define TSU_MMU_UF_CONTROL_KICK_ADDR 0x00200041L
+#define TSU_MMU_UF_CONTROL_KICK_STRIDE 1
+#define TSU_MMU_UF_CONTROL_KICK_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_MMU_INT_STATUS_ADDR 0x00200042L
+#define TSU_MMU_INT_STATUS_STRIDE 1
+#define TSU_MMU_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_MMU_INT_MASK_ADDR 0x00200043L
+#define TSU_MMU_INT_MASK_STRIDE 1
+#define TSU_MMU_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_MMU_INT_PRI_ADDR 0x00200044L
+#define TSU_MMU_INT_PRI_STRIDE 1
+#define TSU_MMU_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_MMU_INT_STATUS_CLEAR_ADDR 0x00200045L
+#define TSU_MMU_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_MMU_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_MMU_INT_STATUS_CLEAR_KICK_ADDR 0x00200046L
+#define TSU_MMU_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_MMU_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /* Uncorrectable-Fatal Error Mask */
+#define TSU_MMU_UNCOR_ERR_MASK_ADDR 0x00200047L
+#define TSU_MMU_UNCOR_ERR_MASK_STRIDE 1
+#define TSU_MMU_UNCOR_ERR_MASK_DEPTH 1
+
+ /* MMU Cache VA Address Mask */
+#define TSU_MMU_MMUC_VA_MASK_ADDR 0x00200048L
+#define TSU_MMU_MMUC_VA_MASK_STRIDE 1
+#define TSU_MMU_MMUC_VA_MASK_DEPTH 1
+
+ /* tsu_mmu_llq Debug Signals */
+#define TSU_MMU_MMU_LLQ_MOD_DEBUG_ADDR 0x00200049L
+#define TSU_MMU_MMU_LLQ_MOD_DEBUG_STRIDE 1
+#define TSU_MMU_MMU_LLQ_MOD_DEBUG_DEPTH 1
+
+ /* tsu_mmu_cache Debug Signals */
+#define TSU_MMU_MMU_CACHE_MOD_DEBUG_ADDR 0x0020004aL
+#define TSU_MMU_MMU_CACHE_MOD_DEBUG_STRIDE 1
+#define TSU_MMU_MMU_CACHE_MOD_DEBUG_DEPTH 1
+
+ /* tsu_mmu_ptw Debug Signals */
+#define TSU_MMU_MMU_PTW_MOD_DEBUG_ADDR 0x0020004bL
+#define TSU_MMU_MMU_PTW_MOD_DEBUG_STRIDE 1
+#define TSU_MMU_MMU_PTW_MOD_DEBUG_DEPTH 1
+
+ /* Page Table Walk Error Debug State Reg0 */
+#define TSU_MMU_PTW_ERROR_DEBUG_REG0_ADDR 0x0020004cL
+#define TSU_MMU_PTW_ERROR_DEBUG_REG0_STRIDE 1
+#define TSU_MMU_PTW_ERROR_DEBUG_REG0_DEPTH 1
+
+ /* Page Table Walk Error Debug State Reg1 */
+#define TSU_MMU_PTW_ERROR_DEBUG_REG1_ADDR 0x0020004dL
+#define TSU_MMU_PTW_ERROR_DEBUG_REG1_STRIDE 1
+#define TSU_MMU_PTW_ERROR_DEBUG_REG1_DEPTH 1
+
+ /* Page Table Walk Error Debug State Reg2 */
+#define TSU_MMU_PTW_ERROR_DEBUG_REG2_ADDR 0x0020004eL
+#define TSU_MMU_PTW_ERROR_DEBUG_REG2_STRIDE 1
+#define TSU_MMU_PTW_ERROR_DEBUG_REG2_DEPTH 1
+
+ /* Clear the PTW debug error registers. */
+#define TSU_MMU_PTW_DEBUG_CLEAR_KICK_ADDR 0x0020004fL
+#define TSU_MMU_PTW_DEBUG_CLEAR_KICK_STRIDE 1
+#define TSU_MMU_PTW_DEBUG_CLEAR_KICK_DEPTH 1
+
+ /*
+ * TSU VL mapping table for requests. Inputs/addressing to this table are
+ * {UF, tsu_qosl (High/Low BAR), tsu_sl}.
+ */
+#define TSU_CBU_TVL_TABLE_ADDR 0x00300000L
+#define TSU_CBU_TVL_TABLE_STRIDE 1
+#define TSU_CBU_TVL_TABLE_DEPTH 1120
+
+ /*
+ * Below dcb_bar address is a write to the VCB, else write to the DCB.
+ * dcb_bar = 0 applies no VCB. Below this qosl_bar address is low BAR, else
+ * is high BAR. Inputs/addressing to this table is UF.
+ */
+#define TSU_CBU_SUB_BAR_ADDR_ADDR 0x00300800L
+#define TSU_CBU_SUB_BAR_ADDR_STRIDE 1
+#define TSU_CBU_SUB_BAR_ADDR_DEPTH 33
+
+ /*
+ * Virtual collect buffer start offset. VCB#=vcb_start_offset + pio
+ * address[25:12]. Inputs/addressing to this table is UF.
+ */
+#define TSU_CBU_VCB_START_OFFSET_ADDR 0x00300840L
+#define TSU_CBU_VCB_START_OFFSET_STRIDE 1
+#define TSU_CBU_VCB_START_OFFSET_DEPTH 33
+
+ /*
+ * How many physical collect buffers are allocated to the high BAR.
+ * Inputs/addressing to this table is UF.
+ */
+#define TSU_CBU_PCB_ALLOC_HIGH_ADDR 0x00300880L
+#define TSU_CBU_PCB_ALLOC_HIGH_STRIDE 1
+#define TSU_CBU_PCB_ALLOC_HIGH_DEPTH 33
+
+ /*
+ * How many physical collect buffers are allocated to the low BAR.
+ * Inputs/addressing to this table is UF.
+ */
+#define TSU_CBU_PCB_ALLOC_LOW_ADDR 0x003008c0L
+#define TSU_CBU_PCB_ALLOC_LOW_STRIDE 1
+#define TSU_CBU_PCB_ALLOC_LOW_DEPTH 33
+
+ /*
+ * How many physical collect buffers are available. Inputs/addressing to this
+ * table is UF.
+ */
+#define TSU_CBU_PCB_AVAILABLE_ADDR 0x00300900L
+#define TSU_CBU_PCB_AVAILABLE_STRIDE 1
+#define TSU_CBU_PCB_AVAILABLE_DEPTH 33
+
+ /*
+ * How many physical collect buffers are used in high BAR. Inputs/addressing
+ * to this table is UF.
+ */
+#define TSU_CBU_PCB_HIGH_USED_ADDR 0x00300940L
+#define TSU_CBU_PCB_HIGH_USED_STRIDE 1
+#define TSU_CBU_PCB_HIGH_USED_DEPTH 33
+
+ /*
+ * How many physical collect buffers are used in low BAR. Inputs/addressing
+ * to this table is UF.
+ */
+#define TSU_CBU_PCB_LOW_USED_ADDR 0x00300980L
+#define TSU_CBU_PCB_LOW_USED_STRIDE 1
+#define TSU_CBU_PCB_LOW_USED_DEPTH 33
+
+ /* scoreboard init. */
+#define TSU_CBU_SCBD_INIT_ADDR 0x003009c0L
+#define TSU_CBU_SCBD_INIT_STRIDE 1
+#define TSU_CBU_SCBD_INIT_DEPTH 1
+
+ /* scoreboard init done status. */
+#define TSU_CBU_SCBD_INIT_DONE_ADDR 0x003009c1L
+#define TSU_CBU_SCBD_INIT_DONE_STRIDE 1
+#define TSU_CBU_SCBD_INIT_DONE_DEPTH 1
+
+ /* Start offset of dedicated collect buffers number for the host driver. */
+#define TSU_CBU_DCB_START_OFFSET_HOST_ADDR 0x003009c2L
+#define TSU_CBU_DCB_START_OFFSET_HOST_STRIDE 1
+#define TSU_CBU_DCB_START_OFFSET_HOST_DEPTH 1
+
+ /* Start offset of dedicated collect buffers number for the eps. */
+#define TSU_CBU_DCB_START_OFFSET_EPS_ADDR 0x003009c3L
+#define TSU_CBU_DCB_START_OFFSET_EPS_STRIDE 1
+#define TSU_CBU_DCB_START_OFFSET_EPS_DEPTH 1
+
+ /*
+ * Start offset of dedicated collect buffers number for the send queue
+ * scheduler.
+ */
+#define TSU_CBU_DCB_START_OFFSET_SQS_ADDR 0x003009c4L
+#define TSU_CBU_DCB_START_OFFSET_SQS_STRIDE 1
+#define TSU_CBU_DCB_START_OFFSET_SQS_DEPTH 1
+
+ /* Collect length round up to 64B for scoreboard. */
+#define TSU_CBU_COLLECT_LEN_ROUNDUP_ADDR 0x003009c5L
+#define TSU_CBU_COLLECT_LEN_ROUNDUP_STRIDE 1
+#define TSU_CBU_COLLECT_LEN_ROUNDUP_DEPTH 1
+
+ /* ECC error control */
+#define TSU_CBU_ECC_ERR_CTRL_ADDR 0x003009c6L
+#define TSU_CBU_ECC_ERR_CTRL_STRIDE 1
+#define TSU_CBU_ECC_ERR_CTRL_DEPTH 1
+
+ /* ECC status */
+#define TSU_CBU_ECC_ERR_STATUS_ADDR 0x003009c7L
+#define TSU_CBU_ECC_ERR_STATUS_STRIDE 1
+#define TSU_CBU_ECC_ERR_STATUS_DEPTH 1
+
+ /* ECC status */
+#define TSU_CBU_ECC_ERR_STATUS_CLEAR_ADDR 0x003009c8L
+#define TSU_CBU_ECC_ERR_STATUS_CLEAR_STRIDE 1
+#define TSU_CBU_ECC_ERR_STATUS_CLEAR_DEPTH 1
+
+ /* Number of VCB checksum Error */
+#define TSU_CBU_NUM_VCB_CHECKSUM_ERR_ADDR 0x003009c9L
+#define TSU_CBU_NUM_VCB_CHECKSUM_ERR_STRIDE 1
+#define TSU_CBU_NUM_VCB_CHECKSUM_ERR_DEPTH 1
+
+ /* Number of VCB checksum Error */
+#define TSU_CBU_NUM_VCB_CHECKSUM_LOCKED_ADDR 0x003009caL
+#define TSU_CBU_NUM_VCB_CHECKSUM_LOCKED_STRIDE 1
+#define TSU_CBU_NUM_VCB_CHECKSUM_LOCKED_DEPTH 1
+
+ /* Number of VCB checksum Error */
+#define TSU_CBU_NUM_DCB_CHECKSUM_ERR_ADDR 0x003009cbL
+#define TSU_CBU_NUM_DCB_CHECKSUM_ERR_STRIDE 1
+#define TSU_CBU_NUM_DCB_CHECKSUM_ERR_DEPTH 1
+
+ /* Number of VCB checksum Error */
+#define TSU_CBU_NUM_DCB_CHECKSUM_LOCKED_ADDR 0x003009ccL
+#define TSU_CBU_NUM_DCB_CHECKSUM_LOCKED_STRIDE 1
+#define TSU_CBU_NUM_DCB_CHECKSUM_LOCKED_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_CBU_INT_STATUS_ADDR 0x003009cdL
+#define TSU_CBU_INT_STATUS_STRIDE 1
+#define TSU_CBU_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_CBU_INT_MASK_ADDR 0x003009ceL
+#define TSU_CBU_INT_MASK_STRIDE 1
+#define TSU_CBU_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_CBU_INT_PRI_ADDR 0x003009cfL
+#define TSU_CBU_INT_PRI_STRIDE 1
+#define TSU_CBU_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_CBU_INT_STATUS_CLEAR_ADDR 0x003009d0L
+#define TSU_CBU_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_CBU_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_CBU_INT_STATUS_CLEAR_KICK_ADDR 0x003009d1L
+#define TSU_CBU_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_CBU_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /* kick counter and dcb list ready for 64 to 69 */
+#define TSU_CBU_KICK_COUNTER_ADDR 0x003009d2L
+#define TSU_CBU_KICK_COUNTER_STRIDE 1
+#define TSU_CBU_KICK_COUNTER_DEPTH 1
+
+ /* dcb list ready for 0 to 63. */
+#define TSU_CBU_DCB_LIST_READY_ADDR 0x003009d3L
+#define TSU_CBU_DCB_LIST_READY_STRIDE 1
+#define TSU_CBU_DCB_LIST_READY_DEPTH 1
+
+ /* Per UF to drop PIO. Inputs/addressing to this table is UF. */
+#define TSU_CBU_CHOKE_ADDR 0x00300a00L
+#define TSU_CBU_CHOKE_STRIDE 1
+#define TSU_CBU_CHOKE_DEPTH 33
+
+ /* UF choke status. Inputs/addressing to this table is UF. */
+#define TSU_CBU_UF_STATUS_ADDR 0x00300a40L
+#define TSU_CBU_UF_STATUS_STRIDE 1
+#define TSU_CBU_UF_STATUS_DEPTH 33
+
+ /* PIO DCB start_offset. Inputs/addressing to this table is UF. */
+#define TSU_CBU_DCB_START_OFFSET_ADDR 0x00300b00L
+#define TSU_CBU_DCB_START_OFFSET_STRIDE 1
+#define TSU_CBU_DCB_START_OFFSET_DEPTH 33
+
+ /*
+ * Table to contain UF number for each DCB. EPS/Host drive has to write UF #
+ * to this table before it writes to the DCB. Inputs/addressing to this table
+ * is DCB#
+ */
+#define TSU_CBU_DCB_UF_TABLE_ADDR 0x00301000L
+#define TSU_CBU_DCB_UF_TABLE_STRIDE 1
+#define TSU_CBU_DCB_UF_TABLE_DEPTH 256
+
+ /*
+ * Status state of each DCB. The EPS/Host drive has to read this table to
+ * claim a DCB. Inputs/addressing to this table is DCB#
+ */
+#define TSU_CBU_DCB_STATUS_HW_LOCK_ADDR 0x00301100L
+#define TSU_CBU_DCB_STATUS_HW_LOCK_STRIDE 1
+#define TSU_CBU_DCB_STATUS_HW_LOCK_DEPTH 256
+
+ /* Status state of each DCB. Inputs/addressing to this table is DCB# */
+#define TSU_CBU_DCB_STATUS_ADDR 0x00301200L
+#define TSU_CBU_DCB_STATUS_STRIDE 1
+#define TSU_CBU_DCB_STATUS_DEPTH 256
+
+ /* dcb clear. Inputs/addressing to this table is scoreboard table. */
+#define TSU_CBU_DCB_CLEAR_ADDR 0x00301300L
+#define TSU_CBU_DCB_CLEAR_STRIDE 1
+#define TSU_CBU_DCB_CLEAR_DEPTH 256
+
+ /*
+ * DCB doorbell header/payload memory from EPS-C. Address[13:6] = DCB number
+ * and Address[5:0] = 8 bytes offset into the DCB.
+ */
+#define TSU_CBU_DCB_DOORBELL_ADDR 0x00304000L
+#define TSU_CBU_DCB_DOORBELL_STRIDE 1
+#define TSU_CBU_DCB_DOORBELL_DEPTH 16384
+
+ /*
+ * vcb clear. Inputs/addressing to this table is scoreboard table. Write to
+ * clear VCB, Read to get the scoreboard status
+ */
+#define TSU_CBU_VCB_CLEAR_ADDR 0x00308000L
+#define TSU_CBU_VCB_CLEAR_STRIDE 1
+#define TSU_CBU_VCB_CLEAR_DEPTH 16384
+
+ /*
+ * Initial completion credit per TVL. This is private credit for the
+ * particular TVL and can only be used by this TVL. The private completion
+ * credit indicates how many entries in tsu_cmpl are reserved for requests on
+ * this TVL.
+ */
+#define TSU_RQS_PRIVATE_CMPL_CREDIT_ADDR 0x00400000L
+#define TSU_RQS_PRIVATE_CMPL_CREDIT_STRIDE 1
+#define TSU_RQS_PRIVATE_CMPL_CREDIT_DEPTH 128
+
+ /*
+ * Current completion credits used per TVL. This is credit currently used by
+ * a particular TVL. This register is updated by hardware and can be read by
+ * software.
+ */
+#define TSU_RQS_TVL_CMPL_CREDIT_CONSUMED_ADDR 0x00400080L
+#define TSU_RQS_TVL_CMPL_CREDIT_CONSUMED_STRIDE 1
+#define TSU_RQS_TVL_CMPL_CREDIT_CONSUMED_DEPTH 128
+
+ /*
+ * Initial completion credit for the free pool. The free pool can be used by
+ * anyone being set up to use common credits. This is additional credits
+ * which can be used in addition to the private TVL completion credit. The
+ * common completion credit indicates how many entries in tsu_cmpl can be
+ * used by any TVL. It is a restriction that the TVL is set up to use common
+ * credit.
+ */
+#define TSU_RQS_COMMON_CMPL_CREDIT_ADDR 0x00400100L
+#define TSU_RQS_COMMON_CMPL_CREDIT_STRIDE 1
+#define TSU_RQS_COMMON_CMPL_CREDIT_DEPTH 1
+
+ /*
+ * This is register contain the number of currently consumed common
+ * completion credits. This register is updated by hardware and can be read
+ * from software.
+ */
+#define TSU_RQS_COMMON_CMPL_CREDIT_CONSUMED_ADDR 0x00400101L
+#define TSU_RQS_COMMON_CMPL_CREDIT_CONSUMED_STRIDE 1
+#define TSU_RQS_COMMON_CMPL_CREDIT_CONSUMED_DEPTH 1
+
+#define TSU_RQS_COMMON_CMPL_CREDIT_ENABLE_0_ADDR 0x00400102L
+#define TSU_RQS_COMMON_CMPL_CREDIT_ENABLE_0_STRIDE 2
+#define TSU_RQS_COMMON_CMPL_CREDIT_ENABLE_0_DEPTH 1
+
+#define TSU_RQS_COMMON_CMPL_CREDIT_ENABLE_1_ADDR 0x00400103L
+#define TSU_RQS_COMMON_CMPL_CREDIT_ENABLE_1_STRIDE 2
+#define TSU_RQS_COMMON_CMPL_CREDIT_ENABLE_1_DEPTH 1
+
+ /*
+ * Initial execution credit per TVL. This is private credit for the
+ * particular TVL and can only be used by this TVL. The credit indicates how
+ * many DMA contexts are reserved for this particular TVL
+ */
+#define TSU_RQS_PRIVATE_EXEC_CREDIT_ADDR 0x00400200L
+#define TSU_RQS_PRIVATE_EXEC_CREDIT_STRIDE 1
+#define TSU_RQS_PRIVATE_EXEC_CREDIT_DEPTH 128
+
+ /*
+ * Current execution credit used per TVL. This is credit used by a particular
+ * TVL. This register is updated by hardware and can be read by software.
+ */
+#define TSU_RQS_TVL_EXEC_CREDIT_CONSUMED_ADDR 0x00400280L
+#define TSU_RQS_TVL_EXEC_CREDIT_CONSUMED_STRIDE 1
+#define TSU_RQS_TVL_EXEC_CREDIT_CONSUMED_DEPTH 128
+
+ /*
+ * Initial execution credit for the free pool. The free pool can be used by
+ * anyone being set up to use common credits. This is additional credits
+ * which can be used in addition to the private TVL execution credit. The
+ * common execution credit indicates how many DMA contexts can be used by any
+ * TVL. It is a restriction that the TVL is set up to use common credit.
+ */
+#define TSU_RQS_COMMON_EXEC_CREDIT_ADDR 0x00400300L
+#define TSU_RQS_COMMON_EXEC_CREDIT_STRIDE 1
+#define TSU_RQS_COMMON_EXEC_CREDIT_DEPTH 1
+
+ /*
+ * This register contain the number of currently consumed common execution
+ * credits. The register is updated by hardware and can be read from
+ * software.
+ */
+#define TSU_RQS_COMMON_EXEC_CREDIT_CONSUMED_ADDR 0x00400301L
+#define TSU_RQS_COMMON_EXEC_CREDIT_CONSUMED_STRIDE 1
+#define TSU_RQS_COMMON_EXEC_CREDIT_CONSUMED_DEPTH 1
+
+#define TSU_RQS_COMMON_EXEC_CREDIT_ENABLE_0_ADDR 0x00400302L
+#define TSU_RQS_COMMON_EXEC_CREDIT_ENABLE_0_STRIDE 2
+#define TSU_RQS_COMMON_EXEC_CREDIT_ENABLE_0_DEPTH 1
+
+#define TSU_RQS_COMMON_EXEC_CREDIT_ENABLE_1_ADDR 0x00400303L
+#define TSU_RQS_COMMON_EXEC_CREDIT_ENABLE_1_STRIDE 2
+#define TSU_RQS_COMMON_EXEC_CREDIT_ENABLE_1_DEPTH 1
+
+ /*
+ * Port1 SL to VL mapping tables. One entry in this table is the SL to VL
+ * mapping table for one UF.
+ */
+#define TSU_RQS_P1_SL2VL_ADDR 0x00400400L
+#define TSU_RQS_P1_SL2VL_STRIDE 1
+#define TSU_RQS_P1_SL2VL_DEPTH 34
+
+ /*
+ * Port2 SL to VL mapping tables. There is one table per UF. The table is
+ * implemented as one register.
+ */
+#define TSU_RQS_P2_SL2VL_ADDR 0x00400440L
+#define TSU_RQS_P2_SL2VL_STRIDE 1
+#define TSU_RQS_P2_SL2VL_DEPTH 34
+
+ /*
+ * Jumbo frame enabled CSR. One register for the device indicating if jumbo
+ * frames are allowed or not.
+ */
+#define TSU_RQS_JUMBO_FRAME_ENABLED_ADDR 0x00400600L
+#define TSU_RQS_JUMBO_FRAME_ENABLED_STRIDE 1
+#define TSU_RQS_JUMBO_FRAME_ENABLED_DEPTH 1
+
+ /*
+ * Own LIDs base and LMC. Potentially all own LID bits come from the QP state
+ * entry. The number of bits to use is based on the LMC. Per UF register.
+ */
+#define TSU_RQS_P1_OWN_LID_BASE_ADDR 0x00400800L
+#define TSU_RQS_P1_OWN_LID_BASE_STRIDE 1
+#define TSU_RQS_P1_OWN_LID_BASE_DEPTH 34
+
+ /*
+ * Own LIDs base and LMC. Potentially all own LID bits come from the QP state
+ * entry. The number of bits to use is based on the LMC. Per UF register.
+ */
+#define TSU_RQS_P2_OWN_LID_BASE_ADDR 0x00400840L
+#define TSU_RQS_P2_OWN_LID_BASE_STRIDE 1
+#define TSU_RQS_P2_OWN_LID_BASE_DEPTH 34
+
+ /*
+ * Port1 enable bits per UF. If bit is set, the corresponding GID and LID
+ * table entries are valid.
+ */
+#define TSU_RQS_P1_PORT_ENABLE_ADDR 0x00400880L
+#define TSU_RQS_P1_PORT_ENABLE_STRIDE 1
+#define TSU_RQS_P1_PORT_ENABLE_DEPTH 1
+
+ /*
+ * Port2 enable bits per UF. If bit is set, the corresponding GID and LID
+ * table entries are valid.
+ */
+#define TSU_RQS_P2_PORT_ENABLE_ADDR 0x00400881L
+#define TSU_RQS_P2_PORT_ENABLE_STRIDE 1
+#define TSU_RQS_P2_PORT_ENABLE_DEPTH 1
+
+ /*
+ * Register with a bit per UF/VHCA indicating if the UF/VHCA is allowed to
+ * send SMPs.
+ */
+#define TSU_RQS_P1_SMP_ALLOWED_ADDR 0x00400882L
+#define TSU_RQS_P1_SMP_ALLOWED_STRIDE 1
+#define TSU_RQS_P1_SMP_ALLOWED_DEPTH 1
+
+ /*
+ * Register with a bit per UF/VHCA indicating if the UF/VHCA is allowed to
+ * send SMPs.
+ */
+#define TSU_RQS_P2_SMP_ALLOWED_ADDR 0x00400883L
+#define TSU_RQS_P2_SMP_ALLOWED_STRIDE 1
+#define TSU_RQS_P2_SMP_ALLOWED_DEPTH 1
+
+ /* Kick FIFO entries in use per UF */
+#define TSU_RQS_KICK_FIFO_UF_INUSE_ADDR 0x00400884L
+#define TSU_RQS_KICK_FIFO_UF_INUSE_STRIDE 1
+#define TSU_RQS_KICK_FIFO_UF_INUSE_DEPTH 34
+
+ /* Base Q-Key for EoIB range of Q-Keys. */
+#define TSU_RQS_EOIB_QKEY_BASE_ADDR 0x004008c4L
+#define TSU_RQS_EOIB_QKEY_BASE_STRIDE 1
+#define TSU_RQS_EOIB_QKEY_BASE_DEPTH 1
+
+ /* Mask Q-Key for EoIB range of Q-Keys. */
+#define TSU_RQS_EOIB_QKEY_MASK_ADDR 0x004008c5L
+#define TSU_RQS_EOIB_QKEY_MASK_STRIDE 1
+#define TSU_RQS_EOIB_QKEY_MASK_DEPTH 1
+
+ /* Q-Key used for IPoIB. */
+#define TSU_RQS_IPOIB_QKEY_BASE_ADDR 0x004008c6L
+#define TSU_RQS_IPOIB_QKEY_BASE_STRIDE 1
+#define TSU_RQS_IPOIB_QKEY_BASE_DEPTH 1
+
+ /* Range select register - defining the start bit for Q-Key (N+3:N). */
+#define TSU_RQS_QKEY_RANGE_SELECT_ADDR 0x004008c7L
+#define TSU_RQS_QKEY_RANGE_SELECT_STRIDE 1
+#define TSU_RQS_QKEY_RANGE_SELECT_DEPTH 1
+
+ /* Per UF EoIB enforcement definitions. */
+#define TSU_RQS_EOIB_ENFORCEMENT_ALLOWED_ADDR 0x00400a00L
+#define TSU_RQS_EOIB_ENFORCEMENT_ALLOWED_STRIDE 1
+#define TSU_RQS_EOIB_ENFORCEMENT_ALLOWED_DEPTH 34
+
+ /*
+ * 16 entries per UF. The table is addressed with {UF, index}. There are four
+ * entries per table entry. Because of a bug, each vNIC table entry could not
+ * be defined as a struct, but it could be cast to
+ * psif_verbs_pk::vnic_table_entry_t.
+ */
+#define TSU_RQS_VNIC_TABLE_ADDR 0x00400c00L
+#define TSU_RQS_VNIC_TABLE_STRIDE 1
+#define TSU_RQS_VNIC_TABLE_DEPTH 136
+
+ /*
+ * GID forwarding table. The forwarding table is used to figure out if a
+ * packet should be sent in loopback or not. There are (2 * NUM_VHCA + 1) 67
+ * GIDs per physical IB port.
+ */
+#define TSU_RQS_P1_GID_FORWARDING_TABLE_ADDR 0x00402000L
+#define TSU_RQS_P1_GID_FORWARDING_TABLE_STRIDE 1
+#define TSU_RQS_P1_GID_FORWARDING_TABLE_DEPTH 67
+
+ /*
+ * GID forwarding table. The forwarding table is used to figure out if a
+ * packet should be sent in loopback or not. There are (2 * NUM_VHCA + 1) 67
+ * GIDs per physical IB port.
+ */
+#define TSU_RQS_P2_GID_FORWARDING_TABLE_ADDR 0x00402400L
+#define TSU_RQS_P2_GID_FORWARDING_TABLE_STRIDE 1
+#define TSU_RQS_P2_GID_FORWARDING_TABLE_DEPTH 67
+
+ /*
+ * Per VL register (0-7: Port 0 VL0-7, 8: Port 0 VL15, 9: Port0 loopback.
+ * 10-19: Port 1). Maximum global buffer a particular VL can get.
+ */
+#define TSU_DMA_MAX_ALLOC_VL_BUFF_ADDR 0x00500000L
+#define TSU_DMA_MAX_ALLOC_VL_BUFF_STRIDE 1
+#define TSU_DMA_MAX_ALLOC_VL_BUFF_DEPTH 20
+
+ /*
+ * Per VL register (0-7: Port0 VL0-7, 8: Port0 VL15, 9: Port0 loopback.
+ * 10-19: Port 1). The amount of buffer dedicated to this VL.
+ */
+#define TSU_DMA_PRIVATE_VL_BUFF_ADDR 0x00500020L
+#define TSU_DMA_PRIVATE_VL_BUFF_STRIDE 1
+#define TSU_DMA_PRIVATE_VL_BUFF_DEPTH 20
+
+ /*
+ * Per VL register (0-7: Port0 VL0-7, 8: Port0 VL15, 9: Port0 loopback.
+ * 10-19: Port 1). The amount of dedicated and global buffer used to this VL.
+ */
+#define TSU_DMA_VL_BUFF_USED_ADDR 0x00500040L
+#define TSU_DMA_VL_BUFF_USED_STRIDE 1
+#define TSU_DMA_VL_BUFF_USED_DEPTH 20
+
+ /* Amount of global buffer used shared among all VLs. */
+#define TSU_DMA_GLOBAL_BUFF_USED_ADDR 0x00500054L
+#define TSU_DMA_GLOBAL_BUFF_USED_STRIDE 1
+#define TSU_DMA_GLOBAL_BUFF_USED_DEPTH 1
+
+ /* Num of 256B block DMA buffer check-out */
+#define TSU_DMA_NUM_OF_BUF_CO_ADDR 0x00500055L
+#define TSU_DMA_NUM_OF_BUF_CO_STRIDE 1
+#define TSU_DMA_NUM_OF_BUF_CO_DEPTH 1
+
+ /* Num of 256B block DMA buffer check-in */
+#define TSU_DMA_NUM_OF_BUF_CI_ADDR 0x00500056L
+#define TSU_DMA_NUM_OF_BUF_CI_STRIDE 1
+#define TSU_DMA_NUM_OF_BUF_CI_DEPTH 1
+
+ /* Number of RQS command to DMA */
+#define TSU_DMA_NUM_OF_CNTXTLLQ_INBUN_ADDR 0x00500057L
+#define TSU_DMA_NUM_OF_CNTXTLLQ_INBUN_STRIDE 1
+#define TSU_DMA_NUM_OF_CNTXTLLQ_INBUN_DEPTH 1
+
+ /* Number of Context LLQ pop */
+#define TSU_DMA_NUM_OF_CNTXTLLQ_POP_ADDR 0x00500058L
+#define TSU_DMA_NUM_OF_CNTXTLLQ_POP_STRIDE 1
+#define TSU_DMA_NUM_OF_CNTXTLLQ_POP_DEPTH 1
+
+ /* Number of Context LLQ ready to go set */
+#define TSU_DMA_NUM_OF_CNTXTLLQ_R2G_ADDR 0x00500059L
+#define TSU_DMA_NUM_OF_CNTXTLLQ_R2G_STRIDE 1
+#define TSU_DMA_NUM_OF_CNTXTLLQ_R2G_DEPTH 1
+
+ /* Number of IBPB command from DMA */
+#define TSU_DMA_NUM_OF_IBPB_CMD_ADDR 0x0050005aL
+#define TSU_DMA_NUM_OF_IBPB_CMD_STRIDE 1
+#define TSU_DMA_NUM_OF_IBPB_CMD_DEPTH 1
+
+ /* Number of CMPL command from DMA */
+#define TSU_DMA_NUM_OF_CMPL_CMD_ADDR 0x0050005bL
+#define TSU_DMA_NUM_OF_CMPL_CMD_STRIDE 1
+#define TSU_DMA_NUM_OF_CMPL_CMD_DEPTH 1
+
+ /* Number of QPS RD command from DMA */
+#define TSU_DMA_NUM_OF_QPS_RD_CMD_ADDR 0x0050005cL
+#define TSU_DMA_NUM_OF_QPS_RD_CMD_STRIDE 1
+#define TSU_DMA_NUM_OF_QPS_RD_CMD_DEPTH 1
+
+ /* Number of QPS RD response from QPS */
+#define TSU_DMA_NUM_OF_QPS_RD_RSP_ADDR 0x0050005dL
+#define TSU_DMA_NUM_OF_QPS_RD_RSP_STRIDE 1
+#define TSU_DMA_NUM_OF_QPS_RD_RSP_DEPTH 1
+
+ /* Number of QPS WR command from DMA */
+#define TSU_DMA_NUM_OF_QPS_WR_CMD_ADDR 0x0050005eL
+#define TSU_DMA_NUM_OF_QPS_WR_CMD_STRIDE 1
+#define TSU_DMA_NUM_OF_QPS_WR_CMD_DEPTH 1
+
+ /* Number of QPS WR response from QPS */
+#define TSU_DMA_NUM_OF_QPS_WR_RSP_ADDR 0x0050005fL
+#define TSU_DMA_NUM_OF_QPS_WR_RSP_STRIDE 1
+#define TSU_DMA_NUM_OF_QPS_WR_RSP_DEPTH 1
+
+ /* Number of packet in the packet LLQ */
+#define TSU_DMA_NUM_OF_PKTLLQ_INBUN_ADDR 0x00500060L
+#define TSU_DMA_NUM_OF_PKTLLQ_INBUN_STRIDE 1
+#define TSU_DMA_NUM_OF_PKTLLQ_INBUN_DEPTH 1
+
+ /* Number of Packet LLQ pop */
+#define TSU_DMA_NUM_OF_PKTLLQ_POP_ADDR 0x00500061L
+#define TSU_DMA_NUM_OF_PKTLLQ_POP_STRIDE 1
+#define TSU_DMA_NUM_OF_PKTLLQ_POP_DEPTH 1
+
+ /* Number of Packet LLQ ready to go set */
+#define TSU_DMA_NUM_OF_PKTLLQ_R2G_ADDR 0x00500062L
+#define TSU_DMA_NUM_OF_PKTLLQ_R2G_STRIDE 1
+#define TSU_DMA_NUM_OF_PKTLLQ_R2G_DEPTH 1
+
+ /* Num of payload DMA command */
+#define TSU_DMA_NUM_OF_PYLD_CMD_ADDR 0x00500063L
+#define TSU_DMA_NUM_OF_PYLD_CMD_STRIDE 1
+#define TSU_DMA_NUM_OF_PYLD_CMD_DEPTH 1
+
+ /* Num of payload DMA response */
+#define TSU_DMA_NUM_OF_PYLD_RSP_ADDR 0x00500064L
+#define TSU_DMA_NUM_OF_PYLD_RSP_STRIDE 1
+#define TSU_DMA_NUM_OF_PYLD_RSP_DEPTH 1
+
+ /* Num of sge DMA command */
+#define TSU_DMA_NUM_OF_SGE_CMD_ADDR 0x00500065L
+#define TSU_DMA_NUM_OF_SGE_CMD_STRIDE 1
+#define TSU_DMA_NUM_OF_SGE_CMD_DEPTH 1
+
+ /* Num of sge DMA response */
+#define TSU_DMA_NUM_OF_SGE_RSP_ADDR 0x00500066L
+#define TSU_DMA_NUM_OF_SGE_RSP_STRIDE 1
+#define TSU_DMA_NUM_OF_SGE_RSP_DEPTH 1
+
+ /* Num of LSO buffer used */
+#define TSU_DMA_LSO_BUF_USED_ADDR 0x00500067L
+#define TSU_DMA_LSO_BUF_USED_STRIDE 1
+#define TSU_DMA_LSO_BUF_USED_DEPTH 1
+
+ /* ECC error control */
+#define TSU_DMA_ECC_ERR_CTRL_ADDR 0x00500068L
+#define TSU_DMA_ECC_ERR_CTRL_STRIDE 1
+#define TSU_DMA_ECC_ERR_CTRL_DEPTH 1
+
+ /* ECC status */
+#define TSU_DMA_ECC_ERR_STATUS_ADDR 0x00500069L
+#define TSU_DMA_ECC_ERR_STATUS_STRIDE 1
+#define TSU_DMA_ECC_ERR_STATUS_DEPTH 1
+
+ /* ECC status */
+#define TSU_DMA_ECC_ERR_STATUS_CLEAR_ADDR 0x0050006aL
+#define TSU_DMA_ECC_ERR_STATUS_CLEAR_STRIDE 1
+#define TSU_DMA_ECC_ERR_STATUS_CLEAR_DEPTH 1
+
+ /* Num of 32B IB header size to be calculated in SR */
+#define TSU_DMA_SR_IB_HEADER_SIZE_ADDR 0x0050006bL
+#define TSU_DMA_SR_IB_HEADER_SIZE_STRIDE 1
+#define TSU_DMA_SR_IB_HEADER_SIZE_DEPTH 1
+
+ /*
+ * Timer scale for congestion control and static rate: 12 bits interval
+ * counter 8.192us, 18 bits wrap counter
+ */
+#define TSU_DMA_TIMER_SCALE_ADDR 0x0050006cL
+#define TSU_DMA_TIMER_SCALE_STRIDE 1
+#define TSU_DMA_TIMER_SCALE_DEPTH 1
+
+ /*
+ * IB link speed per port. 0=EDR, 1=QDR, 2=DDR, 3=SDR. 4=FDR Address to the
+ * Register Table: {uf, port}
+ */
+#define TSU_DMA_LINK_SPEED_ADDR 0x00500080L
+#define TSU_DMA_LINK_SPEED_STRIDE 1
+#define TSU_DMA_LINK_SPEED_DEPTH 70
+
+ /*
+ * IB link width per port. 0=X4 and 1=X1. Address to the Register Table: {uf,
+ * port}
+ */
+#define TSU_DMA_LINK_WIDTH_ADDR 0x00500100L
+#define TSU_DMA_LINK_WIDTH_STRIDE 1
+#define TSU_DMA_LINK_WIDTH_DEPTH 70
+
+ /*
+ * Maximum number of payload read 256B buffer per UF. Address to the Register
+ * Table:uf
+ */
+#define TSU_DMA_UF_TRANS_MAX_ADDR 0x00500180L
+#define TSU_DMA_UF_TRANS_MAX_STRIDE 1
+#define TSU_DMA_UF_TRANS_MAX_DEPTH 35
+
+ /* Number of payload read transaction per UF. Address to the Register Table:uf */
+#define TSU_DMA_UF_TRANS_USED_ADDR 0x005001c0L
+#define TSU_DMA_UF_TRANS_USED_STRIDE 1
+#define TSU_DMA_UF_TRANS_USED_DEPTH 35
+
+ /* MAC control per port per UF 0-33. Address to the Register Table: {uf port} */
+#define TSU_DMA_MAC_CTRL_ADDR 0x00500600L
+#define TSU_DMA_MAC_CTRL_STRIDE 1
+#define TSU_DMA_MAC_CTRL_DEPTH 68
+
+ /* Size of the EoIB and IPoIB header */
+#define TSU_DMA_PPTY_HDR_LENGTH_ADDR 0x00500680L
+#define TSU_DMA_PPTY_HDR_LENGTH_STRIDE 1
+#define TSU_DMA_PPTY_HDR_LENGTH_DEPTH 1
+
+ /* Mask bit to the TCP flags for the LSO segments */
+#define TSU_DMA_TCP_FLAGS_MASK_ADDR 0x00500682L
+#define TSU_DMA_TCP_FLAGS_MASK_STRIDE 1
+#define TSU_DMA_TCP_FLAGS_MASK_DEPTH 1
+
+ /* Control for ip checksum tcp checksum udp checksum and ethernet padding */
+#define TSU_DMA_OFFLOAD_CTRL_ADDR 0x00500683L
+#define TSU_DMA_OFFLOAD_CTRL_STRIDE 1
+#define TSU_DMA_OFFLOAD_CTRL_DEPTH 1
+
+ /* This register is defined as JUMBO MTU allowed to transmit when MTU_10240B */
+#define TSU_DMA_JUMBO_MTU_ADDR 0x00500684L
+#define TSU_DMA_JUMBO_MTU_STRIDE 1
+#define TSU_DMA_JUMBO_MTU_DEPTH 1
+
+ /*
+ * VLAN membership table per UF 0-33. Inputs/addressing to this table is {UF,
+ * vid[11:6}}.
+ */
+#define TSU_DMA_VLAN_MEMBER_TABLE_ADDR 0x00501000L
+#define TSU_DMA_VLAN_MEMBER_TABLE_STRIDE 1
+#define TSU_DMA_VLAN_MEMBER_TABLE_DEPTH 2176
+
+ /* Outer VLAN Ethernet type */
+#define TSU_DMA_OUTER_VLAN_TYPE_ADDR 0x00502000L
+#define TSU_DMA_OUTER_VLAN_TYPE_STRIDE 1
+#define TSU_DMA_OUTER_VLAN_TYPE_DEPTH 34
+
+ /* Outer VLAN Ethernet type */
+#define TSU_DMA_INNER_VLAN_TYPE_ADDR 0x00502040L
+#define TSU_DMA_INNER_VLAN_TYPE_STRIDE 1
+#define TSU_DMA_INNER_VLAN_TYPE_DEPTH 34
+
+ /*
+ * Q key enforcement VNIC VID table for uf 0-33. Inputs/addressing to this
+ * table are {UF, index}.
+ */
+#define TSU_DMA_VNIC_VID_TABLE_ADDR 0x00502400L
+#define TSU_DMA_VNIC_VID_TABLE_STRIDE 1
+#define TSU_DMA_VNIC_VID_TABLE_DEPTH 544
+
+ /*
+ * Q key enforcement MAC address for uf 0-33. Inputs/addressing to this table
+ * are {UF, index}.
+ */
+#define TSU_DMA_VNIC_MAC_ADDR_TABLE_ADDR 0x00502800L
+#define TSU_DMA_VNIC_MAC_ADDR_TABLE_STRIDE 1
+#define TSU_DMA_VNIC_MAC_ADDR_TABLE_DEPTH 544
+
+ /*
+ * Q key table - Inputs/addressing to this table are {UF, index}. There are
+ * 16 entries per UF.
+ */
+#define TSU_DMA_QKEY_TABLE_ADDR 0x00502c00L
+#define TSU_DMA_QKEY_TABLE_STRIDE 1
+#define TSU_DMA_QKEY_TABLE_DEPTH 544
+
+ /*
+ * Congestion control DLID CAM table. Inputs/addressing to this table are
+ * {port, CAM entry number}.
+ */
+#define TSU_DMA_CC_DLID_TABLE_ADDR 0x00503000L
+#define TSU_DMA_CC_DLID_TABLE_STRIDE 1
+#define TSU_DMA_CC_DLID_TABLE_DEPTH 64
+
+ /*
+ * Shared P-Key table for all UFs on this port. Number of entries valid per
+ * UF is defined by the p1_pkey_uf_stride register.
+ */
+#define TSU_IBPB_P1_PKEY_TABLE_ADDR 0x00600000L
+#define TSU_IBPB_P1_PKEY_TABLE_STRIDE 1
+#define TSU_IBPB_P1_PKEY_TABLE_DEPTH 272
+
+ /*
+ * Upper 64 bits of GID for port1. There are (2 * NUM_VHCA + 1) 67 GIDs per
+ * physical IB port.
+ */
+#define TSU_IBPB_P1_GID_UPPER_ADDR 0x00600200L
+#define TSU_IBPB_P1_GID_UPPER_STRIDE 1
+#define TSU_IBPB_P1_GID_UPPER_DEPTH 67
+
+ /*
+ * Lower 64 bits of GID for port1. There are (2 * NUM_VHCA + 1) 67 GIDs per
+ * physical IB port.
+ */
+#define TSU_IBPB_P1_GID_LOWER_ADDR 0x00600300L
+#define TSU_IBPB_P1_GID_LOWER_STRIDE 1
+#define TSU_IBPB_P1_GID_LOWER_DEPTH 67
+
+ /*
+ * Own LIDs base and LMC. Potentially all own LID bits come from the QP state
+ * entry. The number of bits to use is based on the LMC. Per UF register.
+ */
+#define TSU_IBPB_P1_OWN_LID_BASE_ADDR 0x00600400L
+#define TSU_IBPB_P1_OWN_LID_BASE_STRIDE 1
+#define TSU_IBPB_P1_OWN_LID_BASE_DEPTH 34
+
+ /*
+ * Size of individual P-Key tables per UF. All UFs have the same size or if
+ * set to 0, it means one common table.
+ */
+#define TSU_IBPB_P1_PKEY_UF_STRIDE_ADDR 0x00600440L
+#define TSU_IBPB_P1_PKEY_UF_STRIDE_STRIDE 1
+#define TSU_IBPB_P1_PKEY_UF_STRIDE_DEPTH 1
+
+ /*
+ * Shared P-Key table for all UFs on this port. Number of entries valid per
+ * UF is defined by the p2_pkey_uf_stride register.
+ */
+#define TSU_IBPB_P2_PKEY_TABLE_ADDR 0x00600800L
+#define TSU_IBPB_P2_PKEY_TABLE_STRIDE 1
+#define TSU_IBPB_P2_PKEY_TABLE_DEPTH 272
+
+ /*
+ * Upper 64 bits of GID for port2. There are (2 * NUM_VHCA + 1) 67 GIDs per
+ * physical IB port.
+ */
+#define TSU_IBPB_P2_GID_UPPER_ADDR 0x00600a00L
+#define TSU_IBPB_P2_GID_UPPER_STRIDE 1
+#define TSU_IBPB_P2_GID_UPPER_DEPTH 67
+
+ /* Lower 64 bits of GID for port2. The table is per UF. */
+#define TSU_IBPB_P2_GID_LOWER_ADDR 0x00600b00L
+#define TSU_IBPB_P2_GID_LOWER_STRIDE 1
+#define TSU_IBPB_P2_GID_LOWER_DEPTH 67
+
+ /*
+ * Own LIDs base and LMC. Potentially all own LID bits come from the QP state
+ * entry. The number of bits to use is based on the LMC. Per UF register.
+ */
+#define TSU_IBPB_P2_OWN_LID_BASE_ADDR 0x00600c00L
+#define TSU_IBPB_P2_OWN_LID_BASE_STRIDE 1
+#define TSU_IBPB_P2_OWN_LID_BASE_DEPTH 34
+
+ /*
+ * Size of individual P-Key tables per UF. All UFs have the same size or if
+ * set to 0, it means one common table.
+ */
+#define TSU_IBPB_P2_PKEY_UF_STRIDE_ADDR 0x00600c40L
+#define TSU_IBPB_P2_PKEY_UF_STRIDE_STRIDE 1
+#define TSU_IBPB_P2_PKEY_UF_STRIDE_DEPTH 1
+
+ /* Mask of fatal error stall input */
+#define TSU_IBPB_MASK_CRB_IBPB_FATAL_ERR_STALL_ADDR 0x00600cc0L
+#define TSU_IBPB_MASK_CRB_IBPB_FATAL_ERR_STALL_STRIDE 1
+#define TSU_IBPB_MASK_CRB_IBPB_FATAL_ERR_STALL_DEPTH 1
+
+ /* Misc IBPB debug signals */
+#define TSU_IBPB_IBPB_DEBUG_ADDR 0x00600d40L
+#define TSU_IBPB_IBPB_DEBUG_STRIDE 1
+#define TSU_IBPB_IBPB_DEBUG_DEPTH 1
+
+#define TSU_QPS_AHA_BASE_ADDR_0_ADDR 0x00700000L
+#define TSU_QPS_AHA_BASE_ADDR_0_STRIDE 1
+#define TSU_QPS_AHA_BASE_ADDR_0_DEPTH 34
+
+#define TSU_QPS_AHA_BASE_ADDR_1_ADDR 0x00700040L
+#define TSU_QPS_AHA_BASE_ADDR_1_STRIDE 1
+#define TSU_QPS_AHA_BASE_ADDR_1_DEPTH 34
+
+#define TSU_QPS_AHA_BASE_ADDR_2_ADDR 0x00700080L
+#define TSU_QPS_AHA_BASE_ADDR_2_STRIDE 1
+#define TSU_QPS_AHA_BASE_ADDR_2_DEPTH 34
+
+#define TSU_QPS_QP_BASE_ADDR_0_ADDR 0x00700100L
+#define TSU_QPS_QP_BASE_ADDR_0_STRIDE 1
+#define TSU_QPS_QP_BASE_ADDR_0_DEPTH 34
+
+#define TSU_QPS_QP_BASE_ADDR_1_ADDR 0x00700140L
+#define TSU_QPS_QP_BASE_ADDR_1_STRIDE 1
+#define TSU_QPS_QP_BASE_ADDR_1_DEPTH 34
+
+#define TSU_QPS_QP_BASE_ADDR_2_ADDR 0x00700180L
+#define TSU_QPS_QP_BASE_ADDR_2_STRIDE 1
+#define TSU_QPS_QP_BASE_ADDR_2_DEPTH 34
+
+ /*
+ * This register must be set and the kick register is written in order to
+ * start the UF invalidate operation.
+ */
+#define TSU_QPS_UF_CONTROL_ADDR 0x00700200L
+#define TSU_QPS_UF_CONTROL_STRIDE 1
+#define TSU_QPS_UF_CONTROL_DEPTH 1
+
+ /*
+ * Starts operation defined in uf_control. Now only UF invalidate is
+ * supported.
+ */
+#define TSU_QPS_UF_CONTROL_KICK_ADDR 0x00700201L
+#define TSU_QPS_UF_CONTROL_KICK_STRIDE 1
+#define TSU_QPS_UF_CONTROL_KICK_DEPTH 1
+
+ /*
+ * Bitvector indicating (one bit per UF) if a UF has entries in tsu_qps or
+ * not. This could be used to verify that a UF flush/invalidate has happened.
+ */
+#define TSU_QPS_UF_EMPTY_ADDR 0x00700202L
+#define TSU_QPS_UF_EMPTY_STRIDE 1
+#define TSU_QPS_UF_EMPTY_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_QPS_INT_STATUS_ADDR 0x00700203L
+#define TSU_QPS_INT_STATUS_STRIDE 1
+#define TSU_QPS_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_QPS_INT_MASK_ADDR 0x00700204L
+#define TSU_QPS_INT_MASK_STRIDE 1
+#define TSU_QPS_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_QPS_INT_PRI_ADDR 0x00700205L
+#define TSU_QPS_INT_PRI_STRIDE 1
+#define TSU_QPS_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_QPS_INT_STATUS_CLEAR_ADDR 0x00700206L
+#define TSU_QPS_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_QPS_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_QPS_INT_STATUS_CLEAR_KICK_ADDR 0x00700207L
+#define TSU_QPS_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_QPS_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /*
+ * Stops timeout checking for UF in the uf_control register. This register
+ * must be kicked in order to make sure refcounts are not incremented for the
+ * UF to be flushed/invalidated.
+ */
+#define TSU_QPS_UF_STOP_TIMEOUT_KICK_ADDR 0x00700240L
+#define TSU_QPS_UF_STOP_TIMEOUT_KICK_STRIDE 1
+#define TSU_QPS_UF_STOP_TIMEOUT_KICK_DEPTH 1
+
+ /*
+ * Per UF modify/query QP command/attribute register. Only one register is
+ * implemented in hardware - one at a time. EPS implements one register per
+ * UF. When one is written, the modify data is written to modify_qp_data
+ * register before this register is written. The Modify or Query QP command
+ * is autmatically kicked when this register is written. Is one outstanding
+ * modify/query QP per UF ok, or do we need more?
+ */
+#define TSU_QPS_MODIFY_QP_CTRL_ADDR 0x00700400L
+#define TSU_QPS_MODIFY_QP_CTRL_STRIDE 1
+#define TSU_QPS_MODIFY_QP_CTRL_DEPTH 1
+
+#define TSU_QPS_MODIFY_QP_DATA_0_ADDR 0x00700440L
+#define TSU_QPS_MODIFY_QP_DATA_0_STRIDE 10
+#define TSU_QPS_MODIFY_QP_DATA_0_DEPTH 1
+
+#define TSU_QPS_MODIFY_QP_DATA_1_ADDR 0x00700441L
+#define TSU_QPS_MODIFY_QP_DATA_1_STRIDE 10
+#define TSU_QPS_MODIFY_QP_DATA_1_DEPTH 1
+
+#define TSU_QPS_MODIFY_QP_DATA_2_ADDR 0x00700442L
+#define TSU_QPS_MODIFY_QP_DATA_2_STRIDE 10
+#define TSU_QPS_MODIFY_QP_DATA_2_DEPTH 1
+
+#define TSU_QPS_MODIFY_QP_DATA_3_ADDR 0x00700443L
+#define TSU_QPS_MODIFY_QP_DATA_3_STRIDE 10
+#define TSU_QPS_MODIFY_QP_DATA_3_DEPTH 1
+
+#define TSU_QPS_MODIFY_QP_DATA_4_ADDR 0x00700444L
+#define TSU_QPS_MODIFY_QP_DATA_4_STRIDE 10
+#define TSU_QPS_MODIFY_QP_DATA_4_DEPTH 1
+
+#define TSU_QPS_MODIFY_QP_DATA_5_ADDR 0x00700445L
+#define TSU_QPS_MODIFY_QP_DATA_5_STRIDE 10
+#define TSU_QPS_MODIFY_QP_DATA_5_DEPTH 1
+
+#define TSU_QPS_MODIFY_QP_DATA_6_ADDR 0x00700446L
+#define TSU_QPS_MODIFY_QP_DATA_6_STRIDE 10
+#define TSU_QPS_MODIFY_QP_DATA_6_DEPTH 1
+
+#define TSU_QPS_MODIFY_QP_DATA_7_ADDR 0x00700447L
+#define TSU_QPS_MODIFY_QP_DATA_7_STRIDE 10
+#define TSU_QPS_MODIFY_QP_DATA_7_DEPTH 1
+
+#define TSU_QPS_MODIFY_QP_DATA_8_ADDR 0x00700448L
+#define TSU_QPS_MODIFY_QP_DATA_8_STRIDE 10
+#define TSU_QPS_MODIFY_QP_DATA_8_DEPTH 1
+
+#define TSU_QPS_MODIFY_QP_DATA_9_ADDR 0x00700449L
+#define TSU_QPS_MODIFY_QP_DATA_9_STRIDE 10
+#define TSU_QPS_MODIFY_QP_DATA_9_DEPTH 1
+
+ /*
+ * Kick register to start a new modify or query command. This register is
+ * written by EPS.
+ */
+#define TSU_QPS_MODIFY_QP_KICK_ADDR 0x00700480L
+#define TSU_QPS_MODIFY_QP_KICK_STRIDE 1
+#define TSU_QPS_MODIFY_QP_KICK_DEPTH 1
+
+ /*
+ * Status register indicating status of modify QP and query QP commands. This
+ * register is read by the EPS only.
+ */
+#define TSU_QPS_MODIFY_QP_STATUS_ADDR 0x00700481L
+#define TSU_QPS_MODIFY_QP_STATUS_STRIDE 1
+#define TSU_QPS_MODIFY_QP_STATUS_DEPTH 1
+
+ /*
+ * Data register containing data for the query QP command. This is read by
+ * the EPS only. The register is laid out to contain QP, primary_path and
+ * alternate path - same as it is in host memory. This is only a data bus,
+ * not using the structure psif_verbs_pkg::query_qp_t. When data is queried,
+ * and written to this register the psif_verbs_pkg::query_qp_t is cast to
+ * this structure. Please look at psif_verbs_pkg::query_qp_t for details.
+ */
+#define TSU_QPS_QUERY_QP_DATA_ADDR 0x00700482L
+#define TSU_QPS_QUERY_QP_DATA_STRIDE 1
+#define TSU_QPS_QUERY_QP_DATA_DEPTH 24
+
+ /*
+ * QP data register - see psif_verbs_pkg::qp_t for details on layout. This
+ * register contain the QP data information to write to QP index (HW cache
+ * index) given by the wr_qp_index CSR. This register is used to initialize
+ * QP 0/1, and is not accessible from user space. It could also be used for
+ * diagnostics.
+ */
+#define TSU_QPS_WR_QP_DATA_ADDR 0x00700500L
+#define TSU_QPS_WR_QP_DATA_STRIDE 1
+#define TSU_QPS_WR_QP_DATA_DEPTH 16
+
+ /*
+ * QP data register - see psif_verbs_pkg::path_info_t for details on layout.
+ * This register contain the path data to write to QP index (HW cache index)
+ * given by the wr_qp_index CSR. This register is used to initialize QP 0/1,
+ * and is not accessible from user space.
+ */
+#define TSU_QPS_WR_QP_PATH_ADDR 0x00700514L
+#define TSU_QPS_WR_QP_PATH_STRIDE 1
+#define TSU_QPS_WR_QP_PATH_DEPTH 4
+
+ /*
+ * QP index register. This register contain the QP index where the QP
+ * information is written to. This register is used to initialize QP 0/1, and
+ * is not accessible from user space. Set this to 0 for QP0 and 1 for QP1.
+ */
+#define TSU_QPS_WR_QP_INDEX_ADDR 0x00700540L
+#define TSU_QPS_WR_QP_INDEX_STRIDE 1
+#define TSU_QPS_WR_QP_INDEX_DEPTH 1
+
+ /*
+ * Kick register to start a new writing the QP information in wr_qp_data and
+ * wr_qp_path to QP index given in wr_qp_index CSR. This register is .
+ */
+#define TSU_QPS_WR_QP_KICK_ADDR 0x00700541L
+#define TSU_QPS_WR_QP_KICK_STRIDE 1
+#define TSU_QPS_WR_QP_KICK_DEPTH 1
+
+ /*
+ * DO NOT USE!! This register gives the option to change fields which can be
+ * changed in a QP modify command. It is not to be accessed by users, and is
+ * only here for flexibility. The register contain legal attribute masks for
+ * QP modification for state transition INIT to RTR.
+ */
+#define TSU_QPS_MODIFY_ATTR_MASK_INIT_RTR_ADDR 0x00700800L
+#define TSU_QPS_MODIFY_ATTR_MASK_INIT_RTR_STRIDE 1
+#define TSU_QPS_MODIFY_ATTR_MASK_INIT_RTR_DEPTH 2
+
+ /*
+ * DO NOT USE!! This register gives the option to change fields which can be
+ * changed in a QP modify command. It is not to be accessed by users, and is
+ * only here for flexibility. The register contain legal attribute masks for
+ * QP modification for state transition RTR to RTS.
+ */
+#define TSU_QPS_MODIFY_ATTR_MASK_RTR_RTS_ADDR 0x00700802L
+#define TSU_QPS_MODIFY_ATTR_MASK_RTR_RTS_STRIDE 1
+#define TSU_QPS_MODIFY_ATTR_MASK_RTR_RTS_DEPTH 2
+
+ /*
+ * DO NOT USE!! This register gives the option to change fields which can be
+ * changed in a QP modify command. It is not to be accessed by users, and is
+ * only here for flexibility. The register contain legal attribute masks for
+ * QP modification for state transition RTS to RTS.
+ */
+#define TSU_QPS_MODIFY_ATTR_MASK_RTS_RTS_ADDR 0x00700804L
+#define TSU_QPS_MODIFY_ATTR_MASK_RTS_RTS_STRIDE 1
+#define TSU_QPS_MODIFY_ATTR_MASK_RTS_RTS_DEPTH 2
+
+ /*
+ * DO NOT USE!! This register gives the option to change fields which can be
+ * changed in a QP modify command. It is not to be accessed by users, and is
+ * only here for flexibility. The register contain legal attribute masks for
+ * QP modification for state transition from any state to RESET or ERROR.
+ */
+#define TSU_QPS_MODIFY_ATTR_MASK_ANY_ERR_RESET_ADDR 0x00700806L
+#define TSU_QPS_MODIFY_ATTR_MASK_ANY_ERR_RESET_STRIDE 1
+#define TSU_QPS_MODIFY_ATTR_MASK_ANY_ERR_RESET_DEPTH 2
+
+ /*
+ * DO NOT USE!! This register gives the option to change fields which can be
+ * changed in a QP modify command. It is not to be accessed by users, and is
+ * only here for flexibility. Legal attribute masks for QP modification for
+ * state transition from SQERR to RTS.
+ */
+#define TSU_QPS_MODIFY_ATTR_MASK_SQERR_RTS_ADDR 0x00700808L
+#define TSU_QPS_MODIFY_ATTR_MASK_SQERR_RTS_STRIDE 1
+#define TSU_QPS_MODIFY_ATTR_MASK_SQERR_RTS_DEPTH 2
+
+ /*
+ * Status register indicating that the refcount hit zero after the qp_index
+ * was armed. There is one bit per QP index. This register is read by the EPS
+ * only.
+ */
+#define TSU_QPS_REFCOUNT_ZERO_STATUS_ADDR 0x00701000L
+#define TSU_QPS_REFCOUNT_ZERO_STATUS_STRIDE 1
+#define TSU_QPS_REFCOUNT_ZERO_STATUS_DEPTH 32
+
+ /* Mask CAM parity errors such that they do not cause FATAL errors. */
+#define TSU_QPS_CAM_PAR_ERR_MASK_ADDR 0x00701020L
+#define TSU_QPS_CAM_PAR_ERR_MASK_STRIDE 1
+#define TSU_QPS_CAM_PAR_ERR_MASK_DEPTH 1
+
+ /* Per UF refcount register. This is used for UF flushing. */
+#define TSU_QPS_REF_COUNT_ADDR 0x00702000L
+#define TSU_QPS_REF_COUNT_STRIDE 1
+#define TSU_QPS_REF_COUNT_DEPTH 33
+
+ /* Debug register for the modify block. */
+#define TSU_QPS_MODIFY_QP_DEBUG_ADDR 0x00702040L
+#define TSU_QPS_MODIFY_QP_DEBUG_STRIDE 1
+#define TSU_QPS_MODIFY_QP_DEBUG_DEPTH 1
+
+ /*
+ * Status register indicating that the refcount hit zero after the qp_index
+ * was armed. There is one bit per QP index. This register is read by the EPS
+ * only.
+ */
+#define TSU_QPS_REFCOUNT_ZERO_STATUS_CLEAR_ADDR 0x00704000L
+#define TSU_QPS_REFCOUNT_ZERO_STATUS_CLEAR_STRIDE 1
+#define TSU_QPS_REFCOUNT_ZERO_STATUS_CLEAR_DEPTH 2048
+
+ /*
+ * This register must be set and the kick register is written in order to
+ * start the operation.
+ */
+#define TSU_CMPL_UF_CONTROL_ADDR 0x00800000L
+#define TSU_CMPL_UF_CONTROL_STRIDE 1
+#define TSU_CMPL_UF_CONTROL_DEPTH 1
+
+ /* Starts operation defined in uf_control. */
+#define TSU_CMPL_UF_CONTROL_KICK_ADDR 0x00800001L
+#define TSU_CMPL_UF_CONTROL_KICK_STRIDE 1
+#define TSU_CMPL_UF_CONTROL_KICK_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_CMPL_INT_STATUS_ADDR 0x00800002L
+#define TSU_CMPL_INT_STATUS_STRIDE 1
+#define TSU_CMPL_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_CMPL_INT_MASK_ADDR 0x00800003L
+#define TSU_CMPL_INT_MASK_STRIDE 1
+#define TSU_CMPL_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_CMPL_INT_PRI_ADDR 0x00800004L
+#define TSU_CMPL_INT_PRI_STRIDE 1
+#define TSU_CMPL_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_CMPL_INT_STATUS_CLEAR_ADDR 0x00800005L
+#define TSU_CMPL_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_CMPL_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_CMPL_INT_STATUS_CLEAR_KICK_ADDR 0x00800006L
+#define TSU_CMPL_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_CMPL_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /* CAM PERR detected status register. */
+#define TSU_CMPL_PERR_STATUS_ADDR 0x00800007L
+#define TSU_CMPL_PERR_STATUS_STRIDE 1
+#define TSU_CMPL_PERR_STATUS_DEPTH 1
+
+ /* Mask PERR interrupt. */
+#define TSU_CMPL_PERR_MASK_ADDR 0x00800008L
+#define TSU_CMPL_PERR_MASK_STRIDE 1
+#define TSU_CMPL_PERR_MASK_DEPTH 1
+
+ /* Mask packet stall on PERR interrupt. */
+#define TSU_CMPL_PERR_STALL_MASK_ADDR 0x00800009L
+#define TSU_CMPL_PERR_STALL_MASK_STRIDE 1
+#define TSU_CMPL_PERR_STALL_MASK_DEPTH 1
+
+ /* Spin set size used when handling max spin set response. */
+#define TSU_CMPL_DEBUG_SPIN_SET_SIZE_ADDR 0x0080000aL
+#define TSU_CMPL_DEBUG_SPIN_SET_SIZE_STRIDE 1
+#define TSU_CMPL_DEBUG_SPIN_SET_SIZE_DEPTH 1
+
+ /* UF QPN and MSN of max spin set response. */
+#define TSU_CMPL_DEBUG_RESPONSE_INFO_ADDR 0x0080000bL
+#define TSU_CMPL_DEBUG_RESPONSE_INFO_STRIDE 1
+#define TSU_CMPL_DEBUG_RESPONSE_INFO_DEPTH 1
+
+ /* Spin set mode (safe = 1 fast = 0). Default is fast mode. */
+#define TSU_CMPL_SPIN_SET_CONTROL_ADDR 0x0080000cL
+#define TSU_CMPL_SPIN_SET_CONTROL_STRIDE 1
+#define TSU_CMPL_SPIN_SET_CONTROL_DEPTH 1
+
+ /* Base address. */
+#define TSU_CMPL_SQ_BASE_ADDR_0_ADDR 0x00800040L
+#define TSU_CMPL_SQ_BASE_ADDR_0_STRIDE 1
+#define TSU_CMPL_SQ_BASE_ADDR_0_DEPTH 34
+
+ /* MMU context. */
+#define TSU_CMPL_SQ_BASE_ADDR_1_ADDR 0x00800080L
+#define TSU_CMPL_SQ_BASE_ADDR_1_STRIDE 1
+#define TSU_CMPL_SQ_BASE_ADDR_1_DEPTH 34
+
+ /* Num entries and extent. */
+#define TSU_CMPL_SQ_BASE_ADDR_2_ADDR 0x008000c0L
+#define TSU_CMPL_SQ_BASE_ADDR_2_STRIDE 1
+#define TSU_CMPL_SQ_BASE_ADDR_2_DEPTH 34
+
+#define TSU_VAL_KEY_BASE_ADDR_0_ADDR 0x00900000L
+#define TSU_VAL_KEY_BASE_ADDR_0_STRIDE 1
+#define TSU_VAL_KEY_BASE_ADDR_0_DEPTH 34
+
+#define TSU_VAL_KEY_BASE_ADDR_1_ADDR 0x00900040L
+#define TSU_VAL_KEY_BASE_ADDR_1_STRIDE 1
+#define TSU_VAL_KEY_BASE_ADDR_1_DEPTH 34
+
+#define TSU_VAL_KEY_BASE_ADDR_2_ADDR 0x00900080L
+#define TSU_VAL_KEY_BASE_ADDR_2_STRIDE 1
+#define TSU_VAL_KEY_BASE_ADDR_2_DEPTH 34
+
+ /*
+ * This register must be set and the kick register is written in order to
+ * start the operation.
+ */
+#define TSU_VAL_UF_CONTROL_ADDR 0x00900100L
+#define TSU_VAL_UF_CONTROL_STRIDE 1
+#define TSU_VAL_UF_CONTROL_DEPTH 1
+
+ /* Starts operation defined in uf_control. */
+#define TSU_VAL_UF_CONTROL_KICK_ADDR 0x00900101L
+#define TSU_VAL_UF_CONTROL_KICK_STRIDE 1
+#define TSU_VAL_UF_CONTROL_KICK_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_VAL_INT_STATUS_ADDR 0x00900102L
+#define TSU_VAL_INT_STATUS_STRIDE 1
+#define TSU_VAL_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_VAL_INT_MASK_ADDR 0x00900103L
+#define TSU_VAL_INT_MASK_STRIDE 1
+#define TSU_VAL_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_VAL_INT_PRI_ADDR 0x00900104L
+#define TSU_VAL_INT_PRI_STRIDE 1
+#define TSU_VAL_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_VAL_INT_STATUS_CLEAR_ADDR 0x00900105L
+#define TSU_VAL_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_VAL_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_VAL_INT_STATUS_CLEAR_KICK_ADDR 0x00900106L
+#define TSU_VAL_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_VAL_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /*
+ * This register must be set and the kick register is written in order to
+ * start the operation.
+ */
+#define TSU_RQH_UF_CONTROL_ADDR 0x00a00000L
+#define TSU_RQH_UF_CONTROL_STRIDE 1
+#define TSU_RQH_UF_CONTROL_DEPTH 1
+
+ /* Starts operation defined in uf_control. */
+#define TSU_RQH_UF_CONTROL_KICK_ADDR 0x00a00001L
+#define TSU_RQH_UF_CONTROL_KICK_STRIDE 1
+#define TSU_RQH_UF_CONTROL_KICK_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_RQH_INT_STATUS_ADDR 0x00a00002L
+#define TSU_RQH_INT_STATUS_STRIDE 1
+#define TSU_RQH_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_RQH_INT_MASK_ADDR 0x00a00003L
+#define TSU_RQH_INT_MASK_STRIDE 1
+#define TSU_RQH_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_RQH_INT_PRI_ADDR 0x00a00004L
+#define TSU_RQH_INT_PRI_STRIDE 1
+#define TSU_RQH_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_RQH_INT_STATUS_CLEAR_ADDR 0x00a00005L
+#define TSU_RQH_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_RQH_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_RQH_INT_STATUS_CLEAR_KICK_ADDR 0x00a00006L
+#define TSU_RQH_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_RQH_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+#define TSU_RQH_QP_BASE_ADDR_0_ADDR 0x00a00080L
+#define TSU_RQH_QP_BASE_ADDR_0_STRIDE 1
+#define TSU_RQH_QP_BASE_ADDR_0_DEPTH 34
+
+#define TSU_RQH_QP_BASE_ADDR_1_ADDR 0x00a000c0L
+#define TSU_RQH_QP_BASE_ADDR_1_STRIDE 1
+#define TSU_RQH_QP_BASE_ADDR_1_DEPTH 34
+
+#define TSU_RQH_QP_BASE_ADDR_2_ADDR 0x00a00100L
+#define TSU_RQH_QP_BASE_ADDR_2_STRIDE 1
+#define TSU_RQH_QP_BASE_ADDR_2_DEPTH 34
+
+ /*
+ * Base address registers per UF for software owned descriptor portion of
+ * receive queue descriptors.
+ */
+#define TSU_DSCR_RQ_BASE_ADDR_SW_0_ADDR 0x00b00300L
+#define TSU_DSCR_RQ_BASE_ADDR_SW_0_STRIDE 1
+#define TSU_DSCR_RQ_BASE_ADDR_SW_0_DEPTH 34
+
+#define TSU_DSCR_RQ_BASE_ADDR_SW_1_ADDR 0x00b00340L
+#define TSU_DSCR_RQ_BASE_ADDR_SW_1_STRIDE 1
+#define TSU_DSCR_RQ_BASE_ADDR_SW_1_DEPTH 34
+
+#define TSU_DSCR_RQ_BASE_ADDR_SW_2_ADDR 0x00b00380L
+#define TSU_DSCR_RQ_BASE_ADDR_SW_2_STRIDE 1
+#define TSU_DSCR_RQ_BASE_ADDR_SW_2_DEPTH 34
+
+ /*
+ * Base address registers per UF for hardware owned descriptor portion of
+ * receive queue descriptors.
+ */
+#define TSU_DSCR_RQ_BASE_ADDR_HW_0_ADDR 0x00b003c0L
+#define TSU_DSCR_RQ_BASE_ADDR_HW_0_STRIDE 1
+#define TSU_DSCR_RQ_BASE_ADDR_HW_0_DEPTH 34
+
+#define TSU_DSCR_RQ_BASE_ADDR_HW_1_ADDR 0x00b00400L
+#define TSU_DSCR_RQ_BASE_ADDR_HW_1_STRIDE 1
+#define TSU_DSCR_RQ_BASE_ADDR_HW_1_DEPTH 34
+
+#define TSU_DSCR_RQ_BASE_ADDR_HW_2_ADDR 0x00b00440L
+#define TSU_DSCR_RQ_BASE_ADDR_HW_2_STRIDE 1
+#define TSU_DSCR_RQ_BASE_ADDR_HW_2_DEPTH 34
+
+ /*
+ * This register must be set and the kick register is written in order to
+ * start the operation.
+ */
+#define TSU_DSCR_UF_CONTROL_ADDR 0x00b00700L
+#define TSU_DSCR_UF_CONTROL_STRIDE 1
+#define TSU_DSCR_UF_CONTROL_DEPTH 1
+
+ /* Starts operation defined in uf_control. */
+#define TSU_DSCR_UF_CONTROL_KICK_ADDR 0x00b00701L
+#define TSU_DSCR_UF_CONTROL_KICK_STRIDE 1
+#define TSU_DSCR_UF_CONTROL_KICK_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_DSCR_INT_STATUS_ADDR 0x00b00702L
+#define TSU_DSCR_INT_STATUS_STRIDE 1
+#define TSU_DSCR_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_DSCR_INT_MASK_ADDR 0x00b00703L
+#define TSU_DSCR_INT_MASK_STRIDE 1
+#define TSU_DSCR_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_DSCR_INT_PRI_ADDR 0x00b00704L
+#define TSU_DSCR_INT_PRI_STRIDE 1
+#define TSU_DSCR_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_DSCR_INT_STATUS_CLEAR_ADDR 0x00b00705L
+#define TSU_DSCR_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_DSCR_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_DSCR_INT_STATUS_CLEAR_KICK_ADDR 0x00b00706L
+#define TSU_DSCR_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_DSCR_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /* Various diagnostic control bits */
+#define TSU_DSCR_DIAGNOSTIC_ADDR 0x00b00800L
+#define TSU_DSCR_DIAGNOSTIC_STRIDE 1
+#define TSU_DSCR_DIAGNOSTIC_DEPTH 1
+
+ /* Fatal interrupt bits */
+#define TSU_DSCR_FATAL_INTERRUPT_ADDR 0x00b01000L
+#define TSU_DSCR_FATAL_INTERRUPT_STRIDE 1
+#define TSU_DSCR_FATAL_INTERRUPT_DEPTH 1
+
+ /* RSS table containing CQ and RQ. This table is used for EoIB RSS. */
+#define TSU_RCV_RSS_EOIB_TABLE_ADDR 0x00c00000L
+#define TSU_RCV_RSS_EOIB_TABLE_STRIDE 1
+#define TSU_RCV_RSS_EOIB_TABLE_DEPTH 128
+
+ /*
+ * Control register for RSS per vHCA (UF0-UF32). Containing the bit masks to
+ * use when masking hashes.
+ */
+#define TSU_RCV_RSS_CTRL_EOIB_TABLE_ADDR 0x00c00080L
+#define TSU_RCV_RSS_CTRL_EOIB_TABLE_STRIDE 1
+#define TSU_RCV_RSS_CTRL_EOIB_TABLE_DEPTH 33
+
+ /* RSS table containing CQ and RQ. This table is used for IPoIB RSS. */
+#define TSU_RCV_RSS_IPOIB_TABLE_ADDR 0x00c00100L
+#define TSU_RCV_RSS_IPOIB_TABLE_STRIDE 1
+#define TSU_RCV_RSS_IPOIB_TABLE_DEPTH 128
+
+ /*
+ * Control register for RSS per vHCA (UF0-UF32). Containing the bit masks to
+ * use when masking hashes.
+ */
+#define TSU_RCV_RSS_CTRL_IPOIB_TABLE_ADDR 0x00c00180L
+#define TSU_RCV_RSS_CTRL_IPOIB_TABLE_STRIDE 1
+#define TSU_RCV_RSS_CTRL_IPOIB_TABLE_DEPTH 33
+
+ /*
+ * Control register for EPS-A offloading per vHCA (UF0-UF32). It is
+ * containing the size which is the limit for sending packets to EPS-A.
+ */
+#define TSU_RCV_PROXY_SIZE_ADDR 0x00c00200L
+#define TSU_RCV_PROXY_SIZE_STRIDE 1
+#define TSU_RCV_PROXY_SIZE_DEPTH 33
+
+ /* Maximum MAD packet size supported. */
+#define TSU_RCV_MAD_SIZE_ADDR 0x00c00300L
+#define TSU_RCV_MAD_SIZE_STRIDE 1
+#define TSU_RCV_MAD_SIZE_DEPTH 1
+
+ /*
+ * One bit per vHCA indicating if the vHCA is allowed to use proxy mode.
+ */
+#define TSU_RCV_PROXY_ALLOWED_ADDR 0x00c00301L
+#define TSU_RCV_PROXY_ALLOWED_STRIDE 1
+#define TSU_RCV_PROXY_ALLOWED_DEPTH 1
+
+ /*
+ * Error counter for multicast rejects. There is one register per vHCA port.
+ */
+#define TSU_RCV_EOIB_MCAST_REJECT_ADDR 0x00c02000L
+#define TSU_RCV_EOIB_MCAST_REJECT_STRIDE 1
+#define TSU_RCV_EOIB_MCAST_REJECT_DEPTH 68
+
+ /*
+ * Error counter for broadcast rejects. There is one register per vHCA port.
+ */
+#define TSU_RCV_EOIB_BCAST_REJECT_ADDR 0x00c02080L
+#define TSU_RCV_EOIB_BCAST_REJECT_STRIDE 1
+#define TSU_RCV_EOIB_BCAST_REJECT_DEPTH 68
+
+ /*
+ * Error counter for unicast rejects. There is one register per vHCA port.
+ */
+#define TSU_RCV_EOIB_UCAST_REJECT_ADDR 0x00c02100L
+#define TSU_RCV_EOIB_UCAST_REJECT_STRIDE 1
+#define TSU_RCV_EOIB_UCAST_REJECT_DEPTH 68
+
+ /*
+ * Error counter for rejects. There is one register per vHCA port.
+ */
+#define TSU_RCV_EOIB_TCP_PORT_VIOLATION_REJECT_ADDR 0x00c02180L
+#define TSU_RCV_EOIB_TCP_PORT_VIOLATION_REJECT_STRIDE 1
+#define TSU_RCV_EOIB_TCP_PORT_VIOLATION_REJECT_DEPTH 68
+
+ /*
+ * Error counter for runt rejects. There is one register per vHCA port.
+ */
+#define TSU_RCV_EOIB_RUNTS_REJECT_ADDR 0x00c02200L
+#define TSU_RCV_EOIB_RUNTS_REJECT_STRIDE 1
+#define TSU_RCV_EOIB_RUNTS_REJECT_DEPTH 68
+
+ /*
+ * Error counter for outer VLAN rejects. There is one register per vHCA port.
+ */
+#define TSU_RCV_EOIB_OUTER_VLAN_REJECT_ADDR 0x00c02280L
+#define TSU_RCV_EOIB_OUTER_VLAN_REJECT_STRIDE 1
+#define TSU_RCV_EOIB_OUTER_VLAN_REJECT_DEPTH 68
+
+ /*
+ * Error counter for VLAN tag rejects. There is one register per vHCA port.
+ */
+#define TSU_RCV_EOIB_VLAN_TAG_REJECT_ADDR 0x00c02300L
+#define TSU_RCV_EOIB_VLAN_TAG_REJECT_STRIDE 1
+#define TSU_RCV_EOIB_VLAN_TAG_REJECT_DEPTH 68
+
+ /*
+ * Error counter for VID rejects. There is one register per vHCA port.
+ */
+#define TSU_RCV_EOIB_VID_REJECT_ADDR 0x00c02380L
+#define TSU_RCV_EOIB_VID_REJECT_STRIDE 1
+#define TSU_RCV_EOIB_VID_REJECT_DEPTH 68
+
+ /*
+ * Error counter for TCP port filtering violation rejects. There is one
+ * register per vHCA port.
+ */
+#define TSU_RCV_IPOIB_TCP_PORT_VIOLATION_REJECT_ADDR 0x00c02400L
+#define TSU_RCV_IPOIB_TCP_PORT_VIOLATION_REJECT_STRIDE 1
+#define TSU_RCV_IPOIB_TCP_PORT_VIOLATION_REJECT_DEPTH 68
+
+ /*
+ * Control if multicast packets should be forwarded to yourself or not when
+ * the QP is a IPoIB or EoIB QP.
+ */
+#define TSU_RCV_NO_MCAST_DUPLICATION_ADDR 0x00c02800L
+#define TSU_RCV_NO_MCAST_DUPLICATION_STRIDE 1
+#define TSU_RCV_NO_MCAST_DUPLICATION_DEPTH 1
+
+ /* Trap register for P-Key and Q-Key traps. */
+#define TSU_RCV_KEY_TRAP_SGID_UPPER_ADDR 0x00c04000L
+#define TSU_RCV_KEY_TRAP_SGID_UPPER_STRIDE 1
+#define TSU_RCV_KEY_TRAP_SGID_UPPER_DEPTH 1
+
+ /* Trap register for P-Key and Q-Key traps. */
+#define TSU_RCV_KEY_TRAP_SGID_LOWER_ADDR 0x00c04001L
+#define TSU_RCV_KEY_TRAP_SGID_LOWER_STRIDE 1
+#define TSU_RCV_KEY_TRAP_SGID_LOWER_DEPTH 1
+
+ /* Trap register for P-Key and Q-Key traps. */
+#define TSU_RCV_KEY_TRAP_DGID_UPPER_ADDR 0x00c04002L
+#define TSU_RCV_KEY_TRAP_DGID_UPPER_STRIDE 1
+#define TSU_RCV_KEY_TRAP_DGID_UPPER_DEPTH 1
+
+ /* Trap register for P-Key and Q-Key traps. */
+#define TSU_RCV_KEY_TRAP_DGID_LOWER_ADDR 0x00c04003L
+#define TSU_RCV_KEY_TRAP_DGID_LOWER_STRIDE 1
+#define TSU_RCV_KEY_TRAP_DGID_LOWER_DEPTH 1
+
+ /* Trap register for P-Key and Q-Key traps. */
+#define TSU_RCV_KEY_TRAP_QP_ADDR 0x00c04004L
+#define TSU_RCV_KEY_TRAP_QP_STRIDE 1
+#define TSU_RCV_KEY_TRAP_QP_DEPTH 1
+
+ /* Trap register for P-Key and Q-Key traps. */
+#define TSU_RCV_KEY_TRAP_LID_KEY_ADDR 0x00c04005L
+#define TSU_RCV_KEY_TRAP_LID_KEY_STRIDE 1
+#define TSU_RCV_KEY_TRAP_LID_KEY_DEPTH 1
+
+ /* Pop register for P-Key and Q-Key trap FIFO. */
+#define TSU_RCV_KEY_TRAP_POP_ADDR 0x00c04008L
+#define TSU_RCV_KEY_TRAP_POP_STRIDE 1
+#define TSU_RCV_KEY_TRAP_POP_DEPTH 1
+
+ /* Register indicating what to do if the trap FIFO is full. */
+#define TSU_RCV_KEY_TRAP_BACKPRESSURE_ADDR 0x00c04010L
+#define TSU_RCV_KEY_TRAP_BACKPRESSURE_STRIDE 1
+#define TSU_RCV_KEY_TRAP_BACKPRESSURE_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_RCV_INT_STATUS_ADDR 0x00c04400L
+#define TSU_RCV_INT_STATUS_STRIDE 1
+#define TSU_RCV_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_RCV_INT_MASK_ADDR 0x00c04401L
+#define TSU_RCV_INT_MASK_STRIDE 1
+#define TSU_RCV_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_RCV_INT_PRI_ADDR 0x00c04402L
+#define TSU_RCV_INT_PRI_STRIDE 1
+#define TSU_RCV_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_RCV_INT_STATUS_CLEAR_ADDR 0x00c04403L
+#define TSU_RCV_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_RCV_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_RCV_INT_STATUS_CLEAR_KICK_ADDR 0x00c04404L
+#define TSU_RCV_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_RCV_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /*
+ * 64 bits of IPv4/IPv6 address. This register is fed by a FIFO feeding into
+ * int_status. Clearing the interrupt status will pop the FIFO.
+ */
+#define TSU_RCV_PORT_FILTER_IP_SOURCE_ADDR 0x00c04800L
+#define TSU_RCV_PORT_FILTER_IP_SOURCE_STRIDE 1
+#define TSU_RCV_PORT_FILTER_IP_SOURCE_DEPTH 1
+
+ /*
+ * TCP destination port and SLID. This register is fed by a FIFO feeding into
+ * int_status. Clearing the interrupt status will pop the FIFO.
+ */
+#define TSU_RCV_PORT_FILTER_SLID_PORT_ADDR 0x00c04801L
+#define TSU_RCV_PORT_FILTER_SLID_PORT_STRIDE 1
+#define TSU_RCV_PORT_FILTER_SLID_PORT_DEPTH 1
+
+ /* Decide if the debug FIFO should be used or not. */
+#define TSU_RCV_PORT_FILTER_USE_FIFO_ADDR 0x00c04802L
+#define TSU_RCV_PORT_FILTER_USE_FIFO_STRIDE 1
+#define TSU_RCV_PORT_FILTER_USE_FIFO_DEPTH 1
+
+ /* Pop register for port filter debug FIFO. */
+#define TSU_RCV_PORT_FILTER_POP_ADDR 0x00c04803L
+#define TSU_RCV_PORT_FILTER_POP_STRIDE 1
+#define TSU_RCV_PORT_FILTER_POP_DEPTH 1
+
+ /*
+ * Shared P-Key table for all UFs on this port. Number of entries valid per
+ * UF is defined by the p1_pkey_uf_stride register.
+ */
+#define TSU_IBPR_P1_PKEY_TABLE_ADDR 0x00d00000L
+#define TSU_IBPR_P1_PKEY_TABLE_STRIDE 1
+#define TSU_IBPR_P1_PKEY_TABLE_DEPTH 272
+
+ /*
+ * Size of individual P-Key tables per UF. All UFs have the same size or if
+ * set to 0, it means one common table.
+ */
+#define TSU_IBPR_P1_PKEY_UF_STRIDE_ADDR 0x00d00200L
+#define TSU_IBPR_P1_PKEY_UF_STRIDE_STRIDE 1
+#define TSU_IBPR_P1_PKEY_UF_STRIDE_DEPTH 1
+
+ /* Permission and entry table for TCP port filtering. */
+#define TSU_IBPR_P1_TCP_PERMISSION_TABLE_ADDR 0x00d00400L
+#define TSU_IBPR_P1_TCP_PERMISSION_TABLE_STRIDE 1
+#define TSU_IBPR_P1_TCP_PERMISSION_TABLE_DEPTH 272
+
+ /* Range table for the TCP Port filtering. */
+#define TSU_IBPR_P1_TCP_PORT_RANGE_TABLE_ADDR 0x00d00600L
+#define TSU_IBPR_P1_TCP_PORT_RANGE_TABLE_STRIDE 1
+#define TSU_IBPR_P1_TCP_PORT_RANGE_TABLE_DEPTH 32
+
+ /*
+ * Own LIDs base and LMC. Potentially all own LID bits come from the QP state
+ * entry. The number of bits to use is based on the LMC. Per UF register.
+ */
+#define TSU_IBPR_P1_OWN_LID_BASE_ADDR 0x00d00800L
+#define TSU_IBPR_P1_OWN_LID_BASE_STRIDE 1
+#define TSU_IBPR_P1_OWN_LID_BASE_DEPTH 34
+
+ /*
+ * Upper 64 bits of GID for port1. There are (2 * NUM_VHCA + 1) 67 GIDs per
+ * physical IB port.
+ */
+#define TSU_IBPR_P1_GID_UPPER_ADDR 0x00d00880L
+#define TSU_IBPR_P1_GID_UPPER_STRIDE 1
+#define TSU_IBPR_P1_GID_UPPER_DEPTH 67
+
+ /*
+ * Lower 64 bits of GID for port1. There are (2 * NUM_VHCA + 1) 67 GIDs per
+ * physical IB port.
+ */
+#define TSU_IBPR_P1_GID_LOWER_ADDR 0x00d00900L
+#define TSU_IBPR_P1_GID_LOWER_STRIDE 1
+#define TSU_IBPR_P1_GID_LOWER_DEPTH 67
+
+ /*
+ * GID forwarding table. The forwarding table is used to figure out if a
+ * packet should be sent in loopback or not. There are (2 * NUM_VHCA + 1) 67
+ * GIDs per physical IB port.
+ */
+#define TSU_IBPR_P1_GID_FORWARDING_TABLE_ADDR 0x00d00980L
+#define TSU_IBPR_P1_GID_FORWARDING_TABLE_STRIDE 1
+#define TSU_IBPR_P1_GID_FORWARDING_TABLE_DEPTH 67
+
+ /*
+ * One bit ber UF. If set for the UF, the upper 64bits are ignored in the
+ * DGID check.
+ */
+#define TSU_IBPR_P1_IGNORE_UPPER_64B_DGID_CHECK_ADDR 0x00d00a00L
+#define TSU_IBPR_P1_IGNORE_UPPER_64B_DGID_CHECK_STRIDE 1
+#define TSU_IBPR_P1_IGNORE_UPPER_64B_DGID_CHECK_DEPTH 1
+
+ /* Default vSwitch port for vSwitch1. */
+#define TSU_IBPR_P1_DEFAULT_VSWITCH_PORT_ADDR 0x00d00a80L
+#define TSU_IBPR_P1_DEFAULT_VSWITCH_PORT_STRIDE 1
+#define TSU_IBPR_P1_DEFAULT_VSWITCH_PORT_DEPTH 1
+
+ /* Default SM HCA. Indicating which vHCA to send SM packets to. */
+#define TSU_IBPR_P1_DEFAULT_SM_HCA_ADDR 0x00d00b00L
+#define TSU_IBPR_P1_DEFAULT_SM_HCA_STRIDE 1
+#define TSU_IBPR_P1_DEFAULT_SM_HCA_DEPTH 1
+
+ /*
+ * When a bit is set, the TSU will forward the particular management class to
+ * EPS-C. Per UF0-UF32.
+ */
+#define TSU_IBPR_P1_GSI_FORWARDING_TABLE_ADDR 0x00d00b80L
+#define TSU_IBPR_P1_GSI_FORWARDING_TABLE_STRIDE 1
+#define TSU_IBPR_P1_GSI_FORWARDING_TABLE_DEPTH 33
+
+ /*
+ * Register with a bit per UF/VHCA indicating if the UF/VHCA is allowed to
+ * send SMPs.
+ */
+#define TSU_IBPR_P1_SMP_ALLOWED_ADDR 0x00d01000L
+#define TSU_IBPR_P1_SMP_ALLOWED_STRIDE 1
+#define TSU_IBPR_P1_SMP_ALLOWED_DEPTH 1
+
+ /*
+ * Status register with a bit per UF/VHCA indicating if an UF/VHCA SMP not
+ * allowed packet drop status is cleared.
+ */
+#define TSU_IBPR_P1_SMP_ALLOWED_DROP_STATUS_CLEAR_ADDR 0x00d01080L
+#define TSU_IBPR_P1_SMP_ALLOWED_DROP_STATUS_CLEAR_STRIDE 1
+#define TSU_IBPR_P1_SMP_ALLOWED_DROP_STATUS_CLEAR_DEPTH 1
+
+ /*
+ * Status register with a bit per UF/VHCA indicating if an UF/VHCA SMP not
+ * allowed packet is dropped.
+ */
+#define TSU_IBPR_P1_SMP_ALLOWED_DROP_STATUS_ADDR 0x00d01100L
+#define TSU_IBPR_P1_SMP_ALLOWED_DROP_STATUS_STRIDE 1
+#define TSU_IBPR_P1_SMP_ALLOWED_DROP_STATUS_DEPTH 1
+
+ /* Rx choke register */
+#define TSU_IBPR_P1_RX_CHOKE_ADDR 0x00d01180L
+#define TSU_IBPR_P1_RX_CHOKE_STRIDE 1
+#define TSU_IBPR_P1_RX_CHOKE_DEPTH 1
+
+ /*
+ * Get vlink state for the vHCA and the vSwitch. It is up to the firmware to
+ * report correct physical link states when one side is set to disabled and
+ * the other side is down.
+ */
+#define TSU_IBPR_P1_VLINK_STATE_ADDR 0x00d01200L
+#define TSU_IBPR_P1_VLINK_STATE_STRIDE 1
+#define TSU_IBPR_P1_VLINK_STATE_DEPTH 33
+
+ /*
+ * When data is present, this register should be read for processing.
+ * Hardware multicast FIFO is popped when p1_mcast_pop is written.
+ */
+#define TSU_IBPR_P1_MCAST_GID_UPPER_ADDR 0x00d01800L
+#define TSU_IBPR_P1_MCAST_GID_UPPER_STRIDE 1
+#define TSU_IBPR_P1_MCAST_GID_UPPER_DEPTH 1
+
+ /*
+ * When data is present, this register should be read for processing.
+ * Hardware multicast FIFO is popped when p1_mcast_pop is written.
+ */
+#define TSU_IBPR_P1_MCAST_GID_LOWER_ADDR 0x00d01802L
+#define TSU_IBPR_P1_MCAST_GID_LOWER_STRIDE 1
+#define TSU_IBPR_P1_MCAST_GID_LOWER_DEPTH 1
+
+ /*
+ * When data is present, this register should be read for processing.
+ * Hardware multicast FIFO is popped when p1_mcast_pop is written.
+ */
+#define TSU_IBPR_P1_MCAST_GIDHASH_LID_ADDR 0x00d01804L
+#define TSU_IBPR_P1_MCAST_GIDHASH_LID_STRIDE 1
+#define TSU_IBPR_P1_MCAST_GIDHASH_LID_DEPTH 1
+
+ /*
+ * This pop register is written after data in p1_mcast_gid_upper,
+ * p1_mcast_gid_lower and p1_mcast_lid is read. Writing this register will
+ * pop the FIFO.
+ */
+#define TSU_IBPR_P1_MCAST_POP_ADDR 0x00d01806L
+#define TSU_IBPR_P1_MCAST_POP_STRIDE 1
+#define TSU_IBPR_P1_MCAST_POP_DEPTH 1
+
+ /*
+ * This registers indicate how many multicast packets this port can hold
+ * before starting drop packets.
+ */
+#define TSU_IBPR_P1_MCAST_MAX_PKTS_ADDR 0x00d01808L
+#define TSU_IBPR_P1_MCAST_MAX_PKTS_STRIDE 1
+#define TSU_IBPR_P1_MCAST_MAX_PKTS_DEPTH 1
+
+ /*
+ * This register contain the credit for writing to the CSR FIFO for multicast
+ * packets.
+ */
+#define TSU_IBPR_P1_MCAST_WR_CREDIT_ADDR 0x00d0180aL
+#define TSU_IBPR_P1_MCAST_WR_CREDIT_STRIDE 1
+#define TSU_IBPR_P1_MCAST_WR_CREDIT_DEPTH 1
+
+ /* Write to multicast FIFO. */
+#define TSU_IBPR_P1_MCAST_WR_FIFO_ADDR 0x00d0180cL
+#define TSU_IBPR_P1_MCAST_WR_FIFO_STRIDE 1
+#define TSU_IBPR_P1_MCAST_WR_FIFO_DEPTH 1
+
+ /* Kick multicast FIFO - data is valid in the multicast FIFO. */
+#define TSU_IBPR_P1_MCAST_WR_FIFO_KICK_ADDR 0x00d0180eL
+#define TSU_IBPR_P1_MCAST_WR_FIFO_KICK_STRIDE 1
+#define TSU_IBPR_P1_MCAST_WR_FIFO_KICK_DEPTH 1
+
+ /* Congestion DLID cam */
+#define TSU_IBPR_P1_CONG_CAM_ADDR 0x00d02000L
+#define TSU_IBPR_P1_CONG_CAM_STRIDE 1
+#define TSU_IBPR_P1_CONG_CAM_DEPTH 32
+
+ /* Congestion Control Table Index */
+#define TSU_IBPR_P1_CONG_CCTI_ADDR 0x00d02080L
+#define TSU_IBPR_P1_CONG_CCTI_STRIDE 1
+#define TSU_IBPR_P1_CONG_CCTI_DEPTH 32
+
+ /* Congestion Control Table */
+#define TSU_IBPR_P1_CONG_CCT_ADDR 0x00d02100L
+#define TSU_IBPR_P1_CONG_CCT_STRIDE 1
+#define TSU_IBPR_P1_CONG_CCT_DEPTH 128
+
+ /* Congestion Control Table Index data */
+#define TSU_IBPR_P1_CONG_CCTI_DATA_ADDR 0x00d02180L
+#define TSU_IBPR_P1_CONG_CCTI_DATA_STRIDE 1
+#define TSU_IBPR_P1_CONG_CCTI_DATA_DEPTH 32
+
+ /*
+ * This pop register is written after data in p1 congestion log is read.
+ * Writing this register will pop the FIFO.
+ */
+#define TSU_IBPR_P1_CONGESTION_LOG_POP_ADDR 0x00d02200L
+#define TSU_IBPR_P1_CONGESTION_LOG_POP_STRIDE 1
+#define TSU_IBPR_P1_CONGESTION_LOG_POP_DEPTH 1
+
+ /* When this bit is set congestion log update from HW is enabled */
+#define TSU_IBPR_P1_CONGESTION_LOG_ENABLE_ADDR 0x00d02280L
+#define TSU_IBPR_P1_CONGESTION_LOG_ENABLE_STRIDE 1
+#define TSU_IBPR_P1_CONGESTION_LOG_ENABLE_DEPTH 1
+
+ /*
+ * When data is present, this register contains congestion log. Hardware
+ * multicast FIFO is popped when p1_congestion_log_pop is written.
+ */
+#define TSU_IBPR_P1_CONGESTION_LOG_ADDR 0x00d02300L
+#define TSU_IBPR_P1_CONGESTION_LOG_STRIDE 1
+#define TSU_IBPR_P1_CONGESTION_LOG_DEPTH 1
+
+ /* Sample interval register. */
+#define TSU_IBPR_VSWITCH1_SAMPLE_INTERVAL_ADDR 0x00d02800L
+#define TSU_IBPR_VSWITCH1_SAMPLE_INTERVAL_STRIDE 1
+#define TSU_IBPR_VSWITCH1_SAMPLE_INTERVAL_DEPTH 1
+
+ /* Sample start delay register. */
+#define TSU_IBPR_VSWITCH1_SAMPLE_START_ADDR 0x00d02802L
+#define TSU_IBPR_VSWITCH1_SAMPLE_START_STRIDE 1
+#define TSU_IBPR_VSWITCH1_SAMPLE_START_DEPTH 1
+
+ /* Sample count register. This register contain the counted values. */
+#define TSU_IBPR_VSWITCH1_SAMPLE_COUNT_ADDR 0x00d02804L
+#define TSU_IBPR_VSWITCH1_SAMPLE_COUNT_STRIDE 1
+#define TSU_IBPR_VSWITCH1_SAMPLE_COUNT_DEPTH 1
+
+ /*
+ * Sample UF register. Indicating which port this entry is counting for and
+ * what type it is counting.
+ */
+#define TSU_IBPR_VSWITCH1_SAMPLE_PORT_ADDR 0x00d02806L
+#define TSU_IBPR_VSWITCH1_SAMPLE_PORT_STRIDE 1
+#define TSU_IBPR_VSWITCH1_SAMPLE_PORT_DEPTH 1
+
+ /* Start port Sampling. */
+#define TSU_IBPR_VSWITCH1_PORTSAMPLE_START_ADDR 0x00d02808L
+#define TSU_IBPR_VSWITCH1_PORTSAMPLE_START_STRIDE 1
+#define TSU_IBPR_VSWITCH1_PORTSAMPLE_START_DEPTH 1
+
+ /* Sample status register. */
+#define TSU_IBPR_VSWITCH1_SAMPLE_STATUS_ADDR 0x00d0280aL
+#define TSU_IBPR_VSWITCH1_SAMPLE_STATUS_STRIDE 1
+#define TSU_IBPR_VSWITCH1_SAMPLE_STATUS_DEPTH 1
+
+ /* Sample interval register. */
+#define TSU_IBPR_VHCA_P1_SAMPLE_INTERVAL_ADDR 0x00d02880L
+#define TSU_IBPR_VHCA_P1_SAMPLE_INTERVAL_STRIDE 1
+#define TSU_IBPR_VHCA_P1_SAMPLE_INTERVAL_DEPTH 1
+
+ /* Sample start delay register. */
+#define TSU_IBPR_VHCA_P1_SAMPLE_START_ADDR 0x00d02882L
+#define TSU_IBPR_VHCA_P1_SAMPLE_START_STRIDE 1
+#define TSU_IBPR_VHCA_P1_SAMPLE_START_DEPTH 1
+
+ /* Sample count register. This register contain the counted values. */
+#define TSU_IBPR_VHCA_P1_SAMPLE_COUNT_ADDR 0x00d02884L
+#define TSU_IBPR_VHCA_P1_SAMPLE_COUNT_STRIDE 1
+#define TSU_IBPR_VHCA_P1_SAMPLE_COUNT_DEPTH 1
+
+ /*
+ * Sample UF register. Indicating which port this entry is counting for and
+ * what type it is counting.
+ */
+#define TSU_IBPR_VHCA_P1_SAMPLE_PORT_ADDR 0x00d02886L
+#define TSU_IBPR_VHCA_P1_SAMPLE_PORT_STRIDE 1
+#define TSU_IBPR_VHCA_P1_SAMPLE_PORT_DEPTH 1
+
+ /* Start port Sampling. */
+#define TSU_IBPR_VHCA_P1_PORTSAMPLE_START_ADDR 0x00d02888L
+#define TSU_IBPR_VHCA_P1_PORTSAMPLE_START_STRIDE 1
+#define TSU_IBPR_VHCA_P1_PORTSAMPLE_START_DEPTH 1
+
+ /* Sample status register. */
+#define TSU_IBPR_VHCA_P1_SAMPLE_STATUS_ADDR 0x00d0288aL
+#define TSU_IBPR_VHCA_P1_SAMPLE_STATUS_STRIDE 1
+#define TSU_IBPR_VHCA_P1_SAMPLE_STATUS_DEPTH 1
+
+ /* Port counter PortXmitDiscards. This is per vSwitch port [32:0]. */
+#define TSU_IBPR_VSWITCH1_XMIT_DISCARDS_ADDR 0x00d02900L
+#define TSU_IBPR_VSWITCH1_XMIT_DISCARDS_STRIDE 1
+#define TSU_IBPR_VSWITCH1_XMIT_DISCARDS_DEPTH 33
+
+ /* Port counter PortRcvSwitchRelayErrors. This is per Switch */
+#define TSU_IBPR_VSWITCH1_RCV_SWITCH_RELAY_ERRORS_ADDR 0x00d02980L
+#define TSU_IBPR_VSWITCH1_RCV_SWITCH_RELAY_ERRORS_STRIDE 1
+#define TSU_IBPR_VSWITCH1_RCV_SWITCH_RELAY_ERRORS_DEPTH 1
+
+ /* Vendor Port counter receive packets drop. This is per vSwitch. */
+#define TSU_IBPR_VSWITCH1_RCV_PKTS_DROP_ADDR 0x00d02982L
+#define TSU_IBPR_VSWITCH1_RCV_PKTS_DROP_STRIDE 1
+#define TSU_IBPR_VSWITCH1_RCV_PKTS_DROP_DEPTH 1
+
+ /* Clear portcounter port receive drop */
+#define TSU_IBPR_VSWITCH1_PORTCOUNTER_PRCVDROP_CLEAR_ADDR 0x00d02984L
+#define TSU_IBPR_VSWITCH1_PORTCOUNTER_PRCVDROP_CLEAR_STRIDE 1
+#define TSU_IBPR_VSWITCH1_PORTCOUNTER_PRCVDROP_CLEAR_DEPTH 1
+
+ /* Clear portcounter Port Receive Switch Relay Error */
+#define TSU_IBPR_VSWITCH1_PORTCOUNTER_PRSRE_CLEAR_ADDR 0x00d02986L
+#define TSU_IBPR_VSWITCH1_PORTCOUNTER_PRSRE_CLEAR_STRIDE 1
+#define TSU_IBPR_VSWITCH1_PORTCOUNTER_PRSRE_CLEAR_DEPTH 1
+
+ /* Port counter PortXmitDiscards. This is per vSwitch port. */
+#define TSU_IBPR_VHCA_P1_XMIT_DISCARDS_ADDR 0x00d02a00L
+#define TSU_IBPR_VHCA_P1_XMIT_DISCARDS_STRIDE 1
+#define TSU_IBPR_VHCA_P1_XMIT_DISCARDS_DEPTH 33
+
+ /*
+ * Port counter Port Receive data. This is per vSwitch port - not the
+ * external port.
+ */
+#define TSU_IBPR_VHCA_P1_RCV_DATA_ADDR 0x00d02a80L
+#define TSU_IBPR_VHCA_P1_RCV_DATA_STRIDE 1
+#define TSU_IBPR_VHCA_P1_RCV_DATA_DEPTH 34
+
+ /*
+ * Port counter Port Receive Packets. This is per vSwitch port - not the
+ * external port.
+ */
+#define TSU_IBPR_VHCA_P1_RCV_PKTS_ADDR 0x00d02b00L
+#define TSU_IBPR_VHCA_P1_RCV_PKTS_STRIDE 1
+#define TSU_IBPR_VHCA_P1_RCV_PKTS_DEPTH 34
+
+ /*
+ * Port counter Port Xmit data. This is per vSwitch port - not the external
+ * port.
+ */
+#define TSU_IBPR_VHCA_P1_XMIT_DATA_ADDR 0x00d02b80L
+#define TSU_IBPR_VHCA_P1_XMIT_DATA_STRIDE 1
+#define TSU_IBPR_VHCA_P1_XMIT_DATA_DEPTH 34
+
+ /*
+ * Port counter Port Xmit Packets. This is per vSwitch port - not the
+ * external port.
+ */
+#define TSU_IBPR_VHCA_P1_XMIT_PKTS_ADDR 0x00d02c00L
+#define TSU_IBPR_VHCA_P1_XMIT_PKTS_STRIDE 1
+#define TSU_IBPR_VHCA_P1_XMIT_PKTS_DEPTH 34
+
+ /*
+ * Port counter counting packets dropped (marked p_error) in Xmit path.
+ */
+#define TSU_IBPR_VHCA_P1_XMIT_PKTS_DROP_ADDR 0x00d02c80L
+#define TSU_IBPR_VHCA_P1_XMIT_PKTS_DROP_STRIDE 1
+#define TSU_IBPR_VHCA_P1_XMIT_PKTS_DROP_DEPTH 1
+
+ /* Clear portcounter Port Xmit Drop. */
+#define TSU_IBPR_VHCA_P1_PORTCOUNTER_PXDROP_CLEAR_ADDR 0x00d02c82L
+#define TSU_IBPR_VHCA_P1_PORTCOUNTER_PXDROP_CLEAR_STRIDE 1
+#define TSU_IBPR_VHCA_P1_PORTCOUNTER_PXDROP_CLEAR_DEPTH 1
+
+ /*
+ * Shared P-Key table for all UFs on this port. Number of entries valid per
+ * UF is defined by the p2_pkey_uf_stride register.
+ */
+#define TSU_IBPR_P2_PKEY_TABLE_ADDR 0x00d08000L
+#define TSU_IBPR_P2_PKEY_TABLE_STRIDE 1
+#define TSU_IBPR_P2_PKEY_TABLE_DEPTH 272
+
+ /*
+ * Size of individual P-Key tables per UF. All UFs have the same size or if
+ * set to 0, it means one common table.
+ */
+#define TSU_IBPR_P2_PKEY_UF_STRIDE_ADDR 0x00d08200L
+#define TSU_IBPR_P2_PKEY_UF_STRIDE_STRIDE 1
+#define TSU_IBPR_P2_PKEY_UF_STRIDE_DEPTH 1
+
+ /* Permission and entry table for TCP port filtering. */
+#define TSU_IBPR_P2_TCP_PERMISSION_TABLE_ADDR 0x00d08400L
+#define TSU_IBPR_P2_TCP_PERMISSION_TABLE_STRIDE 1
+#define TSU_IBPR_P2_TCP_PERMISSION_TABLE_DEPTH 272
+
+ /* Range table for the TCP Port filtering. */
+#define TSU_IBPR_P2_TCP_PORT_RANGE_TABLE_ADDR 0x00d08600L
+#define TSU_IBPR_P2_TCP_PORT_RANGE_TABLE_STRIDE 1
+#define TSU_IBPR_P2_TCP_PORT_RANGE_TABLE_DEPTH 32
+
+ /*
+ * Own LIDs base and LMC. Potentially all own LID bits come from the QP state
+ * entry. The number of bits to use is based on the LMC. Per UF register.
+ */
+#define TSU_IBPR_P2_OWN_LID_BASE_ADDR 0x00d08800L
+#define TSU_IBPR_P2_OWN_LID_BASE_STRIDE 1
+#define TSU_IBPR_P2_OWN_LID_BASE_DEPTH 34
+
+ /*
+ * Upper 64 bits of GID for port2. There are (2 * NUM_VHCA + 1) 67 GIDs per
+ * physical IB port.
+ */
+#define TSU_IBPR_P2_GID_UPPER_ADDR 0x00d08880L
+#define TSU_IBPR_P2_GID_UPPER_STRIDE 1
+#define TSU_IBPR_P2_GID_UPPER_DEPTH 67
+
+ /*
+ * Lower 64 bits of GID for port2. There are (2 * NUM_VHCA + 1) 67 GIDs per
+ * physical IB port.
+ */
+#define TSU_IBPR_P2_GID_LOWER_ADDR 0x00d08900L
+#define TSU_IBPR_P2_GID_LOWER_STRIDE 1
+#define TSU_IBPR_P2_GID_LOWER_DEPTH 67
+
+ /*
+ * GID forwarding table. The forwarding table is used to figure out if a
+ * packet should be sent in loopback or not. There are (2 * NUM_VHCA + 1) 67
+ * GIDs per physical IB port.
+ */
+#define TSU_IBPR_P2_GID_FORWARDING_TABLE_ADDR 0x00d08980L
+#define TSU_IBPR_P2_GID_FORWARDING_TABLE_STRIDE 1
+#define TSU_IBPR_P2_GID_FORWARDING_TABLE_DEPTH 67
+
+ /*
+ * One bit ber UF. If set for the UF, the upper 64bits are ignored in the
+ * DGID check.
+ */
+#define TSU_IBPR_P2_IGNORE_UPPER_64B_DGID_CHECK_ADDR 0x00d08a00L
+#define TSU_IBPR_P2_IGNORE_UPPER_64B_DGID_CHECK_STRIDE 1
+#define TSU_IBPR_P2_IGNORE_UPPER_64B_DGID_CHECK_DEPTH 1
+
+ /* Default vSwitch port for vSwitch2. */
+#define TSU_IBPR_P2_DEFAULT_VSWITCH_PORT_ADDR 0x00d08a80L
+#define TSU_IBPR_P2_DEFAULT_VSWITCH_PORT_STRIDE 1
+#define TSU_IBPR_P2_DEFAULT_VSWITCH_PORT_DEPTH 1
+
+ /* Default SM HCA. Indicating which vHCA to send SM packets to. */
+#define TSU_IBPR_P2_DEFAULT_SM_HCA_ADDR 0x00d08b00L
+#define TSU_IBPR_P2_DEFAULT_SM_HCA_STRIDE 1
+#define TSU_IBPR_P2_DEFAULT_SM_HCA_DEPTH 1
+
+ /*
+ * When a bit is set, the TSU will forward the particular management class to
+ * EPS-C. Per UF0-UF32.
+ */
+#define TSU_IBPR_P2_GSI_FORWARDING_TABLE_ADDR 0x00d08b80L
+#define TSU_IBPR_P2_GSI_FORWARDING_TABLE_STRIDE 1
+#define TSU_IBPR_P2_GSI_FORWARDING_TABLE_DEPTH 33
+
+ /*
+ * Register with a bit per UF/VHCA indicating if the UF/VHCA is allowed to
+ * send SMPs.
+ */
+#define TSU_IBPR_P2_SMP_ALLOWED_ADDR 0x00d09000L
+#define TSU_IBPR_P2_SMP_ALLOWED_STRIDE 1
+#define TSU_IBPR_P2_SMP_ALLOWED_DEPTH 1
+
+ /*
+ * Status register with a bit per UF/VHCA indicating if an UF/VHCA SMP not
+ * allowed packet drop status is cleared.
+ */
+#define TSU_IBPR_P2_SMP_ALLOWED_DROP_STATUS_CLEAR_ADDR 0x00d09080L
+#define TSU_IBPR_P2_SMP_ALLOWED_DROP_STATUS_CLEAR_STRIDE 1
+#define TSU_IBPR_P2_SMP_ALLOWED_DROP_STATUS_CLEAR_DEPTH 1
+
+ /*
+ * Status register with a bit per UF/VHCA indicating if an UF/VHCA SMP not
+ * allowed packet is dropped.
+ */
+#define TSU_IBPR_P2_SMP_ALLOWED_DROP_STATUS_ADDR 0x00d09100L
+#define TSU_IBPR_P2_SMP_ALLOWED_DROP_STATUS_STRIDE 1
+#define TSU_IBPR_P2_SMP_ALLOWED_DROP_STATUS_DEPTH 1
+
+ /* Rx choke register */
+#define TSU_IBPR_P2_RX_CHOKE_ADDR 0x00d09180L
+#define TSU_IBPR_P2_RX_CHOKE_STRIDE 1
+#define TSU_IBPR_P2_RX_CHOKE_DEPTH 1
+
+ /*
+ * Get vlink state for the vHCA and the vSwitch. It is up to the firmware to
+ * report correct physical link states when one side is set to disabled and
+ * the other side is down.
+ */
+#define TSU_IBPR_P2_VLINK_STATE_ADDR 0x00d09200L
+#define TSU_IBPR_P2_VLINK_STATE_STRIDE 1
+#define TSU_IBPR_P2_VLINK_STATE_DEPTH 33
+
+ /*
+ * When data is present, this register should be read for processing.
+ * Hardware multicast FIFO is popped when p2_mcast_pop is written.
+ */
+#define TSU_IBPR_P2_MCAST_GID_UPPER_ADDR 0x00d09800L
+#define TSU_IBPR_P2_MCAST_GID_UPPER_STRIDE 1
+#define TSU_IBPR_P2_MCAST_GID_UPPER_DEPTH 1
+
+ /*
+ * When data is present, this register should be read for processing.
+ * Hardware multicast FIFO is popped when p2_mcast_pop is written.
+ */
+#define TSU_IBPR_P2_MCAST_GID_LOWER_ADDR 0x00d09802L
+#define TSU_IBPR_P2_MCAST_GID_LOWER_STRIDE 1
+#define TSU_IBPR_P2_MCAST_GID_LOWER_DEPTH 1
+
+ /*
+ * When data is present, this register should be read for processing.
+ * Hardware multicast FIFO is popped when p2_mcast_pop is written.
+ */
+#define TSU_IBPR_P2_MCAST_GIDHASH_LID_ADDR 0x00d09804L
+#define TSU_IBPR_P2_MCAST_GIDHASH_LID_STRIDE 1
+#define TSU_IBPR_P2_MCAST_GIDHASH_LID_DEPTH 1
+
+ /*
+ * This pop register is written after data in p2_mcast_gid_upper,
+ * p2_mcast_gid_lower and p2_mcast_lid is read. Writing this register will
+ * pop the FIFO.
+ */
+#define TSU_IBPR_P2_MCAST_POP_ADDR 0x00d09806L
+#define TSU_IBPR_P2_MCAST_POP_STRIDE 1
+#define TSU_IBPR_P2_MCAST_POP_DEPTH 1
+
+ /*
+ * This registers indicate how many multicast packets this port can hold
+ * before starting drop packets.
+ */
+#define TSU_IBPR_P2_MCAST_MAX_PKTS_ADDR 0x00d09808L
+#define TSU_IBPR_P2_MCAST_MAX_PKTS_STRIDE 1
+#define TSU_IBPR_P2_MCAST_MAX_PKTS_DEPTH 1
+
+ /*
+ * This register contain the credit for writing to the CSR FIFO for multicast
+ * packets.
+ */
+#define TSU_IBPR_P2_MCAST_WR_CREDIT_ADDR 0x00d0980aL
+#define TSU_IBPR_P2_MCAST_WR_CREDIT_STRIDE 1
+#define TSU_IBPR_P2_MCAST_WR_CREDIT_DEPTH 1
+
+ /* Write to multicast FIFO. */
+#define TSU_IBPR_P2_MCAST_WR_FIFO_ADDR 0x00d0980cL
+#define TSU_IBPR_P2_MCAST_WR_FIFO_STRIDE 1
+#define TSU_IBPR_P2_MCAST_WR_FIFO_DEPTH 1
+
+ /* Kick multicast FIFO - data is valid in the multicast FIFO. */
+#define TSU_IBPR_P2_MCAST_WR_FIFO_KICK_ADDR 0x00d0980eL
+#define TSU_IBPR_P2_MCAST_WR_FIFO_KICK_STRIDE 1
+#define TSU_IBPR_P2_MCAST_WR_FIFO_KICK_DEPTH 1
+
+ /* Congestion DLID cam */
+#define TSU_IBPR_P2_CONG_CAM_ADDR 0x00d0a000L
+#define TSU_IBPR_P2_CONG_CAM_STRIDE 1
+#define TSU_IBPR_P2_CONG_CAM_DEPTH 32
+
+ /* Congestion Control Table Index */
+#define TSU_IBPR_P2_CONG_CCTI_ADDR 0x00d0a080L
+#define TSU_IBPR_P2_CONG_CCTI_STRIDE 1
+#define TSU_IBPR_P2_CONG_CCTI_DEPTH 32
+
+ /* Congestion Control Table */
+#define TSU_IBPR_P2_CONG_CCT_ADDR 0x00d0a100L
+#define TSU_IBPR_P2_CONG_CCT_STRIDE 1
+#define TSU_IBPR_P2_CONG_CCT_DEPTH 128
+
+ /* Congestion Control Table Index data */
+#define TSU_IBPR_P2_CONG_CCTI_DATA_ADDR 0x00d0a180L
+#define TSU_IBPR_P2_CONG_CCTI_DATA_STRIDE 1
+#define TSU_IBPR_P2_CONG_CCTI_DATA_DEPTH 32
+
+ /*
+ * This pop register is written after data in p2 congestion log is read.
+ * Writing this register will pop the FIFO.
+ */
+#define TSU_IBPR_P2_CONGESTION_LOG_POP_ADDR 0x00d0a200L
+#define TSU_IBPR_P2_CONGESTION_LOG_POP_STRIDE 1
+#define TSU_IBPR_P2_CONGESTION_LOG_POP_DEPTH 1
+
+ /* When this bit is set congestion log update from HW is enabled */
+#define TSU_IBPR_P2_CONGESTION_LOG_ENABLE_ADDR 0x00d0a280L
+#define TSU_IBPR_P2_CONGESTION_LOG_ENABLE_STRIDE 1
+#define TSU_IBPR_P2_CONGESTION_LOG_ENABLE_DEPTH 1
+
+ /*
+ * When data is present, this register contains congestion log. Hardware
+ * multicast FIFO is popped when p2_congestion_log_pop is written.
+ */
+#define TSU_IBPR_P2_CONGESTION_LOG_ADDR 0x00d0a300L
+#define TSU_IBPR_P2_CONGESTION_LOG_STRIDE 1
+#define TSU_IBPR_P2_CONGESTION_LOG_DEPTH 1
+
+ /* Sample interval register. */
+#define TSU_IBPR_VSWITCH2_SAMPLE_INTERVAL_ADDR 0x00d0a800L
+#define TSU_IBPR_VSWITCH2_SAMPLE_INTERVAL_STRIDE 1
+#define TSU_IBPR_VSWITCH2_SAMPLE_INTERVAL_DEPTH 1
+
+ /* Sample start delay register. */
+#define TSU_IBPR_VSWITCH2_SAMPLE_START_ADDR 0x00d0a802L
+#define TSU_IBPR_VSWITCH2_SAMPLE_START_STRIDE 1
+#define TSU_IBPR_VSWITCH2_SAMPLE_START_DEPTH 1
+
+ /* Sample count register. This register contain the counted values. */
+#define TSU_IBPR_VSWITCH2_SAMPLE_COUNT_ADDR 0x00d0a804L
+#define TSU_IBPR_VSWITCH2_SAMPLE_COUNT_STRIDE 1
+#define TSU_IBPR_VSWITCH2_SAMPLE_COUNT_DEPTH 1
+
+ /*
+ * Sample UF register. Indicating which UF this entry is counting for and
+ * what type it is counting.
+ */
+#define TSU_IBPR_VSWITCH2_SAMPLE_PORT_ADDR 0x00d0a806L
+#define TSU_IBPR_VSWITCH2_SAMPLE_PORT_STRIDE 1
+#define TSU_IBPR_VSWITCH2_SAMPLE_PORT_DEPTH 1
+
+ /* Start port Sampling. */
+#define TSU_IBPR_VSWITCH2_PORTSAMPLE_START_ADDR 0x00d0a808L
+#define TSU_IBPR_VSWITCH2_PORTSAMPLE_START_STRIDE 1
+#define TSU_IBPR_VSWITCH2_PORTSAMPLE_START_DEPTH 1
+
+ /* Sample status register. */
+#define TSU_IBPR_VSWITCH2_SAMPLE_STATUS_ADDR 0x00d0a80aL
+#define TSU_IBPR_VSWITCH2_SAMPLE_STATUS_STRIDE 1
+#define TSU_IBPR_VSWITCH2_SAMPLE_STATUS_DEPTH 1
+
+ /* Sample interval register. */
+#define TSU_IBPR_VHCA_P2_SAMPLE_INTERVAL_ADDR 0x00d0a880L
+#define TSU_IBPR_VHCA_P2_SAMPLE_INTERVAL_STRIDE 1
+#define TSU_IBPR_VHCA_P2_SAMPLE_INTERVAL_DEPTH 1
+
+ /* Sample start delay register. */
+#define TSU_IBPR_VHCA_P2_SAMPLE_START_ADDR 0x00d0a882L
+#define TSU_IBPR_VHCA_P2_SAMPLE_START_STRIDE 1
+#define TSU_IBPR_VHCA_P2_SAMPLE_START_DEPTH 1
+
+ /* Sample count register. This register contain the counted values. */
+#define TSU_IBPR_VHCA_P2_SAMPLE_COUNT_ADDR 0x00d0a884L
+#define TSU_IBPR_VHCA_P2_SAMPLE_COUNT_STRIDE 1
+#define TSU_IBPR_VHCA_P2_SAMPLE_COUNT_DEPTH 1
+
+ /*
+ * Sample UF register. Indicating which port this entry is counting for and
+ * what type it is counting.
+ */
+#define TSU_IBPR_VHCA_P2_SAMPLE_PORT_ADDR 0x00d0a886L
+#define TSU_IBPR_VHCA_P2_SAMPLE_PORT_STRIDE 1
+#define TSU_IBPR_VHCA_P2_SAMPLE_PORT_DEPTH 1
+
+ /* Start port Sampling. */
+#define TSU_IBPR_VHCA_P2_PORTSAMPLE_START_ADDR 0x00d0a888L
+#define TSU_IBPR_VHCA_P2_PORTSAMPLE_START_STRIDE 1
+#define TSU_IBPR_VHCA_P2_PORTSAMPLE_START_DEPTH 1
+
+ /* Sample status register. */
+#define TSU_IBPR_VHCA_P2_SAMPLE_STATUS_ADDR 0x00d0a88aL
+#define TSU_IBPR_VHCA_P2_SAMPLE_STATUS_STRIDE 1
+#define TSU_IBPR_VHCA_P2_SAMPLE_STATUS_DEPTH 1
+
+ /* Port counter PortXmitDiscards. This is per vSwitch port [32:0]. */
+#define TSU_IBPR_VSWITCH2_XMIT_DISCARDS_ADDR 0x00d0a900L
+#define TSU_IBPR_VSWITCH2_XMIT_DISCARDS_STRIDE 1
+#define TSU_IBPR_VSWITCH2_XMIT_DISCARDS_DEPTH 33
+
+ /* Port counter PortRcvSwitchRelayErrors. This is per Switch */
+#define TSU_IBPR_VSWITCH2_RCV_SWITCH_RELAY_ERRORS_ADDR 0x00d0a980L
+#define TSU_IBPR_VSWITCH2_RCV_SWITCH_RELAY_ERRORS_STRIDE 1
+#define TSU_IBPR_VSWITCH2_RCV_SWITCH_RELAY_ERRORS_DEPTH 1
+
+ /* Vendor Port counter receive packets drop. This is per vSwitch. */
+#define TSU_IBPR_VSWITCH2_RCV_PKTS_DROP_ADDR 0x00d0a982L
+#define TSU_IBPR_VSWITCH2_RCV_PKTS_DROP_STRIDE 1
+#define TSU_IBPR_VSWITCH2_RCV_PKTS_DROP_DEPTH 1
+
+ /* Clear portcounter port receive drop */
+#define TSU_IBPR_VSWITCH2_PORTCOUNTER_PRCVDROP_CLEAR_ADDR 0x00d0a984L
+#define TSU_IBPR_VSWITCH2_PORTCOUNTER_PRCVDROP_CLEAR_STRIDE 1
+#define TSU_IBPR_VSWITCH2_PORTCOUNTER_PRCVDROP_CLEAR_DEPTH 1
+
+ /* Clear portcounter Port Receive Switch Relay Error */
+#define TSU_IBPR_VSWITCH2_PORTCOUNTER_PRSRE_CLEAR_ADDR 0x00d0a986L
+#define TSU_IBPR_VSWITCH2_PORTCOUNTER_PRSRE_CLEAR_STRIDE 1
+#define TSU_IBPR_VSWITCH2_PORTCOUNTER_PRSRE_CLEAR_DEPTH 1
+
+ /* Port counter PortXmitDiscards. This is per vSwitch port. */
+#define TSU_IBPR_VHCA_P2_XMIT_DISCARDS_ADDR 0x00d0b000L
+#define TSU_IBPR_VHCA_P2_XMIT_DISCARDS_STRIDE 1
+#define TSU_IBPR_VHCA_P2_XMIT_DISCARDS_DEPTH 33
+
+ /*
+ * Port counter Port Receive data. This is per vSwitch port - not the
+ * external port.
+ */
+#define TSU_IBPR_VHCA_P2_RCV_DATA_ADDR 0x00d0b080L
+#define TSU_IBPR_VHCA_P2_RCV_DATA_STRIDE 1
+#define TSU_IBPR_VHCA_P2_RCV_DATA_DEPTH 34
+
+ /*
+ * Port counter Port Receive Packets. This is per vSwitch port - not the
+ * external port.
+ */
+#define TSU_IBPR_VHCA_P2_RCV_PKTS_ADDR 0x00d0b100L
+#define TSU_IBPR_VHCA_P2_RCV_PKTS_STRIDE 1
+#define TSU_IBPR_VHCA_P2_RCV_PKTS_DEPTH 34
+
+ /*
+ * Port counter Port Xmit data. This is per vSwitch port - not the external
+ * port.
+ */
+#define TSU_IBPR_VHCA_P2_XMIT_DATA_ADDR 0x00d0b180L
+#define TSU_IBPR_VHCA_P2_XMIT_DATA_STRIDE 1
+#define TSU_IBPR_VHCA_P2_XMIT_DATA_DEPTH 34
+
+ /*
+ * Port counter Port Xmit Packets. This is per vSwitch port - not the
+ * external port.
+ */
+#define TSU_IBPR_VHCA_P2_XMIT_PKTS_ADDR 0x00d0b200L
+#define TSU_IBPR_VHCA_P2_XMIT_PKTS_STRIDE 1
+#define TSU_IBPR_VHCA_P2_XMIT_PKTS_DEPTH 34
+
+ /*
+ * Port counter counting packets dropped (marked p_error) in Xmit path.
+ */
+#define TSU_IBPR_VHCA_P2_XMIT_PKTS_DROP_ADDR 0x00d0b280L
+#define TSU_IBPR_VHCA_P2_XMIT_PKTS_DROP_STRIDE 1
+#define TSU_IBPR_VHCA_P2_XMIT_PKTS_DROP_DEPTH 1
+
+ /* Clear portcounter Port Xmit Drop. */
+#define TSU_IBPR_VHCA_P2_PORTCOUNTER_PXDROP_CLEAR_ADDR 0x00d0b282L
+#define TSU_IBPR_VHCA_P2_PORTCOUNTER_PXDROP_CLEAR_STRIDE 1
+#define TSU_IBPR_VHCA_P2_PORTCOUNTER_PXDROP_CLEAR_DEPTH 1
+
+ /* Set link state for the vHCA or the vSwitch. */
+#define TSU_IBPR_SET_VLINK_STATE_ADDR 0x00d10000L
+#define TSU_IBPR_SET_VLINK_STATE_STRIDE 1
+#define TSU_IBPR_SET_VLINK_STATE_DEPTH 1
+
+ /* link state for the vHCA or the vSwitch. */
+#define TSU_IBPR_VLINK_STATE_REGISTER_ADDR 0x00d10002L
+#define TSU_IBPR_VLINK_STATE_REGISTER_STRIDE 1
+#define TSU_IBPR_VLINK_STATE_REGISTER_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_IBPR_INT_STATUS_ADDR 0x00d10004L
+#define TSU_IBPR_INT_STATUS_STRIDE 1
+#define TSU_IBPR_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_IBPR_INT_MASK_ADDR 0x00d10006L
+#define TSU_IBPR_INT_MASK_STRIDE 1
+#define TSU_IBPR_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_IBPR_INT_PRI_ADDR 0x00d10008L
+#define TSU_IBPR_INT_PRI_STRIDE 1
+#define TSU_IBPR_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_IBPR_INT_STATUS_CLEAR_ADDR 0x00d1000aL
+#define TSU_IBPR_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_IBPR_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_IBPR_INT_STATUS_CLEAR_KICK_ADDR 0x00d1000cL
+#define TSU_IBPR_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_IBPR_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /* Trace buffer setup */
+#define TSU_IBPR_TRACE_BUFFER_SETUP_ADDR 0x00d10080L
+#define TSU_IBPR_TRACE_BUFFER_SETUP_STRIDE 1
+#define TSU_IBPR_TRACE_BUFFER_SETUP_DEPTH 1
+
+ /* Trace buffer Store qualifier1 */
+#define TSU_IBPR_TRACE_STORE_QUALIFIER1_ADDR 0x00d10082L
+#define TSU_IBPR_TRACE_STORE_QUALIFIER1_STRIDE 1
+#define TSU_IBPR_TRACE_STORE_QUALIFIER1_DEPTH 1
+
+ /* Trace buffer Store qualifier2 */
+#define TSU_IBPR_TRACE_STORE_QUALIFIER2_ADDR 0x00d10084L
+#define TSU_IBPR_TRACE_STORE_QUALIFIER2_STRIDE 1
+#define TSU_IBPR_TRACE_STORE_QUALIFIER2_DEPTH 1
+
+ /* Trace buffer Store qualifier1 mask */
+#define TSU_IBPR_TRACE_STORE_QUALIFIER1_MASK_ADDR 0x00d10086L
+#define TSU_IBPR_TRACE_STORE_QUALIFIER1_MASK_STRIDE 1
+#define TSU_IBPR_TRACE_STORE_QUALIFIER1_MASK_DEPTH 1
+
+ /* Trace buffer Store qualifier2 mask */
+#define TSU_IBPR_TRACE_STORE_QUALIFIER2_MASK_ADDR 0x00d10088L
+#define TSU_IBPR_TRACE_STORE_QUALIFIER2_MASK_STRIDE 1
+#define TSU_IBPR_TRACE_STORE_QUALIFIER2_MASK_DEPTH 1
+
+ /* Trace buffer trigger1 */
+#define TSU_IBPR_TRACE_TRIGGER1_ADDR 0x00d1008aL
+#define TSU_IBPR_TRACE_TRIGGER1_STRIDE 1
+#define TSU_IBPR_TRACE_TRIGGER1_DEPTH 1
+
+ /* Trace buffer trigger2 */
+#define TSU_IBPR_TRACE_TRIGGER2_ADDR 0x00d1008cL
+#define TSU_IBPR_TRACE_TRIGGER2_STRIDE 1
+#define TSU_IBPR_TRACE_TRIGGER2_DEPTH 1
+
+ /* Trace buffer trigger1 mask */
+#define TSU_IBPR_TRACE_TRIGGER1_MASK_ADDR 0x00d1008eL
+#define TSU_IBPR_TRACE_TRIGGER1_MASK_STRIDE 1
+#define TSU_IBPR_TRACE_TRIGGER1_MASK_DEPTH 1
+
+ /* Trace buffer trigger2 mask */
+#define TSU_IBPR_TRACE_TRIGGER2_MASK_ADDR 0x00d10090L
+#define TSU_IBPR_TRACE_TRIGGER2_MASK_STRIDE 1
+#define TSU_IBPR_TRACE_TRIGGER2_MASK_DEPTH 1
+
+ /* Start trace buffer */
+#define TSU_IBPR_TRACE_START_ADDR 0x00d10092L
+#define TSU_IBPR_TRACE_START_STRIDE 1
+#define TSU_IBPR_TRACE_START_DEPTH 1
+
+ /* Stop trace buffer */
+#define TSU_IBPR_TRACE_STOP_ADDR 0x00d10094L
+#define TSU_IBPR_TRACE_STOP_STRIDE 1
+#define TSU_IBPR_TRACE_STOP_DEPTH 1
+
+ /* Trace buffer status */
+#define TSU_IBPR_TRACE_BUFFER_STATUS_ADDR 0x00d10096L
+#define TSU_IBPR_TRACE_BUFFER_STATUS_STRIDE 1
+#define TSU_IBPR_TRACE_BUFFER_STATUS_DEPTH 1
+
+ /* Trace buffer */
+#define TSU_IBPR_TRACE_BUFFER_ADDR 0x00d14000L
+#define TSU_IBPR_TRACE_BUFFER_STRIDE 1
+#define TSU_IBPR_TRACE_BUFFER_DEPTH 16384
+
+ /* Trace buffer assoc info */
+#define TSU_IBPR_TRACE_BUFFER_ASSOC_INFO_ADDR 0x00d18000L
+#define TSU_IBPR_TRACE_BUFFER_ASSOC_INFO_STRIDE 1
+#define TSU_IBPR_TRACE_BUFFER_ASSOC_INFO_DEPTH 16384
+
+ /* Debug */
+#define TSU_IBPR_TRACE_BUFFER_DEBUG_ADDR 0x00d1c000L
+#define TSU_IBPR_TRACE_BUFFER_DEBUG_STRIDE 1
+#define TSU_IBPR_TRACE_BUFFER_DEBUG_DEPTH 16384
+
+ /*
+ * Per vHCA (UF0-32) register. This table contain valid RSS combinations to
+ * calculate for this UF.
+ */
+#define TSU_IBPR_RSS_CONTROL_ADDR 0x00d20000L
+#define TSU_IBPR_RSS_CONTROL_STRIDE 1
+#define TSU_IBPR_RSS_CONTROL_DEPTH 33
+
+ /* 16B Secret key for RSS generation for IPv4. */
+#define TSU_IBPR_RSS_IPV4_SECRET_KEY_ADDR 0x00d20080L
+#define TSU_IBPR_RSS_IPV4_SECRET_KEY_STRIDE 1
+#define TSU_IBPR_RSS_IPV4_SECRET_KEY_DEPTH 2
+
+ /* 40B Secret key for RSS generation for IPv6. */
+#define TSU_IBPR_RSS_IPV6_SECRET_KEY_ADDR 0x00d20090L
+#define TSU_IBPR_RSS_IPV6_SECRET_KEY_STRIDE 1
+#define TSU_IBPR_RSS_IPV6_SECRET_KEY_DEPTH 5
+
+ /* Per vHCA + EPS-C ethernet MAC address register. */
+#define TSU_IBPR_P1_EOIB_MAC1_ADDR 0x00d20100L
+#define TSU_IBPR_P1_EOIB_MAC1_STRIDE 1
+#define TSU_IBPR_P1_EOIB_MAC1_DEPTH 34
+
+ /* Per vHCA + EPS-C ethernet MAC address register. */
+#define TSU_IBPR_P1_EOIB_MAC2_ADDR 0x00d20180L
+#define TSU_IBPR_P1_EOIB_MAC2_STRIDE 1
+#define TSU_IBPR_P1_EOIB_MAC2_DEPTH 34
+
+ /* Per vHCA + EPS-C ethernet MAC address register. */
+#define TSU_IBPR_P2_EOIB_MAC1_ADDR 0x00d20200L
+#define TSU_IBPR_P2_EOIB_MAC1_STRIDE 1
+#define TSU_IBPR_P2_EOIB_MAC1_DEPTH 34
+
+ /* Per vHCA + EPS-C ethernet MAC address register. */
+#define TSU_IBPR_P2_EOIB_MAC2_ADDR 0x00d20280L
+#define TSU_IBPR_P2_EOIB_MAC2_STRIDE 1
+#define TSU_IBPR_P2_EOIB_MAC2_DEPTH 34
+
+ /* Per vHCA + EPS-C ethernet control register. */
+#define TSU_IBPR_EOIB_CONTROL_ADDR 0x00d20300L
+#define TSU_IBPR_EOIB_CONTROL_STRIDE 1
+#define TSU_IBPR_EOIB_CONTROL_DEPTH 34
+
+ /* Per vHCA + EPS-C DMAC seed register. */
+#define TSU_IBPR_DMAC_SEED_ADDR 0x00d20380L
+#define TSU_IBPR_DMAC_SEED_STRIDE 1
+#define TSU_IBPR_DMAC_SEED_DEPTH 34
+
+ /* Per vHCA + EPS-C VLAN EtherTypes register. */
+#define TSU_IBPR_EOIB_VLAN_ETHERTYPES_1_ADDR 0x00d20400L
+#define TSU_IBPR_EOIB_VLAN_ETHERTYPES_1_STRIDE 1
+#define TSU_IBPR_EOIB_VLAN_ETHERTYPES_1_DEPTH 1
+
+ /* Per vHCA + EPS-C VLAN EtherTypes register. */
+#define TSU_IBPR_EOIB_VLAN_ETHERTYPES_2_ADDR 0x00d20480L
+#define TSU_IBPR_EOIB_VLAN_ETHERTYPES_2_STRIDE 1
+#define TSU_IBPR_EOIB_VLAN_ETHERTYPES_2_DEPTH 1
+
+ /* Per vHCA PF control register. */
+#define TSU_IBPR_EOIB_PF_CONTROL_ADDR 0x00d20500L
+#define TSU_IBPR_EOIB_PF_CONTROL_STRIDE 1
+#define TSU_IBPR_EOIB_PF_CONTROL_DEPTH 34
+
+ /* Common unicast overflow table for all vHCAs. */
+#define TSU_IBPR_EOIB_UNICAST_OVERFLOW_TABLE_ADDR 0x00d20580L
+#define TSU_IBPR_EOIB_UNICAST_OVERFLOW_TABLE_STRIDE 1
+#define TSU_IBPR_EOIB_UNICAST_OVERFLOW_TABLE_DEPTH 64
+
+ /* Common multicast table for all VHCAs. */
+#define TSU_IBPR_EOIB_MULTICAST_TABLE_ADDR 0x00d20600L
+#define TSU_IBPR_EOIB_MULTICAST_TABLE_STRIDE 1
+#define TSU_IBPR_EOIB_MULTICAST_TABLE_DEPTH 64
+
+ /*
+ * Per vHCA + EPS-C VID table. There are 64 entries per UF. 4096b * 34 (64x34
+ * entries).
+ */
+#define TSU_IBPR_EOIB_VID_TABLE_ADDR 0x00d21000L
+#define TSU_IBPR_EOIB_VID_TABLE_STRIDE 1
+#define TSU_IBPR_EOIB_VID_TABLE_DEPTH 2176
+
+ /*
+ * Header split register indicating what EoIB headers to try splitting at.
+ */
+#define TSU_IBPR_HDR_SPLIT_EOIB_ADDR 0x00d22000L
+#define TSU_IBPR_HDR_SPLIT_EOIB_STRIDE 1
+#define TSU_IBPR_HDR_SPLIT_EOIB_DEPTH 33
+
+ /*
+ * Header split register indicating what IPoIB headers to try splitting at
+ * for UD transport.
+ */
+#define TSU_IBPR_HDR_SPLIT_IPOIB_UD_ADDR 0x00d22080L
+#define TSU_IBPR_HDR_SPLIT_IPOIB_UD_STRIDE 1
+#define TSU_IBPR_HDR_SPLIT_IPOIB_UD_DEPTH 33
+
+ /* Legal ether type. */
+#define TSU_IBPR_LEGAL_ETHER_TYPE_ADDR 0x00d22100L
+#define TSU_IBPR_LEGAL_ETHER_TYPE_STRIDE 1
+#define TSU_IBPR_LEGAL_ETHER_TYPE_DEPTH 2
+
+ /*
+ * Legal extensions for IPv6. 256 bits per UF. Table size is then 4*NUM_UF
+ * (should be 34)
+ */
+#define TSU_IBPR_IPV6_LEGAL_EXTENSION_HEADER_ADDR 0x00d22200L
+#define TSU_IBPR_IPV6_LEGAL_EXTENSION_HEADER_STRIDE 1
+#define TSU_IBPR_IPV6_LEGAL_EXTENSION_HEADER_DEPTH 4
+
+ /* Max ethernet frame size typically 1500 or 1535 */
+#define TSU_IBPR_MAX_ETH_FRAME_ADDR 0x00d22300L
+#define TSU_IBPR_MAX_ETH_FRAME_STRIDE 1
+#define TSU_IBPR_MAX_ETH_FRAME_DEPTH 1
+
+ /* bypass offload */
+#define TSU_IBPR_BYPASS_OFFLOAD_ADDR 0x00d22320L
+#define TSU_IBPR_BYPASS_OFFLOAD_STRIDE 1
+#define TSU_IBPR_BYPASS_OFFLOAD_DEPTH 1
+
+ /* debug signals */
+#define TSU_IBPR_IBPR_DEBUG_ADDR 0x00d22340L
+#define TSU_IBPR_IBPR_DEBUG_STRIDE 1
+#define TSU_IBPR_IBPR_DEBUG_DEPTH 1
+
+ /*
+ * Base address registers per UF for software owned descriptor portion of
+ * send queue descriptors.
+ */
+#define TSU_SQS_SQ_BASE_ADDR_SW_0_ADDR 0x00e00000L
+#define TSU_SQS_SQ_BASE_ADDR_SW_0_STRIDE 1
+#define TSU_SQS_SQ_BASE_ADDR_SW_0_DEPTH 34
+
+ /*
+ * Base address registers per UF for software owned descriptor portion of
+ * send queue descriptors.
+ */
+#define TSU_SQS_SQ_BASE_ADDR_SW_1_ADDR 0x00e00040L
+#define TSU_SQS_SQ_BASE_ADDR_SW_1_STRIDE 1
+#define TSU_SQS_SQ_BASE_ADDR_SW_1_DEPTH 34
+
+ /*
+ * Base address registers per UF for software owned descriptor portion of
+ * send queue descriptors.
+ */
+#define TSU_SQS_SQ_BASE_ADDR_SW_2_ADDR 0x00e00080L
+#define TSU_SQS_SQ_BASE_ADDR_SW_2_STRIDE 1
+#define TSU_SQS_SQ_BASE_ADDR_SW_2_DEPTH 34
+
+ /*
+ * Base address registers per UF for hardware owned descriptor portion of
+ * send queue descriptors.
+ */
+#define TSU_SQS_SQ_BASE_ADDR_HW_0_ADDR 0x00e00100L
+#define TSU_SQS_SQ_BASE_ADDR_HW_0_STRIDE 1
+#define TSU_SQS_SQ_BASE_ADDR_HW_0_DEPTH 34
+
+ /*
+ * Base address registers per UF for hardware owned descriptor portion of
+ * send queue descriptors.
+ */
+#define TSU_SQS_SQ_BASE_ADDR_HW_1_ADDR 0x00e00140L
+#define TSU_SQS_SQ_BASE_ADDR_HW_1_STRIDE 1
+#define TSU_SQS_SQ_BASE_ADDR_HW_1_DEPTH 34
+
+ /*
+ * Base address registers per UF for hardware owned descriptor portion of
+ * send queue descriptors.
+ */
+#define TSU_SQS_SQ_BASE_ADDR_HW_2_ADDR 0x00e00180L
+#define TSU_SQS_SQ_BASE_ADDR_HW_2_STRIDE 1
+#define TSU_SQS_SQ_BASE_ADDR_HW_2_DEPTH 34
+
+ /*
+ * SQS list table is used to program the list number to associate with UF.
+ * Address is list number and data is UF. A single UF can allocate multiple
+ * lists.
+ */
+#define TSU_SQS_SQS_LIST_TABLE_ADDR 0x00e00200L
+#define TSU_SQS_SQS_LIST_TABLE_STRIDE 1
+#define TSU_SQS_SQS_LIST_TABLE_DEPTH 68
+
+ /*
+ * This register must be set and the kick register is written in order to
+ * start the operation.
+ */
+#define TSU_SQS_UF_CONTROL_ADDR 0x00e00280L
+#define TSU_SQS_UF_CONTROL_STRIDE 1
+#define TSU_SQS_UF_CONTROL_DEPTH 1
+
+ /* Starts operation defined in uf_control. */
+#define TSU_SQS_UF_CONTROL_KICK_ADDR 0x00e00281L
+#define TSU_SQS_UF_CONTROL_KICK_STRIDE 1
+#define TSU_SQS_UF_CONTROL_KICK_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_SQS_INT_STATUS_ADDR 0x00e00282L
+#define TSU_SQS_INT_STATUS_STRIDE 1
+#define TSU_SQS_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_SQS_INT_MASK_ADDR 0x00e00283L
+#define TSU_SQS_INT_MASK_STRIDE 1
+#define TSU_SQS_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_SQS_INT_PRI_ADDR 0x00e00284L
+#define TSU_SQS_INT_PRI_STRIDE 1
+#define TSU_SQS_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_SQS_INT_STATUS_CLEAR_ADDR 0x00e00285L
+#define TSU_SQS_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_SQS_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_SQS_INT_STATUS_CLEAR_KICK_ADDR 0x00e00286L
+#define TSU_SQS_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_SQS_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /* Address: SQS list number. Flush status. */
+#define TSU_SQS_SQS_LIST_STATUS0_ADDR 0x00e00300L
+#define TSU_SQS_SQS_LIST_STATUS0_STRIDE 1
+#define TSU_SQS_SQS_LIST_STATUS0_DEPTH 68
+
+ /*
+ * Address: SQS list number. Set when the PCIe response has error on the
+ * descriptor read.
+ */
+#define TSU_SQS_SQS_LIST_STATUS1_ADDR 0x00e00380L
+#define TSU_SQS_SQS_LIST_STATUS1_STRIDE 1
+#define TSU_SQS_SQS_LIST_STATUS1_DEPTH 68
+
+ /*
+ * Hash mask and shift control. XOR width is based on the log 2 of number of
+ * list for that UF.
+ */
+#define TSU_SQS_HASH_CTRL_ADDR 0x00e00400L
+#define TSU_SQS_HASH_CTRL_STRIDE 1
+#define TSU_SQS_HASH_CTRL_DEPTH 4
+
+ /*
+ * Disble Atomic cmp and swap for the QP next pointer null check. If set,
+ * hardware generates read-then-write to update the QP next pointer.
+ */
+#define TSU_SQS_ATOMIC_DISABLE_ADDR 0x00e00405L
+#define TSU_SQS_ATOMIC_DISABLE_STRIDE 1
+#define TSU_SQS_ATOMIC_DISABLE_DEPTH 1
+
+ /* Number of burst read for the send queue element per QP. */
+#define TSU_SQS_SQ_BURST_READ_SIZE_ADDR 0x00e00406L
+#define TSU_SQS_SQ_BURST_READ_SIZE_STRIDE 1
+#define TSU_SQS_SQ_BURST_READ_SIZE_DEPTH 1
+
+ /* Number of DB count from CBU. */
+#define TSU_SQS_CBU_DB_CNT_ADDR 0x00e00407L
+#define TSU_SQS_CBU_DB_CNT_STRIDE 1
+#define TSU_SQS_CBU_DB_CNT_DEPTH 1
+
+ /* Number of DB count from ERR. */
+#define TSU_SQS_ERR_DB_CNT_ADDR 0x00e00408L
+#define TSU_SQS_ERR_DB_CNT_STRIDE 1
+#define TSU_SQS_ERR_DB_CNT_DEPTH 1
+
+ /* Number of LLQ push. */
+#define TSU_SQS_LLQ_PUSH_CNT_ADDR 0x00e00409L
+#define TSU_SQS_LLQ_PUSH_CNT_STRIDE 1
+#define TSU_SQS_LLQ_PUSH_CNT_DEPTH 1
+
+ /* Number of LLQ pop. */
+#define TSU_SQS_LLQ_POP_CNT_ADDR 0x00e0040aL
+#define TSU_SQS_LLQ_POP_CNT_STRIDE 1
+#define TSU_SQS_LLQ_POP_CNT_DEPTH 1
+
+ /* Number of LLQ peek. */
+#define TSU_SQS_LLQ_PEEK_CNT_ADDR 0x00e0040bL
+#define TSU_SQS_LLQ_PEEK_CNT_STRIDE 1
+#define TSU_SQS_LLQ_PEEK_CNT_DEPTH 1
+
+ /* Number of Send Queue read. */
+#define TSU_SQS_SQ_RD_CNT_ADDR 0x00e0040cL
+#define TSU_SQS_SQ_RD_CNT_STRIDE 1
+#define TSU_SQS_SQ_RD_CNT_DEPTH 1
+
+ /* Number of Descriptor read. */
+#define TSU_SQS_DSCR_REQ_CNT_ADDR 0x00e0040dL
+#define TSU_SQS_DSCR_REQ_CNT_STRIDE 1
+#define TSU_SQS_DSCR_REQ_CNT_DEPTH 1
+
+ /* Number of Descriptor read response. */
+#define TSU_SQS_DSCR_RSP_CNT_ADDR 0x00e0040eL
+#define TSU_SQS_DSCR_RSP_CNT_STRIDE 1
+#define TSU_SQS_DSCR_RSP_CNT_DEPTH 1
+
+ /* Number of Atomic request. */
+#define TSU_SQS_ATM_REQ_CNT_ADDR 0x00e0040fL
+#define TSU_SQS_ATM_REQ_CNT_STRIDE 1
+#define TSU_SQS_ATM_REQ_CNT_DEPTH 1
+
+ /* Number of Atomic response. */
+#define TSU_SQS_ATM_RSP_CNT_ADDR 0x00e00410L
+#define TSU_SQS_ATM_RSP_CNT_STRIDE 1
+#define TSU_SQS_ATM_RSP_CNT_DEPTH 1
+
+ /* Number of QP insert to the SQS list. */
+#define TSU_SQS_PUSH_SQS_LIST_CNT_ADDR 0x00e00411L
+#define TSU_SQS_PUSH_SQS_LIST_CNT_STRIDE 1
+#define TSU_SQS_PUSH_SQS_LIST_CNT_DEPTH 1
+
+ /* Number of clock to wait before writting to the ring. */
+#define TSU_SQS_RING_TIMER_ADDR 0x00e00412L
+#define TSU_SQS_RING_TIMER_STRIDE 1
+#define TSU_SQS_RING_TIMER_DEPTH 1
+
+ /* Set to write 64B for the send queue hardware descriptor. */
+#define TSU_SQS_PADDED_SQ_DSCR_HW_ADDR 0x00e00413L
+#define TSU_SQS_PADDED_SQ_DSCR_HW_STRIDE 1
+#define TSU_SQS_PADDED_SQ_DSCR_HW_DEPTH 1
+
+ /* Set to write 64B for the PIO ring buffer. */
+#define TSU_SQS_PADDED_RING_BUFFER_ADDR 0x00e00414L
+#define TSU_SQS_PADDED_RING_BUFFER_STRIDE 1
+#define TSU_SQS_PADDED_RING_BUFFER_DEPTH 1
+
+ /* ECC error control */
+#define TSU_SQS_ECC_ERR_CTRL_ADDR 0x00e00415L
+#define TSU_SQS_ECC_ERR_CTRL_STRIDE 1
+#define TSU_SQS_ECC_ERR_CTRL_DEPTH 1
+
+ /* ECC status */
+#define TSU_SQS_ECC_ERR_STATUS_ADDR 0x00e00416L
+#define TSU_SQS_ECC_ERR_STATUS_STRIDE 1
+#define TSU_SQS_ECC_ERR_STATUS_DEPTH 1
+
+ /* ECC status */
+#define TSU_SQS_ECC_ERR_STATUS_CLEAR_ADDR 0x00e00417L
+#define TSU_SQS_ECC_ERR_STATUS_CLEAR_STRIDE 1
+#define TSU_SQS_ECC_ERR_STATUS_CLEAR_DEPTH 1
+
+ /* SQ MMU context to use EPSC memory permission */
+#define TSU_SQS_SQ_MMU_CONTEXT_EPSC_PERM_ADDR 0x00e00418L
+#define TSU_SQS_SQ_MMU_CONTEXT_EPSC_PERM_STRIDE 1
+#define TSU_SQS_SQ_MMU_CONTEXT_EPSC_PERM_DEPTH 1
+
+ /* Timer scale: 12 bits interval counter 8.192us 32 bits wrap counter */
+#define TSU_SQS_TIMER_SCALE_ADDR 0x00e00419L
+#define TSU_SQS_TIMER_SCALE_STRIDE 1
+#define TSU_SQS_TIMER_SCALE_DEPTH 1
+
+ /* LLQ credit for Doorbell Retry Transport Timer and Response */
+#define TSU_SQS_LLQ_CREDIT_ADDR 0x00e0041aL
+#define TSU_SQS_LLQ_CREDIT_STRIDE 1
+#define TSU_SQS_LLQ_CREDIT_DEPTH 1
+
+ /* software mode for qps_if */
+#define TSU_SQS_QPS_IF_ADDR 0x00e0041bL
+#define TSU_SQS_QPS_IF_STRIDE 1
+#define TSU_SQS_QPS_IF_DEPTH 1
+
+ /* software mode for qps_if kick */
+#define TSU_SQS_QPS_IF_KICK_ADDR 0x00e0041cL
+#define TSU_SQS_QPS_IF_KICK_STRIDE 1
+#define TSU_SQS_QPS_IF_KICK_DEPTH 1
+
+ /* software mode for host_if response scheduling */
+#define TSU_SQS_HOST_IF0_ADDR 0x00e0041dL
+#define TSU_SQS_HOST_IF0_STRIDE 1
+#define TSU_SQS_HOST_IF0_DEPTH 1
+
+ /* software mode for host_if response scheduling */
+#define TSU_SQS_HOST_IF1_ADDR 0x00e0041eL
+#define TSU_SQS_HOST_IF1_STRIDE 1
+#define TSU_SQS_HOST_IF1_DEPTH 1
+
+ /* software mode for host_if response scheduling */
+#define TSU_SQS_HOST_IF2_ADDR 0x00e0041fL
+#define TSU_SQS_HOST_IF2_STRIDE 1
+#define TSU_SQS_HOST_IF2_DEPTH 1
+
+ /* software mode for host_if response scheduling */
+#define TSU_SQS_HOST_IF3_ADDR 0x00e00420L
+#define TSU_SQS_HOST_IF3_STRIDE 1
+#define TSU_SQS_HOST_IF3_DEPTH 1
+
+ /* software mode for host_if response scheduling kick */
+#define TSU_SQS_HOST_IF_KICK_ADDR 0x00e00421L
+#define TSU_SQS_HOST_IF_KICK_STRIDE 1
+#define TSU_SQS_HOST_IF_KICK_DEPTH 1
+
+ /* Base address registers per UF for hardware to FIFO PIO doorbell. */
+#define TSU_SQS_PIO_RING_BASE_ADDR_0_ADDR 0x00e00500L
+#define TSU_SQS_PIO_RING_BASE_ADDR_0_STRIDE 1
+#define TSU_SQS_PIO_RING_BASE_ADDR_0_DEPTH 34
+
+ /* Base address registers per UF for hardware to FIFO PIO doorbell. */
+#define TSU_SQS_PIO_RING_BASE_ADDR_1_ADDR 0x00e00540L
+#define TSU_SQS_PIO_RING_BASE_ADDR_1_STRIDE 1
+#define TSU_SQS_PIO_RING_BASE_ADDR_1_DEPTH 34
+
+ /* Base address registers per UF for hardware to FIFO PIO doorbell. */
+#define TSU_SQS_PIO_RING_BASE_ADDR_2_ADDR 0x00e00580L
+#define TSU_SQS_PIO_RING_BASE_ADDR_2_STRIDE 1
+#define TSU_SQS_PIO_RING_BASE_ADDR_2_DEPTH 34
+
+ /* Read/Write for the PIO ring buffer write pointer */
+#define TSU_SQS_PIO_RING_BUFFER_WR_PTR_ADDR 0x00e005c0L
+#define TSU_SQS_PIO_RING_BUFFER_WR_PTR_STRIDE 1
+#define TSU_SQS_PIO_RING_BUFFER_WR_PTR_DEPTH 34
+
+ /*
+ * Address: SQS list number. Set when the PCIe response has error on the
+ * descriptor read.
+ */
+#define TSU_SQS_SQS_LIST_ERR_STATUS_ADDR 0x00e00600L
+#define TSU_SQS_SQS_LIST_ERR_STATUS_STRIDE 1
+#define TSU_SQS_SQS_LIST_ERR_STATUS_DEPTH 68
+
+ /* Read/Write for the PIO ring buffer read pointer */
+#define TSU_SQS_PIO_RING_BUFFER_RD_PTR_ADDR 0x00e00680L
+#define TSU_SQS_PIO_RING_BUFFER_RD_PTR_STRIDE 1
+#define TSU_SQS_PIO_RING_BUFFER_RD_PTR_DEPTH 34
+
+ /* Read/Write for the PIO ring buffer pending count */
+#define TSU_SQS_PIO_RING_BUFFER_PENDING_CNT_ADDR 0x00e006c0L
+#define TSU_SQS_PIO_RING_BUFFER_PENDING_CNT_STRIDE 1
+#define TSU_SQS_PIO_RING_BUFFER_PENDING_CNT_DEPTH 34
+
+ /* Base address registers per UF for response queue. */
+#define TSU_SQS_RSPQ_BASE_ADDR_0_ADDR 0x00e00700L
+#define TSU_SQS_RSPQ_BASE_ADDR_0_STRIDE 1
+#define TSU_SQS_RSPQ_BASE_ADDR_0_DEPTH 33
+
+ /* Base address registers per UF for response queue. */
+#define TSU_SQS_RSPQ_BASE_ADDR_1_ADDR 0x00e00740L
+#define TSU_SQS_RSPQ_BASE_ADDR_1_STRIDE 1
+#define TSU_SQS_RSPQ_BASE_ADDR_1_DEPTH 33
+
+ /* Base address registers per UF for response queue. */
+#define TSU_SQS_RSPQ_BASE_ADDR_2_ADDR 0x00e00780L
+#define TSU_SQS_RSPQ_BASE_ADDR_2_STRIDE 1
+#define TSU_SQS_RSPQ_BASE_ADDR_2_DEPTH 33
+
+ /* Credit a particular TVL can get. */
+#define TSU_SQS_TVL_CREDIT_ADDR 0x00e007c0L
+#define TSU_SQS_TVL_CREDIT_STRIDE 1
+#define TSU_SQS_TVL_CREDIT_DEPTH 128
+
+ /* Head pointer for MMU contexts policies check failed. */
+#define TSU_SQS_BAD_MMU_CNTXT_HP_ADDR 0x00e00840L
+#define TSU_SQS_BAD_MMU_CNTXT_HP_STRIDE 1
+#define TSU_SQS_BAD_MMU_CNTXT_HP_DEPTH 34
+
+ /*
+ * Base address registers per UF for response queue tvl pointer. Each tvl has
+ * 16 bytes pointers
+ */
+#define TSU_SQS_RSPQ_TVL_BASE_ADDR_0_ADDR 0x00e00880L
+#define TSU_SQS_RSPQ_TVL_BASE_ADDR_0_STRIDE 1
+#define TSU_SQS_RSPQ_TVL_BASE_ADDR_0_DEPTH 33
+
+ /* Base address registers per UF for response queue tvl pointer. */
+#define TSU_SQS_RSPQ_TVL_BASE_ADDR_1_ADDR 0x00e008c0L
+#define TSU_SQS_RSPQ_TVL_BASE_ADDR_1_STRIDE 1
+#define TSU_SQS_RSPQ_TVL_BASE_ADDR_1_DEPTH 33
+
+ /*
+ * Base address registers per UF for response queue tvl pointer. Warning!
+ * This register is unused by hardware and it is always read as 0.
+ */
+#define TSU_SQS_RSPQ_TVL_BASE_ADDR_2_ADDR 0x00e00900L
+#define TSU_SQS_RSPQ_TVL_BASE_ADDR_2_STRIDE 1
+#define TSU_SQS_RSPQ_TVL_BASE_ADDR_2_DEPTH 33
+
+ /* Address: uf number tvl list number. Flush and Error status. */
+#define TSU_SQS_RSPQ_LIST_STATUS_ADDR 0x00e02000L
+#define TSU_SQS_RSPQ_LIST_STATUS_STRIDE 1
+#define TSU_SQS_RSPQ_LIST_STATUS_DEPTH 4224
+
+ /*
+ * Base address registers per UF for software owned descriptor portion of
+ * completion queue descriptors.
+ */
+#define TSU_CBLD_CQ_BASE_ADDR_SW_0_ADDR 0x00f00000L
+#define TSU_CBLD_CQ_BASE_ADDR_SW_0_STRIDE 1
+#define TSU_CBLD_CQ_BASE_ADDR_SW_0_DEPTH 34
+
+#define TSU_CBLD_CQ_BASE_ADDR_SW_1_ADDR 0x00f00040L
+#define TSU_CBLD_CQ_BASE_ADDR_SW_1_STRIDE 1
+#define TSU_CBLD_CQ_BASE_ADDR_SW_1_DEPTH 34
+
+#define TSU_CBLD_CQ_BASE_ADDR_SW_2_ADDR 0x00f00080L
+#define TSU_CBLD_CQ_BASE_ADDR_SW_2_STRIDE 1
+#define TSU_CBLD_CQ_BASE_ADDR_SW_2_DEPTH 34
+
+ /*
+ * Base address registers per UF for hardware owned descriptor portion of
+ * completion queue descriptors.
+ */
+#define TSU_CBLD_CQ_BASE_ADDR_HW_0_ADDR 0x00f000c0L
+#define TSU_CBLD_CQ_BASE_ADDR_HW_0_STRIDE 1
+#define TSU_CBLD_CQ_BASE_ADDR_HW_0_DEPTH 34
+
+#define TSU_CBLD_CQ_BASE_ADDR_HW_1_ADDR 0x00f00100L
+#define TSU_CBLD_CQ_BASE_ADDR_HW_1_STRIDE 1
+#define TSU_CBLD_CQ_BASE_ADDR_HW_1_DEPTH 34
+
+#define TSU_CBLD_CQ_BASE_ADDR_HW_2_ADDR 0x00f00140L
+#define TSU_CBLD_CQ_BASE_ADDR_HW_2_STRIDE 1
+#define TSU_CBLD_CQ_BASE_ADDR_HW_2_DEPTH 34
+
+ /* Error type the programmable counter is counting. */
+#define TSU_CBLD_PROG_ERROR_TYPE_ADDR 0x00f00200L
+#define TSU_CBLD_PROG_ERROR_TYPE_STRIDE 1
+#define TSU_CBLD_PROG_ERROR_TYPE_DEPTH 1
+
+ /*
+ * Counts how many times error type defined in prog_error_type register is
+ * received by tsu_cbld. Sticky at max value and then needs to be cleared.
+ */
+#define TSU_CBLD_PROG_COUNTER_ADDR 0x00f00201L
+#define TSU_CBLD_PROG_COUNTER_STRIDE 1
+#define TSU_CBLD_PROG_COUNTER_DEPTH 1
+
+ /* Clears prog_counter. */
+#define TSU_CBLD_CLEAR_PROG_COUNTER_ADDR 0x00f00202L
+#define TSU_CBLD_CLEAR_PROG_COUNTER_STRIDE 1
+#define TSU_CBLD_CLEAR_PROG_COUNTER_DEPTH 1
+
+ /* Interrupt status register. 1b per source (1 = int triggered). */
+#define TSU_CBLD_INT_STATUS_ADDR 0x00f00400L
+#define TSU_CBLD_INT_STATUS_STRIDE 1
+#define TSU_CBLD_INT_STATUS_DEPTH 1
+
+ /* Interrupt mask register. 1b per source (1 = masked). */
+#define TSU_CBLD_INT_MASK_ADDR 0x00f00401L
+#define TSU_CBLD_INT_MASK_STRIDE 1
+#define TSU_CBLD_INT_MASK_DEPTH 1
+
+ /* Interrupt priority register. 1b per source (1 = high 0 = low). */
+#define TSU_CBLD_INT_PRI_ADDR 0x00f00402L
+#define TSU_CBLD_INT_PRI_STRIDE 1
+#define TSU_CBLD_INT_PRI_DEPTH 1
+
+ /*
+ * Interrupt status clear register. 1b per source (1=source will be cleared
+ * from int_status register when kick is called).
+ */
+#define TSU_CBLD_INT_STATUS_CLEAR_ADDR 0x00f00403L
+#define TSU_CBLD_INT_STATUS_CLEAR_STRIDE 1
+#define TSU_CBLD_INT_STATUS_CLEAR_DEPTH 1
+
+ /* Trigger the int_status clear operation. */
+#define TSU_CBLD_INT_STATUS_CLEAR_KICK_ADDR 0x00f00404L
+#define TSU_CBLD_INT_STATUS_CLEAR_KICK_STRIDE 1
+#define TSU_CBLD_INT_STATUS_CLEAR_KICK_DEPTH 1
+
+ /*
+ * This register must be set and the kick register is written in order to
+ * start the operation.
+ */
+#define TSU_CBLD_UF_CONTROL_ADDR 0x00f00700L
+#define TSU_CBLD_UF_CONTROL_STRIDE 1
+#define TSU_CBLD_UF_CONTROL_DEPTH 1
+
+ /* Starts operation defined in uf_control. */
+#define TSU_CBLD_UF_CONTROL_KICK_ADDR 0x00f00701L
+#define TSU_CBLD_UF_CONTROL_KICK_STRIDE 1
+#define TSU_CBLD_UF_CONTROL_KICK_DEPTH 1
+
+ /*
+ * One bit per vHCA indicating if the vHCA is allowed to use proxy mode.
+ */
+#define TSU_CBLD_PROXY_ALLOWED_ADDR 0x00f00702L
+#define TSU_CBLD_PROXY_ALLOWED_STRIDE 1
+#define TSU_CBLD_PROXY_ALLOWED_DEPTH 1
+
+ /* Various diagnostic control bits */
+#define TSU_CBLD_DIAGNOSTIC_ADDR 0x00f00800L
+#define TSU_CBLD_DIAGNOSTIC_STRIDE 1
+#define TSU_CBLD_DIAGNOSTIC_DEPTH 1
+
+ /*
+ * Debug register0. There are no definitions of the fields generated, but
+ * they can be found from the HW definitions.
+ */
+#define TSU_CBLD_DEBUG_0_ADDR 0x00f00801L
+#define TSU_CBLD_DEBUG_0_STRIDE 1
+#define TSU_CBLD_DEBUG_0_DEPTH 1
+
+ /*
+ * Debug register. There are no definitions of the fields generated, but they
+ * can be found from the HW definitions.
+ */
+#define TSU_CBLD_DEBUG_1_ADDR 0x00f00802L
+#define TSU_CBLD_DEBUG_1_STRIDE 1
+#define TSU_CBLD_DEBUG_1_DEPTH 1
+
+ /*
+ * Debug register. There are no definitions of the fields generated, but they
+ * can be found from the HW definitions.
+ */
+#define TSU_CBLD_DEBUG_2_ADDR 0x00f00803L
+#define TSU_CBLD_DEBUG_2_STRIDE 1
+#define TSU_CBLD_DEBUG_2_DEPTH 1
+
+ /* Clears the diag RAM for the UF specified. */
+#define TSU_CBLD_CLEAR_DIAG_RAM_ADDR 0x00f01000L
+#define TSU_CBLD_CLEAR_DIAG_RAM_STRIDE 1
+#define TSU_CBLD_CLEAR_DIAG_RAM_DEPTH 1
+
+ /* Clears the diag RAM - per UF. */
+#define TSU_CBLD_CLEAR_DIAG_RAM_KICK_ADDR 0x00f01001L
+#define TSU_CBLD_CLEAR_DIAG_RAM_KICK_STRIDE 1
+#define TSU_CBLD_CLEAR_DIAG_RAM_KICK_DEPTH 1
+
+ /* Read the address for the UF. */
+#define TSU_CBLD_DIAG_RAM_ADDR_ADDR 0x00f0139cL
+#define TSU_CBLD_DIAG_RAM_ADDR_STRIDE 1
+#define TSU_CBLD_DIAG_RAM_ADDR_DEPTH 34
+
+ /* Set up which RAM entry to read. */
+#define TSU_CBLD_DIAG_RAM_READ_ADDR_ADDR 0x00f0179cL
+#define TSU_CBLD_DIAG_RAM_READ_ADDR_STRIDE 1
+#define TSU_CBLD_DIAG_RAM_READ_ADDR_DEPTH 1
+
+ /*
+ * Kick - reads the data from the RAM entry specified in diag_ram_read_addr
+ * and adds it to registers which can be read.
+ */
+#define TSU_CBLD_DIAG_RAM_READ_KICK_ADDR 0x00f01b9bL
+#define TSU_CBLD_DIAG_RAM_READ_KICK_STRIDE 1
+#define TSU_CBLD_DIAG_RAM_READ_KICK_DEPTH 1
+
+ /* Time to wait before starting send queue mode. */
+#define TSU_CBLD_FENCE_TIME_TO_WAIT_ADDR 0x00f02000L
+#define TSU_CBLD_FENCE_TIME_TO_WAIT_STRIDE 1
+#define TSU_CBLD_FENCE_TIME_TO_WAIT_DEPTH 1
+
+ /*
+ * QP state transitions for different error classes. This register should not
+ * be used unless there is a bug.
+ */
+#define TSU_CBLD_ERR_CLASS_MODE_ADDR 0x00f02001L
+#define TSU_CBLD_ERR_CLASS_MODE_STRIDE 1
+#define TSU_CBLD_ERR_CLASS_MODE_DEPTH 1
+
+ /*
+ * When this register is written to, the content of indirect_eq_sw_index_wr,
+ * indirect_eq_hw_index_wr, indirect_eq_ctrl_wr, indirect_eq_base_addr_wr,
+ * indirect_eq_size_wr is written to event queue entry number defined by the
+ * value in the indirect_addr.
+ */
+#define TSU_CBLD_INDIRECT_WR_KICK_ADDR 0x00f04000L
+#define TSU_CBLD_INDIRECT_WR_KICK_STRIDE 1
+#define TSU_CBLD_INDIRECT_WR_KICK_DEPTH 128
+
+ /*
+ * Head index register. Indirect register to write in order to get a
+ * consistent view of the complete descriptor. This is used along with the
+ * address and write register.
+ */
+#define TSU_CBLD_INDIRECT_EQ_SW_INDEX_WR_ADDR 0x00f04080L
+#define TSU_CBLD_INDIRECT_EQ_SW_INDEX_WR_STRIDE 1
+#define TSU_CBLD_INDIRECT_EQ_SW_INDEX_WR_DEPTH 1
+
+ /*
+ * Tail index register. Indirect register to write in order to get a
+ * consistent view of the complete descriptor. This is used along with the
+ * address and write register.
+ */
+#define TSU_CBLD_INDIRECT_EQ_HW_INDEX_WR_ADDR 0x00f04081L
+#define TSU_CBLD_INDIRECT_EQ_HW_INDEX_WR_STRIDE 1
+#define TSU_CBLD_INDIRECT_EQ_HW_INDEX_WR_DEPTH 1
+
+ /*
+ * MMU context and descriptor control register. Indirect register to write in
+ * order to get a consistent view of the complete descriptor. This is used
+ * along with the address and write register.
+ */
+#define TSU_CBLD_INDIRECT_EQ_CTRL_WR_ADDR 0x00f04082L
+#define TSU_CBLD_INDIRECT_EQ_CTRL_WR_STRIDE 1
+#define TSU_CBLD_INDIRECT_EQ_CTRL_WR_DEPTH 1
+
+ /*
+ * Base address register. Indirect register to write in order to get a
+ * consistent view of the complete descriptor. This is used along with the
+ * address and write register.
+ */
+#define TSU_CBLD_INDIRECT_EQ_BASE_ADDR_WR_ADDR 0x00f04083L
+#define TSU_CBLD_INDIRECT_EQ_BASE_ADDR_WR_STRIDE 1
+#define TSU_CBLD_INDIRECT_EQ_BASE_ADDR_WR_DEPTH 1
+
+ /*
+ * Max number of entries and sequence number register. Indirect register to
+ * write in order to get a consistent view of the complete descriptor. This
+ * is used along with the address and write register.
+ */
+#define TSU_CBLD_INDIRECT_MMU_CONTEXT_WR_ADDR 0x00f04084L
+#define TSU_CBLD_INDIRECT_MMU_CONTEXT_WR_STRIDE 1
+#define TSU_CBLD_INDIRECT_MMU_CONTEXT_WR_DEPTH 1
+
+ /*
+ * When this register is written to, the content of event queue entry in
+ * indirect_addr is written to indirect_eq_sw_index_rd,
+ * indirect_eq_hw_index_rd, indirect_eq_ctrl_rd, indirect_eq_base_addr_rd,
+ * indirect_eq_size_rd. These registers can now be read as one consistent
+ * register.
+ */
+#define TSU_CBLD_INDIRECT_RD_KICK_ADDR 0x00f04100L
+#define TSU_CBLD_INDIRECT_RD_KICK_STRIDE 1
+#define TSU_CBLD_INDIRECT_RD_KICK_DEPTH 128
+
+ /*
+ * Head index register. Indirect register to read in order to get a
+ * consistent view of the complete descriptor. This is used along with the
+ * address and read register.
+ */
+#define TSU_CBLD_INDIRECT_EQ_SW_INDEX_RD_ADDR 0x00f04180L
+#define TSU_CBLD_INDIRECT_EQ_SW_INDEX_RD_STRIDE 1
+#define TSU_CBLD_INDIRECT_EQ_SW_INDEX_RD_DEPTH 1
+
+ /*
+ * Tail index register. Indirect register to read in order to get a
+ * consistent view of the complete descriptor. This is used along with the
+ * address and read register.
+ */
+#define TSU_CBLD_INDIRECT_EQ_HW_INDEX_RD_ADDR 0x00f04181L
+#define TSU_CBLD_INDIRECT_EQ_HW_INDEX_RD_STRIDE 1
+#define TSU_CBLD_INDIRECT_EQ_HW_INDEX_RD_DEPTH 1
+
+ /*
+ * MMU context and descriptor control register. Indirect register to read in
+ * order to get a consistent view of the complete descriptor. This is used
+ * along with the address and write register.
+ */
+#define TSU_CBLD_INDIRECT_EQ_CTRL_RD_ADDR 0x00f04182L
+#define TSU_CBLD_INDIRECT_EQ_CTRL_RD_STRIDE 1
+#define TSU_CBLD_INDIRECT_EQ_CTRL_RD_DEPTH 1
+
+ /*
+ * Base address register. Indirect register to read in order to get a
+ * consistent view of the complete descriptor. This is used along with the
+ * address and read register.
+ */
+#define TSU_CBLD_INDIRECT_EQ_BASE_ADDR_RD_ADDR 0x00f04183L
+#define TSU_CBLD_INDIRECT_EQ_BASE_ADDR_RD_STRIDE 1
+#define TSU_CBLD_INDIRECT_EQ_BASE_ADDR_RD_DEPTH 1
+
+ /*
+ * Max number of entries and sequence number register. Indirect register to
+ * read in order to get a consistent view of the complete descriptor. This is
+ * used along with the address and read register.
+ */
+#define TSU_CBLD_INDIRECT_MMU_CONTEXT_RD_ADDR 0x00f04184L
+#define TSU_CBLD_INDIRECT_MMU_CONTEXT_RD_STRIDE 1
+#define TSU_CBLD_INDIRECT_MMU_CONTEXT_RD_DEPTH 1
+
+ /*
+ * Directly accessible software index. Software can update this directly
+ * without having to go through a staging read/write register.
+ */
+#define TSU_CBLD_EQ_SW_INDEX_ADDR 0x00f04200L
+#define TSU_CBLD_EQ_SW_INDEX_STRIDE 1
+#define TSU_CBLD_EQ_SW_INDEX_DEPTH 128
+
+ /*
+ * Directly accessible software index. Software can update this directly
+ * without having to go through a staging read/write register.
+ */
+#define TSU_CBLD_EQ_HW_INDEX_ADDR 0x00f04280L
+#define TSU_CBLD_EQ_HW_INDEX_STRIDE 1
+#define TSU_CBLD_EQ_HW_INDEX_DEPTH 128
+
+ /*
+ * Used for translating each vHCA's EQ number to the physical EQ number.
+ */
+#define TSU_CBLD_EQ_MAPPING_TABLE_ADDR 0x00f04300L
+#define TSU_CBLD_EQ_MAPPING_TABLE_STRIDE 1
+#define TSU_CBLD_EQ_MAPPING_TABLE_DEPTH 34
+
+ /* EQ Overflow Status 0 EQs 0-63 */
+#define TSU_CBLD_EQ_OVERFLOW_STATUS_0_ADDR 0x00f04400L
+#define TSU_CBLD_EQ_OVERFLOW_STATUS_0_STRIDE 1
+#define TSU_CBLD_EQ_OVERFLOW_STATUS_0_DEPTH 1
+
+ /* EQ Overflow Status 1 EQs 64-127 */
+#define TSU_CBLD_EQ_OVERFLOW_STATUS_1_ADDR 0x00f04401L
+#define TSU_CBLD_EQ_OVERFLOW_STATUS_1_STRIDE 1
+#define TSU_CBLD_EQ_OVERFLOW_STATUS_1_DEPTH 1
+
+ /* EQ Invalid Status 0 EQs 0-63 */
+#define TSU_CBLD_EQ_INVALID_STATUS_0_ADDR 0x00f04402L
+#define TSU_CBLD_EQ_INVALID_STATUS_0_STRIDE 1
+#define TSU_CBLD_EQ_INVALID_STATUS_0_DEPTH 1
+
+ /* EQ Invalid Status 1 EQs 64-127 */
+#define TSU_CBLD_EQ_INVALID_STATUS_1_ADDR 0x00f04403L
+#define TSU_CBLD_EQ_INVALID_STATUS_1_STRIDE 1
+#define TSU_CBLD_EQ_INVALID_STATUS_1_DEPTH 1
+
+ /* EQ out of range status */
+#define TSU_CBLD_EQ_OUT_OF_RANGE_STATUS_ADDR 0x00f04404L
+#define TSU_CBLD_EQ_OUT_OF_RANGE_STATUS_STRIDE 1
+#define TSU_CBLD_EQ_OUT_OF_RANGE_STATUS_DEPTH 1
+
+ /* Clear EQ Status 0 EQs 0-63 */
+#define TSU_CBLD_CLEAR_EQ_STATUS_0_ADDR 0x00f04405L
+#define TSU_CBLD_CLEAR_EQ_STATUS_0_STRIDE 1
+#define TSU_CBLD_CLEAR_EQ_STATUS_0_DEPTH 1
+
+ /* Clear EQ Status 1 EQs 64-127 */
+#define TSU_CBLD_CLEAR_EQ_STATUS_1_ADDR 0x00f04406L
+#define TSU_CBLD_CLEAR_EQ_STATUS_1_STRIDE 1
+#define TSU_CBLD_CLEAR_EQ_STATUS_1_DEPTH 1
+
+ /* Initiates clear of EQ status bits as indicated in Clear EQ Status 0/1. */
+#define TSU_CBLD_CLEAR_EQ_STATUS_KICK_ADDR 0x00f04407L
+#define TSU_CBLD_CLEAR_EQ_STATUS_KICK_STRIDE 1
+#define TSU_CBLD_CLEAR_EQ_STATUS_KICK_DEPTH 1
+
+ /* Clear per UF EQ out of range Status */
+#define TSU_CBLD_CLEAR_EQ_UF_STATUS_ADDR 0x00f04408L
+#define TSU_CBLD_CLEAR_EQ_UF_STATUS_STRIDE 1
+#define TSU_CBLD_CLEAR_EQ_UF_STATUS_DEPTH 1
+
+ /* Initiates clear of per UF out of range EQ status bits */
+#define TSU_CBLD_CLEAR_EQ_UF_STATUS_KICK_ADDR 0x00f04409L
+#define TSU_CBLD_CLEAR_EQ_UF_STATUS_KICK_STRIDE 1
+#define TSU_CBLD_CLEAR_EQ_UF_STATUS_KICK_DEPTH 1
+
+ /* Clear all counters having the bit set in the mask. */
+#define TSU_CBLD_CLEAR_ERROR_COUNTERS_ADDR 0x00f08400L
+#define TSU_CBLD_CLEAR_ERROR_COUNTERS_STRIDE 1
+#define TSU_CBLD_CLEAR_ERROR_COUNTERS_DEPTH 1
+
+ /* Clear all counters having the bit set in the mask. */
+#define TSU_CBLD_CLEAR_ERROR_COUNTERS_KICK_ADDR 0x00f08401L
+#define TSU_CBLD_CLEAR_ERROR_COUNTERS_KICK_STRIDE 1
+#define TSU_CBLD_CLEAR_ERROR_COUNTERS_KICK_DEPTH 1
+
+ /* Data from the diagnostic RAM. */
+#define TSU_CBLD_DIAG_RAM_DATA_ADDR 0x00f0c000L
+#define TSU_CBLD_DIAG_RAM_DATA_STRIDE 1
+#define TSU_CBLD_DIAG_RAM_DATA_DEPTH 10
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_1_ADDR 0x00f10000L
+#define TSU_CBLD_ERROR_COUNTER_1_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_1_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_2_ADDR 0x00f10040L
+#define TSU_CBLD_ERROR_COUNTER_2_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_2_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_3_ADDR 0x00f10080L
+#define TSU_CBLD_ERROR_COUNTER_3_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_3_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_4_ADDR 0x00f100c0L
+#define TSU_CBLD_ERROR_COUNTER_4_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_4_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_5_ADDR 0x00f10100L
+#define TSU_CBLD_ERROR_COUNTER_5_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_5_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_6_ADDR 0x00f10140L
+#define TSU_CBLD_ERROR_COUNTER_6_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_6_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_7_ADDR 0x00f10180L
+#define TSU_CBLD_ERROR_COUNTER_7_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_7_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_8_ADDR 0x00f101c0L
+#define TSU_CBLD_ERROR_COUNTER_8_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_8_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_9_ADDR 0x00f10200L
+#define TSU_CBLD_ERROR_COUNTER_9_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_9_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_10_ADDR 0x00f10240L
+#define TSU_CBLD_ERROR_COUNTER_10_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_10_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_11_ADDR 0x00f10280L
+#define TSU_CBLD_ERROR_COUNTER_11_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_11_DEPTH 34
+
+ /* Error counters. */
+#define TSU_CBLD_ERROR_COUNTER_0_ADDR 0x00f102c0L
+#define TSU_CBLD_ERROR_COUNTER_0_STRIDE 1
+#define TSU_CBLD_ERROR_COUNTER_0_DEPTH 34
+
+ /*
+ * Clear TX offload error counters. This register has one bit per UF, and
+ * will clear the corresponding counter.
+ */
+#define TSU_CBLD_TX_OFFLOAD_COUNTER_CLEAR_ADDR 0x00f107feL
+#define TSU_CBLD_TX_OFFLOAD_COUNTER_CLEAR_STRIDE 1
+#define TSU_CBLD_TX_OFFLOAD_COUNTER_CLEAR_DEPTH 1
+
+ /*
+ * Clear TX offload error counters. This register has one bit per UF, and
+ * will clear the corresponding counter.
+ */
+#define TSU_CBLD_TX_OFFLOAD_COUNTER_CLEAR_KICK_ADDR 0x00f107ffL
+#define TSU_CBLD_TX_OFFLOAD_COUNTER_CLEAR_KICK_STRIDE 1
+#define TSU_CBLD_TX_OFFLOAD_COUNTER_CLEAR_KICK_DEPTH 1
+
+ /* TX offload error counters - there is one register per UF. */
+#define TSU_CBLD_TX_OFFLOAD_COUNTER_ADDR 0x00f10800L
+#define TSU_CBLD_TX_OFFLOAD_COUNTER_STRIDE 1
+#define TSU_CBLD_TX_OFFLOAD_COUNTER_DEPTH 34
+
+ /* Sent count per UF for completions and events. */
+#define TSU_CBLD_EVENT_CQ_SENT_ADDR 0x00f10840L
+#define TSU_CBLD_EVENT_CQ_SENT_STRIDE 1
+#define TSU_CBLD_EVENT_CQ_SENT_DEPTH 34
+
+#define IBU_P1_CNT1US_CNT124US_ADDR 0x01100001L
+#define IBU_P1_CNT1US_CNT124US_STRIDE 1
+#define IBU_P1_CNT1US_CNT124US_DEPTH 1
+
+#define IBU_P1_CNT2MS_ADDR 0x01100002L
+#define IBU_P1_CNT2MS_STRIDE 1
+#define IBU_P1_CNT2MS_DEPTH 1
+
+#define IBU_P1_CNT10MS_ADDR 0x01100003L
+#define IBU_P1_CNT10MS_STRIDE 1
+#define IBU_P1_CNT10MS_DEPTH 1
+
+#define IBU_P1_CNT100MS_ADDR 0x01100004L
+#define IBU_P1_CNT100MS_STRIDE 1
+#define IBU_P1_CNT100MS_DEPTH 1
+
+#define IBU_P1_CNT150MS_ADDR 0x01100005L
+#define IBU_P1_CNT150MS_STRIDE 1
+#define IBU_P1_CNT150MS_DEPTH 1
+
+#define IBU_P1_CNT400MS_ADDR 0x01100006L
+#define IBU_P1_CNT400MS_STRIDE 1
+#define IBU_P1_CNT400MS_DEPTH 1
+
+#define IBU_P1_SKP_TO_CNT_ADDR 0x01100007L
+#define IBU_P1_SKP_TO_CNT_STRIDE 1
+#define IBU_P1_SKP_TO_CNT_DEPTH 1
+
+#define IBU_P1_TGT_VAL_ADDR 0x01100008L
+#define IBU_P1_TGT_VAL_STRIDE 1
+#define IBU_P1_TGT_VAL_DEPTH 1
+
+#define IBU_P1_PHY_VCONFIG_ADDR 0x01100009L
+#define IBU_P1_PHY_VCONFIG_STRIDE 1
+#define IBU_P1_PHY_VCONFIG_DEPTH 1
+
+#define IBU_P1_PHY_DISP_ERROR_CNT_ADDR 0x0110000aL
+#define IBU_P1_PHY_DISP_ERROR_CNT_STRIDE 1
+#define IBU_P1_PHY_DISP_ERROR_CNT_DEPTH 1
+
+#define IBU_P1_PHY_CODE_ERROR_CNT_ADDR 0x0110000bL
+#define IBU_P1_PHY_CODE_ERROR_CNT_STRIDE 1
+#define IBU_P1_PHY_CODE_ERROR_CNT_DEPTH 1
+
+#define IBU_P1_PHY_EVENT_LOG_ADDR 0x0110000cL
+#define IBU_P1_PHY_EVENT_LOG_STRIDE 1
+#define IBU_P1_PHY_EVENT_LOG_DEPTH 1
+
+#define IBU_P1_PORT_TRAIN_FSM_ADDR 0x0110000dL
+#define IBU_P1_PORT_TRAIN_FSM_STRIDE 1
+#define IBU_P1_PORT_TRAIN_FSM_DEPTH 1
+
+#define IBU_P1_PHY_TRAIN_SMTIMER_VS1_ADDR 0x0110000eL
+#define IBU_P1_PHY_TRAIN_SMTIMER_VS1_STRIDE 1
+#define IBU_P1_PHY_TRAIN_SMTIMER_VS1_DEPTH 1
+
+#define IBU_P1_MASK_ADDR 0x0110000fL
+#define IBU_P1_MASK_STRIDE 1
+#define IBU_P1_MASK_DEPTH 1
+
+#define IBU_P1_STATUS_ADDR 0x01100010L
+#define IBU_P1_STATUS_STRIDE 1
+#define IBU_P1_STATUS_DEPTH 1
+
+#define IBU_P1_LINK_WIDTH_ENABLED_ADDR 0x01100011L
+#define IBU_P1_LINK_WIDTH_ENABLED_STRIDE 1
+#define IBU_P1_LINK_WIDTH_ENABLED_DEPTH 1
+
+#define IBU_P1_LINK_WIDTH_SUPPORTED_ADDR 0x01100012L
+#define IBU_P1_LINK_WIDTH_SUPPORTED_STRIDE 1
+#define IBU_P1_LINK_WIDTH_SUPPORTED_DEPTH 1
+
+#define IBU_P1_LINK_WIDTH_ACTIVE_ADDR 0x01100013L
+#define IBU_P1_LINK_WIDTH_ACTIVE_STRIDE 1
+#define IBU_P1_LINK_WIDTH_ACTIVE_DEPTH 1
+
+#define IBU_P1_LINK_SPEED_SUPPORTED_ADDR 0x01100014L
+#define IBU_P1_LINK_SPEED_SUPPORTED_STRIDE 1
+#define IBU_P1_LINK_SPEED_SUPPORTED_DEPTH 1
+
+#define IBU_P1_PORT_PHYSICAL_STATE_ADDR 0x01100015L
+#define IBU_P1_PORT_PHYSICAL_STATE_STRIDE 1
+#define IBU_P1_PORT_PHYSICAL_STATE_DEPTH 1
+
+#define IBU_P1_LINK_DOWN_DEFAULT_STATE_ADDR 0x01100016L
+#define IBU_P1_LINK_DOWN_DEFAULT_STATE_STRIDE 1
+#define IBU_P1_LINK_DOWN_DEFAULT_STATE_DEPTH 1
+
+#define IBU_P1_LINK_SPEED_ACTIVE_ADDR 0x01100017L
+#define IBU_P1_LINK_SPEED_ACTIVE_STRIDE 1
+#define IBU_P1_LINK_SPEED_ACTIVE_DEPTH 1
+
+#define IBU_P1_LINK_SPEED_ENABLED_ADDR 0x01100018L
+#define IBU_P1_LINK_SPEED_ENABLED_STRIDE 1
+#define IBU_P1_LINK_SPEED_ENABLED_DEPTH 1
+
+#define IBU_P1_PCPHY_CNT_RST_ADDR 0x01100019L
+#define IBU_P1_PCPHY_CNT_RST_STRIDE 1
+#define IBU_P1_PCPHY_CNT_RST_DEPTH 1
+
+#define IBU_P1_PCPHY_CNT_LOAD_ADDR 0x0110001aL
+#define IBU_P1_PCPHY_CNT_LOAD_STRIDE 1
+#define IBU_P1_PCPHY_CNT_LOAD_DEPTH 1
+
+#define IBU_P1_PCSYMB_ERR_CNT_ADDR 0x0110001bL
+#define IBU_P1_PCSYMB_ERR_CNT_STRIDE 1
+#define IBU_P1_PCSYMB_ERR_CNT_DEPTH 1
+
+#define IBU_P1_PCLINK_ERR_REC_CNT_ADDR 0x0110001cL
+#define IBU_P1_PCLINK_ERR_REC_CNT_STRIDE 1
+#define IBU_P1_PCLINK_ERR_REC_CNT_DEPTH 1
+
+#define IBU_P1_PCLINK_DOWNED_CNT_ADDR 0x0110001dL
+#define IBU_P1_PCLINK_DOWNED_CNT_STRIDE 1
+#define IBU_P1_PCLINK_DOWNED_CNT_DEPTH 1
+
+#define IBU_P1_PCSYMB_ERR_CNT_LANE0_ADDR 0x0110001eL
+#define IBU_P1_PCSYMB_ERR_CNT_LANE0_STRIDE 1
+#define IBU_P1_PCSYMB_ERR_CNT_LANE0_DEPTH 1
+
+#define IBU_P1_PCSYMB_ERR_CNT_LANE1_ADDR 0x0110001fL
+#define IBU_P1_PCSYMB_ERR_CNT_LANE1_STRIDE 1
+#define IBU_P1_PCSYMB_ERR_CNT_LANE1_DEPTH 1
+
+#define IBU_P1_PCSYMB_ERR_CNT_LANE2_ADDR 0x01100020L
+#define IBU_P1_PCSYMB_ERR_CNT_LANE2_STRIDE 1
+#define IBU_P1_PCSYMB_ERR_CNT_LANE2_DEPTH 1
+
+#define IBU_P1_PCSYMB_ERR_CNT_LANE3_ADDR 0x01100021L
+#define IBU_P1_PCSYMB_ERR_CNT_LANE3_STRIDE 1
+#define IBU_P1_PCSYMB_ERR_CNT_LANE3_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT0_COUNTER_ADDR 0x01100022L
+#define IBU_P1_TS3_REV1_TT0_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT0_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT1_COUNTER_ADDR 0x01100023L
+#define IBU_P1_TS3_REV1_TT1_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT1_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT2_COUNTER_ADDR 0x01100024L
+#define IBU_P1_TS3_REV1_TT2_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT2_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT3_COUNTER_ADDR 0x01100025L
+#define IBU_P1_TS3_REV1_TT3_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT3_COUNTER_DEPTH 1
+
+#define IBU_P1_PHY_ALIGN_ERROR_CNT_ADDR 0x01100026L
+#define IBU_P1_PHY_ALIGN_ERROR_CNT_STRIDE 1
+#define IBU_P1_PHY_ALIGN_ERROR_CNT_DEPTH 1
+
+#define IBU_P1_PHY_CNTRL_IN_PKT_ERROR_CNT_ADDR 0x01100027L
+#define IBU_P1_PHY_CNTRL_IN_PKT_ERROR_CNT_STRIDE 1
+#define IBU_P1_PHY_CNTRL_IN_PKT_ERROR_CNT_DEPTH 1
+
+#define IBU_P1_PHY_PAD_ERROR_CNT_ADDR 0x01100028L
+#define IBU_P1_PHY_PAD_ERROR_CNT_STRIDE 1
+#define IBU_P1_PHY_PAD_ERROR_CNT_DEPTH 1
+
+#define IBU_P1_PHY_EDR_FDR_CONFIG0_ADDR 0x01100029L
+#define IBU_P1_PHY_EDR_FDR_CONFIG0_STRIDE 1
+#define IBU_P1_PHY_EDR_FDR_CONFIG0_DEPTH 1
+
+#define IBU_P1_PHY_EDR_FDR_CONFIG1_ADDR 0x0110002aL
+#define IBU_P1_PHY_EDR_FDR_CONFIG1_STRIDE 1
+#define IBU_P1_PHY_EDR_FDR_CONFIG1_DEPTH 1
+
+#define IBU_P1_PHY_LEAKY_BKT_THRSH_ADDR 0x0110002bL
+#define IBU_P1_PHY_LEAKY_BKT_THRSH_STRIDE 1
+#define IBU_P1_PHY_LEAKY_BKT_THRSH_DEPTH 1
+
+#define IBU_P1_RCV_TS3_STATUS_LOW_ADDR 0x0110002dL
+#define IBU_P1_RCV_TS3_STATUS_LOW_STRIDE 1
+#define IBU_P1_RCV_TS3_STATUS_LOW_DEPTH 1
+
+#define IBU_P1_RCV_TS3_STATUS_HIGH_ADDR 0x0110002eL
+#define IBU_P1_RCV_TS3_STATUS_HIGH_STRIDE 1
+#define IBU_P1_RCV_TS3_STATUS_HIGH_DEPTH 1
+
+#define IBU_P1_GUID0_ADDR 0x0110002fL
+#define IBU_P1_GUID0_STRIDE 1
+#define IBU_P1_GUID0_DEPTH 1
+
+#define IBU_P1_GUID1_ADDR 0x01100030L
+#define IBU_P1_GUID1_STRIDE 1
+#define IBU_P1_GUID1_DEPTH 1
+
+#define IBU_P1_PNUM_ADDR 0x01100031L
+#define IBU_P1_PNUM_STRIDE 1
+#define IBU_P1_PNUM_DEPTH 1
+
+#define IBU_P1_CNT4MS_ADDR 0x01100032L
+#define IBU_P1_CNT4MS_STRIDE 1
+#define IBU_P1_CNT4MS_DEPTH 1
+
+#define IBU_P1_CNT36MS_ADDR 0x01100033L
+#define IBU_P1_CNT36MS_STRIDE 1
+#define IBU_P1_CNT36MS_DEPTH 1
+
+#define IBU_P1_PHY_TS3_CONFIG_ADDR 0x01100034L
+#define IBU_P1_PHY_TS3_CONFIG_STRIDE 1
+#define IBU_P1_PHY_TS3_CONFIG_DEPTH 1
+
+#define IBU_P1_DDS_WINDOW_START_ADDR 0x01100035L
+#define IBU_P1_DDS_WINDOW_START_STRIDE 1
+#define IBU_P1_DDS_WINDOW_START_DEPTH 1
+
+#define IBU_P1_DDS_WINDOW_END_ADDR 0x01100036L
+#define IBU_P1_DDS_WINDOW_END_STRIDE 1
+#define IBU_P1_DDS_WINDOW_END_DEPTH 1
+
+#define IBU_P1_DDS_DEFAULT_WINDOW_END_ADDR 0x01100037L
+#define IBU_P1_DDS_DEFAULT_WINDOW_END_STRIDE 1
+#define IBU_P1_DDS_DEFAULT_WINDOW_END_DEPTH 1
+
+#define IBU_P1_RX_TS3DDS_STATUS_ADDR 0x01100038L
+#define IBU_P1_RX_TS3DDS_STATUS_STRIDE 1
+#define IBU_P1_RX_TS3DDS_STATUS_DEPTH 1
+
+#define IBU_P1_TX_TS3DDS_STATUS_ADDR 0x01100039L
+#define IBU_P1_TX_TS3DDS_STATUS_STRIDE 1
+#define IBU_P1_TX_TS3DDS_STATUS_DEPTH 1
+
+#define IBU_P1_CNT16MS_ADDR 0x0110003aL
+#define IBU_P1_CNT16MS_STRIDE 1
+#define IBU_P1_CNT16MS_DEPTH 1
+
+#define IBU_P1_CONF_TEST4MS_SCT_ADDR 0x0110003bL
+#define IBU_P1_CONF_TEST4MS_SCT_STRIDE 1
+#define IBU_P1_CONF_TEST4MS_SCT_DEPTH 1
+
+#define IBU_P1_CONF_TEST16MS_SCT_ADDR 0x0110003cL
+#define IBU_P1_CONF_TEST16MS_SCT_STRIDE 1
+#define IBU_P1_CONF_TEST16MS_SCT_DEPTH 1
+
+#define IBU_P1_LOCAL_ADDTEST_LIMIT_ADDR 0x0110003dL
+#define IBU_P1_LOCAL_ADDTEST_LIMIT_STRIDE 1
+#define IBU_P1_LOCAL_ADDTEST_LIMIT_DEPTH 1
+
+#define IBU_P1_REMOTE_ADDTEST_LIMIT_ADDR 0x0110003eL
+#define IBU_P1_REMOTE_ADDTEST_LIMIT_STRIDE 1
+#define IBU_P1_REMOTE_ADDTEST_LIMIT_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT4_COUNTER_ADDR 0x0110003fL
+#define IBU_P1_TS3_REV1_TT4_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT4_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT5_COUNTER_ADDR 0x01100040L
+#define IBU_P1_TS3_REV1_TT5_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT5_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT6_COUNTER_ADDR 0x01100041L
+#define IBU_P1_TS3_REV1_TT6_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT6_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT7_COUNTER_ADDR 0x01100042L
+#define IBU_P1_TS3_REV1_TT7_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT7_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT8_COUNTER_ADDR 0x01100043L
+#define IBU_P1_TS3_REV1_TT8_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT8_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT9_COUNTER_ADDR 0x01100044L
+#define IBU_P1_TS3_REV1_TT9_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT9_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT10_COUNTER_ADDR 0x01100045L
+#define IBU_P1_TS3_REV1_TT10_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT10_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT11_COUNTER_ADDR 0x01100046L
+#define IBU_P1_TS3_REV1_TT11_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT11_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT12_COUNTER_ADDR 0x01100047L
+#define IBU_P1_TS3_REV1_TT12_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT12_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT13_COUNTER_ADDR 0x01100048L
+#define IBU_P1_TS3_REV1_TT13_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT13_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT14_COUNTER_ADDR 0x01100049L
+#define IBU_P1_TS3_REV1_TT14_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT14_COUNTER_DEPTH 1
+
+#define IBU_P1_TS3_REV1_TT15_COUNTER_ADDR 0x0110004aL
+#define IBU_P1_TS3_REV1_TT15_COUNTER_STRIDE 1
+#define IBU_P1_TS3_REV1_TT15_COUNTER_DEPTH 1
+
+#define IBU_P1_CONF_TEST_LANE_ERROR_LIMIT_ADDR 0x0110004bL
+#define IBU_P1_CONF_TEST_LANE_ERROR_LIMIT_STRIDE 1
+#define IBU_P1_CONF_TEST_LANE_ERROR_LIMIT_DEPTH 1
+
+#define IBU_P1_CONF_TEST_IDLE_LIMIT_ADDR 0x0110004cL
+#define IBU_P1_CONF_TEST_IDLE_LIMIT_STRIDE 1
+#define IBU_P1_CONF_TEST_IDLE_LIMIT_DEPTH 1
+
+#define IBU_P1_CONF_TEST2MS_SCT_ADDR 0x0110004dL
+#define IBU_P1_CONF_TEST2MS_SCT_STRIDE 1
+#define IBU_P1_CONF_TEST2MS_SCT_DEPTH 1
+
+#define IBU_P1_CNT100_MS_HBR_ADDR 0x0110004eL
+#define IBU_P1_CNT100_MS_HBR_STRIDE 1
+#define IBU_P1_CNT100_MS_HBR_DEPTH 1
+
+#define IBU_P1_PMAEQULANE0_STATUS_ADDR 0x0110004fL
+#define IBU_P1_PMAEQULANE0_STATUS_STRIDE 1
+#define IBU_P1_PMAEQULANE0_STATUS_DEPTH 1
+
+#define IBU_P1_PMAEQULANE1_STATUS_ADDR 0x01100050L
+#define IBU_P1_PMAEQULANE1_STATUS_STRIDE 1
+#define IBU_P1_PMAEQULANE1_STATUS_DEPTH 1
+
+#define IBU_P1_PMAEQULANE2_STATUS_ADDR 0x01100051L
+#define IBU_P1_PMAEQULANE2_STATUS_STRIDE 1
+#define IBU_P1_PMAEQULANE2_STATUS_DEPTH 1
+
+#define IBU_P1_PMAEQULANE3_STATUS_ADDR 0x01100052L
+#define IBU_P1_PMAEQULANE3_STATUS_STRIDE 1
+#define IBU_P1_PMAEQULANE3_STATUS_DEPTH 1
+
+#define IBU_P1_PMADDSLANE0_STATUS_ADDR 0x01100053L
+#define IBU_P1_PMADDSLANE0_STATUS_STRIDE 1
+#define IBU_P1_PMADDSLANE0_STATUS_DEPTH 1
+
+#define IBU_P1_PMADDSLANE1_STATUS_ADDR 0x01100054L
+#define IBU_P1_PMADDSLANE1_STATUS_STRIDE 1
+#define IBU_P1_PMADDSLANE1_STATUS_DEPTH 1
+
+#define IBU_P1_PMADDSLANE2_STATUS_ADDR 0x01100055L
+#define IBU_P1_PMADDSLANE2_STATUS_STRIDE 1
+#define IBU_P1_PMADDSLANE2_STATUS_DEPTH 1
+
+#define IBU_P1_PMADDSLANE3_STATUS_ADDR 0x01100056L
+#define IBU_P1_PMADDSLANE3_STATUS_STRIDE 1
+#define IBU_P1_PMADDSLANE3_STATUS_DEPTH 1
+
+#define IBU_P1_PHY_EDPL_ERR0_ADDR 0x01100057L
+#define IBU_P1_PHY_EDPL_ERR0_STRIDE 1
+#define IBU_P1_PHY_EDPL_ERR0_DEPTH 1
+
+#define IBU_P1_PHY_EDPL_ERR1_ADDR 0x01100058L
+#define IBU_P1_PHY_EDPL_ERR1_STRIDE 1
+#define IBU_P1_PHY_EDPL_ERR1_DEPTH 1
+
+#define IBU_P1_PHY_EDPL_ERR2_ADDR 0x01100059L
+#define IBU_P1_PHY_EDPL_ERR2_STRIDE 1
+#define IBU_P1_PHY_EDPL_ERR2_DEPTH 1
+
+#define IBU_P1_PHY_EDPL_ERR3_ADDR 0x0110005aL
+#define IBU_P1_PHY_EDPL_ERR3_STRIDE 1
+#define IBU_P1_PHY_EDPL_ERR3_DEPTH 1
+
+#define IBU_P1_PHY_BLK_TYPE_ERR_ADDR 0x0110005bL
+#define IBU_P1_PHY_BLK_TYPE_ERR_STRIDE 1
+#define IBU_P1_PHY_BLK_TYPE_ERR_DEPTH 1
+
+#define IBU_P1_PHY_BLK_EOP_ERR_ADDR 0x0110005cL
+#define IBU_P1_PHY_BLK_EOP_ERR_STRIDE 1
+#define IBU_P1_PHY_BLK_EOP_ERR_DEPTH 1
+
+#define IBU_P1_PHY_CIN_PKT_ERR_ADDR 0x0110005dL
+#define IBU_P1_PHY_CIN_PKT_ERR_STRIDE 1
+#define IBU_P1_PHY_CIN_PKT_ERR_DEPTH 1
+
+#define IBU_P1_PHY_SYN_HDR_ERR_ADDR 0x0110005eL
+#define IBU_P1_PHY_SYN_HDR_ERR_STRIDE 1
+#define IBU_P1_PHY_SYN_HDR_ERR_DEPTH 1
+
+#define IBU_P1_PHY_PRBS_ERR0_ADDR 0x0110005fL
+#define IBU_P1_PHY_PRBS_ERR0_STRIDE 1
+#define IBU_P1_PHY_PRBS_ERR0_DEPTH 1
+
+#define IBU_P1_PHY_PRBS_ERR1_ADDR 0x01100060L
+#define IBU_P1_PHY_PRBS_ERR1_STRIDE 1
+#define IBU_P1_PHY_PRBS_ERR1_DEPTH 1
+
+#define IBU_P1_PHY_PRBS_ERR2_ADDR 0x01100061L
+#define IBU_P1_PHY_PRBS_ERR2_STRIDE 1
+#define IBU_P1_PHY_PRBS_ERR2_DEPTH 1
+
+#define IBU_P1_PHY_PRBS_ERR3_ADDR 0x01100062L
+#define IBU_P1_PHY_PRBS_ERR3_STRIDE 1
+#define IBU_P1_PHY_PRBS_ERR3_DEPTH 1
+
+#define IBU_P1_PHY_DESKEW_STATUS_ADDR 0x01100063L
+#define IBU_P1_PHY_DESKEW_STATUS_STRIDE 1
+#define IBU_P1_PHY_DESKEW_STATUS_DEPTH 1
+
+#define IBU_P1_PHY_FECUNC_ERR0_ADDR 0x01100064L
+#define IBU_P1_PHY_FECUNC_ERR0_STRIDE 1
+#define IBU_P1_PHY_FECUNC_ERR0_DEPTH 1
+
+#define IBU_P1_PHY_FECUNC_ERR1_ADDR 0x01100065L
+#define IBU_P1_PHY_FECUNC_ERR1_STRIDE 1
+#define IBU_P1_PHY_FECUNC_ERR1_DEPTH 1
+
+#define IBU_P1_PHY_FECUNC_ERR2_ADDR 0x01100066L
+#define IBU_P1_PHY_FECUNC_ERR2_STRIDE 1
+#define IBU_P1_PHY_FECUNC_ERR2_DEPTH 1
+
+#define IBU_P1_PHY_FECUNC_ERR3_ADDR 0x01100067L
+#define IBU_P1_PHY_FECUNC_ERR3_STRIDE 1
+#define IBU_P1_PHY_FECUNC_ERR3_DEPTH 1
+
+#define IBU_P1_PHY_FECCOR_ERR0_ADDR 0x01100068L
+#define IBU_P1_PHY_FECCOR_ERR0_STRIDE 1
+#define IBU_P1_PHY_FECCOR_ERR0_DEPTH 1
+
+#define IBU_P1_PHY_FECCOR_ERR1_ADDR 0x01100069L
+#define IBU_P1_PHY_FECCOR_ERR1_STRIDE 1
+#define IBU_P1_PHY_FECCOR_ERR1_DEPTH 1
+
+#define IBU_P1_PHY_FECCOR_ERR2_ADDR 0x0110006aL
+#define IBU_P1_PHY_FECCOR_ERR2_STRIDE 1
+#define IBU_P1_PHY_FECCOR_ERR2_DEPTH 1
+
+#define IBU_P1_PHY_FECCOR_ERR3_ADDR 0x0110006bL
+#define IBU_P1_PHY_FECCOR_ERR3_STRIDE 1
+#define IBU_P1_PHY_FECCOR_ERR3_DEPTH 1
+
+#define IBU_P1_PHY_SMSTATUS_ADDR 0x0110006cL
+#define IBU_P1_PHY_SMSTATUS_STRIDE 1
+#define IBU_P1_PHY_SMSTATUS_DEPTH 1
+
+#define IBU_P1_PHY_TS3_NEGOTIATED_STATUS_ADDR 0x0110006dL
+#define IBU_P1_PHY_TS3_NEGOTIATED_STATUS_STRIDE 1
+#define IBU_P1_PHY_TS3_NEGOTIATED_STATUS_DEPTH 1
+
+#define IBU_P1_PHY_TEST_ADDR 0x0110006eL
+#define IBU_P1_PHY_TEST_STRIDE 1
+#define IBU_P1_PHY_TEST_DEPTH 1
+
+#define IBU_P1_EDR_FDR_RX_STATUS_REG0_ADDR 0x0110006fL
+#define IBU_P1_EDR_FDR_RX_STATUS_REG0_STRIDE 1
+#define IBU_P1_EDR_FDR_RX_STATUS_REG0_DEPTH 1
+
+#define IBU_P1_EDR_FDR_RX_STATUS_REG1_ADDR 0x01100070L
+#define IBU_P1_EDR_FDR_RX_STATUS_REG1_STRIDE 1
+#define IBU_P1_EDR_FDR_RX_STATUS_REG1_DEPTH 1
+
+#define IBU_P1_EDR_FDR_RX_STATUS_REG2_ADDR 0x01100071L
+#define IBU_P1_EDR_FDR_RX_STATUS_REG2_STRIDE 1
+#define IBU_P1_EDR_FDR_RX_STATUS_REG2_DEPTH 1
+
+#define IBU_P1_EDR_FDR_TX_STATUS_REG0_ADDR 0x01100072L
+#define IBU_P1_EDR_FDR_TX_STATUS_REG0_STRIDE 1
+#define IBU_P1_EDR_FDR_TX_STATUS_REG0_DEPTH 1
+
+#define IBU_P1_INT_PRIORITY_ADDR 0x01100073L
+#define IBU_P1_INT_PRIORITY_STRIDE 1
+#define IBU_P1_INT_PRIORITY_DEPTH 1
+
+#define IBU_P1_INT_FATAL_ADDR 0x01100074L
+#define IBU_P1_INT_FATAL_STRIDE 1
+#define IBU_P1_INT_FATAL_DEPTH 1
+
+#define IBU_P1_LINK_ROUND_TRIP_LATENCY_ADDR 0x01100075L
+#define IBU_P1_LINK_ROUND_TRIP_LATENCY_STRIDE 1
+#define IBU_P1_LINK_ROUND_TRIP_LATENCY_DEPTH 1
+
+#define IBU_P1_PHY_FORCE_LEGACY_MODE_ADDR 0x01100076L
+#define IBU_P1_PHY_FORCE_LEGACY_MODE_STRIDE 1
+#define IBU_P1_PHY_FORCE_LEGACY_MODE_DEPTH 1
+
+#define IBU_P1_SERDES_BYPASS_ADDR 0x01100077L
+#define IBU_P1_SERDES_BYPASS_STRIDE 1
+#define IBU_P1_SERDES_BYPASS_DEPTH 1
+
+#define IBU_P1_LID_ADDR 0x01100100L
+#define IBU_P1_LID_STRIDE 1
+#define IBU_P1_LID_DEPTH 1
+
+#define IBU_P1_LMC_ADDR 0x01100101L
+#define IBU_P1_LMC_STRIDE 1
+#define IBU_P1_LMC_DEPTH 1
+
+#define IBU_P1_PORT_STATE_ADDR 0x01100102L
+#define IBU_P1_PORT_STATE_STRIDE 1
+#define IBU_P1_PORT_STATE_DEPTH 1
+
+#define IBU_P1_VLCAP_ADDR 0x01100103L
+#define IBU_P1_VLCAP_STRIDE 1
+#define IBU_P1_VLCAP_DEPTH 1
+
+#define IBU_P1_NEIGHBOR_MTU_ADDR 0x01100104L
+#define IBU_P1_NEIGHBOR_MTU_STRIDE 1
+#define IBU_P1_NEIGHBOR_MTU_DEPTH 1
+
+#define IBU_P1_VLHIGH_LIMIT_ADDR 0x01100105L
+#define IBU_P1_VLHIGH_LIMIT_STRIDE 1
+#define IBU_P1_VLHIGH_LIMIT_DEPTH 1
+
+#define IBU_P1_VLARBITRATION_HIGH_CAP_ADDR 0x01100106L
+#define IBU_P1_VLARBITRATION_HIGH_CAP_STRIDE 1
+#define IBU_P1_VLARBITRATION_HIGH_CAP_DEPTH 1
+
+#define IBU_P1_VLARBITRATION_LOW_CAP_ADDR 0x01100107L
+#define IBU_P1_VLARBITRATION_LOW_CAP_STRIDE 1
+#define IBU_P1_VLARBITRATION_LOW_CAP_DEPTH 1
+
+#define IBU_P1_MTUCAP_ADDR 0x01100108L
+#define IBU_P1_MTUCAP_STRIDE 1
+#define IBU_P1_MTUCAP_DEPTH 1
+
+#define IBU_P1_OPERATIONAL_VLS_ADDR 0x01100109L
+#define IBU_P1_OPERATIONAL_VLS_STRIDE 1
+#define IBU_P1_OPERATIONAL_VLS_DEPTH 1
+
+#define IBU_P1_PCPORT_RCV_ERROR_ADDR 0x0110010cL
+#define IBU_P1_PCPORT_RCV_ERROR_STRIDE 1
+#define IBU_P1_PCPORT_RCV_ERROR_DEPTH 1
+
+#define IBU_P1_PCPORT_RCV_REMOTE_PHYSICAL_ERRORS_ADDR 0x0110010dL
+#define IBU_P1_PCPORT_RCV_REMOTE_PHYSICAL_ERRORS_STRIDE 1
+#define IBU_P1_PCPORT_RCV_REMOTE_PHYSICAL_ERRORS_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_DISCARDS_ADDR 0x0110010eL
+#define IBU_P1_PCPORT_XMIT_DISCARDS_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_DISCARDS_DEPTH 1
+
+#define IBU_P1_PCLOCAL_LINK_INTEGRITY_ERRORS_ADDR 0x0110010fL
+#define IBU_P1_PCLOCAL_LINK_INTEGRITY_ERRORS_STRIDE 1
+#define IBU_P1_PCLOCAL_LINK_INTEGRITY_ERRORS_DEPTH 1
+
+#define IBU_P1_PCEXCESSIVE_BUFFER_OVERRUN_ERRORS_ADDR 0x01100110L
+#define IBU_P1_PCEXCESSIVE_BUFFER_OVERRUN_ERRORS_STRIDE 1
+#define IBU_P1_PCEXCESSIVE_BUFFER_OVERRUN_ERRORS_DEPTH 1
+
+#define IBU_P1_PCVL15_DROPPED_ADDR 0x01100111L
+#define IBU_P1_PCVL15_DROPPED_STRIDE 1
+#define IBU_P1_PCVL15_DROPPED_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_WAIT_ADDR 0x01100112L
+#define IBU_P1_PCPORT_XMIT_WAIT_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_WAIT_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_DATA_LSQW_ADDR 0x01100113L
+#define IBU_P1_PCPORT_XMIT_DATA_LSQW_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_DATA_LSQW_DEPTH 1
+
+#define IBU_P1_LINK_ERROR_CHECK_ENABLE_ADDR 0x01100114L
+#define IBU_P1_LINK_ERROR_CHECK_ENABLE_STRIDE 1
+#define IBU_P1_LINK_ERROR_CHECK_ENABLE_DEPTH 1
+
+#define IBU_P1_PCPORT_RCV_DATA_LSQW_ADDR 0x01100115L
+#define IBU_P1_PCPORT_RCV_DATA_LSQW_STRIDE 1
+#define IBU_P1_PCPORT_RCV_DATA_LSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_RCV_DATA_HSQW_ADDR 0x01100116L
+#define IBU_P1_PCPORT_RCV_DATA_HSQW_STRIDE 1
+#define IBU_P1_PCPORT_RCV_DATA_HSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_PKTS_LSQW_ADDR 0x01100117L
+#define IBU_P1_PCPORT_XMIT_PKTS_LSQW_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_PKTS_LSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_PKTS_HSQW_ADDR 0x01100118L
+#define IBU_P1_PCPORT_XMIT_PKTS_HSQW_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_PKTS_HSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_RCV_PKTS_LSQW_ADDR 0x01100119L
+#define IBU_P1_PCPORT_RCV_PKTS_LSQW_STRIDE 1
+#define IBU_P1_PCPORT_RCV_PKTS_LSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_RCV_PKTS_HSQW_ADDR 0x0110011aL
+#define IBU_P1_PCPORT_RCV_PKTS_HSQW_STRIDE 1
+#define IBU_P1_PCPORT_RCV_PKTS_HSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_UCXMIT_PKTS_LSQW_ADDR 0x0110011bL
+#define IBU_P1_PCPORT_UCXMIT_PKTS_LSQW_STRIDE 1
+#define IBU_P1_PCPORT_UCXMIT_PKTS_LSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_UCXMIT_PKTS_HSQW_ADDR 0x0110011cL
+#define IBU_P1_PCPORT_UCXMIT_PKTS_HSQW_STRIDE 1
+#define IBU_P1_PCPORT_UCXMIT_PKTS_HSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_MCXMIT_PKTS_LSQW_ADDR 0x0110011dL
+#define IBU_P1_PCPORT_MCXMIT_PKTS_LSQW_STRIDE 1
+#define IBU_P1_PCPORT_MCXMIT_PKTS_LSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_MCXMIT_PKTS_HSQW_ADDR 0x0110011eL
+#define IBU_P1_PCPORT_MCXMIT_PKTS_HSQW_STRIDE 1
+#define IBU_P1_PCPORT_MCXMIT_PKTS_HSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_UCRCV_PKTS_LSQW_ADDR 0x0110011fL
+#define IBU_P1_PCPORT_UCRCV_PKTS_LSQW_STRIDE 1
+#define IBU_P1_PCPORT_UCRCV_PKTS_LSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_UCRCV_PKTS_HSQW_ADDR 0x01100120L
+#define IBU_P1_PCPORT_UCRCV_PKTS_HSQW_STRIDE 1
+#define IBU_P1_PCPORT_UCRCV_PKTS_HSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_MCRCV_PKTS_LSQW_ADDR 0x01100121L
+#define IBU_P1_PCPORT_MCRCV_PKTS_LSQW_STRIDE 1
+#define IBU_P1_PCPORT_MCRCV_PKTS_LSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_MCRCV_PKTS_HSQW_ADDR 0x01100122L
+#define IBU_P1_PCPORT_MCRCV_PKTS_HSQW_STRIDE 1
+#define IBU_P1_PCPORT_MCRCV_PKTS_HSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_WAIT_VL0_ADDR 0x01100123L
+#define IBU_P1_PCPORT_XMIT_WAIT_VL0_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_WAIT_VL0_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_WAIT_VL1_ADDR 0x01100124L
+#define IBU_P1_PCPORT_XMIT_WAIT_VL1_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_WAIT_VL1_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_WAIT_VL2_ADDR 0x01100125L
+#define IBU_P1_PCPORT_XMIT_WAIT_VL2_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_WAIT_VL2_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_WAIT_VL3_ADDR 0x01100126L
+#define IBU_P1_PCPORT_XMIT_WAIT_VL3_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_WAIT_VL3_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_WAIT_VL4_ADDR 0x01100127L
+#define IBU_P1_PCPORT_XMIT_WAIT_VL4_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_WAIT_VL4_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_WAIT_VL5_ADDR 0x01100128L
+#define IBU_P1_PCPORT_XMIT_WAIT_VL5_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_WAIT_VL5_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_WAIT_VL6_ADDR 0x01100129L
+#define IBU_P1_PCPORT_XMIT_WAIT_VL6_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_WAIT_VL6_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_WAIT_VL7_ADDR 0x0110012aL
+#define IBU_P1_PCPORT_XMIT_WAIT_VL7_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_WAIT_VL7_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_WAIT_VL15_ADDR 0x0110012bL
+#define IBU_P1_PCPORT_XMIT_WAIT_VL15_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_WAIT_VL15_DEPTH 1
+
+#define IBU_P1_PCRX_LINK_CNT_RST_ADDR 0x0110012cL
+#define IBU_P1_PCRX_LINK_CNT_RST_STRIDE 1
+#define IBU_P1_PCRX_LINK_CNT_RST_DEPTH 1
+
+#define IBU_P1_PCRX_LINK_CNT_LOAD_ADDR 0x0110012dL
+#define IBU_P1_PCRX_LINK_CNT_LOAD_STRIDE 1
+#define IBU_P1_PCRX_LINK_CNT_LOAD_DEPTH 1
+
+#define IBU_P1_LOCAL_PHY_ERRORS_ADDR 0x0110012eL
+#define IBU_P1_LOCAL_PHY_ERRORS_STRIDE 1
+#define IBU_P1_LOCAL_PHY_ERRORS_DEPTH 1
+
+#define IBU_P1_OVERRUN_ERRORS_ADDR 0x0110012fL
+#define IBU_P1_OVERRUN_ERRORS_STRIDE 1
+#define IBU_P1_OVERRUN_ERRORS_DEPTH 1
+
+#define IBU_P1_PSLINK_DLID_ADDR 0x01100130L
+#define IBU_P1_PSLINK_DLID_STRIDE 1
+#define IBU_P1_PSLINK_DLID_DEPTH 1
+
+#define IBU_P1_PSTICK_ADDR 0x01100131L
+#define IBU_P1_PSTICK_STRIDE 1
+#define IBU_P1_PSTICK_DEPTH 1
+
+#define IBU_P1_PSSTATUS_ADDR 0x01100132L
+#define IBU_P1_PSSTATUS_STRIDE 1
+#define IBU_P1_PSSTATUS_DEPTH 1
+
+#define IBU_P1_PSSTART_DELAY_ADDR 0x01100133L
+#define IBU_P1_PSSTART_DELAY_STRIDE 1
+#define IBU_P1_PSSTART_DELAY_DEPTH 1
+
+#define IBU_P1_PSINTERVAL_ADDR 0x01100134L
+#define IBU_P1_PSINTERVAL_STRIDE 1
+#define IBU_P1_PSINTERVAL_DEPTH 1
+
+#define IBU_P1_PSCNT_SEL0_ADDR 0x01100135L
+#define IBU_P1_PSCNT_SEL0_STRIDE 1
+#define IBU_P1_PSCNT_SEL0_DEPTH 1
+
+#define IBU_P1_PSCNT_SEL1_ADDR 0x01100136L
+#define IBU_P1_PSCNT_SEL1_STRIDE 1
+#define IBU_P1_PSCNT_SEL1_DEPTH 1
+
+#define IBU_P1_PSCNT_SEL2_ADDR 0x01100137L
+#define IBU_P1_PSCNT_SEL2_STRIDE 1
+#define IBU_P1_PSCNT_SEL2_DEPTH 1
+
+#define IBU_P1_PSCNT_SEL3_ADDR 0x01100138L
+#define IBU_P1_PSCNT_SEL3_STRIDE 1
+#define IBU_P1_PSCNT_SEL3_DEPTH 1
+
+#define IBU_P1_PSCNT0_ADDR 0x01100139L
+#define IBU_P1_PSCNT0_STRIDE 1
+#define IBU_P1_PSCNT0_DEPTH 1
+
+#define IBU_P1_PSCNT1_ADDR 0x0110013aL
+#define IBU_P1_PSCNT1_STRIDE 1
+#define IBU_P1_PSCNT1_DEPTH 1
+
+#define IBU_P1_PSCNT2_ADDR 0x0110013bL
+#define IBU_P1_PSCNT2_STRIDE 1
+#define IBU_P1_PSCNT2_DEPTH 1
+
+#define IBU_P1_PSCNT3_ADDR 0x0110013cL
+#define IBU_P1_PSCNT3_STRIDE 1
+#define IBU_P1_PSCNT3_DEPTH 1
+
+#define IBU_P1_PSINIT_SAMPLING_ADDR 0x0110013dL
+#define IBU_P1_PSINIT_SAMPLING_STRIDE 1
+#define IBU_P1_PSINIT_SAMPLING_DEPTH 1
+
+#define IBU_P1_PSCNT_LOAD_ADDR 0x0110013eL
+#define IBU_P1_PSCNT_LOAD_STRIDE 1
+#define IBU_P1_PSCNT_LOAD_DEPTH 1
+
+#define IBU_P1_PORT_STATE_CHANGE_ADDR 0x0110013fL
+#define IBU_P1_PORT_STATE_CHANGE_STRIDE 1
+#define IBU_P1_PORT_STATE_CHANGE_DEPTH 1
+
+#define IBU_P1_LINK_VCONFIG0_ADDR 0x01100141L
+#define IBU_P1_LINK_VCONFIG0_STRIDE 1
+#define IBU_P1_LINK_VCONFIG0_DEPTH 1
+
+#define IBU_P1_LINK_VCONFIG1_ADDR 0x01100142L
+#define IBU_P1_LINK_VCONFIG1_STRIDE 1
+#define IBU_P1_LINK_VCONFIG1_DEPTH 1
+
+#define IBU_P1_LINK_VCONFIG2_ADDR 0x01100143L
+#define IBU_P1_LINK_VCONFIG2_STRIDE 1
+#define IBU_P1_LINK_VCONFIG2_DEPTH 1
+
+#define IBU_P1_LINK_RX_CREDIT_VL1_0_ADDR 0x01100144L
+#define IBU_P1_LINK_RX_CREDIT_VL1_0_STRIDE 1
+#define IBU_P1_LINK_RX_CREDIT_VL1_0_DEPTH 1
+
+#define IBU_P1_LINK_RX_CREDIT_VL3_2_ADDR 0x01100145L
+#define IBU_P1_LINK_RX_CREDIT_VL3_2_STRIDE 1
+#define IBU_P1_LINK_RX_CREDIT_VL3_2_DEPTH 1
+
+#define IBU_P1_LINK_RX_CREDIT_VL5_4_ADDR 0x01100146L
+#define IBU_P1_LINK_RX_CREDIT_VL5_4_STRIDE 1
+#define IBU_P1_LINK_RX_CREDIT_VL5_4_DEPTH 1
+
+#define IBU_P1_LINK_RX_CREDIT_VL7_6_ADDR 0x01100147L
+#define IBU_P1_LINK_RX_CREDIT_VL7_6_STRIDE 1
+#define IBU_P1_LINK_RX_CREDIT_VL7_6_DEPTH 1
+
+#define IBU_P1_LINK_TX_CREDIT_VL1_0_ADDR 0x01100148L
+#define IBU_P1_LINK_TX_CREDIT_VL1_0_STRIDE 1
+#define IBU_P1_LINK_TX_CREDIT_VL1_0_DEPTH 1
+
+#define IBU_P1_LINK_TX_CREDIT_VL3_2_ADDR 0x01100149L
+#define IBU_P1_LINK_TX_CREDIT_VL3_2_STRIDE 1
+#define IBU_P1_LINK_TX_CREDIT_VL3_2_DEPTH 1
+
+#define IBU_P1_LINK_TX_CREDIT_VL5_4_ADDR 0x0110014aL
+#define IBU_P1_LINK_TX_CREDIT_VL5_4_STRIDE 1
+#define IBU_P1_LINK_TX_CREDIT_VL5_4_DEPTH 1
+
+#define IBU_P1_LINK_TX_CREDIT_VL7_6_ADDR 0x0110014bL
+#define IBU_P1_LINK_TX_CREDIT_VL7_6_STRIDE 1
+#define IBU_P1_LINK_TX_CREDIT_VL7_6_DEPTH 1
+
+#define IBU_P1_PCTX_LINK_CNT_RST_ADDR 0x0110014cL
+#define IBU_P1_PCTX_LINK_CNT_RST_STRIDE 1
+#define IBU_P1_PCTX_LINK_CNT_RST_DEPTH 1
+
+#define IBU_P1_PCTX_LINK_CNT_LOAD_ADDR 0x0110014dL
+#define IBU_P1_PCTX_LINK_CNT_LOAD_STRIDE 1
+#define IBU_P1_PCTX_LINK_CNT_LOAD_DEPTH 1
+
+#define IBU_P1_PSCNT_WIDTH_ADDR 0x0110014fL
+#define IBU_P1_PSCNT_WIDTH_STRIDE 1
+#define IBU_P1_PSCNT_WIDTH_DEPTH 1
+
+#define IBU_P1_PSCNT_MASK_ADDR 0x01100150L
+#define IBU_P1_PSCNT_MASK_STRIDE 1
+#define IBU_P1_PSCNT_MASK_DEPTH 1
+
+#define IBU_P1_PCICRC_RCV_ERRORS_ADDR 0x01100151L
+#define IBU_P1_PCICRC_RCV_ERRORS_STRIDE 1
+#define IBU_P1_PCICRC_RCV_ERRORS_DEPTH 1
+
+#define IBU_P1_PCVCRC_RCV_ERRORS_ADDR 0x01100152L
+#define IBU_P1_PCVCRC_RCV_ERRORS_STRIDE 1
+#define IBU_P1_PCVCRC_RCV_ERRORS_DEPTH 1
+
+#define IBU_P1_PCLEN_RCV_ERRORS_ADDR 0x01100153L
+#define IBU_P1_PCLEN_RCV_ERRORS_STRIDE 1
+#define IBU_P1_PCLEN_RCV_ERRORS_DEPTH 1
+
+#define IBU_P1_PCDLID_RCV_ERRORS_ADDR 0x01100154L
+#define IBU_P1_PCDLID_RCV_ERRORS_STRIDE 1
+#define IBU_P1_PCDLID_RCV_ERRORS_DEPTH 1
+
+#define IBU_P1_PCRCV_FCLEN_ERRORS_ADDR 0x01100155L
+#define IBU_P1_PCRCV_FCLEN_ERRORS_STRIDE 1
+#define IBU_P1_PCRCV_FCLEN_ERRORS_DEPTH 1
+
+#define IBU_P1_PCRCV_FCVL_ERRORS_ADDR 0x01100156L
+#define IBU_P1_PCRCV_FCVL_ERRORS_STRIDE 1
+#define IBU_P1_PCRCV_FCVL_ERRORS_DEPTH 1
+
+#define IBU_P1_PCRCV_FCCRC_ERRORS_ADDR 0x01100157L
+#define IBU_P1_PCRCV_FCCRC_ERRORS_STRIDE 1
+#define IBU_P1_PCRCV_FCCRC_ERRORS_DEPTH 1
+
+#define IBU_P1_PORT_LOCAL_PHYSICAL_ERRORS_ADDR 0x01100158L
+#define IBU_P1_PORT_LOCAL_PHYSICAL_ERRORS_STRIDE 1
+#define IBU_P1_PORT_LOCAL_PHYSICAL_ERRORS_DEPTH 1
+
+#define IBU_P1_PCMAL_FORMED_ERRORS_ADDR 0x01100159L
+#define IBU_P1_PCMAL_FORMED_ERRORS_STRIDE 1
+#define IBU_P1_PCMAL_FORMED_ERRORS_DEPTH 1
+
+#define IBU_P1_PCBUF_OVER_ERRORS_ADDR 0x0110015aL
+#define IBU_P1_PCBUF_OVER_ERRORS_STRIDE 1
+#define IBU_P1_PCBUF_OVER_ERRORS_DEPTH 1
+
+#define IBU_P1_PCVLMAP_ERRORS_ADDR 0x0110015bL
+#define IBU_P1_PCVLMAP_ERRORS_STRIDE 1
+#define IBU_P1_PCVLMAP_ERRORS_DEPTH 1
+
+#define IBU_P1_PCVLINIT_CREDIT_VL1_VL0_ADDR 0x0110015cL
+#define IBU_P1_PCVLINIT_CREDIT_VL1_VL0_STRIDE 1
+#define IBU_P1_PCVLINIT_CREDIT_VL1_VL0_DEPTH 1
+
+#define IBU_P1_PCVLINIT_CREDIT_VL3_VL2_ADDR 0x0110015dL
+#define IBU_P1_PCVLINIT_CREDIT_VL3_VL2_STRIDE 1
+#define IBU_P1_PCVLINIT_CREDIT_VL3_VL2_DEPTH 1
+
+#define IBU_P1_PCVLINIT_CREDIT_VL5_VL4_ADDR 0x0110015eL
+#define IBU_P1_PCVLINIT_CREDIT_VL5_VL4_STRIDE 1
+#define IBU_P1_PCVLINIT_CREDIT_VL5_VL4_DEPTH 1
+
+#define IBU_P1_PCVLINIT_CREDIT_VL7_VL6_ADDR 0x0110015fL
+#define IBU_P1_PCVLINIT_CREDIT_VL7_VL6_STRIDE 1
+#define IBU_P1_PCVLINIT_CREDIT_VL7_VL6_DEPTH 1
+
+#define IBU_P1_PCRX_VL07_ECC_COR_ERR_CNT_ADDR 0x01100160L
+#define IBU_P1_PCRX_VL07_ECC_COR_ERR_CNT_STRIDE 1
+#define IBU_P1_PCRX_VL07_ECC_COR_ERR_CNT_DEPTH 1
+
+#define IBU_P1_PCRX_VL07_ECC_UNC_ERR_CNT_ADDR 0x01100161L
+#define IBU_P1_PCRX_VL07_ECC_UNC_ERR_CNT_STRIDE 1
+#define IBU_P1_PCRX_VL07_ECC_UNC_ERR_CNT_DEPTH 1
+
+#define IBU_P1_PCRX_VL15_ECC_COR_ERR_CNT_ADDR 0x01100162L
+#define IBU_P1_PCRX_VL15_ECC_COR_ERR_CNT_STRIDE 1
+#define IBU_P1_PCRX_VL15_ECC_COR_ERR_CNT_DEPTH 1
+
+#define IBU_P1_PCRX_VL15_ECC_UNC_ERR_CNT_ADDR 0x01100163L
+#define IBU_P1_PCRX_VL15_ECC_UNC_ERR_CNT_STRIDE 1
+#define IBU_P1_PCRX_VL15_ECC_UNC_ERR_CNT_DEPTH 1
+
+#define IBU_P1_PCRX_LOOP_ECC_COR_ERR_CNT_ADDR 0x01100164L
+#define IBU_P1_PCRX_LOOP_ECC_COR_ERR_CNT_STRIDE 1
+#define IBU_P1_PCRX_LOOP_ECC_COR_ERR_CNT_DEPTH 1
+
+#define IBU_P1_PCRX_LOOP_ECC_UNC_ERR_CNT_ADDR 0x01100165L
+#define IBU_P1_PCRX_LOOP_ECC_UNC_ERR_CNT_STRIDE 1
+#define IBU_P1_PCRX_LOOP_ECC_UNC_ERR_CNT_DEPTH 1
+
+#define IBU_P1_PCECCENA_ERR_ADDR 0x01100166L
+#define IBU_P1_PCECCENA_ERR_STRIDE 1
+#define IBU_P1_PCECCENA_ERR_DEPTH 1
+
+#define IBU_P1_PCTX_ECC_COR_ERR_CNT_ADDR 0x01100167L
+#define IBU_P1_PCTX_ECC_COR_ERR_CNT_STRIDE 1
+#define IBU_P1_PCTX_ECC_COR_ERR_CNT_DEPTH 1
+
+#define IBU_P1_PCTX_ECC_UNC_ERR_CNT_ADDR 0x01100168L
+#define IBU_P1_PCTX_ECC_UNC_ERR_CNT_STRIDE 1
+#define IBU_P1_PCTX_ECC_UNC_ERR_CNT_DEPTH 1
+
+#define IBU_P1_TX_SRAMSTATUS_ADDR 0x01100169L
+#define IBU_P1_TX_SRAMSTATUS_STRIDE 1
+#define IBU_P1_TX_SRAMSTATUS_DEPTH 1
+
+#define IBU_P1_TX_CACHE_STATUS_ADDR 0x0110016aL
+#define IBU_P1_TX_CACHE_STATUS_STRIDE 1
+#define IBU_P1_TX_CACHE_STATUS_DEPTH 1
+
+#define IBU_P1_TX_DEBUG_ADDR 0x0110016bL
+#define IBU_P1_TX_DEBUG_STRIDE 1
+#define IBU_P1_TX_DEBUG_DEPTH 1
+
+#define IBU_P1_RX_VL07_SRAMSTATUS_ADDR 0x0110016cL
+#define IBU_P1_RX_VL07_SRAMSTATUS_STRIDE 1
+#define IBU_P1_RX_VL07_SRAMSTATUS_DEPTH 1
+
+#define IBU_P1_RX_VL15_SRAMSTATUS_ADDR 0x0110016dL
+#define IBU_P1_RX_VL15_SRAMSTATUS_STRIDE 1
+#define IBU_P1_RX_VL15_SRAMSTATUS_DEPTH 1
+
+#define IBU_P1_LOOPSRAMSTATUS_ADDR 0x0110016eL
+#define IBU_P1_LOOPSRAMSTATUS_STRIDE 1
+#define IBU_P1_LOOPSRAMSTATUS_DEPTH 1
+
+#define IBU_P1_RX_DEBUG_ADDR 0x0110016fL
+#define IBU_P1_RX_DEBUG_STRIDE 1
+#define IBU_P1_RX_DEBUG_DEPTH 1
+
+#define IBU_P1_TX_ARB_LOOPBACK_SRAMSTATUS_ADDR 0x01100170L
+#define IBU_P1_TX_ARB_LOOPBACK_SRAMSTATUS_STRIDE 1
+#define IBU_P1_TX_ARB_LOOPBACK_SRAMSTATUS_DEPTH 1
+
+#define IBU_P1_REMOTE_RX_BUFF_LIMIT_ADDR 0x01100171L
+#define IBU_P1_REMOTE_RX_BUFF_LIMIT_STRIDE 1
+#define IBU_P1_REMOTE_RX_BUFF_LIMIT_DEPTH 1
+
+#define IBU_P1_FCTX_TIMER_ADDR 0x01100172L
+#define IBU_P1_FCTX_TIMER_STRIDE 1
+#define IBU_P1_FCTX_TIMER_DEPTH 1
+
+#define IBU_P1_FCRX_TIMER_ADDR 0x01100173L
+#define IBU_P1_FCRX_TIMER_STRIDE 1
+#define IBU_P1_FCRX_TIMER_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_DATA_HSQW_ADDR 0x01100174L
+#define IBU_P1_PCPORT_XMIT_DATA_HSQW_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_DATA_HSQW_DEPTH 1
+
+#define IBU_P1_PCPORT_XMIT_VLDISCARDS_ADDR 0x01100175L
+#define IBU_P1_PCPORT_XMIT_VLDISCARDS_STRIDE 1
+#define IBU_P1_PCPORT_XMIT_VLDISCARDS_DEPTH 1
+
+#define IBU_P1_PCPORT_COL_LIMIT_ADDR 0x01100176L
+#define IBU_P1_PCPORT_COL_LIMIT_STRIDE 1
+#define IBU_P1_PCPORT_COL_LIMIT_DEPTH 1
+
+#define IBU_P1_VLARB_HI_PRI_TABLE_ADDR 0x01100180L
+#define IBU_P1_VLARB_HI_PRI_TABLE_STRIDE 1
+#define IBU_P1_VLARB_HI_PRI_TABLE_DEPTH 10
+
+#define IBU_P1_VLARB_LO_PRI_TABLE_ADDR 0x011001c0L
+#define IBU_P1_VLARB_LO_PRI_TABLE_STRIDE 1
+#define IBU_P1_VLARB_LO_PRI_TABLE_DEPTH 10
+
+#define IBU_P1_TX_TBSVL10_ADDR 0x011001d0L
+#define IBU_P1_TX_TBSVL10_STRIDE 1
+#define IBU_P1_TX_TBSVL10_DEPTH 1
+
+#define IBU_P1_TX_TBSVL32_ADDR 0x011001d1L
+#define IBU_P1_TX_TBSVL32_STRIDE 1
+#define IBU_P1_TX_TBSVL32_DEPTH 1
+
+#define IBU_P1_TX_TBSVL54_ADDR 0x011001d2L
+#define IBU_P1_TX_TBSVL54_STRIDE 1
+#define IBU_P1_TX_TBSVL54_DEPTH 1
+
+#define IBU_P1_TX_TBSVL76_ADDR 0x011001d3L
+#define IBU_P1_TX_TBSVL76_STRIDE 1
+#define IBU_P1_TX_TBSVL76_DEPTH 1
+
+#define IBU_P1_TX_TBSARB_VL10_ADDR 0x011001d4L
+#define IBU_P1_TX_TBSARB_VL10_STRIDE 1
+#define IBU_P1_TX_TBSARB_VL10_DEPTH 1
+
+#define IBU_P1_TX_TBSARB_VL32_ADDR 0x011001d5L
+#define IBU_P1_TX_TBSARB_VL32_STRIDE 1
+#define IBU_P1_TX_TBSARB_VL32_DEPTH 1
+
+#define IBU_P1_TX_TBSARB_VL54_ADDR 0x011001d6L
+#define IBU_P1_TX_TBSARB_VL54_STRIDE 1
+#define IBU_P1_TX_TBSARB_VL54_DEPTH 1
+
+#define IBU_P1_TX_TBSARB_VL76_ADDR 0x011001d7L
+#define IBU_P1_TX_TBSARB_VL76_STRIDE 1
+#define IBU_P1_TX_TBSARB_VL76_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_ENABLE_ADDR 0x011001d8L
+#define IBU_P1_RX_TRACE_CAPTURE_ENABLE_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_ENABLE_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_MODE_ADDR 0x011001d9L
+#define IBU_P1_RX_TRACE_CAPTURE_MODE_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_MODE_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_RDY_ADDR 0x011001daL
+#define IBU_P1_RX_TRACE_CAPTURE_RDY_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_RDY_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_TIMER_ADDR 0x011001dbL
+#define IBU_P1_RX_TRACE_CAPTURE_TIMER_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_TIMER_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_START_ADDR 0x011001dcL
+#define IBU_P1_RX_TRACE_CAPTURE_START_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_START_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_DATA1_ADDR 0x011001e0L
+#define IBU_P1_RX_TRACE_CAPTURE_DATA1_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_DATA1_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_DATA2_ADDR 0x011001e1L
+#define IBU_P1_RX_TRACE_CAPTURE_DATA2_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_DATA2_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_DATA3_ADDR 0x011001e2L
+#define IBU_P1_RX_TRACE_CAPTURE_DATA3_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_DATA3_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_DATA4_ADDR 0x011001e3L
+#define IBU_P1_RX_TRACE_CAPTURE_DATA4_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_DATA4_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_DATA5_ADDR 0x011001e4L
+#define IBU_P1_RX_TRACE_CAPTURE_DATA5_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_DATA5_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_DATA6_ADDR 0x011001e5L
+#define IBU_P1_RX_TRACE_CAPTURE_DATA6_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_DATA6_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_DATA7_ADDR 0x011001e6L
+#define IBU_P1_RX_TRACE_CAPTURE_DATA7_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_DATA7_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_DATA8_ADDR 0x011001e7L
+#define IBU_P1_RX_TRACE_CAPTURE_DATA8_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_DATA8_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_DATA9_ADDR 0x011001e8L
+#define IBU_P1_RX_TRACE_CAPTURE_DATA9_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_DATA9_DEPTH 1
+
+#define IBU_P1_RX_TRACE_CAPTURE_DATA10_ADDR 0x011001e9L
+#define IBU_P1_RX_TRACE_CAPTURE_DATA10_STRIDE 1
+#define IBU_P1_RX_TRACE_CAPTURE_DATA10_DEPTH 1
+
+#define IBU_P1_LINK_RX_FCCL_VL1_0_ADDR 0x011001eaL
+#define IBU_P1_LINK_RX_FCCL_VL1_0_STRIDE 1
+#define IBU_P1_LINK_RX_FCCL_VL1_0_DEPTH 1
+
+#define IBU_P1_LINK_RX_FCCL_VL3_2_ADDR 0x011001ebL
+#define IBU_P1_LINK_RX_FCCL_VL3_2_STRIDE 1
+#define IBU_P1_LINK_RX_FCCL_VL3_2_DEPTH 1
+
+#define IBU_P1_LINK_RX_FCCL_VL5_4_ADDR 0x011001ecL
+#define IBU_P1_LINK_RX_FCCL_VL5_4_STRIDE 1
+#define IBU_P1_LINK_RX_FCCL_VL5_4_DEPTH 1
+
+#define IBU_P1_LINK_RX_FCCL_VL7_6_ADDR 0x011001edL
+#define IBU_P1_LINK_RX_FCCL_VL7_6_STRIDE 1
+#define IBU_P1_LINK_RX_FCCL_VL7_6_DEPTH 1
+
+#define IBU_P1_LINK_NEIGHBOR_JUMBO_MTU_ADDR 0x011001eeL
+#define IBU_P1_LINK_NEIGHBOR_JUMBO_MTU_STRIDE 1
+#define IBU_P1_LINK_NEIGHBOR_JUMBO_MTU_DEPTH 1
+
+#define IBU_P1_ADD_DEFAULT_LANE0_ADDR 0x01100210L
+#define IBU_P1_ADD_DEFAULT_LANE0_STRIDE 1
+#define IBU_P1_ADD_DEFAULT_LANE0_DEPTH 1
+
+#define IBU_P1_ADD_DEFAULT_LANE1_ADDR 0x01100211L
+#define IBU_P1_ADD_DEFAULT_LANE1_STRIDE 1
+#define IBU_P1_ADD_DEFAULT_LANE1_DEPTH 1
+
+#define IBU_P1_ADD_DEFAULT_LANE2_ADDR 0x01100212L
+#define IBU_P1_ADD_DEFAULT_LANE2_STRIDE 1
+#define IBU_P1_ADD_DEFAULT_LANE2_DEPTH 1
+
+#define IBU_P1_ADD_DEFAULT_LANE3_ADDR 0x01100213L
+#define IBU_P1_ADD_DEFAULT_LANE3_STRIDE 1
+#define IBU_P1_ADD_DEFAULT_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD0_LANE0_ADDR 0x01100214L
+#define IBU_P1_PHY_ADD0_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD0_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD0_LANE1_ADDR 0x01100215L
+#define IBU_P1_PHY_ADD0_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD0_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD0_LANE2_ADDR 0x01100216L
+#define IBU_P1_PHY_ADD0_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD0_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD0_LANE3_ADDR 0x01100217L
+#define IBU_P1_PHY_ADD0_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD0_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD1_LANE0_ADDR 0x01100218L
+#define IBU_P1_PHY_ADD1_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD1_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD1_LANE1_ADDR 0x01100219L
+#define IBU_P1_PHY_ADD1_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD1_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD1_LANE2_ADDR 0x0110021aL
+#define IBU_P1_PHY_ADD1_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD1_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD1_LANE3_ADDR 0x0110021bL
+#define IBU_P1_PHY_ADD1_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD1_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD2_LANE0_ADDR 0x0110021cL
+#define IBU_P1_PHY_ADD2_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD2_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD2_LANE1_ADDR 0x0110021dL
+#define IBU_P1_PHY_ADD2_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD2_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD2_LANE2_ADDR 0x0110021eL
+#define IBU_P1_PHY_ADD2_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD2_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD2_LANE3_ADDR 0x0110021fL
+#define IBU_P1_PHY_ADD2_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD2_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD3_LANE0_ADDR 0x01100220L
+#define IBU_P1_PHY_ADD3_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD3_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD3_LANE1_ADDR 0x01100221L
+#define IBU_P1_PHY_ADD3_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD3_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD3_LANE2_ADDR 0x01100222L
+#define IBU_P1_PHY_ADD3_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD3_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD3_LANE3_ADDR 0x01100223L
+#define IBU_P1_PHY_ADD3_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD3_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD4_LANE0_ADDR 0x01100224L
+#define IBU_P1_PHY_ADD4_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD4_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD4_LANE1_ADDR 0x01100225L
+#define IBU_P1_PHY_ADD4_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD4_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD4_LANE2_ADDR 0x01100226L
+#define IBU_P1_PHY_ADD4_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD4_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD4_LANE3_ADDR 0x01100227L
+#define IBU_P1_PHY_ADD4_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD4_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD5_LANE0_ADDR 0x01100228L
+#define IBU_P1_PHY_ADD5_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD5_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD5_LANE1_ADDR 0x01100229L
+#define IBU_P1_PHY_ADD5_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD5_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD5_LANE2_ADDR 0x0110022aL
+#define IBU_P1_PHY_ADD5_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD5_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD5_LANE3_ADDR 0x0110022bL
+#define IBU_P1_PHY_ADD5_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD5_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD6_LANE0_ADDR 0x0110022cL
+#define IBU_P1_PHY_ADD6_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD6_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD6_LANE1_ADDR 0x0110022dL
+#define IBU_P1_PHY_ADD6_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD6_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD6_LANE2_ADDR 0x0110022eL
+#define IBU_P1_PHY_ADD6_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD6_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD6_LANE3_ADDR 0x0110022fL
+#define IBU_P1_PHY_ADD6_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD6_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD7_LANE0_ADDR 0x01100230L
+#define IBU_P1_PHY_ADD7_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD7_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD7_LANE1_ADDR 0x01100231L
+#define IBU_P1_PHY_ADD7_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD7_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD7_LANE2_ADDR 0x01100232L
+#define IBU_P1_PHY_ADD7_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD7_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD7_LANE3_ADDR 0x01100233L
+#define IBU_P1_PHY_ADD7_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD7_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD8_LANE0_ADDR 0x01100234L
+#define IBU_P1_PHY_ADD8_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD8_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD8_LANE1_ADDR 0x01100235L
+#define IBU_P1_PHY_ADD8_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD8_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD8_LANE2_ADDR 0x01100236L
+#define IBU_P1_PHY_ADD8_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD8_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD8_LANE3_ADDR 0x01100237L
+#define IBU_P1_PHY_ADD8_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD8_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD9_LANE0_ADDR 0x01100238L
+#define IBU_P1_PHY_ADD9_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD9_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD9_LANE1_ADDR 0x01100239L
+#define IBU_P1_PHY_ADD9_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD9_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD9_LANE2_ADDR 0x0110023aL
+#define IBU_P1_PHY_ADD9_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD9_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD9_LANE3_ADDR 0x0110023bL
+#define IBU_P1_PHY_ADD9_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD9_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD10_LANE0_ADDR 0x0110023cL
+#define IBU_P1_PHY_ADD10_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD10_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD10_LANE1_ADDR 0x0110023dL
+#define IBU_P1_PHY_ADD10_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD10_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD10_LANE2_ADDR 0x0110023eL
+#define IBU_P1_PHY_ADD10_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD10_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD10_LANE3_ADDR 0x0110023fL
+#define IBU_P1_PHY_ADD10_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD10_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD11_LANE0_ADDR 0x01100240L
+#define IBU_P1_PHY_ADD11_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD11_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD11_LANE1_ADDR 0x01100241L
+#define IBU_P1_PHY_ADD11_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD11_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD11_LANE2_ADDR 0x01100242L
+#define IBU_P1_PHY_ADD11_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD11_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD11_LANE3_ADDR 0x01100243L
+#define IBU_P1_PHY_ADD11_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD11_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD12_LANE0_ADDR 0x01100244L
+#define IBU_P1_PHY_ADD12_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD12_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD12_LANE1_ADDR 0x01100245L
+#define IBU_P1_PHY_ADD12_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD12_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD12_LANE2_ADDR 0x01100246L
+#define IBU_P1_PHY_ADD12_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD12_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD12_LANE3_ADDR 0x01100247L
+#define IBU_P1_PHY_ADD12_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD12_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD13_LANE0_ADDR 0x01100248L
+#define IBU_P1_PHY_ADD13_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD13_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD13_LANE1_ADDR 0x01100249L
+#define IBU_P1_PHY_ADD13_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD13_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD13_LANE2_ADDR 0x0110024aL
+#define IBU_P1_PHY_ADD13_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD13_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD13_LANE3_ADDR 0x0110024bL
+#define IBU_P1_PHY_ADD13_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD13_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD14_LANE0_ADDR 0x0110024cL
+#define IBU_P1_PHY_ADD14_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD14_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD14_LANE1_ADDR 0x0110024dL
+#define IBU_P1_PHY_ADD14_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD14_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD14_LANE2_ADDR 0x0110024eL
+#define IBU_P1_PHY_ADD14_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD14_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD14_LANE3_ADDR 0x0110024fL
+#define IBU_P1_PHY_ADD14_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD14_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_ADD15_LANE0_ADDR 0x01100250L
+#define IBU_P1_PHY_ADD15_LANE0_STRIDE 1
+#define IBU_P1_PHY_ADD15_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_ADD15_LANE1_ADDR 0x01100251L
+#define IBU_P1_PHY_ADD15_LANE1_STRIDE 1
+#define IBU_P1_PHY_ADD15_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_ADD15_LANE2_ADDR 0x01100252L
+#define IBU_P1_PHY_ADD15_LANE2_STRIDE 1
+#define IBU_P1_PHY_ADD15_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_ADD15_LANE3_ADDR 0x01100253L
+#define IBU_P1_PHY_ADD15_LANE3_STRIDE 1
+#define IBU_P1_PHY_ADD15_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD0_LANE0_ADDR 0x01100254L
+#define IBU_P1_PHY_AMP1_ADD0_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD0_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD0_LANE1_ADDR 0x01100255L
+#define IBU_P1_PHY_AMP1_ADD0_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD0_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD0_LANE2_ADDR 0x01100256L
+#define IBU_P1_PHY_AMP1_ADD0_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD0_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD0_LANE3_ADDR 0x01100257L
+#define IBU_P1_PHY_AMP1_ADD0_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD0_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD1_LANE0_ADDR 0x01100258L
+#define IBU_P1_PHY_AMP1_ADD1_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD1_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD1_LANE1_ADDR 0x01100259L
+#define IBU_P1_PHY_AMP1_ADD1_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD1_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD1_LANE2_ADDR 0x0110025aL
+#define IBU_P1_PHY_AMP1_ADD1_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD1_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD1_LANE3_ADDR 0x0110025bL
+#define IBU_P1_PHY_AMP1_ADD1_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD1_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD2_LANE0_ADDR 0x0110025cL
+#define IBU_P1_PHY_AMP1_ADD2_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD2_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD2_LANE1_ADDR 0x0110025dL
+#define IBU_P1_PHY_AMP1_ADD2_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD2_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD2_LANE2_ADDR 0x0110025eL
+#define IBU_P1_PHY_AMP1_ADD2_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD2_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD2_LANE3_ADDR 0x0110025fL
+#define IBU_P1_PHY_AMP1_ADD2_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD2_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD3_LANE0_ADDR 0x01100260L
+#define IBU_P1_PHY_AMP1_ADD3_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD3_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD3_LANE1_ADDR 0x01100261L
+#define IBU_P1_PHY_AMP1_ADD3_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD3_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD3_LANE2_ADDR 0x01100262L
+#define IBU_P1_PHY_AMP1_ADD3_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD3_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD3_LANE3_ADDR 0x01100263L
+#define IBU_P1_PHY_AMP1_ADD3_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD3_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD4_LANE0_ADDR 0x01100264L
+#define IBU_P1_PHY_AMP1_ADD4_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD4_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD4_LANE1_ADDR 0x01100265L
+#define IBU_P1_PHY_AMP1_ADD4_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD4_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD4_LANE2_ADDR 0x01100266L
+#define IBU_P1_PHY_AMP1_ADD4_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD4_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD4_LANE3_ADDR 0x01100267L
+#define IBU_P1_PHY_AMP1_ADD4_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD4_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD5_LANE0_ADDR 0x01100268L
+#define IBU_P1_PHY_AMP1_ADD5_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD5_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD5_LANE1_ADDR 0x01100269L
+#define IBU_P1_PHY_AMP1_ADD5_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD5_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD5_LANE2_ADDR 0x0110026aL
+#define IBU_P1_PHY_AMP1_ADD5_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD5_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD5_LANE3_ADDR 0x0110026bL
+#define IBU_P1_PHY_AMP1_ADD5_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD5_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD6_LANE0_ADDR 0x0110026cL
+#define IBU_P1_PHY_AMP1_ADD6_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD6_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD6_LANE1_ADDR 0x0110026dL
+#define IBU_P1_PHY_AMP1_ADD6_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD6_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD6_LANE2_ADDR 0x0110026eL
+#define IBU_P1_PHY_AMP1_ADD6_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD6_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD6_LANE3_ADDR 0x0110026fL
+#define IBU_P1_PHY_AMP1_ADD6_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD6_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD7_LANE0_ADDR 0x01100270L
+#define IBU_P1_PHY_AMP1_ADD7_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD7_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD7_LANE1_ADDR 0x01100271L
+#define IBU_P1_PHY_AMP1_ADD7_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD7_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD7_LANE2_ADDR 0x01100272L
+#define IBU_P1_PHY_AMP1_ADD7_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD7_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD7_LANE3_ADDR 0x01100273L
+#define IBU_P1_PHY_AMP1_ADD7_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD7_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD8_LANE0_ADDR 0x01100274L
+#define IBU_P1_PHY_AMP1_ADD8_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD8_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD8_LANE1_ADDR 0x01100275L
+#define IBU_P1_PHY_AMP1_ADD8_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD8_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD8_LANE2_ADDR 0x01100276L
+#define IBU_P1_PHY_AMP1_ADD8_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD8_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD8_LANE3_ADDR 0x01100277L
+#define IBU_P1_PHY_AMP1_ADD8_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD8_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD9_LANE0_ADDR 0x01100278L
+#define IBU_P1_PHY_AMP1_ADD9_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD9_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD9_LANE1_ADDR 0x01100279L
+#define IBU_P1_PHY_AMP1_ADD9_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD9_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD9_LANE2_ADDR 0x0110027aL
+#define IBU_P1_PHY_AMP1_ADD9_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD9_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD9_LANE3_ADDR 0x0110027bL
+#define IBU_P1_PHY_AMP1_ADD9_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD9_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD10_LANE0_ADDR 0x0110027cL
+#define IBU_P1_PHY_AMP1_ADD10_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD10_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD10_LANE1_ADDR 0x0110027dL
+#define IBU_P1_PHY_AMP1_ADD10_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD10_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD10_LANE2_ADDR 0x0110027eL
+#define IBU_P1_PHY_AMP1_ADD10_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD10_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD10_LANE3_ADDR 0x0110027fL
+#define IBU_P1_PHY_AMP1_ADD10_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD10_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD11_LANE0_ADDR 0x01100280L
+#define IBU_P1_PHY_AMP1_ADD11_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD11_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD11_LANE1_ADDR 0x01100281L
+#define IBU_P1_PHY_AMP1_ADD11_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD11_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD11_LANE2_ADDR 0x01100282L
+#define IBU_P1_PHY_AMP1_ADD11_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD11_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD11_LANE3_ADDR 0x01100283L
+#define IBU_P1_PHY_AMP1_ADD11_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD11_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD12_LANE0_ADDR 0x01100284L
+#define IBU_P1_PHY_AMP1_ADD12_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD12_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD12_LANE1_ADDR 0x01100285L
+#define IBU_P1_PHY_AMP1_ADD12_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD12_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD12_LANE2_ADDR 0x01100286L
+#define IBU_P1_PHY_AMP1_ADD12_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD12_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD12_LANE3_ADDR 0x01100287L
+#define IBU_P1_PHY_AMP1_ADD12_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD12_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD13_LANE0_ADDR 0x01100288L
+#define IBU_P1_PHY_AMP1_ADD13_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD13_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD13_LANE1_ADDR 0x01100289L
+#define IBU_P1_PHY_AMP1_ADD13_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD13_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD13_LANE2_ADDR 0x0110028aL
+#define IBU_P1_PHY_AMP1_ADD13_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD13_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD13_LANE3_ADDR 0x0110028bL
+#define IBU_P1_PHY_AMP1_ADD13_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD13_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD14_LANE0_ADDR 0x0110028cL
+#define IBU_P1_PHY_AMP1_ADD14_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD14_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD14_LANE1_ADDR 0x0110028dL
+#define IBU_P1_PHY_AMP1_ADD14_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD14_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD14_LANE2_ADDR 0x0110028eL
+#define IBU_P1_PHY_AMP1_ADD14_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD14_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD14_LANE3_ADDR 0x0110028fL
+#define IBU_P1_PHY_AMP1_ADD14_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD14_LANE3_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD15_LANE0_ADDR 0x01100290L
+#define IBU_P1_PHY_AMP1_ADD15_LANE0_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD15_LANE0_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD15_LANE1_ADDR 0x01100291L
+#define IBU_P1_PHY_AMP1_ADD15_LANE1_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD15_LANE1_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD15_LANE2_ADDR 0x01100292L
+#define IBU_P1_PHY_AMP1_ADD15_LANE2_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD15_LANE2_DEPTH 1
+
+#define IBU_P1_PHY_AMP1_ADD15_LANE3_ADDR 0x01100293L
+#define IBU_P1_PHY_AMP1_ADD15_LANE3_STRIDE 1
+#define IBU_P1_PHY_AMP1_ADD15_LANE3_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS0_ADDR 0x01100294L
+#define IBU_P1_REMOTE_DDS0_STRIDE 1
+#define IBU_P1_REMOTE_DDS0_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS1_ADDR 0x01100295L
+#define IBU_P1_REMOTE_DDS1_STRIDE 1
+#define IBU_P1_REMOTE_DDS1_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS2_ADDR 0x01100296L
+#define IBU_P1_REMOTE_DDS2_STRIDE 1
+#define IBU_P1_REMOTE_DDS2_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS3_ADDR 0x01100297L
+#define IBU_P1_REMOTE_DDS3_STRIDE 1
+#define IBU_P1_REMOTE_DDS3_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS4_ADDR 0x01100298L
+#define IBU_P1_REMOTE_DDS4_STRIDE 1
+#define IBU_P1_REMOTE_DDS4_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS5_ADDR 0x01100299L
+#define IBU_P1_REMOTE_DDS5_STRIDE 1
+#define IBU_P1_REMOTE_DDS5_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS6_ADDR 0x0110029aL
+#define IBU_P1_REMOTE_DDS6_STRIDE 1
+#define IBU_P1_REMOTE_DDS6_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS7_ADDR 0x0110029bL
+#define IBU_P1_REMOTE_DDS7_STRIDE 1
+#define IBU_P1_REMOTE_DDS7_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS8_ADDR 0x0110029cL
+#define IBU_P1_REMOTE_DDS8_STRIDE 1
+#define IBU_P1_REMOTE_DDS8_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS9_ADDR 0x0110029dL
+#define IBU_P1_REMOTE_DDS9_STRIDE 1
+#define IBU_P1_REMOTE_DDS9_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS10_ADDR 0x0110029eL
+#define IBU_P1_REMOTE_DDS10_STRIDE 1
+#define IBU_P1_REMOTE_DDS10_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS11_ADDR 0x0110029fL
+#define IBU_P1_REMOTE_DDS11_STRIDE 1
+#define IBU_P1_REMOTE_DDS11_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS12_ADDR 0x011002a0L
+#define IBU_P1_REMOTE_DDS12_STRIDE 1
+#define IBU_P1_REMOTE_DDS12_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS13_ADDR 0x011002a1L
+#define IBU_P1_REMOTE_DDS13_STRIDE 1
+#define IBU_P1_REMOTE_DDS13_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS14_ADDR 0x011002a2L
+#define IBU_P1_REMOTE_DDS14_STRIDE 1
+#define IBU_P1_REMOTE_DDS14_DEPTH 1
+
+#define IBU_P1_REMOTE_DDS15_ADDR 0x011002a3L
+#define IBU_P1_REMOTE_DDS15_STRIDE 1
+#define IBU_P1_REMOTE_DDS15_DEPTH 1
+
+#define IBU_P1_BAD_CSR_ADDR 0x01100badL
+#define IBU_P1_BAD_CSR_STRIDE 1
+#define IBU_P1_BAD_CSR_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH0_000_ADDR 0x01140000L
+#define IBU_P1_CETUS_CH0_000_STRIDE 1
+#define IBU_P1_CETUS_CH0_000_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH0_001_ADDR 0x01140001L
+#define IBU_P1_CETUS_CH0_001_STRIDE 1
+#define IBU_P1_CETUS_CH0_001_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH0_002_ADDR 0x01140002L
+#define IBU_P1_CETUS_CH0_002_STRIDE 1
+#define IBU_P1_CETUS_CH0_002_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_003_ADDR 0x01140003L
+#define IBU_P1_CETUS_CH0_003_STRIDE 1
+#define IBU_P1_CETUS_CH0_003_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_004_ADDR 0x01140004L
+#define IBU_P1_CETUS_CH0_004_STRIDE 1
+#define IBU_P1_CETUS_CH0_004_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_005_ADDR 0x01140005L
+#define IBU_P1_CETUS_CH0_005_STRIDE 1
+#define IBU_P1_CETUS_CH0_005_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_006_ADDR 0x01140006L
+#define IBU_P1_CETUS_CH0_006_STRIDE 1
+#define IBU_P1_CETUS_CH0_006_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_007_ADDR 0x01140007L
+#define IBU_P1_CETUS_CH0_007_STRIDE 1
+#define IBU_P1_CETUS_CH0_007_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_008_ADDR 0x01140008L
+#define IBU_P1_CETUS_CH0_008_STRIDE 1
+#define IBU_P1_CETUS_CH0_008_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_009_ADDR 0x01140009L
+#define IBU_P1_CETUS_CH0_009_STRIDE 1
+#define IBU_P1_CETUS_CH0_009_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_010_ADDR 0x0114000aL
+#define IBU_P1_CETUS_CH0_010_STRIDE 1
+#define IBU_P1_CETUS_CH0_010_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_011_ADDR 0x0114000bL
+#define IBU_P1_CETUS_CH0_011_STRIDE 1
+#define IBU_P1_CETUS_CH0_011_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_012_ADDR 0x0114000cL
+#define IBU_P1_CETUS_CH0_012_STRIDE 1
+#define IBU_P1_CETUS_CH0_012_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_013_ADDR 0x0114000dL
+#define IBU_P1_CETUS_CH0_013_STRIDE 1
+#define IBU_P1_CETUS_CH0_013_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_014_ADDR 0x0114000eL
+#define IBU_P1_CETUS_CH0_014_STRIDE 1
+#define IBU_P1_CETUS_CH0_014_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_015_ADDR 0x0114000fL
+#define IBU_P1_CETUS_CH0_015_STRIDE 1
+#define IBU_P1_CETUS_CH0_015_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_016_ADDR 0x01140010L
+#define IBU_P1_CETUS_CH0_016_STRIDE 1
+#define IBU_P1_CETUS_CH0_016_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_017_ADDR 0x01140011L
+#define IBU_P1_CETUS_CH0_017_STRIDE 1
+#define IBU_P1_CETUS_CH0_017_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_018_ADDR 0x01140012L
+#define IBU_P1_CETUS_CH0_018_STRIDE 1
+#define IBU_P1_CETUS_CH0_018_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_019_ADDR 0x01140013L
+#define IBU_P1_CETUS_CH0_019_STRIDE 1
+#define IBU_P1_CETUS_CH0_019_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_020_ADDR 0x01140014L
+#define IBU_P1_CETUS_CH0_020_STRIDE 1
+#define IBU_P1_CETUS_CH0_020_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_021_ADDR 0x01140015L
+#define IBU_P1_CETUS_CH0_021_STRIDE 1
+#define IBU_P1_CETUS_CH0_021_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_022_ADDR 0x01140016L
+#define IBU_P1_CETUS_CH0_022_STRIDE 1
+#define IBU_P1_CETUS_CH0_022_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_023_ADDR 0x01140017L
+#define IBU_P1_CETUS_CH0_023_STRIDE 1
+#define IBU_P1_CETUS_CH0_023_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_024_ADDR 0x01140018L
+#define IBU_P1_CETUS_CH0_024_STRIDE 1
+#define IBU_P1_CETUS_CH0_024_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_025_ADDR 0x01140019L
+#define IBU_P1_CETUS_CH0_025_STRIDE 1
+#define IBU_P1_CETUS_CH0_025_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_026_ADDR 0x0114001aL
+#define IBU_P1_CETUS_CH0_026_STRIDE 1
+#define IBU_P1_CETUS_CH0_026_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_027_ADDR 0x0114001bL
+#define IBU_P1_CETUS_CH0_027_STRIDE 1
+#define IBU_P1_CETUS_CH0_027_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_028_ADDR 0x0114001cL
+#define IBU_P1_CETUS_CH0_028_STRIDE 1
+#define IBU_P1_CETUS_CH0_028_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_029_ADDR 0x0114001dL
+#define IBU_P1_CETUS_CH0_029_STRIDE 1
+#define IBU_P1_CETUS_CH0_029_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_030_ADDR 0x0114001eL
+#define IBU_P1_CETUS_CH0_030_STRIDE 1
+#define IBU_P1_CETUS_CH0_030_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_031_ADDR 0x0114001fL
+#define IBU_P1_CETUS_CH0_031_STRIDE 1
+#define IBU_P1_CETUS_CH0_031_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_032_ADDR 0x01140020L
+#define IBU_P1_CETUS_CH0_032_STRIDE 1
+#define IBU_P1_CETUS_CH0_032_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_033_ADDR 0x01140021L
+#define IBU_P1_CETUS_CH0_033_STRIDE 1
+#define IBU_P1_CETUS_CH0_033_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_034_ADDR 0x01140022L
+#define IBU_P1_CETUS_CH0_034_STRIDE 1
+#define IBU_P1_CETUS_CH0_034_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_035_ADDR 0x01140023L
+#define IBU_P1_CETUS_CH0_035_STRIDE 1
+#define IBU_P1_CETUS_CH0_035_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_036_ADDR 0x01140024L
+#define IBU_P1_CETUS_CH0_036_STRIDE 1
+#define IBU_P1_CETUS_CH0_036_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_037_ADDR 0x01140025L
+#define IBU_P1_CETUS_CH0_037_STRIDE 1
+#define IBU_P1_CETUS_CH0_037_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_038_ADDR 0x01140026L
+#define IBU_P1_CETUS_CH0_038_STRIDE 1
+#define IBU_P1_CETUS_CH0_038_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_039_ADDR 0x01140027L
+#define IBU_P1_CETUS_CH0_039_STRIDE 1
+#define IBU_P1_CETUS_CH0_039_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_040_ADDR 0x01140028L
+#define IBU_P1_CETUS_CH0_040_STRIDE 1
+#define IBU_P1_CETUS_CH0_040_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_041_ADDR 0x01140029L
+#define IBU_P1_CETUS_CH0_041_STRIDE 1
+#define IBU_P1_CETUS_CH0_041_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_042_ADDR 0x0114002aL
+#define IBU_P1_CETUS_CH0_042_STRIDE 1
+#define IBU_P1_CETUS_CH0_042_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_043_ADDR 0x0114002bL
+#define IBU_P1_CETUS_CH0_043_STRIDE 1
+#define IBU_P1_CETUS_CH0_043_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_044_ADDR 0x0114002cL
+#define IBU_P1_CETUS_CH0_044_STRIDE 1
+#define IBU_P1_CETUS_CH0_044_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_045_ADDR 0x0114002dL
+#define IBU_P1_CETUS_CH0_045_STRIDE 1
+#define IBU_P1_CETUS_CH0_045_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_046_ADDR 0x0114002eL
+#define IBU_P1_CETUS_CH0_046_STRIDE 1
+#define IBU_P1_CETUS_CH0_046_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_047_ADDR 0x0114002fL
+#define IBU_P1_CETUS_CH0_047_STRIDE 1
+#define IBU_P1_CETUS_CH0_047_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_048_ADDR 0x01140030L
+#define IBU_P1_CETUS_CH0_048_STRIDE 1
+#define IBU_P1_CETUS_CH0_048_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_049_ADDR 0x01140031L
+#define IBU_P1_CETUS_CH0_049_STRIDE 1
+#define IBU_P1_CETUS_CH0_049_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_050_ADDR 0x01140032L
+#define IBU_P1_CETUS_CH0_050_STRIDE 1
+#define IBU_P1_CETUS_CH0_050_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_051_ADDR 0x01140033L
+#define IBU_P1_CETUS_CH0_051_STRIDE 1
+#define IBU_P1_CETUS_CH0_051_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_052_ADDR 0x01140034L
+#define IBU_P1_CETUS_CH0_052_STRIDE 1
+#define IBU_P1_CETUS_CH0_052_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_053_ADDR 0x01140035L
+#define IBU_P1_CETUS_CH0_053_STRIDE 1
+#define IBU_P1_CETUS_CH0_053_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_054_ADDR 0x01140036L
+#define IBU_P1_CETUS_CH0_054_STRIDE 1
+#define IBU_P1_CETUS_CH0_054_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_055_ADDR 0x01140037L
+#define IBU_P1_CETUS_CH0_055_STRIDE 1
+#define IBU_P1_CETUS_CH0_055_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_056_ADDR 0x01140038L
+#define IBU_P1_CETUS_CH0_056_STRIDE 1
+#define IBU_P1_CETUS_CH0_056_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_057_ADDR 0x01140039L
+#define IBU_P1_CETUS_CH0_057_STRIDE 1
+#define IBU_P1_CETUS_CH0_057_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_058_ADDR 0x0114003aL
+#define IBU_P1_CETUS_CH0_058_STRIDE 1
+#define IBU_P1_CETUS_CH0_058_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_059_ADDR 0x0114003bL
+#define IBU_P1_CETUS_CH0_059_STRIDE 1
+#define IBU_P1_CETUS_CH0_059_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_060_ADDR 0x0114003cL
+#define IBU_P1_CETUS_CH0_060_STRIDE 1
+#define IBU_P1_CETUS_CH0_060_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_061_ADDR 0x0114003dL
+#define IBU_P1_CETUS_CH0_061_STRIDE 1
+#define IBU_P1_CETUS_CH0_061_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_062_ADDR 0x0114003eL
+#define IBU_P1_CETUS_CH0_062_STRIDE 1
+#define IBU_P1_CETUS_CH0_062_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_063_ADDR 0x0114003fL
+#define IBU_P1_CETUS_CH0_063_STRIDE 1
+#define IBU_P1_CETUS_CH0_063_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_064_ADDR 0x01140040L
+#define IBU_P1_CETUS_CH0_064_STRIDE 1
+#define IBU_P1_CETUS_CH0_064_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_065_ADDR 0x01140041L
+#define IBU_P1_CETUS_CH0_065_STRIDE 1
+#define IBU_P1_CETUS_CH0_065_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_066_ADDR 0x01140042L
+#define IBU_P1_CETUS_CH0_066_STRIDE 1
+#define IBU_P1_CETUS_CH0_066_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_067_ADDR 0x01140043L
+#define IBU_P1_CETUS_CH0_067_STRIDE 1
+#define IBU_P1_CETUS_CH0_067_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_068_ADDR 0x01140044L
+#define IBU_P1_CETUS_CH0_068_STRIDE 1
+#define IBU_P1_CETUS_CH0_068_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_069_ADDR 0x01140045L
+#define IBU_P1_CETUS_CH0_069_STRIDE 1
+#define IBU_P1_CETUS_CH0_069_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_070_ADDR 0x01140046L
+#define IBU_P1_CETUS_CH0_070_STRIDE 1
+#define IBU_P1_CETUS_CH0_070_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_071_ADDR 0x01140047L
+#define IBU_P1_CETUS_CH0_071_STRIDE 1
+#define IBU_P1_CETUS_CH0_071_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_072_ADDR 0x01140048L
+#define IBU_P1_CETUS_CH0_072_STRIDE 1
+#define IBU_P1_CETUS_CH0_072_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_073_ADDR 0x01140049L
+#define IBU_P1_CETUS_CH0_073_STRIDE 1
+#define IBU_P1_CETUS_CH0_073_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_074_ADDR 0x0114004aL
+#define IBU_P1_CETUS_CH0_074_STRIDE 1
+#define IBU_P1_CETUS_CH0_074_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_075_ADDR 0x0114004bL
+#define IBU_P1_CETUS_CH0_075_STRIDE 1
+#define IBU_P1_CETUS_CH0_075_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_076_ADDR 0x0114004cL
+#define IBU_P1_CETUS_CH0_076_STRIDE 1
+#define IBU_P1_CETUS_CH0_076_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_077_ADDR 0x0114004dL
+#define IBU_P1_CETUS_CH0_077_STRIDE 1
+#define IBU_P1_CETUS_CH0_077_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_078_ADDR 0x0114004eL
+#define IBU_P1_CETUS_CH0_078_STRIDE 1
+#define IBU_P1_CETUS_CH0_078_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_079_ADDR 0x0114004fL
+#define IBU_P1_CETUS_CH0_079_STRIDE 1
+#define IBU_P1_CETUS_CH0_079_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_080_ADDR 0x01140050L
+#define IBU_P1_CETUS_CH0_080_STRIDE 1
+#define IBU_P1_CETUS_CH0_080_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_081_ADDR 0x01140051L
+#define IBU_P1_CETUS_CH0_081_STRIDE 1
+#define IBU_P1_CETUS_CH0_081_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_082_ADDR 0x01140052L
+#define IBU_P1_CETUS_CH0_082_STRIDE 1
+#define IBU_P1_CETUS_CH0_082_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_083_ADDR 0x01140053L
+#define IBU_P1_CETUS_CH0_083_STRIDE 1
+#define IBU_P1_CETUS_CH0_083_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_084_ADDR 0x01140054L
+#define IBU_P1_CETUS_CH0_084_STRIDE 1
+#define IBU_P1_CETUS_CH0_084_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_085_ADDR 0x01140055L
+#define IBU_P1_CETUS_CH0_085_STRIDE 1
+#define IBU_P1_CETUS_CH0_085_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_086_ADDR 0x01140056L
+#define IBU_P1_CETUS_CH0_086_STRIDE 1
+#define IBU_P1_CETUS_CH0_086_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_087_ADDR 0x01140057L
+#define IBU_P1_CETUS_CH0_087_STRIDE 1
+#define IBU_P1_CETUS_CH0_087_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_088_ADDR 0x01140058L
+#define IBU_P1_CETUS_CH0_088_STRIDE 1
+#define IBU_P1_CETUS_CH0_088_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_089_ADDR 0x01140059L
+#define IBU_P1_CETUS_CH0_089_STRIDE 1
+#define IBU_P1_CETUS_CH0_089_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_090_ADDR 0x0114005aL
+#define IBU_P1_CETUS_CH0_090_STRIDE 1
+#define IBU_P1_CETUS_CH0_090_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_091_ADDR 0x0114005bL
+#define IBU_P1_CETUS_CH0_091_STRIDE 1
+#define IBU_P1_CETUS_CH0_091_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_092_ADDR 0x0114005cL
+#define IBU_P1_CETUS_CH0_092_STRIDE 1
+#define IBU_P1_CETUS_CH0_092_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_093_ADDR 0x0114005dL
+#define IBU_P1_CETUS_CH0_093_STRIDE 1
+#define IBU_P1_CETUS_CH0_093_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_094_ADDR 0x0114005eL
+#define IBU_P1_CETUS_CH0_094_STRIDE 1
+#define IBU_P1_CETUS_CH0_094_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_095_ADDR 0x0114005fL
+#define IBU_P1_CETUS_CH0_095_STRIDE 1
+#define IBU_P1_CETUS_CH0_095_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_096_ADDR 0x01140060L
+#define IBU_P1_CETUS_CH0_096_STRIDE 1
+#define IBU_P1_CETUS_CH0_096_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_097_ADDR 0x01140061L
+#define IBU_P1_CETUS_CH0_097_STRIDE 1
+#define IBU_P1_CETUS_CH0_097_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_098_ADDR 0x01140062L
+#define IBU_P1_CETUS_CH0_098_STRIDE 1
+#define IBU_P1_CETUS_CH0_098_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_099_ADDR 0x01140063L
+#define IBU_P1_CETUS_CH0_099_STRIDE 1
+#define IBU_P1_CETUS_CH0_099_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_100_ADDR 0x01140064L
+#define IBU_P1_CETUS_CH0_100_STRIDE 1
+#define IBU_P1_CETUS_CH0_100_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_101_ADDR 0x01140065L
+#define IBU_P1_CETUS_CH0_101_STRIDE 1
+#define IBU_P1_CETUS_CH0_101_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_102_ADDR 0x01140066L
+#define IBU_P1_CETUS_CH0_102_STRIDE 1
+#define IBU_P1_CETUS_CH0_102_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_103_ADDR 0x01140067L
+#define IBU_P1_CETUS_CH0_103_STRIDE 1
+#define IBU_P1_CETUS_CH0_103_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_104_ADDR 0x01140068L
+#define IBU_P1_CETUS_CH0_104_STRIDE 1
+#define IBU_P1_CETUS_CH0_104_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_105_ADDR 0x01140069L
+#define IBU_P1_CETUS_CH0_105_STRIDE 1
+#define IBU_P1_CETUS_CH0_105_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_106_ADDR 0x0114006aL
+#define IBU_P1_CETUS_CH0_106_STRIDE 1
+#define IBU_P1_CETUS_CH0_106_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_107_ADDR 0x0114006bL
+#define IBU_P1_CETUS_CH0_107_STRIDE 1
+#define IBU_P1_CETUS_CH0_107_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_108_ADDR 0x0114006cL
+#define IBU_P1_CETUS_CH0_108_STRIDE 1
+#define IBU_P1_CETUS_CH0_108_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_109_ADDR 0x0114006dL
+#define IBU_P1_CETUS_CH0_109_STRIDE 1
+#define IBU_P1_CETUS_CH0_109_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_110_ADDR 0x0114006eL
+#define IBU_P1_CETUS_CH0_110_STRIDE 1
+#define IBU_P1_CETUS_CH0_110_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_111_ADDR 0x0114006fL
+#define IBU_P1_CETUS_CH0_111_STRIDE 1
+#define IBU_P1_CETUS_CH0_111_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_112_ADDR 0x01140070L
+#define IBU_P1_CETUS_CH0_112_STRIDE 1
+#define IBU_P1_CETUS_CH0_112_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_113_ADDR 0x01140071L
+#define IBU_P1_CETUS_CH0_113_STRIDE 1
+#define IBU_P1_CETUS_CH0_113_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_114_ADDR 0x01140072L
+#define IBU_P1_CETUS_CH0_114_STRIDE 1
+#define IBU_P1_CETUS_CH0_114_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_115_ADDR 0x01140073L
+#define IBU_P1_CETUS_CH0_115_STRIDE 1
+#define IBU_P1_CETUS_CH0_115_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_116_ADDR 0x01140074L
+#define IBU_P1_CETUS_CH0_116_STRIDE 1
+#define IBU_P1_CETUS_CH0_116_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_117_ADDR 0x01140075L
+#define IBU_P1_CETUS_CH0_117_STRIDE 1
+#define IBU_P1_CETUS_CH0_117_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_118_ADDR 0x01140076L
+#define IBU_P1_CETUS_CH0_118_STRIDE 1
+#define IBU_P1_CETUS_CH0_118_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_119_ADDR 0x01140077L
+#define IBU_P1_CETUS_CH0_119_STRIDE 1
+#define IBU_P1_CETUS_CH0_119_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_120_ADDR 0x01140078L
+#define IBU_P1_CETUS_CH0_120_STRIDE 1
+#define IBU_P1_CETUS_CH0_120_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_121_ADDR 0x01140079L
+#define IBU_P1_CETUS_CH0_121_STRIDE 1
+#define IBU_P1_CETUS_CH0_121_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_122_ADDR 0x0114007aL
+#define IBU_P1_CETUS_CH0_122_STRIDE 1
+#define IBU_P1_CETUS_CH0_122_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_123_ADDR 0x0114007bL
+#define IBU_P1_CETUS_CH0_123_STRIDE 1
+#define IBU_P1_CETUS_CH0_123_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_124_ADDR 0x0114007cL
+#define IBU_P1_CETUS_CH0_124_STRIDE 1
+#define IBU_P1_CETUS_CH0_124_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_125_ADDR 0x0114007dL
+#define IBU_P1_CETUS_CH0_125_STRIDE 1
+#define IBU_P1_CETUS_CH0_125_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_126_ADDR 0x0114007eL
+#define IBU_P1_CETUS_CH0_126_STRIDE 1
+#define IBU_P1_CETUS_CH0_126_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_127_ADDR 0x0114007fL
+#define IBU_P1_CETUS_CH0_127_STRIDE 1
+#define IBU_P1_CETUS_CH0_127_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_128_ADDR 0x01140080L
+#define IBU_P1_CETUS_CH0_128_STRIDE 1
+#define IBU_P1_CETUS_CH0_128_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_129_ADDR 0x01140081L
+#define IBU_P1_CETUS_CH0_129_STRIDE 1
+#define IBU_P1_CETUS_CH0_129_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_130_ADDR 0x01140082L
+#define IBU_P1_CETUS_CH0_130_STRIDE 1
+#define IBU_P1_CETUS_CH0_130_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_131_ADDR 0x01140083L
+#define IBU_P1_CETUS_CH0_131_STRIDE 1
+#define IBU_P1_CETUS_CH0_131_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_132_ADDR 0x01140084L
+#define IBU_P1_CETUS_CH0_132_STRIDE 1
+#define IBU_P1_CETUS_CH0_132_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_133_ADDR 0x01140085L
+#define IBU_P1_CETUS_CH0_133_STRIDE 1
+#define IBU_P1_CETUS_CH0_133_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_134_ADDR 0x01140086L
+#define IBU_P1_CETUS_CH0_134_STRIDE 1
+#define IBU_P1_CETUS_CH0_134_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_135_ADDR 0x01140087L
+#define IBU_P1_CETUS_CH0_135_STRIDE 1
+#define IBU_P1_CETUS_CH0_135_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_136_ADDR 0x01140088L
+#define IBU_P1_CETUS_CH0_136_STRIDE 1
+#define IBU_P1_CETUS_CH0_136_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_137_ADDR 0x01140089L
+#define IBU_P1_CETUS_CH0_137_STRIDE 1
+#define IBU_P1_CETUS_CH0_137_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_138_ADDR 0x0114008aL
+#define IBU_P1_CETUS_CH0_138_STRIDE 1
+#define IBU_P1_CETUS_CH0_138_DEPTH 1
+
+#define IBU_P1_CETUS_CH0_139_ADDR 0x0114008bL
+#define IBU_P1_CETUS_CH0_139_STRIDE 1
+#define IBU_P1_CETUS_CH0_139_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH1_000_ADDR 0x01140100L
+#define IBU_P1_CETUS_CH1_000_STRIDE 1
+#define IBU_P1_CETUS_CH1_000_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH1_001_ADDR 0x01140101L
+#define IBU_P1_CETUS_CH1_001_STRIDE 1
+#define IBU_P1_CETUS_CH1_001_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH1_002_ADDR 0x01140102L
+#define IBU_P1_CETUS_CH1_002_STRIDE 1
+#define IBU_P1_CETUS_CH1_002_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_003_ADDR 0x01140103L
+#define IBU_P1_CETUS_CH1_003_STRIDE 1
+#define IBU_P1_CETUS_CH1_003_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_004_ADDR 0x01140104L
+#define IBU_P1_CETUS_CH1_004_STRIDE 1
+#define IBU_P1_CETUS_CH1_004_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_005_ADDR 0x01140105L
+#define IBU_P1_CETUS_CH1_005_STRIDE 1
+#define IBU_P1_CETUS_CH1_005_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_006_ADDR 0x01140106L
+#define IBU_P1_CETUS_CH1_006_STRIDE 1
+#define IBU_P1_CETUS_CH1_006_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_007_ADDR 0x01140107L
+#define IBU_P1_CETUS_CH1_007_STRIDE 1
+#define IBU_P1_CETUS_CH1_007_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_008_ADDR 0x01140108L
+#define IBU_P1_CETUS_CH1_008_STRIDE 1
+#define IBU_P1_CETUS_CH1_008_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_009_ADDR 0x01140109L
+#define IBU_P1_CETUS_CH1_009_STRIDE 1
+#define IBU_P1_CETUS_CH1_009_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_010_ADDR 0x0114010aL
+#define IBU_P1_CETUS_CH1_010_STRIDE 1
+#define IBU_P1_CETUS_CH1_010_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_011_ADDR 0x0114010bL
+#define IBU_P1_CETUS_CH1_011_STRIDE 1
+#define IBU_P1_CETUS_CH1_011_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_012_ADDR 0x0114010cL
+#define IBU_P1_CETUS_CH1_012_STRIDE 1
+#define IBU_P1_CETUS_CH1_012_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_013_ADDR 0x0114010dL
+#define IBU_P1_CETUS_CH1_013_STRIDE 1
+#define IBU_P1_CETUS_CH1_013_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_014_ADDR 0x0114010eL
+#define IBU_P1_CETUS_CH1_014_STRIDE 1
+#define IBU_P1_CETUS_CH1_014_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_015_ADDR 0x0114010fL
+#define IBU_P1_CETUS_CH1_015_STRIDE 1
+#define IBU_P1_CETUS_CH1_015_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_016_ADDR 0x01140110L
+#define IBU_P1_CETUS_CH1_016_STRIDE 1
+#define IBU_P1_CETUS_CH1_016_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_017_ADDR 0x01140111L
+#define IBU_P1_CETUS_CH1_017_STRIDE 1
+#define IBU_P1_CETUS_CH1_017_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_018_ADDR 0x01140112L
+#define IBU_P1_CETUS_CH1_018_STRIDE 1
+#define IBU_P1_CETUS_CH1_018_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_019_ADDR 0x01140113L
+#define IBU_P1_CETUS_CH1_019_STRIDE 1
+#define IBU_P1_CETUS_CH1_019_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_020_ADDR 0x01140114L
+#define IBU_P1_CETUS_CH1_020_STRIDE 1
+#define IBU_P1_CETUS_CH1_020_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_021_ADDR 0x01140115L
+#define IBU_P1_CETUS_CH1_021_STRIDE 1
+#define IBU_P1_CETUS_CH1_021_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_022_ADDR 0x01140116L
+#define IBU_P1_CETUS_CH1_022_STRIDE 1
+#define IBU_P1_CETUS_CH1_022_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_023_ADDR 0x01140117L
+#define IBU_P1_CETUS_CH1_023_STRIDE 1
+#define IBU_P1_CETUS_CH1_023_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_024_ADDR 0x01140118L
+#define IBU_P1_CETUS_CH1_024_STRIDE 1
+#define IBU_P1_CETUS_CH1_024_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_025_ADDR 0x01140119L
+#define IBU_P1_CETUS_CH1_025_STRIDE 1
+#define IBU_P1_CETUS_CH1_025_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_026_ADDR 0x0114011aL
+#define IBU_P1_CETUS_CH1_026_STRIDE 1
+#define IBU_P1_CETUS_CH1_026_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_027_ADDR 0x0114011bL
+#define IBU_P1_CETUS_CH1_027_STRIDE 1
+#define IBU_P1_CETUS_CH1_027_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_028_ADDR 0x0114011cL
+#define IBU_P1_CETUS_CH1_028_STRIDE 1
+#define IBU_P1_CETUS_CH1_028_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_029_ADDR 0x0114011dL
+#define IBU_P1_CETUS_CH1_029_STRIDE 1
+#define IBU_P1_CETUS_CH1_029_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_030_ADDR 0x0114011eL
+#define IBU_P1_CETUS_CH1_030_STRIDE 1
+#define IBU_P1_CETUS_CH1_030_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_031_ADDR 0x0114011fL
+#define IBU_P1_CETUS_CH1_031_STRIDE 1
+#define IBU_P1_CETUS_CH1_031_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_032_ADDR 0x01140120L
+#define IBU_P1_CETUS_CH1_032_STRIDE 1
+#define IBU_P1_CETUS_CH1_032_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_033_ADDR 0x01140121L
+#define IBU_P1_CETUS_CH1_033_STRIDE 1
+#define IBU_P1_CETUS_CH1_033_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_034_ADDR 0x01140122L
+#define IBU_P1_CETUS_CH1_034_STRIDE 1
+#define IBU_P1_CETUS_CH1_034_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_035_ADDR 0x01140123L
+#define IBU_P1_CETUS_CH1_035_STRIDE 1
+#define IBU_P1_CETUS_CH1_035_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_036_ADDR 0x01140124L
+#define IBU_P1_CETUS_CH1_036_STRIDE 1
+#define IBU_P1_CETUS_CH1_036_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_037_ADDR 0x01140125L
+#define IBU_P1_CETUS_CH1_037_STRIDE 1
+#define IBU_P1_CETUS_CH1_037_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_038_ADDR 0x01140126L
+#define IBU_P1_CETUS_CH1_038_STRIDE 1
+#define IBU_P1_CETUS_CH1_038_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_039_ADDR 0x01140127L
+#define IBU_P1_CETUS_CH1_039_STRIDE 1
+#define IBU_P1_CETUS_CH1_039_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_040_ADDR 0x01140128L
+#define IBU_P1_CETUS_CH1_040_STRIDE 1
+#define IBU_P1_CETUS_CH1_040_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_041_ADDR 0x01140129L
+#define IBU_P1_CETUS_CH1_041_STRIDE 1
+#define IBU_P1_CETUS_CH1_041_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_042_ADDR 0x0114012aL
+#define IBU_P1_CETUS_CH1_042_STRIDE 1
+#define IBU_P1_CETUS_CH1_042_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_043_ADDR 0x0114012bL
+#define IBU_P1_CETUS_CH1_043_STRIDE 1
+#define IBU_P1_CETUS_CH1_043_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_044_ADDR 0x0114012cL
+#define IBU_P1_CETUS_CH1_044_STRIDE 1
+#define IBU_P1_CETUS_CH1_044_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_045_ADDR 0x0114012dL
+#define IBU_P1_CETUS_CH1_045_STRIDE 1
+#define IBU_P1_CETUS_CH1_045_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_046_ADDR 0x0114012eL
+#define IBU_P1_CETUS_CH1_046_STRIDE 1
+#define IBU_P1_CETUS_CH1_046_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_047_ADDR 0x0114012fL
+#define IBU_P1_CETUS_CH1_047_STRIDE 1
+#define IBU_P1_CETUS_CH1_047_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_048_ADDR 0x01140130L
+#define IBU_P1_CETUS_CH1_048_STRIDE 1
+#define IBU_P1_CETUS_CH1_048_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_049_ADDR 0x01140131L
+#define IBU_P1_CETUS_CH1_049_STRIDE 1
+#define IBU_P1_CETUS_CH1_049_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_050_ADDR 0x01140132L
+#define IBU_P1_CETUS_CH1_050_STRIDE 1
+#define IBU_P1_CETUS_CH1_050_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_051_ADDR 0x01140133L
+#define IBU_P1_CETUS_CH1_051_STRIDE 1
+#define IBU_P1_CETUS_CH1_051_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_052_ADDR 0x01140134L
+#define IBU_P1_CETUS_CH1_052_STRIDE 1
+#define IBU_P1_CETUS_CH1_052_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_053_ADDR 0x01140135L
+#define IBU_P1_CETUS_CH1_053_STRIDE 1
+#define IBU_P1_CETUS_CH1_053_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_054_ADDR 0x01140136L
+#define IBU_P1_CETUS_CH1_054_STRIDE 1
+#define IBU_P1_CETUS_CH1_054_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_055_ADDR 0x01140137L
+#define IBU_P1_CETUS_CH1_055_STRIDE 1
+#define IBU_P1_CETUS_CH1_055_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_056_ADDR 0x01140138L
+#define IBU_P1_CETUS_CH1_056_STRIDE 1
+#define IBU_P1_CETUS_CH1_056_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_057_ADDR 0x01140139L
+#define IBU_P1_CETUS_CH1_057_STRIDE 1
+#define IBU_P1_CETUS_CH1_057_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_058_ADDR 0x0114013aL
+#define IBU_P1_CETUS_CH1_058_STRIDE 1
+#define IBU_P1_CETUS_CH1_058_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_059_ADDR 0x0114013bL
+#define IBU_P1_CETUS_CH1_059_STRIDE 1
+#define IBU_P1_CETUS_CH1_059_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_060_ADDR 0x0114013cL
+#define IBU_P1_CETUS_CH1_060_STRIDE 1
+#define IBU_P1_CETUS_CH1_060_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_061_ADDR 0x0114013dL
+#define IBU_P1_CETUS_CH1_061_STRIDE 1
+#define IBU_P1_CETUS_CH1_061_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_062_ADDR 0x0114013eL
+#define IBU_P1_CETUS_CH1_062_STRIDE 1
+#define IBU_P1_CETUS_CH1_062_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_063_ADDR 0x0114013fL
+#define IBU_P1_CETUS_CH1_063_STRIDE 1
+#define IBU_P1_CETUS_CH1_063_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_064_ADDR 0x01140140L
+#define IBU_P1_CETUS_CH1_064_STRIDE 1
+#define IBU_P1_CETUS_CH1_064_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_065_ADDR 0x01140141L
+#define IBU_P1_CETUS_CH1_065_STRIDE 1
+#define IBU_P1_CETUS_CH1_065_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_066_ADDR 0x01140142L
+#define IBU_P1_CETUS_CH1_066_STRIDE 1
+#define IBU_P1_CETUS_CH1_066_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_067_ADDR 0x01140143L
+#define IBU_P1_CETUS_CH1_067_STRIDE 1
+#define IBU_P1_CETUS_CH1_067_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_068_ADDR 0x01140144L
+#define IBU_P1_CETUS_CH1_068_STRIDE 1
+#define IBU_P1_CETUS_CH1_068_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_069_ADDR 0x01140145L
+#define IBU_P1_CETUS_CH1_069_STRIDE 1
+#define IBU_P1_CETUS_CH1_069_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_070_ADDR 0x01140146L
+#define IBU_P1_CETUS_CH1_070_STRIDE 1
+#define IBU_P1_CETUS_CH1_070_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_071_ADDR 0x01140147L
+#define IBU_P1_CETUS_CH1_071_STRIDE 1
+#define IBU_P1_CETUS_CH1_071_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_072_ADDR 0x01140148L
+#define IBU_P1_CETUS_CH1_072_STRIDE 1
+#define IBU_P1_CETUS_CH1_072_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_073_ADDR 0x01140149L
+#define IBU_P1_CETUS_CH1_073_STRIDE 1
+#define IBU_P1_CETUS_CH1_073_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_074_ADDR 0x0114014aL
+#define IBU_P1_CETUS_CH1_074_STRIDE 1
+#define IBU_P1_CETUS_CH1_074_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_075_ADDR 0x0114014bL
+#define IBU_P1_CETUS_CH1_075_STRIDE 1
+#define IBU_P1_CETUS_CH1_075_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_076_ADDR 0x0114014cL
+#define IBU_P1_CETUS_CH1_076_STRIDE 1
+#define IBU_P1_CETUS_CH1_076_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_077_ADDR 0x0114014dL
+#define IBU_P1_CETUS_CH1_077_STRIDE 1
+#define IBU_P1_CETUS_CH1_077_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_078_ADDR 0x0114014eL
+#define IBU_P1_CETUS_CH1_078_STRIDE 1
+#define IBU_P1_CETUS_CH1_078_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_079_ADDR 0x0114014fL
+#define IBU_P1_CETUS_CH1_079_STRIDE 1
+#define IBU_P1_CETUS_CH1_079_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_080_ADDR 0x01140150L
+#define IBU_P1_CETUS_CH1_080_STRIDE 1
+#define IBU_P1_CETUS_CH1_080_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_081_ADDR 0x01140151L
+#define IBU_P1_CETUS_CH1_081_STRIDE 1
+#define IBU_P1_CETUS_CH1_081_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_082_ADDR 0x01140152L
+#define IBU_P1_CETUS_CH1_082_STRIDE 1
+#define IBU_P1_CETUS_CH1_082_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_083_ADDR 0x01140153L
+#define IBU_P1_CETUS_CH1_083_STRIDE 1
+#define IBU_P1_CETUS_CH1_083_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_084_ADDR 0x01140154L
+#define IBU_P1_CETUS_CH1_084_STRIDE 1
+#define IBU_P1_CETUS_CH1_084_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_085_ADDR 0x01140155L
+#define IBU_P1_CETUS_CH1_085_STRIDE 1
+#define IBU_P1_CETUS_CH1_085_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_086_ADDR 0x01140156L
+#define IBU_P1_CETUS_CH1_086_STRIDE 1
+#define IBU_P1_CETUS_CH1_086_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_087_ADDR 0x01140157L
+#define IBU_P1_CETUS_CH1_087_STRIDE 1
+#define IBU_P1_CETUS_CH1_087_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_088_ADDR 0x01140158L
+#define IBU_P1_CETUS_CH1_088_STRIDE 1
+#define IBU_P1_CETUS_CH1_088_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_089_ADDR 0x01140159L
+#define IBU_P1_CETUS_CH1_089_STRIDE 1
+#define IBU_P1_CETUS_CH1_089_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_090_ADDR 0x0114015aL
+#define IBU_P1_CETUS_CH1_090_STRIDE 1
+#define IBU_P1_CETUS_CH1_090_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_091_ADDR 0x0114015bL
+#define IBU_P1_CETUS_CH1_091_STRIDE 1
+#define IBU_P1_CETUS_CH1_091_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_092_ADDR 0x0114015cL
+#define IBU_P1_CETUS_CH1_092_STRIDE 1
+#define IBU_P1_CETUS_CH1_092_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_093_ADDR 0x0114015dL
+#define IBU_P1_CETUS_CH1_093_STRIDE 1
+#define IBU_P1_CETUS_CH1_093_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_094_ADDR 0x0114015eL
+#define IBU_P1_CETUS_CH1_094_STRIDE 1
+#define IBU_P1_CETUS_CH1_094_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_095_ADDR 0x0114015fL
+#define IBU_P1_CETUS_CH1_095_STRIDE 1
+#define IBU_P1_CETUS_CH1_095_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_096_ADDR 0x01140160L
+#define IBU_P1_CETUS_CH1_096_STRIDE 1
+#define IBU_P1_CETUS_CH1_096_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_097_ADDR 0x01140161L
+#define IBU_P1_CETUS_CH1_097_STRIDE 1
+#define IBU_P1_CETUS_CH1_097_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_098_ADDR 0x01140162L
+#define IBU_P1_CETUS_CH1_098_STRIDE 1
+#define IBU_P1_CETUS_CH1_098_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_099_ADDR 0x01140163L
+#define IBU_P1_CETUS_CH1_099_STRIDE 1
+#define IBU_P1_CETUS_CH1_099_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_100_ADDR 0x01140164L
+#define IBU_P1_CETUS_CH1_100_STRIDE 1
+#define IBU_P1_CETUS_CH1_100_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_101_ADDR 0x01140165L
+#define IBU_P1_CETUS_CH1_101_STRIDE 1
+#define IBU_P1_CETUS_CH1_101_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_102_ADDR 0x01140166L
+#define IBU_P1_CETUS_CH1_102_STRIDE 1
+#define IBU_P1_CETUS_CH1_102_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_103_ADDR 0x01140167L
+#define IBU_P1_CETUS_CH1_103_STRIDE 1
+#define IBU_P1_CETUS_CH1_103_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_104_ADDR 0x01140168L
+#define IBU_P1_CETUS_CH1_104_STRIDE 1
+#define IBU_P1_CETUS_CH1_104_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_105_ADDR 0x01140169L
+#define IBU_P1_CETUS_CH1_105_STRIDE 1
+#define IBU_P1_CETUS_CH1_105_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_106_ADDR 0x0114016aL
+#define IBU_P1_CETUS_CH1_106_STRIDE 1
+#define IBU_P1_CETUS_CH1_106_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_107_ADDR 0x0114016bL
+#define IBU_P1_CETUS_CH1_107_STRIDE 1
+#define IBU_P1_CETUS_CH1_107_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_108_ADDR 0x0114016cL
+#define IBU_P1_CETUS_CH1_108_STRIDE 1
+#define IBU_P1_CETUS_CH1_108_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_109_ADDR 0x0114016dL
+#define IBU_P1_CETUS_CH1_109_STRIDE 1
+#define IBU_P1_CETUS_CH1_109_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_110_ADDR 0x0114016eL
+#define IBU_P1_CETUS_CH1_110_STRIDE 1
+#define IBU_P1_CETUS_CH1_110_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_111_ADDR 0x0114016fL
+#define IBU_P1_CETUS_CH1_111_STRIDE 1
+#define IBU_P1_CETUS_CH1_111_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_112_ADDR 0x01140170L
+#define IBU_P1_CETUS_CH1_112_STRIDE 1
+#define IBU_P1_CETUS_CH1_112_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_113_ADDR 0x01140171L
+#define IBU_P1_CETUS_CH1_113_STRIDE 1
+#define IBU_P1_CETUS_CH1_113_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_114_ADDR 0x01140172L
+#define IBU_P1_CETUS_CH1_114_STRIDE 1
+#define IBU_P1_CETUS_CH1_114_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_115_ADDR 0x01140173L
+#define IBU_P1_CETUS_CH1_115_STRIDE 1
+#define IBU_P1_CETUS_CH1_115_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_116_ADDR 0x01140174L
+#define IBU_P1_CETUS_CH1_116_STRIDE 1
+#define IBU_P1_CETUS_CH1_116_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_117_ADDR 0x01140175L
+#define IBU_P1_CETUS_CH1_117_STRIDE 1
+#define IBU_P1_CETUS_CH1_117_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_118_ADDR 0x01140176L
+#define IBU_P1_CETUS_CH1_118_STRIDE 1
+#define IBU_P1_CETUS_CH1_118_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_119_ADDR 0x01140177L
+#define IBU_P1_CETUS_CH1_119_STRIDE 1
+#define IBU_P1_CETUS_CH1_119_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_120_ADDR 0x01140178L
+#define IBU_P1_CETUS_CH1_120_STRIDE 1
+#define IBU_P1_CETUS_CH1_120_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_121_ADDR 0x01140179L
+#define IBU_P1_CETUS_CH1_121_STRIDE 1
+#define IBU_P1_CETUS_CH1_121_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_122_ADDR 0x0114017aL
+#define IBU_P1_CETUS_CH1_122_STRIDE 1
+#define IBU_P1_CETUS_CH1_122_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_123_ADDR 0x0114017bL
+#define IBU_P1_CETUS_CH1_123_STRIDE 1
+#define IBU_P1_CETUS_CH1_123_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_124_ADDR 0x0114017cL
+#define IBU_P1_CETUS_CH1_124_STRIDE 1
+#define IBU_P1_CETUS_CH1_124_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_125_ADDR 0x0114017dL
+#define IBU_P1_CETUS_CH1_125_STRIDE 1
+#define IBU_P1_CETUS_CH1_125_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_126_ADDR 0x0114017eL
+#define IBU_P1_CETUS_CH1_126_STRIDE 1
+#define IBU_P1_CETUS_CH1_126_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_127_ADDR 0x0114017fL
+#define IBU_P1_CETUS_CH1_127_STRIDE 1
+#define IBU_P1_CETUS_CH1_127_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_128_ADDR 0x01140180L
+#define IBU_P1_CETUS_CH1_128_STRIDE 1
+#define IBU_P1_CETUS_CH1_128_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_129_ADDR 0x01140181L
+#define IBU_P1_CETUS_CH1_129_STRIDE 1
+#define IBU_P1_CETUS_CH1_129_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_130_ADDR 0x01140182L
+#define IBU_P1_CETUS_CH1_130_STRIDE 1
+#define IBU_P1_CETUS_CH1_130_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_131_ADDR 0x01140183L
+#define IBU_P1_CETUS_CH1_131_STRIDE 1
+#define IBU_P1_CETUS_CH1_131_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_132_ADDR 0x01140184L
+#define IBU_P1_CETUS_CH1_132_STRIDE 1
+#define IBU_P1_CETUS_CH1_132_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_133_ADDR 0x01140185L
+#define IBU_P1_CETUS_CH1_133_STRIDE 1
+#define IBU_P1_CETUS_CH1_133_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_134_ADDR 0x01140186L
+#define IBU_P1_CETUS_CH1_134_STRIDE 1
+#define IBU_P1_CETUS_CH1_134_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_135_ADDR 0x01140187L
+#define IBU_P1_CETUS_CH1_135_STRIDE 1
+#define IBU_P1_CETUS_CH1_135_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_136_ADDR 0x01140188L
+#define IBU_P1_CETUS_CH1_136_STRIDE 1
+#define IBU_P1_CETUS_CH1_136_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_137_ADDR 0x01140189L
+#define IBU_P1_CETUS_CH1_137_STRIDE 1
+#define IBU_P1_CETUS_CH1_137_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_138_ADDR 0x0114018aL
+#define IBU_P1_CETUS_CH1_138_STRIDE 1
+#define IBU_P1_CETUS_CH1_138_DEPTH 1
+
+#define IBU_P1_CETUS_CH1_139_ADDR 0x0114018bL
+#define IBU_P1_CETUS_CH1_139_STRIDE 1
+#define IBU_P1_CETUS_CH1_139_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_CONTROL0_ADDR 0x01140200L
+#define IBU_P1_CETUS_PLLA_CONTROL0_STRIDE 1
+#define IBU_P1_CETUS_PLLA_CONTROL0_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_CONTROL1_ADDR 0x01140201L
+#define IBU_P1_CETUS_PLLA_CONTROL1_STRIDE 1
+#define IBU_P1_CETUS_PLLA_CONTROL1_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_CONTROL2_ADDR 0x01140202L
+#define IBU_P1_CETUS_PLLA_CONTROL2_STRIDE 1
+#define IBU_P1_CETUS_PLLA_CONTROL2_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_EXTFB_CNTR_ADDR 0x01140203L
+#define IBU_P1_CETUS_PLLA_EXTFB_CNTR_STRIDE 1
+#define IBU_P1_CETUS_PLLA_EXTFB_CNTR_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_FBCNT_ATO_ADDR 0x01140204L
+#define IBU_P1_CETUS_PLLA_FBCNT_ATO_STRIDE 1
+#define IBU_P1_CETUS_PLLA_FBCNT_ATO_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_SPARE_USRCNTR_ADDR 0x01140205L
+#define IBU_P1_CETUS_PLLA_SPARE_USRCNTR_STRIDE 1
+#define IBU_P1_CETUS_PLLA_SPARE_USRCNTR_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_DIV_EN_ADDR 0x01140206L
+#define IBU_P1_CETUS_PLLA_DIV_EN_STRIDE 1
+#define IBU_P1_CETUS_PLLA_DIV_EN_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_VCO_WAIT_CNT_ADDR 0x01140207L
+#define IBU_P1_CETUS_PLLA_VCO_WAIT_CNT_STRIDE 1
+#define IBU_P1_CETUS_PLLA_VCO_WAIT_CNT_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_STATUS0_ADDR 0x01140208L
+#define IBU_P1_CETUS_PLLA_STATUS0_STRIDE 1
+#define IBU_P1_CETUS_PLLA_STATUS0_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_STATUS1_ADDR 0x01140209L
+#define IBU_P1_CETUS_PLLA_STATUS1_STRIDE 1
+#define IBU_P1_CETUS_PLLA_STATUS1_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_010_ADDR 0x0114020aL
+#define IBU_P1_CETUS_PLLA_010_STRIDE 1
+#define IBU_P1_CETUS_PLLA_010_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_011_ADDR 0x0114020bL
+#define IBU_P1_CETUS_PLLA_011_STRIDE 1
+#define IBU_P1_CETUS_PLLA_011_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_012_ADDR 0x0114020cL
+#define IBU_P1_CETUS_PLLA_012_STRIDE 1
+#define IBU_P1_CETUS_PLLA_012_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_013_ADDR 0x0114020dL
+#define IBU_P1_CETUS_PLLA_013_STRIDE 1
+#define IBU_P1_CETUS_PLLA_013_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_014_ADDR 0x0114020eL
+#define IBU_P1_CETUS_PLLA_014_STRIDE 1
+#define IBU_P1_CETUS_PLLA_014_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_015_ADDR 0x0114020fL
+#define IBU_P1_CETUS_PLLA_015_STRIDE 1
+#define IBU_P1_CETUS_PLLA_015_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_016_ADDR 0x01140210L
+#define IBU_P1_CETUS_PLLA_016_STRIDE 1
+#define IBU_P1_CETUS_PLLA_016_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_017_ADDR 0x01140211L
+#define IBU_P1_CETUS_PLLA_017_STRIDE 1
+#define IBU_P1_CETUS_PLLA_017_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_018_ADDR 0x01140212L
+#define IBU_P1_CETUS_PLLA_018_STRIDE 1
+#define IBU_P1_CETUS_PLLA_018_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_019_ADDR 0x01140213L
+#define IBU_P1_CETUS_PLLA_019_STRIDE 1
+#define IBU_P1_CETUS_PLLA_019_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_020_ADDR 0x01140214L
+#define IBU_P1_CETUS_PLLA_020_STRIDE 1
+#define IBU_P1_CETUS_PLLA_020_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_021_ADDR 0x01140215L
+#define IBU_P1_CETUS_PLLA_021_STRIDE 1
+#define IBU_P1_CETUS_PLLA_021_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_022_ADDR 0x01140216L
+#define IBU_P1_CETUS_PLLA_022_STRIDE 1
+#define IBU_P1_CETUS_PLLA_022_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_023_ADDR 0x01140217L
+#define IBU_P1_CETUS_PLLA_023_STRIDE 1
+#define IBU_P1_CETUS_PLLA_023_DEPTH 1
+
+#define IBU_P1_CETUS_PLLA_024_ADDR 0x01140218L
+#define IBU_P1_CETUS_PLLA_024_STRIDE 1
+#define IBU_P1_CETUS_PLLA_024_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH2_000_ADDR 0x01140300L
+#define IBU_P1_CETUS_CH2_000_STRIDE 1
+#define IBU_P1_CETUS_CH2_000_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH2_001_ADDR 0x01140301L
+#define IBU_P1_CETUS_CH2_001_STRIDE 1
+#define IBU_P1_CETUS_CH2_001_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH2_002_ADDR 0x01140302L
+#define IBU_P1_CETUS_CH2_002_STRIDE 1
+#define IBU_P1_CETUS_CH2_002_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_003_ADDR 0x01140303L
+#define IBU_P1_CETUS_CH2_003_STRIDE 1
+#define IBU_P1_CETUS_CH2_003_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_004_ADDR 0x01140304L
+#define IBU_P1_CETUS_CH2_004_STRIDE 1
+#define IBU_P1_CETUS_CH2_004_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_005_ADDR 0x01140305L
+#define IBU_P1_CETUS_CH2_005_STRIDE 1
+#define IBU_P1_CETUS_CH2_005_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_006_ADDR 0x01140306L
+#define IBU_P1_CETUS_CH2_006_STRIDE 1
+#define IBU_P1_CETUS_CH2_006_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_007_ADDR 0x01140307L
+#define IBU_P1_CETUS_CH2_007_STRIDE 1
+#define IBU_P1_CETUS_CH2_007_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_008_ADDR 0x01140308L
+#define IBU_P1_CETUS_CH2_008_STRIDE 1
+#define IBU_P1_CETUS_CH2_008_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_009_ADDR 0x01140309L
+#define IBU_P1_CETUS_CH2_009_STRIDE 1
+#define IBU_P1_CETUS_CH2_009_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_010_ADDR 0x0114030aL
+#define IBU_P1_CETUS_CH2_010_STRIDE 1
+#define IBU_P1_CETUS_CH2_010_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_011_ADDR 0x0114030bL
+#define IBU_P1_CETUS_CH2_011_STRIDE 1
+#define IBU_P1_CETUS_CH2_011_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_012_ADDR 0x0114030cL
+#define IBU_P1_CETUS_CH2_012_STRIDE 1
+#define IBU_P1_CETUS_CH2_012_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_013_ADDR 0x0114030dL
+#define IBU_P1_CETUS_CH2_013_STRIDE 1
+#define IBU_P1_CETUS_CH2_013_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_014_ADDR 0x0114030eL
+#define IBU_P1_CETUS_CH2_014_STRIDE 1
+#define IBU_P1_CETUS_CH2_014_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_015_ADDR 0x0114030fL
+#define IBU_P1_CETUS_CH2_015_STRIDE 1
+#define IBU_P1_CETUS_CH2_015_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_016_ADDR 0x01140310L
+#define IBU_P1_CETUS_CH2_016_STRIDE 1
+#define IBU_P1_CETUS_CH2_016_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_017_ADDR 0x01140311L
+#define IBU_P1_CETUS_CH2_017_STRIDE 1
+#define IBU_P1_CETUS_CH2_017_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_018_ADDR 0x01140312L
+#define IBU_P1_CETUS_CH2_018_STRIDE 1
+#define IBU_P1_CETUS_CH2_018_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_019_ADDR 0x01140313L
+#define IBU_P1_CETUS_CH2_019_STRIDE 1
+#define IBU_P1_CETUS_CH2_019_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_020_ADDR 0x01140314L
+#define IBU_P1_CETUS_CH2_020_STRIDE 1
+#define IBU_P1_CETUS_CH2_020_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_021_ADDR 0x01140315L
+#define IBU_P1_CETUS_CH2_021_STRIDE 1
+#define IBU_P1_CETUS_CH2_021_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_022_ADDR 0x01140316L
+#define IBU_P1_CETUS_CH2_022_STRIDE 1
+#define IBU_P1_CETUS_CH2_022_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_023_ADDR 0x01140317L
+#define IBU_P1_CETUS_CH2_023_STRIDE 1
+#define IBU_P1_CETUS_CH2_023_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_024_ADDR 0x01140318L
+#define IBU_P1_CETUS_CH2_024_STRIDE 1
+#define IBU_P1_CETUS_CH2_024_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_025_ADDR 0x01140319L
+#define IBU_P1_CETUS_CH2_025_STRIDE 1
+#define IBU_P1_CETUS_CH2_025_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_026_ADDR 0x0114031aL
+#define IBU_P1_CETUS_CH2_026_STRIDE 1
+#define IBU_P1_CETUS_CH2_026_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_027_ADDR 0x0114031bL
+#define IBU_P1_CETUS_CH2_027_STRIDE 1
+#define IBU_P1_CETUS_CH2_027_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_028_ADDR 0x0114031cL
+#define IBU_P1_CETUS_CH2_028_STRIDE 1
+#define IBU_P1_CETUS_CH2_028_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_029_ADDR 0x0114031dL
+#define IBU_P1_CETUS_CH2_029_STRIDE 1
+#define IBU_P1_CETUS_CH2_029_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_030_ADDR 0x0114031eL
+#define IBU_P1_CETUS_CH2_030_STRIDE 1
+#define IBU_P1_CETUS_CH2_030_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_031_ADDR 0x0114031fL
+#define IBU_P1_CETUS_CH2_031_STRIDE 1
+#define IBU_P1_CETUS_CH2_031_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_032_ADDR 0x01140320L
+#define IBU_P1_CETUS_CH2_032_STRIDE 1
+#define IBU_P1_CETUS_CH2_032_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_033_ADDR 0x01140321L
+#define IBU_P1_CETUS_CH2_033_STRIDE 1
+#define IBU_P1_CETUS_CH2_033_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_034_ADDR 0x01140322L
+#define IBU_P1_CETUS_CH2_034_STRIDE 1
+#define IBU_P1_CETUS_CH2_034_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_035_ADDR 0x01140323L
+#define IBU_P1_CETUS_CH2_035_STRIDE 1
+#define IBU_P1_CETUS_CH2_035_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_036_ADDR 0x01140324L
+#define IBU_P1_CETUS_CH2_036_STRIDE 1
+#define IBU_P1_CETUS_CH2_036_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_037_ADDR 0x01140325L
+#define IBU_P1_CETUS_CH2_037_STRIDE 1
+#define IBU_P1_CETUS_CH2_037_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_038_ADDR 0x01140326L
+#define IBU_P1_CETUS_CH2_038_STRIDE 1
+#define IBU_P1_CETUS_CH2_038_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_039_ADDR 0x01140327L
+#define IBU_P1_CETUS_CH2_039_STRIDE 1
+#define IBU_P1_CETUS_CH2_039_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_040_ADDR 0x01140328L
+#define IBU_P1_CETUS_CH2_040_STRIDE 1
+#define IBU_P1_CETUS_CH2_040_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_041_ADDR 0x01140329L
+#define IBU_P1_CETUS_CH2_041_STRIDE 1
+#define IBU_P1_CETUS_CH2_041_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_042_ADDR 0x0114032aL
+#define IBU_P1_CETUS_CH2_042_STRIDE 1
+#define IBU_P1_CETUS_CH2_042_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_043_ADDR 0x0114032bL
+#define IBU_P1_CETUS_CH2_043_STRIDE 1
+#define IBU_P1_CETUS_CH2_043_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_044_ADDR 0x0114032cL
+#define IBU_P1_CETUS_CH2_044_STRIDE 1
+#define IBU_P1_CETUS_CH2_044_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_045_ADDR 0x0114032dL
+#define IBU_P1_CETUS_CH2_045_STRIDE 1
+#define IBU_P1_CETUS_CH2_045_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_046_ADDR 0x0114032eL
+#define IBU_P1_CETUS_CH2_046_STRIDE 1
+#define IBU_P1_CETUS_CH2_046_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_047_ADDR 0x0114032fL
+#define IBU_P1_CETUS_CH2_047_STRIDE 1
+#define IBU_P1_CETUS_CH2_047_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_048_ADDR 0x01140330L
+#define IBU_P1_CETUS_CH2_048_STRIDE 1
+#define IBU_P1_CETUS_CH2_048_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_049_ADDR 0x01140331L
+#define IBU_P1_CETUS_CH2_049_STRIDE 1
+#define IBU_P1_CETUS_CH2_049_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_050_ADDR 0x01140332L
+#define IBU_P1_CETUS_CH2_050_STRIDE 1
+#define IBU_P1_CETUS_CH2_050_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_051_ADDR 0x01140333L
+#define IBU_P1_CETUS_CH2_051_STRIDE 1
+#define IBU_P1_CETUS_CH2_051_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_052_ADDR 0x01140334L
+#define IBU_P1_CETUS_CH2_052_STRIDE 1
+#define IBU_P1_CETUS_CH2_052_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_053_ADDR 0x01140335L
+#define IBU_P1_CETUS_CH2_053_STRIDE 1
+#define IBU_P1_CETUS_CH2_053_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_054_ADDR 0x01140336L
+#define IBU_P1_CETUS_CH2_054_STRIDE 1
+#define IBU_P1_CETUS_CH2_054_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_055_ADDR 0x01140337L
+#define IBU_P1_CETUS_CH2_055_STRIDE 1
+#define IBU_P1_CETUS_CH2_055_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_056_ADDR 0x01140338L
+#define IBU_P1_CETUS_CH2_056_STRIDE 1
+#define IBU_P1_CETUS_CH2_056_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_057_ADDR 0x01140339L
+#define IBU_P1_CETUS_CH2_057_STRIDE 1
+#define IBU_P1_CETUS_CH2_057_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_058_ADDR 0x0114033aL
+#define IBU_P1_CETUS_CH2_058_STRIDE 1
+#define IBU_P1_CETUS_CH2_058_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_059_ADDR 0x0114033bL
+#define IBU_P1_CETUS_CH2_059_STRIDE 1
+#define IBU_P1_CETUS_CH2_059_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_060_ADDR 0x0114033cL
+#define IBU_P1_CETUS_CH2_060_STRIDE 1
+#define IBU_P1_CETUS_CH2_060_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_061_ADDR 0x0114033dL
+#define IBU_P1_CETUS_CH2_061_STRIDE 1
+#define IBU_P1_CETUS_CH2_061_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_062_ADDR 0x0114033eL
+#define IBU_P1_CETUS_CH2_062_STRIDE 1
+#define IBU_P1_CETUS_CH2_062_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_063_ADDR 0x0114033fL
+#define IBU_P1_CETUS_CH2_063_STRIDE 1
+#define IBU_P1_CETUS_CH2_063_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_064_ADDR 0x01140340L
+#define IBU_P1_CETUS_CH2_064_STRIDE 1
+#define IBU_P1_CETUS_CH2_064_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_065_ADDR 0x01140341L
+#define IBU_P1_CETUS_CH2_065_STRIDE 1
+#define IBU_P1_CETUS_CH2_065_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_066_ADDR 0x01140342L
+#define IBU_P1_CETUS_CH2_066_STRIDE 1
+#define IBU_P1_CETUS_CH2_066_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_067_ADDR 0x01140343L
+#define IBU_P1_CETUS_CH2_067_STRIDE 1
+#define IBU_P1_CETUS_CH2_067_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_068_ADDR 0x01140344L
+#define IBU_P1_CETUS_CH2_068_STRIDE 1
+#define IBU_P1_CETUS_CH2_068_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_069_ADDR 0x01140345L
+#define IBU_P1_CETUS_CH2_069_STRIDE 1
+#define IBU_P1_CETUS_CH2_069_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_070_ADDR 0x01140346L
+#define IBU_P1_CETUS_CH2_070_STRIDE 1
+#define IBU_P1_CETUS_CH2_070_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_071_ADDR 0x01140347L
+#define IBU_P1_CETUS_CH2_071_STRIDE 1
+#define IBU_P1_CETUS_CH2_071_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_072_ADDR 0x01140348L
+#define IBU_P1_CETUS_CH2_072_STRIDE 1
+#define IBU_P1_CETUS_CH2_072_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_073_ADDR 0x01140349L
+#define IBU_P1_CETUS_CH2_073_STRIDE 1
+#define IBU_P1_CETUS_CH2_073_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_074_ADDR 0x0114034aL
+#define IBU_P1_CETUS_CH2_074_STRIDE 1
+#define IBU_P1_CETUS_CH2_074_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_075_ADDR 0x0114034bL
+#define IBU_P1_CETUS_CH2_075_STRIDE 1
+#define IBU_P1_CETUS_CH2_075_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_076_ADDR 0x0114034cL
+#define IBU_P1_CETUS_CH2_076_STRIDE 1
+#define IBU_P1_CETUS_CH2_076_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_077_ADDR 0x0114034dL
+#define IBU_P1_CETUS_CH2_077_STRIDE 1
+#define IBU_P1_CETUS_CH2_077_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_078_ADDR 0x0114034eL
+#define IBU_P1_CETUS_CH2_078_STRIDE 1
+#define IBU_P1_CETUS_CH2_078_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_079_ADDR 0x0114034fL
+#define IBU_P1_CETUS_CH2_079_STRIDE 1
+#define IBU_P1_CETUS_CH2_079_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_080_ADDR 0x01140350L
+#define IBU_P1_CETUS_CH2_080_STRIDE 1
+#define IBU_P1_CETUS_CH2_080_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_081_ADDR 0x01140351L
+#define IBU_P1_CETUS_CH2_081_STRIDE 1
+#define IBU_P1_CETUS_CH2_081_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_082_ADDR 0x01140352L
+#define IBU_P1_CETUS_CH2_082_STRIDE 1
+#define IBU_P1_CETUS_CH2_082_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_083_ADDR 0x01140353L
+#define IBU_P1_CETUS_CH2_083_STRIDE 1
+#define IBU_P1_CETUS_CH2_083_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_084_ADDR 0x01140354L
+#define IBU_P1_CETUS_CH2_084_STRIDE 1
+#define IBU_P1_CETUS_CH2_084_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_085_ADDR 0x01140355L
+#define IBU_P1_CETUS_CH2_085_STRIDE 1
+#define IBU_P1_CETUS_CH2_085_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_086_ADDR 0x01140356L
+#define IBU_P1_CETUS_CH2_086_STRIDE 1
+#define IBU_P1_CETUS_CH2_086_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_087_ADDR 0x01140357L
+#define IBU_P1_CETUS_CH2_087_STRIDE 1
+#define IBU_P1_CETUS_CH2_087_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_088_ADDR 0x01140358L
+#define IBU_P1_CETUS_CH2_088_STRIDE 1
+#define IBU_P1_CETUS_CH2_088_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_089_ADDR 0x01140359L
+#define IBU_P1_CETUS_CH2_089_STRIDE 1
+#define IBU_P1_CETUS_CH2_089_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_090_ADDR 0x0114035aL
+#define IBU_P1_CETUS_CH2_090_STRIDE 1
+#define IBU_P1_CETUS_CH2_090_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_091_ADDR 0x0114035bL
+#define IBU_P1_CETUS_CH2_091_STRIDE 1
+#define IBU_P1_CETUS_CH2_091_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_092_ADDR 0x0114035cL
+#define IBU_P1_CETUS_CH2_092_STRIDE 1
+#define IBU_P1_CETUS_CH2_092_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_093_ADDR 0x0114035dL
+#define IBU_P1_CETUS_CH2_093_STRIDE 1
+#define IBU_P1_CETUS_CH2_093_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_094_ADDR 0x0114035eL
+#define IBU_P1_CETUS_CH2_094_STRIDE 1
+#define IBU_P1_CETUS_CH2_094_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_095_ADDR 0x0114035fL
+#define IBU_P1_CETUS_CH2_095_STRIDE 1
+#define IBU_P1_CETUS_CH2_095_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_096_ADDR 0x01140360L
+#define IBU_P1_CETUS_CH2_096_STRIDE 1
+#define IBU_P1_CETUS_CH2_096_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_097_ADDR 0x01140361L
+#define IBU_P1_CETUS_CH2_097_STRIDE 1
+#define IBU_P1_CETUS_CH2_097_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_098_ADDR 0x01140362L
+#define IBU_P1_CETUS_CH2_098_STRIDE 1
+#define IBU_P1_CETUS_CH2_098_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_099_ADDR 0x01140363L
+#define IBU_P1_CETUS_CH2_099_STRIDE 1
+#define IBU_P1_CETUS_CH2_099_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_100_ADDR 0x01140364L
+#define IBU_P1_CETUS_CH2_100_STRIDE 1
+#define IBU_P1_CETUS_CH2_100_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_101_ADDR 0x01140365L
+#define IBU_P1_CETUS_CH2_101_STRIDE 1
+#define IBU_P1_CETUS_CH2_101_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_102_ADDR 0x01140366L
+#define IBU_P1_CETUS_CH2_102_STRIDE 1
+#define IBU_P1_CETUS_CH2_102_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_103_ADDR 0x01140367L
+#define IBU_P1_CETUS_CH2_103_STRIDE 1
+#define IBU_P1_CETUS_CH2_103_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_104_ADDR 0x01140368L
+#define IBU_P1_CETUS_CH2_104_STRIDE 1
+#define IBU_P1_CETUS_CH2_104_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_105_ADDR 0x01140369L
+#define IBU_P1_CETUS_CH2_105_STRIDE 1
+#define IBU_P1_CETUS_CH2_105_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_106_ADDR 0x0114036aL
+#define IBU_P1_CETUS_CH2_106_STRIDE 1
+#define IBU_P1_CETUS_CH2_106_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_107_ADDR 0x0114036bL
+#define IBU_P1_CETUS_CH2_107_STRIDE 1
+#define IBU_P1_CETUS_CH2_107_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_108_ADDR 0x0114036cL
+#define IBU_P1_CETUS_CH2_108_STRIDE 1
+#define IBU_P1_CETUS_CH2_108_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_109_ADDR 0x0114036dL
+#define IBU_P1_CETUS_CH2_109_STRIDE 1
+#define IBU_P1_CETUS_CH2_109_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_110_ADDR 0x0114036eL
+#define IBU_P1_CETUS_CH2_110_STRIDE 1
+#define IBU_P1_CETUS_CH2_110_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_111_ADDR 0x0114036fL
+#define IBU_P1_CETUS_CH2_111_STRIDE 1
+#define IBU_P1_CETUS_CH2_111_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_112_ADDR 0x01140370L
+#define IBU_P1_CETUS_CH2_112_STRIDE 1
+#define IBU_P1_CETUS_CH2_112_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_113_ADDR 0x01140371L
+#define IBU_P1_CETUS_CH2_113_STRIDE 1
+#define IBU_P1_CETUS_CH2_113_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_114_ADDR 0x01140372L
+#define IBU_P1_CETUS_CH2_114_STRIDE 1
+#define IBU_P1_CETUS_CH2_114_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_115_ADDR 0x01140373L
+#define IBU_P1_CETUS_CH2_115_STRIDE 1
+#define IBU_P1_CETUS_CH2_115_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_116_ADDR 0x01140374L
+#define IBU_P1_CETUS_CH2_116_STRIDE 1
+#define IBU_P1_CETUS_CH2_116_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_117_ADDR 0x01140375L
+#define IBU_P1_CETUS_CH2_117_STRIDE 1
+#define IBU_P1_CETUS_CH2_117_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_118_ADDR 0x01140376L
+#define IBU_P1_CETUS_CH2_118_STRIDE 1
+#define IBU_P1_CETUS_CH2_118_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_119_ADDR 0x01140377L
+#define IBU_P1_CETUS_CH2_119_STRIDE 1
+#define IBU_P1_CETUS_CH2_119_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_120_ADDR 0x01140378L
+#define IBU_P1_CETUS_CH2_120_STRIDE 1
+#define IBU_P1_CETUS_CH2_120_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_121_ADDR 0x01140379L
+#define IBU_P1_CETUS_CH2_121_STRIDE 1
+#define IBU_P1_CETUS_CH2_121_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_122_ADDR 0x0114037aL
+#define IBU_P1_CETUS_CH2_122_STRIDE 1
+#define IBU_P1_CETUS_CH2_122_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_123_ADDR 0x0114037bL
+#define IBU_P1_CETUS_CH2_123_STRIDE 1
+#define IBU_P1_CETUS_CH2_123_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_124_ADDR 0x0114037cL
+#define IBU_P1_CETUS_CH2_124_STRIDE 1
+#define IBU_P1_CETUS_CH2_124_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_125_ADDR 0x0114037dL
+#define IBU_P1_CETUS_CH2_125_STRIDE 1
+#define IBU_P1_CETUS_CH2_125_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_126_ADDR 0x0114037eL
+#define IBU_P1_CETUS_CH2_126_STRIDE 1
+#define IBU_P1_CETUS_CH2_126_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_127_ADDR 0x0114037fL
+#define IBU_P1_CETUS_CH2_127_STRIDE 1
+#define IBU_P1_CETUS_CH2_127_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_128_ADDR 0x01140380L
+#define IBU_P1_CETUS_CH2_128_STRIDE 1
+#define IBU_P1_CETUS_CH2_128_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_129_ADDR 0x01140381L
+#define IBU_P1_CETUS_CH2_129_STRIDE 1
+#define IBU_P1_CETUS_CH2_129_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_130_ADDR 0x01140382L
+#define IBU_P1_CETUS_CH2_130_STRIDE 1
+#define IBU_P1_CETUS_CH2_130_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_131_ADDR 0x01140383L
+#define IBU_P1_CETUS_CH2_131_STRIDE 1
+#define IBU_P1_CETUS_CH2_131_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_132_ADDR 0x01140384L
+#define IBU_P1_CETUS_CH2_132_STRIDE 1
+#define IBU_P1_CETUS_CH2_132_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_133_ADDR 0x01140385L
+#define IBU_P1_CETUS_CH2_133_STRIDE 1
+#define IBU_P1_CETUS_CH2_133_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_134_ADDR 0x01140386L
+#define IBU_P1_CETUS_CH2_134_STRIDE 1
+#define IBU_P1_CETUS_CH2_134_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_135_ADDR 0x01140387L
+#define IBU_P1_CETUS_CH2_135_STRIDE 1
+#define IBU_P1_CETUS_CH2_135_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_136_ADDR 0x01140388L
+#define IBU_P1_CETUS_CH2_136_STRIDE 1
+#define IBU_P1_CETUS_CH2_136_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_137_ADDR 0x01140389L
+#define IBU_P1_CETUS_CH2_137_STRIDE 1
+#define IBU_P1_CETUS_CH2_137_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_138_ADDR 0x0114038aL
+#define IBU_P1_CETUS_CH2_138_STRIDE 1
+#define IBU_P1_CETUS_CH2_138_DEPTH 1
+
+#define IBU_P1_CETUS_CH2_139_ADDR 0x0114038bL
+#define IBU_P1_CETUS_CH2_139_STRIDE 1
+#define IBU_P1_CETUS_CH2_139_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH3_000_ADDR 0x01140400L
+#define IBU_P1_CETUS_CH3_000_STRIDE 1
+#define IBU_P1_CETUS_CH3_000_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH3_001_ADDR 0x01140401L
+#define IBU_P1_CETUS_CH3_001_STRIDE 1
+#define IBU_P1_CETUS_CH3_001_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_CH3_002_ADDR 0x01140402L
+#define IBU_P1_CETUS_CH3_002_STRIDE 1
+#define IBU_P1_CETUS_CH3_002_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_003_ADDR 0x01140403L
+#define IBU_P1_CETUS_CH3_003_STRIDE 1
+#define IBU_P1_CETUS_CH3_003_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_004_ADDR 0x01140404L
+#define IBU_P1_CETUS_CH3_004_STRIDE 1
+#define IBU_P1_CETUS_CH3_004_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_005_ADDR 0x01140405L
+#define IBU_P1_CETUS_CH3_005_STRIDE 1
+#define IBU_P1_CETUS_CH3_005_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_006_ADDR 0x01140406L
+#define IBU_P1_CETUS_CH3_006_STRIDE 1
+#define IBU_P1_CETUS_CH3_006_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_007_ADDR 0x01140407L
+#define IBU_P1_CETUS_CH3_007_STRIDE 1
+#define IBU_P1_CETUS_CH3_007_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_008_ADDR 0x01140408L
+#define IBU_P1_CETUS_CH3_008_STRIDE 1
+#define IBU_P1_CETUS_CH3_008_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_009_ADDR 0x01140409L
+#define IBU_P1_CETUS_CH3_009_STRIDE 1
+#define IBU_P1_CETUS_CH3_009_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_010_ADDR 0x0114040aL
+#define IBU_P1_CETUS_CH3_010_STRIDE 1
+#define IBU_P1_CETUS_CH3_010_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_011_ADDR 0x0114040bL
+#define IBU_P1_CETUS_CH3_011_STRIDE 1
+#define IBU_P1_CETUS_CH3_011_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_012_ADDR 0x0114040cL
+#define IBU_P1_CETUS_CH3_012_STRIDE 1
+#define IBU_P1_CETUS_CH3_012_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_013_ADDR 0x0114040dL
+#define IBU_P1_CETUS_CH3_013_STRIDE 1
+#define IBU_P1_CETUS_CH3_013_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_014_ADDR 0x0114040eL
+#define IBU_P1_CETUS_CH3_014_STRIDE 1
+#define IBU_P1_CETUS_CH3_014_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_015_ADDR 0x0114040fL
+#define IBU_P1_CETUS_CH3_015_STRIDE 1
+#define IBU_P1_CETUS_CH3_015_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_016_ADDR 0x01140410L
+#define IBU_P1_CETUS_CH3_016_STRIDE 1
+#define IBU_P1_CETUS_CH3_016_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_017_ADDR 0x01140411L
+#define IBU_P1_CETUS_CH3_017_STRIDE 1
+#define IBU_P1_CETUS_CH3_017_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_018_ADDR 0x01140412L
+#define IBU_P1_CETUS_CH3_018_STRIDE 1
+#define IBU_P1_CETUS_CH3_018_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_019_ADDR 0x01140413L
+#define IBU_P1_CETUS_CH3_019_STRIDE 1
+#define IBU_P1_CETUS_CH3_019_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_020_ADDR 0x01140414L
+#define IBU_P1_CETUS_CH3_020_STRIDE 1
+#define IBU_P1_CETUS_CH3_020_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_021_ADDR 0x01140415L
+#define IBU_P1_CETUS_CH3_021_STRIDE 1
+#define IBU_P1_CETUS_CH3_021_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_022_ADDR 0x01140416L
+#define IBU_P1_CETUS_CH3_022_STRIDE 1
+#define IBU_P1_CETUS_CH3_022_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_023_ADDR 0x01140417L
+#define IBU_P1_CETUS_CH3_023_STRIDE 1
+#define IBU_P1_CETUS_CH3_023_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_024_ADDR 0x01140418L
+#define IBU_P1_CETUS_CH3_024_STRIDE 1
+#define IBU_P1_CETUS_CH3_024_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_025_ADDR 0x01140419L
+#define IBU_P1_CETUS_CH3_025_STRIDE 1
+#define IBU_P1_CETUS_CH3_025_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_026_ADDR 0x0114041aL
+#define IBU_P1_CETUS_CH3_026_STRIDE 1
+#define IBU_P1_CETUS_CH3_026_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_027_ADDR 0x0114041bL
+#define IBU_P1_CETUS_CH3_027_STRIDE 1
+#define IBU_P1_CETUS_CH3_027_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_028_ADDR 0x0114041cL
+#define IBU_P1_CETUS_CH3_028_STRIDE 1
+#define IBU_P1_CETUS_CH3_028_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_029_ADDR 0x0114041dL
+#define IBU_P1_CETUS_CH3_029_STRIDE 1
+#define IBU_P1_CETUS_CH3_029_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_030_ADDR 0x0114041eL
+#define IBU_P1_CETUS_CH3_030_STRIDE 1
+#define IBU_P1_CETUS_CH3_030_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_031_ADDR 0x0114041fL
+#define IBU_P1_CETUS_CH3_031_STRIDE 1
+#define IBU_P1_CETUS_CH3_031_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_032_ADDR 0x01140420L
+#define IBU_P1_CETUS_CH3_032_STRIDE 1
+#define IBU_P1_CETUS_CH3_032_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_033_ADDR 0x01140421L
+#define IBU_P1_CETUS_CH3_033_STRIDE 1
+#define IBU_P1_CETUS_CH3_033_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_034_ADDR 0x01140422L
+#define IBU_P1_CETUS_CH3_034_STRIDE 1
+#define IBU_P1_CETUS_CH3_034_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_035_ADDR 0x01140423L
+#define IBU_P1_CETUS_CH3_035_STRIDE 1
+#define IBU_P1_CETUS_CH3_035_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_036_ADDR 0x01140424L
+#define IBU_P1_CETUS_CH3_036_STRIDE 1
+#define IBU_P1_CETUS_CH3_036_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_037_ADDR 0x01140425L
+#define IBU_P1_CETUS_CH3_037_STRIDE 1
+#define IBU_P1_CETUS_CH3_037_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_038_ADDR 0x01140426L
+#define IBU_P1_CETUS_CH3_038_STRIDE 1
+#define IBU_P1_CETUS_CH3_038_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_039_ADDR 0x01140427L
+#define IBU_P1_CETUS_CH3_039_STRIDE 1
+#define IBU_P1_CETUS_CH3_039_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_040_ADDR 0x01140428L
+#define IBU_P1_CETUS_CH3_040_STRIDE 1
+#define IBU_P1_CETUS_CH3_040_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_041_ADDR 0x01140429L
+#define IBU_P1_CETUS_CH3_041_STRIDE 1
+#define IBU_P1_CETUS_CH3_041_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_042_ADDR 0x0114042aL
+#define IBU_P1_CETUS_CH3_042_STRIDE 1
+#define IBU_P1_CETUS_CH3_042_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_043_ADDR 0x0114042bL
+#define IBU_P1_CETUS_CH3_043_STRIDE 1
+#define IBU_P1_CETUS_CH3_043_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_044_ADDR 0x0114042cL
+#define IBU_P1_CETUS_CH3_044_STRIDE 1
+#define IBU_P1_CETUS_CH3_044_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_045_ADDR 0x0114042dL
+#define IBU_P1_CETUS_CH3_045_STRIDE 1
+#define IBU_P1_CETUS_CH3_045_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_046_ADDR 0x0114042eL
+#define IBU_P1_CETUS_CH3_046_STRIDE 1
+#define IBU_P1_CETUS_CH3_046_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_047_ADDR 0x0114042fL
+#define IBU_P1_CETUS_CH3_047_STRIDE 1
+#define IBU_P1_CETUS_CH3_047_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_048_ADDR 0x01140430L
+#define IBU_P1_CETUS_CH3_048_STRIDE 1
+#define IBU_P1_CETUS_CH3_048_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_049_ADDR 0x01140431L
+#define IBU_P1_CETUS_CH3_049_STRIDE 1
+#define IBU_P1_CETUS_CH3_049_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_050_ADDR 0x01140432L
+#define IBU_P1_CETUS_CH3_050_STRIDE 1
+#define IBU_P1_CETUS_CH3_050_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_051_ADDR 0x01140433L
+#define IBU_P1_CETUS_CH3_051_STRIDE 1
+#define IBU_P1_CETUS_CH3_051_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_052_ADDR 0x01140434L
+#define IBU_P1_CETUS_CH3_052_STRIDE 1
+#define IBU_P1_CETUS_CH3_052_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_053_ADDR 0x01140435L
+#define IBU_P1_CETUS_CH3_053_STRIDE 1
+#define IBU_P1_CETUS_CH3_053_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_054_ADDR 0x01140436L
+#define IBU_P1_CETUS_CH3_054_STRIDE 1
+#define IBU_P1_CETUS_CH3_054_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_055_ADDR 0x01140437L
+#define IBU_P1_CETUS_CH3_055_STRIDE 1
+#define IBU_P1_CETUS_CH3_055_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_056_ADDR 0x01140438L
+#define IBU_P1_CETUS_CH3_056_STRIDE 1
+#define IBU_P1_CETUS_CH3_056_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_057_ADDR 0x01140439L
+#define IBU_P1_CETUS_CH3_057_STRIDE 1
+#define IBU_P1_CETUS_CH3_057_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_058_ADDR 0x0114043aL
+#define IBU_P1_CETUS_CH3_058_STRIDE 1
+#define IBU_P1_CETUS_CH3_058_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_059_ADDR 0x0114043bL
+#define IBU_P1_CETUS_CH3_059_STRIDE 1
+#define IBU_P1_CETUS_CH3_059_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_060_ADDR 0x0114043cL
+#define IBU_P1_CETUS_CH3_060_STRIDE 1
+#define IBU_P1_CETUS_CH3_060_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_061_ADDR 0x0114043dL
+#define IBU_P1_CETUS_CH3_061_STRIDE 1
+#define IBU_P1_CETUS_CH3_061_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_062_ADDR 0x0114043eL
+#define IBU_P1_CETUS_CH3_062_STRIDE 1
+#define IBU_P1_CETUS_CH3_062_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_063_ADDR 0x0114043fL
+#define IBU_P1_CETUS_CH3_063_STRIDE 1
+#define IBU_P1_CETUS_CH3_063_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_064_ADDR 0x01140440L
+#define IBU_P1_CETUS_CH3_064_STRIDE 1
+#define IBU_P1_CETUS_CH3_064_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_065_ADDR 0x01140441L
+#define IBU_P1_CETUS_CH3_065_STRIDE 1
+#define IBU_P1_CETUS_CH3_065_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_066_ADDR 0x01140442L
+#define IBU_P1_CETUS_CH3_066_STRIDE 1
+#define IBU_P1_CETUS_CH3_066_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_067_ADDR 0x01140443L
+#define IBU_P1_CETUS_CH3_067_STRIDE 1
+#define IBU_P1_CETUS_CH3_067_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_068_ADDR 0x01140444L
+#define IBU_P1_CETUS_CH3_068_STRIDE 1
+#define IBU_P1_CETUS_CH3_068_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_069_ADDR 0x01140445L
+#define IBU_P1_CETUS_CH3_069_STRIDE 1
+#define IBU_P1_CETUS_CH3_069_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_070_ADDR 0x01140446L
+#define IBU_P1_CETUS_CH3_070_STRIDE 1
+#define IBU_P1_CETUS_CH3_070_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_071_ADDR 0x01140447L
+#define IBU_P1_CETUS_CH3_071_STRIDE 1
+#define IBU_P1_CETUS_CH3_071_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_072_ADDR 0x01140448L
+#define IBU_P1_CETUS_CH3_072_STRIDE 1
+#define IBU_P1_CETUS_CH3_072_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_073_ADDR 0x01140449L
+#define IBU_P1_CETUS_CH3_073_STRIDE 1
+#define IBU_P1_CETUS_CH3_073_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_074_ADDR 0x0114044aL
+#define IBU_P1_CETUS_CH3_074_STRIDE 1
+#define IBU_P1_CETUS_CH3_074_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_075_ADDR 0x0114044bL
+#define IBU_P1_CETUS_CH3_075_STRIDE 1
+#define IBU_P1_CETUS_CH3_075_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_076_ADDR 0x0114044cL
+#define IBU_P1_CETUS_CH3_076_STRIDE 1
+#define IBU_P1_CETUS_CH3_076_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_077_ADDR 0x0114044dL
+#define IBU_P1_CETUS_CH3_077_STRIDE 1
+#define IBU_P1_CETUS_CH3_077_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_078_ADDR 0x0114044eL
+#define IBU_P1_CETUS_CH3_078_STRIDE 1
+#define IBU_P1_CETUS_CH3_078_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_079_ADDR 0x0114044fL
+#define IBU_P1_CETUS_CH3_079_STRIDE 1
+#define IBU_P1_CETUS_CH3_079_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_080_ADDR 0x01140450L
+#define IBU_P1_CETUS_CH3_080_STRIDE 1
+#define IBU_P1_CETUS_CH3_080_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_081_ADDR 0x01140451L
+#define IBU_P1_CETUS_CH3_081_STRIDE 1
+#define IBU_P1_CETUS_CH3_081_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_082_ADDR 0x01140452L
+#define IBU_P1_CETUS_CH3_082_STRIDE 1
+#define IBU_P1_CETUS_CH3_082_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_083_ADDR 0x01140453L
+#define IBU_P1_CETUS_CH3_083_STRIDE 1
+#define IBU_P1_CETUS_CH3_083_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_084_ADDR 0x01140454L
+#define IBU_P1_CETUS_CH3_084_STRIDE 1
+#define IBU_P1_CETUS_CH3_084_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_085_ADDR 0x01140455L
+#define IBU_P1_CETUS_CH3_085_STRIDE 1
+#define IBU_P1_CETUS_CH3_085_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_086_ADDR 0x01140456L
+#define IBU_P1_CETUS_CH3_086_STRIDE 1
+#define IBU_P1_CETUS_CH3_086_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_087_ADDR 0x01140457L
+#define IBU_P1_CETUS_CH3_087_STRIDE 1
+#define IBU_P1_CETUS_CH3_087_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_088_ADDR 0x01140458L
+#define IBU_P1_CETUS_CH3_088_STRIDE 1
+#define IBU_P1_CETUS_CH3_088_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_089_ADDR 0x01140459L
+#define IBU_P1_CETUS_CH3_089_STRIDE 1
+#define IBU_P1_CETUS_CH3_089_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_090_ADDR 0x0114045aL
+#define IBU_P1_CETUS_CH3_090_STRIDE 1
+#define IBU_P1_CETUS_CH3_090_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_091_ADDR 0x0114045bL
+#define IBU_P1_CETUS_CH3_091_STRIDE 1
+#define IBU_P1_CETUS_CH3_091_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_092_ADDR 0x0114045cL
+#define IBU_P1_CETUS_CH3_092_STRIDE 1
+#define IBU_P1_CETUS_CH3_092_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_093_ADDR 0x0114045dL
+#define IBU_P1_CETUS_CH3_093_STRIDE 1
+#define IBU_P1_CETUS_CH3_093_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_094_ADDR 0x0114045eL
+#define IBU_P1_CETUS_CH3_094_STRIDE 1
+#define IBU_P1_CETUS_CH3_094_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_095_ADDR 0x0114045fL
+#define IBU_P1_CETUS_CH3_095_STRIDE 1
+#define IBU_P1_CETUS_CH3_095_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_096_ADDR 0x01140460L
+#define IBU_P1_CETUS_CH3_096_STRIDE 1
+#define IBU_P1_CETUS_CH3_096_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_097_ADDR 0x01140461L
+#define IBU_P1_CETUS_CH3_097_STRIDE 1
+#define IBU_P1_CETUS_CH3_097_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_098_ADDR 0x01140462L
+#define IBU_P1_CETUS_CH3_098_STRIDE 1
+#define IBU_P1_CETUS_CH3_098_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_099_ADDR 0x01140463L
+#define IBU_P1_CETUS_CH3_099_STRIDE 1
+#define IBU_P1_CETUS_CH3_099_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_100_ADDR 0x01140464L
+#define IBU_P1_CETUS_CH3_100_STRIDE 1
+#define IBU_P1_CETUS_CH3_100_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_101_ADDR 0x01140465L
+#define IBU_P1_CETUS_CH3_101_STRIDE 1
+#define IBU_P1_CETUS_CH3_101_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_102_ADDR 0x01140466L
+#define IBU_P1_CETUS_CH3_102_STRIDE 1
+#define IBU_P1_CETUS_CH3_102_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_103_ADDR 0x01140467L
+#define IBU_P1_CETUS_CH3_103_STRIDE 1
+#define IBU_P1_CETUS_CH3_103_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_104_ADDR 0x01140468L
+#define IBU_P1_CETUS_CH3_104_STRIDE 1
+#define IBU_P1_CETUS_CH3_104_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_105_ADDR 0x01140469L
+#define IBU_P1_CETUS_CH3_105_STRIDE 1
+#define IBU_P1_CETUS_CH3_105_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_106_ADDR 0x0114046aL
+#define IBU_P1_CETUS_CH3_106_STRIDE 1
+#define IBU_P1_CETUS_CH3_106_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_107_ADDR 0x0114046bL
+#define IBU_P1_CETUS_CH3_107_STRIDE 1
+#define IBU_P1_CETUS_CH3_107_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_108_ADDR 0x0114046cL
+#define IBU_P1_CETUS_CH3_108_STRIDE 1
+#define IBU_P1_CETUS_CH3_108_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_109_ADDR 0x0114046dL
+#define IBU_P1_CETUS_CH3_109_STRIDE 1
+#define IBU_P1_CETUS_CH3_109_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_110_ADDR 0x0114046eL
+#define IBU_P1_CETUS_CH3_110_STRIDE 1
+#define IBU_P1_CETUS_CH3_110_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_111_ADDR 0x0114046fL
+#define IBU_P1_CETUS_CH3_111_STRIDE 1
+#define IBU_P1_CETUS_CH3_111_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_112_ADDR 0x01140470L
+#define IBU_P1_CETUS_CH3_112_STRIDE 1
+#define IBU_P1_CETUS_CH3_112_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_113_ADDR 0x01140471L
+#define IBU_P1_CETUS_CH3_113_STRIDE 1
+#define IBU_P1_CETUS_CH3_113_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_114_ADDR 0x01140472L
+#define IBU_P1_CETUS_CH3_114_STRIDE 1
+#define IBU_P1_CETUS_CH3_114_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_115_ADDR 0x01140473L
+#define IBU_P1_CETUS_CH3_115_STRIDE 1
+#define IBU_P1_CETUS_CH3_115_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_116_ADDR 0x01140474L
+#define IBU_P1_CETUS_CH3_116_STRIDE 1
+#define IBU_P1_CETUS_CH3_116_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_117_ADDR 0x01140475L
+#define IBU_P1_CETUS_CH3_117_STRIDE 1
+#define IBU_P1_CETUS_CH3_117_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_118_ADDR 0x01140476L
+#define IBU_P1_CETUS_CH3_118_STRIDE 1
+#define IBU_P1_CETUS_CH3_118_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_119_ADDR 0x01140477L
+#define IBU_P1_CETUS_CH3_119_STRIDE 1
+#define IBU_P1_CETUS_CH3_119_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_120_ADDR 0x01140478L
+#define IBU_P1_CETUS_CH3_120_STRIDE 1
+#define IBU_P1_CETUS_CH3_120_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_121_ADDR 0x01140479L
+#define IBU_P1_CETUS_CH3_121_STRIDE 1
+#define IBU_P1_CETUS_CH3_121_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_122_ADDR 0x0114047aL
+#define IBU_P1_CETUS_CH3_122_STRIDE 1
+#define IBU_P1_CETUS_CH3_122_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_123_ADDR 0x0114047bL
+#define IBU_P1_CETUS_CH3_123_STRIDE 1
+#define IBU_P1_CETUS_CH3_123_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_124_ADDR 0x0114047cL
+#define IBU_P1_CETUS_CH3_124_STRIDE 1
+#define IBU_P1_CETUS_CH3_124_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_125_ADDR 0x0114047dL
+#define IBU_P1_CETUS_CH3_125_STRIDE 1
+#define IBU_P1_CETUS_CH3_125_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_126_ADDR 0x0114047eL
+#define IBU_P1_CETUS_CH3_126_STRIDE 1
+#define IBU_P1_CETUS_CH3_126_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_127_ADDR 0x0114047fL
+#define IBU_P1_CETUS_CH3_127_STRIDE 1
+#define IBU_P1_CETUS_CH3_127_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_128_ADDR 0x01140480L
+#define IBU_P1_CETUS_CH3_128_STRIDE 1
+#define IBU_P1_CETUS_CH3_128_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_129_ADDR 0x01140481L
+#define IBU_P1_CETUS_CH3_129_STRIDE 1
+#define IBU_P1_CETUS_CH3_129_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_130_ADDR 0x01140482L
+#define IBU_P1_CETUS_CH3_130_STRIDE 1
+#define IBU_P1_CETUS_CH3_130_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_131_ADDR 0x01140483L
+#define IBU_P1_CETUS_CH3_131_STRIDE 1
+#define IBU_P1_CETUS_CH3_131_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_132_ADDR 0x01140484L
+#define IBU_P1_CETUS_CH3_132_STRIDE 1
+#define IBU_P1_CETUS_CH3_132_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_133_ADDR 0x01140485L
+#define IBU_P1_CETUS_CH3_133_STRIDE 1
+#define IBU_P1_CETUS_CH3_133_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_134_ADDR 0x01140486L
+#define IBU_P1_CETUS_CH3_134_STRIDE 1
+#define IBU_P1_CETUS_CH3_134_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_135_ADDR 0x01140487L
+#define IBU_P1_CETUS_CH3_135_STRIDE 1
+#define IBU_P1_CETUS_CH3_135_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_136_ADDR 0x01140488L
+#define IBU_P1_CETUS_CH3_136_STRIDE 1
+#define IBU_P1_CETUS_CH3_136_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_137_ADDR 0x01140489L
+#define IBU_P1_CETUS_CH3_137_STRIDE 1
+#define IBU_P1_CETUS_CH3_137_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_138_ADDR 0x0114048aL
+#define IBU_P1_CETUS_CH3_138_STRIDE 1
+#define IBU_P1_CETUS_CH3_138_DEPTH 1
+
+#define IBU_P1_CETUS_CH3_139_ADDR 0x0114048bL
+#define IBU_P1_CETUS_CH3_139_STRIDE 1
+#define IBU_P1_CETUS_CH3_139_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_CONTROL0_ADDR 0x01140600L
+#define IBU_P1_CETUS_PLLB_CONTROL0_STRIDE 1
+#define IBU_P1_CETUS_PLLB_CONTROL0_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_CONTROL1_ADDR 0x01140601L
+#define IBU_P1_CETUS_PLLB_CONTROL1_STRIDE 1
+#define IBU_P1_CETUS_PLLB_CONTROL1_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_CONTROL2_ADDR 0x01140602L
+#define IBU_P1_CETUS_PLLB_CONTROL2_STRIDE 1
+#define IBU_P1_CETUS_PLLB_CONTROL2_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_EXTFB_CNTR_ADDR 0x01140603L
+#define IBU_P1_CETUS_PLLB_EXTFB_CNTR_STRIDE 1
+#define IBU_P1_CETUS_PLLB_EXTFB_CNTR_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_FBCNT_ATO_ADDR 0x01140604L
+#define IBU_P1_CETUS_PLLB_FBCNT_ATO_STRIDE 1
+#define IBU_P1_CETUS_PLLB_FBCNT_ATO_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_SPARE_USRCNTR_ADDR 0x01140605L
+#define IBU_P1_CETUS_PLLB_SPARE_USRCNTR_STRIDE 1
+#define IBU_P1_CETUS_PLLB_SPARE_USRCNTR_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_DIV_EN_ADDR 0x01140606L
+#define IBU_P1_CETUS_PLLB_DIV_EN_STRIDE 1
+#define IBU_P1_CETUS_PLLB_DIV_EN_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_VCO_WAIT_CNT_ADDR 0x01140607L
+#define IBU_P1_CETUS_PLLB_VCO_WAIT_CNT_STRIDE 1
+#define IBU_P1_CETUS_PLLB_VCO_WAIT_CNT_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_STATUS0_ADDR 0x01140608L
+#define IBU_P1_CETUS_PLLB_STATUS0_STRIDE 1
+#define IBU_P1_CETUS_PLLB_STATUS0_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_STATUS1_ADDR 0x01140609L
+#define IBU_P1_CETUS_PLLB_STATUS1_STRIDE 1
+#define IBU_P1_CETUS_PLLB_STATUS1_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_010_ADDR 0x0114060aL
+#define IBU_P1_CETUS_PLLB_010_STRIDE 1
+#define IBU_P1_CETUS_PLLB_010_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_011_ADDR 0x0114060bL
+#define IBU_P1_CETUS_PLLB_011_STRIDE 1
+#define IBU_P1_CETUS_PLLB_011_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_012_ADDR 0x0114060cL
+#define IBU_P1_CETUS_PLLB_012_STRIDE 1
+#define IBU_P1_CETUS_PLLB_012_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_013_ADDR 0x0114060dL
+#define IBU_P1_CETUS_PLLB_013_STRIDE 1
+#define IBU_P1_CETUS_PLLB_013_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_014_ADDR 0x0114060eL
+#define IBU_P1_CETUS_PLLB_014_STRIDE 1
+#define IBU_P1_CETUS_PLLB_014_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_015_ADDR 0x0114060fL
+#define IBU_P1_CETUS_PLLB_015_STRIDE 1
+#define IBU_P1_CETUS_PLLB_015_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_016_ADDR 0x01140610L
+#define IBU_P1_CETUS_PLLB_016_STRIDE 1
+#define IBU_P1_CETUS_PLLB_016_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_017_ADDR 0x01140611L
+#define IBU_P1_CETUS_PLLB_017_STRIDE 1
+#define IBU_P1_CETUS_PLLB_017_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_018_ADDR 0x01140612L
+#define IBU_P1_CETUS_PLLB_018_STRIDE 1
+#define IBU_P1_CETUS_PLLB_018_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_019_ADDR 0x01140613L
+#define IBU_P1_CETUS_PLLB_019_STRIDE 1
+#define IBU_P1_CETUS_PLLB_019_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_020_ADDR 0x01140614L
+#define IBU_P1_CETUS_PLLB_020_STRIDE 1
+#define IBU_P1_CETUS_PLLB_020_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_021_ADDR 0x01140615L
+#define IBU_P1_CETUS_PLLB_021_STRIDE 1
+#define IBU_P1_CETUS_PLLB_021_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_022_ADDR 0x01140616L
+#define IBU_P1_CETUS_PLLB_022_STRIDE 1
+#define IBU_P1_CETUS_PLLB_022_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_023_ADDR 0x01140617L
+#define IBU_P1_CETUS_PLLB_023_STRIDE 1
+#define IBU_P1_CETUS_PLLB_023_DEPTH 1
+
+#define IBU_P1_CETUS_PLLB_024_ADDR 0x01140618L
+#define IBU_P1_CETUS_PLLB_024_STRIDE 1
+#define IBU_P1_CETUS_PLLB_024_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_ALL_000_ADDR 0x01140f00L
+#define IBU_P1_CETUS_ALL_000_STRIDE 1
+#define IBU_P1_CETUS_ALL_000_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_ALL_001_ADDR 0x01140f01L
+#define IBU_P1_CETUS_ALL_001_STRIDE 1
+#define IBU_P1_CETUS_ALL_001_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P1_CETUS_ALL_002_ADDR 0x01140f02L
+#define IBU_P1_CETUS_ALL_002_STRIDE 1
+#define IBU_P1_CETUS_ALL_002_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_003_ADDR 0x01140f03L
+#define IBU_P1_CETUS_ALL_003_STRIDE 1
+#define IBU_P1_CETUS_ALL_003_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_004_ADDR 0x01140f04L
+#define IBU_P1_CETUS_ALL_004_STRIDE 1
+#define IBU_P1_CETUS_ALL_004_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_005_ADDR 0x01140f05L
+#define IBU_P1_CETUS_ALL_005_STRIDE 1
+#define IBU_P1_CETUS_ALL_005_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_006_ADDR 0x01140f06L
+#define IBU_P1_CETUS_ALL_006_STRIDE 1
+#define IBU_P1_CETUS_ALL_006_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_007_ADDR 0x01140f07L
+#define IBU_P1_CETUS_ALL_007_STRIDE 1
+#define IBU_P1_CETUS_ALL_007_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_008_ADDR 0x01140f08L
+#define IBU_P1_CETUS_ALL_008_STRIDE 1
+#define IBU_P1_CETUS_ALL_008_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_009_ADDR 0x01140f09L
+#define IBU_P1_CETUS_ALL_009_STRIDE 1
+#define IBU_P1_CETUS_ALL_009_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_010_ADDR 0x01140f0aL
+#define IBU_P1_CETUS_ALL_010_STRIDE 1
+#define IBU_P1_CETUS_ALL_010_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_011_ADDR 0x01140f0bL
+#define IBU_P1_CETUS_ALL_011_STRIDE 1
+#define IBU_P1_CETUS_ALL_011_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_012_ADDR 0x01140f0cL
+#define IBU_P1_CETUS_ALL_012_STRIDE 1
+#define IBU_P1_CETUS_ALL_012_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_013_ADDR 0x01140f0dL
+#define IBU_P1_CETUS_ALL_013_STRIDE 1
+#define IBU_P1_CETUS_ALL_013_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_014_ADDR 0x01140f0eL
+#define IBU_P1_CETUS_ALL_014_STRIDE 1
+#define IBU_P1_CETUS_ALL_014_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_015_ADDR 0x01140f0fL
+#define IBU_P1_CETUS_ALL_015_STRIDE 1
+#define IBU_P1_CETUS_ALL_015_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_016_ADDR 0x01140f10L
+#define IBU_P1_CETUS_ALL_016_STRIDE 1
+#define IBU_P1_CETUS_ALL_016_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_017_ADDR 0x01140f11L
+#define IBU_P1_CETUS_ALL_017_STRIDE 1
+#define IBU_P1_CETUS_ALL_017_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_018_ADDR 0x01140f12L
+#define IBU_P1_CETUS_ALL_018_STRIDE 1
+#define IBU_P1_CETUS_ALL_018_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_019_ADDR 0x01140f13L
+#define IBU_P1_CETUS_ALL_019_STRIDE 1
+#define IBU_P1_CETUS_ALL_019_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_020_ADDR 0x01140f14L
+#define IBU_P1_CETUS_ALL_020_STRIDE 1
+#define IBU_P1_CETUS_ALL_020_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_021_ADDR 0x01140f15L
+#define IBU_P1_CETUS_ALL_021_STRIDE 1
+#define IBU_P1_CETUS_ALL_021_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_022_ADDR 0x01140f16L
+#define IBU_P1_CETUS_ALL_022_STRIDE 1
+#define IBU_P1_CETUS_ALL_022_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_023_ADDR 0x01140f17L
+#define IBU_P1_CETUS_ALL_023_STRIDE 1
+#define IBU_P1_CETUS_ALL_023_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_024_ADDR 0x01140f18L
+#define IBU_P1_CETUS_ALL_024_STRIDE 1
+#define IBU_P1_CETUS_ALL_024_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_025_ADDR 0x01140f19L
+#define IBU_P1_CETUS_ALL_025_STRIDE 1
+#define IBU_P1_CETUS_ALL_025_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_026_ADDR 0x01140f1aL
+#define IBU_P1_CETUS_ALL_026_STRIDE 1
+#define IBU_P1_CETUS_ALL_026_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_027_ADDR 0x01140f1bL
+#define IBU_P1_CETUS_ALL_027_STRIDE 1
+#define IBU_P1_CETUS_ALL_027_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_028_ADDR 0x01140f1cL
+#define IBU_P1_CETUS_ALL_028_STRIDE 1
+#define IBU_P1_CETUS_ALL_028_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_029_ADDR 0x01140f1dL
+#define IBU_P1_CETUS_ALL_029_STRIDE 1
+#define IBU_P1_CETUS_ALL_029_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_030_ADDR 0x01140f1eL
+#define IBU_P1_CETUS_ALL_030_STRIDE 1
+#define IBU_P1_CETUS_ALL_030_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_031_ADDR 0x01140f1fL
+#define IBU_P1_CETUS_ALL_031_STRIDE 1
+#define IBU_P1_CETUS_ALL_031_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_032_ADDR 0x01140f20L
+#define IBU_P1_CETUS_ALL_032_STRIDE 1
+#define IBU_P1_CETUS_ALL_032_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_033_ADDR 0x01140f21L
+#define IBU_P1_CETUS_ALL_033_STRIDE 1
+#define IBU_P1_CETUS_ALL_033_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_034_ADDR 0x01140f22L
+#define IBU_P1_CETUS_ALL_034_STRIDE 1
+#define IBU_P1_CETUS_ALL_034_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_035_ADDR 0x01140f23L
+#define IBU_P1_CETUS_ALL_035_STRIDE 1
+#define IBU_P1_CETUS_ALL_035_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_036_ADDR 0x01140f24L
+#define IBU_P1_CETUS_ALL_036_STRIDE 1
+#define IBU_P1_CETUS_ALL_036_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_037_ADDR 0x01140f25L
+#define IBU_P1_CETUS_ALL_037_STRIDE 1
+#define IBU_P1_CETUS_ALL_037_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_038_ADDR 0x01140f26L
+#define IBU_P1_CETUS_ALL_038_STRIDE 1
+#define IBU_P1_CETUS_ALL_038_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_039_ADDR 0x01140f27L
+#define IBU_P1_CETUS_ALL_039_STRIDE 1
+#define IBU_P1_CETUS_ALL_039_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_040_ADDR 0x01140f28L
+#define IBU_P1_CETUS_ALL_040_STRIDE 1
+#define IBU_P1_CETUS_ALL_040_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_041_ADDR 0x01140f29L
+#define IBU_P1_CETUS_ALL_041_STRIDE 1
+#define IBU_P1_CETUS_ALL_041_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_042_ADDR 0x01140f2aL
+#define IBU_P1_CETUS_ALL_042_STRIDE 1
+#define IBU_P1_CETUS_ALL_042_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_043_ADDR 0x01140f2bL
+#define IBU_P1_CETUS_ALL_043_STRIDE 1
+#define IBU_P1_CETUS_ALL_043_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_044_ADDR 0x01140f2cL
+#define IBU_P1_CETUS_ALL_044_STRIDE 1
+#define IBU_P1_CETUS_ALL_044_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_045_ADDR 0x01140f2dL
+#define IBU_P1_CETUS_ALL_045_STRIDE 1
+#define IBU_P1_CETUS_ALL_045_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_046_ADDR 0x01140f2eL
+#define IBU_P1_CETUS_ALL_046_STRIDE 1
+#define IBU_P1_CETUS_ALL_046_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_047_ADDR 0x01140f2fL
+#define IBU_P1_CETUS_ALL_047_STRIDE 1
+#define IBU_P1_CETUS_ALL_047_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_048_ADDR 0x01140f30L
+#define IBU_P1_CETUS_ALL_048_STRIDE 1
+#define IBU_P1_CETUS_ALL_048_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_049_ADDR 0x01140f31L
+#define IBU_P1_CETUS_ALL_049_STRIDE 1
+#define IBU_P1_CETUS_ALL_049_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_050_ADDR 0x01140f32L
+#define IBU_P1_CETUS_ALL_050_STRIDE 1
+#define IBU_P1_CETUS_ALL_050_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_051_ADDR 0x01140f33L
+#define IBU_P1_CETUS_ALL_051_STRIDE 1
+#define IBU_P1_CETUS_ALL_051_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_052_ADDR 0x01140f34L
+#define IBU_P1_CETUS_ALL_052_STRIDE 1
+#define IBU_P1_CETUS_ALL_052_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_053_ADDR 0x01140f35L
+#define IBU_P1_CETUS_ALL_053_STRIDE 1
+#define IBU_P1_CETUS_ALL_053_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_054_ADDR 0x01140f36L
+#define IBU_P1_CETUS_ALL_054_STRIDE 1
+#define IBU_P1_CETUS_ALL_054_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_055_ADDR 0x01140f37L
+#define IBU_P1_CETUS_ALL_055_STRIDE 1
+#define IBU_P1_CETUS_ALL_055_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_056_ADDR 0x01140f38L
+#define IBU_P1_CETUS_ALL_056_STRIDE 1
+#define IBU_P1_CETUS_ALL_056_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_057_ADDR 0x01140f39L
+#define IBU_P1_CETUS_ALL_057_STRIDE 1
+#define IBU_P1_CETUS_ALL_057_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_058_ADDR 0x01140f3aL
+#define IBU_P1_CETUS_ALL_058_STRIDE 1
+#define IBU_P1_CETUS_ALL_058_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_059_ADDR 0x01140f3bL
+#define IBU_P1_CETUS_ALL_059_STRIDE 1
+#define IBU_P1_CETUS_ALL_059_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_060_ADDR 0x01140f3cL
+#define IBU_P1_CETUS_ALL_060_STRIDE 1
+#define IBU_P1_CETUS_ALL_060_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_061_ADDR 0x01140f3dL
+#define IBU_P1_CETUS_ALL_061_STRIDE 1
+#define IBU_P1_CETUS_ALL_061_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_062_ADDR 0x01140f3eL
+#define IBU_P1_CETUS_ALL_062_STRIDE 1
+#define IBU_P1_CETUS_ALL_062_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_063_ADDR 0x01140f3fL
+#define IBU_P1_CETUS_ALL_063_STRIDE 1
+#define IBU_P1_CETUS_ALL_063_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_064_ADDR 0x01140f40L
+#define IBU_P1_CETUS_ALL_064_STRIDE 1
+#define IBU_P1_CETUS_ALL_064_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_065_ADDR 0x01140f41L
+#define IBU_P1_CETUS_ALL_065_STRIDE 1
+#define IBU_P1_CETUS_ALL_065_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_066_ADDR 0x01140f42L
+#define IBU_P1_CETUS_ALL_066_STRIDE 1
+#define IBU_P1_CETUS_ALL_066_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_067_ADDR 0x01140f43L
+#define IBU_P1_CETUS_ALL_067_STRIDE 1
+#define IBU_P1_CETUS_ALL_067_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_068_ADDR 0x01140f44L
+#define IBU_P1_CETUS_ALL_068_STRIDE 1
+#define IBU_P1_CETUS_ALL_068_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_069_ADDR 0x01140f45L
+#define IBU_P1_CETUS_ALL_069_STRIDE 1
+#define IBU_P1_CETUS_ALL_069_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_070_ADDR 0x01140f46L
+#define IBU_P1_CETUS_ALL_070_STRIDE 1
+#define IBU_P1_CETUS_ALL_070_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_071_ADDR 0x01140f47L
+#define IBU_P1_CETUS_ALL_071_STRIDE 1
+#define IBU_P1_CETUS_ALL_071_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_072_ADDR 0x01140f48L
+#define IBU_P1_CETUS_ALL_072_STRIDE 1
+#define IBU_P1_CETUS_ALL_072_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_073_ADDR 0x01140f49L
+#define IBU_P1_CETUS_ALL_073_STRIDE 1
+#define IBU_P1_CETUS_ALL_073_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_074_ADDR 0x01140f4aL
+#define IBU_P1_CETUS_ALL_074_STRIDE 1
+#define IBU_P1_CETUS_ALL_074_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_075_ADDR 0x01140f4bL
+#define IBU_P1_CETUS_ALL_075_STRIDE 1
+#define IBU_P1_CETUS_ALL_075_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_076_ADDR 0x01140f4cL
+#define IBU_P1_CETUS_ALL_076_STRIDE 1
+#define IBU_P1_CETUS_ALL_076_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_077_ADDR 0x01140f4dL
+#define IBU_P1_CETUS_ALL_077_STRIDE 1
+#define IBU_P1_CETUS_ALL_077_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_078_ADDR 0x01140f4eL
+#define IBU_P1_CETUS_ALL_078_STRIDE 1
+#define IBU_P1_CETUS_ALL_078_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_079_ADDR 0x01140f4fL
+#define IBU_P1_CETUS_ALL_079_STRIDE 1
+#define IBU_P1_CETUS_ALL_079_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_080_ADDR 0x01140f50L
+#define IBU_P1_CETUS_ALL_080_STRIDE 1
+#define IBU_P1_CETUS_ALL_080_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_081_ADDR 0x01140f51L
+#define IBU_P1_CETUS_ALL_081_STRIDE 1
+#define IBU_P1_CETUS_ALL_081_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_082_ADDR 0x01140f52L
+#define IBU_P1_CETUS_ALL_082_STRIDE 1
+#define IBU_P1_CETUS_ALL_082_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_083_ADDR 0x01140f53L
+#define IBU_P1_CETUS_ALL_083_STRIDE 1
+#define IBU_P1_CETUS_ALL_083_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_084_ADDR 0x01140f54L
+#define IBU_P1_CETUS_ALL_084_STRIDE 1
+#define IBU_P1_CETUS_ALL_084_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_085_ADDR 0x01140f55L
+#define IBU_P1_CETUS_ALL_085_STRIDE 1
+#define IBU_P1_CETUS_ALL_085_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_086_ADDR 0x01140f56L
+#define IBU_P1_CETUS_ALL_086_STRIDE 1
+#define IBU_P1_CETUS_ALL_086_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_087_ADDR 0x01140f57L
+#define IBU_P1_CETUS_ALL_087_STRIDE 1
+#define IBU_P1_CETUS_ALL_087_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_088_ADDR 0x01140f58L
+#define IBU_P1_CETUS_ALL_088_STRIDE 1
+#define IBU_P1_CETUS_ALL_088_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_089_ADDR 0x01140f59L
+#define IBU_P1_CETUS_ALL_089_STRIDE 1
+#define IBU_P1_CETUS_ALL_089_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_090_ADDR 0x01140f5aL
+#define IBU_P1_CETUS_ALL_090_STRIDE 1
+#define IBU_P1_CETUS_ALL_090_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_091_ADDR 0x01140f5bL
+#define IBU_P1_CETUS_ALL_091_STRIDE 1
+#define IBU_P1_CETUS_ALL_091_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_092_ADDR 0x01140f5cL
+#define IBU_P1_CETUS_ALL_092_STRIDE 1
+#define IBU_P1_CETUS_ALL_092_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_093_ADDR 0x01140f5dL
+#define IBU_P1_CETUS_ALL_093_STRIDE 1
+#define IBU_P1_CETUS_ALL_093_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_094_ADDR 0x01140f5eL
+#define IBU_P1_CETUS_ALL_094_STRIDE 1
+#define IBU_P1_CETUS_ALL_094_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_095_ADDR 0x01140f5fL
+#define IBU_P1_CETUS_ALL_095_STRIDE 1
+#define IBU_P1_CETUS_ALL_095_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_096_ADDR 0x01140f60L
+#define IBU_P1_CETUS_ALL_096_STRIDE 1
+#define IBU_P1_CETUS_ALL_096_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_097_ADDR 0x01140f61L
+#define IBU_P1_CETUS_ALL_097_STRIDE 1
+#define IBU_P1_CETUS_ALL_097_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_098_ADDR 0x01140f62L
+#define IBU_P1_CETUS_ALL_098_STRIDE 1
+#define IBU_P1_CETUS_ALL_098_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_099_ADDR 0x01140f63L
+#define IBU_P1_CETUS_ALL_099_STRIDE 1
+#define IBU_P1_CETUS_ALL_099_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_100_ADDR 0x01140f64L
+#define IBU_P1_CETUS_ALL_100_STRIDE 1
+#define IBU_P1_CETUS_ALL_100_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_101_ADDR 0x01140f65L
+#define IBU_P1_CETUS_ALL_101_STRIDE 1
+#define IBU_P1_CETUS_ALL_101_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_102_ADDR 0x01140f66L
+#define IBU_P1_CETUS_ALL_102_STRIDE 1
+#define IBU_P1_CETUS_ALL_102_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_103_ADDR 0x01140f67L
+#define IBU_P1_CETUS_ALL_103_STRIDE 1
+#define IBU_P1_CETUS_ALL_103_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_104_ADDR 0x01140f68L
+#define IBU_P1_CETUS_ALL_104_STRIDE 1
+#define IBU_P1_CETUS_ALL_104_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_105_ADDR 0x01140f69L
+#define IBU_P1_CETUS_ALL_105_STRIDE 1
+#define IBU_P1_CETUS_ALL_105_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_106_ADDR 0x01140f6aL
+#define IBU_P1_CETUS_ALL_106_STRIDE 1
+#define IBU_P1_CETUS_ALL_106_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_107_ADDR 0x01140f6bL
+#define IBU_P1_CETUS_ALL_107_STRIDE 1
+#define IBU_P1_CETUS_ALL_107_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_108_ADDR 0x01140f6cL
+#define IBU_P1_CETUS_ALL_108_STRIDE 1
+#define IBU_P1_CETUS_ALL_108_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_109_ADDR 0x01140f6dL
+#define IBU_P1_CETUS_ALL_109_STRIDE 1
+#define IBU_P1_CETUS_ALL_109_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_110_ADDR 0x01140f6eL
+#define IBU_P1_CETUS_ALL_110_STRIDE 1
+#define IBU_P1_CETUS_ALL_110_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_111_ADDR 0x01140f6fL
+#define IBU_P1_CETUS_ALL_111_STRIDE 1
+#define IBU_P1_CETUS_ALL_111_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_112_ADDR 0x01140f70L
+#define IBU_P1_CETUS_ALL_112_STRIDE 1
+#define IBU_P1_CETUS_ALL_112_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_113_ADDR 0x01140f71L
+#define IBU_P1_CETUS_ALL_113_STRIDE 1
+#define IBU_P1_CETUS_ALL_113_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_114_ADDR 0x01140f72L
+#define IBU_P1_CETUS_ALL_114_STRIDE 1
+#define IBU_P1_CETUS_ALL_114_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_115_ADDR 0x01140f73L
+#define IBU_P1_CETUS_ALL_115_STRIDE 1
+#define IBU_P1_CETUS_ALL_115_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_116_ADDR 0x01140f74L
+#define IBU_P1_CETUS_ALL_116_STRIDE 1
+#define IBU_P1_CETUS_ALL_116_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_117_ADDR 0x01140f75L
+#define IBU_P1_CETUS_ALL_117_STRIDE 1
+#define IBU_P1_CETUS_ALL_117_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_118_ADDR 0x01140f76L
+#define IBU_P1_CETUS_ALL_118_STRIDE 1
+#define IBU_P1_CETUS_ALL_118_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_119_ADDR 0x01140f77L
+#define IBU_P1_CETUS_ALL_119_STRIDE 1
+#define IBU_P1_CETUS_ALL_119_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_120_ADDR 0x01140f78L
+#define IBU_P1_CETUS_ALL_120_STRIDE 1
+#define IBU_P1_CETUS_ALL_120_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_121_ADDR 0x01140f79L
+#define IBU_P1_CETUS_ALL_121_STRIDE 1
+#define IBU_P1_CETUS_ALL_121_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_122_ADDR 0x01140f7aL
+#define IBU_P1_CETUS_ALL_122_STRIDE 1
+#define IBU_P1_CETUS_ALL_122_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_123_ADDR 0x01140f7bL
+#define IBU_P1_CETUS_ALL_123_STRIDE 1
+#define IBU_P1_CETUS_ALL_123_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_124_ADDR 0x01140f7cL
+#define IBU_P1_CETUS_ALL_124_STRIDE 1
+#define IBU_P1_CETUS_ALL_124_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_125_ADDR 0x01140f7dL
+#define IBU_P1_CETUS_ALL_125_STRIDE 1
+#define IBU_P1_CETUS_ALL_125_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_126_ADDR 0x01140f7eL
+#define IBU_P1_CETUS_ALL_126_STRIDE 1
+#define IBU_P1_CETUS_ALL_126_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_127_ADDR 0x01140f7fL
+#define IBU_P1_CETUS_ALL_127_STRIDE 1
+#define IBU_P1_CETUS_ALL_127_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_128_ADDR 0x01140f80L
+#define IBU_P1_CETUS_ALL_128_STRIDE 1
+#define IBU_P1_CETUS_ALL_128_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_129_ADDR 0x01140f81L
+#define IBU_P1_CETUS_ALL_129_STRIDE 1
+#define IBU_P1_CETUS_ALL_129_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_130_ADDR 0x01140f82L
+#define IBU_P1_CETUS_ALL_130_STRIDE 1
+#define IBU_P1_CETUS_ALL_130_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_131_ADDR 0x01140f83L
+#define IBU_P1_CETUS_ALL_131_STRIDE 1
+#define IBU_P1_CETUS_ALL_131_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_132_ADDR 0x01140f84L
+#define IBU_P1_CETUS_ALL_132_STRIDE 1
+#define IBU_P1_CETUS_ALL_132_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_133_ADDR 0x01140f85L
+#define IBU_P1_CETUS_ALL_133_STRIDE 1
+#define IBU_P1_CETUS_ALL_133_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_134_ADDR 0x01140f86L
+#define IBU_P1_CETUS_ALL_134_STRIDE 1
+#define IBU_P1_CETUS_ALL_134_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_135_ADDR 0x01140f87L
+#define IBU_P1_CETUS_ALL_135_STRIDE 1
+#define IBU_P1_CETUS_ALL_135_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_136_ADDR 0x01140f88L
+#define IBU_P1_CETUS_ALL_136_STRIDE 1
+#define IBU_P1_CETUS_ALL_136_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_137_ADDR 0x01140f89L
+#define IBU_P1_CETUS_ALL_137_STRIDE 1
+#define IBU_P1_CETUS_ALL_137_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_138_ADDR 0x01140f8aL
+#define IBU_P1_CETUS_ALL_138_STRIDE 1
+#define IBU_P1_CETUS_ALL_138_DEPTH 1
+
+#define IBU_P1_CETUS_ALL_139_ADDR 0x01140f8bL
+#define IBU_P1_CETUS_ALL_139_STRIDE 1
+#define IBU_P1_CETUS_ALL_139_DEPTH 1
+
+#define IBU_P1_PMA_RESET_CSR_ADDR 0x01160000L
+#define IBU_P1_PMA_RESET_CSR_STRIDE 1
+#define IBU_P1_PMA_RESET_CSR_DEPTH 1
+
+#define IBU_P1_PMA_PLLA_CSR_ADDR 0x01160001L
+#define IBU_P1_PMA_PLLA_CSR_STRIDE 1
+#define IBU_P1_PMA_PLLA_CSR_DEPTH 1
+
+#define IBU_P1_PMA_PLLB_CSR_ADDR 0x01160002L
+#define IBU_P1_PMA_PLLB_CSR_STRIDE 1
+#define IBU_P1_PMA_PLLB_CSR_DEPTH 1
+
+#define IBU_P1_PMA_CMODE_CSR_ADDR 0x01160003L
+#define IBU_P1_PMA_CMODE_CSR_STRIDE 1
+#define IBU_P1_PMA_CMODE_CSR_DEPTH 1
+
+#define IBU_P1_PMA_LB_CSR_ADDR 0x01160004L
+#define IBU_P1_PMA_LB_CSR_STRIDE 1
+#define IBU_P1_PMA_LB_CSR_DEPTH 1
+
+#define IBU_P1_PMA_PWR_CSR_ADDR 0x01160005L
+#define IBU_P1_PMA_PWR_CSR_STRIDE 1
+#define IBU_P1_PMA_PWR_CSR_DEPTH 1
+
+#define IBU_P1_PMA_STATUS0_CSR_ADDR 0x01160006L
+#define IBU_P1_PMA_STATUS0_CSR_STRIDE 1
+#define IBU_P1_PMA_STATUS0_CSR_DEPTH 1
+
+#define IBU_P1_PMA_STATUS1_CSR_ADDR 0x01160007L
+#define IBU_P1_PMA_STATUS1_CSR_STRIDE 1
+#define IBU_P1_PMA_STATUS1_CSR_DEPTH 1
+
+#define IBU_P1_PMA_STATUS2_CSR_ADDR 0x01160008L
+#define IBU_P1_PMA_STATUS2_CSR_STRIDE 1
+#define IBU_P1_PMA_STATUS2_CSR_DEPTH 1
+
+#define IBU_P1_PMA_TXWCLK0_CNT_CSR_ADDR 0x01160009L
+#define IBU_P1_PMA_TXWCLK0_CNT_CSR_STRIDE 1
+#define IBU_P1_PMA_TXWCLK0_CNT_CSR_DEPTH 1
+
+#define IBU_P1_PMA_TXWCLK0_CNT_VAL_ADDR 0x0116000aL
+#define IBU_P1_PMA_TXWCLK0_CNT_VAL_STRIDE 1
+#define IBU_P1_PMA_TXWCLK0_CNT_VAL_DEPTH 1
+
+#define IBU_P1_PMA_RXWCLK0_CNT_CSR_ADDR 0x0116000bL
+#define IBU_P1_PMA_RXWCLK0_CNT_CSR_STRIDE 1
+#define IBU_P1_PMA_RXWCLK0_CNT_CSR_DEPTH 1
+
+#define IBU_P1_PMA_RXWCLK0_CNT_VAL_ADDR 0x0116000cL
+#define IBU_P1_PMA_RXWCLK0_CNT_VAL_STRIDE 1
+#define IBU_P1_PMA_RXWCLK0_CNT_VAL_DEPTH 1
+
+#define IBU_P1_PMA_IRQ_STATUS_CSR_ADDR 0x0116000dL
+#define IBU_P1_PMA_IRQ_STATUS_CSR_STRIDE 1
+#define IBU_P1_PMA_IRQ_STATUS_CSR_DEPTH 1
+
+#define IBU_P1_PMA_IRQ_MASK_CSR_ADDR 0x0116000eL
+#define IBU_P1_PMA_IRQ_MASK_CSR_STRIDE 1
+#define IBU_P1_PMA_IRQ_MASK_CSR_DEPTH 1
+
+#define IBU_P1_PMA_BAD_CSR_ADDR 0x0116fbadL
+#define IBU_P1_PMA_BAD_CSR_STRIDE 1
+#define IBU_P1_PMA_BAD_CSR_DEPTH 1
+
+#define IBU_P2_CNT1US_CNT124US_ADDR 0x01180001L
+#define IBU_P2_CNT1US_CNT124US_STRIDE 1
+#define IBU_P2_CNT1US_CNT124US_DEPTH 1
+
+#define IBU_P2_CNT2MS_ADDR 0x01180002L
+#define IBU_P2_CNT2MS_STRIDE 1
+#define IBU_P2_CNT2MS_DEPTH 1
+
+#define IBU_P2_CNT10MS_ADDR 0x01180003L
+#define IBU_P2_CNT10MS_STRIDE 1
+#define IBU_P2_CNT10MS_DEPTH 1
+
+#define IBU_P2_CNT100MS_ADDR 0x01180004L
+#define IBU_P2_CNT100MS_STRIDE 1
+#define IBU_P2_CNT100MS_DEPTH 1
+
+#define IBU_P2_CNT150MS_ADDR 0x01180005L
+#define IBU_P2_CNT150MS_STRIDE 1
+#define IBU_P2_CNT150MS_DEPTH 1
+
+#define IBU_P2_CNT400MS_ADDR 0x01180006L
+#define IBU_P2_CNT400MS_STRIDE 1
+#define IBU_P2_CNT400MS_DEPTH 1
+
+#define IBU_P2_SKP_TO_CNT_ADDR 0x01180007L
+#define IBU_P2_SKP_TO_CNT_STRIDE 1
+#define IBU_P2_SKP_TO_CNT_DEPTH 1
+
+#define IBU_P2_TGT_VAL_ADDR 0x01180008L
+#define IBU_P2_TGT_VAL_STRIDE 1
+#define IBU_P2_TGT_VAL_DEPTH 1
+
+#define IBU_P2_PHY_VCONFIG_ADDR 0x01180009L
+#define IBU_P2_PHY_VCONFIG_STRIDE 1
+#define IBU_P2_PHY_VCONFIG_DEPTH 1
+
+#define IBU_P2_PHY_DISP_ERROR_CNT_ADDR 0x0118000aL
+#define IBU_P2_PHY_DISP_ERROR_CNT_STRIDE 1
+#define IBU_P2_PHY_DISP_ERROR_CNT_DEPTH 1
+
+#define IBU_P2_PHY_CODE_ERROR_CNT_ADDR 0x0118000bL
+#define IBU_P2_PHY_CODE_ERROR_CNT_STRIDE 1
+#define IBU_P2_PHY_CODE_ERROR_CNT_DEPTH 1
+
+#define IBU_P2_PHY_EVENT_LOG_ADDR 0x0118000cL
+#define IBU_P2_PHY_EVENT_LOG_STRIDE 1
+#define IBU_P2_PHY_EVENT_LOG_DEPTH 1
+
+#define IBU_P2_PORT_TRAIN_FSM_ADDR 0x0118000dL
+#define IBU_P2_PORT_TRAIN_FSM_STRIDE 1
+#define IBU_P2_PORT_TRAIN_FSM_DEPTH 1
+
+#define IBU_P2_PHY_TRAIN_SMTIMER_VS1_ADDR 0x0118000eL
+#define IBU_P2_PHY_TRAIN_SMTIMER_VS1_STRIDE 1
+#define IBU_P2_PHY_TRAIN_SMTIMER_VS1_DEPTH 1
+
+#define IBU_P2_MASK_ADDR 0x0118000fL
+#define IBU_P2_MASK_STRIDE 1
+#define IBU_P2_MASK_DEPTH 1
+
+#define IBU_P2_STATUS_ADDR 0x01180010L
+#define IBU_P2_STATUS_STRIDE 1
+#define IBU_P2_STATUS_DEPTH 1
+
+#define IBU_P2_LINK_WIDTH_ENABLED_ADDR 0x01180011L
+#define IBU_P2_LINK_WIDTH_ENABLED_STRIDE 1
+#define IBU_P2_LINK_WIDTH_ENABLED_DEPTH 1
+
+#define IBU_P2_LINK_WIDTH_SUPPORTED_ADDR 0x01180012L
+#define IBU_P2_LINK_WIDTH_SUPPORTED_STRIDE 1
+#define IBU_P2_LINK_WIDTH_SUPPORTED_DEPTH 1
+
+#define IBU_P2_LINK_WIDTH_ACTIVE_ADDR 0x01180013L
+#define IBU_P2_LINK_WIDTH_ACTIVE_STRIDE 1
+#define IBU_P2_LINK_WIDTH_ACTIVE_DEPTH 1
+
+#define IBU_P2_LINK_SPEED_SUPPORTED_ADDR 0x01180014L
+#define IBU_P2_LINK_SPEED_SUPPORTED_STRIDE 1
+#define IBU_P2_LINK_SPEED_SUPPORTED_DEPTH 1
+
+#define IBU_P2_PORT_PHYSICAL_STATE_ADDR 0x01180015L
+#define IBU_P2_PORT_PHYSICAL_STATE_STRIDE 1
+#define IBU_P2_PORT_PHYSICAL_STATE_DEPTH 1
+
+#define IBU_P2_LINK_DOWN_DEFAULT_STATE_ADDR 0x01180016L
+#define IBU_P2_LINK_DOWN_DEFAULT_STATE_STRIDE 1
+#define IBU_P2_LINK_DOWN_DEFAULT_STATE_DEPTH 1
+
+#define IBU_P2_LINK_SPEED_ACTIVE_ADDR 0x01180017L
+#define IBU_P2_LINK_SPEED_ACTIVE_STRIDE 1
+#define IBU_P2_LINK_SPEED_ACTIVE_DEPTH 1
+
+#define IBU_P2_LINK_SPEED_ENABLED_ADDR 0x01180018L
+#define IBU_P2_LINK_SPEED_ENABLED_STRIDE 1
+#define IBU_P2_LINK_SPEED_ENABLED_DEPTH 1
+
+#define IBU_P2_PCPHY_CNT_RST_ADDR 0x01180019L
+#define IBU_P2_PCPHY_CNT_RST_STRIDE 1
+#define IBU_P2_PCPHY_CNT_RST_DEPTH 1
+
+#define IBU_P2_PCPHY_CNT_LOAD_ADDR 0x0118001aL
+#define IBU_P2_PCPHY_CNT_LOAD_STRIDE 1
+#define IBU_P2_PCPHY_CNT_LOAD_DEPTH 1
+
+#define IBU_P2_PCSYMB_ERR_CNT_ADDR 0x0118001bL
+#define IBU_P2_PCSYMB_ERR_CNT_STRIDE 1
+#define IBU_P2_PCSYMB_ERR_CNT_DEPTH 1
+
+#define IBU_P2_PCLINK_ERR_REC_CNT_ADDR 0x0118001cL
+#define IBU_P2_PCLINK_ERR_REC_CNT_STRIDE 1
+#define IBU_P2_PCLINK_ERR_REC_CNT_DEPTH 1
+
+#define IBU_P2_PCLINK_DOWNED_CNT_ADDR 0x0118001dL
+#define IBU_P2_PCLINK_DOWNED_CNT_STRIDE 1
+#define IBU_P2_PCLINK_DOWNED_CNT_DEPTH 1
+
+#define IBU_P2_PCSYMB_ERR_CNT_LANE0_ADDR 0x0118001eL
+#define IBU_P2_PCSYMB_ERR_CNT_LANE0_STRIDE 1
+#define IBU_P2_PCSYMB_ERR_CNT_LANE0_DEPTH 1
+
+#define IBU_P2_PCSYMB_ERR_CNT_LANE1_ADDR 0x0118001fL
+#define IBU_P2_PCSYMB_ERR_CNT_LANE1_STRIDE 1
+#define IBU_P2_PCSYMB_ERR_CNT_LANE1_DEPTH 1
+
+#define IBU_P2_PCSYMB_ERR_CNT_LANE2_ADDR 0x01180020L
+#define IBU_P2_PCSYMB_ERR_CNT_LANE2_STRIDE 1
+#define IBU_P2_PCSYMB_ERR_CNT_LANE2_DEPTH 1
+
+#define IBU_P2_PCSYMB_ERR_CNT_LANE3_ADDR 0x01180021L
+#define IBU_P2_PCSYMB_ERR_CNT_LANE3_STRIDE 1
+#define IBU_P2_PCSYMB_ERR_CNT_LANE3_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT0_COUNTER_ADDR 0x01180022L
+#define IBU_P2_TS3_REV1_TT0_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT0_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT1_COUNTER_ADDR 0x01180023L
+#define IBU_P2_TS3_REV1_TT1_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT1_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT2_COUNTER_ADDR 0x01180024L
+#define IBU_P2_TS3_REV1_TT2_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT2_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT3_COUNTER_ADDR 0x01180025L
+#define IBU_P2_TS3_REV1_TT3_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT3_COUNTER_DEPTH 1
+
+#define IBU_P2_PHY_ALIGN_ERROR_CNT_ADDR 0x01180026L
+#define IBU_P2_PHY_ALIGN_ERROR_CNT_STRIDE 1
+#define IBU_P2_PHY_ALIGN_ERROR_CNT_DEPTH 1
+
+#define IBU_P2_PHY_CNTRL_IN_PKT_ERROR_CNT_ADDR 0x01180027L
+#define IBU_P2_PHY_CNTRL_IN_PKT_ERROR_CNT_STRIDE 1
+#define IBU_P2_PHY_CNTRL_IN_PKT_ERROR_CNT_DEPTH 1
+
+#define IBU_P2_PHY_PAD_ERROR_CNT_ADDR 0x01180028L
+#define IBU_P2_PHY_PAD_ERROR_CNT_STRIDE 1
+#define IBU_P2_PHY_PAD_ERROR_CNT_DEPTH 1
+
+#define IBU_P2_PHY_EDR_FDR_CONFIG0_ADDR 0x01180029L
+#define IBU_P2_PHY_EDR_FDR_CONFIG0_STRIDE 1
+#define IBU_P2_PHY_EDR_FDR_CONFIG0_DEPTH 1
+
+#define IBU_P2_PHY_EDR_FDR_CONFIG1_ADDR 0x0118002aL
+#define IBU_P2_PHY_EDR_FDR_CONFIG1_STRIDE 1
+#define IBU_P2_PHY_EDR_FDR_CONFIG1_DEPTH 1
+
+#define IBU_P2_PHY_LEAKY_BKT_THRSH_ADDR 0x0118002bL
+#define IBU_P2_PHY_LEAKY_BKT_THRSH_STRIDE 1
+#define IBU_P2_PHY_LEAKY_BKT_THRSH_DEPTH 1
+
+#define IBU_P2_RCV_TS3_STATUS_LOW_ADDR 0x0118002dL
+#define IBU_P2_RCV_TS3_STATUS_LOW_STRIDE 1
+#define IBU_P2_RCV_TS3_STATUS_LOW_DEPTH 1
+
+#define IBU_P2_RCV_TS3_STATUS_HIGH_ADDR 0x0118002eL
+#define IBU_P2_RCV_TS3_STATUS_HIGH_STRIDE 1
+#define IBU_P2_RCV_TS3_STATUS_HIGH_DEPTH 1
+
+#define IBU_P2_GUID0_ADDR 0x0118002fL
+#define IBU_P2_GUID0_STRIDE 1
+#define IBU_P2_GUID0_DEPTH 1
+
+#define IBU_P2_GUID1_ADDR 0x01180030L
+#define IBU_P2_GUID1_STRIDE 1
+#define IBU_P2_GUID1_DEPTH 1
+
+#define IBU_P2_PNUM_ADDR 0x01180031L
+#define IBU_P2_PNUM_STRIDE 1
+#define IBU_P2_PNUM_DEPTH 1
+
+#define IBU_P2_CNT4MS_ADDR 0x01180032L
+#define IBU_P2_CNT4MS_STRIDE 1
+#define IBU_P2_CNT4MS_DEPTH 1
+
+#define IBU_P2_CNT36MS_ADDR 0x01180033L
+#define IBU_P2_CNT36MS_STRIDE 1
+#define IBU_P2_CNT36MS_DEPTH 1
+
+#define IBU_P2_PHY_TS3_CONFIG_ADDR 0x01180034L
+#define IBU_P2_PHY_TS3_CONFIG_STRIDE 1
+#define IBU_P2_PHY_TS3_CONFIG_DEPTH 1
+
+#define IBU_P2_DDS_WINDOW_START_ADDR 0x01180035L
+#define IBU_P2_DDS_WINDOW_START_STRIDE 1
+#define IBU_P2_DDS_WINDOW_START_DEPTH 1
+
+#define IBU_P2_DDS_WINDOW_END_ADDR 0x01180036L
+#define IBU_P2_DDS_WINDOW_END_STRIDE 1
+#define IBU_P2_DDS_WINDOW_END_DEPTH 1
+
+#define IBU_P2_DDS_DEFAULT_WINDOW_END_ADDR 0x01180037L
+#define IBU_P2_DDS_DEFAULT_WINDOW_END_STRIDE 1
+#define IBU_P2_DDS_DEFAULT_WINDOW_END_DEPTH 1
+
+#define IBU_P2_RX_TS3DDS_STATUS_ADDR 0x01180038L
+#define IBU_P2_RX_TS3DDS_STATUS_STRIDE 1
+#define IBU_P2_RX_TS3DDS_STATUS_DEPTH 1
+
+#define IBU_P2_TX_TS3DDS_STATUS_ADDR 0x01180039L
+#define IBU_P2_TX_TS3DDS_STATUS_STRIDE 1
+#define IBU_P2_TX_TS3DDS_STATUS_DEPTH 1
+
+#define IBU_P2_CNT16MS_ADDR 0x0118003aL
+#define IBU_P2_CNT16MS_STRIDE 1
+#define IBU_P2_CNT16MS_DEPTH 1
+
+#define IBU_P2_CONF_TEST4MS_SCT_ADDR 0x0118003bL
+#define IBU_P2_CONF_TEST4MS_SCT_STRIDE 1
+#define IBU_P2_CONF_TEST4MS_SCT_DEPTH 1
+
+#define IBU_P2_CONF_TEST16MS_SCT_ADDR 0x0118003cL
+#define IBU_P2_CONF_TEST16MS_SCT_STRIDE 1
+#define IBU_P2_CONF_TEST16MS_SCT_DEPTH 1
+
+#define IBU_P2_LOCAL_ADDTEST_LIMIT_ADDR 0x0118003dL
+#define IBU_P2_LOCAL_ADDTEST_LIMIT_STRIDE 1
+#define IBU_P2_LOCAL_ADDTEST_LIMIT_DEPTH 1
+
+#define IBU_P2_REMOTE_ADDTEST_LIMIT_ADDR 0x0118003eL
+#define IBU_P2_REMOTE_ADDTEST_LIMIT_STRIDE 1
+#define IBU_P2_REMOTE_ADDTEST_LIMIT_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT4_COUNTER_ADDR 0x0118003fL
+#define IBU_P2_TS3_REV1_TT4_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT4_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT5_COUNTER_ADDR 0x01180040L
+#define IBU_P2_TS3_REV1_TT5_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT5_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT6_COUNTER_ADDR 0x01180041L
+#define IBU_P2_TS3_REV1_TT6_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT6_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT7_COUNTER_ADDR 0x01180042L
+#define IBU_P2_TS3_REV1_TT7_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT7_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT8_COUNTER_ADDR 0x01180043L
+#define IBU_P2_TS3_REV1_TT8_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT8_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT9_COUNTER_ADDR 0x01180044L
+#define IBU_P2_TS3_REV1_TT9_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT9_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT10_COUNTER_ADDR 0x01180045L
+#define IBU_P2_TS3_REV1_TT10_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT10_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT11_COUNTER_ADDR 0x01180046L
+#define IBU_P2_TS3_REV1_TT11_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT11_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT12_COUNTER_ADDR 0x01180047L
+#define IBU_P2_TS3_REV1_TT12_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT12_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT13_COUNTER_ADDR 0x01180048L
+#define IBU_P2_TS3_REV1_TT13_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT13_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT14_COUNTER_ADDR 0x01180049L
+#define IBU_P2_TS3_REV1_TT14_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT14_COUNTER_DEPTH 1
+
+#define IBU_P2_TS3_REV1_TT15_COUNTER_ADDR 0x0118004aL
+#define IBU_P2_TS3_REV1_TT15_COUNTER_STRIDE 1
+#define IBU_P2_TS3_REV1_TT15_COUNTER_DEPTH 1
+
+#define IBU_P2_CONF_TEST_LANE_ERROR_LIMIT_ADDR 0x0118004bL
+#define IBU_P2_CONF_TEST_LANE_ERROR_LIMIT_STRIDE 1
+#define IBU_P2_CONF_TEST_LANE_ERROR_LIMIT_DEPTH 1
+
+#define IBU_P2_CONF_TEST_IDLE_LIMIT_ADDR 0x0118004cL
+#define IBU_P2_CONF_TEST_IDLE_LIMIT_STRIDE 1
+#define IBU_P2_CONF_TEST_IDLE_LIMIT_DEPTH 1
+
+#define IBU_P2_CONF_TEST2MS_SCT_ADDR 0x0118004dL
+#define IBU_P2_CONF_TEST2MS_SCT_STRIDE 1
+#define IBU_P2_CONF_TEST2MS_SCT_DEPTH 1
+
+#define IBU_P2_CNT100_MS_HBR_ADDR 0x0118004eL
+#define IBU_P2_CNT100_MS_HBR_STRIDE 1
+#define IBU_P2_CNT100_MS_HBR_DEPTH 1
+
+#define IBU_P2_PMAEQULANE0_STATUS_ADDR 0x0118004fL
+#define IBU_P2_PMAEQULANE0_STATUS_STRIDE 1
+#define IBU_P2_PMAEQULANE0_STATUS_DEPTH 1
+
+#define IBU_P2_PMAEQULANE1_STATUS_ADDR 0x01180050L
+#define IBU_P2_PMAEQULANE1_STATUS_STRIDE 1
+#define IBU_P2_PMAEQULANE1_STATUS_DEPTH 1
+
+#define IBU_P2_PMAEQULANE2_STATUS_ADDR 0x01180051L
+#define IBU_P2_PMAEQULANE2_STATUS_STRIDE 1
+#define IBU_P2_PMAEQULANE2_STATUS_DEPTH 1
+
+#define IBU_P2_PMAEQULANE3_STATUS_ADDR 0x01180052L
+#define IBU_P2_PMAEQULANE3_STATUS_STRIDE 1
+#define IBU_P2_PMAEQULANE3_STATUS_DEPTH 1
+
+#define IBU_P2_PMADDSLANE0_STATUS_ADDR 0x01180053L
+#define IBU_P2_PMADDSLANE0_STATUS_STRIDE 1
+#define IBU_P2_PMADDSLANE0_STATUS_DEPTH 1
+
+#define IBU_P2_PMADDSLANE1_STATUS_ADDR 0x01180054L
+#define IBU_P2_PMADDSLANE1_STATUS_STRIDE 1
+#define IBU_P2_PMADDSLANE1_STATUS_DEPTH 1
+
+#define IBU_P2_PMADDSLANE2_STATUS_ADDR 0x01180055L
+#define IBU_P2_PMADDSLANE2_STATUS_STRIDE 1
+#define IBU_P2_PMADDSLANE2_STATUS_DEPTH 1
+
+#define IBU_P2_PMADDSLANE3_STATUS_ADDR 0x01180056L
+#define IBU_P2_PMADDSLANE3_STATUS_STRIDE 1
+#define IBU_P2_PMADDSLANE3_STATUS_DEPTH 1
+
+#define IBU_P2_PHY_EDPL_ERR0_ADDR 0x01180057L
+#define IBU_P2_PHY_EDPL_ERR0_STRIDE 1
+#define IBU_P2_PHY_EDPL_ERR0_DEPTH 1
+
+#define IBU_P2_PHY_EDPL_ERR1_ADDR 0x01180058L
+#define IBU_P2_PHY_EDPL_ERR1_STRIDE 1
+#define IBU_P2_PHY_EDPL_ERR1_DEPTH 1
+
+#define IBU_P2_PHY_EDPL_ERR2_ADDR 0x01180059L
+#define IBU_P2_PHY_EDPL_ERR2_STRIDE 1
+#define IBU_P2_PHY_EDPL_ERR2_DEPTH 1
+
+#define IBU_P2_PHY_EDPL_ERR3_ADDR 0x0118005aL
+#define IBU_P2_PHY_EDPL_ERR3_STRIDE 1
+#define IBU_P2_PHY_EDPL_ERR3_DEPTH 1
+
+#define IBU_P2_PHY_BLK_TYPE_ERR_ADDR 0x0118005bL
+#define IBU_P2_PHY_BLK_TYPE_ERR_STRIDE 1
+#define IBU_P2_PHY_BLK_TYPE_ERR_DEPTH 1
+
+#define IBU_P2_PHY_BLK_EOP_ERR_ADDR 0x0118005cL
+#define IBU_P2_PHY_BLK_EOP_ERR_STRIDE 1
+#define IBU_P2_PHY_BLK_EOP_ERR_DEPTH 1
+
+#define IBU_P2_PHY_CIN_PKT_ERR_ADDR 0x0118005dL
+#define IBU_P2_PHY_CIN_PKT_ERR_STRIDE 1
+#define IBU_P2_PHY_CIN_PKT_ERR_DEPTH 1
+
+#define IBU_P2_PHY_SYN_HDR_ERR_ADDR 0x0118005eL
+#define IBU_P2_PHY_SYN_HDR_ERR_STRIDE 1
+#define IBU_P2_PHY_SYN_HDR_ERR_DEPTH 1
+
+#define IBU_P2_PHY_PRBS_ERR0_ADDR 0x0118005fL
+#define IBU_P2_PHY_PRBS_ERR0_STRIDE 1
+#define IBU_P2_PHY_PRBS_ERR0_DEPTH 1
+
+#define IBU_P2_PHY_PRBS_ERR1_ADDR 0x01180060L
+#define IBU_P2_PHY_PRBS_ERR1_STRIDE 1
+#define IBU_P2_PHY_PRBS_ERR1_DEPTH 1
+
+#define IBU_P2_PHY_PRBS_ERR2_ADDR 0x01180061L
+#define IBU_P2_PHY_PRBS_ERR2_STRIDE 1
+#define IBU_P2_PHY_PRBS_ERR2_DEPTH 1
+
+#define IBU_P2_PHY_PRBS_ERR3_ADDR 0x01180062L
+#define IBU_P2_PHY_PRBS_ERR3_STRIDE 1
+#define IBU_P2_PHY_PRBS_ERR3_DEPTH 1
+
+#define IBU_P2_PHY_DESKEW_STATUS_ADDR 0x01180063L
+#define IBU_P2_PHY_DESKEW_STATUS_STRIDE 1
+#define IBU_P2_PHY_DESKEW_STATUS_DEPTH 1
+
+#define IBU_P2_PHY_FECUNC_ERR0_ADDR 0x01180064L
+#define IBU_P2_PHY_FECUNC_ERR0_STRIDE 1
+#define IBU_P2_PHY_FECUNC_ERR0_DEPTH 1
+
+#define IBU_P2_PHY_FECUNC_ERR1_ADDR 0x01180065L
+#define IBU_P2_PHY_FECUNC_ERR1_STRIDE 1
+#define IBU_P2_PHY_FECUNC_ERR1_DEPTH 1
+
+#define IBU_P2_PHY_FECUNC_ERR2_ADDR 0x01180066L
+#define IBU_P2_PHY_FECUNC_ERR2_STRIDE 1
+#define IBU_P2_PHY_FECUNC_ERR2_DEPTH 1
+
+#define IBU_P2_PHY_FECUNC_ERR3_ADDR 0x01180067L
+#define IBU_P2_PHY_FECUNC_ERR3_STRIDE 1
+#define IBU_P2_PHY_FECUNC_ERR3_DEPTH 1
+
+#define IBU_P2_PHY_FECCOR_ERR0_ADDR 0x01180068L
+#define IBU_P2_PHY_FECCOR_ERR0_STRIDE 1
+#define IBU_P2_PHY_FECCOR_ERR0_DEPTH 1
+
+#define IBU_P2_PHY_FECCOR_ERR1_ADDR 0x01180069L
+#define IBU_P2_PHY_FECCOR_ERR1_STRIDE 1
+#define IBU_P2_PHY_FECCOR_ERR1_DEPTH 1
+
+#define IBU_P2_PHY_FECCOR_ERR2_ADDR 0x0118006aL
+#define IBU_P2_PHY_FECCOR_ERR2_STRIDE 1
+#define IBU_P2_PHY_FECCOR_ERR2_DEPTH 1
+
+#define IBU_P2_PHY_FECCOR_ERR3_ADDR 0x0118006bL
+#define IBU_P2_PHY_FECCOR_ERR3_STRIDE 1
+#define IBU_P2_PHY_FECCOR_ERR3_DEPTH 1
+
+#define IBU_P2_PHY_SMSTATUS_ADDR 0x0118006cL
+#define IBU_P2_PHY_SMSTATUS_STRIDE 1
+#define IBU_P2_PHY_SMSTATUS_DEPTH 1
+
+#define IBU_P2_PHY_TS3_NEGOTIATED_STATUS_ADDR 0x0118006dL
+#define IBU_P2_PHY_TS3_NEGOTIATED_STATUS_STRIDE 1
+#define IBU_P2_PHY_TS3_NEGOTIATED_STATUS_DEPTH 1
+
+#define IBU_P2_PHY_TEST_ADDR 0x0118006eL
+#define IBU_P2_PHY_TEST_STRIDE 1
+#define IBU_P2_PHY_TEST_DEPTH 1
+
+#define IBU_P2_EDR_FDR_RX_STATUS_REG0_ADDR 0x0118006fL
+#define IBU_P2_EDR_FDR_RX_STATUS_REG0_STRIDE 1
+#define IBU_P2_EDR_FDR_RX_STATUS_REG0_DEPTH 1
+
+#define IBU_P2_EDR_FDR_RX_STATUS_REG1_ADDR 0x01180070L
+#define IBU_P2_EDR_FDR_RX_STATUS_REG1_STRIDE 1
+#define IBU_P2_EDR_FDR_RX_STATUS_REG1_DEPTH 1
+
+#define IBU_P2_EDR_FDR_RX_STATUS_REG2_ADDR 0x01180071L
+#define IBU_P2_EDR_FDR_RX_STATUS_REG2_STRIDE 1
+#define IBU_P2_EDR_FDR_RX_STATUS_REG2_DEPTH 1
+
+#define IBU_P2_EDR_FDR_TX_STATUS_REG0_ADDR 0x01180072L
+#define IBU_P2_EDR_FDR_TX_STATUS_REG0_STRIDE 1
+#define IBU_P2_EDR_FDR_TX_STATUS_REG0_DEPTH 1
+
+#define IBU_P2_INT_PRIORITY_ADDR 0x01180073L
+#define IBU_P2_INT_PRIORITY_STRIDE 1
+#define IBU_P2_INT_PRIORITY_DEPTH 1
+
+#define IBU_P2_INT_FATAL_ADDR 0x01180074L
+#define IBU_P2_INT_FATAL_STRIDE 1
+#define IBU_P2_INT_FATAL_DEPTH 1
+
+#define IBU_P2_LINK_ROUND_TRIP_LATENCY_ADDR 0x01180075L
+#define IBU_P2_LINK_ROUND_TRIP_LATENCY_STRIDE 1
+#define IBU_P2_LINK_ROUND_TRIP_LATENCY_DEPTH 1
+
+#define IBU_P2_PHY_FORCE_LEGACY_MODE_ADDR 0x01180076L
+#define IBU_P2_PHY_FORCE_LEGACY_MODE_STRIDE 1
+#define IBU_P2_PHY_FORCE_LEGACY_MODE_DEPTH 1
+
+#define IBU_P2_SERDES_BYPASS_ADDR 0x01180077L
+#define IBU_P2_SERDES_BYPASS_STRIDE 1
+#define IBU_P2_SERDES_BYPASS_DEPTH 1
+
+#define IBU_P2_LID_ADDR 0x01180100L
+#define IBU_P2_LID_STRIDE 1
+#define IBU_P2_LID_DEPTH 1
+
+#define IBU_P2_LMC_ADDR 0x01180101L
+#define IBU_P2_LMC_STRIDE 1
+#define IBU_P2_LMC_DEPTH 1
+
+#define IBU_P2_PORT_STATE_ADDR 0x01180102L
+#define IBU_P2_PORT_STATE_STRIDE 1
+#define IBU_P2_PORT_STATE_DEPTH 1
+
+#define IBU_P2_VLCAP_ADDR 0x01180103L
+#define IBU_P2_VLCAP_STRIDE 1
+#define IBU_P2_VLCAP_DEPTH 1
+
+#define IBU_P2_NEIGHBOR_MTU_ADDR 0x01180104L
+#define IBU_P2_NEIGHBOR_MTU_STRIDE 1
+#define IBU_P2_NEIGHBOR_MTU_DEPTH 1
+
+#define IBU_P2_VLHIGH_LIMIT_ADDR 0x01180105L
+#define IBU_P2_VLHIGH_LIMIT_STRIDE 1
+#define IBU_P2_VLHIGH_LIMIT_DEPTH 1
+
+#define IBU_P2_VLARBITRATION_HIGH_CAP_ADDR 0x01180106L
+#define IBU_P2_VLARBITRATION_HIGH_CAP_STRIDE 1
+#define IBU_P2_VLARBITRATION_HIGH_CAP_DEPTH 1
+
+#define IBU_P2_VLARBITRATION_LOW_CAP_ADDR 0x01180107L
+#define IBU_P2_VLARBITRATION_LOW_CAP_STRIDE 1
+#define IBU_P2_VLARBITRATION_LOW_CAP_DEPTH 1
+
+#define IBU_P2_MTUCAP_ADDR 0x01180108L
+#define IBU_P2_MTUCAP_STRIDE 1
+#define IBU_P2_MTUCAP_DEPTH 1
+
+#define IBU_P2_OPERATIONAL_VLS_ADDR 0x01180109L
+#define IBU_P2_OPERATIONAL_VLS_STRIDE 1
+#define IBU_P2_OPERATIONAL_VLS_DEPTH 1
+
+#define IBU_P2_PCPORT_RCV_ERROR_ADDR 0x0118010cL
+#define IBU_P2_PCPORT_RCV_ERROR_STRIDE 1
+#define IBU_P2_PCPORT_RCV_ERROR_DEPTH 1
+
+#define IBU_P2_PCPORT_RCV_REMOTE_PHYSICAL_ERRORS_ADDR 0x0118010dL
+#define IBU_P2_PCPORT_RCV_REMOTE_PHYSICAL_ERRORS_STRIDE 1
+#define IBU_P2_PCPORT_RCV_REMOTE_PHYSICAL_ERRORS_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_DISCARDS_ADDR 0x0118010eL
+#define IBU_P2_PCPORT_XMIT_DISCARDS_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_DISCARDS_DEPTH 1
+
+#define IBU_P2_PCLOCAL_LINK_INTEGRITY_ERRORS_ADDR 0x0118010fL
+#define IBU_P2_PCLOCAL_LINK_INTEGRITY_ERRORS_STRIDE 1
+#define IBU_P2_PCLOCAL_LINK_INTEGRITY_ERRORS_DEPTH 1
+
+#define IBU_P2_PCEXCESSIVE_BUFFER_OVERRUN_ERRORS_ADDR 0x01180110L
+#define IBU_P2_PCEXCESSIVE_BUFFER_OVERRUN_ERRORS_STRIDE 1
+#define IBU_P2_PCEXCESSIVE_BUFFER_OVERRUN_ERRORS_DEPTH 1
+
+#define IBU_P2_PCVL15_DROPPED_ADDR 0x01180111L
+#define IBU_P2_PCVL15_DROPPED_STRIDE 1
+#define IBU_P2_PCVL15_DROPPED_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_WAIT_ADDR 0x01180112L
+#define IBU_P2_PCPORT_XMIT_WAIT_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_WAIT_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_DATA_LSQW_ADDR 0x01180113L
+#define IBU_P2_PCPORT_XMIT_DATA_LSQW_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_DATA_LSQW_DEPTH 1
+
+#define IBU_P2_LINK_ERROR_CHECK_ENABLE_ADDR 0x01180114L
+#define IBU_P2_LINK_ERROR_CHECK_ENABLE_STRIDE 1
+#define IBU_P2_LINK_ERROR_CHECK_ENABLE_DEPTH 1
+
+#define IBU_P2_PCPORT_RCV_DATA_LSQW_ADDR 0x01180115L
+#define IBU_P2_PCPORT_RCV_DATA_LSQW_STRIDE 1
+#define IBU_P2_PCPORT_RCV_DATA_LSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_RCV_DATA_HSQW_ADDR 0x01180116L
+#define IBU_P2_PCPORT_RCV_DATA_HSQW_STRIDE 1
+#define IBU_P2_PCPORT_RCV_DATA_HSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_PKTS_LSQW_ADDR 0x01180117L
+#define IBU_P2_PCPORT_XMIT_PKTS_LSQW_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_PKTS_LSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_PKTS_HSQW_ADDR 0x01180118L
+#define IBU_P2_PCPORT_XMIT_PKTS_HSQW_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_PKTS_HSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_RCV_PKTS_LSQW_ADDR 0x01180119L
+#define IBU_P2_PCPORT_RCV_PKTS_LSQW_STRIDE 1
+#define IBU_P2_PCPORT_RCV_PKTS_LSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_RCV_PKTS_HSQW_ADDR 0x0118011aL
+#define IBU_P2_PCPORT_RCV_PKTS_HSQW_STRIDE 1
+#define IBU_P2_PCPORT_RCV_PKTS_HSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_UCXMIT_PKTS_LSQW_ADDR 0x0118011bL
+#define IBU_P2_PCPORT_UCXMIT_PKTS_LSQW_STRIDE 1
+#define IBU_P2_PCPORT_UCXMIT_PKTS_LSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_UCXMIT_PKTS_HSQW_ADDR 0x0118011cL
+#define IBU_P2_PCPORT_UCXMIT_PKTS_HSQW_STRIDE 1
+#define IBU_P2_PCPORT_UCXMIT_PKTS_HSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_MCXMIT_PKTS_LSQW_ADDR 0x0118011dL
+#define IBU_P2_PCPORT_MCXMIT_PKTS_LSQW_STRIDE 1
+#define IBU_P2_PCPORT_MCXMIT_PKTS_LSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_MCXMIT_PKTS_HSQW_ADDR 0x0118011eL
+#define IBU_P2_PCPORT_MCXMIT_PKTS_HSQW_STRIDE 1
+#define IBU_P2_PCPORT_MCXMIT_PKTS_HSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_UCRCV_PKTS_LSQW_ADDR 0x0118011fL
+#define IBU_P2_PCPORT_UCRCV_PKTS_LSQW_STRIDE 1
+#define IBU_P2_PCPORT_UCRCV_PKTS_LSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_UCRCV_PKTS_HSQW_ADDR 0x01180120L
+#define IBU_P2_PCPORT_UCRCV_PKTS_HSQW_STRIDE 1
+#define IBU_P2_PCPORT_UCRCV_PKTS_HSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_MCRCV_PKTS_LSQW_ADDR 0x01180121L
+#define IBU_P2_PCPORT_MCRCV_PKTS_LSQW_STRIDE 1
+#define IBU_P2_PCPORT_MCRCV_PKTS_LSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_MCRCV_PKTS_HSQW_ADDR 0x01180122L
+#define IBU_P2_PCPORT_MCRCV_PKTS_HSQW_STRIDE 1
+#define IBU_P2_PCPORT_MCRCV_PKTS_HSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_WAIT_VL0_ADDR 0x01180123L
+#define IBU_P2_PCPORT_XMIT_WAIT_VL0_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_WAIT_VL0_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_WAIT_VL1_ADDR 0x01180124L
+#define IBU_P2_PCPORT_XMIT_WAIT_VL1_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_WAIT_VL1_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_WAIT_VL2_ADDR 0x01180125L
+#define IBU_P2_PCPORT_XMIT_WAIT_VL2_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_WAIT_VL2_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_WAIT_VL3_ADDR 0x01180126L
+#define IBU_P2_PCPORT_XMIT_WAIT_VL3_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_WAIT_VL3_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_WAIT_VL4_ADDR 0x01180127L
+#define IBU_P2_PCPORT_XMIT_WAIT_VL4_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_WAIT_VL4_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_WAIT_VL5_ADDR 0x01180128L
+#define IBU_P2_PCPORT_XMIT_WAIT_VL5_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_WAIT_VL5_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_WAIT_VL6_ADDR 0x01180129L
+#define IBU_P2_PCPORT_XMIT_WAIT_VL6_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_WAIT_VL6_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_WAIT_VL7_ADDR 0x0118012aL
+#define IBU_P2_PCPORT_XMIT_WAIT_VL7_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_WAIT_VL7_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_WAIT_VL15_ADDR 0x0118012bL
+#define IBU_P2_PCPORT_XMIT_WAIT_VL15_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_WAIT_VL15_DEPTH 1
+
+#define IBU_P2_PCRX_LINK_CNT_RST_ADDR 0x0118012cL
+#define IBU_P2_PCRX_LINK_CNT_RST_STRIDE 1
+#define IBU_P2_PCRX_LINK_CNT_RST_DEPTH 1
+
+#define IBU_P2_PCRX_LINK_CNT_LOAD_ADDR 0x0118012dL
+#define IBU_P2_PCRX_LINK_CNT_LOAD_STRIDE 1
+#define IBU_P2_PCRX_LINK_CNT_LOAD_DEPTH 1
+
+#define IBU_P2_LOCAL_PHY_ERRORS_ADDR 0x0118012eL
+#define IBU_P2_LOCAL_PHY_ERRORS_STRIDE 1
+#define IBU_P2_LOCAL_PHY_ERRORS_DEPTH 1
+
+#define IBU_P2_OVERRUN_ERRORS_ADDR 0x0118012fL
+#define IBU_P2_OVERRUN_ERRORS_STRIDE 1
+#define IBU_P2_OVERRUN_ERRORS_DEPTH 1
+
+#define IBU_P2_PSLINK_DLID_ADDR 0x01180130L
+#define IBU_P2_PSLINK_DLID_STRIDE 1
+#define IBU_P2_PSLINK_DLID_DEPTH 1
+
+#define IBU_P2_PSTICK_ADDR 0x01180131L
+#define IBU_P2_PSTICK_STRIDE 1
+#define IBU_P2_PSTICK_DEPTH 1
+
+#define IBU_P2_PSSTATUS_ADDR 0x01180132L
+#define IBU_P2_PSSTATUS_STRIDE 1
+#define IBU_P2_PSSTATUS_DEPTH 1
+
+#define IBU_P2_PSSTART_DELAY_ADDR 0x01180133L
+#define IBU_P2_PSSTART_DELAY_STRIDE 1
+#define IBU_P2_PSSTART_DELAY_DEPTH 1
+
+#define IBU_P2_PSINTERVAL_ADDR 0x01180134L
+#define IBU_P2_PSINTERVAL_STRIDE 1
+#define IBU_P2_PSINTERVAL_DEPTH 1
+
+#define IBU_P2_PSCNT_SEL0_ADDR 0x01180135L
+#define IBU_P2_PSCNT_SEL0_STRIDE 1
+#define IBU_P2_PSCNT_SEL0_DEPTH 1
+
+#define IBU_P2_PSCNT_SEL1_ADDR 0x01180136L
+#define IBU_P2_PSCNT_SEL1_STRIDE 1
+#define IBU_P2_PSCNT_SEL1_DEPTH 1
+
+#define IBU_P2_PSCNT_SEL2_ADDR 0x01180137L
+#define IBU_P2_PSCNT_SEL2_STRIDE 1
+#define IBU_P2_PSCNT_SEL2_DEPTH 1
+
+#define IBU_P2_PSCNT_SEL3_ADDR 0x01180138L
+#define IBU_P2_PSCNT_SEL3_STRIDE 1
+#define IBU_P2_PSCNT_SEL3_DEPTH 1
+
+#define IBU_P2_PSCNT0_ADDR 0x01180139L
+#define IBU_P2_PSCNT0_STRIDE 1
+#define IBU_P2_PSCNT0_DEPTH 1
+
+#define IBU_P2_PSCNT1_ADDR 0x0118013aL
+#define IBU_P2_PSCNT1_STRIDE 1
+#define IBU_P2_PSCNT1_DEPTH 1
+
+#define IBU_P2_PSCNT2_ADDR 0x0118013bL
+#define IBU_P2_PSCNT2_STRIDE 1
+#define IBU_P2_PSCNT2_DEPTH 1
+
+#define IBU_P2_PSCNT3_ADDR 0x0118013cL
+#define IBU_P2_PSCNT3_STRIDE 1
+#define IBU_P2_PSCNT3_DEPTH 1
+
+#define IBU_P2_PSINIT_SAMPLING_ADDR 0x0118013dL
+#define IBU_P2_PSINIT_SAMPLING_STRIDE 1
+#define IBU_P2_PSINIT_SAMPLING_DEPTH 1
+
+#define IBU_P2_PSCNT_LOAD_ADDR 0x0118013eL
+#define IBU_P2_PSCNT_LOAD_STRIDE 1
+#define IBU_P2_PSCNT_LOAD_DEPTH 1
+
+#define IBU_P2_PORT_STATE_CHANGE_ADDR 0x0118013fL
+#define IBU_P2_PORT_STATE_CHANGE_STRIDE 1
+#define IBU_P2_PORT_STATE_CHANGE_DEPTH 1
+
+#define IBU_P2_LINK_VCONFIG0_ADDR 0x01180141L
+#define IBU_P2_LINK_VCONFIG0_STRIDE 1
+#define IBU_P2_LINK_VCONFIG0_DEPTH 1
+
+#define IBU_P2_LINK_VCONFIG1_ADDR 0x01180142L
+#define IBU_P2_LINK_VCONFIG1_STRIDE 1
+#define IBU_P2_LINK_VCONFIG1_DEPTH 1
+
+#define IBU_P2_LINK_VCONFIG2_ADDR 0x01180143L
+#define IBU_P2_LINK_VCONFIG2_STRIDE 1
+#define IBU_P2_LINK_VCONFIG2_DEPTH 1
+
+#define IBU_P2_LINK_RX_CREDIT_VL1_0_ADDR 0x01180144L
+#define IBU_P2_LINK_RX_CREDIT_VL1_0_STRIDE 1
+#define IBU_P2_LINK_RX_CREDIT_VL1_0_DEPTH 1
+
+#define IBU_P2_LINK_RX_CREDIT_VL3_2_ADDR 0x01180145L
+#define IBU_P2_LINK_RX_CREDIT_VL3_2_STRIDE 1
+#define IBU_P2_LINK_RX_CREDIT_VL3_2_DEPTH 1
+
+#define IBU_P2_LINK_RX_CREDIT_VL5_4_ADDR 0x01180146L
+#define IBU_P2_LINK_RX_CREDIT_VL5_4_STRIDE 1
+#define IBU_P2_LINK_RX_CREDIT_VL5_4_DEPTH 1
+
+#define IBU_P2_LINK_RX_CREDIT_VL7_6_ADDR 0x01180147L
+#define IBU_P2_LINK_RX_CREDIT_VL7_6_STRIDE 1
+#define IBU_P2_LINK_RX_CREDIT_VL7_6_DEPTH 1
+
+#define IBU_P2_LINK_TX_CREDIT_VL1_0_ADDR 0x01180148L
+#define IBU_P2_LINK_TX_CREDIT_VL1_0_STRIDE 1
+#define IBU_P2_LINK_TX_CREDIT_VL1_0_DEPTH 1
+
+#define IBU_P2_LINK_TX_CREDIT_VL3_2_ADDR 0x01180149L
+#define IBU_P2_LINK_TX_CREDIT_VL3_2_STRIDE 1
+#define IBU_P2_LINK_TX_CREDIT_VL3_2_DEPTH 1
+
+#define IBU_P2_LINK_TX_CREDIT_VL5_4_ADDR 0x0118014aL
+#define IBU_P2_LINK_TX_CREDIT_VL5_4_STRIDE 1
+#define IBU_P2_LINK_TX_CREDIT_VL5_4_DEPTH 1
+
+#define IBU_P2_LINK_TX_CREDIT_VL7_6_ADDR 0x0118014bL
+#define IBU_P2_LINK_TX_CREDIT_VL7_6_STRIDE 1
+#define IBU_P2_LINK_TX_CREDIT_VL7_6_DEPTH 1
+
+#define IBU_P2_PCTX_LINK_CNT_RST_ADDR 0x0118014cL
+#define IBU_P2_PCTX_LINK_CNT_RST_STRIDE 1
+#define IBU_P2_PCTX_LINK_CNT_RST_DEPTH 1
+
+#define IBU_P2_PCTX_LINK_CNT_LOAD_ADDR 0x0118014dL
+#define IBU_P2_PCTX_LINK_CNT_LOAD_STRIDE 1
+#define IBU_P2_PCTX_LINK_CNT_LOAD_DEPTH 1
+
+#define IBU_P2_PSCNT_WIDTH_ADDR 0x0118014fL
+#define IBU_P2_PSCNT_WIDTH_STRIDE 1
+#define IBU_P2_PSCNT_WIDTH_DEPTH 1
+
+#define IBU_P2_PSCNT_MASK_ADDR 0x01180150L
+#define IBU_P2_PSCNT_MASK_STRIDE 1
+#define IBU_P2_PSCNT_MASK_DEPTH 1
+
+#define IBU_P2_PCICRC_RCV_ERRORS_ADDR 0x01180151L
+#define IBU_P2_PCICRC_RCV_ERRORS_STRIDE 1
+#define IBU_P2_PCICRC_RCV_ERRORS_DEPTH 1
+
+#define IBU_P2_PCVCRC_RCV_ERRORS_ADDR 0x01180152L
+#define IBU_P2_PCVCRC_RCV_ERRORS_STRIDE 1
+#define IBU_P2_PCVCRC_RCV_ERRORS_DEPTH 1
+
+#define IBU_P2_PCLEN_RCV_ERRORS_ADDR 0x01180153L
+#define IBU_P2_PCLEN_RCV_ERRORS_STRIDE 1
+#define IBU_P2_PCLEN_RCV_ERRORS_DEPTH 1
+
+#define IBU_P2_PCDLID_RCV_ERRORS_ADDR 0x01180154L
+#define IBU_P2_PCDLID_RCV_ERRORS_STRIDE 1
+#define IBU_P2_PCDLID_RCV_ERRORS_DEPTH 1
+
+#define IBU_P2_PCRCV_FCLEN_ERRORS_ADDR 0x01180155L
+#define IBU_P2_PCRCV_FCLEN_ERRORS_STRIDE 1
+#define IBU_P2_PCRCV_FCLEN_ERRORS_DEPTH 1
+
+#define IBU_P2_PCRCV_FCVL_ERRORS_ADDR 0x01180156L
+#define IBU_P2_PCRCV_FCVL_ERRORS_STRIDE 1
+#define IBU_P2_PCRCV_FCVL_ERRORS_DEPTH 1
+
+#define IBU_P2_PCRCV_FCCRC_ERRORS_ADDR 0x01180157L
+#define IBU_P2_PCRCV_FCCRC_ERRORS_STRIDE 1
+#define IBU_P2_PCRCV_FCCRC_ERRORS_DEPTH 1
+
+#define IBU_P2_PORT_LOCAL_PHYSICAL_ERRORS_ADDR 0x01180158L
+#define IBU_P2_PORT_LOCAL_PHYSICAL_ERRORS_STRIDE 1
+#define IBU_P2_PORT_LOCAL_PHYSICAL_ERRORS_DEPTH 1
+
+#define IBU_P2_PCMAL_FORMED_ERRORS_ADDR 0x01180159L
+#define IBU_P2_PCMAL_FORMED_ERRORS_STRIDE 1
+#define IBU_P2_PCMAL_FORMED_ERRORS_DEPTH 1
+
+#define IBU_P2_PCBUF_OVER_ERRORS_ADDR 0x0118015aL
+#define IBU_P2_PCBUF_OVER_ERRORS_STRIDE 1
+#define IBU_P2_PCBUF_OVER_ERRORS_DEPTH 1
+
+#define IBU_P2_PCVLMAP_ERRORS_ADDR 0x0118015bL
+#define IBU_P2_PCVLMAP_ERRORS_STRIDE 1
+#define IBU_P2_PCVLMAP_ERRORS_DEPTH 1
+
+#define IBU_P2_PCVLINIT_CREDIT_VL1_VL0_ADDR 0x0118015cL
+#define IBU_P2_PCVLINIT_CREDIT_VL1_VL0_STRIDE 1
+#define IBU_P2_PCVLINIT_CREDIT_VL1_VL0_DEPTH 1
+
+#define IBU_P2_PCVLINIT_CREDIT_VL3_VL2_ADDR 0x0118015dL
+#define IBU_P2_PCVLINIT_CREDIT_VL3_VL2_STRIDE 1
+#define IBU_P2_PCVLINIT_CREDIT_VL3_VL2_DEPTH 1
+
+#define IBU_P2_PCVLINIT_CREDIT_VL5_VL4_ADDR 0x0118015eL
+#define IBU_P2_PCVLINIT_CREDIT_VL5_VL4_STRIDE 1
+#define IBU_P2_PCVLINIT_CREDIT_VL5_VL4_DEPTH 1
+
+#define IBU_P2_PCVLINIT_CREDIT_VL7_VL6_ADDR 0x0118015fL
+#define IBU_P2_PCVLINIT_CREDIT_VL7_VL6_STRIDE 1
+#define IBU_P2_PCVLINIT_CREDIT_VL7_VL6_DEPTH 1
+
+#define IBU_P2_PCRX_VL07_ECC_COR_ERR_CNT_ADDR 0x01180160L
+#define IBU_P2_PCRX_VL07_ECC_COR_ERR_CNT_STRIDE 1
+#define IBU_P2_PCRX_VL07_ECC_COR_ERR_CNT_DEPTH 1
+
+#define IBU_P2_PCRX_VL07_ECC_UNC_ERR_CNT_ADDR 0x01180161L
+#define IBU_P2_PCRX_VL07_ECC_UNC_ERR_CNT_STRIDE 1
+#define IBU_P2_PCRX_VL07_ECC_UNC_ERR_CNT_DEPTH 1
+
+#define IBU_P2_PCRX_VL15_ECC_COR_ERR_CNT_ADDR 0x01180162L
+#define IBU_P2_PCRX_VL15_ECC_COR_ERR_CNT_STRIDE 1
+#define IBU_P2_PCRX_VL15_ECC_COR_ERR_CNT_DEPTH 1
+
+#define IBU_P2_PCRX_VL15_ECC_UNC_ERR_CNT_ADDR 0x01180163L
+#define IBU_P2_PCRX_VL15_ECC_UNC_ERR_CNT_STRIDE 1
+#define IBU_P2_PCRX_VL15_ECC_UNC_ERR_CNT_DEPTH 1
+
+#define IBU_P2_PCRX_LOOP_ECC_COR_ERR_CNT_ADDR 0x01180164L
+#define IBU_P2_PCRX_LOOP_ECC_COR_ERR_CNT_STRIDE 1
+#define IBU_P2_PCRX_LOOP_ECC_COR_ERR_CNT_DEPTH 1
+
+#define IBU_P2_PCRX_LOOP_ECC_UNC_ERR_CNT_ADDR 0x01180165L
+#define IBU_P2_PCRX_LOOP_ECC_UNC_ERR_CNT_STRIDE 1
+#define IBU_P2_PCRX_LOOP_ECC_UNC_ERR_CNT_DEPTH 1
+
+#define IBU_P2_PCECCENA_ERR_ADDR 0x01180166L
+#define IBU_P2_PCECCENA_ERR_STRIDE 1
+#define IBU_P2_PCECCENA_ERR_DEPTH 1
+
+#define IBU_P2_PCTX_ECC_COR_ERR_CNT_ADDR 0x01180167L
+#define IBU_P2_PCTX_ECC_COR_ERR_CNT_STRIDE 1
+#define IBU_P2_PCTX_ECC_COR_ERR_CNT_DEPTH 1
+
+#define IBU_P2_PCTX_ECC_UNC_ERR_CNT_ADDR 0x01180168L
+#define IBU_P2_PCTX_ECC_UNC_ERR_CNT_STRIDE 1
+#define IBU_P2_PCTX_ECC_UNC_ERR_CNT_DEPTH 1
+
+#define IBU_P2_TX_SRAMSTATUS_ADDR 0x01180169L
+#define IBU_P2_TX_SRAMSTATUS_STRIDE 1
+#define IBU_P2_TX_SRAMSTATUS_DEPTH 1
+
+#define IBU_P2_TX_CACHE_STATUS_ADDR 0x0118016aL
+#define IBU_P2_TX_CACHE_STATUS_STRIDE 1
+#define IBU_P2_TX_CACHE_STATUS_DEPTH 1
+
+#define IBU_P2_TX_DEBUG_ADDR 0x0118016bL
+#define IBU_P2_TX_DEBUG_STRIDE 1
+#define IBU_P2_TX_DEBUG_DEPTH 1
+
+#define IBU_P2_RX_VL07_SRAMSTATUS_ADDR 0x0118016cL
+#define IBU_P2_RX_VL07_SRAMSTATUS_STRIDE 1
+#define IBU_P2_RX_VL07_SRAMSTATUS_DEPTH 1
+
+#define IBU_P2_RX_VL15_SRAMSTATUS_ADDR 0x0118016dL
+#define IBU_P2_RX_VL15_SRAMSTATUS_STRIDE 1
+#define IBU_P2_RX_VL15_SRAMSTATUS_DEPTH 1
+
+#define IBU_P2_LOOPSRAMSTATUS_ADDR 0x0118016eL
+#define IBU_P2_LOOPSRAMSTATUS_STRIDE 1
+#define IBU_P2_LOOPSRAMSTATUS_DEPTH 1
+
+#define IBU_P2_RX_DEBUG_ADDR 0x0118016fL
+#define IBU_P2_RX_DEBUG_STRIDE 1
+#define IBU_P2_RX_DEBUG_DEPTH 1
+
+#define IBU_P2_TX_ARB_LOOPBACK_SRAMSTATUS_ADDR 0x01180170L
+#define IBU_P2_TX_ARB_LOOPBACK_SRAMSTATUS_STRIDE 1
+#define IBU_P2_TX_ARB_LOOPBACK_SRAMSTATUS_DEPTH 1
+
+#define IBU_P2_REMOTE_RX_BUFF_LIMIT_ADDR 0x01180171L
+#define IBU_P2_REMOTE_RX_BUFF_LIMIT_STRIDE 1
+#define IBU_P2_REMOTE_RX_BUFF_LIMIT_DEPTH 1
+
+#define IBU_P2_FCTX_TIMER_ADDR 0x01180172L
+#define IBU_P2_FCTX_TIMER_STRIDE 1
+#define IBU_P2_FCTX_TIMER_DEPTH 1
+
+#define IBU_P2_FCRX_TIMER_ADDR 0x01180173L
+#define IBU_P2_FCRX_TIMER_STRIDE 1
+#define IBU_P2_FCRX_TIMER_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_DATA_HSQW_ADDR 0x01180174L
+#define IBU_P2_PCPORT_XMIT_DATA_HSQW_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_DATA_HSQW_DEPTH 1
+
+#define IBU_P2_PCPORT_XMIT_VLDISCARDS_ADDR 0x01180175L
+#define IBU_P2_PCPORT_XMIT_VLDISCARDS_STRIDE 1
+#define IBU_P2_PCPORT_XMIT_VLDISCARDS_DEPTH 1
+
+#define IBU_P2_PCPORT_COL_LIMIT_ADDR 0x01180176L
+#define IBU_P2_PCPORT_COL_LIMIT_STRIDE 1
+#define IBU_P2_PCPORT_COL_LIMIT_DEPTH 1
+
+#define IBU_P2_VLARB_HI_PRI_TABLE_ADDR 0x01180180L
+#define IBU_P2_VLARB_HI_PRI_TABLE_STRIDE 1
+#define IBU_P2_VLARB_HI_PRI_TABLE_DEPTH 10
+
+#define IBU_P2_VLARB_LO_PRI_TABLE_ADDR 0x011801c0L
+#define IBU_P2_VLARB_LO_PRI_TABLE_STRIDE 1
+#define IBU_P2_VLARB_LO_PRI_TABLE_DEPTH 10
+
+#define IBU_P2_TX_TBSVL10_ADDR 0x011801d0L
+#define IBU_P2_TX_TBSVL10_STRIDE 1
+#define IBU_P2_TX_TBSVL10_DEPTH 1
+
+#define IBU_P2_TX_TBSVL32_ADDR 0x011801d1L
+#define IBU_P2_TX_TBSVL32_STRIDE 1
+#define IBU_P2_TX_TBSVL32_DEPTH 1
+
+#define IBU_P2_TX_TBSVL54_ADDR 0x011801d2L
+#define IBU_P2_TX_TBSVL54_STRIDE 1
+#define IBU_P2_TX_TBSVL54_DEPTH 1
+
+#define IBU_P2_TX_TBSVL76_ADDR 0x011801d3L
+#define IBU_P2_TX_TBSVL76_STRIDE 1
+#define IBU_P2_TX_TBSVL76_DEPTH 1
+
+#define IBU_P2_TX_TBSARB_VL10_ADDR 0x011801d4L
+#define IBU_P2_TX_TBSARB_VL10_STRIDE 1
+#define IBU_P2_TX_TBSARB_VL10_DEPTH 1
+
+#define IBU_P2_TX_TBSARB_VL32_ADDR 0x011801d5L
+#define IBU_P2_TX_TBSARB_VL32_STRIDE 1
+#define IBU_P2_TX_TBSARB_VL32_DEPTH 1
+
+#define IBU_P2_TX_TBSARB_VL54_ADDR 0x011801d6L
+#define IBU_P2_TX_TBSARB_VL54_STRIDE 1
+#define IBU_P2_TX_TBSARB_VL54_DEPTH 1
+
+#define IBU_P2_TX_TBSARB_VL76_ADDR 0x011801d7L
+#define IBU_P2_TX_TBSARB_VL76_STRIDE 1
+#define IBU_P2_TX_TBSARB_VL76_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_ENABLE_ADDR 0x011801d8L
+#define IBU_P2_RX_TRACE_CAPTURE_ENABLE_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_ENABLE_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_MODE_ADDR 0x011801d9L
+#define IBU_P2_RX_TRACE_CAPTURE_MODE_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_MODE_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_RDY_ADDR 0x011801daL
+#define IBU_P2_RX_TRACE_CAPTURE_RDY_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_RDY_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_TIMER_ADDR 0x011801dbL
+#define IBU_P2_RX_TRACE_CAPTURE_TIMER_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_TIMER_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_START_ADDR 0x011801dcL
+#define IBU_P2_RX_TRACE_CAPTURE_START_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_START_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_DATA1_ADDR 0x011801e0L
+#define IBU_P2_RX_TRACE_CAPTURE_DATA1_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_DATA1_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_DATA2_ADDR 0x011801e1L
+#define IBU_P2_RX_TRACE_CAPTURE_DATA2_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_DATA2_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_DATA3_ADDR 0x011801e2L
+#define IBU_P2_RX_TRACE_CAPTURE_DATA3_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_DATA3_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_DATA4_ADDR 0x011801e3L
+#define IBU_P2_RX_TRACE_CAPTURE_DATA4_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_DATA4_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_DATA5_ADDR 0x011801e4L
+#define IBU_P2_RX_TRACE_CAPTURE_DATA5_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_DATA5_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_DATA6_ADDR 0x011801e5L
+#define IBU_P2_RX_TRACE_CAPTURE_DATA6_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_DATA6_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_DATA7_ADDR 0x011801e6L
+#define IBU_P2_RX_TRACE_CAPTURE_DATA7_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_DATA7_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_DATA8_ADDR 0x011801e7L
+#define IBU_P2_RX_TRACE_CAPTURE_DATA8_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_DATA8_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_DATA9_ADDR 0x011801e8L
+#define IBU_P2_RX_TRACE_CAPTURE_DATA9_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_DATA9_DEPTH 1
+
+#define IBU_P2_RX_TRACE_CAPTURE_DATA10_ADDR 0x011801e9L
+#define IBU_P2_RX_TRACE_CAPTURE_DATA10_STRIDE 1
+#define IBU_P2_RX_TRACE_CAPTURE_DATA10_DEPTH 1
+
+#define IBU_P2_LINK_RX_FCCL_VL1_0_ADDR 0x011801eaL
+#define IBU_P2_LINK_RX_FCCL_VL1_0_STRIDE 1
+#define IBU_P2_LINK_RX_FCCL_VL1_0_DEPTH 1
+
+#define IBU_P2_LINK_RX_FCCL_VL3_2_ADDR 0x011801ebL
+#define IBU_P2_LINK_RX_FCCL_VL3_2_STRIDE 1
+#define IBU_P2_LINK_RX_FCCL_VL3_2_DEPTH 1
+
+#define IBU_P2_LINK_RX_FCCL_VL5_4_ADDR 0x011801ecL
+#define IBU_P2_LINK_RX_FCCL_VL5_4_STRIDE 1
+#define IBU_P2_LINK_RX_FCCL_VL5_4_DEPTH 1
+
+#define IBU_P2_LINK_RX_FCCL_VL7_6_ADDR 0x011801edL
+#define IBU_P2_LINK_RX_FCCL_VL7_6_STRIDE 1
+#define IBU_P2_LINK_RX_FCCL_VL7_6_DEPTH 1
+
+#define IBU_P2_LINK_NEIGHBOR_JUMBO_MTU_ADDR 0x011801eeL
+#define IBU_P2_LINK_NEIGHBOR_JUMBO_MTU_STRIDE 1
+#define IBU_P2_LINK_NEIGHBOR_JUMBO_MTU_DEPTH 1
+
+#define IBU_P2_ADD_DEFAULT_LANE0_ADDR 0x01180210L
+#define IBU_P2_ADD_DEFAULT_LANE0_STRIDE 1
+#define IBU_P2_ADD_DEFAULT_LANE0_DEPTH 1
+
+#define IBU_P2_ADD_DEFAULT_LANE1_ADDR 0x01180211L
+#define IBU_P2_ADD_DEFAULT_LANE1_STRIDE 1
+#define IBU_P2_ADD_DEFAULT_LANE1_DEPTH 1
+
+#define IBU_P2_ADD_DEFAULT_LANE2_ADDR 0x01180212L
+#define IBU_P2_ADD_DEFAULT_LANE2_STRIDE 1
+#define IBU_P2_ADD_DEFAULT_LANE2_DEPTH 1
+
+#define IBU_P2_ADD_DEFAULT_LANE3_ADDR 0x01180213L
+#define IBU_P2_ADD_DEFAULT_LANE3_STRIDE 1
+#define IBU_P2_ADD_DEFAULT_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD0_LANE0_ADDR 0x01180214L
+#define IBU_P2_PHY_ADD0_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD0_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD0_LANE1_ADDR 0x01180215L
+#define IBU_P2_PHY_ADD0_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD0_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD0_LANE2_ADDR 0x01180216L
+#define IBU_P2_PHY_ADD0_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD0_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD0_LANE3_ADDR 0x01180217L
+#define IBU_P2_PHY_ADD0_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD0_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD1_LANE0_ADDR 0x01180218L
+#define IBU_P2_PHY_ADD1_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD1_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD1_LANE1_ADDR 0x01180219L
+#define IBU_P2_PHY_ADD1_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD1_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD1_LANE2_ADDR 0x0118021aL
+#define IBU_P2_PHY_ADD1_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD1_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD1_LANE3_ADDR 0x0118021bL
+#define IBU_P2_PHY_ADD1_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD1_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD2_LANE0_ADDR 0x0118021cL
+#define IBU_P2_PHY_ADD2_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD2_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD2_LANE1_ADDR 0x0118021dL
+#define IBU_P2_PHY_ADD2_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD2_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD2_LANE2_ADDR 0x0118021eL
+#define IBU_P2_PHY_ADD2_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD2_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD2_LANE3_ADDR 0x0118021fL
+#define IBU_P2_PHY_ADD2_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD2_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD3_LANE0_ADDR 0x01180220L
+#define IBU_P2_PHY_ADD3_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD3_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD3_LANE1_ADDR 0x01180221L
+#define IBU_P2_PHY_ADD3_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD3_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD3_LANE2_ADDR 0x01180222L
+#define IBU_P2_PHY_ADD3_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD3_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD3_LANE3_ADDR 0x01180223L
+#define IBU_P2_PHY_ADD3_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD3_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD4_LANE0_ADDR 0x01180224L
+#define IBU_P2_PHY_ADD4_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD4_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD4_LANE1_ADDR 0x01180225L
+#define IBU_P2_PHY_ADD4_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD4_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD4_LANE2_ADDR 0x01180226L
+#define IBU_P2_PHY_ADD4_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD4_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD4_LANE3_ADDR 0x01180227L
+#define IBU_P2_PHY_ADD4_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD4_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD5_LANE0_ADDR 0x01180228L
+#define IBU_P2_PHY_ADD5_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD5_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD5_LANE1_ADDR 0x01180229L
+#define IBU_P2_PHY_ADD5_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD5_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD5_LANE2_ADDR 0x0118022aL
+#define IBU_P2_PHY_ADD5_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD5_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD5_LANE3_ADDR 0x0118022bL
+#define IBU_P2_PHY_ADD5_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD5_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD6_LANE0_ADDR 0x0118022cL
+#define IBU_P2_PHY_ADD6_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD6_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD6_LANE1_ADDR 0x0118022dL
+#define IBU_P2_PHY_ADD6_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD6_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD6_LANE2_ADDR 0x0118022eL
+#define IBU_P2_PHY_ADD6_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD6_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD6_LANE3_ADDR 0x0118022fL
+#define IBU_P2_PHY_ADD6_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD6_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD7_LANE0_ADDR 0x01180230L
+#define IBU_P2_PHY_ADD7_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD7_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD7_LANE1_ADDR 0x01180231L
+#define IBU_P2_PHY_ADD7_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD7_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD7_LANE2_ADDR 0x01180232L
+#define IBU_P2_PHY_ADD7_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD7_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD7_LANE3_ADDR 0x01180233L
+#define IBU_P2_PHY_ADD7_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD7_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD8_LANE0_ADDR 0x01180234L
+#define IBU_P2_PHY_ADD8_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD8_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD8_LANE1_ADDR 0x01180235L
+#define IBU_P2_PHY_ADD8_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD8_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD8_LANE2_ADDR 0x01180236L
+#define IBU_P2_PHY_ADD8_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD8_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD8_LANE3_ADDR 0x01180237L
+#define IBU_P2_PHY_ADD8_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD8_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD9_LANE0_ADDR 0x01180238L
+#define IBU_P2_PHY_ADD9_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD9_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD9_LANE1_ADDR 0x01180239L
+#define IBU_P2_PHY_ADD9_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD9_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD9_LANE2_ADDR 0x0118023aL
+#define IBU_P2_PHY_ADD9_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD9_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD9_LANE3_ADDR 0x0118023bL
+#define IBU_P2_PHY_ADD9_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD9_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD10_LANE0_ADDR 0x0118023cL
+#define IBU_P2_PHY_ADD10_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD10_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD10_LANE1_ADDR 0x0118023dL
+#define IBU_P2_PHY_ADD10_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD10_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD10_LANE2_ADDR 0x0118023eL
+#define IBU_P2_PHY_ADD10_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD10_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD10_LANE3_ADDR 0x0118023fL
+#define IBU_P2_PHY_ADD10_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD10_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD11_LANE0_ADDR 0x01180240L
+#define IBU_P2_PHY_ADD11_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD11_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD11_LANE1_ADDR 0x01180241L
+#define IBU_P2_PHY_ADD11_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD11_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD11_LANE2_ADDR 0x01180242L
+#define IBU_P2_PHY_ADD11_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD11_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD11_LANE3_ADDR 0x01180243L
+#define IBU_P2_PHY_ADD11_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD11_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD12_LANE0_ADDR 0x01180244L
+#define IBU_P2_PHY_ADD12_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD12_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD12_LANE1_ADDR 0x01180245L
+#define IBU_P2_PHY_ADD12_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD12_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD12_LANE2_ADDR 0x01180246L
+#define IBU_P2_PHY_ADD12_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD12_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD12_LANE3_ADDR 0x01180247L
+#define IBU_P2_PHY_ADD12_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD12_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD13_LANE0_ADDR 0x01180248L
+#define IBU_P2_PHY_ADD13_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD13_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD13_LANE1_ADDR 0x01180249L
+#define IBU_P2_PHY_ADD13_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD13_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD13_LANE2_ADDR 0x0118024aL
+#define IBU_P2_PHY_ADD13_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD13_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD13_LANE3_ADDR 0x0118024bL
+#define IBU_P2_PHY_ADD13_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD13_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD14_LANE0_ADDR 0x0118024cL
+#define IBU_P2_PHY_ADD14_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD14_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD14_LANE1_ADDR 0x0118024dL
+#define IBU_P2_PHY_ADD14_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD14_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD14_LANE2_ADDR 0x0118024eL
+#define IBU_P2_PHY_ADD14_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD14_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD14_LANE3_ADDR 0x0118024fL
+#define IBU_P2_PHY_ADD14_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD14_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_ADD15_LANE0_ADDR 0x01180250L
+#define IBU_P2_PHY_ADD15_LANE0_STRIDE 1
+#define IBU_P2_PHY_ADD15_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_ADD15_LANE1_ADDR 0x01180251L
+#define IBU_P2_PHY_ADD15_LANE1_STRIDE 1
+#define IBU_P2_PHY_ADD15_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_ADD15_LANE2_ADDR 0x01180252L
+#define IBU_P2_PHY_ADD15_LANE2_STRIDE 1
+#define IBU_P2_PHY_ADD15_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_ADD15_LANE3_ADDR 0x01180253L
+#define IBU_P2_PHY_ADD15_LANE3_STRIDE 1
+#define IBU_P2_PHY_ADD15_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD0_LANE0_ADDR 0x01180254L
+#define IBU_P2_PHY_AMP1_ADD0_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD0_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD0_LANE1_ADDR 0x01180255L
+#define IBU_P2_PHY_AMP1_ADD0_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD0_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD0_LANE2_ADDR 0x01180256L
+#define IBU_P2_PHY_AMP1_ADD0_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD0_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD0_LANE3_ADDR 0x01180257L
+#define IBU_P2_PHY_AMP1_ADD0_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD0_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD1_LANE0_ADDR 0x01180258L
+#define IBU_P2_PHY_AMP1_ADD1_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD1_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD1_LANE1_ADDR 0x01180259L
+#define IBU_P2_PHY_AMP1_ADD1_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD1_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD1_LANE2_ADDR 0x0118025aL
+#define IBU_P2_PHY_AMP1_ADD1_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD1_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD1_LANE3_ADDR 0x0118025bL
+#define IBU_P2_PHY_AMP1_ADD1_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD1_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD2_LANE0_ADDR 0x0118025cL
+#define IBU_P2_PHY_AMP1_ADD2_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD2_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD2_LANE1_ADDR 0x0118025dL
+#define IBU_P2_PHY_AMP1_ADD2_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD2_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD2_LANE2_ADDR 0x0118025eL
+#define IBU_P2_PHY_AMP1_ADD2_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD2_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD2_LANE3_ADDR 0x0118025fL
+#define IBU_P2_PHY_AMP1_ADD2_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD2_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD3_LANE0_ADDR 0x01180260L
+#define IBU_P2_PHY_AMP1_ADD3_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD3_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD3_LANE1_ADDR 0x01180261L
+#define IBU_P2_PHY_AMP1_ADD3_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD3_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD3_LANE2_ADDR 0x01180262L
+#define IBU_P2_PHY_AMP1_ADD3_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD3_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD3_LANE3_ADDR 0x01180263L
+#define IBU_P2_PHY_AMP1_ADD3_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD3_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD4_LANE0_ADDR 0x01180264L
+#define IBU_P2_PHY_AMP1_ADD4_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD4_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD4_LANE1_ADDR 0x01180265L
+#define IBU_P2_PHY_AMP1_ADD4_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD4_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD4_LANE2_ADDR 0x01180266L
+#define IBU_P2_PHY_AMP1_ADD4_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD4_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD4_LANE3_ADDR 0x01180267L
+#define IBU_P2_PHY_AMP1_ADD4_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD4_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD5_LANE0_ADDR 0x01180268L
+#define IBU_P2_PHY_AMP1_ADD5_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD5_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD5_LANE1_ADDR 0x01180269L
+#define IBU_P2_PHY_AMP1_ADD5_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD5_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD5_LANE2_ADDR 0x0118026aL
+#define IBU_P2_PHY_AMP1_ADD5_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD5_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD5_LANE3_ADDR 0x0118026bL
+#define IBU_P2_PHY_AMP1_ADD5_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD5_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD6_LANE0_ADDR 0x0118026cL
+#define IBU_P2_PHY_AMP1_ADD6_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD6_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD6_LANE1_ADDR 0x0118026dL
+#define IBU_P2_PHY_AMP1_ADD6_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD6_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD6_LANE2_ADDR 0x0118026eL
+#define IBU_P2_PHY_AMP1_ADD6_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD6_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD6_LANE3_ADDR 0x0118026fL
+#define IBU_P2_PHY_AMP1_ADD6_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD6_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD7_LANE0_ADDR 0x01180270L
+#define IBU_P2_PHY_AMP1_ADD7_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD7_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD7_LANE1_ADDR 0x01180271L
+#define IBU_P2_PHY_AMP1_ADD7_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD7_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD7_LANE2_ADDR 0x01180272L
+#define IBU_P2_PHY_AMP1_ADD7_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD7_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD7_LANE3_ADDR 0x01180273L
+#define IBU_P2_PHY_AMP1_ADD7_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD7_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD8_LANE0_ADDR 0x01180274L
+#define IBU_P2_PHY_AMP1_ADD8_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD8_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD8_LANE1_ADDR 0x01180275L
+#define IBU_P2_PHY_AMP1_ADD8_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD8_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD8_LANE2_ADDR 0x01180276L
+#define IBU_P2_PHY_AMP1_ADD8_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD8_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD8_LANE3_ADDR 0x01180277L
+#define IBU_P2_PHY_AMP1_ADD8_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD8_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD9_LANE0_ADDR 0x01180278L
+#define IBU_P2_PHY_AMP1_ADD9_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD9_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD9_LANE1_ADDR 0x01180279L
+#define IBU_P2_PHY_AMP1_ADD9_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD9_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD9_LANE2_ADDR 0x0118027aL
+#define IBU_P2_PHY_AMP1_ADD9_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD9_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD9_LANE3_ADDR 0x0118027bL
+#define IBU_P2_PHY_AMP1_ADD9_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD9_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD10_LANE0_ADDR 0x0118027cL
+#define IBU_P2_PHY_AMP1_ADD10_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD10_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD10_LANE1_ADDR 0x0118027dL
+#define IBU_P2_PHY_AMP1_ADD10_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD10_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD10_LANE2_ADDR 0x0118027eL
+#define IBU_P2_PHY_AMP1_ADD10_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD10_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD10_LANE3_ADDR 0x0118027fL
+#define IBU_P2_PHY_AMP1_ADD10_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD10_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD11_LANE0_ADDR 0x01180280L
+#define IBU_P2_PHY_AMP1_ADD11_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD11_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD11_LANE1_ADDR 0x01180281L
+#define IBU_P2_PHY_AMP1_ADD11_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD11_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD11_LANE2_ADDR 0x01180282L
+#define IBU_P2_PHY_AMP1_ADD11_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD11_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD11_LANE3_ADDR 0x01180283L
+#define IBU_P2_PHY_AMP1_ADD11_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD11_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD12_LANE0_ADDR 0x01180284L
+#define IBU_P2_PHY_AMP1_ADD12_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD12_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD12_LANE1_ADDR 0x01180285L
+#define IBU_P2_PHY_AMP1_ADD12_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD12_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD12_LANE2_ADDR 0x01180286L
+#define IBU_P2_PHY_AMP1_ADD12_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD12_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD12_LANE3_ADDR 0x01180287L
+#define IBU_P2_PHY_AMP1_ADD12_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD12_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD13_LANE0_ADDR 0x01180288L
+#define IBU_P2_PHY_AMP1_ADD13_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD13_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD13_LANE1_ADDR 0x01180289L
+#define IBU_P2_PHY_AMP1_ADD13_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD13_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD13_LANE2_ADDR 0x0118028aL
+#define IBU_P2_PHY_AMP1_ADD13_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD13_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD13_LANE3_ADDR 0x0118028bL
+#define IBU_P2_PHY_AMP1_ADD13_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD13_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD14_LANE0_ADDR 0x0118028cL
+#define IBU_P2_PHY_AMP1_ADD14_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD14_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD14_LANE1_ADDR 0x0118028dL
+#define IBU_P2_PHY_AMP1_ADD14_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD14_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD14_LANE2_ADDR 0x0118028eL
+#define IBU_P2_PHY_AMP1_ADD14_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD14_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD14_LANE3_ADDR 0x0118028fL
+#define IBU_P2_PHY_AMP1_ADD14_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD14_LANE3_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD15_LANE0_ADDR 0x01180290L
+#define IBU_P2_PHY_AMP1_ADD15_LANE0_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD15_LANE0_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD15_LANE1_ADDR 0x01180291L
+#define IBU_P2_PHY_AMP1_ADD15_LANE1_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD15_LANE1_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD15_LANE2_ADDR 0x01180292L
+#define IBU_P2_PHY_AMP1_ADD15_LANE2_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD15_LANE2_DEPTH 1
+
+#define IBU_P2_PHY_AMP1_ADD15_LANE3_ADDR 0x01180293L
+#define IBU_P2_PHY_AMP1_ADD15_LANE3_STRIDE 1
+#define IBU_P2_PHY_AMP1_ADD15_LANE3_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS0_ADDR 0x01180294L
+#define IBU_P2_REMOTE_DDS0_STRIDE 1
+#define IBU_P2_REMOTE_DDS0_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS1_ADDR 0x01180295L
+#define IBU_P2_REMOTE_DDS1_STRIDE 1
+#define IBU_P2_REMOTE_DDS1_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS2_ADDR 0x01180296L
+#define IBU_P2_REMOTE_DDS2_STRIDE 1
+#define IBU_P2_REMOTE_DDS2_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS3_ADDR 0x01180297L
+#define IBU_P2_REMOTE_DDS3_STRIDE 1
+#define IBU_P2_REMOTE_DDS3_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS4_ADDR 0x01180298L
+#define IBU_P2_REMOTE_DDS4_STRIDE 1
+#define IBU_P2_REMOTE_DDS4_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS5_ADDR 0x01180299L
+#define IBU_P2_REMOTE_DDS5_STRIDE 1
+#define IBU_P2_REMOTE_DDS5_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS6_ADDR 0x0118029aL
+#define IBU_P2_REMOTE_DDS6_STRIDE 1
+#define IBU_P2_REMOTE_DDS6_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS7_ADDR 0x0118029bL
+#define IBU_P2_REMOTE_DDS7_STRIDE 1
+#define IBU_P2_REMOTE_DDS7_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS8_ADDR 0x0118029cL
+#define IBU_P2_REMOTE_DDS8_STRIDE 1
+#define IBU_P2_REMOTE_DDS8_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS9_ADDR 0x0118029dL
+#define IBU_P2_REMOTE_DDS9_STRIDE 1
+#define IBU_P2_REMOTE_DDS9_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS10_ADDR 0x0118029eL
+#define IBU_P2_REMOTE_DDS10_STRIDE 1
+#define IBU_P2_REMOTE_DDS10_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS11_ADDR 0x0118029fL
+#define IBU_P2_REMOTE_DDS11_STRIDE 1
+#define IBU_P2_REMOTE_DDS11_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS12_ADDR 0x011802a0L
+#define IBU_P2_REMOTE_DDS12_STRIDE 1
+#define IBU_P2_REMOTE_DDS12_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS13_ADDR 0x011802a1L
+#define IBU_P2_REMOTE_DDS13_STRIDE 1
+#define IBU_P2_REMOTE_DDS13_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS14_ADDR 0x011802a2L
+#define IBU_P2_REMOTE_DDS14_STRIDE 1
+#define IBU_P2_REMOTE_DDS14_DEPTH 1
+
+#define IBU_P2_REMOTE_DDS15_ADDR 0x011802a3L
+#define IBU_P2_REMOTE_DDS15_STRIDE 1
+#define IBU_P2_REMOTE_DDS15_DEPTH 1
+
+#define IBU_P2_BAD_CSR_ADDR 0x01180badL
+#define IBU_P2_BAD_CSR_STRIDE 1
+#define IBU_P2_BAD_CSR_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH0_000_ADDR 0x011c0000L
+#define IBU_P2_CETUS_CH0_000_STRIDE 1
+#define IBU_P2_CETUS_CH0_000_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH0_001_ADDR 0x011c0001L
+#define IBU_P2_CETUS_CH0_001_STRIDE 1
+#define IBU_P2_CETUS_CH0_001_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH0_002_ADDR 0x011c0002L
+#define IBU_P2_CETUS_CH0_002_STRIDE 1
+#define IBU_P2_CETUS_CH0_002_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_003_ADDR 0x011c0003L
+#define IBU_P2_CETUS_CH0_003_STRIDE 1
+#define IBU_P2_CETUS_CH0_003_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_004_ADDR 0x011c0004L
+#define IBU_P2_CETUS_CH0_004_STRIDE 1
+#define IBU_P2_CETUS_CH0_004_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_005_ADDR 0x011c0005L
+#define IBU_P2_CETUS_CH0_005_STRIDE 1
+#define IBU_P2_CETUS_CH0_005_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_006_ADDR 0x011c0006L
+#define IBU_P2_CETUS_CH0_006_STRIDE 1
+#define IBU_P2_CETUS_CH0_006_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_007_ADDR 0x011c0007L
+#define IBU_P2_CETUS_CH0_007_STRIDE 1
+#define IBU_P2_CETUS_CH0_007_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_008_ADDR 0x011c0008L
+#define IBU_P2_CETUS_CH0_008_STRIDE 1
+#define IBU_P2_CETUS_CH0_008_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_009_ADDR 0x011c0009L
+#define IBU_P2_CETUS_CH0_009_STRIDE 1
+#define IBU_P2_CETUS_CH0_009_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_010_ADDR 0x011c000aL
+#define IBU_P2_CETUS_CH0_010_STRIDE 1
+#define IBU_P2_CETUS_CH0_010_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_011_ADDR 0x011c000bL
+#define IBU_P2_CETUS_CH0_011_STRIDE 1
+#define IBU_P2_CETUS_CH0_011_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_012_ADDR 0x011c000cL
+#define IBU_P2_CETUS_CH0_012_STRIDE 1
+#define IBU_P2_CETUS_CH0_012_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_013_ADDR 0x011c000dL
+#define IBU_P2_CETUS_CH0_013_STRIDE 1
+#define IBU_P2_CETUS_CH0_013_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_014_ADDR 0x011c000eL
+#define IBU_P2_CETUS_CH0_014_STRIDE 1
+#define IBU_P2_CETUS_CH0_014_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_015_ADDR 0x011c000fL
+#define IBU_P2_CETUS_CH0_015_STRIDE 1
+#define IBU_P2_CETUS_CH0_015_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_016_ADDR 0x011c0010L
+#define IBU_P2_CETUS_CH0_016_STRIDE 1
+#define IBU_P2_CETUS_CH0_016_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_017_ADDR 0x011c0011L
+#define IBU_P2_CETUS_CH0_017_STRIDE 1
+#define IBU_P2_CETUS_CH0_017_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_018_ADDR 0x011c0012L
+#define IBU_P2_CETUS_CH0_018_STRIDE 1
+#define IBU_P2_CETUS_CH0_018_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_019_ADDR 0x011c0013L
+#define IBU_P2_CETUS_CH0_019_STRIDE 1
+#define IBU_P2_CETUS_CH0_019_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_020_ADDR 0x011c0014L
+#define IBU_P2_CETUS_CH0_020_STRIDE 1
+#define IBU_P2_CETUS_CH0_020_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_021_ADDR 0x011c0015L
+#define IBU_P2_CETUS_CH0_021_STRIDE 1
+#define IBU_P2_CETUS_CH0_021_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_022_ADDR 0x011c0016L
+#define IBU_P2_CETUS_CH0_022_STRIDE 1
+#define IBU_P2_CETUS_CH0_022_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_023_ADDR 0x011c0017L
+#define IBU_P2_CETUS_CH0_023_STRIDE 1
+#define IBU_P2_CETUS_CH0_023_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_024_ADDR 0x011c0018L
+#define IBU_P2_CETUS_CH0_024_STRIDE 1
+#define IBU_P2_CETUS_CH0_024_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_025_ADDR 0x011c0019L
+#define IBU_P2_CETUS_CH0_025_STRIDE 1
+#define IBU_P2_CETUS_CH0_025_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_026_ADDR 0x011c001aL
+#define IBU_P2_CETUS_CH0_026_STRIDE 1
+#define IBU_P2_CETUS_CH0_026_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_027_ADDR 0x011c001bL
+#define IBU_P2_CETUS_CH0_027_STRIDE 1
+#define IBU_P2_CETUS_CH0_027_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_028_ADDR 0x011c001cL
+#define IBU_P2_CETUS_CH0_028_STRIDE 1
+#define IBU_P2_CETUS_CH0_028_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_029_ADDR 0x011c001dL
+#define IBU_P2_CETUS_CH0_029_STRIDE 1
+#define IBU_P2_CETUS_CH0_029_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_030_ADDR 0x011c001eL
+#define IBU_P2_CETUS_CH0_030_STRIDE 1
+#define IBU_P2_CETUS_CH0_030_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_031_ADDR 0x011c001fL
+#define IBU_P2_CETUS_CH0_031_STRIDE 1
+#define IBU_P2_CETUS_CH0_031_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_032_ADDR 0x011c0020L
+#define IBU_P2_CETUS_CH0_032_STRIDE 1
+#define IBU_P2_CETUS_CH0_032_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_033_ADDR 0x011c0021L
+#define IBU_P2_CETUS_CH0_033_STRIDE 1
+#define IBU_P2_CETUS_CH0_033_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_034_ADDR 0x011c0022L
+#define IBU_P2_CETUS_CH0_034_STRIDE 1
+#define IBU_P2_CETUS_CH0_034_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_035_ADDR 0x011c0023L
+#define IBU_P2_CETUS_CH0_035_STRIDE 1
+#define IBU_P2_CETUS_CH0_035_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_036_ADDR 0x011c0024L
+#define IBU_P2_CETUS_CH0_036_STRIDE 1
+#define IBU_P2_CETUS_CH0_036_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_037_ADDR 0x011c0025L
+#define IBU_P2_CETUS_CH0_037_STRIDE 1
+#define IBU_P2_CETUS_CH0_037_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_038_ADDR 0x011c0026L
+#define IBU_P2_CETUS_CH0_038_STRIDE 1
+#define IBU_P2_CETUS_CH0_038_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_039_ADDR 0x011c0027L
+#define IBU_P2_CETUS_CH0_039_STRIDE 1
+#define IBU_P2_CETUS_CH0_039_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_040_ADDR 0x011c0028L
+#define IBU_P2_CETUS_CH0_040_STRIDE 1
+#define IBU_P2_CETUS_CH0_040_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_041_ADDR 0x011c0029L
+#define IBU_P2_CETUS_CH0_041_STRIDE 1
+#define IBU_P2_CETUS_CH0_041_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_042_ADDR 0x011c002aL
+#define IBU_P2_CETUS_CH0_042_STRIDE 1
+#define IBU_P2_CETUS_CH0_042_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_043_ADDR 0x011c002bL
+#define IBU_P2_CETUS_CH0_043_STRIDE 1
+#define IBU_P2_CETUS_CH0_043_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_044_ADDR 0x011c002cL
+#define IBU_P2_CETUS_CH0_044_STRIDE 1
+#define IBU_P2_CETUS_CH0_044_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_045_ADDR 0x011c002dL
+#define IBU_P2_CETUS_CH0_045_STRIDE 1
+#define IBU_P2_CETUS_CH0_045_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_046_ADDR 0x011c002eL
+#define IBU_P2_CETUS_CH0_046_STRIDE 1
+#define IBU_P2_CETUS_CH0_046_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_047_ADDR 0x011c002fL
+#define IBU_P2_CETUS_CH0_047_STRIDE 1
+#define IBU_P2_CETUS_CH0_047_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_048_ADDR 0x011c0030L
+#define IBU_P2_CETUS_CH0_048_STRIDE 1
+#define IBU_P2_CETUS_CH0_048_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_049_ADDR 0x011c0031L
+#define IBU_P2_CETUS_CH0_049_STRIDE 1
+#define IBU_P2_CETUS_CH0_049_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_050_ADDR 0x011c0032L
+#define IBU_P2_CETUS_CH0_050_STRIDE 1
+#define IBU_P2_CETUS_CH0_050_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_051_ADDR 0x011c0033L
+#define IBU_P2_CETUS_CH0_051_STRIDE 1
+#define IBU_P2_CETUS_CH0_051_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_052_ADDR 0x011c0034L
+#define IBU_P2_CETUS_CH0_052_STRIDE 1
+#define IBU_P2_CETUS_CH0_052_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_053_ADDR 0x011c0035L
+#define IBU_P2_CETUS_CH0_053_STRIDE 1
+#define IBU_P2_CETUS_CH0_053_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_054_ADDR 0x011c0036L
+#define IBU_P2_CETUS_CH0_054_STRIDE 1
+#define IBU_P2_CETUS_CH0_054_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_055_ADDR 0x011c0037L
+#define IBU_P2_CETUS_CH0_055_STRIDE 1
+#define IBU_P2_CETUS_CH0_055_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_056_ADDR 0x011c0038L
+#define IBU_P2_CETUS_CH0_056_STRIDE 1
+#define IBU_P2_CETUS_CH0_056_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_057_ADDR 0x011c0039L
+#define IBU_P2_CETUS_CH0_057_STRIDE 1
+#define IBU_P2_CETUS_CH0_057_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_058_ADDR 0x011c003aL
+#define IBU_P2_CETUS_CH0_058_STRIDE 1
+#define IBU_P2_CETUS_CH0_058_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_059_ADDR 0x011c003bL
+#define IBU_P2_CETUS_CH0_059_STRIDE 1
+#define IBU_P2_CETUS_CH0_059_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_060_ADDR 0x011c003cL
+#define IBU_P2_CETUS_CH0_060_STRIDE 1
+#define IBU_P2_CETUS_CH0_060_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_061_ADDR 0x011c003dL
+#define IBU_P2_CETUS_CH0_061_STRIDE 1
+#define IBU_P2_CETUS_CH0_061_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_062_ADDR 0x011c003eL
+#define IBU_P2_CETUS_CH0_062_STRIDE 1
+#define IBU_P2_CETUS_CH0_062_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_063_ADDR 0x011c003fL
+#define IBU_P2_CETUS_CH0_063_STRIDE 1
+#define IBU_P2_CETUS_CH0_063_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_064_ADDR 0x011c0040L
+#define IBU_P2_CETUS_CH0_064_STRIDE 1
+#define IBU_P2_CETUS_CH0_064_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_065_ADDR 0x011c0041L
+#define IBU_P2_CETUS_CH0_065_STRIDE 1
+#define IBU_P2_CETUS_CH0_065_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_066_ADDR 0x011c0042L
+#define IBU_P2_CETUS_CH0_066_STRIDE 1
+#define IBU_P2_CETUS_CH0_066_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_067_ADDR 0x011c0043L
+#define IBU_P2_CETUS_CH0_067_STRIDE 1
+#define IBU_P2_CETUS_CH0_067_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_068_ADDR 0x011c0044L
+#define IBU_P2_CETUS_CH0_068_STRIDE 1
+#define IBU_P2_CETUS_CH0_068_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_069_ADDR 0x011c0045L
+#define IBU_P2_CETUS_CH0_069_STRIDE 1
+#define IBU_P2_CETUS_CH0_069_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_070_ADDR 0x011c0046L
+#define IBU_P2_CETUS_CH0_070_STRIDE 1
+#define IBU_P2_CETUS_CH0_070_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_071_ADDR 0x011c0047L
+#define IBU_P2_CETUS_CH0_071_STRIDE 1
+#define IBU_P2_CETUS_CH0_071_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_072_ADDR 0x011c0048L
+#define IBU_P2_CETUS_CH0_072_STRIDE 1
+#define IBU_P2_CETUS_CH0_072_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_073_ADDR 0x011c0049L
+#define IBU_P2_CETUS_CH0_073_STRIDE 1
+#define IBU_P2_CETUS_CH0_073_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_074_ADDR 0x011c004aL
+#define IBU_P2_CETUS_CH0_074_STRIDE 1
+#define IBU_P2_CETUS_CH0_074_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_075_ADDR 0x011c004bL
+#define IBU_P2_CETUS_CH0_075_STRIDE 1
+#define IBU_P2_CETUS_CH0_075_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_076_ADDR 0x011c004cL
+#define IBU_P2_CETUS_CH0_076_STRIDE 1
+#define IBU_P2_CETUS_CH0_076_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_077_ADDR 0x011c004dL
+#define IBU_P2_CETUS_CH0_077_STRIDE 1
+#define IBU_P2_CETUS_CH0_077_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_078_ADDR 0x011c004eL
+#define IBU_P2_CETUS_CH0_078_STRIDE 1
+#define IBU_P2_CETUS_CH0_078_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_079_ADDR 0x011c004fL
+#define IBU_P2_CETUS_CH0_079_STRIDE 1
+#define IBU_P2_CETUS_CH0_079_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_080_ADDR 0x011c0050L
+#define IBU_P2_CETUS_CH0_080_STRIDE 1
+#define IBU_P2_CETUS_CH0_080_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_081_ADDR 0x011c0051L
+#define IBU_P2_CETUS_CH0_081_STRIDE 1
+#define IBU_P2_CETUS_CH0_081_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_082_ADDR 0x011c0052L
+#define IBU_P2_CETUS_CH0_082_STRIDE 1
+#define IBU_P2_CETUS_CH0_082_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_083_ADDR 0x011c0053L
+#define IBU_P2_CETUS_CH0_083_STRIDE 1
+#define IBU_P2_CETUS_CH0_083_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_084_ADDR 0x011c0054L
+#define IBU_P2_CETUS_CH0_084_STRIDE 1
+#define IBU_P2_CETUS_CH0_084_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_085_ADDR 0x011c0055L
+#define IBU_P2_CETUS_CH0_085_STRIDE 1
+#define IBU_P2_CETUS_CH0_085_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_086_ADDR 0x011c0056L
+#define IBU_P2_CETUS_CH0_086_STRIDE 1
+#define IBU_P2_CETUS_CH0_086_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_087_ADDR 0x011c0057L
+#define IBU_P2_CETUS_CH0_087_STRIDE 1
+#define IBU_P2_CETUS_CH0_087_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_088_ADDR 0x011c0058L
+#define IBU_P2_CETUS_CH0_088_STRIDE 1
+#define IBU_P2_CETUS_CH0_088_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_089_ADDR 0x011c0059L
+#define IBU_P2_CETUS_CH0_089_STRIDE 1
+#define IBU_P2_CETUS_CH0_089_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_090_ADDR 0x011c005aL
+#define IBU_P2_CETUS_CH0_090_STRIDE 1
+#define IBU_P2_CETUS_CH0_090_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_091_ADDR 0x011c005bL
+#define IBU_P2_CETUS_CH0_091_STRIDE 1
+#define IBU_P2_CETUS_CH0_091_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_092_ADDR 0x011c005cL
+#define IBU_P2_CETUS_CH0_092_STRIDE 1
+#define IBU_P2_CETUS_CH0_092_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_093_ADDR 0x011c005dL
+#define IBU_P2_CETUS_CH0_093_STRIDE 1
+#define IBU_P2_CETUS_CH0_093_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_094_ADDR 0x011c005eL
+#define IBU_P2_CETUS_CH0_094_STRIDE 1
+#define IBU_P2_CETUS_CH0_094_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_095_ADDR 0x011c005fL
+#define IBU_P2_CETUS_CH0_095_STRIDE 1
+#define IBU_P2_CETUS_CH0_095_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_096_ADDR 0x011c0060L
+#define IBU_P2_CETUS_CH0_096_STRIDE 1
+#define IBU_P2_CETUS_CH0_096_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_097_ADDR 0x011c0061L
+#define IBU_P2_CETUS_CH0_097_STRIDE 1
+#define IBU_P2_CETUS_CH0_097_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_098_ADDR 0x011c0062L
+#define IBU_P2_CETUS_CH0_098_STRIDE 1
+#define IBU_P2_CETUS_CH0_098_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_099_ADDR 0x011c0063L
+#define IBU_P2_CETUS_CH0_099_STRIDE 1
+#define IBU_P2_CETUS_CH0_099_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_100_ADDR 0x011c0064L
+#define IBU_P2_CETUS_CH0_100_STRIDE 1
+#define IBU_P2_CETUS_CH0_100_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_101_ADDR 0x011c0065L
+#define IBU_P2_CETUS_CH0_101_STRIDE 1
+#define IBU_P2_CETUS_CH0_101_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_102_ADDR 0x011c0066L
+#define IBU_P2_CETUS_CH0_102_STRIDE 1
+#define IBU_P2_CETUS_CH0_102_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_103_ADDR 0x011c0067L
+#define IBU_P2_CETUS_CH0_103_STRIDE 1
+#define IBU_P2_CETUS_CH0_103_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_104_ADDR 0x011c0068L
+#define IBU_P2_CETUS_CH0_104_STRIDE 1
+#define IBU_P2_CETUS_CH0_104_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_105_ADDR 0x011c0069L
+#define IBU_P2_CETUS_CH0_105_STRIDE 1
+#define IBU_P2_CETUS_CH0_105_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_106_ADDR 0x011c006aL
+#define IBU_P2_CETUS_CH0_106_STRIDE 1
+#define IBU_P2_CETUS_CH0_106_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_107_ADDR 0x011c006bL
+#define IBU_P2_CETUS_CH0_107_STRIDE 1
+#define IBU_P2_CETUS_CH0_107_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_108_ADDR 0x011c006cL
+#define IBU_P2_CETUS_CH0_108_STRIDE 1
+#define IBU_P2_CETUS_CH0_108_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_109_ADDR 0x011c006dL
+#define IBU_P2_CETUS_CH0_109_STRIDE 1
+#define IBU_P2_CETUS_CH0_109_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_110_ADDR 0x011c006eL
+#define IBU_P2_CETUS_CH0_110_STRIDE 1
+#define IBU_P2_CETUS_CH0_110_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_111_ADDR 0x011c006fL
+#define IBU_P2_CETUS_CH0_111_STRIDE 1
+#define IBU_P2_CETUS_CH0_111_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_112_ADDR 0x011c0070L
+#define IBU_P2_CETUS_CH0_112_STRIDE 1
+#define IBU_P2_CETUS_CH0_112_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_113_ADDR 0x011c0071L
+#define IBU_P2_CETUS_CH0_113_STRIDE 1
+#define IBU_P2_CETUS_CH0_113_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_114_ADDR 0x011c0072L
+#define IBU_P2_CETUS_CH0_114_STRIDE 1
+#define IBU_P2_CETUS_CH0_114_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_115_ADDR 0x011c0073L
+#define IBU_P2_CETUS_CH0_115_STRIDE 1
+#define IBU_P2_CETUS_CH0_115_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_116_ADDR 0x011c0074L
+#define IBU_P2_CETUS_CH0_116_STRIDE 1
+#define IBU_P2_CETUS_CH0_116_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_117_ADDR 0x011c0075L
+#define IBU_P2_CETUS_CH0_117_STRIDE 1
+#define IBU_P2_CETUS_CH0_117_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_118_ADDR 0x011c0076L
+#define IBU_P2_CETUS_CH0_118_STRIDE 1
+#define IBU_P2_CETUS_CH0_118_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_119_ADDR 0x011c0077L
+#define IBU_P2_CETUS_CH0_119_STRIDE 1
+#define IBU_P2_CETUS_CH0_119_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_120_ADDR 0x011c0078L
+#define IBU_P2_CETUS_CH0_120_STRIDE 1
+#define IBU_P2_CETUS_CH0_120_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_121_ADDR 0x011c0079L
+#define IBU_P2_CETUS_CH0_121_STRIDE 1
+#define IBU_P2_CETUS_CH0_121_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_122_ADDR 0x011c007aL
+#define IBU_P2_CETUS_CH0_122_STRIDE 1
+#define IBU_P2_CETUS_CH0_122_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_123_ADDR 0x011c007bL
+#define IBU_P2_CETUS_CH0_123_STRIDE 1
+#define IBU_P2_CETUS_CH0_123_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_124_ADDR 0x011c007cL
+#define IBU_P2_CETUS_CH0_124_STRIDE 1
+#define IBU_P2_CETUS_CH0_124_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_125_ADDR 0x011c007dL
+#define IBU_P2_CETUS_CH0_125_STRIDE 1
+#define IBU_P2_CETUS_CH0_125_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_126_ADDR 0x011c007eL
+#define IBU_P2_CETUS_CH0_126_STRIDE 1
+#define IBU_P2_CETUS_CH0_126_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_127_ADDR 0x011c007fL
+#define IBU_P2_CETUS_CH0_127_STRIDE 1
+#define IBU_P2_CETUS_CH0_127_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_128_ADDR 0x011c0080L
+#define IBU_P2_CETUS_CH0_128_STRIDE 1
+#define IBU_P2_CETUS_CH0_128_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_129_ADDR 0x011c0081L
+#define IBU_P2_CETUS_CH0_129_STRIDE 1
+#define IBU_P2_CETUS_CH0_129_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_130_ADDR 0x011c0082L
+#define IBU_P2_CETUS_CH0_130_STRIDE 1
+#define IBU_P2_CETUS_CH0_130_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_131_ADDR 0x011c0083L
+#define IBU_P2_CETUS_CH0_131_STRIDE 1
+#define IBU_P2_CETUS_CH0_131_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_132_ADDR 0x011c0084L
+#define IBU_P2_CETUS_CH0_132_STRIDE 1
+#define IBU_P2_CETUS_CH0_132_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_133_ADDR 0x011c0085L
+#define IBU_P2_CETUS_CH0_133_STRIDE 1
+#define IBU_P2_CETUS_CH0_133_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_134_ADDR 0x011c0086L
+#define IBU_P2_CETUS_CH0_134_STRIDE 1
+#define IBU_P2_CETUS_CH0_134_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_135_ADDR 0x011c0087L
+#define IBU_P2_CETUS_CH0_135_STRIDE 1
+#define IBU_P2_CETUS_CH0_135_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_136_ADDR 0x011c0088L
+#define IBU_P2_CETUS_CH0_136_STRIDE 1
+#define IBU_P2_CETUS_CH0_136_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_137_ADDR 0x011c0089L
+#define IBU_P2_CETUS_CH0_137_STRIDE 1
+#define IBU_P2_CETUS_CH0_137_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_138_ADDR 0x011c008aL
+#define IBU_P2_CETUS_CH0_138_STRIDE 1
+#define IBU_P2_CETUS_CH0_138_DEPTH 1
+
+#define IBU_P2_CETUS_CH0_139_ADDR 0x011c008bL
+#define IBU_P2_CETUS_CH0_139_STRIDE 1
+#define IBU_P2_CETUS_CH0_139_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH1_000_ADDR 0x011c0100L
+#define IBU_P2_CETUS_CH1_000_STRIDE 1
+#define IBU_P2_CETUS_CH1_000_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH1_001_ADDR 0x011c0101L
+#define IBU_P2_CETUS_CH1_001_STRIDE 1
+#define IBU_P2_CETUS_CH1_001_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH1_002_ADDR 0x011c0102L
+#define IBU_P2_CETUS_CH1_002_STRIDE 1
+#define IBU_P2_CETUS_CH1_002_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_003_ADDR 0x011c0103L
+#define IBU_P2_CETUS_CH1_003_STRIDE 1
+#define IBU_P2_CETUS_CH1_003_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_004_ADDR 0x011c0104L
+#define IBU_P2_CETUS_CH1_004_STRIDE 1
+#define IBU_P2_CETUS_CH1_004_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_005_ADDR 0x011c0105L
+#define IBU_P2_CETUS_CH1_005_STRIDE 1
+#define IBU_P2_CETUS_CH1_005_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_006_ADDR 0x011c0106L
+#define IBU_P2_CETUS_CH1_006_STRIDE 1
+#define IBU_P2_CETUS_CH1_006_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_007_ADDR 0x011c0107L
+#define IBU_P2_CETUS_CH1_007_STRIDE 1
+#define IBU_P2_CETUS_CH1_007_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_008_ADDR 0x011c0108L
+#define IBU_P2_CETUS_CH1_008_STRIDE 1
+#define IBU_P2_CETUS_CH1_008_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_009_ADDR 0x011c0109L
+#define IBU_P2_CETUS_CH1_009_STRIDE 1
+#define IBU_P2_CETUS_CH1_009_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_010_ADDR 0x011c010aL
+#define IBU_P2_CETUS_CH1_010_STRIDE 1
+#define IBU_P2_CETUS_CH1_010_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_011_ADDR 0x011c010bL
+#define IBU_P2_CETUS_CH1_011_STRIDE 1
+#define IBU_P2_CETUS_CH1_011_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_012_ADDR 0x011c010cL
+#define IBU_P2_CETUS_CH1_012_STRIDE 1
+#define IBU_P2_CETUS_CH1_012_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_013_ADDR 0x011c010dL
+#define IBU_P2_CETUS_CH1_013_STRIDE 1
+#define IBU_P2_CETUS_CH1_013_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_014_ADDR 0x011c010eL
+#define IBU_P2_CETUS_CH1_014_STRIDE 1
+#define IBU_P2_CETUS_CH1_014_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_015_ADDR 0x011c010fL
+#define IBU_P2_CETUS_CH1_015_STRIDE 1
+#define IBU_P2_CETUS_CH1_015_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_016_ADDR 0x011c0110L
+#define IBU_P2_CETUS_CH1_016_STRIDE 1
+#define IBU_P2_CETUS_CH1_016_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_017_ADDR 0x011c0111L
+#define IBU_P2_CETUS_CH1_017_STRIDE 1
+#define IBU_P2_CETUS_CH1_017_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_018_ADDR 0x011c0112L
+#define IBU_P2_CETUS_CH1_018_STRIDE 1
+#define IBU_P2_CETUS_CH1_018_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_019_ADDR 0x011c0113L
+#define IBU_P2_CETUS_CH1_019_STRIDE 1
+#define IBU_P2_CETUS_CH1_019_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_020_ADDR 0x011c0114L
+#define IBU_P2_CETUS_CH1_020_STRIDE 1
+#define IBU_P2_CETUS_CH1_020_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_021_ADDR 0x011c0115L
+#define IBU_P2_CETUS_CH1_021_STRIDE 1
+#define IBU_P2_CETUS_CH1_021_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_022_ADDR 0x011c0116L
+#define IBU_P2_CETUS_CH1_022_STRIDE 1
+#define IBU_P2_CETUS_CH1_022_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_023_ADDR 0x011c0117L
+#define IBU_P2_CETUS_CH1_023_STRIDE 1
+#define IBU_P2_CETUS_CH1_023_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_024_ADDR 0x011c0118L
+#define IBU_P2_CETUS_CH1_024_STRIDE 1
+#define IBU_P2_CETUS_CH1_024_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_025_ADDR 0x011c0119L
+#define IBU_P2_CETUS_CH1_025_STRIDE 1
+#define IBU_P2_CETUS_CH1_025_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_026_ADDR 0x011c011aL
+#define IBU_P2_CETUS_CH1_026_STRIDE 1
+#define IBU_P2_CETUS_CH1_026_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_027_ADDR 0x011c011bL
+#define IBU_P2_CETUS_CH1_027_STRIDE 1
+#define IBU_P2_CETUS_CH1_027_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_028_ADDR 0x011c011cL
+#define IBU_P2_CETUS_CH1_028_STRIDE 1
+#define IBU_P2_CETUS_CH1_028_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_029_ADDR 0x011c011dL
+#define IBU_P2_CETUS_CH1_029_STRIDE 1
+#define IBU_P2_CETUS_CH1_029_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_030_ADDR 0x011c011eL
+#define IBU_P2_CETUS_CH1_030_STRIDE 1
+#define IBU_P2_CETUS_CH1_030_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_031_ADDR 0x011c011fL
+#define IBU_P2_CETUS_CH1_031_STRIDE 1
+#define IBU_P2_CETUS_CH1_031_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_032_ADDR 0x011c0120L
+#define IBU_P2_CETUS_CH1_032_STRIDE 1
+#define IBU_P2_CETUS_CH1_032_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_033_ADDR 0x011c0121L
+#define IBU_P2_CETUS_CH1_033_STRIDE 1
+#define IBU_P2_CETUS_CH1_033_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_034_ADDR 0x011c0122L
+#define IBU_P2_CETUS_CH1_034_STRIDE 1
+#define IBU_P2_CETUS_CH1_034_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_035_ADDR 0x011c0123L
+#define IBU_P2_CETUS_CH1_035_STRIDE 1
+#define IBU_P2_CETUS_CH1_035_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_036_ADDR 0x011c0124L
+#define IBU_P2_CETUS_CH1_036_STRIDE 1
+#define IBU_P2_CETUS_CH1_036_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_037_ADDR 0x011c0125L
+#define IBU_P2_CETUS_CH1_037_STRIDE 1
+#define IBU_P2_CETUS_CH1_037_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_038_ADDR 0x011c0126L
+#define IBU_P2_CETUS_CH1_038_STRIDE 1
+#define IBU_P2_CETUS_CH1_038_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_039_ADDR 0x011c0127L
+#define IBU_P2_CETUS_CH1_039_STRIDE 1
+#define IBU_P2_CETUS_CH1_039_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_040_ADDR 0x011c0128L
+#define IBU_P2_CETUS_CH1_040_STRIDE 1
+#define IBU_P2_CETUS_CH1_040_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_041_ADDR 0x011c0129L
+#define IBU_P2_CETUS_CH1_041_STRIDE 1
+#define IBU_P2_CETUS_CH1_041_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_042_ADDR 0x011c012aL
+#define IBU_P2_CETUS_CH1_042_STRIDE 1
+#define IBU_P2_CETUS_CH1_042_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_043_ADDR 0x011c012bL
+#define IBU_P2_CETUS_CH1_043_STRIDE 1
+#define IBU_P2_CETUS_CH1_043_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_044_ADDR 0x011c012cL
+#define IBU_P2_CETUS_CH1_044_STRIDE 1
+#define IBU_P2_CETUS_CH1_044_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_045_ADDR 0x011c012dL
+#define IBU_P2_CETUS_CH1_045_STRIDE 1
+#define IBU_P2_CETUS_CH1_045_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_046_ADDR 0x011c012eL
+#define IBU_P2_CETUS_CH1_046_STRIDE 1
+#define IBU_P2_CETUS_CH1_046_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_047_ADDR 0x011c012fL
+#define IBU_P2_CETUS_CH1_047_STRIDE 1
+#define IBU_P2_CETUS_CH1_047_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_048_ADDR 0x011c0130L
+#define IBU_P2_CETUS_CH1_048_STRIDE 1
+#define IBU_P2_CETUS_CH1_048_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_049_ADDR 0x011c0131L
+#define IBU_P2_CETUS_CH1_049_STRIDE 1
+#define IBU_P2_CETUS_CH1_049_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_050_ADDR 0x011c0132L
+#define IBU_P2_CETUS_CH1_050_STRIDE 1
+#define IBU_P2_CETUS_CH1_050_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_051_ADDR 0x011c0133L
+#define IBU_P2_CETUS_CH1_051_STRIDE 1
+#define IBU_P2_CETUS_CH1_051_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_052_ADDR 0x011c0134L
+#define IBU_P2_CETUS_CH1_052_STRIDE 1
+#define IBU_P2_CETUS_CH1_052_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_053_ADDR 0x011c0135L
+#define IBU_P2_CETUS_CH1_053_STRIDE 1
+#define IBU_P2_CETUS_CH1_053_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_054_ADDR 0x011c0136L
+#define IBU_P2_CETUS_CH1_054_STRIDE 1
+#define IBU_P2_CETUS_CH1_054_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_055_ADDR 0x011c0137L
+#define IBU_P2_CETUS_CH1_055_STRIDE 1
+#define IBU_P2_CETUS_CH1_055_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_056_ADDR 0x011c0138L
+#define IBU_P2_CETUS_CH1_056_STRIDE 1
+#define IBU_P2_CETUS_CH1_056_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_057_ADDR 0x011c0139L
+#define IBU_P2_CETUS_CH1_057_STRIDE 1
+#define IBU_P2_CETUS_CH1_057_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_058_ADDR 0x011c013aL
+#define IBU_P2_CETUS_CH1_058_STRIDE 1
+#define IBU_P2_CETUS_CH1_058_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_059_ADDR 0x011c013bL
+#define IBU_P2_CETUS_CH1_059_STRIDE 1
+#define IBU_P2_CETUS_CH1_059_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_060_ADDR 0x011c013cL
+#define IBU_P2_CETUS_CH1_060_STRIDE 1
+#define IBU_P2_CETUS_CH1_060_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_061_ADDR 0x011c013dL
+#define IBU_P2_CETUS_CH1_061_STRIDE 1
+#define IBU_P2_CETUS_CH1_061_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_062_ADDR 0x011c013eL
+#define IBU_P2_CETUS_CH1_062_STRIDE 1
+#define IBU_P2_CETUS_CH1_062_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_063_ADDR 0x011c013fL
+#define IBU_P2_CETUS_CH1_063_STRIDE 1
+#define IBU_P2_CETUS_CH1_063_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_064_ADDR 0x011c0140L
+#define IBU_P2_CETUS_CH1_064_STRIDE 1
+#define IBU_P2_CETUS_CH1_064_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_065_ADDR 0x011c0141L
+#define IBU_P2_CETUS_CH1_065_STRIDE 1
+#define IBU_P2_CETUS_CH1_065_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_066_ADDR 0x011c0142L
+#define IBU_P2_CETUS_CH1_066_STRIDE 1
+#define IBU_P2_CETUS_CH1_066_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_067_ADDR 0x011c0143L
+#define IBU_P2_CETUS_CH1_067_STRIDE 1
+#define IBU_P2_CETUS_CH1_067_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_068_ADDR 0x011c0144L
+#define IBU_P2_CETUS_CH1_068_STRIDE 1
+#define IBU_P2_CETUS_CH1_068_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_069_ADDR 0x011c0145L
+#define IBU_P2_CETUS_CH1_069_STRIDE 1
+#define IBU_P2_CETUS_CH1_069_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_070_ADDR 0x011c0146L
+#define IBU_P2_CETUS_CH1_070_STRIDE 1
+#define IBU_P2_CETUS_CH1_070_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_071_ADDR 0x011c0147L
+#define IBU_P2_CETUS_CH1_071_STRIDE 1
+#define IBU_P2_CETUS_CH1_071_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_072_ADDR 0x011c0148L
+#define IBU_P2_CETUS_CH1_072_STRIDE 1
+#define IBU_P2_CETUS_CH1_072_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_073_ADDR 0x011c0149L
+#define IBU_P2_CETUS_CH1_073_STRIDE 1
+#define IBU_P2_CETUS_CH1_073_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_074_ADDR 0x011c014aL
+#define IBU_P2_CETUS_CH1_074_STRIDE 1
+#define IBU_P2_CETUS_CH1_074_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_075_ADDR 0x011c014bL
+#define IBU_P2_CETUS_CH1_075_STRIDE 1
+#define IBU_P2_CETUS_CH1_075_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_076_ADDR 0x011c014cL
+#define IBU_P2_CETUS_CH1_076_STRIDE 1
+#define IBU_P2_CETUS_CH1_076_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_077_ADDR 0x011c014dL
+#define IBU_P2_CETUS_CH1_077_STRIDE 1
+#define IBU_P2_CETUS_CH1_077_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_078_ADDR 0x011c014eL
+#define IBU_P2_CETUS_CH1_078_STRIDE 1
+#define IBU_P2_CETUS_CH1_078_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_079_ADDR 0x011c014fL
+#define IBU_P2_CETUS_CH1_079_STRIDE 1
+#define IBU_P2_CETUS_CH1_079_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_080_ADDR 0x011c0150L
+#define IBU_P2_CETUS_CH1_080_STRIDE 1
+#define IBU_P2_CETUS_CH1_080_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_081_ADDR 0x011c0151L
+#define IBU_P2_CETUS_CH1_081_STRIDE 1
+#define IBU_P2_CETUS_CH1_081_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_082_ADDR 0x011c0152L
+#define IBU_P2_CETUS_CH1_082_STRIDE 1
+#define IBU_P2_CETUS_CH1_082_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_083_ADDR 0x011c0153L
+#define IBU_P2_CETUS_CH1_083_STRIDE 1
+#define IBU_P2_CETUS_CH1_083_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_084_ADDR 0x011c0154L
+#define IBU_P2_CETUS_CH1_084_STRIDE 1
+#define IBU_P2_CETUS_CH1_084_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_085_ADDR 0x011c0155L
+#define IBU_P2_CETUS_CH1_085_STRIDE 1
+#define IBU_P2_CETUS_CH1_085_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_086_ADDR 0x011c0156L
+#define IBU_P2_CETUS_CH1_086_STRIDE 1
+#define IBU_P2_CETUS_CH1_086_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_087_ADDR 0x011c0157L
+#define IBU_P2_CETUS_CH1_087_STRIDE 1
+#define IBU_P2_CETUS_CH1_087_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_088_ADDR 0x011c0158L
+#define IBU_P2_CETUS_CH1_088_STRIDE 1
+#define IBU_P2_CETUS_CH1_088_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_089_ADDR 0x011c0159L
+#define IBU_P2_CETUS_CH1_089_STRIDE 1
+#define IBU_P2_CETUS_CH1_089_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_090_ADDR 0x011c015aL
+#define IBU_P2_CETUS_CH1_090_STRIDE 1
+#define IBU_P2_CETUS_CH1_090_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_091_ADDR 0x011c015bL
+#define IBU_P2_CETUS_CH1_091_STRIDE 1
+#define IBU_P2_CETUS_CH1_091_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_092_ADDR 0x011c015cL
+#define IBU_P2_CETUS_CH1_092_STRIDE 1
+#define IBU_P2_CETUS_CH1_092_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_093_ADDR 0x011c015dL
+#define IBU_P2_CETUS_CH1_093_STRIDE 1
+#define IBU_P2_CETUS_CH1_093_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_094_ADDR 0x011c015eL
+#define IBU_P2_CETUS_CH1_094_STRIDE 1
+#define IBU_P2_CETUS_CH1_094_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_095_ADDR 0x011c015fL
+#define IBU_P2_CETUS_CH1_095_STRIDE 1
+#define IBU_P2_CETUS_CH1_095_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_096_ADDR 0x011c0160L
+#define IBU_P2_CETUS_CH1_096_STRIDE 1
+#define IBU_P2_CETUS_CH1_096_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_097_ADDR 0x011c0161L
+#define IBU_P2_CETUS_CH1_097_STRIDE 1
+#define IBU_P2_CETUS_CH1_097_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_098_ADDR 0x011c0162L
+#define IBU_P2_CETUS_CH1_098_STRIDE 1
+#define IBU_P2_CETUS_CH1_098_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_099_ADDR 0x011c0163L
+#define IBU_P2_CETUS_CH1_099_STRIDE 1
+#define IBU_P2_CETUS_CH1_099_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_100_ADDR 0x011c0164L
+#define IBU_P2_CETUS_CH1_100_STRIDE 1
+#define IBU_P2_CETUS_CH1_100_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_101_ADDR 0x011c0165L
+#define IBU_P2_CETUS_CH1_101_STRIDE 1
+#define IBU_P2_CETUS_CH1_101_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_102_ADDR 0x011c0166L
+#define IBU_P2_CETUS_CH1_102_STRIDE 1
+#define IBU_P2_CETUS_CH1_102_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_103_ADDR 0x011c0167L
+#define IBU_P2_CETUS_CH1_103_STRIDE 1
+#define IBU_P2_CETUS_CH1_103_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_104_ADDR 0x011c0168L
+#define IBU_P2_CETUS_CH1_104_STRIDE 1
+#define IBU_P2_CETUS_CH1_104_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_105_ADDR 0x011c0169L
+#define IBU_P2_CETUS_CH1_105_STRIDE 1
+#define IBU_P2_CETUS_CH1_105_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_106_ADDR 0x011c016aL
+#define IBU_P2_CETUS_CH1_106_STRIDE 1
+#define IBU_P2_CETUS_CH1_106_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_107_ADDR 0x011c016bL
+#define IBU_P2_CETUS_CH1_107_STRIDE 1
+#define IBU_P2_CETUS_CH1_107_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_108_ADDR 0x011c016cL
+#define IBU_P2_CETUS_CH1_108_STRIDE 1
+#define IBU_P2_CETUS_CH1_108_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_109_ADDR 0x011c016dL
+#define IBU_P2_CETUS_CH1_109_STRIDE 1
+#define IBU_P2_CETUS_CH1_109_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_110_ADDR 0x011c016eL
+#define IBU_P2_CETUS_CH1_110_STRIDE 1
+#define IBU_P2_CETUS_CH1_110_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_111_ADDR 0x011c016fL
+#define IBU_P2_CETUS_CH1_111_STRIDE 1
+#define IBU_P2_CETUS_CH1_111_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_112_ADDR 0x011c0170L
+#define IBU_P2_CETUS_CH1_112_STRIDE 1
+#define IBU_P2_CETUS_CH1_112_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_113_ADDR 0x011c0171L
+#define IBU_P2_CETUS_CH1_113_STRIDE 1
+#define IBU_P2_CETUS_CH1_113_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_114_ADDR 0x011c0172L
+#define IBU_P2_CETUS_CH1_114_STRIDE 1
+#define IBU_P2_CETUS_CH1_114_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_115_ADDR 0x011c0173L
+#define IBU_P2_CETUS_CH1_115_STRIDE 1
+#define IBU_P2_CETUS_CH1_115_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_116_ADDR 0x011c0174L
+#define IBU_P2_CETUS_CH1_116_STRIDE 1
+#define IBU_P2_CETUS_CH1_116_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_117_ADDR 0x011c0175L
+#define IBU_P2_CETUS_CH1_117_STRIDE 1
+#define IBU_P2_CETUS_CH1_117_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_118_ADDR 0x011c0176L
+#define IBU_P2_CETUS_CH1_118_STRIDE 1
+#define IBU_P2_CETUS_CH1_118_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_119_ADDR 0x011c0177L
+#define IBU_P2_CETUS_CH1_119_STRIDE 1
+#define IBU_P2_CETUS_CH1_119_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_120_ADDR 0x011c0178L
+#define IBU_P2_CETUS_CH1_120_STRIDE 1
+#define IBU_P2_CETUS_CH1_120_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_121_ADDR 0x011c0179L
+#define IBU_P2_CETUS_CH1_121_STRIDE 1
+#define IBU_P2_CETUS_CH1_121_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_122_ADDR 0x011c017aL
+#define IBU_P2_CETUS_CH1_122_STRIDE 1
+#define IBU_P2_CETUS_CH1_122_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_123_ADDR 0x011c017bL
+#define IBU_P2_CETUS_CH1_123_STRIDE 1
+#define IBU_P2_CETUS_CH1_123_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_124_ADDR 0x011c017cL
+#define IBU_P2_CETUS_CH1_124_STRIDE 1
+#define IBU_P2_CETUS_CH1_124_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_125_ADDR 0x011c017dL
+#define IBU_P2_CETUS_CH1_125_STRIDE 1
+#define IBU_P2_CETUS_CH1_125_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_126_ADDR 0x011c017eL
+#define IBU_P2_CETUS_CH1_126_STRIDE 1
+#define IBU_P2_CETUS_CH1_126_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_127_ADDR 0x011c017fL
+#define IBU_P2_CETUS_CH1_127_STRIDE 1
+#define IBU_P2_CETUS_CH1_127_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_128_ADDR 0x011c0180L
+#define IBU_P2_CETUS_CH1_128_STRIDE 1
+#define IBU_P2_CETUS_CH1_128_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_129_ADDR 0x011c0181L
+#define IBU_P2_CETUS_CH1_129_STRIDE 1
+#define IBU_P2_CETUS_CH1_129_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_130_ADDR 0x011c0182L
+#define IBU_P2_CETUS_CH1_130_STRIDE 1
+#define IBU_P2_CETUS_CH1_130_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_131_ADDR 0x011c0183L
+#define IBU_P2_CETUS_CH1_131_STRIDE 1
+#define IBU_P2_CETUS_CH1_131_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_132_ADDR 0x011c0184L
+#define IBU_P2_CETUS_CH1_132_STRIDE 1
+#define IBU_P2_CETUS_CH1_132_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_133_ADDR 0x011c0185L
+#define IBU_P2_CETUS_CH1_133_STRIDE 1
+#define IBU_P2_CETUS_CH1_133_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_134_ADDR 0x011c0186L
+#define IBU_P2_CETUS_CH1_134_STRIDE 1
+#define IBU_P2_CETUS_CH1_134_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_135_ADDR 0x011c0187L
+#define IBU_P2_CETUS_CH1_135_STRIDE 1
+#define IBU_P2_CETUS_CH1_135_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_136_ADDR 0x011c0188L
+#define IBU_P2_CETUS_CH1_136_STRIDE 1
+#define IBU_P2_CETUS_CH1_136_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_137_ADDR 0x011c0189L
+#define IBU_P2_CETUS_CH1_137_STRIDE 1
+#define IBU_P2_CETUS_CH1_137_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_138_ADDR 0x011c018aL
+#define IBU_P2_CETUS_CH1_138_STRIDE 1
+#define IBU_P2_CETUS_CH1_138_DEPTH 1
+
+#define IBU_P2_CETUS_CH1_139_ADDR 0x011c018bL
+#define IBU_P2_CETUS_CH1_139_STRIDE 1
+#define IBU_P2_CETUS_CH1_139_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_CONTROL0_ADDR 0x011c0200L
+#define IBU_P2_CETUS_PLLA_CONTROL0_STRIDE 1
+#define IBU_P2_CETUS_PLLA_CONTROL0_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_CONTROL1_ADDR 0x011c0201L
+#define IBU_P2_CETUS_PLLA_CONTROL1_STRIDE 1
+#define IBU_P2_CETUS_PLLA_CONTROL1_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_CONTROL2_ADDR 0x011c0202L
+#define IBU_P2_CETUS_PLLA_CONTROL2_STRIDE 1
+#define IBU_P2_CETUS_PLLA_CONTROL2_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_EXTFB_CNTR_ADDR 0x011c0203L
+#define IBU_P2_CETUS_PLLA_EXTFB_CNTR_STRIDE 1
+#define IBU_P2_CETUS_PLLA_EXTFB_CNTR_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_FBCNT_ATO_ADDR 0x011c0204L
+#define IBU_P2_CETUS_PLLA_FBCNT_ATO_STRIDE 1
+#define IBU_P2_CETUS_PLLA_FBCNT_ATO_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_SPARE_USRCNTR_ADDR 0x011c0205L
+#define IBU_P2_CETUS_PLLA_SPARE_USRCNTR_STRIDE 1
+#define IBU_P2_CETUS_PLLA_SPARE_USRCNTR_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_DIV_EN_ADDR 0x011c0206L
+#define IBU_P2_CETUS_PLLA_DIV_EN_STRIDE 1
+#define IBU_P2_CETUS_PLLA_DIV_EN_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_VCO_WAIT_CNT_ADDR 0x011c0207L
+#define IBU_P2_CETUS_PLLA_VCO_WAIT_CNT_STRIDE 1
+#define IBU_P2_CETUS_PLLA_VCO_WAIT_CNT_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_STATUS0_ADDR 0x011c0208L
+#define IBU_P2_CETUS_PLLA_STATUS0_STRIDE 1
+#define IBU_P2_CETUS_PLLA_STATUS0_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_STATUS1_ADDR 0x011c0209L
+#define IBU_P2_CETUS_PLLA_STATUS1_STRIDE 1
+#define IBU_P2_CETUS_PLLA_STATUS1_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_010_ADDR 0x011c020aL
+#define IBU_P2_CETUS_PLLA_010_STRIDE 1
+#define IBU_P2_CETUS_PLLA_010_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_011_ADDR 0x011c020bL
+#define IBU_P2_CETUS_PLLA_011_STRIDE 1
+#define IBU_P2_CETUS_PLLA_011_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_012_ADDR 0x011c020cL
+#define IBU_P2_CETUS_PLLA_012_STRIDE 1
+#define IBU_P2_CETUS_PLLA_012_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_013_ADDR 0x011c020dL
+#define IBU_P2_CETUS_PLLA_013_STRIDE 1
+#define IBU_P2_CETUS_PLLA_013_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_014_ADDR 0x011c020eL
+#define IBU_P2_CETUS_PLLA_014_STRIDE 1
+#define IBU_P2_CETUS_PLLA_014_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_015_ADDR 0x011c020fL
+#define IBU_P2_CETUS_PLLA_015_STRIDE 1
+#define IBU_P2_CETUS_PLLA_015_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_016_ADDR 0x011c0210L
+#define IBU_P2_CETUS_PLLA_016_STRIDE 1
+#define IBU_P2_CETUS_PLLA_016_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_017_ADDR 0x011c0211L
+#define IBU_P2_CETUS_PLLA_017_STRIDE 1
+#define IBU_P2_CETUS_PLLA_017_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_018_ADDR 0x011c0212L
+#define IBU_P2_CETUS_PLLA_018_STRIDE 1
+#define IBU_P2_CETUS_PLLA_018_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_019_ADDR 0x011c0213L
+#define IBU_P2_CETUS_PLLA_019_STRIDE 1
+#define IBU_P2_CETUS_PLLA_019_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_020_ADDR 0x011c0214L
+#define IBU_P2_CETUS_PLLA_020_STRIDE 1
+#define IBU_P2_CETUS_PLLA_020_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_021_ADDR 0x011c0215L
+#define IBU_P2_CETUS_PLLA_021_STRIDE 1
+#define IBU_P2_CETUS_PLLA_021_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_022_ADDR 0x011c0216L
+#define IBU_P2_CETUS_PLLA_022_STRIDE 1
+#define IBU_P2_CETUS_PLLA_022_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_023_ADDR 0x011c0217L
+#define IBU_P2_CETUS_PLLA_023_STRIDE 1
+#define IBU_P2_CETUS_PLLA_023_DEPTH 1
+
+#define IBU_P2_CETUS_PLLA_024_ADDR 0x011c0218L
+#define IBU_P2_CETUS_PLLA_024_STRIDE 1
+#define IBU_P2_CETUS_PLLA_024_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH2_000_ADDR 0x011c0300L
+#define IBU_P2_CETUS_CH2_000_STRIDE 1
+#define IBU_P2_CETUS_CH2_000_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH2_001_ADDR 0x011c0301L
+#define IBU_P2_CETUS_CH2_001_STRIDE 1
+#define IBU_P2_CETUS_CH2_001_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH2_002_ADDR 0x011c0302L
+#define IBU_P2_CETUS_CH2_002_STRIDE 1
+#define IBU_P2_CETUS_CH2_002_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_003_ADDR 0x011c0303L
+#define IBU_P2_CETUS_CH2_003_STRIDE 1
+#define IBU_P2_CETUS_CH2_003_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_004_ADDR 0x011c0304L
+#define IBU_P2_CETUS_CH2_004_STRIDE 1
+#define IBU_P2_CETUS_CH2_004_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_005_ADDR 0x011c0305L
+#define IBU_P2_CETUS_CH2_005_STRIDE 1
+#define IBU_P2_CETUS_CH2_005_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_006_ADDR 0x011c0306L
+#define IBU_P2_CETUS_CH2_006_STRIDE 1
+#define IBU_P2_CETUS_CH2_006_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_007_ADDR 0x011c0307L
+#define IBU_P2_CETUS_CH2_007_STRIDE 1
+#define IBU_P2_CETUS_CH2_007_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_008_ADDR 0x011c0308L
+#define IBU_P2_CETUS_CH2_008_STRIDE 1
+#define IBU_P2_CETUS_CH2_008_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_009_ADDR 0x011c0309L
+#define IBU_P2_CETUS_CH2_009_STRIDE 1
+#define IBU_P2_CETUS_CH2_009_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_010_ADDR 0x011c030aL
+#define IBU_P2_CETUS_CH2_010_STRIDE 1
+#define IBU_P2_CETUS_CH2_010_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_011_ADDR 0x011c030bL
+#define IBU_P2_CETUS_CH2_011_STRIDE 1
+#define IBU_P2_CETUS_CH2_011_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_012_ADDR 0x011c030cL
+#define IBU_P2_CETUS_CH2_012_STRIDE 1
+#define IBU_P2_CETUS_CH2_012_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_013_ADDR 0x011c030dL
+#define IBU_P2_CETUS_CH2_013_STRIDE 1
+#define IBU_P2_CETUS_CH2_013_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_014_ADDR 0x011c030eL
+#define IBU_P2_CETUS_CH2_014_STRIDE 1
+#define IBU_P2_CETUS_CH2_014_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_015_ADDR 0x011c030fL
+#define IBU_P2_CETUS_CH2_015_STRIDE 1
+#define IBU_P2_CETUS_CH2_015_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_016_ADDR 0x011c0310L
+#define IBU_P2_CETUS_CH2_016_STRIDE 1
+#define IBU_P2_CETUS_CH2_016_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_017_ADDR 0x011c0311L
+#define IBU_P2_CETUS_CH2_017_STRIDE 1
+#define IBU_P2_CETUS_CH2_017_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_018_ADDR 0x011c0312L
+#define IBU_P2_CETUS_CH2_018_STRIDE 1
+#define IBU_P2_CETUS_CH2_018_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_019_ADDR 0x011c0313L
+#define IBU_P2_CETUS_CH2_019_STRIDE 1
+#define IBU_P2_CETUS_CH2_019_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_020_ADDR 0x011c0314L
+#define IBU_P2_CETUS_CH2_020_STRIDE 1
+#define IBU_P2_CETUS_CH2_020_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_021_ADDR 0x011c0315L
+#define IBU_P2_CETUS_CH2_021_STRIDE 1
+#define IBU_P2_CETUS_CH2_021_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_022_ADDR 0x011c0316L
+#define IBU_P2_CETUS_CH2_022_STRIDE 1
+#define IBU_P2_CETUS_CH2_022_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_023_ADDR 0x011c0317L
+#define IBU_P2_CETUS_CH2_023_STRIDE 1
+#define IBU_P2_CETUS_CH2_023_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_024_ADDR 0x011c0318L
+#define IBU_P2_CETUS_CH2_024_STRIDE 1
+#define IBU_P2_CETUS_CH2_024_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_025_ADDR 0x011c0319L
+#define IBU_P2_CETUS_CH2_025_STRIDE 1
+#define IBU_P2_CETUS_CH2_025_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_026_ADDR 0x011c031aL
+#define IBU_P2_CETUS_CH2_026_STRIDE 1
+#define IBU_P2_CETUS_CH2_026_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_027_ADDR 0x011c031bL
+#define IBU_P2_CETUS_CH2_027_STRIDE 1
+#define IBU_P2_CETUS_CH2_027_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_028_ADDR 0x011c031cL
+#define IBU_P2_CETUS_CH2_028_STRIDE 1
+#define IBU_P2_CETUS_CH2_028_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_029_ADDR 0x011c031dL
+#define IBU_P2_CETUS_CH2_029_STRIDE 1
+#define IBU_P2_CETUS_CH2_029_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_030_ADDR 0x011c031eL
+#define IBU_P2_CETUS_CH2_030_STRIDE 1
+#define IBU_P2_CETUS_CH2_030_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_031_ADDR 0x011c031fL
+#define IBU_P2_CETUS_CH2_031_STRIDE 1
+#define IBU_P2_CETUS_CH2_031_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_032_ADDR 0x011c0320L
+#define IBU_P2_CETUS_CH2_032_STRIDE 1
+#define IBU_P2_CETUS_CH2_032_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_033_ADDR 0x011c0321L
+#define IBU_P2_CETUS_CH2_033_STRIDE 1
+#define IBU_P2_CETUS_CH2_033_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_034_ADDR 0x011c0322L
+#define IBU_P2_CETUS_CH2_034_STRIDE 1
+#define IBU_P2_CETUS_CH2_034_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_035_ADDR 0x011c0323L
+#define IBU_P2_CETUS_CH2_035_STRIDE 1
+#define IBU_P2_CETUS_CH2_035_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_036_ADDR 0x011c0324L
+#define IBU_P2_CETUS_CH2_036_STRIDE 1
+#define IBU_P2_CETUS_CH2_036_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_037_ADDR 0x011c0325L
+#define IBU_P2_CETUS_CH2_037_STRIDE 1
+#define IBU_P2_CETUS_CH2_037_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_038_ADDR 0x011c0326L
+#define IBU_P2_CETUS_CH2_038_STRIDE 1
+#define IBU_P2_CETUS_CH2_038_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_039_ADDR 0x011c0327L
+#define IBU_P2_CETUS_CH2_039_STRIDE 1
+#define IBU_P2_CETUS_CH2_039_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_040_ADDR 0x011c0328L
+#define IBU_P2_CETUS_CH2_040_STRIDE 1
+#define IBU_P2_CETUS_CH2_040_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_041_ADDR 0x011c0329L
+#define IBU_P2_CETUS_CH2_041_STRIDE 1
+#define IBU_P2_CETUS_CH2_041_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_042_ADDR 0x011c032aL
+#define IBU_P2_CETUS_CH2_042_STRIDE 1
+#define IBU_P2_CETUS_CH2_042_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_043_ADDR 0x011c032bL
+#define IBU_P2_CETUS_CH2_043_STRIDE 1
+#define IBU_P2_CETUS_CH2_043_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_044_ADDR 0x011c032cL
+#define IBU_P2_CETUS_CH2_044_STRIDE 1
+#define IBU_P2_CETUS_CH2_044_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_045_ADDR 0x011c032dL
+#define IBU_P2_CETUS_CH2_045_STRIDE 1
+#define IBU_P2_CETUS_CH2_045_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_046_ADDR 0x011c032eL
+#define IBU_P2_CETUS_CH2_046_STRIDE 1
+#define IBU_P2_CETUS_CH2_046_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_047_ADDR 0x011c032fL
+#define IBU_P2_CETUS_CH2_047_STRIDE 1
+#define IBU_P2_CETUS_CH2_047_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_048_ADDR 0x011c0330L
+#define IBU_P2_CETUS_CH2_048_STRIDE 1
+#define IBU_P2_CETUS_CH2_048_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_049_ADDR 0x011c0331L
+#define IBU_P2_CETUS_CH2_049_STRIDE 1
+#define IBU_P2_CETUS_CH2_049_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_050_ADDR 0x011c0332L
+#define IBU_P2_CETUS_CH2_050_STRIDE 1
+#define IBU_P2_CETUS_CH2_050_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_051_ADDR 0x011c0333L
+#define IBU_P2_CETUS_CH2_051_STRIDE 1
+#define IBU_P2_CETUS_CH2_051_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_052_ADDR 0x011c0334L
+#define IBU_P2_CETUS_CH2_052_STRIDE 1
+#define IBU_P2_CETUS_CH2_052_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_053_ADDR 0x011c0335L
+#define IBU_P2_CETUS_CH2_053_STRIDE 1
+#define IBU_P2_CETUS_CH2_053_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_054_ADDR 0x011c0336L
+#define IBU_P2_CETUS_CH2_054_STRIDE 1
+#define IBU_P2_CETUS_CH2_054_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_055_ADDR 0x011c0337L
+#define IBU_P2_CETUS_CH2_055_STRIDE 1
+#define IBU_P2_CETUS_CH2_055_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_056_ADDR 0x011c0338L
+#define IBU_P2_CETUS_CH2_056_STRIDE 1
+#define IBU_P2_CETUS_CH2_056_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_057_ADDR 0x011c0339L
+#define IBU_P2_CETUS_CH2_057_STRIDE 1
+#define IBU_P2_CETUS_CH2_057_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_058_ADDR 0x011c033aL
+#define IBU_P2_CETUS_CH2_058_STRIDE 1
+#define IBU_P2_CETUS_CH2_058_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_059_ADDR 0x011c033bL
+#define IBU_P2_CETUS_CH2_059_STRIDE 1
+#define IBU_P2_CETUS_CH2_059_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_060_ADDR 0x011c033cL
+#define IBU_P2_CETUS_CH2_060_STRIDE 1
+#define IBU_P2_CETUS_CH2_060_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_061_ADDR 0x011c033dL
+#define IBU_P2_CETUS_CH2_061_STRIDE 1
+#define IBU_P2_CETUS_CH2_061_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_062_ADDR 0x011c033eL
+#define IBU_P2_CETUS_CH2_062_STRIDE 1
+#define IBU_P2_CETUS_CH2_062_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_063_ADDR 0x011c033fL
+#define IBU_P2_CETUS_CH2_063_STRIDE 1
+#define IBU_P2_CETUS_CH2_063_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_064_ADDR 0x011c0340L
+#define IBU_P2_CETUS_CH2_064_STRIDE 1
+#define IBU_P2_CETUS_CH2_064_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_065_ADDR 0x011c0341L
+#define IBU_P2_CETUS_CH2_065_STRIDE 1
+#define IBU_P2_CETUS_CH2_065_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_066_ADDR 0x011c0342L
+#define IBU_P2_CETUS_CH2_066_STRIDE 1
+#define IBU_P2_CETUS_CH2_066_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_067_ADDR 0x011c0343L
+#define IBU_P2_CETUS_CH2_067_STRIDE 1
+#define IBU_P2_CETUS_CH2_067_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_068_ADDR 0x011c0344L
+#define IBU_P2_CETUS_CH2_068_STRIDE 1
+#define IBU_P2_CETUS_CH2_068_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_069_ADDR 0x011c0345L
+#define IBU_P2_CETUS_CH2_069_STRIDE 1
+#define IBU_P2_CETUS_CH2_069_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_070_ADDR 0x011c0346L
+#define IBU_P2_CETUS_CH2_070_STRIDE 1
+#define IBU_P2_CETUS_CH2_070_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_071_ADDR 0x011c0347L
+#define IBU_P2_CETUS_CH2_071_STRIDE 1
+#define IBU_P2_CETUS_CH2_071_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_072_ADDR 0x011c0348L
+#define IBU_P2_CETUS_CH2_072_STRIDE 1
+#define IBU_P2_CETUS_CH2_072_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_073_ADDR 0x011c0349L
+#define IBU_P2_CETUS_CH2_073_STRIDE 1
+#define IBU_P2_CETUS_CH2_073_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_074_ADDR 0x011c034aL
+#define IBU_P2_CETUS_CH2_074_STRIDE 1
+#define IBU_P2_CETUS_CH2_074_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_075_ADDR 0x011c034bL
+#define IBU_P2_CETUS_CH2_075_STRIDE 1
+#define IBU_P2_CETUS_CH2_075_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_076_ADDR 0x011c034cL
+#define IBU_P2_CETUS_CH2_076_STRIDE 1
+#define IBU_P2_CETUS_CH2_076_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_077_ADDR 0x011c034dL
+#define IBU_P2_CETUS_CH2_077_STRIDE 1
+#define IBU_P2_CETUS_CH2_077_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_078_ADDR 0x011c034eL
+#define IBU_P2_CETUS_CH2_078_STRIDE 1
+#define IBU_P2_CETUS_CH2_078_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_079_ADDR 0x011c034fL
+#define IBU_P2_CETUS_CH2_079_STRIDE 1
+#define IBU_P2_CETUS_CH2_079_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_080_ADDR 0x011c0350L
+#define IBU_P2_CETUS_CH2_080_STRIDE 1
+#define IBU_P2_CETUS_CH2_080_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_081_ADDR 0x011c0351L
+#define IBU_P2_CETUS_CH2_081_STRIDE 1
+#define IBU_P2_CETUS_CH2_081_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_082_ADDR 0x011c0352L
+#define IBU_P2_CETUS_CH2_082_STRIDE 1
+#define IBU_P2_CETUS_CH2_082_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_083_ADDR 0x011c0353L
+#define IBU_P2_CETUS_CH2_083_STRIDE 1
+#define IBU_P2_CETUS_CH2_083_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_084_ADDR 0x011c0354L
+#define IBU_P2_CETUS_CH2_084_STRIDE 1
+#define IBU_P2_CETUS_CH2_084_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_085_ADDR 0x011c0355L
+#define IBU_P2_CETUS_CH2_085_STRIDE 1
+#define IBU_P2_CETUS_CH2_085_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_086_ADDR 0x011c0356L
+#define IBU_P2_CETUS_CH2_086_STRIDE 1
+#define IBU_P2_CETUS_CH2_086_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_087_ADDR 0x011c0357L
+#define IBU_P2_CETUS_CH2_087_STRIDE 1
+#define IBU_P2_CETUS_CH2_087_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_088_ADDR 0x011c0358L
+#define IBU_P2_CETUS_CH2_088_STRIDE 1
+#define IBU_P2_CETUS_CH2_088_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_089_ADDR 0x011c0359L
+#define IBU_P2_CETUS_CH2_089_STRIDE 1
+#define IBU_P2_CETUS_CH2_089_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_090_ADDR 0x011c035aL
+#define IBU_P2_CETUS_CH2_090_STRIDE 1
+#define IBU_P2_CETUS_CH2_090_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_091_ADDR 0x011c035bL
+#define IBU_P2_CETUS_CH2_091_STRIDE 1
+#define IBU_P2_CETUS_CH2_091_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_092_ADDR 0x011c035cL
+#define IBU_P2_CETUS_CH2_092_STRIDE 1
+#define IBU_P2_CETUS_CH2_092_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_093_ADDR 0x011c035dL
+#define IBU_P2_CETUS_CH2_093_STRIDE 1
+#define IBU_P2_CETUS_CH2_093_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_094_ADDR 0x011c035eL
+#define IBU_P2_CETUS_CH2_094_STRIDE 1
+#define IBU_P2_CETUS_CH2_094_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_095_ADDR 0x011c035fL
+#define IBU_P2_CETUS_CH2_095_STRIDE 1
+#define IBU_P2_CETUS_CH2_095_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_096_ADDR 0x011c0360L
+#define IBU_P2_CETUS_CH2_096_STRIDE 1
+#define IBU_P2_CETUS_CH2_096_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_097_ADDR 0x011c0361L
+#define IBU_P2_CETUS_CH2_097_STRIDE 1
+#define IBU_P2_CETUS_CH2_097_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_098_ADDR 0x011c0362L
+#define IBU_P2_CETUS_CH2_098_STRIDE 1
+#define IBU_P2_CETUS_CH2_098_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_099_ADDR 0x011c0363L
+#define IBU_P2_CETUS_CH2_099_STRIDE 1
+#define IBU_P2_CETUS_CH2_099_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_100_ADDR 0x011c0364L
+#define IBU_P2_CETUS_CH2_100_STRIDE 1
+#define IBU_P2_CETUS_CH2_100_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_101_ADDR 0x011c0365L
+#define IBU_P2_CETUS_CH2_101_STRIDE 1
+#define IBU_P2_CETUS_CH2_101_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_102_ADDR 0x011c0366L
+#define IBU_P2_CETUS_CH2_102_STRIDE 1
+#define IBU_P2_CETUS_CH2_102_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_103_ADDR 0x011c0367L
+#define IBU_P2_CETUS_CH2_103_STRIDE 1
+#define IBU_P2_CETUS_CH2_103_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_104_ADDR 0x011c0368L
+#define IBU_P2_CETUS_CH2_104_STRIDE 1
+#define IBU_P2_CETUS_CH2_104_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_105_ADDR 0x011c0369L
+#define IBU_P2_CETUS_CH2_105_STRIDE 1
+#define IBU_P2_CETUS_CH2_105_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_106_ADDR 0x011c036aL
+#define IBU_P2_CETUS_CH2_106_STRIDE 1
+#define IBU_P2_CETUS_CH2_106_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_107_ADDR 0x011c036bL
+#define IBU_P2_CETUS_CH2_107_STRIDE 1
+#define IBU_P2_CETUS_CH2_107_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_108_ADDR 0x011c036cL
+#define IBU_P2_CETUS_CH2_108_STRIDE 1
+#define IBU_P2_CETUS_CH2_108_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_109_ADDR 0x011c036dL
+#define IBU_P2_CETUS_CH2_109_STRIDE 1
+#define IBU_P2_CETUS_CH2_109_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_110_ADDR 0x011c036eL
+#define IBU_P2_CETUS_CH2_110_STRIDE 1
+#define IBU_P2_CETUS_CH2_110_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_111_ADDR 0x011c036fL
+#define IBU_P2_CETUS_CH2_111_STRIDE 1
+#define IBU_P2_CETUS_CH2_111_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_112_ADDR 0x011c0370L
+#define IBU_P2_CETUS_CH2_112_STRIDE 1
+#define IBU_P2_CETUS_CH2_112_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_113_ADDR 0x011c0371L
+#define IBU_P2_CETUS_CH2_113_STRIDE 1
+#define IBU_P2_CETUS_CH2_113_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_114_ADDR 0x011c0372L
+#define IBU_P2_CETUS_CH2_114_STRIDE 1
+#define IBU_P2_CETUS_CH2_114_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_115_ADDR 0x011c0373L
+#define IBU_P2_CETUS_CH2_115_STRIDE 1
+#define IBU_P2_CETUS_CH2_115_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_116_ADDR 0x011c0374L
+#define IBU_P2_CETUS_CH2_116_STRIDE 1
+#define IBU_P2_CETUS_CH2_116_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_117_ADDR 0x011c0375L
+#define IBU_P2_CETUS_CH2_117_STRIDE 1
+#define IBU_P2_CETUS_CH2_117_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_118_ADDR 0x011c0376L
+#define IBU_P2_CETUS_CH2_118_STRIDE 1
+#define IBU_P2_CETUS_CH2_118_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_119_ADDR 0x011c0377L
+#define IBU_P2_CETUS_CH2_119_STRIDE 1
+#define IBU_P2_CETUS_CH2_119_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_120_ADDR 0x011c0378L
+#define IBU_P2_CETUS_CH2_120_STRIDE 1
+#define IBU_P2_CETUS_CH2_120_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_121_ADDR 0x011c0379L
+#define IBU_P2_CETUS_CH2_121_STRIDE 1
+#define IBU_P2_CETUS_CH2_121_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_122_ADDR 0x011c037aL
+#define IBU_P2_CETUS_CH2_122_STRIDE 1
+#define IBU_P2_CETUS_CH2_122_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_123_ADDR 0x011c037bL
+#define IBU_P2_CETUS_CH2_123_STRIDE 1
+#define IBU_P2_CETUS_CH2_123_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_124_ADDR 0x011c037cL
+#define IBU_P2_CETUS_CH2_124_STRIDE 1
+#define IBU_P2_CETUS_CH2_124_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_125_ADDR 0x011c037dL
+#define IBU_P2_CETUS_CH2_125_STRIDE 1
+#define IBU_P2_CETUS_CH2_125_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_126_ADDR 0x011c037eL
+#define IBU_P2_CETUS_CH2_126_STRIDE 1
+#define IBU_P2_CETUS_CH2_126_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_127_ADDR 0x011c037fL
+#define IBU_P2_CETUS_CH2_127_STRIDE 1
+#define IBU_P2_CETUS_CH2_127_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_128_ADDR 0x011c0380L
+#define IBU_P2_CETUS_CH2_128_STRIDE 1
+#define IBU_P2_CETUS_CH2_128_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_129_ADDR 0x011c0381L
+#define IBU_P2_CETUS_CH2_129_STRIDE 1
+#define IBU_P2_CETUS_CH2_129_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_130_ADDR 0x011c0382L
+#define IBU_P2_CETUS_CH2_130_STRIDE 1
+#define IBU_P2_CETUS_CH2_130_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_131_ADDR 0x011c0383L
+#define IBU_P2_CETUS_CH2_131_STRIDE 1
+#define IBU_P2_CETUS_CH2_131_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_132_ADDR 0x011c0384L
+#define IBU_P2_CETUS_CH2_132_STRIDE 1
+#define IBU_P2_CETUS_CH2_132_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_133_ADDR 0x011c0385L
+#define IBU_P2_CETUS_CH2_133_STRIDE 1
+#define IBU_P2_CETUS_CH2_133_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_134_ADDR 0x011c0386L
+#define IBU_P2_CETUS_CH2_134_STRIDE 1
+#define IBU_P2_CETUS_CH2_134_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_135_ADDR 0x011c0387L
+#define IBU_P2_CETUS_CH2_135_STRIDE 1
+#define IBU_P2_CETUS_CH2_135_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_136_ADDR 0x011c0388L
+#define IBU_P2_CETUS_CH2_136_STRIDE 1
+#define IBU_P2_CETUS_CH2_136_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_137_ADDR 0x011c0389L
+#define IBU_P2_CETUS_CH2_137_STRIDE 1
+#define IBU_P2_CETUS_CH2_137_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_138_ADDR 0x011c038aL
+#define IBU_P2_CETUS_CH2_138_STRIDE 1
+#define IBU_P2_CETUS_CH2_138_DEPTH 1
+
+#define IBU_P2_CETUS_CH2_139_ADDR 0x011c038bL
+#define IBU_P2_CETUS_CH2_139_STRIDE 1
+#define IBU_P2_CETUS_CH2_139_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH3_000_ADDR 0x011c0400L
+#define IBU_P2_CETUS_CH3_000_STRIDE 1
+#define IBU_P2_CETUS_CH3_000_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH3_001_ADDR 0x011c0401L
+#define IBU_P2_CETUS_CH3_001_STRIDE 1
+#define IBU_P2_CETUS_CH3_001_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_CH3_002_ADDR 0x011c0402L
+#define IBU_P2_CETUS_CH3_002_STRIDE 1
+#define IBU_P2_CETUS_CH3_002_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_003_ADDR 0x011c0403L
+#define IBU_P2_CETUS_CH3_003_STRIDE 1
+#define IBU_P2_CETUS_CH3_003_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_004_ADDR 0x011c0404L
+#define IBU_P2_CETUS_CH3_004_STRIDE 1
+#define IBU_P2_CETUS_CH3_004_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_005_ADDR 0x011c0405L
+#define IBU_P2_CETUS_CH3_005_STRIDE 1
+#define IBU_P2_CETUS_CH3_005_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_006_ADDR 0x011c0406L
+#define IBU_P2_CETUS_CH3_006_STRIDE 1
+#define IBU_P2_CETUS_CH3_006_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_007_ADDR 0x011c0407L
+#define IBU_P2_CETUS_CH3_007_STRIDE 1
+#define IBU_P2_CETUS_CH3_007_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_008_ADDR 0x011c0408L
+#define IBU_P2_CETUS_CH3_008_STRIDE 1
+#define IBU_P2_CETUS_CH3_008_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_009_ADDR 0x011c0409L
+#define IBU_P2_CETUS_CH3_009_STRIDE 1
+#define IBU_P2_CETUS_CH3_009_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_010_ADDR 0x011c040aL
+#define IBU_P2_CETUS_CH3_010_STRIDE 1
+#define IBU_P2_CETUS_CH3_010_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_011_ADDR 0x011c040bL
+#define IBU_P2_CETUS_CH3_011_STRIDE 1
+#define IBU_P2_CETUS_CH3_011_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_012_ADDR 0x011c040cL
+#define IBU_P2_CETUS_CH3_012_STRIDE 1
+#define IBU_P2_CETUS_CH3_012_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_013_ADDR 0x011c040dL
+#define IBU_P2_CETUS_CH3_013_STRIDE 1
+#define IBU_P2_CETUS_CH3_013_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_014_ADDR 0x011c040eL
+#define IBU_P2_CETUS_CH3_014_STRIDE 1
+#define IBU_P2_CETUS_CH3_014_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_015_ADDR 0x011c040fL
+#define IBU_P2_CETUS_CH3_015_STRIDE 1
+#define IBU_P2_CETUS_CH3_015_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_016_ADDR 0x011c0410L
+#define IBU_P2_CETUS_CH3_016_STRIDE 1
+#define IBU_P2_CETUS_CH3_016_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_017_ADDR 0x011c0411L
+#define IBU_P2_CETUS_CH3_017_STRIDE 1
+#define IBU_P2_CETUS_CH3_017_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_018_ADDR 0x011c0412L
+#define IBU_P2_CETUS_CH3_018_STRIDE 1
+#define IBU_P2_CETUS_CH3_018_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_019_ADDR 0x011c0413L
+#define IBU_P2_CETUS_CH3_019_STRIDE 1
+#define IBU_P2_CETUS_CH3_019_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_020_ADDR 0x011c0414L
+#define IBU_P2_CETUS_CH3_020_STRIDE 1
+#define IBU_P2_CETUS_CH3_020_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_021_ADDR 0x011c0415L
+#define IBU_P2_CETUS_CH3_021_STRIDE 1
+#define IBU_P2_CETUS_CH3_021_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_022_ADDR 0x011c0416L
+#define IBU_P2_CETUS_CH3_022_STRIDE 1
+#define IBU_P2_CETUS_CH3_022_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_023_ADDR 0x011c0417L
+#define IBU_P2_CETUS_CH3_023_STRIDE 1
+#define IBU_P2_CETUS_CH3_023_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_024_ADDR 0x011c0418L
+#define IBU_P2_CETUS_CH3_024_STRIDE 1
+#define IBU_P2_CETUS_CH3_024_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_025_ADDR 0x011c0419L
+#define IBU_P2_CETUS_CH3_025_STRIDE 1
+#define IBU_P2_CETUS_CH3_025_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_026_ADDR 0x011c041aL
+#define IBU_P2_CETUS_CH3_026_STRIDE 1
+#define IBU_P2_CETUS_CH3_026_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_027_ADDR 0x011c041bL
+#define IBU_P2_CETUS_CH3_027_STRIDE 1
+#define IBU_P2_CETUS_CH3_027_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_028_ADDR 0x011c041cL
+#define IBU_P2_CETUS_CH3_028_STRIDE 1
+#define IBU_P2_CETUS_CH3_028_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_029_ADDR 0x011c041dL
+#define IBU_P2_CETUS_CH3_029_STRIDE 1
+#define IBU_P2_CETUS_CH3_029_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_030_ADDR 0x011c041eL
+#define IBU_P2_CETUS_CH3_030_STRIDE 1
+#define IBU_P2_CETUS_CH3_030_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_031_ADDR 0x011c041fL
+#define IBU_P2_CETUS_CH3_031_STRIDE 1
+#define IBU_P2_CETUS_CH3_031_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_032_ADDR 0x011c0420L
+#define IBU_P2_CETUS_CH3_032_STRIDE 1
+#define IBU_P2_CETUS_CH3_032_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_033_ADDR 0x011c0421L
+#define IBU_P2_CETUS_CH3_033_STRIDE 1
+#define IBU_P2_CETUS_CH3_033_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_034_ADDR 0x011c0422L
+#define IBU_P2_CETUS_CH3_034_STRIDE 1
+#define IBU_P2_CETUS_CH3_034_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_035_ADDR 0x011c0423L
+#define IBU_P2_CETUS_CH3_035_STRIDE 1
+#define IBU_P2_CETUS_CH3_035_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_036_ADDR 0x011c0424L
+#define IBU_P2_CETUS_CH3_036_STRIDE 1
+#define IBU_P2_CETUS_CH3_036_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_037_ADDR 0x011c0425L
+#define IBU_P2_CETUS_CH3_037_STRIDE 1
+#define IBU_P2_CETUS_CH3_037_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_038_ADDR 0x011c0426L
+#define IBU_P2_CETUS_CH3_038_STRIDE 1
+#define IBU_P2_CETUS_CH3_038_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_039_ADDR 0x011c0427L
+#define IBU_P2_CETUS_CH3_039_STRIDE 1
+#define IBU_P2_CETUS_CH3_039_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_040_ADDR 0x011c0428L
+#define IBU_P2_CETUS_CH3_040_STRIDE 1
+#define IBU_P2_CETUS_CH3_040_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_041_ADDR 0x011c0429L
+#define IBU_P2_CETUS_CH3_041_STRIDE 1
+#define IBU_P2_CETUS_CH3_041_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_042_ADDR 0x011c042aL
+#define IBU_P2_CETUS_CH3_042_STRIDE 1
+#define IBU_P2_CETUS_CH3_042_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_043_ADDR 0x011c042bL
+#define IBU_P2_CETUS_CH3_043_STRIDE 1
+#define IBU_P2_CETUS_CH3_043_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_044_ADDR 0x011c042cL
+#define IBU_P2_CETUS_CH3_044_STRIDE 1
+#define IBU_P2_CETUS_CH3_044_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_045_ADDR 0x011c042dL
+#define IBU_P2_CETUS_CH3_045_STRIDE 1
+#define IBU_P2_CETUS_CH3_045_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_046_ADDR 0x011c042eL
+#define IBU_P2_CETUS_CH3_046_STRIDE 1
+#define IBU_P2_CETUS_CH3_046_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_047_ADDR 0x011c042fL
+#define IBU_P2_CETUS_CH3_047_STRIDE 1
+#define IBU_P2_CETUS_CH3_047_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_048_ADDR 0x011c0430L
+#define IBU_P2_CETUS_CH3_048_STRIDE 1
+#define IBU_P2_CETUS_CH3_048_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_049_ADDR 0x011c0431L
+#define IBU_P2_CETUS_CH3_049_STRIDE 1
+#define IBU_P2_CETUS_CH3_049_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_050_ADDR 0x011c0432L
+#define IBU_P2_CETUS_CH3_050_STRIDE 1
+#define IBU_P2_CETUS_CH3_050_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_051_ADDR 0x011c0433L
+#define IBU_P2_CETUS_CH3_051_STRIDE 1
+#define IBU_P2_CETUS_CH3_051_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_052_ADDR 0x011c0434L
+#define IBU_P2_CETUS_CH3_052_STRIDE 1
+#define IBU_P2_CETUS_CH3_052_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_053_ADDR 0x011c0435L
+#define IBU_P2_CETUS_CH3_053_STRIDE 1
+#define IBU_P2_CETUS_CH3_053_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_054_ADDR 0x011c0436L
+#define IBU_P2_CETUS_CH3_054_STRIDE 1
+#define IBU_P2_CETUS_CH3_054_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_055_ADDR 0x011c0437L
+#define IBU_P2_CETUS_CH3_055_STRIDE 1
+#define IBU_P2_CETUS_CH3_055_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_056_ADDR 0x011c0438L
+#define IBU_P2_CETUS_CH3_056_STRIDE 1
+#define IBU_P2_CETUS_CH3_056_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_057_ADDR 0x011c0439L
+#define IBU_P2_CETUS_CH3_057_STRIDE 1
+#define IBU_P2_CETUS_CH3_057_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_058_ADDR 0x011c043aL
+#define IBU_P2_CETUS_CH3_058_STRIDE 1
+#define IBU_P2_CETUS_CH3_058_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_059_ADDR 0x011c043bL
+#define IBU_P2_CETUS_CH3_059_STRIDE 1
+#define IBU_P2_CETUS_CH3_059_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_060_ADDR 0x011c043cL
+#define IBU_P2_CETUS_CH3_060_STRIDE 1
+#define IBU_P2_CETUS_CH3_060_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_061_ADDR 0x011c043dL
+#define IBU_P2_CETUS_CH3_061_STRIDE 1
+#define IBU_P2_CETUS_CH3_061_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_062_ADDR 0x011c043eL
+#define IBU_P2_CETUS_CH3_062_STRIDE 1
+#define IBU_P2_CETUS_CH3_062_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_063_ADDR 0x011c043fL
+#define IBU_P2_CETUS_CH3_063_STRIDE 1
+#define IBU_P2_CETUS_CH3_063_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_064_ADDR 0x011c0440L
+#define IBU_P2_CETUS_CH3_064_STRIDE 1
+#define IBU_P2_CETUS_CH3_064_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_065_ADDR 0x011c0441L
+#define IBU_P2_CETUS_CH3_065_STRIDE 1
+#define IBU_P2_CETUS_CH3_065_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_066_ADDR 0x011c0442L
+#define IBU_P2_CETUS_CH3_066_STRIDE 1
+#define IBU_P2_CETUS_CH3_066_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_067_ADDR 0x011c0443L
+#define IBU_P2_CETUS_CH3_067_STRIDE 1
+#define IBU_P2_CETUS_CH3_067_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_068_ADDR 0x011c0444L
+#define IBU_P2_CETUS_CH3_068_STRIDE 1
+#define IBU_P2_CETUS_CH3_068_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_069_ADDR 0x011c0445L
+#define IBU_P2_CETUS_CH3_069_STRIDE 1
+#define IBU_P2_CETUS_CH3_069_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_070_ADDR 0x011c0446L
+#define IBU_P2_CETUS_CH3_070_STRIDE 1
+#define IBU_P2_CETUS_CH3_070_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_071_ADDR 0x011c0447L
+#define IBU_P2_CETUS_CH3_071_STRIDE 1
+#define IBU_P2_CETUS_CH3_071_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_072_ADDR 0x011c0448L
+#define IBU_P2_CETUS_CH3_072_STRIDE 1
+#define IBU_P2_CETUS_CH3_072_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_073_ADDR 0x011c0449L
+#define IBU_P2_CETUS_CH3_073_STRIDE 1
+#define IBU_P2_CETUS_CH3_073_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_074_ADDR 0x011c044aL
+#define IBU_P2_CETUS_CH3_074_STRIDE 1
+#define IBU_P2_CETUS_CH3_074_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_075_ADDR 0x011c044bL
+#define IBU_P2_CETUS_CH3_075_STRIDE 1
+#define IBU_P2_CETUS_CH3_075_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_076_ADDR 0x011c044cL
+#define IBU_P2_CETUS_CH3_076_STRIDE 1
+#define IBU_P2_CETUS_CH3_076_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_077_ADDR 0x011c044dL
+#define IBU_P2_CETUS_CH3_077_STRIDE 1
+#define IBU_P2_CETUS_CH3_077_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_078_ADDR 0x011c044eL
+#define IBU_P2_CETUS_CH3_078_STRIDE 1
+#define IBU_P2_CETUS_CH3_078_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_079_ADDR 0x011c044fL
+#define IBU_P2_CETUS_CH3_079_STRIDE 1
+#define IBU_P2_CETUS_CH3_079_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_080_ADDR 0x011c0450L
+#define IBU_P2_CETUS_CH3_080_STRIDE 1
+#define IBU_P2_CETUS_CH3_080_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_081_ADDR 0x011c0451L
+#define IBU_P2_CETUS_CH3_081_STRIDE 1
+#define IBU_P2_CETUS_CH3_081_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_082_ADDR 0x011c0452L
+#define IBU_P2_CETUS_CH3_082_STRIDE 1
+#define IBU_P2_CETUS_CH3_082_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_083_ADDR 0x011c0453L
+#define IBU_P2_CETUS_CH3_083_STRIDE 1
+#define IBU_P2_CETUS_CH3_083_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_084_ADDR 0x011c0454L
+#define IBU_P2_CETUS_CH3_084_STRIDE 1
+#define IBU_P2_CETUS_CH3_084_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_085_ADDR 0x011c0455L
+#define IBU_P2_CETUS_CH3_085_STRIDE 1
+#define IBU_P2_CETUS_CH3_085_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_086_ADDR 0x011c0456L
+#define IBU_P2_CETUS_CH3_086_STRIDE 1
+#define IBU_P2_CETUS_CH3_086_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_087_ADDR 0x011c0457L
+#define IBU_P2_CETUS_CH3_087_STRIDE 1
+#define IBU_P2_CETUS_CH3_087_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_088_ADDR 0x011c0458L
+#define IBU_P2_CETUS_CH3_088_STRIDE 1
+#define IBU_P2_CETUS_CH3_088_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_089_ADDR 0x011c0459L
+#define IBU_P2_CETUS_CH3_089_STRIDE 1
+#define IBU_P2_CETUS_CH3_089_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_090_ADDR 0x011c045aL
+#define IBU_P2_CETUS_CH3_090_STRIDE 1
+#define IBU_P2_CETUS_CH3_090_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_091_ADDR 0x011c045bL
+#define IBU_P2_CETUS_CH3_091_STRIDE 1
+#define IBU_P2_CETUS_CH3_091_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_092_ADDR 0x011c045cL
+#define IBU_P2_CETUS_CH3_092_STRIDE 1
+#define IBU_P2_CETUS_CH3_092_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_093_ADDR 0x011c045dL
+#define IBU_P2_CETUS_CH3_093_STRIDE 1
+#define IBU_P2_CETUS_CH3_093_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_094_ADDR 0x011c045eL
+#define IBU_P2_CETUS_CH3_094_STRIDE 1
+#define IBU_P2_CETUS_CH3_094_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_095_ADDR 0x011c045fL
+#define IBU_P2_CETUS_CH3_095_STRIDE 1
+#define IBU_P2_CETUS_CH3_095_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_096_ADDR 0x011c0460L
+#define IBU_P2_CETUS_CH3_096_STRIDE 1
+#define IBU_P2_CETUS_CH3_096_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_097_ADDR 0x011c0461L
+#define IBU_P2_CETUS_CH3_097_STRIDE 1
+#define IBU_P2_CETUS_CH3_097_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_098_ADDR 0x011c0462L
+#define IBU_P2_CETUS_CH3_098_STRIDE 1
+#define IBU_P2_CETUS_CH3_098_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_099_ADDR 0x011c0463L
+#define IBU_P2_CETUS_CH3_099_STRIDE 1
+#define IBU_P2_CETUS_CH3_099_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_100_ADDR 0x011c0464L
+#define IBU_P2_CETUS_CH3_100_STRIDE 1
+#define IBU_P2_CETUS_CH3_100_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_101_ADDR 0x011c0465L
+#define IBU_P2_CETUS_CH3_101_STRIDE 1
+#define IBU_P2_CETUS_CH3_101_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_102_ADDR 0x011c0466L
+#define IBU_P2_CETUS_CH3_102_STRIDE 1
+#define IBU_P2_CETUS_CH3_102_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_103_ADDR 0x011c0467L
+#define IBU_P2_CETUS_CH3_103_STRIDE 1
+#define IBU_P2_CETUS_CH3_103_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_104_ADDR 0x011c0468L
+#define IBU_P2_CETUS_CH3_104_STRIDE 1
+#define IBU_P2_CETUS_CH3_104_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_105_ADDR 0x011c0469L
+#define IBU_P2_CETUS_CH3_105_STRIDE 1
+#define IBU_P2_CETUS_CH3_105_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_106_ADDR 0x011c046aL
+#define IBU_P2_CETUS_CH3_106_STRIDE 1
+#define IBU_P2_CETUS_CH3_106_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_107_ADDR 0x011c046bL
+#define IBU_P2_CETUS_CH3_107_STRIDE 1
+#define IBU_P2_CETUS_CH3_107_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_108_ADDR 0x011c046cL
+#define IBU_P2_CETUS_CH3_108_STRIDE 1
+#define IBU_P2_CETUS_CH3_108_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_109_ADDR 0x011c046dL
+#define IBU_P2_CETUS_CH3_109_STRIDE 1
+#define IBU_P2_CETUS_CH3_109_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_110_ADDR 0x011c046eL
+#define IBU_P2_CETUS_CH3_110_STRIDE 1
+#define IBU_P2_CETUS_CH3_110_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_111_ADDR 0x011c046fL
+#define IBU_P2_CETUS_CH3_111_STRIDE 1
+#define IBU_P2_CETUS_CH3_111_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_112_ADDR 0x011c0470L
+#define IBU_P2_CETUS_CH3_112_STRIDE 1
+#define IBU_P2_CETUS_CH3_112_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_113_ADDR 0x011c0471L
+#define IBU_P2_CETUS_CH3_113_STRIDE 1
+#define IBU_P2_CETUS_CH3_113_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_114_ADDR 0x011c0472L
+#define IBU_P2_CETUS_CH3_114_STRIDE 1
+#define IBU_P2_CETUS_CH3_114_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_115_ADDR 0x011c0473L
+#define IBU_P2_CETUS_CH3_115_STRIDE 1
+#define IBU_P2_CETUS_CH3_115_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_116_ADDR 0x011c0474L
+#define IBU_P2_CETUS_CH3_116_STRIDE 1
+#define IBU_P2_CETUS_CH3_116_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_117_ADDR 0x011c0475L
+#define IBU_P2_CETUS_CH3_117_STRIDE 1
+#define IBU_P2_CETUS_CH3_117_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_118_ADDR 0x011c0476L
+#define IBU_P2_CETUS_CH3_118_STRIDE 1
+#define IBU_P2_CETUS_CH3_118_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_119_ADDR 0x011c0477L
+#define IBU_P2_CETUS_CH3_119_STRIDE 1
+#define IBU_P2_CETUS_CH3_119_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_120_ADDR 0x011c0478L
+#define IBU_P2_CETUS_CH3_120_STRIDE 1
+#define IBU_P2_CETUS_CH3_120_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_121_ADDR 0x011c0479L
+#define IBU_P2_CETUS_CH3_121_STRIDE 1
+#define IBU_P2_CETUS_CH3_121_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_122_ADDR 0x011c047aL
+#define IBU_P2_CETUS_CH3_122_STRIDE 1
+#define IBU_P2_CETUS_CH3_122_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_123_ADDR 0x011c047bL
+#define IBU_P2_CETUS_CH3_123_STRIDE 1
+#define IBU_P2_CETUS_CH3_123_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_124_ADDR 0x011c047cL
+#define IBU_P2_CETUS_CH3_124_STRIDE 1
+#define IBU_P2_CETUS_CH3_124_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_125_ADDR 0x011c047dL
+#define IBU_P2_CETUS_CH3_125_STRIDE 1
+#define IBU_P2_CETUS_CH3_125_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_126_ADDR 0x011c047eL
+#define IBU_P2_CETUS_CH3_126_STRIDE 1
+#define IBU_P2_CETUS_CH3_126_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_127_ADDR 0x011c047fL
+#define IBU_P2_CETUS_CH3_127_STRIDE 1
+#define IBU_P2_CETUS_CH3_127_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_128_ADDR 0x011c0480L
+#define IBU_P2_CETUS_CH3_128_STRIDE 1
+#define IBU_P2_CETUS_CH3_128_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_129_ADDR 0x011c0481L
+#define IBU_P2_CETUS_CH3_129_STRIDE 1
+#define IBU_P2_CETUS_CH3_129_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_130_ADDR 0x011c0482L
+#define IBU_P2_CETUS_CH3_130_STRIDE 1
+#define IBU_P2_CETUS_CH3_130_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_131_ADDR 0x011c0483L
+#define IBU_P2_CETUS_CH3_131_STRIDE 1
+#define IBU_P2_CETUS_CH3_131_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_132_ADDR 0x011c0484L
+#define IBU_P2_CETUS_CH3_132_STRIDE 1
+#define IBU_P2_CETUS_CH3_132_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_133_ADDR 0x011c0485L
+#define IBU_P2_CETUS_CH3_133_STRIDE 1
+#define IBU_P2_CETUS_CH3_133_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_134_ADDR 0x011c0486L
+#define IBU_P2_CETUS_CH3_134_STRIDE 1
+#define IBU_P2_CETUS_CH3_134_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_135_ADDR 0x011c0487L
+#define IBU_P2_CETUS_CH3_135_STRIDE 1
+#define IBU_P2_CETUS_CH3_135_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_136_ADDR 0x011c0488L
+#define IBU_P2_CETUS_CH3_136_STRIDE 1
+#define IBU_P2_CETUS_CH3_136_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_137_ADDR 0x011c0489L
+#define IBU_P2_CETUS_CH3_137_STRIDE 1
+#define IBU_P2_CETUS_CH3_137_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_138_ADDR 0x011c048aL
+#define IBU_P2_CETUS_CH3_138_STRIDE 1
+#define IBU_P2_CETUS_CH3_138_DEPTH 1
+
+#define IBU_P2_CETUS_CH3_139_ADDR 0x011c048bL
+#define IBU_P2_CETUS_CH3_139_STRIDE 1
+#define IBU_P2_CETUS_CH3_139_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_CONTROL0_ADDR 0x011c0600L
+#define IBU_P2_CETUS_PLLB_CONTROL0_STRIDE 1
+#define IBU_P2_CETUS_PLLB_CONTROL0_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_CONTROL1_ADDR 0x011c0601L
+#define IBU_P2_CETUS_PLLB_CONTROL1_STRIDE 1
+#define IBU_P2_CETUS_PLLB_CONTROL1_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_CONTROL2_ADDR 0x011c0602L
+#define IBU_P2_CETUS_PLLB_CONTROL2_STRIDE 1
+#define IBU_P2_CETUS_PLLB_CONTROL2_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_EXTFB_CNTR_ADDR 0x011c0603L
+#define IBU_P2_CETUS_PLLB_EXTFB_CNTR_STRIDE 1
+#define IBU_P2_CETUS_PLLB_EXTFB_CNTR_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_FBCNT_ATO_ADDR 0x011c0604L
+#define IBU_P2_CETUS_PLLB_FBCNT_ATO_STRIDE 1
+#define IBU_P2_CETUS_PLLB_FBCNT_ATO_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_SPARE_USRCNTR_ADDR 0x011c0605L
+#define IBU_P2_CETUS_PLLB_SPARE_USRCNTR_STRIDE 1
+#define IBU_P2_CETUS_PLLB_SPARE_USRCNTR_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_DIV_EN_ADDR 0x011c0606L
+#define IBU_P2_CETUS_PLLB_DIV_EN_STRIDE 1
+#define IBU_P2_CETUS_PLLB_DIV_EN_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_VCO_WAIT_CNT_ADDR 0x011c0607L
+#define IBU_P2_CETUS_PLLB_VCO_WAIT_CNT_STRIDE 1
+#define IBU_P2_CETUS_PLLB_VCO_WAIT_CNT_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_STATUS0_ADDR 0x011c0608L
+#define IBU_P2_CETUS_PLLB_STATUS0_STRIDE 1
+#define IBU_P2_CETUS_PLLB_STATUS0_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_STATUS1_ADDR 0x011c0609L
+#define IBU_P2_CETUS_PLLB_STATUS1_STRIDE 1
+#define IBU_P2_CETUS_PLLB_STATUS1_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_010_ADDR 0x011c060aL
+#define IBU_P2_CETUS_PLLB_010_STRIDE 1
+#define IBU_P2_CETUS_PLLB_010_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_011_ADDR 0x011c060bL
+#define IBU_P2_CETUS_PLLB_011_STRIDE 1
+#define IBU_P2_CETUS_PLLB_011_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_012_ADDR 0x011c060cL
+#define IBU_P2_CETUS_PLLB_012_STRIDE 1
+#define IBU_P2_CETUS_PLLB_012_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_013_ADDR 0x011c060dL
+#define IBU_P2_CETUS_PLLB_013_STRIDE 1
+#define IBU_P2_CETUS_PLLB_013_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_014_ADDR 0x011c060eL
+#define IBU_P2_CETUS_PLLB_014_STRIDE 1
+#define IBU_P2_CETUS_PLLB_014_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_015_ADDR 0x011c060fL
+#define IBU_P2_CETUS_PLLB_015_STRIDE 1
+#define IBU_P2_CETUS_PLLB_015_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_016_ADDR 0x011c0610L
+#define IBU_P2_CETUS_PLLB_016_STRIDE 1
+#define IBU_P2_CETUS_PLLB_016_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_017_ADDR 0x011c0611L
+#define IBU_P2_CETUS_PLLB_017_STRIDE 1
+#define IBU_P2_CETUS_PLLB_017_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_018_ADDR 0x011c0612L
+#define IBU_P2_CETUS_PLLB_018_STRIDE 1
+#define IBU_P2_CETUS_PLLB_018_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_019_ADDR 0x011c0613L
+#define IBU_P2_CETUS_PLLB_019_STRIDE 1
+#define IBU_P2_CETUS_PLLB_019_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_020_ADDR 0x011c0614L
+#define IBU_P2_CETUS_PLLB_020_STRIDE 1
+#define IBU_P2_CETUS_PLLB_020_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_021_ADDR 0x011c0615L
+#define IBU_P2_CETUS_PLLB_021_STRIDE 1
+#define IBU_P2_CETUS_PLLB_021_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_022_ADDR 0x011c0616L
+#define IBU_P2_CETUS_PLLB_022_STRIDE 1
+#define IBU_P2_CETUS_PLLB_022_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_023_ADDR 0x011c0617L
+#define IBU_P2_CETUS_PLLB_023_STRIDE 1
+#define IBU_P2_CETUS_PLLB_023_DEPTH 1
+
+#define IBU_P2_CETUS_PLLB_024_ADDR 0x011c0618L
+#define IBU_P2_CETUS_PLLB_024_STRIDE 1
+#define IBU_P2_CETUS_PLLB_024_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_ALL_000_ADDR 0x011c0f00L
+#define IBU_P2_CETUS_ALL_000_STRIDE 1
+#define IBU_P2_CETUS_ALL_000_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_ALL_001_ADDR 0x011c0f01L
+#define IBU_P2_CETUS_ALL_001_STRIDE 1
+#define IBU_P2_CETUS_ALL_001_DEPTH 1
+
+ /* CETUS register */
+#define IBU_P2_CETUS_ALL_002_ADDR 0x011c0f02L
+#define IBU_P2_CETUS_ALL_002_STRIDE 1
+#define IBU_P2_CETUS_ALL_002_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_003_ADDR 0x011c0f03L
+#define IBU_P2_CETUS_ALL_003_STRIDE 1
+#define IBU_P2_CETUS_ALL_003_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_004_ADDR 0x011c0f04L
+#define IBU_P2_CETUS_ALL_004_STRIDE 1
+#define IBU_P2_CETUS_ALL_004_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_005_ADDR 0x011c0f05L
+#define IBU_P2_CETUS_ALL_005_STRIDE 1
+#define IBU_P2_CETUS_ALL_005_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_006_ADDR 0x011c0f06L
+#define IBU_P2_CETUS_ALL_006_STRIDE 1
+#define IBU_P2_CETUS_ALL_006_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_007_ADDR 0x011c0f07L
+#define IBU_P2_CETUS_ALL_007_STRIDE 1
+#define IBU_P2_CETUS_ALL_007_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_008_ADDR 0x011c0f08L
+#define IBU_P2_CETUS_ALL_008_STRIDE 1
+#define IBU_P2_CETUS_ALL_008_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_009_ADDR 0x011c0f09L
+#define IBU_P2_CETUS_ALL_009_STRIDE 1
+#define IBU_P2_CETUS_ALL_009_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_010_ADDR 0x011c0f0aL
+#define IBU_P2_CETUS_ALL_010_STRIDE 1
+#define IBU_P2_CETUS_ALL_010_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_011_ADDR 0x011c0f0bL
+#define IBU_P2_CETUS_ALL_011_STRIDE 1
+#define IBU_P2_CETUS_ALL_011_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_012_ADDR 0x011c0f0cL
+#define IBU_P2_CETUS_ALL_012_STRIDE 1
+#define IBU_P2_CETUS_ALL_012_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_013_ADDR 0x011c0f0dL
+#define IBU_P2_CETUS_ALL_013_STRIDE 1
+#define IBU_P2_CETUS_ALL_013_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_014_ADDR 0x011c0f0eL
+#define IBU_P2_CETUS_ALL_014_STRIDE 1
+#define IBU_P2_CETUS_ALL_014_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_015_ADDR 0x011c0f0fL
+#define IBU_P2_CETUS_ALL_015_STRIDE 1
+#define IBU_P2_CETUS_ALL_015_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_016_ADDR 0x011c0f10L
+#define IBU_P2_CETUS_ALL_016_STRIDE 1
+#define IBU_P2_CETUS_ALL_016_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_017_ADDR 0x011c0f11L
+#define IBU_P2_CETUS_ALL_017_STRIDE 1
+#define IBU_P2_CETUS_ALL_017_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_018_ADDR 0x011c0f12L
+#define IBU_P2_CETUS_ALL_018_STRIDE 1
+#define IBU_P2_CETUS_ALL_018_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_019_ADDR 0x011c0f13L
+#define IBU_P2_CETUS_ALL_019_STRIDE 1
+#define IBU_P2_CETUS_ALL_019_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_020_ADDR 0x011c0f14L
+#define IBU_P2_CETUS_ALL_020_STRIDE 1
+#define IBU_P2_CETUS_ALL_020_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_021_ADDR 0x011c0f15L
+#define IBU_P2_CETUS_ALL_021_STRIDE 1
+#define IBU_P2_CETUS_ALL_021_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_022_ADDR 0x011c0f16L
+#define IBU_P2_CETUS_ALL_022_STRIDE 1
+#define IBU_P2_CETUS_ALL_022_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_023_ADDR 0x011c0f17L
+#define IBU_P2_CETUS_ALL_023_STRIDE 1
+#define IBU_P2_CETUS_ALL_023_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_024_ADDR 0x011c0f18L
+#define IBU_P2_CETUS_ALL_024_STRIDE 1
+#define IBU_P2_CETUS_ALL_024_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_025_ADDR 0x011c0f19L
+#define IBU_P2_CETUS_ALL_025_STRIDE 1
+#define IBU_P2_CETUS_ALL_025_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_026_ADDR 0x011c0f1aL
+#define IBU_P2_CETUS_ALL_026_STRIDE 1
+#define IBU_P2_CETUS_ALL_026_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_027_ADDR 0x011c0f1bL
+#define IBU_P2_CETUS_ALL_027_STRIDE 1
+#define IBU_P2_CETUS_ALL_027_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_028_ADDR 0x011c0f1cL
+#define IBU_P2_CETUS_ALL_028_STRIDE 1
+#define IBU_P2_CETUS_ALL_028_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_029_ADDR 0x011c0f1dL
+#define IBU_P2_CETUS_ALL_029_STRIDE 1
+#define IBU_P2_CETUS_ALL_029_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_030_ADDR 0x011c0f1eL
+#define IBU_P2_CETUS_ALL_030_STRIDE 1
+#define IBU_P2_CETUS_ALL_030_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_031_ADDR 0x011c0f1fL
+#define IBU_P2_CETUS_ALL_031_STRIDE 1
+#define IBU_P2_CETUS_ALL_031_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_032_ADDR 0x011c0f20L
+#define IBU_P2_CETUS_ALL_032_STRIDE 1
+#define IBU_P2_CETUS_ALL_032_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_033_ADDR 0x011c0f21L
+#define IBU_P2_CETUS_ALL_033_STRIDE 1
+#define IBU_P2_CETUS_ALL_033_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_034_ADDR 0x011c0f22L
+#define IBU_P2_CETUS_ALL_034_STRIDE 1
+#define IBU_P2_CETUS_ALL_034_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_035_ADDR 0x011c0f23L
+#define IBU_P2_CETUS_ALL_035_STRIDE 1
+#define IBU_P2_CETUS_ALL_035_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_036_ADDR 0x011c0f24L
+#define IBU_P2_CETUS_ALL_036_STRIDE 1
+#define IBU_P2_CETUS_ALL_036_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_037_ADDR 0x011c0f25L
+#define IBU_P2_CETUS_ALL_037_STRIDE 1
+#define IBU_P2_CETUS_ALL_037_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_038_ADDR 0x011c0f26L
+#define IBU_P2_CETUS_ALL_038_STRIDE 1
+#define IBU_P2_CETUS_ALL_038_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_039_ADDR 0x011c0f27L
+#define IBU_P2_CETUS_ALL_039_STRIDE 1
+#define IBU_P2_CETUS_ALL_039_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_040_ADDR 0x011c0f28L
+#define IBU_P2_CETUS_ALL_040_STRIDE 1
+#define IBU_P2_CETUS_ALL_040_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_041_ADDR 0x011c0f29L
+#define IBU_P2_CETUS_ALL_041_STRIDE 1
+#define IBU_P2_CETUS_ALL_041_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_042_ADDR 0x011c0f2aL
+#define IBU_P2_CETUS_ALL_042_STRIDE 1
+#define IBU_P2_CETUS_ALL_042_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_043_ADDR 0x011c0f2bL
+#define IBU_P2_CETUS_ALL_043_STRIDE 1
+#define IBU_P2_CETUS_ALL_043_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_044_ADDR 0x011c0f2cL
+#define IBU_P2_CETUS_ALL_044_STRIDE 1
+#define IBU_P2_CETUS_ALL_044_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_045_ADDR 0x011c0f2dL
+#define IBU_P2_CETUS_ALL_045_STRIDE 1
+#define IBU_P2_CETUS_ALL_045_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_046_ADDR 0x011c0f2eL
+#define IBU_P2_CETUS_ALL_046_STRIDE 1
+#define IBU_P2_CETUS_ALL_046_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_047_ADDR 0x011c0f2fL
+#define IBU_P2_CETUS_ALL_047_STRIDE 1
+#define IBU_P2_CETUS_ALL_047_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_048_ADDR 0x011c0f30L
+#define IBU_P2_CETUS_ALL_048_STRIDE 1
+#define IBU_P2_CETUS_ALL_048_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_049_ADDR 0x011c0f31L
+#define IBU_P2_CETUS_ALL_049_STRIDE 1
+#define IBU_P2_CETUS_ALL_049_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_050_ADDR 0x011c0f32L
+#define IBU_P2_CETUS_ALL_050_STRIDE 1
+#define IBU_P2_CETUS_ALL_050_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_051_ADDR 0x011c0f33L
+#define IBU_P2_CETUS_ALL_051_STRIDE 1
+#define IBU_P2_CETUS_ALL_051_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_052_ADDR 0x011c0f34L
+#define IBU_P2_CETUS_ALL_052_STRIDE 1
+#define IBU_P2_CETUS_ALL_052_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_053_ADDR 0x011c0f35L
+#define IBU_P2_CETUS_ALL_053_STRIDE 1
+#define IBU_P2_CETUS_ALL_053_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_054_ADDR 0x011c0f36L
+#define IBU_P2_CETUS_ALL_054_STRIDE 1
+#define IBU_P2_CETUS_ALL_054_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_055_ADDR 0x011c0f37L
+#define IBU_P2_CETUS_ALL_055_STRIDE 1
+#define IBU_P2_CETUS_ALL_055_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_056_ADDR 0x011c0f38L
+#define IBU_P2_CETUS_ALL_056_STRIDE 1
+#define IBU_P2_CETUS_ALL_056_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_057_ADDR 0x011c0f39L
+#define IBU_P2_CETUS_ALL_057_STRIDE 1
+#define IBU_P2_CETUS_ALL_057_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_058_ADDR 0x011c0f3aL
+#define IBU_P2_CETUS_ALL_058_STRIDE 1
+#define IBU_P2_CETUS_ALL_058_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_059_ADDR 0x011c0f3bL
+#define IBU_P2_CETUS_ALL_059_STRIDE 1
+#define IBU_P2_CETUS_ALL_059_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_060_ADDR 0x011c0f3cL
+#define IBU_P2_CETUS_ALL_060_STRIDE 1
+#define IBU_P2_CETUS_ALL_060_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_061_ADDR 0x011c0f3dL
+#define IBU_P2_CETUS_ALL_061_STRIDE 1
+#define IBU_P2_CETUS_ALL_061_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_062_ADDR 0x011c0f3eL
+#define IBU_P2_CETUS_ALL_062_STRIDE 1
+#define IBU_P2_CETUS_ALL_062_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_063_ADDR 0x011c0f3fL
+#define IBU_P2_CETUS_ALL_063_STRIDE 1
+#define IBU_P2_CETUS_ALL_063_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_064_ADDR 0x011c0f40L
+#define IBU_P2_CETUS_ALL_064_STRIDE 1
+#define IBU_P2_CETUS_ALL_064_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_065_ADDR 0x011c0f41L
+#define IBU_P2_CETUS_ALL_065_STRIDE 1
+#define IBU_P2_CETUS_ALL_065_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_066_ADDR 0x011c0f42L
+#define IBU_P2_CETUS_ALL_066_STRIDE 1
+#define IBU_P2_CETUS_ALL_066_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_067_ADDR 0x011c0f43L
+#define IBU_P2_CETUS_ALL_067_STRIDE 1
+#define IBU_P2_CETUS_ALL_067_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_068_ADDR 0x011c0f44L
+#define IBU_P2_CETUS_ALL_068_STRIDE 1
+#define IBU_P2_CETUS_ALL_068_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_069_ADDR 0x011c0f45L
+#define IBU_P2_CETUS_ALL_069_STRIDE 1
+#define IBU_P2_CETUS_ALL_069_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_070_ADDR 0x011c0f46L
+#define IBU_P2_CETUS_ALL_070_STRIDE 1
+#define IBU_P2_CETUS_ALL_070_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_071_ADDR 0x011c0f47L
+#define IBU_P2_CETUS_ALL_071_STRIDE 1
+#define IBU_P2_CETUS_ALL_071_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_072_ADDR 0x011c0f48L
+#define IBU_P2_CETUS_ALL_072_STRIDE 1
+#define IBU_P2_CETUS_ALL_072_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_073_ADDR 0x011c0f49L
+#define IBU_P2_CETUS_ALL_073_STRIDE 1
+#define IBU_P2_CETUS_ALL_073_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_074_ADDR 0x011c0f4aL
+#define IBU_P2_CETUS_ALL_074_STRIDE 1
+#define IBU_P2_CETUS_ALL_074_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_075_ADDR 0x011c0f4bL
+#define IBU_P2_CETUS_ALL_075_STRIDE 1
+#define IBU_P2_CETUS_ALL_075_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_076_ADDR 0x011c0f4cL
+#define IBU_P2_CETUS_ALL_076_STRIDE 1
+#define IBU_P2_CETUS_ALL_076_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_077_ADDR 0x011c0f4dL
+#define IBU_P2_CETUS_ALL_077_STRIDE 1
+#define IBU_P2_CETUS_ALL_077_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_078_ADDR 0x011c0f4eL
+#define IBU_P2_CETUS_ALL_078_STRIDE 1
+#define IBU_P2_CETUS_ALL_078_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_079_ADDR 0x011c0f4fL
+#define IBU_P2_CETUS_ALL_079_STRIDE 1
+#define IBU_P2_CETUS_ALL_079_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_080_ADDR 0x011c0f50L
+#define IBU_P2_CETUS_ALL_080_STRIDE 1
+#define IBU_P2_CETUS_ALL_080_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_081_ADDR 0x011c0f51L
+#define IBU_P2_CETUS_ALL_081_STRIDE 1
+#define IBU_P2_CETUS_ALL_081_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_082_ADDR 0x011c0f52L
+#define IBU_P2_CETUS_ALL_082_STRIDE 1
+#define IBU_P2_CETUS_ALL_082_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_083_ADDR 0x011c0f53L
+#define IBU_P2_CETUS_ALL_083_STRIDE 1
+#define IBU_P2_CETUS_ALL_083_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_084_ADDR 0x011c0f54L
+#define IBU_P2_CETUS_ALL_084_STRIDE 1
+#define IBU_P2_CETUS_ALL_084_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_085_ADDR 0x011c0f55L
+#define IBU_P2_CETUS_ALL_085_STRIDE 1
+#define IBU_P2_CETUS_ALL_085_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_086_ADDR 0x011c0f56L
+#define IBU_P2_CETUS_ALL_086_STRIDE 1
+#define IBU_P2_CETUS_ALL_086_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_087_ADDR 0x011c0f57L
+#define IBU_P2_CETUS_ALL_087_STRIDE 1
+#define IBU_P2_CETUS_ALL_087_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_088_ADDR 0x011c0f58L
+#define IBU_P2_CETUS_ALL_088_STRIDE 1
+#define IBU_P2_CETUS_ALL_088_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_089_ADDR 0x011c0f59L
+#define IBU_P2_CETUS_ALL_089_STRIDE 1
+#define IBU_P2_CETUS_ALL_089_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_090_ADDR 0x011c0f5aL
+#define IBU_P2_CETUS_ALL_090_STRIDE 1
+#define IBU_P2_CETUS_ALL_090_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_091_ADDR 0x011c0f5bL
+#define IBU_P2_CETUS_ALL_091_STRIDE 1
+#define IBU_P2_CETUS_ALL_091_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_092_ADDR 0x011c0f5cL
+#define IBU_P2_CETUS_ALL_092_STRIDE 1
+#define IBU_P2_CETUS_ALL_092_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_093_ADDR 0x011c0f5dL
+#define IBU_P2_CETUS_ALL_093_STRIDE 1
+#define IBU_P2_CETUS_ALL_093_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_094_ADDR 0x011c0f5eL
+#define IBU_P2_CETUS_ALL_094_STRIDE 1
+#define IBU_P2_CETUS_ALL_094_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_095_ADDR 0x011c0f5fL
+#define IBU_P2_CETUS_ALL_095_STRIDE 1
+#define IBU_P2_CETUS_ALL_095_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_096_ADDR 0x011c0f60L
+#define IBU_P2_CETUS_ALL_096_STRIDE 1
+#define IBU_P2_CETUS_ALL_096_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_097_ADDR 0x011c0f61L
+#define IBU_P2_CETUS_ALL_097_STRIDE 1
+#define IBU_P2_CETUS_ALL_097_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_098_ADDR 0x011c0f62L
+#define IBU_P2_CETUS_ALL_098_STRIDE 1
+#define IBU_P2_CETUS_ALL_098_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_099_ADDR 0x011c0f63L
+#define IBU_P2_CETUS_ALL_099_STRIDE 1
+#define IBU_P2_CETUS_ALL_099_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_100_ADDR 0x011c0f64L
+#define IBU_P2_CETUS_ALL_100_STRIDE 1
+#define IBU_P2_CETUS_ALL_100_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_101_ADDR 0x011c0f65L
+#define IBU_P2_CETUS_ALL_101_STRIDE 1
+#define IBU_P2_CETUS_ALL_101_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_102_ADDR 0x011c0f66L
+#define IBU_P2_CETUS_ALL_102_STRIDE 1
+#define IBU_P2_CETUS_ALL_102_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_103_ADDR 0x011c0f67L
+#define IBU_P2_CETUS_ALL_103_STRIDE 1
+#define IBU_P2_CETUS_ALL_103_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_104_ADDR 0x011c0f68L
+#define IBU_P2_CETUS_ALL_104_STRIDE 1
+#define IBU_P2_CETUS_ALL_104_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_105_ADDR 0x011c0f69L
+#define IBU_P2_CETUS_ALL_105_STRIDE 1
+#define IBU_P2_CETUS_ALL_105_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_106_ADDR 0x011c0f6aL
+#define IBU_P2_CETUS_ALL_106_STRIDE 1
+#define IBU_P2_CETUS_ALL_106_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_107_ADDR 0x011c0f6bL
+#define IBU_P2_CETUS_ALL_107_STRIDE 1
+#define IBU_P2_CETUS_ALL_107_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_108_ADDR 0x011c0f6cL
+#define IBU_P2_CETUS_ALL_108_STRIDE 1
+#define IBU_P2_CETUS_ALL_108_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_109_ADDR 0x011c0f6dL
+#define IBU_P2_CETUS_ALL_109_STRIDE 1
+#define IBU_P2_CETUS_ALL_109_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_110_ADDR 0x011c0f6eL
+#define IBU_P2_CETUS_ALL_110_STRIDE 1
+#define IBU_P2_CETUS_ALL_110_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_111_ADDR 0x011c0f6fL
+#define IBU_P2_CETUS_ALL_111_STRIDE 1
+#define IBU_P2_CETUS_ALL_111_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_112_ADDR 0x011c0f70L
+#define IBU_P2_CETUS_ALL_112_STRIDE 1
+#define IBU_P2_CETUS_ALL_112_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_113_ADDR 0x011c0f71L
+#define IBU_P2_CETUS_ALL_113_STRIDE 1
+#define IBU_P2_CETUS_ALL_113_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_114_ADDR 0x011c0f72L
+#define IBU_P2_CETUS_ALL_114_STRIDE 1
+#define IBU_P2_CETUS_ALL_114_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_115_ADDR 0x011c0f73L
+#define IBU_P2_CETUS_ALL_115_STRIDE 1
+#define IBU_P2_CETUS_ALL_115_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_116_ADDR 0x011c0f74L
+#define IBU_P2_CETUS_ALL_116_STRIDE 1
+#define IBU_P2_CETUS_ALL_116_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_117_ADDR 0x011c0f75L
+#define IBU_P2_CETUS_ALL_117_STRIDE 1
+#define IBU_P2_CETUS_ALL_117_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_118_ADDR 0x011c0f76L
+#define IBU_P2_CETUS_ALL_118_STRIDE 1
+#define IBU_P2_CETUS_ALL_118_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_119_ADDR 0x011c0f77L
+#define IBU_P2_CETUS_ALL_119_STRIDE 1
+#define IBU_P2_CETUS_ALL_119_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_120_ADDR 0x011c0f78L
+#define IBU_P2_CETUS_ALL_120_STRIDE 1
+#define IBU_P2_CETUS_ALL_120_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_121_ADDR 0x011c0f79L
+#define IBU_P2_CETUS_ALL_121_STRIDE 1
+#define IBU_P2_CETUS_ALL_121_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_122_ADDR 0x011c0f7aL
+#define IBU_P2_CETUS_ALL_122_STRIDE 1
+#define IBU_P2_CETUS_ALL_122_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_123_ADDR 0x011c0f7bL
+#define IBU_P2_CETUS_ALL_123_STRIDE 1
+#define IBU_P2_CETUS_ALL_123_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_124_ADDR 0x011c0f7cL
+#define IBU_P2_CETUS_ALL_124_STRIDE 1
+#define IBU_P2_CETUS_ALL_124_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_125_ADDR 0x011c0f7dL
+#define IBU_P2_CETUS_ALL_125_STRIDE 1
+#define IBU_P2_CETUS_ALL_125_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_126_ADDR 0x011c0f7eL
+#define IBU_P2_CETUS_ALL_126_STRIDE 1
+#define IBU_P2_CETUS_ALL_126_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_127_ADDR 0x011c0f7fL
+#define IBU_P2_CETUS_ALL_127_STRIDE 1
+#define IBU_P2_CETUS_ALL_127_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_128_ADDR 0x011c0f80L
+#define IBU_P2_CETUS_ALL_128_STRIDE 1
+#define IBU_P2_CETUS_ALL_128_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_129_ADDR 0x011c0f81L
+#define IBU_P2_CETUS_ALL_129_STRIDE 1
+#define IBU_P2_CETUS_ALL_129_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_130_ADDR 0x011c0f82L
+#define IBU_P2_CETUS_ALL_130_STRIDE 1
+#define IBU_P2_CETUS_ALL_130_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_131_ADDR 0x011c0f83L
+#define IBU_P2_CETUS_ALL_131_STRIDE 1
+#define IBU_P2_CETUS_ALL_131_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_132_ADDR 0x011c0f84L
+#define IBU_P2_CETUS_ALL_132_STRIDE 1
+#define IBU_P2_CETUS_ALL_132_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_133_ADDR 0x011c0f85L
+#define IBU_P2_CETUS_ALL_133_STRIDE 1
+#define IBU_P2_CETUS_ALL_133_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_134_ADDR 0x011c0f86L
+#define IBU_P2_CETUS_ALL_134_STRIDE 1
+#define IBU_P2_CETUS_ALL_134_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_135_ADDR 0x011c0f87L
+#define IBU_P2_CETUS_ALL_135_STRIDE 1
+#define IBU_P2_CETUS_ALL_135_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_136_ADDR 0x011c0f88L
+#define IBU_P2_CETUS_ALL_136_STRIDE 1
+#define IBU_P2_CETUS_ALL_136_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_137_ADDR 0x011c0f89L
+#define IBU_P2_CETUS_ALL_137_STRIDE 1
+#define IBU_P2_CETUS_ALL_137_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_138_ADDR 0x011c0f8aL
+#define IBU_P2_CETUS_ALL_138_STRIDE 1
+#define IBU_P2_CETUS_ALL_138_DEPTH 1
+
+#define IBU_P2_CETUS_ALL_139_ADDR 0x011c0f8bL
+#define IBU_P2_CETUS_ALL_139_STRIDE 1
+#define IBU_P2_CETUS_ALL_139_DEPTH 1
+
+#define IBU_P2_PMA_RESET_CSR_ADDR 0x011e0000L
+#define IBU_P2_PMA_RESET_CSR_STRIDE 1
+#define IBU_P2_PMA_RESET_CSR_DEPTH 1
+
+#define IBU_P2_PMA_PLLA_CSR_ADDR 0x011e0001L
+#define IBU_P2_PMA_PLLA_CSR_STRIDE 1
+#define IBU_P2_PMA_PLLA_CSR_DEPTH 1
+
+#define IBU_P2_PMA_PLLB_CSR_ADDR 0x011e0002L
+#define IBU_P2_PMA_PLLB_CSR_STRIDE 1
+#define IBU_P2_PMA_PLLB_CSR_DEPTH 1
+
+#define IBU_P2_PMA_CMODE_CSR_ADDR 0x011e0003L
+#define IBU_P2_PMA_CMODE_CSR_STRIDE 1
+#define IBU_P2_PMA_CMODE_CSR_DEPTH 1
+
+#define IBU_P2_PMA_LB_CSR_ADDR 0x011e0004L
+#define IBU_P2_PMA_LB_CSR_STRIDE 1
+#define IBU_P2_PMA_LB_CSR_DEPTH 1
+
+#define IBU_P2_PMA_PWR_CSR_ADDR 0x011e0005L
+#define IBU_P2_PMA_PWR_CSR_STRIDE 1
+#define IBU_P2_PMA_PWR_CSR_DEPTH 1
+
+#define IBU_P2_PMA_STATUS0_CSR_ADDR 0x011e0006L
+#define IBU_P2_PMA_STATUS0_CSR_STRIDE 1
+#define IBU_P2_PMA_STATUS0_CSR_DEPTH 1
+
+#define IBU_P2_PMA_STATUS1_CSR_ADDR 0x011e0007L
+#define IBU_P2_PMA_STATUS1_CSR_STRIDE 1
+#define IBU_P2_PMA_STATUS1_CSR_DEPTH 1
+
+#define IBU_P2_PMA_STATUS2_CSR_ADDR 0x011e0008L
+#define IBU_P2_PMA_STATUS2_CSR_STRIDE 1
+#define IBU_P2_PMA_STATUS2_CSR_DEPTH 1
+
+#define IBU_P2_PMA_TXWCLK0_CNT_CSR_ADDR 0x011e0009L
+#define IBU_P2_PMA_TXWCLK0_CNT_CSR_STRIDE 1
+#define IBU_P2_PMA_TXWCLK0_CNT_CSR_DEPTH 1
+
+#define IBU_P2_PMA_TXWCLK0_CNT_VAL_ADDR 0x011e000aL
+#define IBU_P2_PMA_TXWCLK0_CNT_VAL_STRIDE 1
+#define IBU_P2_PMA_TXWCLK0_CNT_VAL_DEPTH 1
+
+#define IBU_P2_PMA_RXWCLK0_CNT_CSR_ADDR 0x011e000bL
+#define IBU_P2_PMA_RXWCLK0_CNT_CSR_STRIDE 1
+#define IBU_P2_PMA_RXWCLK0_CNT_CSR_DEPTH 1
+
+#define IBU_P2_PMA_RXWCLK0_CNT_VAL_ADDR 0x011e000cL
+#define IBU_P2_PMA_RXWCLK0_CNT_VAL_STRIDE 1
+#define IBU_P2_PMA_RXWCLK0_CNT_VAL_DEPTH 1
+
+#define IBU_P2_PMA_IRQ_STATUS_CSR_ADDR 0x011e000dL
+#define IBU_P2_PMA_IRQ_STATUS_CSR_STRIDE 1
+#define IBU_P2_PMA_IRQ_STATUS_CSR_DEPTH 1
+
+#define IBU_P2_PMA_IRQ_MASK_CSR_ADDR 0x011e000eL
+#define IBU_P2_PMA_IRQ_MASK_CSR_STRIDE 1
+#define IBU_P2_PMA_IRQ_MASK_CSR_DEPTH 1
+
+#define IBU_P2_PMA_BAD_CSR_ADDR 0x011efbadL
+#define IBU_P2_PMA_BAD_CSR_STRIDE 1
+#define IBU_P2_PMA_BAD_CSR_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG0_ADDR 0x01200000L
+#define PEU_P_REQ_CREDIT_REG0_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG0_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG0_ADDR 0x01200001L
+#define PEU_NP_REQ_CREDIT_REG0_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG0_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG0_ADDR 0x01200002L
+#define PEU_P_RETURN_CREDIT_REG0_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG0_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG0_ADDR 0x01200003L
+#define PEU_NP_RETURN_CREDIT_REG0_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG0_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG0_ADDR 0x01200004L
+#define PEU_P_RETURN_INTERVAL_REG0_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG0_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG0_ADDR 0x01200005L
+#define PEU_NP_RETURN_INTERVAL_REG0_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG0_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD0_ADDR 0x01200006L
+#define PEU_Q_NP_TAG_CNT_THLD0_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD0_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD0_ADDR 0x01200007L
+#define PEU_XADM_PH_CDTS_THLD0_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD0_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD0_ADDR 0x01200008L
+#define PEU_XADM_PD_CDTS_THLD0_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD0_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD0_ADDR 0x01200009L
+#define PEU_XADM_NPH_CDTS_THLD0_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD0_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD0_ADDR 0x0120000aL
+#define PEU_XADM_NPD_CDTS_THLD0_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD0_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG1_ADDR 0x0120000bL
+#define PEU_P_REQ_CREDIT_REG1_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG1_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG1_ADDR 0x0120000cL
+#define PEU_NP_REQ_CREDIT_REG1_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG1_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG1_ADDR 0x0120000dL
+#define PEU_P_RETURN_CREDIT_REG1_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG1_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG1_ADDR 0x0120000eL
+#define PEU_NP_RETURN_CREDIT_REG1_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG1_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG1_ADDR 0x0120000fL
+#define PEU_P_RETURN_INTERVAL_REG1_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG1_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG1_ADDR 0x01200010L
+#define PEU_NP_RETURN_INTERVAL_REG1_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG1_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD1_ADDR 0x01200011L
+#define PEU_Q_NP_TAG_CNT_THLD1_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD1_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD1_ADDR 0x01200012L
+#define PEU_XADM_PH_CDTS_THLD1_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD1_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD1_ADDR 0x01200013L
+#define PEU_XADM_PD_CDTS_THLD1_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD1_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD1_ADDR 0x01200014L
+#define PEU_XADM_NPH_CDTS_THLD1_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD1_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD1_ADDR 0x01200015L
+#define PEU_XADM_NPD_CDTS_THLD1_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD1_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG2_ADDR 0x01200016L
+#define PEU_P_REQ_CREDIT_REG2_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG2_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG2_ADDR 0x01200017L
+#define PEU_NP_REQ_CREDIT_REG2_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG2_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG2_ADDR 0x01200018L
+#define PEU_P_RETURN_CREDIT_REG2_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG2_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG2_ADDR 0x01200019L
+#define PEU_NP_RETURN_CREDIT_REG2_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG2_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG2_ADDR 0x0120001aL
+#define PEU_P_RETURN_INTERVAL_REG2_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG2_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG2_ADDR 0x0120001bL
+#define PEU_NP_RETURN_INTERVAL_REG2_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG2_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD2_ADDR 0x0120001cL
+#define PEU_Q_NP_TAG_CNT_THLD2_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD2_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD2_ADDR 0x0120001dL
+#define PEU_XADM_PH_CDTS_THLD2_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD2_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD2_ADDR 0x0120001eL
+#define PEU_XADM_PD_CDTS_THLD2_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD2_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD2_ADDR 0x0120001fL
+#define PEU_XADM_NPH_CDTS_THLD2_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD2_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD2_ADDR 0x01200020L
+#define PEU_XADM_NPD_CDTS_THLD2_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD2_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG3_ADDR 0x01200021L
+#define PEU_P_REQ_CREDIT_REG3_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG3_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG3_ADDR 0x01200022L
+#define PEU_NP_REQ_CREDIT_REG3_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG3_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG3_ADDR 0x01200023L
+#define PEU_P_RETURN_CREDIT_REG3_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG3_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG3_ADDR 0x01200024L
+#define PEU_NP_RETURN_CREDIT_REG3_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG3_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG3_ADDR 0x01200025L
+#define PEU_P_RETURN_INTERVAL_REG3_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG3_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG3_ADDR 0x01200026L
+#define PEU_NP_RETURN_INTERVAL_REG3_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG3_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD3_ADDR 0x01200027L
+#define PEU_Q_NP_TAG_CNT_THLD3_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD3_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD3_ADDR 0x01200028L
+#define PEU_XADM_PH_CDTS_THLD3_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD3_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD3_ADDR 0x01200029L
+#define PEU_XADM_PD_CDTS_THLD3_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD3_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD3_ADDR 0x0120002aL
+#define PEU_XADM_NPH_CDTS_THLD3_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD3_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD3_ADDR 0x0120002bL
+#define PEU_XADM_NPD_CDTS_THLD3_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD3_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG4_ADDR 0x0120002cL
+#define PEU_P_REQ_CREDIT_REG4_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG4_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG4_ADDR 0x0120002dL
+#define PEU_NP_REQ_CREDIT_REG4_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG4_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG4_ADDR 0x0120002eL
+#define PEU_P_RETURN_CREDIT_REG4_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG4_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG4_ADDR 0x0120002fL
+#define PEU_NP_RETURN_CREDIT_REG4_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG4_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG4_ADDR 0x01200030L
+#define PEU_P_RETURN_INTERVAL_REG4_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG4_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG4_ADDR 0x01200031L
+#define PEU_NP_RETURN_INTERVAL_REG4_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG4_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD4_ADDR 0x01200032L
+#define PEU_Q_NP_TAG_CNT_THLD4_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD4_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD4_ADDR 0x01200033L
+#define PEU_XADM_PH_CDTS_THLD4_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD4_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD4_ADDR 0x01200034L
+#define PEU_XADM_PD_CDTS_THLD4_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD4_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD4_ADDR 0x01200035L
+#define PEU_XADM_NPH_CDTS_THLD4_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD4_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD4_ADDR 0x01200036L
+#define PEU_XADM_NPD_CDTS_THLD4_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD4_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG5_ADDR 0x01200037L
+#define PEU_P_REQ_CREDIT_REG5_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG5_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG5_ADDR 0x01200038L
+#define PEU_NP_REQ_CREDIT_REG5_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG5_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG5_ADDR 0x01200039L
+#define PEU_P_RETURN_CREDIT_REG5_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG5_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG5_ADDR 0x0120003aL
+#define PEU_NP_RETURN_CREDIT_REG5_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG5_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG5_ADDR 0x0120003bL
+#define PEU_P_RETURN_INTERVAL_REG5_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG5_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG5_ADDR 0x0120003cL
+#define PEU_NP_RETURN_INTERVAL_REG5_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG5_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD5_ADDR 0x0120003dL
+#define PEU_Q_NP_TAG_CNT_THLD5_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD5_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD5_ADDR 0x0120003eL
+#define PEU_XADM_PH_CDTS_THLD5_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD5_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD5_ADDR 0x0120003fL
+#define PEU_XADM_PD_CDTS_THLD5_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD5_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD5_ADDR 0x01200040L
+#define PEU_XADM_NPH_CDTS_THLD5_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD5_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD5_ADDR 0x01200041L
+#define PEU_XADM_NPD_CDTS_THLD5_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD5_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG6_ADDR 0x01200042L
+#define PEU_P_REQ_CREDIT_REG6_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG6_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG6_ADDR 0x01200043L
+#define PEU_NP_REQ_CREDIT_REG6_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG6_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG6_ADDR 0x01200044L
+#define PEU_P_RETURN_CREDIT_REG6_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG6_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG6_ADDR 0x01200045L
+#define PEU_NP_RETURN_CREDIT_REG6_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG6_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG6_ADDR 0x01200046L
+#define PEU_P_RETURN_INTERVAL_REG6_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG6_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG6_ADDR 0x01200047L
+#define PEU_NP_RETURN_INTERVAL_REG6_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG6_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD6_ADDR 0x01200048L
+#define PEU_Q_NP_TAG_CNT_THLD6_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD6_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD6_ADDR 0x01200049L
+#define PEU_XADM_PH_CDTS_THLD6_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD6_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD6_ADDR 0x0120004aL
+#define PEU_XADM_PD_CDTS_THLD6_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD6_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD6_ADDR 0x0120004bL
+#define PEU_XADM_NPH_CDTS_THLD6_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD6_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD6_ADDR 0x0120004cL
+#define PEU_XADM_NPD_CDTS_THLD6_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD6_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG7_ADDR 0x0120004dL
+#define PEU_P_REQ_CREDIT_REG7_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG7_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG7_ADDR 0x0120004eL
+#define PEU_NP_REQ_CREDIT_REG7_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG7_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG7_ADDR 0x0120004fL
+#define PEU_P_RETURN_CREDIT_REG7_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG7_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG7_ADDR 0x01200050L
+#define PEU_NP_RETURN_CREDIT_REG7_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG7_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG7_ADDR 0x01200051L
+#define PEU_P_RETURN_INTERVAL_REG7_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG7_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG7_ADDR 0x01200052L
+#define PEU_NP_RETURN_INTERVAL_REG7_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG7_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD7_ADDR 0x01200053L
+#define PEU_Q_NP_TAG_CNT_THLD7_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD7_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD7_ADDR 0x01200054L
+#define PEU_XADM_PH_CDTS_THLD7_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD7_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD7_ADDR 0x01200055L
+#define PEU_XADM_PD_CDTS_THLD7_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD7_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD7_ADDR 0x01200056L
+#define PEU_XADM_NPH_CDTS_THLD7_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD7_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD7_ADDR 0x01200057L
+#define PEU_XADM_NPD_CDTS_THLD7_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD7_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG8_ADDR 0x01200058L
+#define PEU_P_REQ_CREDIT_REG8_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG8_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG8_ADDR 0x01200059L
+#define PEU_NP_REQ_CREDIT_REG8_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG8_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG8_ADDR 0x0120005aL
+#define PEU_P_RETURN_CREDIT_REG8_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG8_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG8_ADDR 0x0120005bL
+#define PEU_NP_RETURN_CREDIT_REG8_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG8_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG8_ADDR 0x0120005cL
+#define PEU_P_RETURN_INTERVAL_REG8_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG8_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG8_ADDR 0x0120005dL
+#define PEU_NP_RETURN_INTERVAL_REG8_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG8_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD8_ADDR 0x0120005eL
+#define PEU_Q_NP_TAG_CNT_THLD8_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD8_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD8_ADDR 0x0120005fL
+#define PEU_XADM_PH_CDTS_THLD8_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD8_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD8_ADDR 0x01200060L
+#define PEU_XADM_PD_CDTS_THLD8_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD8_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD8_ADDR 0x01200061L
+#define PEU_XADM_NPH_CDTS_THLD8_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD8_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD8_ADDR 0x01200062L
+#define PEU_XADM_NPD_CDTS_THLD8_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD8_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG9_ADDR 0x01200063L
+#define PEU_P_REQ_CREDIT_REG9_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG9_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG9_ADDR 0x01200064L
+#define PEU_NP_REQ_CREDIT_REG9_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG9_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG9_ADDR 0x01200065L
+#define PEU_P_RETURN_CREDIT_REG9_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG9_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG9_ADDR 0x01200066L
+#define PEU_NP_RETURN_CREDIT_REG9_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG9_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG9_ADDR 0x01200067L
+#define PEU_P_RETURN_INTERVAL_REG9_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG9_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG9_ADDR 0x01200068L
+#define PEU_NP_RETURN_INTERVAL_REG9_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG9_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD9_ADDR 0x01200069L
+#define PEU_Q_NP_TAG_CNT_THLD9_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD9_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD9_ADDR 0x0120006aL
+#define PEU_XADM_PH_CDTS_THLD9_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD9_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD9_ADDR 0x0120006bL
+#define PEU_XADM_PD_CDTS_THLD9_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD9_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD9_ADDR 0x0120006cL
+#define PEU_XADM_NPH_CDTS_THLD9_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD9_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD9_ADDR 0x0120006dL
+#define PEU_XADM_NPD_CDTS_THLD9_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD9_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG10_ADDR 0x0120006eL
+#define PEU_P_REQ_CREDIT_REG10_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG10_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG10_ADDR 0x0120006fL
+#define PEU_NP_REQ_CREDIT_REG10_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG10_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG10_ADDR 0x01200070L
+#define PEU_P_RETURN_CREDIT_REG10_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG10_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG10_ADDR 0x01200071L
+#define PEU_NP_RETURN_CREDIT_REG10_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG10_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG10_ADDR 0x01200072L
+#define PEU_P_RETURN_INTERVAL_REG10_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG10_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG10_ADDR 0x01200073L
+#define PEU_NP_RETURN_INTERVAL_REG10_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG10_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD10_ADDR 0x01200074L
+#define PEU_Q_NP_TAG_CNT_THLD10_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD10_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD10_ADDR 0x01200075L
+#define PEU_XADM_PH_CDTS_THLD10_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD10_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD10_ADDR 0x01200076L
+#define PEU_XADM_PD_CDTS_THLD10_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD10_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD10_ADDR 0x01200077L
+#define PEU_XADM_NPH_CDTS_THLD10_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD10_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD10_ADDR 0x01200078L
+#define PEU_XADM_NPD_CDTS_THLD10_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD10_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG11_ADDR 0x01200079L
+#define PEU_P_REQ_CREDIT_REG11_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG11_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG11_ADDR 0x0120007aL
+#define PEU_NP_REQ_CREDIT_REG11_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG11_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG11_ADDR 0x0120007bL
+#define PEU_P_RETURN_CREDIT_REG11_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG11_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG11_ADDR 0x0120007cL
+#define PEU_NP_RETURN_CREDIT_REG11_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG11_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG11_ADDR 0x0120007dL
+#define PEU_P_RETURN_INTERVAL_REG11_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG11_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG11_ADDR 0x0120007eL
+#define PEU_NP_RETURN_INTERVAL_REG11_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG11_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD11_ADDR 0x0120007fL
+#define PEU_Q_NP_TAG_CNT_THLD11_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD11_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD11_ADDR 0x01200080L
+#define PEU_XADM_PH_CDTS_THLD11_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD11_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD11_ADDR 0x01200081L
+#define PEU_XADM_PD_CDTS_THLD11_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD11_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD11_ADDR 0x01200082L
+#define PEU_XADM_NPH_CDTS_THLD11_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD11_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD11_ADDR 0x01200083L
+#define PEU_XADM_NPD_CDTS_THLD11_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD11_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG12_ADDR 0x01200084L
+#define PEU_P_REQ_CREDIT_REG12_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG12_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG12_ADDR 0x01200085L
+#define PEU_NP_REQ_CREDIT_REG12_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG12_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG12_ADDR 0x01200086L
+#define PEU_P_RETURN_CREDIT_REG12_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG12_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG12_ADDR 0x01200087L
+#define PEU_NP_RETURN_CREDIT_REG12_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG12_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG12_ADDR 0x01200088L
+#define PEU_P_RETURN_INTERVAL_REG12_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG12_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG12_ADDR 0x01200089L
+#define PEU_NP_RETURN_INTERVAL_REG12_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG12_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD12_ADDR 0x0120008aL
+#define PEU_Q_NP_TAG_CNT_THLD12_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD12_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD12_ADDR 0x0120008bL
+#define PEU_XADM_PH_CDTS_THLD12_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD12_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD12_ADDR 0x0120008cL
+#define PEU_XADM_PD_CDTS_THLD12_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD12_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD12_ADDR 0x0120008dL
+#define PEU_XADM_NPH_CDTS_THLD12_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD12_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD12_ADDR 0x0120008eL
+#define PEU_XADM_NPD_CDTS_THLD12_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD12_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG13_ADDR 0x0120008fL
+#define PEU_P_REQ_CREDIT_REG13_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG13_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG13_ADDR 0x01200090L
+#define PEU_NP_REQ_CREDIT_REG13_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG13_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG13_ADDR 0x01200091L
+#define PEU_P_RETURN_CREDIT_REG13_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG13_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG13_ADDR 0x01200092L
+#define PEU_NP_RETURN_CREDIT_REG13_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG13_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG13_ADDR 0x01200093L
+#define PEU_P_RETURN_INTERVAL_REG13_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG13_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG13_ADDR 0x01200094L
+#define PEU_NP_RETURN_INTERVAL_REG13_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG13_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD13_ADDR 0x01200095L
+#define PEU_Q_NP_TAG_CNT_THLD13_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD13_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD13_ADDR 0x01200096L
+#define PEU_XADM_PH_CDTS_THLD13_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD13_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD13_ADDR 0x01200097L
+#define PEU_XADM_PD_CDTS_THLD13_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD13_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD13_ADDR 0x01200098L
+#define PEU_XADM_NPH_CDTS_THLD13_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD13_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD13_ADDR 0x01200099L
+#define PEU_XADM_NPD_CDTS_THLD13_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD13_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG14_ADDR 0x0120009aL
+#define PEU_P_REQ_CREDIT_REG14_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG14_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG14_ADDR 0x0120009bL
+#define PEU_NP_REQ_CREDIT_REG14_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG14_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG14_ADDR 0x0120009cL
+#define PEU_P_RETURN_CREDIT_REG14_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG14_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG14_ADDR 0x0120009dL
+#define PEU_NP_RETURN_CREDIT_REG14_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG14_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG14_ADDR 0x0120009eL
+#define PEU_P_RETURN_INTERVAL_REG14_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG14_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG14_ADDR 0x0120009fL
+#define PEU_NP_RETURN_INTERVAL_REG14_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG14_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD14_ADDR 0x012000a0L
+#define PEU_Q_NP_TAG_CNT_THLD14_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD14_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD14_ADDR 0x012000a1L
+#define PEU_XADM_PH_CDTS_THLD14_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD14_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD14_ADDR 0x012000a2L
+#define PEU_XADM_PD_CDTS_THLD14_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD14_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD14_ADDR 0x012000a3L
+#define PEU_XADM_NPH_CDTS_THLD14_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD14_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD14_ADDR 0x012000a4L
+#define PEU_XADM_NPD_CDTS_THLD14_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD14_DEPTH 1
+
+#define PEU_P_REQ_CREDIT_REG15_ADDR 0x012000a5L
+#define PEU_P_REQ_CREDIT_REG15_STRIDE 1
+#define PEU_P_REQ_CREDIT_REG15_DEPTH 1
+
+#define PEU_NP_REQ_CREDIT_REG15_ADDR 0x012000a6L
+#define PEU_NP_REQ_CREDIT_REG15_STRIDE 1
+#define PEU_NP_REQ_CREDIT_REG15_DEPTH 1
+
+#define PEU_P_RETURN_CREDIT_REG15_ADDR 0x012000a7L
+#define PEU_P_RETURN_CREDIT_REG15_STRIDE 1
+#define PEU_P_RETURN_CREDIT_REG15_DEPTH 1
+
+#define PEU_NP_RETURN_CREDIT_REG15_ADDR 0x012000a8L
+#define PEU_NP_RETURN_CREDIT_REG15_STRIDE 1
+#define PEU_NP_RETURN_CREDIT_REG15_DEPTH 1
+
+#define PEU_P_RETURN_INTERVAL_REG15_ADDR 0x012000a9L
+#define PEU_P_RETURN_INTERVAL_REG15_STRIDE 1
+#define PEU_P_RETURN_INTERVAL_REG15_DEPTH 1
+
+#define PEU_NP_RETURN_INTERVAL_REG15_ADDR 0x012000aaL
+#define PEU_NP_RETURN_INTERVAL_REG15_STRIDE 1
+#define PEU_NP_RETURN_INTERVAL_REG15_DEPTH 1
+
+#define PEU_Q_NP_TAG_CNT_THLD15_ADDR 0x012000abL
+#define PEU_Q_NP_TAG_CNT_THLD15_STRIDE 1
+#define PEU_Q_NP_TAG_CNT_THLD15_DEPTH 1
+
+#define PEU_XADM_PH_CDTS_THLD15_ADDR 0x012000acL
+#define PEU_XADM_PH_CDTS_THLD15_STRIDE 1
+#define PEU_XADM_PH_CDTS_THLD15_DEPTH 1
+
+#define PEU_XADM_PD_CDTS_THLD15_ADDR 0x012000adL
+#define PEU_XADM_PD_CDTS_THLD15_STRIDE 1
+#define PEU_XADM_PD_CDTS_THLD15_DEPTH 1
+
+#define PEU_XADM_NPH_CDTS_THLD15_ADDR 0x012000aeL
+#define PEU_XADM_NPH_CDTS_THLD15_STRIDE 1
+#define PEU_XADM_NPH_CDTS_THLD15_DEPTH 1
+
+#define PEU_XADM_NPD_CDTS_THLD15_ADDR 0x012000afL
+#define PEU_XADM_NPD_CDTS_THLD15_STRIDE 1
+#define PEU_XADM_NPD_CDTS_THLD15_DEPTH 1
+
+#define PEU_HPRI_Q_REG_ADDR 0x012000b0L
+#define PEU_HPRI_Q_REG_STRIDE 1
+#define PEU_HPRI_Q_REG_DEPTH 1
+
+#define PEU_HPRI_RR_WEIGHT_REG_ADDR 0x012000b1L
+#define PEU_HPRI_RR_WEIGHT_REG_STRIDE 1
+#define PEU_HPRI_RR_WEIGHT_REG_DEPTH 1
+
+#define PEU_MAX_RD_REQ_SIZE_REG_ADDR 0x012000b2L
+#define PEU_MAX_RD_REQ_SIZE_REG_STRIDE 1
+#define PEU_MAX_RD_REQ_SIZE_REG_DEPTH 1
+
+#define PEU_DIRTY_PCI_TAG_CTL_REG_ADDR 0x012000b3L
+#define PEU_DIRTY_PCI_TAG_CTL_REG_STRIDE 1
+#define PEU_DIRTY_PCI_TAG_CTL_REG_DEPTH 1
+
+#define PEU_MASTER_VEC_ST_REG_ADDR 0x012000b4L
+#define PEU_MASTER_VEC_ST_REG_STRIDE 1
+#define PEU_MASTER_VEC_ST_REG_DEPTH 1
+
+#define PEU_MASTER_VEC_MSK_REG_ADDR 0x012000b5L
+#define PEU_MASTER_VEC_MSK_REG_STRIDE 1
+#define PEU_MASTER_VEC_MSK_REG_DEPTH 1
+
+#define PEU_FLR_REQ_DBG_REG_ADDR 0x012000b6L
+#define PEU_FLR_REQ_DBG_REG_STRIDE 1
+#define PEU_FLR_REQ_DBG_REG_DEPTH 1
+
+#define PEU_FLR_DONE_DBG_REG_ADDR 0x012000b7L
+#define PEU_FLR_DONE_DBG_REG_STRIDE 1
+#define PEU_FLR_DONE_DBG_REG_DEPTH 1
+
+#define PEU_FLR_REQ_VEC_ST_REG_ADDR 0x012000b8L
+#define PEU_FLR_REQ_VEC_ST_REG_STRIDE 1
+#define PEU_FLR_REQ_VEC_ST_REG_DEPTH 1
+
+#define PEU_FLR_DONE_VEC_ST_REG_ADDR 0x012000b9L
+#define PEU_FLR_DONE_VEC_ST_REG_STRIDE 1
+#define PEU_FLR_DONE_VEC_ST_REG_DEPTH 1
+
+#define PEU_TAG_POOL_DBG_REG_ADDR 0x012000baL
+#define PEU_TAG_POOL_DBG_REG_STRIDE 1
+#define PEU_TAG_POOL_DBG_REG_DEPTH 1
+
+#define PEU_LTSSM_DBG_REG_ADDR 0x012000bbL
+#define PEU_LTSSM_DBG_REG_STRIDE 1
+#define PEU_LTSSM_DBG_REG_DEPTH 1
+
+#define PEU_TSU_REQ_DBG_REG_ADDR 0x012000bcL
+#define PEU_TSU_REQ_DBG_REG_STRIDE 1
+#define PEU_TSU_REQ_DBG_REG_DEPTH 1
+
+#define PEU_EPS_REQ_DBG_REG_ADDR 0x012000bdL
+#define PEU_EPS_REQ_DBG_REG_STRIDE 1
+#define PEU_EPS_REQ_DBG_REG_DEPTH 1
+
+#define PEU_P_REQ_DBG_REG_ADDR 0x012000beL
+#define PEU_P_REQ_DBG_REG_STRIDE 1
+#define PEU_P_REQ_DBG_REG_DEPTH 1
+
+#define PEU_NP_REQ_DBG_REG_ADDR 0x012000bfL
+#define PEU_NP_REQ_DBG_REG_STRIDE 1
+#define PEU_NP_REQ_DBG_REG_DEPTH 1
+
+#define PEU_DBI_CSR_WDAT_REG_ADDR 0x012000c0L
+#define PEU_DBI_CSR_WDAT_REG_STRIDE 1
+#define PEU_DBI_CSR_WDAT_REG_DEPTH 1
+
+#define PEU_DBI_CSR_CMD_REG_ADDR 0x012000c1L
+#define PEU_DBI_CSR_CMD_REG_STRIDE 1
+#define PEU_DBI_CSR_CMD_REG_DEPTH 1
+
+#define PEU_DBI_CSR_STATUS_REG_ADDR 0x012000c2L
+#define PEU_DBI_CSR_STATUS_REG_STRIDE 1
+#define PEU_DBI_CSR_STATUS_REG_DEPTH 1
+
+#define PEU_DBI_CSR_RDAT_REG_ADDR 0x012000c3L
+#define PEU_DBI_CSR_RDAT_REG_STRIDE 1
+#define PEU_DBI_CSR_RDAT_REG_DEPTH 1
+
+#define PEU_CPL_BUF_WATER_MARK_REG_ADDR 0x012000c4L
+#define PEU_CPL_BUF_WATER_MARK_REG_STRIDE 1
+#define PEU_CPL_BUF_WATER_MARK_REG_DEPTH 1
+
+#define PEU_ARB_CPL_BUF_THLD_REG_ADDR 0x012000c5L
+#define PEU_ARB_CPL_BUF_THLD_REG_STRIDE 1
+#define PEU_ARB_CPL_BUF_THLD_REG_DEPTH 1
+
+#define PEU_CPL_BUF_CREDIT_REG_ADDR 0x012000c6L
+#define PEU_CPL_BUF_CREDIT_REG_STRIDE 1
+#define PEU_CPL_BUF_CREDIT_REG_DEPTH 1
+
+#define PEU_CPL_MAX_CREDIT_REG_ADDR 0x012000c7L
+#define PEU_CPL_MAX_CREDIT_REG_STRIDE 1
+#define PEU_CPL_MAX_CREDIT_REG_DEPTH 1
+
+#define PEU_PCIE_PHY_CTL_REG_ADDR 0x012000c8L
+#define PEU_PCIE_PHY_CTL_REG_STRIDE 1
+#define PEU_PCIE_PHY_CTL_REG_DEPTH 1
+
+#define PEU_FORCE_ERR_REG_ADDR 0x012000c9L
+#define PEU_FORCE_ERR_REG_STRIDE 1
+#define PEU_FORCE_ERR_REG_DEPTH 1
+
+#define PEU_MSG_GEN_QW0_REG_ADDR 0x012000caL
+#define PEU_MSG_GEN_QW0_REG_STRIDE 1
+#define PEU_MSG_GEN_QW0_REG_DEPTH 1
+
+#define PEU_MSG_GEN_QW1_REG_ADDR 0x012000cbL
+#define PEU_MSG_GEN_QW1_REG_STRIDE 1
+#define PEU_MSG_GEN_QW1_REG_DEPTH 1
+
+#define PEU_MSG_STATUS_REG_ADDR 0x012000ccL
+#define PEU_MSG_STATUS_REG_STRIDE 1
+#define PEU_MSG_STATUS_REG_DEPTH 1
+
+#define PEU_ATS_MSG_QW0_REG_ADDR 0x012000cdL
+#define PEU_ATS_MSG_QW0_REG_STRIDE 1
+#define PEU_ATS_MSG_QW0_REG_DEPTH 1
+
+#define PEU_ATS_MSG_QW1_REG_ADDR 0x012000ceL
+#define PEU_ATS_MSG_QW1_REG_STRIDE 1
+#define PEU_ATS_MSG_QW1_REG_DEPTH 1
+
+#define PEU_SRAM_CORR_ERR_STATUS_REG_ADDR 0x012000cfL
+#define PEU_SRAM_CORR_ERR_STATUS_REG_STRIDE 1
+#define PEU_SRAM_CORR_ERR_STATUS_REG_DEPTH 1
+
+#define PEU_HI_PRI_MSK_REG_ADDR 0x012000d0L
+#define PEU_HI_PRI_MSK_REG_STRIDE 1
+#define PEU_HI_PRI_MSK_REG_DEPTH 1
+
+#define PEU_HI_PRI_INTR_VEC_REG_ADDR 0x012000d1L
+#define PEU_HI_PRI_INTR_VEC_REG_STRIDE 1
+#define PEU_HI_PRI_INTR_VEC_REG_DEPTH 1
+
+#define PEU_FATAL_INTR_MSK_REG_ADDR 0x012000d2L
+#define PEU_FATAL_INTR_MSK_REG_STRIDE 1
+#define PEU_FATAL_INTR_MSK_REG_DEPTH 1
+
+#define PEU_FATAL_INTR_VEC_REG_ADDR 0x012000d3L
+#define PEU_FATAL_INTR_VEC_REG_STRIDE 1
+#define PEU_FATAL_INTR_VEC_REG_DEPTH 1
+
+#define PEU_INTR_REQ_DBG_REG_ADDR 0x012000d4L
+#define PEU_INTR_REQ_DBG_REG_STRIDE 1
+#define PEU_INTR_REQ_DBG_REG_DEPTH 1
+
+#define PEU_TSU_PIO_REQ_DBG_REG_ADDR 0x012000d5L
+#define PEU_TSU_PIO_REQ_DBG_REG_STRIDE 1
+#define PEU_TSU_PIO_REQ_DBG_REG_DEPTH 1
+
+#define PEU_EPRM_PIO_REQ_DBG_REG_ADDR 0x012000d6L
+#define PEU_EPRM_PIO_REQ_DBG_REG_STRIDE 1
+#define PEU_EPRM_PIO_REQ_DBG_REG_DEPTH 1
+
+#define PEU_INTR_PIO_REQ_DBG_REG_ADDR 0x012000d7L
+#define PEU_INTR_PIO_REQ_DBG_REG_STRIDE 1
+#define PEU_INTR_PIO_REQ_DBG_REG_DEPTH 1
+
+#define PEU_CPL_FLUSH_DBG_REG_ADDR 0x012000d8L
+#define PEU_CPL_FLUSH_DBG_REG_STRIDE 1
+#define PEU_CPL_FLUSH_DBG_REG_DEPTH 1
+
+#define PEU_EP_DIAG_DBG_REG_ADDR 0x012000d9L
+#define PEU_EP_DIAG_DBG_REG_STRIDE 1
+#define PEU_EP_DIAG_DBG_REG_DEPTH 1
+
+#define PEU_CXPL_EI_DBG_REG_ADDR 0x012000daL
+#define PEU_CXPL_EI_DBG_REG_STRIDE 1
+#define PEU_CXPL_EI_DBG_REG_DEPTH 1
+
+#define PEU_CXPL_DBG_REG_ADDR 0x012000dbL
+#define PEU_CXPL_DBG_REG_STRIDE 1
+#define PEU_CXPL_DBG_REG_DEPTH 1
+
+#define PEU_FF_DC_1_DBG_REG_ADDR 0x012000dcL
+#define PEU_FF_DC_1_DBG_REG_STRIDE 1
+#define PEU_FF_DC_1_DBG_REG_DEPTH 1
+
+#define PEU_FF_DC_2_DBG_REG_ADDR 0x012000ddL
+#define PEU_FF_DC_2_DBG_REG_STRIDE 1
+#define PEU_FF_DC_2_DBG_REG_DEPTH 1
+
+#define PEU_FORCE_FLR_REG_ADDR 0x012000deL
+#define PEU_FORCE_FLR_REG_STRIDE 1
+#define PEU_FORCE_FLR_REG_DEPTH 1
+
+#define PEU_CSR_PEU_CTL_ST_REG_ADDR 0x01200100L
+#define PEU_CSR_PEU_CTL_ST_REG_STRIDE 1
+#define PEU_CSR_PEU_CTL_ST_REG_DEPTH 1
+
+#define PEU_CSR_PEU_INT_ST_REG_ADDR 0x01200101L
+#define PEU_CSR_PEU_INT_ST_REG_STRIDE 1
+#define PEU_CSR_PEU_INT_ST_REG_DEPTH 1
+
+#define PEU_CSR_PEU_INT_MSK_REG_ADDR 0x01200102L
+#define PEU_CSR_PEU_INT_MSK_REG_STRIDE 1
+#define PEU_CSR_PEU_INT_MSK_REG_DEPTH 1
+
+#define PEU_CSR_LP_INTR_VEC_REG_ADDR 0x01200103L
+#define PEU_CSR_LP_INTR_VEC_REG_STRIDE 1
+#define PEU_CSR_LP_INTR_VEC_REG_DEPTH 1
+
+#define PEU_CSR_LPRI_INT_MSK_REG_ADDR 0x01200104L
+#define PEU_CSR_LPRI_INT_MSK_REG_STRIDE 1
+#define PEU_CSR_LPRI_INT_MSK_REG_DEPTH 1
+
+#define PEU_CSR_SER_INT_ST_REG_ADDR 0x01200105L
+#define PEU_CSR_SER_INT_ST_REG_STRIDE 1
+#define PEU_CSR_SER_INT_ST_REG_DEPTH 1
+
+#define PEU_TSU_FLR_REQ_DBG_REG_ADDR 0x012001b0L
+#define PEU_TSU_FLR_REQ_DBG_REG_STRIDE 1
+#define PEU_TSU_FLR_REQ_DBG_REG_DEPTH 1
+
+#define PEU_TSU_FLR_DONE_DBG_REG_ADDR 0x012001b1L
+#define PEU_TSU_FLR_DONE_DBG_REG_STRIDE 1
+#define PEU_TSU_FLR_DONE_DBG_REG_DEPTH 1
+
+#define PEU_EPS_FLR_REQ_DBG_REG_ADDR 0x012001b2L
+#define PEU_EPS_FLR_REQ_DBG_REG_STRIDE 1
+#define PEU_EPS_FLR_REQ_DBG_REG_DEPTH 1
+
+#define PEU_EPS_FLR_DONE_DBG_REG_ADDR 0x012001b3L
+#define PEU_EPS_FLR_DONE_DBG_REG_STRIDE 1
+#define PEU_EPS_FLR_DONE_DBG_REG_DEPTH 1
+
+#define PEU_PIPE_CSR_WDAT_REG_ADDR 0x012001b4L
+#define PEU_PIPE_CSR_WDAT_REG_STRIDE 1
+#define PEU_PIPE_CSR_WDAT_REG_DEPTH 1
+
+#define PEU_PIPE_CSR_CMD_REG_ADDR 0x012001b5L
+#define PEU_PIPE_CSR_CMD_REG_STRIDE 1
+#define PEU_PIPE_CSR_CMD_REG_DEPTH 1
+
+#define PEU_PIPE_CSR_STATUS_REG_ADDR 0x012001b6L
+#define PEU_PIPE_CSR_STATUS_REG_STRIDE 1
+#define PEU_PIPE_CSR_STATUS_REG_DEPTH 1
+
+#define PEU_PIPE_CSR_RDAT_REG_ADDR 0x012001b7L
+#define PEU_PIPE_CSR_RDAT_REG_STRIDE 1
+#define PEU_PIPE_CSR_RDAT_REG_DEPTH 1
+
+#define PEU_SER_CSR_WDAT_REG_ADDR 0x012001b8L
+#define PEU_SER_CSR_WDAT_REG_STRIDE 1
+#define PEU_SER_CSR_WDAT_REG_DEPTH 1
+
+#define PEU_SER_CSR_CMD_REG_ADDR 0x012001b9L
+#define PEU_SER_CSR_CMD_REG_STRIDE 1
+#define PEU_SER_CSR_CMD_REG_DEPTH 1
+
+#define PEU_SER_CSR_STATUS_REG_ADDR 0x012001baL
+#define PEU_SER_CSR_STATUS_REG_STRIDE 1
+#define PEU_SER_CSR_STATUS_REG_DEPTH 1
+
+#define PEU_SER_CSR_RDAT_REG_ADDR 0x012001bbL
+#define PEU_SER_CSR_RDAT_REG_STRIDE 1
+#define PEU_SER_CSR_RDAT_REG_DEPTH 1
+
+#define PEU_SER_1_CSR_WDAT_REG_ADDR 0x012001bcL
+#define PEU_SER_1_CSR_WDAT_REG_STRIDE 1
+#define PEU_SER_1_CSR_WDAT_REG_DEPTH 1
+
+#define PEU_SER_1_CSR_CMD_REG_ADDR 0x012001bdL
+#define PEU_SER_1_CSR_CMD_REG_STRIDE 1
+#define PEU_SER_1_CSR_CMD_REG_DEPTH 1
+
+#define PEU_SER_1_CSR_STATUS_REG_ADDR 0x012001beL
+#define PEU_SER_1_CSR_STATUS_REG_STRIDE 1
+#define PEU_SER_1_CSR_STATUS_REG_DEPTH 1
+
+#define PEU_SER_1_CSR_RDAT_REG_ADDR 0x012001bfL
+#define PEU_SER_1_CSR_RDAT_REG_STRIDE 1
+#define PEU_SER_1_CSR_RDAT_REG_DEPTH 1
+
+#define PEU_SER_DFE_ST_SEL_REG_ADDR 0x012001c0L
+#define PEU_SER_DFE_ST_SEL_REG_STRIDE 1
+#define PEU_SER_DFE_ST_SEL_REG_DEPTH 1
+
+#define PEU_SER_DFE_ST_0_REG_ADDR 0x012001c1L
+#define PEU_SER_DFE_ST_0_REG_STRIDE 1
+#define PEU_SER_DFE_ST_0_REG_DEPTH 1
+
+#define PEU_SER_DFE_ST_1_REG_ADDR 0x012001c2L
+#define PEU_SER_DFE_ST_1_REG_STRIDE 1
+#define PEU_SER_DFE_ST_1_REG_DEPTH 1
+
+#define PEU_SER_DFE_ST_2_REG_ADDR 0x012001c3L
+#define PEU_SER_DFE_ST_2_REG_STRIDE 1
+#define PEU_SER_DFE_ST_2_REG_DEPTH 1
+
+#define PEU_SER_DFE_ST_3_REG_ADDR 0x012001c4L
+#define PEU_SER_DFE_ST_3_REG_STRIDE 1
+#define PEU_SER_DFE_ST_3_REG_DEPTH 1
+
+#define PEU_SER_POWERDOWN_CTL_REG_ADDR 0x012001f0L
+#define PEU_SER_POWERDOWN_CTL_REG_STRIDE 1
+#define PEU_SER_POWERDOWN_CTL_REG_DEPTH 1
+
+#define PEU_SER_CFG0_REG_ADDR 0x012001f1L
+#define PEU_SER_CFG0_REG_STRIDE 1
+#define PEU_SER_CFG0_REG_DEPTH 1
+
+#define PEU_SER_CFG1_REG_ADDR 0x012001f2L
+#define PEU_SER_CFG1_REG_STRIDE 1
+#define PEU_SER_CFG1_REG_DEPTH 1
+
+#define PEU_SER_CFG2_REG_ADDR 0x012001f3L
+#define PEU_SER_CFG2_REG_STRIDE 1
+#define PEU_SER_CFG2_REG_DEPTH 1
+
+#define PEU_SER_CFG3_REG_ADDR 0x012001f4L
+#define PEU_SER_CFG3_REG_STRIDE 1
+#define PEU_SER_CFG3_REG_DEPTH 1
+
+#define PEU_CSR_SER_CTL_REG_ADDR 0x012001f5L
+#define PEU_CSR_SER_CTL_REG_STRIDE 1
+#define PEU_CSR_SER_CTL_REG_DEPTH 1
+
+#define PEU_CSR_SER_ST_REG_ADDR 0x012001f6L
+#define PEU_CSR_SER_ST_REG_STRIDE 1
+#define PEU_CSR_SER_ST_REG_DEPTH 1
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _PSIF_FW_ADDR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_csr.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PSIF_HW_CSR_H
+#define _PSIF_HW_CSR_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "psif_api.h"
+
+/* The psif base address setup access ids */
+enum psif_csr_map {
+ PSIF_CSR_ADDR_BASE_ADDR_ATSP = 0x5248,
+ PSIF_CSR_ADDR_BASE_ADDR_AH = 0x55948,
+ PSIF_CSR_ADDR_BASE_ADDR_QP = 0x55960,
+ PSIF_CSR_ADDR_BASE_ADDR_SQ_CMPL = 0x59d68,
+ PSIF_CSR_ADDR_BASE_ADDR_KEY = 0x59d80,
+ PSIF_CSR_ADDR_BASE_ADDR_RQSP = 0x59e08,
+ PSIF_CSR_ADDR_BASE_ADDR_RQ_SW = 0x59e20,
+ PSIF_CSR_ADDR_BASE_ADDR_RQ_HW = 0x59e38,
+ PSIF_CSR_ADDR_BASE_ADDR_SQ_SW = 0xc4548,
+ PSIF_CSR_ADDR_BASE_ADDR_SQ_HW = 0xc4560,
+ PSIF_CSR_ADDR_BASE_ADDR_SQ_RING = 0xc4d18,
+ PSIF_CSR_ADDR_BASE_ADDR_SQ_RSPQ = 0xc4f68,
+ PSIF_CSR_ADDR_BASE_ADDR_SQ_TVL = 0xc5388,
+ PSIF_CSR_ADDR_BASE_ADDR_CQ_SW = 0xcd7a0,
+ PSIF_CSR_ADDR_BASE_ADDR_CQ_HW = 0xcd7b8,
+ PSIF_CSR_ADDR_END = 0xce9f0
+}; /* enum psif_csr_map */
+
+/* The psif base address setup access ids as offset in a struct */
+/* *** DEPRECATED DATA TYPE *** */
+struct psif_csr_be {
+ __be64 ingenting_01[((0x5248) / sizeof(__be64))];
+ /* HW:TSU_HOST_QP_BASE_ADDR_0 -> struct base_addr_atsp [165 bits] */
+ __be64 base_addr_atsp[3]; /* Offset 0x5248 */
+ /* HW:TSU_QPS_AHA_BASE_ADDR_0 -> struct base_addr_ah [165 bits] */
+ __be64 ingenting_03[((0x55948 - 0x5248) / sizeof(__be64)) - 3];
+ __be64 base_addr_ah[3]; /* Offset 0x55948 */
+ /* HW:TSU_QPS_QP_BASE_ADDR_0 -> struct base_addr_qp [165 bits] */
+ __be64 ingenting_04[((0x55960 - 0x55948) / sizeof(__be64)) - 3];
+ __be64 base_addr_qp[3]; /* Offset 0x55960 */
+ /* HW:TSU_CMPL_SQ_BASE_ADDR_0 -> struct base_addr_sq_cmpl [165 bits] */
+ __be64 ingenting_05[((0x59d68 - 0x55960) / sizeof(__be64)) - 3];
+ __be64 base_addr_sq_cmpl[3]; /* Offset 0x59d68 */
+ /* HW:TSU_VAL_KEY_BASE_ADDR_0 -> struct base_addr_key [165 bits] */
+ __be64 ingenting_06[((0x59d80 - 0x59d68) / sizeof(__be64)) - 3];
+ __be64 base_addr_key[3]; /* Offset 0x59d80 */
+ /* HW:TSU_RQH_QP_BASE_ADDR_0 -> struct base_addr_rqsp [165 bits] */
+ __be64 ingenting_07[((0x59e08 - 0x59d80) / sizeof(__be64)) - 3];
+ __be64 base_addr_rqsp[3]; /* Offset 0x59e08 */
+ /* HW:TSU_DSCR_RQ_BASE_ADDR_SW_0 -> struct base_addr_rq_sw [165 bits] */
+ __be64 ingenting_08[((0x59e20 - 0x59e08) / sizeof(__be64)) - 3];
+ __be64 base_addr_rq_sw[3]; /* Offset 0x59e20 */
+ /* HW:TSU_DSCR_RQ_BASE_ADDR_HW_0 -> struct base_addr_rq_hw [165 bits] */
+ __be64 ingenting_09[((0x59e38 - 0x59e20) / sizeof(__be64)) - 3];
+ __be64 base_addr_rq_hw[3]; /* Offset 0x59e38 */
+ /* HW:TSU_IBPR_P1_EOIB_MAC1 SW:ibpr_p1_eoib_mac1
+ * -> struct psif_csr_ibpr_p1_eoib_mac1 [64 bits] */
+ __be64 ingenting_10[((0xbfcb8 - 0x59e38) / sizeof(__be64)) - 1];
+ __be64 ibpr_p1_eoib_mac1; /* Offset 0xbfcb8 */
+ /* HW:TSU_IBPR_P1_EOIB_MAC2 SW:ibpr_p1_eoib_mac2
+ * -> struct psif_csr_ibpr_p1_eoib_mac2 [64 bits] */
+ __be64 ingenting_11[((0xbfcc0 - 0xbfcb8) / sizeof(__be64)) - 1];
+ __be64 ibpr_p1_eoib_mac2; /* Offset 0xbfcc0 */
+ /* HW:TSU_IBPR_P2_EOIB_MAC1 SW:ibpr_p2_eoib_mac1
+ * -> struct psif_csr_ibpr_p2_eoib_mac1 [64 bits] */
+ __be64 ingenting_12[((0xbfcc8 - 0xbfcc0) / sizeof(__be64)) - 1];
+ __be64 ibpr_p2_eoib_mac1; /* Offset 0xbfcc8 */
+ /* HW:TSU_IBPR_P2_EOIB_MAC2 SW:ibpr_p2_eoib_mac2
+ * -> struct psif_csr_ibpr_p2_eoib_mac2 [64 bits] */
+ __be64 ingenting_13[((0xbfcd0 - 0xbfcc8) / sizeof(__be64)) - 1];
+ __be64 ibpr_p2_eoib_mac2; /* Offset 0xbfcd0 */
+ /* HW:TSU_SQS_SQ_BASE_ADDR_SW_0 -> struct base_addr_sq_sw [165 bits] */
+ __be64 ingenting_14[((0xc4548 - 0xbfcd0) / sizeof(__be64)) - 3];
+ __be64 base_addr_sq_sw[3]; /* Offset 0xc4548 */
+ /* HW:TSU_SQS_SQ_BASE_ADDR_HW_0 -> struct base_addr_sq_hw [165 bits] */
+ __be64 ingenting_15[((0xc4560 - 0xc4548) / sizeof(__be64)) - 3];
+ __be64 base_addr_sq_hw[3]; /* Offset 0xc4560 */
+ /* HW:TSU_SQS_PIO_RING_BASE_ADDR_0 -> struct base_addr_sq_ring [165 bits] */
+ __be64 ingenting_16[((0xc4d18 - 0xc4560) / sizeof(__be64)) - 3];
+ __be64 base_addr_sq_ring[3]; /* Offset 0xc4d18 */
+ /* HW:TSU_SQS_RSPQ_BASE_ADDR_0 -> struct base_addr_sq_rspq [165 bits] */
+ __be64 ingenting_17[((0xc4f68 - 0xc4d18) / sizeof(__be64)) - 3];
+ __be64 base_addr_sq_rspq[3]; /* Offset 0xc4f68 */
+ /* HW:TSU_SQS_RSPQ_TVL_BASE_ADDR_0 -> struct base_addr_sq_tvl [165 bits] */
+ __be64 ingenting_18[((0xc5388 - 0xc4f68) / sizeof(__be64)) - 3];
+ __be64 base_addr_sq_tvl[3]; /* Offset 0xc5388 */
+ /* HW:TSU_CBLD_CQ_BASE_ADDR_SW_0 -> struct base_addr_cq_sw [165 bits] */
+ __be64 ingenting_19[((0xcd7a0 - 0xc5388) / sizeof(__be64)) - 3];
+ __be64 base_addr_cq_sw[3]; /* Offset 0xcd7a0 */
+ /* HW:TSU_CBLD_CQ_BASE_ADDR_HW_0 -> struct base_addr_cq_hw [165 bits] */
+ __be64 ingenting_20[((0xcd7b8 - 0xcd7a0) / sizeof(__be64)) - 3];
+ __be64 base_addr_cq_hw[3]; /* Offset 0xcd7b8 */
+ __be64 ingenting_21[((0xce9f0 - 0xcd7b8) / sizeof(__be64)) - 3];
+}; /* struct psif_csr_be [6770560 bits] */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _PSIF_HW_CSR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_data.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,2022 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PSIF_HW_DATA_H
+#define _PSIF_HW_DATA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "psif_api.h"
+
+#define psif_port_flags psif_event
+#define string_enum_psif_port_flags(data) string_enum_psif_event((enum psif_event)data)
+#include "psif_endian.h"
+#if !defined(__KERNEL__)
+#include "os_header.h"
+#endif
+
+/* Extent of all psif enums */
+enum psif_enum_extent {
+ PSIF_MMU_TRANSLATION_EXTENT = 0x8,
+ PSIF_PAGE_SIZE_EXTENT = 0xf,
+ PSIF_WR_TYPE_EXTENT = 0x8f,
+ PSIF_PORT_EXTENT = 0x2,
+ PSIF_USE_AH_EXTENT = 0x2,
+ PSIF_TSU_QOS_EXTENT = 0x2,
+ PSIF_WC_OPCODE_EXTENT = 0x83,
+ PSIF_WC_STATUS_EXTENT = 0x16,
+ PSIF_TSL_QP_WR_EXTENT = 0x10,
+ PSIF_TABLE_LEVEL_EXTENT = 0x6,
+ IB_OPCODE_EXTENT = 0xca,
+ PSIF_RB_TYPE_EXTENT = 0x7,
+ PSIF_EPS_A_CORE_EXTENT = 0x4,
+ PSIF_QP_STATE_EXTENT = 0x8,
+ PSIF_CMPL_OUTSTANDING_ERROR_EXTENT = 0xa,
+ PSIF_EXPECTED_OP_EXTENT = 0x4,
+ PSIF_MIGRATION_EXTENT = 0x4,
+ PSIF_QP_TRANS_EXTENT = 0x8,
+ PSIF_BOOL_EXTENT = 0x2,
+ PSIF_EOIB_TYPE_EXTENT = 0x4,
+ PSIF_COMM_LIVE_EXTENT = 0x2,
+ PSIF_PATH_MTU_EXTENT = 0x8,
+ PSIF_USE_GRH_EXTENT = 0x2,
+ PSIF_LOOPBACK_EXTENT = 0x2,
+ PSIF_PORT_SPEED_EXTENT = 0x21,
+ PSIF_PCIE_WR_OFFS_EXTENT = 0x1000,
+ PSIF_QP_COMMAND_EXTENT = 0x4,
+ PSIF_SIBS_MBOX_TYPE_EXTENT = 0x2,
+ PSIF_MBOX_TYPE_EXTENT = 0x6,
+ PSIF_DMA_VT_KEY_STATES_EXTENT = 0x4,
+ PSIF_FLASH_IMAGE_TYPE_EXTENT = 0x5,
+ PSIF_EVENT_EXTENT = 0x11,
+ PSIF_TSU_ERROR_TYPES_EXTENT = 0x8c,
+ PSIF_EPS_CORE_ID_EXTENT = 0x5,
+ PSIF_EPSC_LOG_MODE_EXTENT = 0x11,
+ PSIF_EPSC_LOG_LEVEL_EXTENT = 0x8,
+ PSIF_EPSC_PORT_STATE_EXTENT = 0x6,
+ PSIF_EPSC_PATH_MTU_EXTENT = 0x8,
+ PSIF_EPSC_MONITOR_EXTENT = 0x5,
+ PSIF_EPSC_INTERRUPT_SOURCE_EXTENT = 0x15,
+ PSIF_EPSC_INTERRUPT_PRI_EXTENT = 0x4,
+ PSIF_EPSC_ATOMIC_CAP_EXTENT = 0x3,
+ PSIF_EPSC_CSR_STATUS_EXTENT = 0x100,
+ PSIF_EPSC_CSR_OPCODE_EXTENT = 0x4f,
+ PSIF_EPSC_CSR_FLAGS_EXTENT = 0x5,
+ PSIF_VLINK_STATE_EXTENT = 0x11,
+ PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_EXTENT = 0x3,
+ PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_EXTENT = 0x11,
+ PSIF_EPSC_CSR_EPSA_COMMAND_EXTENT = 0x4,
+ PSIF_EPSA_COMMAND_EXTENT = 0xb,
+ PSIF_EPSC_QUERY_OP_EXTENT = 0x4b,
+ PSIF_EPSC_CSR_UPDATE_OPCODE_EXTENT = 0x8,
+ PSIF_EPSC_FLASH_SLOT_EXTENT = 0x6,
+ PSIF_EPSC_UPDATE_SET_EXTENT = 0x5,
+ PSIF_EPSC_CSR_UF_CTRL_OPCODE_EXTENT = 0x9,
+ PSIF_EPSC_VIMMA_CTRL_OPCODE_EXTENT = 0x8,
+ PSIF_EPSC_VIMMA_ADMMODE_EXTENT = 0x2,
+ PSIF_EPSC_CSR_PMA_COUNTERS_ENUM_EXTENT = 0x17,
+ PSIF_EPSC_CSR_ATOMIC_OP_EXTENT = 0x4,
+ PSIF_CQ_STATE_EXTENT = 0x4,
+ PSIF_RSS_HASH_SOURCE_EXTENT = 0x2
+}; /* enum psif_enum_extent [16 bits] */
+
+/* MMU operation modes. */
+enum psif_mmu_translation {
+ MMU_PASS_THROUGH0,
+ MMU_PASS_THROUGH_PAD,
+ MMU_GVA2GPA_MODE,
+ MMU_GVA2GPA_MODE_PAD,
+ MMU_PRETRANSLATED,
+ MMU_PRETRANSLATED_PAD,
+ MMU_EPSA_MODE,
+ MMU_EPSC_MODE
+}; /* enum psif_mmu_translation [ 3 bits] */
+
+/*
+ * Enumeration for the different supported page sizes. XXX: Define the page
+ * sizes
+ */
+enum psif_page_size {
+ PAGE_SIZE_IA32E_4KB = 0,
+ PAGE_SIZE_IA32E_2MB = 0x1,
+ PAGE_SIZE_IA32E_1GB = 0x2,
+ PAGE_SIZE_S64_8KB = 0x8,
+ PAGE_SIZE_S64_64KB = 0x9,
+ PAGE_SIZE_S64_512KB = 0xa,
+ PAGE_SIZE_S64_4MB = 0xb,
+ PAGE_SIZE_S64_32MB = 0xc,
+ PAGE_SIZE_S64_2GB = 0xd,
+ PAGE_SIZE_S64_16GB = 0xe
+}; /* enum psif_page_size [ 4 bits] */
+
+/*
+ * These are the different work request opcodes supported by PSIF.
+ * PSIF_WR_ENTER_SQ_MODE and PSIF_WR_CANCEL_CMD are special opcodes only used
+ * when writing to a special offset of the VCBs. RQS must check that the
+ * PSIF_WR_SEND_EPS and PSIF_WR_SEND_EPS_DR really comes from the EPS. CBU
+ * must report the source of a WR to RQS.
+ */
+enum psif_wr_type {
+ PSIF_WR_SEND,
+ PSIF_WR_SEND_IMM,
+ PSIF_WR_SPECIAL_QP_SEND,
+ PSIF_WR_QP0_SEND_DR_XMIT,
+ PSIF_WR_QP0_SEND_DR_LOOPBACK,
+ PSIF_WR_EPS_SPECIAL_QP_SEND,
+ PSIF_WR_EPS_QP0_SEND_DR_XMIT,
+ PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK,
+ PSIF_WR_RDMA_WR,
+ PSIF_WR_RDMA_WR_IMM,
+ PSIF_WR_RDMA_RD,
+ PSIF_WR_CMP_SWAP,
+ PSIF_WR_FETCH_ADD,
+ PSIF_WR_MASK_CMP_SWAP,
+ PSIF_WR_MASK_FETCH_ADD,
+ PSIF_WR_LSO,
+ PSIF_WR_INVALIDATE_RKEY = 0x80,
+ PSIF_WR_INVALIDATE_LKEY,
+ PSIF_WR_INVALIDATE_BOTH_KEYS,
+ PSIF_WR_INVALIDATE_TLB,
+ PSIF_WR_RESIZE_CQ,
+ PSIF_WR_SET_SRQ_LIM,
+ PSIF_WR_SET_XRCSRQ_LIM,
+ PSIF_WR_REQ_CMPL_NOTIFY,
+ PSIF_WR_CMPL_NOTIFY_RCVD,
+ PSIF_WR_REARM_CMPL_EVENT,
+ PSIF_WR_GENERATE_COMPLETION,
+ PSIF_WR_INVALIDATE_RQ,
+ PSIF_WR_INVALIDATE_CQ,
+ PSIF_WR_INVALIDATE_XRCSRQ,
+ PSIF_WR_INVALIDATE_SGL_CACHE
+}; /* enum psif_wr_type [ 8 bits] */
+
+/* Port number the IB packet is transimitted on. */
+enum psif_port {
+ PORT_1 = 0,
+ PORT_2 = 0x1
+}; /* enum psif_port [ 1 bits] */
+
+/*
+ * Enumeration for using AHA or not. When set, AHA should be used instead of
+ * information from the QP state in appropriate places.
+ */
+enum psif_use_ah {
+ NO_AHA = 0,
+ USE_AHA = 0x1
+}; /* enum psif_use_ah [ 1 bits] */
+
+/*
+ * Indicating if this QP is configured as a high bandwidth or a low latency
+ * QP.
+ */
+enum psif_tsu_qos {
+ QOSL_HIGH_BANDWIDTH = 0,
+ QOSL_LOW_LATENCY = 0x1
+}; /* enum psif_tsu_qos [ 1 bits] */
+
+/*
+ * Completion entry opcode indicating what type of request this completion
+ * entry is completed.
+ */
+enum psif_wc_opcode {
+ PSIF_WC_OPCODE_SEND = 0,
+ PSIF_WC_OPCODE_RDMA_WR = 0x1,
+ PSIF_WC_OPCODE_RDMA_READ = 0x2,
+ PSIF_WC_OPCODE_CMP_SWAP = 0x3,
+ PSIF_WC_OPCODE_FETCH_ADD = 0x4,
+ PSIF_WC_OPCODE_LSO = 0x6,
+ PSIF_WC_OPCODE_MASKED_CMP_SWAP = 0x9,
+ PSIF_WC_OPCODE_MASKED_FETCH_ADD,
+ PSIF_WC_OPCODE_INVALIDATE_RKEY = 0x40,
+ PSIF_WC_OPCODE_INVALIDATE_LKEY,
+ PSIF_WC_OPCODE_INVALIDATE_BOTH_KEYS,
+ PSIF_WC_OPCODE_INVALIDATE_TLB,
+ PSIF_WC_OPCODE_RESIZE_CQ,
+ PSIF_WC_OPCODE_SET_SRQ_LIM,
+ PSIF_WC_OPCODE_SET_XRCSRQ_LIM,
+ PSIF_WC_OPCODE_REQ_CMPL_NOTIFY,
+ PSIF_WC_OPCODE_CMPL_NOTIFY_RCVD,
+ PSIF_WC_OPCODE_REARM_CMPL_EVENT,
+ PSIF_WC_OPCODE_GENERATE_COMPLETION,
+ PSIF_WC_OPCODE_INVALIDATE_RQ,
+ PSIF_WC_OPCODE_INVALIDATE_CQ,
+ PSIF_WC_OPCODE_INVALIDATE_RB,
+ PSIF_WC_OPCODE_INVALIDATE_XRCSRQ,
+ PSIF_WC_OPCODE_INVALIDATE_SGL_CACHE,
+ PSIF_WC_OPCODE_RECEIVE_SEND = 0x80,
+ PSIF_WC_OPCODE_RECEIVE_RDMA_WR_IMM,
+ PSIF_WC_OPCODE_RECEIVE_CONDITIONAL_WR_IMM
+}; /* enum psif_wc_opcode [ 8 bits] */
+
+/* Completion status for this completion. */
+enum psif_wc_status {
+ PSIF_WC_STATUS_SUCCESS,
+ PSIF_WC_STATUS_LOC_LEN_ERR,
+ PSIF_WC_STATUS_LOC_QP_OP_ERR,
+ PSIF_WC_STATUS_LOC_EEC_OP_ERR,
+ PSIF_WC_STATUS_LOC_PROT_ERR,
+ PSIF_WC_STATUS_WR_FLUSH_ERR,
+ PSIF_WC_STATUS_MW_BIND_ERR,
+ PSIF_WC_STATUS_BAD_RESP_ERR,
+ PSIF_WC_STATUS_LOC_ACCESS_ERR,
+ PSIF_WC_STATUS_REM_INV_REQ_ERR,
+ PSIF_WC_STATUS_REM_ACCESS_ERR,
+ PSIF_WC_STATUS_REM_OP_ERR,
+ PSIF_WC_STATUS_RETRY_EXC_ERR,
+ PSIF_WC_STATUS_RNR_RETRY_EXC_ERR,
+ PSIF_WC_STATUS_LOC_RDD_VIOL_ERR,
+ PSIF_WC_STATUS_REM_INV_RD_REQ_ERR,
+ PSIF_WC_STATUS_REM_ABORT_ERR,
+ PSIF_WC_STATUS_INV_EECN_ERR,
+ PSIF_WC_STATUS_INV_EEC_STATE_ERR,
+ PSIF_WC_STATUS_FATAL_ERR,
+ PSIF_WC_STATUS_RESP_TIMEOUT_ERR,
+ PSIF_WC_STATUS_GENERAL_ERR,
+ /* Padding out to required bits allocated */
+ PSIF_WC_STATUS_FIELD_MAX = 0xff
+}; /* enum psif_wc_status [ 8 bits] */
+
+/* TSU Service level required in the QP and WR */
+enum psif_tsl_qp_wr {
+ /* Dataplane traffic separated in 4 TSLs */
+ TSL_DATA,
+ TSL_DATA_1,
+ TSL_DATA_2,
+ TSL_DATA_3,
+ /* TSL for privelidge QP */
+ TSL_PRIV = 0xe,
+ /* Strapped down TSL for testing */
+ TSL_JUNK = 0xf
+}; /* enum psif_tsl_qp_wr [ 4 bits] */
+
+/* MMU table level definition
+ * If page level is not applicable it should be set to PAGE_LEVEL0
+ * Values beyond PAGE_LEVEL4 (5-7) are reserved by HW
+ */
+enum psif_table_level {
+ /* */
+ PAGE_LEVEL0 = 0,
+ PAGE_LEVEL1,
+ PAGE_LEVEL2,
+ PAGE_LEVEL3,
+ /* PAGE_LEVEL4 is SPARC only ? */
+ PAGE_LEVEL4,
+ PAGE_LEVEL_RESERVED
+}; /* enum psif_table_level [ 3 bits] */
+
+
+enum ib_opcode {
+ RC_SEND_First = 0,
+ RC_SEND_Middle = 0x1,
+ RC_SEND_Last = 0x2,
+ RC_SEND_Last_Imm = 0x3,
+ RC_SEND_Only = 0x4,
+ RC_SEND_Only_Imm = 0x5,
+ RC_RDMA_WR_First = 0x6,
+ RC_RDMA_WR_Middle = 0x7,
+ RC_RDMA_WR_Last = 0x8,
+ RC_RDMA_WR_Last_Imm = 0x9,
+ RC_RDMA_WR_Only = 0xa,
+ RC_RDMA_WR_Only_Imm = 0xb,
+ RC_RDMA_RD_Req = 0xc,
+ RC_RDMA_RD_Resp_First = 0xd,
+ RC_RDMA_RD_Resp_Middle = 0xe,
+ RC_RDMA_RD_Resp_Last = 0xf,
+ RC_RDMA_RD_Resp_Only = 0x10,
+ RC_ACK = 0x11,
+ RC_Atomic_ACK = 0x12,
+ RC_CmpSwap = 0x13,
+ RC_FetchAdd = 0x14,
+ RC_Reserved = 0x15,
+ RC_SEND_Last_Invalid = 0x16,
+ RC_SEND_Only_Invalid = 0x17,
+ RC_MaskCmpSwap = 0x18,
+ RC_MaskFetchAdd = 0x19,
+ UC_SEND_First = 0x20,
+ UC_SEND_Middle = 0x21,
+ UC_SEND_Last = 0x22,
+ UC_SEND_Last_Imm = 0x23,
+ UC_SEND_Only = 0x24,
+ UC_SEND_Only_Imm = 0x25,
+ UC_RDMA_WR_First = 0x26,
+ UC_RDMA_WR_Middle = 0x27,
+ UC_RDMA_WR_Last = 0x28,
+ UC_RDMA_WR_Last_Imm = 0x29,
+ UC_RDMA_WR_Only = 0x2a,
+ UC_RDMA_WR_Only_Imm = 0x2b,
+ RD_SEND_First = 0x40,
+ RD_SEND_Middle = 0x41,
+ RD_SEND_Last = 0x42,
+ RD_SEND_Last_Imm = 0x43,
+ RD_SEND_Only = 0x44,
+ RD_SEND_Only_Imm = 0x45,
+ RD_RDMA_WR_First = 0x46,
+ RD_RDMA_WR_Middle = 0x47,
+ RD_RDMA_WR_Last = 0x48,
+ RD_RDMA_WR_Last_Imm = 0x49,
+ RD_RDMA_WR_Only = 0x4a,
+ RD_RDMA_WR_Only_Imm = 0x4b,
+ RD_RDMA_RD_Req = 0x4c,
+ RD_RDMA_RD_Resp_First = 0x4d,
+ RD_RDMA_RD_Resp_Middle = 0x4e,
+ RD_RDMA_RD_Resp_Last = 0x4f,
+ RD_RDMA_RD_Resp_Only = 0x50,
+ RD_ACK = 0x51,
+ RD_Atomic_ACK = 0x52,
+ RD_CmpSwap = 0x53,
+ RD_FetchAdd = 0x54,
+ RD_RESYNC = 0x55,
+ UD_SEND_Only = 0x64,
+ UD_SEND_Only_Imm = 0x65,
+ CNP = 0x80,
+ XRC_SEND_First = 0xa0,
+ XRC_SEND_Middle = 0xa1,
+ XRC_SEND_Last = 0xa2,
+ XRC_SEND_Last_Imm = 0xa3,
+ XRC_SEND_Only = 0xa4,
+ XRC_SEND_Only_Imm = 0xa5,
+ XRC_RDMA_WR_First = 0xa6,
+ XRC_RDMA_WR_Middle = 0xa7,
+ XRC_RDMA_WR_Last = 0xa8,
+ XRC_RDMA_WR_Last_Imm = 0xa9,
+ XRC_RDMA_WR_Only = 0xaa,
+ XRC_RDMA_WR_Only_Imm = 0xab,
+ XRC_RDMA_RD_Req = 0xac,
+ XRC_RDMA_RD_Resp_First = 0xad,
+ XRC_RDMA_RD_Resp_Middle = 0xae,
+ XRC_RDMA_RD_Resp_Last = 0xaf,
+ XRC_RDMA_RD_Resp_Only = 0xb0,
+ XRC_ACK = 0xb1,
+ XRC_Atomic_ACK = 0xb2,
+ XRC_CmpSwap = 0xb3,
+ XRC_FetchAdd = 0xb4,
+ XRC_Reserved = 0xb5,
+ XRC_SEND_Last_Invalid = 0xb6,
+ XRC_SEND_Only_Invalid = 0xb7,
+ XRC_MaskCmpSwap = 0xb8,
+ XRC_MaskFetchAdd = 0xb9,
+ MANSP1_INVALID = 0xc0,
+ MANSP1_HOST_READ = 0xc1,
+ MANSP1_HOST_WRITE = 0xc2,
+ MANSP1_HOST_READ_NO_DMAVT = 0xc3,
+ MANSP1_HOST_WRITE_NO_DMAVT = 0xc4,
+ MANSP1_INTERNAL_TYPE = 0xc5,
+ MANSP1_INTERNAL_TYPE_MMU_BYPASS = 0xc6,
+ MANSP1_HOST_CMP_SWAP = 0xc7,
+ MANSP1_DR_LOOPBACK = 0xc8,
+ MANSP1_ARP_LOOPBACK = 0xc9
+}; /* enum ib_opcode [ 8 bits] */
+
+/*
+ * This is a ring buffer type defining the type of transaction this
+ * represents.
+ */
+enum psif_rb_type {
+ PSIF_RB_TYPE_INVALID,
+ PSIF_RB_TYPE_DM_PUT,
+ PSIF_RB_TYPE_DM_GET_RESP,
+ PSIF_RB_TYPE_RCV_PROXY_COMPLETION,
+ PSIF_RB_TYPE_RCV_PROXY_COMPLETION_AND_DATA,
+ PSIF_RB_TYPE_SEND_PROXY_COMPLETION,
+ PSIF_RB_TYPE_SEND_COMPLETION
+}; /* enum psif_rb_type [ 3 bits] */
+
+/*
+ * Core number for EPS-A.1 PSIF_EPS_A_1 PSIF_EPS_A_2 PSIF_EPS_A_3
+ * PSIF_EPS_A_4
+ */
+enum psif_eps_a_core {
+ PSIF_EPS_A_1,
+ PSIF_EPS_A_2,
+ PSIF_EPS_A_3,
+ PSIF_EPS_A_4
+}; /* enum psif_eps_a_core [ 2 bits] */
+
+/* This is the state this QP is in. */
+enum psif_qp_state {
+ PSIF_QP_STATE_RESET = 0,
+ PSIF_QP_STATE_INIT = 0x1,
+ PSIF_QP_STATE_RTR = 0x2,
+ PSIF_QP_STATE_RTS = 0x3,
+ PSIF_QP_STATE_SQERR = 0x5,
+ PSIF_QP_STATE_ERROR = 0x6,
+ PSIF_QP_STATE_INVALID = 0x7
+}; /* enum psif_qp_state [ 3 bits] */
+
+/*
+ * CMPL_NO_ERROR CMPL_RQS_INVALID_REQUEST_ERR CMPL_RQS_QP_IN_WRONG_STATE_ERR
+ * CMPL_RQS_MAX_OUTSTANDING_REACHED_ERR CMPL_RQS_REQUEST_FENCED_ERR
+ * CMPL_RQS_CMD_FROM_EPS_ERR CMPL_DMA_SGL_RD_ERR CMPL_DMA_PYLD_RD_ERR
+ * CMPL_DMA_SGL_LENGTH_ERR CMPL_DMA_LKEY_ERR
+ */
+enum psif_cmpl_outstanding_error {
+ CMPL_NO_ERROR,
+ CMPL_RQS_INVALID_REQUEST_ERR,
+ CMPL_RQS_QP_IN_WRONG_STATE_ERR,
+ CMPL_RQS_MAX_OUTSTANDING_REACHED_ERR,
+ CMPL_RQS_REQUEST_FENCED_ERR,
+ CMPL_RQS_CMD_FROM_EPS_ERR,
+ CMPL_DMA_SGL_RD_ERR,
+ CMPL_DMA_PYLD_RD_ERR,
+ CMPL_DMA_SGL_LENGTH_ERR,
+ CMPL_DMA_LKEY_ERR
+}; /* enum psif_cmpl_outstanding_error [ 4 bits] */
+
+/*
+ * 2 bits (next_opcode) 0x0: No operation in progress 0x1: Expect SEND middle
+ * or last 0x2: Expect RDMA_WR middle or last 0x3: Expect DM_PUT middle or
+ * last
+ */
+enum psif_expected_op {
+ NO_OPERATION_IN_PROGRESS = 0,
+ EXPECT_SEND_MIDDLE_LAST = 0x1,
+ EXPECT_RDMA_WR_MIDDLE_LAST = 0x2,
+ EXPECT_DM_PUT_MIDDLE_LAST = 0x3
+}; /* enum psif_expected_op [ 2 bits] */
+
+/*
+ * Migration state (migrated, re-arm and armed). XXX: Assign values to the
+ * states.
+ */
+enum psif_migration {
+ APM_OFF,
+ APM_MIGRATED,
+ APM_REARM,
+ APM_ARMED
+}; /* enum psif_migration [ 2 bits] */
+
+/*
+ * 3 bits (transport) 0x0: RC - Reliable connection. 0x1: UC - Unreliable
+ * connection. 0x2: RD - Reliable datagram - not supported. 0x3: UD -
+ * Unreliable datagram. 0x4: RSVD1 0x5: XRC - Extended reliable connection.
+ * 0x6: MANSP1 - manufacturer specific opcodes. 0x7: MANSP2 - manufacturer
+ * specific opcodes.
+ */
+enum psif_qp_trans {
+ PSIF_QP_TRANSPORT_RC = 0,
+ PSIF_QP_TRANSPORT_UC = 0x1,
+ PSIF_QP_TRANSPORT_RD = 0x2,
+ PSIF_QP_TRANSPORT_UD = 0x3,
+ PSIF_QP_TRANSPORT_RSVD1 = 0x4,
+ PSIF_QP_TRANSPORT_XRC = 0x5,
+ PSIF_QP_TRANSPORT_MANSP1 = 0x6,
+ PSIF_QP_TRANSPORT_MANSP2 = 0x7
+}; /* enum psif_qp_trans [ 3 bits] */
+
+
+enum psif_bool {
+ FALSE = 0,
+ TRUE = 0x1
+}; /* enum psif_bool [ 1 bits] */
+
+/*
+ * EoIB types enumerated type having these enumerations: EOIB_FULL,
+ * EOIB_PARTIAL, EOIB_QKEY_ONLY, EOIB_NONE.
+ */
+enum psif_eoib_type {
+ EOIB_FULL,
+ EOIB_PARTIAL,
+ EOIB_QKEY_ONLY,
+ EOIB_NONE
+}; /* enum psif_eoib_type [ 2 bits] */
+
+/*
+ * Communication established state. This gets set when a packet is received
+ * error free when in RTR state.
+ */
+enum psif_comm_live {
+ NO_COMM_ESTABLISHED = 0,
+ COMM_ESTABLISHED = 0x1
+}; /* enum psif_comm_live [ 1 bits] */
+
+/* Definitions for the different supported MTU sizes. */
+enum psif_path_mtu {
+ MTU_INVALID = 0,
+ MTU_256B = 0x1,
+ MTU_512B = 0x2,
+ MTU_1024B = 0x3,
+ MTU_2048B = 0x4,
+ MTU_4096B = 0x5,
+ MTU_10240B = 0x6,
+ MTU_XXX = 0x7
+}; /* enum psif_path_mtu [ 3 bits] */
+
+/* Enumeration for using GRH or not. When set GRH should be used. */
+enum psif_use_grh {
+ NO_GRH = 0,
+ USE_GRH = 0x1
+}; /* enum psif_use_grh [ 1 bits] */
+
+/* Enumeration for loopback indication NO_LOOPBACK = 0 LOOPBACK = 1. */
+enum psif_loopback {
+ NO_LOOPBACK = 0,
+ LOOPBACK = 0x1
+}; /* enum psif_loopback [ 1 bits] */
+
+/*
+ * Should match definitions in ib_verbs.h
+ */
+enum psif_port_speed {
+ PSIF_SPEED_SDR = 0x1,
+ PSIF_SPEED_DDR = 0x2,
+ PSIF_SPEED_QDR = 0x4,
+ PSIF_SPEED_FDR10 = 0x8,
+ PSIF_SPEED_FDR = 0x10,
+ PSIF_SPEED_EDR = 0x20,
+ /* Padding out to required bits allocated */
+ PSIF_PORT_SPEED_FIELD_MAX = 0xff
+}; /* enum psif_port_speed [ 8 bits] */
+
+/* Depricated data type... */
+enum psif_pcie_wr_offs {
+ WR_CB_START_OFFS = 0,
+ WR_CB_LAST_OFFS = 0x140,
+ WR_SQS_DOORBELL_OFFS = 0xfc0,
+ WR_CB_CLEAR_OFFS = 0xff8,
+ WR_MAX_BAR_OFFS = 0xfff
+}; /* enum psif_pcie_wr_offs [12 bits] */
+
+/* Commands used for modify/query QP. */
+enum psif_qp_command {
+ QP_CMD_INVALID = 0,
+ QP_CMD_MODIFY = 0x1,
+ QP_CMD_QUERY = 0x2,
+ QP_CMD_CHECK_TIMEOUT = 0x3
+}; /* enum psif_qp_command [ 2 bits] */
+
+
+enum psif_sibs_mbox_type {
+ SIBS_MBOX_EPSC,
+ SIBS_MBOX_EPS_MAX,
+ /* Padding out to required bits allocated */
+ PSIF_SIBS_MBOX_TYPE_FIELD_MAX = 0xff
+}; /* enum psif_sibs_mbox_type [ 8 bits] */
+
+
+enum psif_mbox_type {
+ MBOX_EPSA0,
+ MBOX_EPSA1,
+ MBOX_EPSA2,
+ MBOX_EPSA3,
+ MBOX_EPSC,
+ MBOX_EPS_MAX,
+ /* Padding out to required bits allocated */
+ PSIF_MBOX_TYPE_FIELD_MAX = 0xff
+}; /* enum psif_mbox_type [ 8 bits] */
+
+/*
+ * DMA Validation Key states. The valid states are: PSIF_DMA_KEY_INVALID=0
+ * PSIF_DMA_KEY_FREE = 1 PSIF_DMA_KEY_VALID = 2 PSIF_DMA_KEY_MMU_VALID
+ */
+enum psif_dma_vt_key_states {
+ PSIF_DMA_KEY_INVALID = 0,
+ PSIF_DMA_KEY_FREE = 0x1,
+ PSIF_DMA_KEY_VALID = 0x2,
+ PSIF_DMA_KEY_MMU_VALID = 0x3
+}; /* enum psif_dma_vt_key_states [ 2 bits] */
+
+/**
+ * Flash image types. More comming...
+ */
+enum psif_flash_image_type {
+ PSIF_IMAGE_INVALID = 0,
+ PSIF_IMAGE_BOOT_LOADER = 0x1,
+ PSIF_IMAGE_EPS_C_APPLICATION = 0x2,
+ PSIF_IMAGE_EPS_A_APPLICATION = 0x3,
+ PSIF_IMAGE_DIAGNOSTICS = 0x4,
+ /* Padding out to required bits allocated */
+ PSIF_FLASH_IMAGE_TYPE_FIELD_MAX = 0x7fffffff
+}; /* enum psif_flash_image_type [32 bits] */
+
+/** \brief SW EQ event type
+ * \details
+ * Software events use `eq_entry::port_flags` for the event type. As this is
+ * limited to 4 bits the special value `PSIF_EVENT_EXTENSION` is used to
+ * indicate that the actual event type is to be found in
+ * `eq_entry::extension_type`. This is done for all enum values larger than
+ * 4 bits.
+ *
+ * \par Width
+ * 32 bit
+ * \par Used in
+ * struct psif_eq_entry
+ * \par Restrictions
+ * none (all UF)
+ * \par Classification
+ * driver
+ */
+enum psif_event {
+ /** Event without a reason... */
+ PSIF_EVENT_NO_CHANGE = 0,
+ /** GID table have been updated */
+ PSIF_EVENT_SGID_TABLE_CHANGED,
+ /** PKEY table have been updated by the SM */
+ PSIF_EVENT_PKEY_TABLE_CHANGED,
+ /** SM lid have been updated by master SM */
+ PSIF_EVENT_MASTER_SM_LID_CHANGED,
+ /** The SMs SL have changed */
+ PSIF_EVENT_MASTER_SM_SL_CHANGED,
+ /** */
+ PSIF_EVENT_SUBNET_TIMEOUT_CHANGED,
+ /** */
+ PSIF_EVENT_IS_SM_DISABLED_CHANGED,
+ /** New master SM - client must reregister */
+ PSIF_EVENT_CLIENT_REREGISTER,
+ /** vHCA have been assigned a new LID */
+ PSIF_EVENT_LID_TABLE_CHANGED,
+ /** */
+ PSIF_EVENT_EPSC_COMPLETION,
+ /** Mailbox request handled (only if EPSC_FL_NOTIFY was set in the request) */
+ PSIF_EVENT_MAILBOX,
+ /** The real event type value is found in `eq_entry::extension_type` */
+ PSIF_EVENT_EXTENSION,
+ /** Host should retrieve the EPS log for persistent storage */
+ PSIF_EVENT_LOG,
+ /** */
+ PSIF_EVENT_PORT_ACTIVE,
+ /** */
+ PSIF_EVENT_PORT_ERR,
+ /** Event queue full (replaces the actual event) */
+ PSIF_EVENT_QUEUE_FULL,
+ /** FW entered degraded mode */
+ PSIF_EVENT_DEGRADED_MODE,
+ /* Padding out to required bits allocated */
+ PSIF_EVENT_FIELD_MAX = 0x7fffffff
+}; /* enum psif_event [32 bits] */
+
+/*
+ * Enumerations of error types. The following error types are defined for the
+ * TSU: TSU_NO_ERROR = 8'h0 TSU_IBPR_ICRC_ERR TSU_IBPR_INVALID_PKEY_ERR
+ * TSU_IBPR_INVALID_QP_ERR TSU_IBPR_VSWITCH_UF_ERR
+ * TSU_IBPR_UNDEFINED_OPCODE_ERR TSU_IBPR_MCAST_NO_GRH_ERR
+ * TSU_IBPR_MCAST_NO_TARGET_ERR TSU_IBPR_INVALID_DGID_ERR TSU_IBPR_BADPKT_ERR
+ * TSU_RCV_QP_INVALID_ERR TSU_RCV_HDR_BTH_TVER_ERR TSU_RCV_HDR_BTH_QP_ERR
+ * TSU_RCV_HDR_GRH_ERR TSU_RCV_HDR_PKEY_ERR TSU_RCV_HDR_QKEY_ERR
+ * TSU_RCV_HDR_LID_ERR TSU_RCV_HDR_MAD_ERR TSU_RCV_EOIB_MCAST_ERR
+ * TSU_RCV_EOIB_BCAST_ERR TSU_RCV_EOIB_UCAST_ERR TSU_RCV_EOIB_FRAGMENT_ERR
+ * TSU_RCV_EOIB_RUNTS_ERR TSU_RCV_EOIB_OUTER_VLAN_ERR
+ * TSU_RCV_EOIB_VLAN_TAG_ERR TSU_RCV_EOIB_VID_ERR TSU_RCV_MCAST_DUP_ERR
+ * TSU_RCV_ECC_ERR TSU_DSCR_RESPONDER_RC_PSN_ERR
+ * TSU_DSCR_RESPONDER_RC_DUPLICATE TSU_DSCR_RESPONDER_RC_OPCODE_SEQ_ERR
+ * TSU_DSCR_RESPONDER_RC_OPCODE_VAL_ERR TSU_DSCR_RESPONDER_RC_OPCODE_LEN_ERR
+ * TSU_DSCR_RESPONDER_RC_DMALEN_ERR TSU_DSCR_RESPONDER_XRC_PSN_ERR
+ * TSU_DSCR_RESPONDER_XRC_DUPLICATE TSU_DSCR_RESPONDER_XRC_OPCODE_SEQ_ERR
+ * TSU_DSCR_RESPONDER_XRC_OPCODE_VAL_ERR
+ * TSU_DSCR_RESPONDER_XRC_OPCODE_LEN_ERR TSU_DSCR_RESPONDER_XRC_DMALEN_ERR
+ * TSU_DSCR_RESPONDER_UC_PSN_ERR TSU_DSCR_RESPONDER_UC_OPCODE_SEQ_ERR
+ * TSU_DSCR_RESPONDER_UC_OPCODE_VAL_ERR TSU_DSCR_RESPONDER_UC_OPCODE_LEN_ERR
+ * TSU_DSCR_RESPONDER_UC_DMALEN_ERR TSU_DSCR_RESPONDER_UD_OPCODE_LEN_ERR
+ * TSU_DSCR_RESPONDER_DUPLICATE_WITH_ERR
+ * TSU_DSCR_QP_CAP_MASKED_ATOMIC_ENABLE_ERR
+ * TSU_DSCR_QP_CAP_RDMA_RD_ENABLE_ERR TSU_DSCR_QP_CAP_RDMA_WR_ENABLE_ERR
+ * TSU_DSCR_QP_CAP_ATOMIC_ENABLE_ERR TSU_DSCR_XRC_DOMAIN_VIOLATION_ERR
+ * TSU_DSCR_XRCETH_ERR TSU_DSCR_RQ_INVALID_ERR TSU_DSCR_RQ_PD_CHECK_ERR
+ * TSU_DSCR_RQ_EMPTY_ERR TSU_DSCR_RQ_IN_ERROR_ERR
+ * TSU_DSCR_TRANSLATION_TYPE_ERR TSU_DSCR_RQ_DESCRIPTOR_INCONSISTENT_ERR
+ * TSU_DSCR_PCIE_ERR TSU_DSCR_ECC_ERR TSU_RQH_PCIE_ERR TSU_RQH_SGL_LKEY_ERR
+ * TSU_RQH_NOT_ENOUGH_RQ_SPACE_ERR TSU_RQH_ECC_ERR TSU_VAL_DUPLICATE_WITH_ERR
+ * TSU_VAL_RKEY_VLD_ERR TSU_VAL_RKEY_ADDR_RANGE_ERR TSU_VAL_RKEY_ACCESS_ERR
+ * TSU_VAL_RKEY_PD_ERR TSU_VAL_RKEY_RANGE_ERR TSU_VAL_LKEY_VLD_ERR
+ * TSU_VAL_LKEY_ADDR_RANGE_ERR TSU_VAL_LKEY_ACCESS_ERR TSU_VAL_LKEY_PD_ERR
+ * TSU_VAL_LKEY_RANGE_ERR TSU_VAL_TRANSLATION_TYPE_ERR TSU_VAL_PCIE_ERR
+ * TSU_VAL_ECC_ERR TSU_MMU_DUPLICATE_WITH_ERR TSU_MMU_PTW_ERR TSU_MMU_UF_ERR
+ * TSU_MMU_AC_ERR TSU_MMU_ECC_ERR TSU_CBLD_CQ_INVALID_ERR
+ * TSU_CBLD_CQ_FULL_ERR TSU_CBLD_CQ_IS_PROXY_ERR
+ * TSU_CBLD_TRANSLATION_TYPE_ERR TSU_CBLD_CQ_DESCRIPTOR_INCONSISTENT_ERR
+ * TSU_CBLD_ECC_ERR TSU_CBLD_QP_ERR TSU_RQS_CHECKSUM_ERR TSU_RQS_SEQNUM_ERR
+ * TSU_RQS_INVALID_REQUEST_ERR TSU_RQS_QP_IN_WRONG_STATE_ERR
+ * TSU_RQS_STOP_TIMER_ERR TSU_RQS_CMD_FROM_EPS_ERR TSU_RQS_SQ_FLUSH_ERR
+ * TSU_RQS_SMP_NOT_AUTH_ERR TSU_RQS_REQUEST_FENCED_ERR
+ * TSU_RQS_MAX_OUTSTANDING_REACHED_ERR TSU_RQS_ECC_ERR
+ * TSU_RQS_EOIB_QKEY_VIOLATION TSU_RQS_IPOIB_QKEY_VIOLATION
+ * TSU_RQS_EOIB_MODE_VIOLATION TSU_RQS_MISCONFIGURED_QP
+ * TSU_RQS_PORT_AUTH_VIOLATION TSU_DMA_SGL_RD_ERR TSU_DMA_PYLD_RD_ERR
+ * TSU_DMA_SGL_LENGTH_ERR TSU_DMA_LKEY_ERR TSU_DMA_RKEY_ERR
+ * TSU_DMA_LSO_PKTLEN_ERR TSU_DMA_LSO_ILLEGAL_CLASSIFICATION_ERR
+ * TSU_DMA_PCIE_ERR TSU_DMA_ECC_ERR TSU_CMPL_PCIE_ERR TSU_CMPL_ECC_ERR
+ * TSU_CMPL_REQUESTER_PSN_ERR TSU_CMPL_REQUESTER_SYNDROME_ERR
+ * TSU_CMPL_REQUESTER_OUTSTANDING_MATCH_ERR TSU_CMPL_REQUESTER_LEN_ERR
+ * TSU_CMPL_REQUESTER_UNEXP_OPCODE_ERR TSU_CMPL_REQUESTER_DUPLICATE
+ * TSU_CMPL_RC_IN_ERROR_ERR TSU_CMPL_NAK_RNR_ERR TSU_CMPL_NAK_SEQUENCE_ERR
+ * TSU_CMPL_NAK_INVALID_REQUEST_ERR TSU_CMPL_NAK_REMOTE_ACCESS_ERR
+ * TSU_CMPL_NAK_REMOTE_OPS_ERR TSU_CMPL_NAK_INVALID_RD_REQUEST_ERR
+ * TSU_CMPL_TIMEOUT_ERR TSU_CMPL_IMPLIED_NAK TSU_CMPL_GHOST_RESP_ERR
+ */
+enum psif_tsu_error_types {
+ TSU_NO_ERROR = 0,
+ TSU_IBPR_ICRC_ERR,
+ TSU_IBPR_INVALID_PKEY_ERR,
+ TSU_IBPR_INVALID_QP_ERR,
+ TSU_IBPR_VSWITCH_UF_ERR,
+ TSU_IBPR_PKTLEN_ERR,
+ TSU_IBPR_UNDEFINED_OPCODE_ERR,
+ TSU_IBPR_MCAST_NO_GRH_ERR,
+ TSU_IBPR_MCAST_NO_TARGET_ERR,
+ TSU_IBPR_INVALID_DGID_ERR,
+ TSU_IBPR_BADPKT_ERR,
+ TSU_RCV_QP_INVALID_ERR,
+ TSU_RCV_HDR_BTH_TVER_ERR,
+ TSU_RCV_HDR_BTH_QP_ERR,
+ TSU_RCV_HDR_GRH_ERR,
+ TSU_RCV_HDR_PKEY_ERR,
+ TSU_RCV_HDR_QKEY_ERR,
+ TSU_RCV_HDR_LID_ERR,
+ TSU_RCV_HDR_MAD_ERR,
+ TSU_RCV_EOIB_MCAST_ERR,
+ TSU_RCV_EOIB_BCAST_ERR,
+ TSU_RCV_EOIB_UCAST_ERR,
+ TSU_RCV_EOIB_TCP_PORT_VIOLATION_ERR,
+ TSU_RCV_EOIB_RUNTS_ERR,
+ TSU_RCV_EOIB_OUTER_VLAN_ERR,
+ TSU_RCV_EOIB_VLAN_TAG_ERR,
+ TSU_RCV_EOIB_VID_ERR,
+ TSU_RCV_IPOIB_TCP_PORT_VIOLATION_ERR,
+ TSU_RCV_MCAST_DUP_ERR,
+ TSU_RCV_ECC_ERR,
+ TSU_DSCR_RESPONDER_RC_PSN_ERR,
+ TSU_DSCR_RESPONDER_RC_DUPLICATE,
+ TSU_DSCR_RESPONDER_RC_OPCODE_SEQ_ERR,
+ TSU_DSCR_RESPONDER_RC_OPCODE_VAL_ERR,
+ TSU_DSCR_RESPONDER_RC_OPCODE_LEN_ERR,
+ TSU_DSCR_RESPONDER_RC_DMALEN_ERR,
+ TSU_DSCR_RESPONDER_XRC_PSN_ERR,
+ TSU_DSCR_RESPONDER_XRC_DUPLICATE,
+ TSU_DSCR_RESPONDER_XRC_OPCODE_SEQ_ERR,
+ TSU_DSCR_RESPONDER_XRC_OPCODE_VAL_ERR,
+ TSU_DSCR_RESPONDER_XRC_OPCODE_LEN_ERR,
+ TSU_DSCR_RESPONDER_XRC_DMALEN_ERR,
+ TSU_DSCR_RESPONDER_UC_PSN_ERR,
+ TSU_DSCR_RESPONDER_UC_OPCODE_SEQ_ERR,
+ TSU_DSCR_RESPONDER_UC_OPCODE_VAL_ERR,
+ TSU_DSCR_RESPONDER_UC_OPCODE_LEN_ERR,
+ TSU_DSCR_RESPONDER_UC_DMALEN_ERR,
+ TSU_DSCR_RESPONDER_UD_OPCODE_LEN_ERR,
+ TSU_DSCR_RESPONDER_DUPLICATE_WITH_ERR,
+ TSU_DSCR_QP_CAP_MASKED_ATOMIC_ENABLE_ERR,
+ TSU_DSCR_QP_CAP_RDMA_RD_ENABLE_ERR,
+ TSU_DSCR_QP_CAP_RDMA_WR_ENABLE_ERR,
+ TSU_DSCR_QP_CAP_ATOMIC_ENABLE_ERR,
+ TSU_DSCR_XRC_DOMAIN_VIOLATION_ERR,
+ TSU_DSCR_XRCETH_ERR,
+ TSU_DSCR_RQ_INVALID_ERR,
+ TSU_DSCR_RQ_PD_CHECK_ERR,
+ TSU_DSCR_RQ_EMPTY_ERR,
+ TSU_DSCR_RQ_IN_ERROR_ERR,
+ TSU_DSCR_TRANSLATION_TYPE_ERR,
+ TSU_DSCR_RQ_DESCRIPTOR_INCONSISTENT_ERR,
+ TSU_DSCR_MISALIGNED_ATOMIC_ERR,
+ TSU_DSCR_PCIE_ERR,
+ TSU_DSCR_ECC_ERR,
+ TSU_RQH_PCIE_ERR,
+ TSU_RQH_SGL_LKEY_ERR,
+ TSU_RQH_NOT_ENOUGH_RQ_SPACE_ERR,
+ TSU_RQH_ECC_ERR,
+ TSU_VAL_DUPLICATE_WITH_ERR,
+ TSU_VAL_RKEY_VLD_ERR,
+ TSU_VAL_RKEY_ADDR_RANGE_ERR,
+ TSU_VAL_RKEY_ACCESS_ERR,
+ TSU_VAL_RKEY_PD_ERR,
+ TSU_VAL_RKEY_RANGE_ERR,
+ TSU_VAL_LKEY_VLD_ERR,
+ TSU_VAL_LKEY_ADDR_RANGE_ERR,
+ TSU_VAL_LKEY_ACCESS_ERR,
+ TSU_VAL_LKEY_PD_ERR,
+ TSU_VAL_LKEY_RANGE_ERR,
+ TSU_VAL_TRANSLATION_TYPE_ERR,
+ TSU_VAL_PCIE_ERR,
+ TSU_VAL_ECC_ERR,
+ TSU_MMU_DUPLICATE_WITH_ERR,
+ TSU_MMU_PTW_ERR,
+ TSU_MMU_UF_ERR,
+ TSU_MMU_AC_ERR,
+ TSU_MMU_ECC_ERR,
+ TSU_CBLD_CQ_INVALID_ERR,
+ TSU_CBLD_CQ_FULL_ERR,
+ TSU_CBLD_CQ_ALREADY_IN_ERR,
+ TSU_CBLD_CQ_IS_PROXY_ERR,
+ TSU_CBLD_TRANSLATION_TYPE_ERR,
+ TSU_CBLD_CQ_DESCRIPTOR_INCONSISTENT_ERR,
+ TSU_CBLD_ECC_ERR,
+ TSU_CBLD_PCIE_ERR,
+ TSU_CBLD_QP_ERR,
+ TSU_RQS_CHECKSUM_ERR,
+ TSU_RQS_SEQNUM_ERR,
+ TSU_RQS_INVALID_REQUEST_ERR,
+ TSU_RQS_QP_IN_WRONG_STATE_ERR,
+ TSU_RQS_STOP_TIMER_ERR,
+ TSU_RQS_CMD_FROM_EPS_ERR,
+ TSU_RQS_SQ_FLUSH_ERR,
+ TSU_RQS_SMP_NOT_AUTH_ERR,
+ TSU_RQS_REQUEST_FENCED_ERR,
+ TSU_RQS_MAX_OUTSTANDING_REACHED_ERR,
+ TSU_RQS_ECC_ERR,
+ TSU_RQS_EOIB_QKEY_VIOLATION,
+ TSU_RQS_IPOIB_QKEY_VIOLATION,
+ TSU_RQS_EOIB_MODE_VIOLATION,
+ TSU_RQS_MISCONFIGURED_QP,
+ TSU_RQS_PORT_AUTH_VIOLATION,
+ TSU_DMA_SGL_RD_ERR,
+ TSU_DMA_REQ_PYLD_RD_ERR,
+ TSU_DMA_RESP_PYLD_RD_ERR,
+ TSU_DMA_SGL_LENGTH_ERR,
+ TSU_DMA_LKEY_ERR,
+ TSU_DMA_RKEY_ERR,
+ TSU_DMA_LSO_PKTLEN_ERR,
+ TSU_DMA_LSO_ILLEGAL_CLASSIFICATION_ERR,
+ TSU_DMA_PCIE_ERR,
+ TSU_DMA_ECC_ERR,
+ TSU_CMPL_PCIE_ERR,
+ TSU_CMPL_ECC_ERR,
+ TSU_CMPL_REQUESTER_PSN_ERR,
+ TSU_CMPL_REQUESTER_SYNDROME_ERR,
+ TSU_CMPL_REQUESTER_OUTSTANDING_MATCH_ERR,
+ TSU_CMPL_REQUESTER_LEN_ERR,
+ TSU_CMPL_REQUESTER_UNEXP_OPCODE_ERR,
+ TSU_CMPL_REQUESTER_DUPLICATE,
+ TSU_CMPL_RC_IN_ERROR_ERR,
+ TSU_CMPL_NAK_RNR_ERR,
+ TSU_CMPL_NAK_SEQUENCE_ERR,
+ TSU_CMPL_NAK_INVALID_REQUEST_ERR,
+ TSU_CMPL_NAK_REMOTE_ACCESS_ERR,
+ TSU_CMPL_NAK_REMOTE_OPS_ERR,
+ TSU_CMPL_NAK_INVALID_RD_REQUEST_ERR,
+ TSU_CMPL_TIMEOUT_ERR,
+ TSU_CMPL_IMPLIED_NAK,
+ TSU_CMPL_GHOST_RESP_ERR
+}; /* enum psif_tsu_error_types [ 8 bits] */
+
+/*
+ * Here are the different EPS core IDs: PSIF_EVENT_EPS_A_1 PSIF_EVENT_EPS_A_2
+ * PSIF_EVENT_EPS_A_3 PSIF_EVENT_EPS_A_4 PSIF_EVENT_EPS_C
+ */
+enum psif_eps_core_id {
+ PSIF_EVENT_CORE_EPS_A_1,
+ PSIF_EVENT_CORE_EPS_A_2,
+ PSIF_EVENT_CORE_EPS_A_3,
+ PSIF_EVENT_CORE_EPS_A_4,
+ PSIF_EVENT_CORE_EPS_C,
+ /* Padding out to required bits allocated */
+ PSIF_EPS_CORE_ID_FIELD_MAX = 0xf
+}; /* enum psif_eps_core_id [ 4 bits] */
+
+
+enum psif_epsc_log_mode {
+/* Logging completely disabled */
+
+ EPSC_LOG_MODE_OFF = 0,
+/* See epsfw/src/include/logging.h */
+
+ EPSC_LOG_MODE_SCAT = 0x1,
+ EPSC_LOG_MODE_MALLOC = 0x2,
+ EPSC_LOG_MODE_LOCAL = 0x3,
+/* Redirect logging to host (dma) */
+
+ EPSC_LOG_MODE_HOST = 0x4,
+/* Save the set log mode in the flash */
+
+ EPSC_LOG_MODE_SAVE = 0x10,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_LOG_MODE_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_log_mode [32 bits] */
+
+/**
+ * EPSC_LOG_CTRL
+ */
+enum psif_epsc_log_level {
+ EPS_LOG_OFF = 0,
+ EPS_LOG_FATAL = 0x1,
+ EPS_LOG_ERROR = 0x2,
+ EPS_LOG_WARN = 0x3,
+ EPS_LOG_INFO = 0x4,
+ EPS_LOG_DEBUG = 0x5,
+ EPS_LOG_TRACE = 0x6,
+ EPS_LOG_ALL = 0x7,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_LOG_LEVEL_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_log_level [32 bits] */
+
+/**
+ * \brief Port state
+ * \details
+ * This enum specifies the state of a UF port's port state machine. It
+ * is used to either force a new state or to report the current state
+ * (via \ref EPSC_QUERY_PORT_1 and \ref EPSC_QUERY_PORT_2).
+ *
+ * \par Width
+ * 32 bit
+ * \par Used in
+ * psif_epsc_port_attr_t
+ * \par Classification
+ * driver, internal
+ *
+ * \todo
+ * The externally provided version of the documentation should probably
+ * not contain the information about forcing the state as this is only
+ * for FW.
+ */
+enum psif_epsc_port_state {
+ /** No change */
+ EPSC_PORT_NOP = 0,
+ /** The port is down. */
+ EPSC_PORT_DOWN = 0x1,
+ /** The port is in init state. */
+ EPSC_PORT_INIT = 0x2,
+ /** The port state is armed. */
+ EPSC_PORT_ARMED = 0x3,
+ /** The port is active. */
+ EPSC_PORT_ACTIVE = 0x4,
+ /** The port is in deferred active state. */
+ EPSC_PORT_ACTIVE_DEFER = 0x5,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_PORT_STATE_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_port_state [32 bits] */
+
+/**
+ * \brief Version fixed copy of psif_path_mtu
+ * \details
+ * This enum specifies the path MTU values and is the same as `psif_path_mtu`
+ * found in `psif_verbs.h`. The difference is the data type. The version in
+ * `psif_verbs.h` is smaller!
+ *
+ * \todo
+ * Change version in `psif_verbs.h` to 32b and then drop this one here?
+ *
+ * \par Width
+ * 32 bit
+ * \par Used in
+ * psif_epsc_port_attr_t
+ * \par Classification
+ * driver
+ */
+enum psif_epsc_path_mtu {
+ /** Not a valid MTU. */
+ EPSC_MTU_INVALID = 0,
+ /** The MTU is 256 bytes. */
+ EPSC_MTU_256B = 0x1,
+ /** The MTU is 512 bytes. */
+ EPSC_MTU_512B = 0x2,
+ /** The MTU is 1024 bytes. */
+ EPSC_MTU_1024B = 0x3,
+ /** The MTU is 2048 bytes. */
+ EPSC_MTU_2048B = 0x4,
+ /** The MTU is 4069 bytes. */
+ EPSC_MTU_4096B = 0x5,
+ /** The MTU is 10240 bytes. */
+ EPSC_MTU_10240B = 0x6,
+ /** Not a specific MTU. */
+ EPSC_MTU_XXX = 0x7,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_PATH_MTU_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_path_mtu [32 bits] */
+
+/**
+ * \brief Monitors handling asynchronous event
+ * \details
+ * This is only found in a structure definition in EPS-A but not used there.
+ *
+ * \todo
+ * Remove this?
+ *
+ * \par Width
+ * 4 bit
+ * \par Used in
+ * N/A
+ * \par Classification
+ * unused
+ */
+enum psif_epsc_monitor {
+ PSIF_MONITOR_ARM,
+ PSIF_MONITOR_TRIG,
+ PSIF_MONITOR_REARM,
+ PSIF_MONITOR_INACTIVE,
+ PSIF_MONITOR_ERROR,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_MONITOR_FIELD_MAX = 0xf
+}; /* enum psif_epsc_monitor [ 4 bits] */
+
+/**
+ * \brief Interrupt sources definitions as bit indexes.
+ * \details
+ * In a mask the active interrupt sources are represented by set bits
+ * `bits[x]=(1 << EPSC_INTR_x)`. These values are defined by hardware.
+ *
+ * \par Width
+ * 5 bit
+ * \par Used in
+ * N/A
+ * \par Classification
+ * internal, development
+ */
+enum psif_epsc_interrupt_source {
+ /** Interrupt source is LCSR OR_LOW only with own (HI-)pin. */
+ EPSC_INTR_LCSR,
+ /** Interrupt source is message box OR_LOW only with own (HI-)pin. */
+ EPSC_INTR_MBOX,
+ /** Interrupt source is XIU OR_LOW only with own (HI-)pin. */
+ EPSC_INTR_XIU,
+ /** Interrupt source is IBU-0 OR_LOW only with own (HI-)pin. */
+ EPSC_INTR_IBU0,
+ /** Interrupt source is IBU-1 OR_LOW only with own (HI-)pin. */
+ EPSC_INTR_IBU1,
+ /** Interrupt source is NCSI. */
+ EPSC_INTR_TSU_NCSI,
+ /** Interrupt source is IBPB. */
+ EPSC_INTR_TSU_IBPB,
+ /** Interrupt source is DMA. */
+ EPSC_INTR_TSU_DMA,
+ /** Interrupt source is RQS. */
+ EPSC_INTR_TSU_RQS,
+ /** Interrupt source is QPS. */
+ EPSC_INTR_TSU_QPS,
+ /** Interrupt source is SQS. */
+ EPSC_INTR_TSU_SQS,
+ /** Interrupt source is ERR. */
+ EPSC_INTR_TSU_ERR,
+ /** Interrupt source is CMPL. */
+ EPSC_INTR_TSU_CMPL,
+ /** Interrupt source is VAL. */
+ EPSC_INTR_TSU_VAL,
+ /** Interrupt source is RQH. */
+ EPSC_INTR_TSU_RQH,
+ /** Interrupt source is DSCR. */
+ EPSC_INTR_TSU_DSCR,
+ /** Interrupt source is RCV. */
+ EPSC_INTR_TSU_RCV,
+ /** Interrupt source is IBPR. */
+ EPSC_INTR_TSU_IBPR,
+ /** Interrupt source is CBU. */
+ EPSC_INTR_TSU_CBU,
+ /** Interrupt source is HOST. */
+ EPSC_INTR_TSU_HOST,
+ /** Interrupt source is MMU. */
+ EPSC_INTR_TSU_MMU
+}; /* enum psif_epsc_interrupt_source [ 5 bits] */
+
+/**
+ * \brief Interrupt severity levels
+ * \details
+ * This lists the interrupt levels as used by the simulators PRM responder
+ * (psifsim) and cosim. They are not in sync with the values used by EPS
+ * firmware.
+ *
+ * \par Width
+ * 2 bit
+ * \par Used in
+ * N/A
+ * \par Classification
+ * development
+ */
+enum psif_epsc_interrupt_pri {
+ /** unknown/invalid interrupt priority */
+ EPSC_INTR_RESERVED,
+ /** low interrupt priority */
+ EPSC_INTR_LOW,
+ /** high interrupt priority */
+ EPSC_INTR_HIGH,
+ /** nonmaskable/fatal interrupt */
+ EPSC_INTR_FATAL
+}; /* enum psif_epsc_interrupt_pri [ 2 bits] */
+
+/**
+ * \brief Query HCA verb response member `atomicity guarantee` values
+ * \details
+ * This enum specifies values possible for the (masked) atomicity guarantee
+ * capability reported in the Query HCA verb (via \ref EPSC_QUERY_DEVICE).
+ *
+ * \par Width
+ * 32 bit
+ * \par Used in
+ * psif_epsc_device_attr_t
+ * \par Classification
+ * driver
+ */
+enum psif_epsc_atomic_cap {
+ /** no atomicity guarantee */
+ EPSC_ATOMIC_NONE,
+ /** HCA atomicity guarantee */
+ EPSC_ATOMIC_HCA,
+ /** global atomicity guarantee */
+ EPSC_ATOMIC_GLOB,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_ATOMIC_CAP_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_atomic_cap [32 bits] */
+
+/**
+ * \brief The EPS-C FW status return codes
+ * \details These error codes are retured from the EPS-C.
+ * \par Width
+ * 8 bit
+ * \par Used in
+ * psif_epsc_csr_rsp member `status`
+ * \par Classification
+ * external, driver
+ */
+enum psif_epsc_csr_status {
+ /** Successful exit status. */
+ EPSC_SUCCESS = 0,
+ /** Key was rejected by service. */
+ EPSC_EKEYREJECTED = 0x1,
+ /** Cannot assign requested address. */
+ EPSC_EADDRNOTAVAIL = 0x2,
+ /** Operation not supported on transport endpoint. */
+ EPSC_EOPNOTSUPP = 0x3,
+ /** Out of memory. */
+ EPSC_ENOMEM = 0x4,
+ /** No data available. */
+ EPSC_ENODATA = 0x5,
+ /** Try again. */
+ EPSC_EAGAIN = 0x6,
+ /** Operation canceled. */
+ EPSC_ECANCELED = 0x7,
+ /** Connection reset by peer. */
+ EPSC_ECONNRESET = 0x8,
+ /** CSR operation failed. */
+ EPSC_ECSR = 0x9,
+ /** Modify queue pair error: QP index out of range. */
+ EPSC_MODIFY_QP_OUT_OF_RANGE = 0xa,
+ /** Modify queue pair error: QP is invalid. */
+ EPSC_MODIFY_QP_INVALID = 0xb,
+ /** Modify queue pair error: failed to change QP attribute. */
+ EPSC_MODIFY_CANNOT_CHANGE_QP_ATTR = 0xc,
+ /** Modify queue pair error: failed to change QP due to invalid or not matching state. */
+ EPSC_MODIFY_INVALID_QP_STATE = 0xd,
+ /** Modify queue pair error: failed to change QP due to invalid or not matching migration state. */
+ EPSC_MODIFY_INVALID_MIG_STATE = 0xe,
+ /** Modify queue pair error: the operation timed out. */
+ EPSC_MODIFY_TIMEOUT = 0xf,
+ /** DMA test failure in HEAD. */
+ EPSC_ETEST_HEAD = 0x10,
+ /** DMA test failure in TAIL. */
+ EPSC_ETEST_TAIL = 0x11,
+ /** DMA test failure in PATTERN. */
+ EPSC_ETEST_PATTERN = 0x12,
+ /** Multicast address already exist. */
+ EPSC_EADDRINUSE = 0x13,
+ /** vHCA out of range */
+ EPSC_EINVALID_VHCA = 0x14,
+ /** Port out of range */
+ EPSC_EINVALID_PORT = 0x15,
+ /** Address out of range */
+ EPSC_EINVALID_ADDRESS = 0x16,
+ /** Parameter out of range */
+ EPSC_EINVALID_PARAMETER = 0x17,
+ /** General failure. */
+ EPSC_FAIL = 0xff
+}; /* enum psif_epsc_csr_status [ 8 bits] */
+
+/**
+ * \brief Host to EPS operation codes
+ * \details
+ * These operation codes are sent in the \ref psif_epsc_csr_req::opcode member
+ * from the host or a particular core (EPS-Ax/EPS-C) to the mailbox thread in
+ * EPS-C or EPS-Ax in order to specify the request. In addition the operation
+ * codes are used as a selector for the \ref psif_epsc_csr_req::u member of
+ * type \ref psif_epsc_csr_details_t in order to specify the particular
+ * structure if the request requires specific arguments. In some cases the
+ * selected structure defines an own set of sub-operation codes like for
+ * \ref EPSC_QUERY with \ref psif_epsc_query_req_t::op of type
+ * \ref psif_epsc_query_op_t.
+ * \par
+ * Responses are always of type \ref psif_epsc_csr_rsp_t but the meaning of the
+ * members of that structure depend on the operation code. The response state
+ * is \ref EPSC_EADDRNOTAVAIL for all not supported operation codes.
+ *
+ * \par Width
+ * 8 bit
+ * \par Used in
+ * psif_epsc_csr_req_t
+ * \par Classification
+ * see each of the operation codes
+ *
+ * \note
+ * - All codes must be unique and fit into a 8 bit number.
+ * - In order to provide backward compatibility new codes must start from the
+ * current value of \ref EPSC_LAST_OP and the value of \ref EPSC_LAST_OP
+ * must be incremented by the number of newly inserted codes.
+ */
+enum psif_epsc_csr_opcode {
+ /** Not a valid operation code. */
+ EPSC_NOOP = 0,
+ /** EPS-C ping over mailbox. */
+ EPSC_MAILBOX_PING = 0x4c,
+ /** Host patting of EPS-C SW watch-dog. */
+ EPSC_KEEP_ALIVE = 0x4d,
+ /** Initial configuration request per UF.
+ * This request is transferred from the host to the epsc at driver
+ * attach using an encoding of the physical mailbox register. It
+ * is not a legal request on an operational mailbox communication
+ *
+ * \par Request
+ * Structure details:
+ * Member | Content
+ * -------|-------------------
+ * u | \ref psif_epsc_csr_config_t
+ * \par Response
+ * Structure contents:
+ * Member | Content
+ * -------|-------------------
+ * addr | number of event queues (EQ) per UF
+ * data | PSIF/EPS-C version
+ * \par
+ * The version is encoded this way:
+ * Bits | Version Specifier
+ * ------|---------
+ * 63-48 | PSIF_MAJOR_VERSION
+ * 47-32 | PSIF_MINOR_VERSION
+ * 31-16 | EPSC_MAJOR_VERSION
+ * 15-0 | EPSC_MINOR_VERSION
+ *
+ * \par Return Codes
+ * \ref EPSC_SUCCESS
+ * \par Restrictions
+ * none (all UF)
+ * \par Classification
+ * driver
+ */
+ EPSC_SETUP = 0x1,
+ /** Final de-configuration request.
+ * This request is sent from the host driver to indicate that it has
+ * cleaned up all queues and flushed caches associated with the current
+ * UF. It is the last command for that UF and the firmware will take down
+ * the associated virtual links and mailbox settings. For further
+ * communication with that UF the mailbox needs to be set up again via
+ * \ref EPSC_SETUP .
+ *
+ * \par Request
+ * N/A
+ * \par Return Codes
+ * \ref EPSC_SUCCESS
+ * \par Restrictions
+ * none (all UF)
+ * \par Classification
+ * driver
+ */
+ EPSC_TEARDOWN = 0x36,
+ /** Operation code for a general set request.
+ * The request usees the same parameter structure as the \ref EPSC_QUERY
+ * request. Upon recieve the mailbox thread first processes the set request
+ * in \ref psif_epsc_csr_query_t::info and then the request in
+ * \ref psif_epsc_csr_query_t::data. Both members are of type
+ * \ref psif_epsc_query_req_t and have their own sub-operation codes in
+ * \ref psif_epsc_query_req_t::op (of type \ref psif_epsc_query_op_t).
+ * Therefore requests instantiating only one set attribute
+ * (i.e. \ref psif_epsc_csr_query_t::info or \ref psif_epsc_csr_query_t::data)
+ * have to set the sub-operation code of the other member to
+ * \ref EPSC_QUERY_BLANK.
+ *
+ * \par Request
+ * Structure details:
+ * Member | Content
+ * -------|-------------------
+ * u | \ref psif_epsc_csr_query_t
+ * \par Return Codes
+ * \ref EPSC_SUCCESS, \ref EPSC_EOPNOTSUPP, \ref EPSC_FAIL
+ * \par Restrictions
+ * none (all UF)
+ * \par Classification
+ * external
+ */
+ EPSC_SET = 0x46,
+ /** Operation code for a single CSR write request.
+ * \note
+ * The request is deprecated and will be removed as soon as all
+ * references to this opcode have been cleaned up.
+ * \par Return Codes
+ * \ref EPSC_EADDRNOTAVAIL
+ */
+ EPSC_SET_SINGLE = 0x2,
+ /** Operation code for setting an arbitrary CSR.
+ * \note
+ * The request is used mainly for debugging tools and will be either removed
+ * completely or limited to certain register addresses.
+ *
+ * \par Request
+ * Structure details:
+ * Member | Content
+ * -------|-------------------
+ * addr | CSR address
+ * u | `data[0]` value to write to CSR
+ * \par Response
+ * Structure contents:
+ * Member | Content
+ * -------|----------------------------------------
+ * addr | the value `addr` from the request
+ * data | the value `data[0]` from the request
+ *
+ * \par Return Codes
+ * \ref EPSC_SUCCESS, \ref EPSC_FAIL
+ * \par Restrictions
+ * valid register addresses depend on UF
+ * \par Classification
+ * driver, development
+ */
+ EPSC_SET_ONE_CSR = 0x3,
+ /** Old operation code to set up a descriptor base address.
+ * \note
+ * The request is deprecated and will be removed as soon as all
+ * references to this opcode have been cleaned up.
+ *
+ * \par Return Codes
+ * \ref EPSC_EADDRNOTAVAIL
+ * \par Classification
+ * driver
+ */
+ EPSC_SETUP_BASEADDR = 0x4,
+ /** Operation code to set up a descriptor base address.
+ * With this request the driver configures the descriptor base addresses
+ * of queues, queue pairs and address handles.
+ *
+ * \par Request
+ * Structure details:
+ * Member | Content
+ * -------|-------------------------------------------
+ * addr | Descriptor base address setup CSR address
+ * u | \ref psif_epsc_csr_base_addr_t
+ *
+ * \par Return Codes
+ * \ref EPSC_SUCCESS, \ref EPSC_FAIL
+ * \par Restrictions
+ * none (all UF)
+ * \par Classification
+ * driver, development
+ */
+ EPSC_SET_BASEADDR = 0x5,
+ /** Operation code to set up an event queue (EQ).
+ * With this request the driver configures an EQ descriptor base address
+ * as well as the associated interrupt.
+ *
+ * \par Request
+ * Structure details:
+ * Member | Content
+ * -------|-------------------------------------------
+ * addr | event queue number
+ * u | \ref psif_epsc_csr_base_addr_t
+ *
+ * \par Return Codes
+ * \ref EPSC_SUCCESS, \ref EPSC_FAIL
+ * \par Restrictions
+ * none (all UF)
+ * \par Classification
+ * driver
+ */
+ EPSC_SET_BASEADDR_EQ = 0x6,
+ /* Set Local ID for UF (backdoor) */
+ EPSC_SET_LID = 0x7,
+ OBSOLETE_1 = 0x8,
+ OBSOLETE_2 = 0x9,
+ /* Set Global ID for UF (backdoor) */
+ EPSC_SET_GID = 0xa,
+ /* Set EoIB MAC address (backdoor) */
+ EPSC_SET_EOIB_MAC = 0x40,
+ /* Set Vlink state */
+ EPSC_SET_VLINK_STATE = 0xb,
+ /* Get Vlink state */
+ EPSC_QUERY_VLINK_STATE = 0xc,
+ /* Reset UF at startup */
+ EPSC_UF_RESET = 0xd,
+ /* Modify QP complete w/kick */
+ EPSC_MODIFY_QP = 0xe,
+ /* Get single 64bit register - depricated */
+ EPSC_GET_SINGLE = 0xf,
+ /* Get one 64bit register using CSR addr */
+ EPSC_GET_ONE_CSR = 0x10,
+ /* Query QP sub-entry */
+ EPSC_QUERY_QP = 0x11,
+ /** Query HW receive queue. */
+ EPSC_QUERY_HW_RQ = 0x42,
+ /** Query HW SQ. */
+ EPSC_QUERY_HW_SQ = 0x43,
+ /* Non-MAD query device */
+ EPSC_QUERY_DEVICE = 0x12,
+ /* Non-MAD query port */
+ EPSC_QUERY_PORT_1 = 0x13,
+ EPSC_QUERY_PORT_2 = 0x14,
+ /* Non-MAD SMA attribute query */
+ EPSC_QUERY_PKEY = 0x15,
+ EPSC_QUERY_GID = 0x16,
+ /* Non-MAD SMA attribute setting */
+ EPSC_MODIFY_DEVICE = 0x17,
+ EPSC_MODIFY_PORT_1 = 0x18,
+ EPSC_MODIFY_PORT_2 = 0x19,
+ /* Local MC subscription handling */
+ EPSC_MC_ATTACH = 0x1a,
+ EPSC_MC_DETACH = 0x1b,
+ EPSC_MC_QUERY = 0x1c,
+ /* Handle asynchronous events */
+ EPSC_EVENT_ACK = 0x1d,
+ EPSC_EVENT_INDEX = 0x1e,
+ /* Program flash content */
+ EPSC_FLASH_START = 0x1f,
+ EPSC_FLASH_INFO = 0x20,
+ EPSC_FLASH_ERASE_SECTOR = 0x21,
+ EPSC_FLASH_RD = 0x22,
+ EPSC_FLASH_WR = 0x23,
+ EPSC_FLASH_CHECK = 0x24,
+ EPSC_FLASH_SCAN = 0x25,
+ EPSC_FLASH_STOP = 0x26,
+ /* new update handling */
+ EPSC_UPDATE = 0x47,
+ /* IB packet tracer */
+ EPSC_TRACE_STATUS = 0x27,
+ EPSC_TRACE_SETUP = 0x28,
+ EPSC_TRACE_START = 0x29,
+ EPSC_TRACE_STOP = 0x2a,
+ EPSC_TRACE_ACQUIRE = 0x2b,
+ /* Test operations */
+ EPSC_TEST_HOST_RD = 0x2c,
+ EPSC_TEST_HOST_WR = 0x2d,
+ /* Get EPS-C version details */
+ EPSC_FW_VERSION = 0x2e,
+ /* Redirection/configuration of EPSC's internal log subsystem */
+ EPSC_LOG_CTRL = 0x2f,
+ EPSC_LOG_REQ_NOTIFY = 0x30,
+ /* Force & read back link speed */
+ EPSC_LINK_CNTRL = 0x31,
+ /* EPS-A control & communication (to EPS-C) */
+ EPSC_A_CONTROL = 0x33,
+ /* EPS-A targeted commands (to EPS-A) */
+ EPSC_A_COMMAND = 0x35,
+ /* Exercise mmu with access from epsc */
+ EPSC_EXERCISE_MMU = 0x34,
+ /* Access to EPS-C CLI */
+ EPSC_CLI_ACCESS = 0x37,
+ /* IB packet proxy to/from host */
+ EPSC_MAD_PROCESS = 0x38,
+ EPSC_MAD_SEND_WR = 0x39,
+ /** Generic query epsc interface. */
+ EPSC_QUERY = 0x41,
+ /* Setup interrupt coalescing etc. */
+ EPSC_HOST_INT_COMMON_CTRL = 0x44,
+ EPSC_HOST_INT_CHANNEL_CTRL = 0x45,
+ /** UF control depends on \ref psif_epsc_csr_uf_ctrl_t::opcode. */
+ EPSC_UF_CTRL = 0x48,
+ /* Flush MMU and-or PTW Caches */
+ EPSC_FLUSH_CACHES = 0x49,
+ /* Query PMA counters - alternative path to sending MAD's */
+ EPSC_PMA_COUNTERS = 0x4a,
+ /** VIMMA operations depends on \ref psif_epsc_csr_vimma_ctrl_t::opcode. */
+ EPSC_VIMMA_CTRL = 0x4b,
+ /** EOF marker - must be last and highest in this enum type. */
+ EPSC_LAST_OP = 0x4e,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_CSR_OPCODE_FIELD_MAX = 0xff
+}; /* enum psif_epsc_csr_opcode [ 8 bits] */
+
+/**
+ * The eps-c fw csr flags
+ */
+enum psif_epsc_csr_flags {
+ EPSC_FL_NONE = 0,
+ /* Request notification (interrupt) when completion is ready */
+ EPSC_FL_NOTIFY = 0x1,
+ /* Privileged QP indicator only valid for query and modify QP */
+ EPSC_FL_PQP = 0x2,
+ /* Allways report opertion success */
+ EPSC_FL_IGNORE_ERROR = 0x4,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_CSR_FLAGS_FIELD_MAX = 0xff
+}; /* enum psif_epsc_csr_flags [ 8 bits] */
+
+/*
+ * Link states for the virtual HCA and switch. The following onehot encoded
+ * states exist: PSIF_LINK_DISABLED = 1 PSIF_LINK_DOWN = 2 PSIF_LINK_INIT = 4
+ * PSIF_LINK_ARM = 8 PSIF_LINK_ACTIVE = 16
+ */
+enum psif_vlink_state {
+ PSIF_LINK_DISABLED = 0x1,
+ PSIF_LINK_DOWN = 0x2,
+ PSIF_LINK_INIT = 0x4,
+ PSIF_LINK_ARM = 0x8,
+ PSIF_LINK_ACTIVE = 0x10
+}; /* enum psif_vlink_state [ 5 bits] */
+
+/**
+ * EPSC_MODIFY_DEVICE operations
+ */
+enum psif_epsc_csr_modify_device_flags {
+ PSIF_DEVICE_MODIFY_SYS_IMAGE_GUID = 0x1,
+ PSIF_DEVICE_MODIFY_NODE_DESC = 0x2,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_CSR_MODIFY_DEVICE_FLAGS_FIELD_MAX = 0xffff
+}; /* enum psif_epsc_csr_modify_device_flags [16 bits] */
+
+/**
+ * EPSC_MODIFY_PORT_{1,2} operations
+ */
+enum psif_epsc_csr_modify_port_flags {
+ PSIF_PORT_SHUTDOWN = 0x1,
+ PSIF_PORT_INIT_TYPE = 0x4,
+ PSIF_PORT_RESET_QKEY_CNTR = 0x8,
+ PSIF_PORT_RESET_PKEY_CNTR = 0x10,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_CSR_MODIFY_PORT_FLAGS_FIELD_MAX = 0xffff
+}; /* enum psif_epsc_csr_modify_port_flags [16 bits] */
+
+
+enum psif_epsc_csr_epsa_command {
+ EPSC_A_LOAD,
+ EPSC_A_START,
+ EPSC_A_STOP,
+ EPSC_A_STATUS,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_CSR_EPSA_COMMAND_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_csr_epsa_command [32 bits] */
+
+/*
+ */
+enum psif_epsa_command {
+ EPSA_DYNAMIC_LOAD,
+ EPSA_TEST_FABOUT,
+ EPSA_TEST_FABIN,
+ EPSA_TEST_FABIN_FABOUT,
+ EPSA_TEST_SKJM_MEMREAD,
+ EPSA_TEST_SKJM_MEMWRITE,
+ EPSA_TEST_SKJM_MEMLOCK,
+ EPSA_SKJM_LOAD,
+ EPSA_SKJM_ACC,
+ EPSA_SKJM_MEMACC,
+ EPSA_GET_PROXY_QP_SQ_KEY,
+ /* Padding out to required bits allocated */
+ PSIF_EPSA_COMMAND_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsa_command [32 bits] */
+
+/**
+ * \brief Sub-operation codes as used by EPSC_QUERY and EPSC_SET requests.
+ * \details
+ * \par Width
+ * 32 bit
+ * \par Used in
+ * psif_epsc_query_req member `op`
+ * \par Classification
+ * internal, development
+ */
+enum psif_epsc_query_op {
+ /** If initiated from a EPSC_QUERY this operation code will always return zero and report success.
+ * In case of a intended set request (EPSC_SET) this operation code ignore the request and return success.
+ */
+ EPSC_QUERY_BLANK = 0,
+ /* Obsolete - use EPSC_QUERY_CAP_VCB_{LO HI} */
+ EPSC_QUERY_CAP_VCB = 0x1,
+ /* Obsolete - use EPSC_QUERY_CAP_PCB_{LO HI} */
+ EPSC_QUERY_CAP_PCB = 0x2,
+ EPSC_QUERY_NUM_UF = 0x3,
+ EPSC_QUERY_GID_HI = 0x4,
+ EPSC_QUERY_GID_LO = 0x5,
+ EPSC_QUERY_P_KEY = 0x6,
+ EPSC_QUERY_Q_KEY = 0x7,
+ EPSC_QUERY_UF = 0x8,
+ EPSC_QUERY_LINK_STATE = 0x9,
+ EPSC_QUERY_VHCA_STATE = 0xa,
+ /* Corresponds to register TSU_HOST_INT_CTRL_ADDR */
+ EPSC_QUERY_INT_COMMON = 0xb,
+ /* Corresponds to register TSU_HOST_INT_CHAN_CTRL_0 */
+ EPSC_QUERY_INT_CHAN_RATE = 0xc,
+ /* Corresponds to register TSU_HOST_INT_CHAN_CTRL_1 */
+ EPSC_QUERY_INT_CHAN_AUSEC = 0xd,
+ /* Corresponds to register TSU_HOST_INT_CHAN_CTRL_2 */
+ EPSC_QUERY_INT_CHAN_PUSEC = 0xe,
+ /* Number of VCBs in PCI lo BAR */
+ EPSC_QUERY_CAP_VCB_LO = 0xf,
+ /* Number of VCBs in PCI hi BAR */
+ EPSC_QUERY_CAP_VCB_HI = 0x10,
+ /* Number of PCBs mapped to lo BAR VCBs */
+ EPSC_QUERY_CAP_PCB_LO = 0x11,
+ /* Number of PCBs mapped to hi BAR VCBs */
+ EPSC_QUERY_CAP_PCB_HI = 0x12,
+ /* psif_epsc_query_req.index = IB port number [1 2] */
+ EPSC_QUERY_PMA_REDIRECT_QP = 0x13,
+ /* uptime in seconds */
+ EPSC_QUERY_FW_UPTIME = 0x14,
+ /* date the firmware was programmed in epoch time */
+ EPSC_QUERY_FW_PROG_DATE = 0x15,
+ /* date the firmware was built in epoch time */
+ EPSC_QUERY_FW_BUILD_DATE = 0x16,
+ /* current firmware image number (flash slot) */
+ EPSC_QUERY_FW_CURR_IMG = 0x17,
+ /* oneshot firmware image number (flash slot) */
+ EPSC_QUERY_FW_ONESHOT_IMG = 0x18,
+ /* autostart firmware image number (flash slot) */
+ EPSC_QUERY_FW_AUTOSTART_IMG = 0x19,
+ /* bit field encoding why the FW image was booted */
+ EPSC_QUERY_FW_START_CAUSE = 0x1a,
+ /* firmware version */
+ EPSC_QUERY_FW_VERSION = 0x1b,
+ /* Requester - number of bad response errors. */
+ EPSC_QUERY_SQ_NUM_BRE = 0x1c,
+ /* Requester - number of bad response errors. */
+ EPSC_QUERY_NUM_CQOVF = 0x1d,
+ /* Requester - number of CQEs with status flushed in error. */
+ EPSC_QUERY_SQ_NUM_WRFE = 0x1e,
+ /* Responder - number of CQEs with status flushed in error. */
+ EPSC_QUERY_RQ_NUM_WRFE = 0x1f,
+ /* Responder - number of local access errors. */
+ EPSC_QUERY_RQ_NUM_LAE = 0x20,
+ /* Responder - number of local protection errors. */
+ EPSC_QUERY_RQ_NUM_LPE = 0x21,
+ /* Requester - number of local length errors. */
+ EPSC_QUERY_SQ_NUM_LLE = 0x22,
+ /* Responder - number of local length errors. */
+ EPSC_QUERY_RQ_NUM_LLE = 0x23,
+ /* Requester - number local QP operation error. */
+ EPSC_QUERY_SQ_NUM_LQPOE = 0x24,
+ /* Responder - number local QP operation error. */
+ EPSC_QUERY_RQ_NUM_LQPOE = 0x25,
+ /* Requester - number of NAK-Sequence Error received. */
+ EPSC_QUERY_SQ_NUM_OOS = 0x26,
+ /* Responder - number of NAK-Sequence Error sent. */
+ EPSC_QUERY_RQ_NUM_OOS = 0x27,
+ /* Requester - number of RNR nak retries exceeded errors. */
+ EPSC_QUERY_SQ_NUM_RREE = 0x28,
+ /* Requester - number of transport retries exceeded errors. */
+ EPSC_QUERY_SQ_NUM_TREE = 0x29,
+ /* Requester - number of NAK-Remote Access Error received. */
+ EPSC_QUERY_SQ_NUM_ROE = 0x2a,
+ /*
+ * Responder - number of NAK-Remote Access Error sent. NAK-Remote Operation
+ * Error on: 1. Malformed WQE: Responder detected a malformed Receive Queue
+ * WQE while processing the packet. 2. Remote Operation Error: Responder
+ * encountered an error, (local to the responder), which prevented it from
+ * completing the request.
+ */
+ EPSC_QUERY_RQ_NUM_ROE = 0x2b,
+ /*
+ * Requester - number of NAK-Remote Access Error received. R_Key Violation:
+ * Responder detected an invalid R_Key while executing an RDMA Request.
+ */
+ EPSC_QUERY_SQ_NUM_RAE = 0x2c,
+ /*
+ * Responder - number of NAK-Remote Access Error sent. R_Key Violation
+ * Responder detected an R_Key violation while executing an RDMA request.
+ */
+ EPSC_QUERY_RQ_NUM_RAE = 0x2d,
+ /*
+ * The number of UD packets silently discarded on the receive queue due to
+ * lack of receive descriptor.
+ */
+ EPSC_QUERY_RQ_NUM_UDSDPRD = 0x2e,
+ /*
+ * The number of UC packets silently discarded on the receive queue due to
+ * lack of receive descriptor.
+ */
+ EPSC_QUERY_RQ_NUM_UCSDPRD = 0x2f,
+ /*
+ * Requester - number of remote invalid request errors NAK-Invalid Request
+ * on: 1. Unsupported OpCode: Responder detected an unsupported OpCode. 2.
+ * Unexpected OpCode: Responder detected an error in the sequence of OpCodes,
+ * such as a missing Last packet.
+ */
+ EPSC_QUERY_SQ_NUM_RIRE = 0x30,
+ /*
+ * Responder - number of remote invalid request errors. NAK may or may not be
+ * sent. 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD
+ * only): Inbound request OpCode was either reserved, or was for a function
+ * not supported by thisQP. (E.g. RDMA or ATOMIC on QP not set up for this).
+ * 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic
+ * operation. 3. Too many RDMA READ or ATOMIC Requests: There were more
+ * requests received and not ACKed than allowed for the connection. 4. Out of
+ * Sequence OpCode, current packet is First or Only: The Responder detected
+ * an error in the sequence of OpCodes; a missing Last packet. 5. Out of
+ * Sequence OpCode, current packet is not First or Only: The Responder
+ * detected an error in the sequence of OpCodes; a missing First packet. 6.
+ * Local Length Error: Inbound Send request message exceeded the responder's
+ * available buffer space. 7. Length error: RDMA WRITE request message
+ * contained too much or too little pay-load data compared to the DMA length
+ * advertised in the first or only packet. 8. Length error: Payload length
+ * was not consistent with the opcode: a: only is between 0 and PMTU bytes b:
+ * (first or middle) equals PMTU bytes c: last is between 1 byte and PMTU
+ * bytes 9. Length error: Inbound message exceeded the size supported by the
+ * CA port.
+ */
+ EPSC_QUERY_RQ_NUM_RIRE = 0x31,
+ /* Requester - the number of RNR Naks received. */
+ EPSC_QUERY_SQ_NUM_RNR = 0x32,
+ /* Responder - the number of RNR Naks sent. */
+ EPSC_QUERY_RQ_NUM_RNR = 0x33,
+ /* twoshot firmware image number (flash slot) */
+ EPSC_QUERY_FW_TWOSHOT_IMG = 0x34,
+ /* firmware type */
+ EPSC_QUERY_FW_TYPE = 0x35,
+ /* firmware size */
+ EPSC_QUERY_FW_SIZE = 0x36,
+ /* firmware slot size (available space for an image) */
+ EPSC_QUERY_FW_SLOT_SIZE = 0x37,
+ /* version of boot loader that has started the application */
+ EPSC_QUERY_BL_VERSION = 0x38,
+ /* boot loader build date in epoch time format */
+ EPSC_QUERY_BL_BUILD_DATE = 0x39,
+ /* only used by EPSC_SET mark a PQP CQ ID as clean (WA bug 3769) */
+ EPSC_QUERY_CLEAN_CQ_ID = 0x3a,
+ /* Number of TSL supported by FW */
+ EPSC_QUERY_CAP_TSL_TX = 0x3b,
+ EPSC_QUERY_CAP_TSL_RX = 0x3c,
+ /* Reset CBLD Diag counters. Only used by EPSC_SET */
+ EPSC_QUERY_RESET_CBLD_DIAG_COUNTERS = 0x3d,
+ /* Max QP index used since power-on or host reset - to optimize WA for HW bug 3251 */
+ EPSC_QUERY_MAX_QP_USED = 0x3e,
+ /** the UF and QP where modify QP timed out ((uf << 32) | (qp)) */
+ EPSC_QUERY_MODQP_TO_SOURCE = 0x3f,
+ /** the debug register when modify QP timed out */
+ EPSC_QUERY_MODQP_TO_DEBUG = 0x40,
+ /** the bit vector containing the reasons for entering degraded mode */
+ EPSC_QUERY_DEGRADED_CAUSE = 0x41,
+ /** CMPL spin set mode (safe = 1 fast = 0) */
+ EPSC_QUERY_SPIN_SET_CONTROL = 0x42,
+ /** VPD MAC address */
+ EPSC_QUERY_VPD_MAC = 0x43,
+ /** VPD part number */
+ EPSC_QUERY_VPD_PART_NUMBER = 0x44,
+ /** VPD revision */
+ EPSC_QUERY_VPD_REVISION = 0x45,
+ /** VPD serial number (big endian sub-string) - 8 byte offset in query index */
+ EPSC_QUERY_VPD_SERIAL_NUMBER = 0x46,
+ /** VPD manufacturer = = Oracle Corporation - 8 byte offset in query index */
+ EPSC_QUERY_VPD_MANUFACTURER = 0x47,
+ /** PSIF TSU SL and QoS mapping for priv QP - port number in query index */
+ EPSC_QUERY_MAP_PQP_TO_TSL = 0x48,
+ /** PSIF TSU SL and QoS mapping for IB SL 0-7 - port number in query index */
+ EPSC_QUERY_MAP_SL_TO_TSL_LO = 0x49,
+ /** PSIF TSU SL and QoS mapping for IB SL 8-15 - port number in query index */
+ EPSC_QUERY_MAP_SL_TO_TSL_HI = 0x4a,
+ /** VPD Product Name - 8 byte offset in query index */
+ EPSC_QUERY_VPD_PRODUCT_NAME = 0x4b,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_QUERY_OP_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_query_op [32 bits] */
+
+/**
+ * Valid values for struct psif_epsc_csr_update::opcode
+ */
+enum psif_epsc_csr_update_opcode {
+ EPSC_UPDATE_OP_POLL = 0,
+ EPSC_UPDATE_OP_START,
+ EPSC_UPDATE_OP_ERASE,
+ EPSC_UPDATE_OP_WRITE,
+ EPSC_UPDATE_OP_READ,
+ EPSC_UPDATE_OP_STOP,
+ EPSC_UPDATE_OP_SET,
+ EPSC_UPDATE_OP_MAX,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_CSR_UPDATE_OPCODE_FIELD_MAX = 0xffff
+}; /* enum psif_epsc_csr_update_opcode [16 bits] */
+
+/**
+ * Flash slot numbers used by e.g. EPSC_QUERY::EPSC_QUERY_FW_CURR_IMG
+ */
+enum psif_epsc_flash_slot {
+ EPSC_FLASH_SLOT_INVALID,
+ EPSC_FLASH_SLOT_EPS_C_IMG_1,
+ EPSC_FLASH_SLOT_EPS_C_IMG_2,
+ EPSC_FLASH_SLOT_EPS_A_IMG,
+ EPSC_FLASH_SLOT_BOOT_IMG,
+ /* always last */
+ EPSC_FLASH_SLOT_COUNT,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_FLASH_SLOT_FIELD_MAX = 0xffff
+}; /* enum psif_epsc_flash_slot [16 bits] */
+
+/**
+ * Valid values for struct psif_epsc_csr_update::u::set
+ */
+enum psif_epsc_update_set {
+ EPSC_UPDATE_SET_INVALID,
+ EPSC_UPDATE_SET_AUTOSTART_IMG,
+ EPSC_UPDATE_SET_ONESHOT_IMG,
+ EPSC_UPDATE_SET_TWOSHOT_IMG,
+ EPSC_UPDATE_SET_IMG_VALID,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_UPDATE_SET_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_update_set [32 bits] */
+
+/**
+ * Opcodes for psif_epsc_csr_uf_ctrl_t::opcode
+ */
+enum psif_epsc_csr_uf_ctrl_opcode {
+ EPSC_UF_CTRL_MMU_FLUSH,
+ EPSC_UF_CTRL_GET_UF_USED_QP,
+ EPSC_UF_CTRL_CLEAR_UF_USED_QP,
+ /** For SMP {en dis}able is the flag param a bitvector for which ports to update 0x6 hence indicate P1 and P2. */
+ EPSC_UF_CTRL_SMP_ENABLE,
+ EPSC_UF_CTRL_SMP_DISABLE,
+ /** For Vlink {dis }connect is the flag param a bitvector for which ports to update 0x6 hence indicate P1 and P2. */
+ EPSC_UF_CTRL_VLINK_CONNECT,
+ EPSC_UF_CTRL_VLINK_DISCONNECT,
+ /** Retrieve the highest QP number used by the given UF */
+ EPSC_UF_CTRL_GET_HIGHEST_QP_IDX,
+ /** Reset the highest QP number cache for the given UF */
+ EPSC_UF_CTRL_RESET_HIGHEST_QP_IDX,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_CSR_UF_CTRL_OPCODE_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_csr_uf_ctrl_opcode [32 bits] */
+
+/**
+ * \brief Host to VIMMA operation codes
+ * \details
+ * These operation codes are sent in the
+ * \ref psif_epsc_csr_vimma_ctrl_t::opcode member
+ * from the host to the mailbox thread in EPS-C in order to specify the
+ * VIMMA request. In addition the operation
+ * codes are used as a selector for the
+ * \ref psif_epsc_csr_vimma_ctrl_t::u member of
+ * psif_epsc_csr_vimma_ctrl_t in order to specify a particular
+ * set of arguments if the request requires specific arguments.
+ * \par
+ * User of the VIMMA operation codes is the "PSIF SRIOV control API" library
+ * running in Dom0 in user space. This library uses libsif to access the
+ * mailbox. Requests are formed by using the VIMMA operation codes. Response
+ * status is always delivered "inline" as return codes when the libsif API
+ * returns from the mailbox operations.
+ * Additional information retrieval can either be delivered "inline" as long
+ * as space permits inside the mailbox response, OR responses
+ * can also be extended by DMA-ing back response structures to pinned memory
+ * in the library.
+ * The DMA memory is prepared by the library before executing an opcode
+ * that requires DMA for requested data.
+ * \par
+ * INLINE responses: Response data from VIMMA operation codes are delivered
+ * via libsif to the "PSIF SRIOV control API" as two u64
+ * parameters: "data" and "info".
+ * These are carried by \ref psif_epsc_csr_rsp_t as part of mailbox response.
+ * The encoding of the "data" and "info" responses depend on the VIMMA operation
+ * code. For code using libsif library, the two u64 response codes "data"
+ * and "info" is overlayed with the union
+ * \ref psif_epsc_csr_vimma_ctrl_resp_inline_u,
+ * and by using the opcode as a selector for the union members, the correct info
+ * from the operation will be found.
+ * \par
+ * DMA responses: The requested data using DMA is delivered back to caller in
+ * pinned memory of appropriate size. A pinned memory block of the maximum sized
+ * response structure will do, and this can be obtained as
+ * sizeof(psif_epsc_csr_vimma_ctrl_resp_dma_u) + appropriate extension for
+ * for some variable arrays if those extend outside of
+ * psif_epsc_csr_vimma_ctrl_resp_dma_uend of some union members.
+ * The opcode just executed will be the selector for the union members.
+ *
+ * \par Width
+ * 32 bit
+ * \par Used in
+ * psif_epsc_csr_vimma_ctrl_t
+ * \par Classification
+ * external
+ *
+ * \note
+ * - In order to provide backward compatibility new codes must be added
+ * at the end of the enum. Deprecated codes can not be removed, but will instead
+ * be responded to with error codes if not supported anymore.
+ */
+enum psif_epsc_vimma_ctrl_opcode {
+ /* no DMA.*/
+ EPSC_VIMMA_CTRL_GET_VER_AND_COMPAT,
+ /* DMA for resp. */
+ EPSC_VIMMA_CTRL_GET_MISC_INFO,
+ /* DMA for resp. */
+ EPSC_VIMMA_CTRL_GET_GUIDS,
+ /* DMA for resp. */
+ EPSC_VIMMA_CTRL_GET_REG_INFO,
+ /* DMA for resp. */
+ EPSC_VIMMA_CTRL_GET_VHCA_STATS,
+ /* no DMA. */
+ EPSC_VIMMA_CTRL_SET_VFP_VHCA_REGISTER,
+ /* no DMA. */
+ EPSC_VIMMA_CTRL_SET_VFP_VHCA_DEREGISTER,
+ /* no DMA or DMA if multiple UFs */
+ EPSC_VIMMA_CTRL_SET_ADMIN_MODE,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_VIMMA_CTRL_OPCODE_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_vimma_ctrl_opcode [32 bits] */
+
+
+enum psif_epsc_vimma_admmode {
+ EPSC_VIMMA_CTRL_IB_ADM_MODE_SM_STANDARD,
+ /* VFP used as short for VM Fabric Profile */
+ EPSC_VIMMA_CTRL_IB_ADM_MODE_VM_FABRIC_PROFILE,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_VIMMA_ADMMODE_FIELD_MAX = 0xffff
+}; /* enum psif_epsc_vimma_admmode [16 bits] */
+
+/**
+ * For response structure to EPSC_PMA_COUNTERS Op.
+ * Common PMA counters for TSU and IBU layers.
+ */
+enum psif_epsc_csr_pma_counters_enum {
+ /** Regular counters - IB Spec chapter 16.1.3.5 */
+ EPSC_PMA_SYMBOL_ERR_CNTR = 0,
+ EPSC_PMA_LINK_ERR_RECOVERY_CNTR,
+ EPSC_PMA_LINK_DOWNED_CNTR,
+ EPSC_PMA_PORT_RCV_ERR,
+ EPSC_PMA_PORT_RCV_REMOTE_PHYSICAL_ERR,
+ EPSC_PMA_PORT_RCV_SWITCH_RELAY_ERR,
+ EPSC_PMA_PORT_XMIT_DISCARD,
+ EPSC_PMA_PORT_XMIT_CONSTRAINT_ERR,
+ EPSC_PMA_PORT_RCV_CONSTRAINT_ERR,
+ EPSC_PMA_LOCAL_LINK_INTEGRITY_ERR,
+ EPSC_PMA_EXCESS_BUFF_OVERRUN_ERR,
+ EPSC_PMA_VL15_DROPPED,
+ /** Extended counters if Extended Width supported Regular otherwise */
+ EPSC_PMA_PORT_XMIT_DATA,
+ EPSC_PMA_PORT_RCV_DATA,
+ EPSC_PMA_PORT_XMIT_PKTS,
+ EPSC_PMA_PORT_RCV_PKTS,
+ /**
+ * If ClassPortInfo:CapabilityMask.PortCountersXmitWaitSupported
+ * set to 1. IB Spec chapter 16.1.3.5
+ */
+ EPSC_PMA_PORT_XMIT_WAIT,
+ /** Strictly Extended counters - IB Spec Chapter 16.1.4.11 */
+ EPSC_PMA_PORT_UNICAST_XMIT_PKTS,
+ EPSC_PMA_PORT_UNICAST_RCV_PKTS,
+ EPSC_PMA_PORT_MULTICAST_XMIT_PKTS,
+ EPSC_PMA_PORT_MULTICAST_RCV_PKTS,
+ /* IB Spec Chapter 16.1.4.1 */
+ EPSC_PMA_PORT_LOCAL_PHYSICAL_ERR,
+ /* Keep this in End */
+ EPSC_PMA_COUNTERS_TOTAL,
+ /* Padding out to required bits allocated */
+ PSIF_EPSC_CSR_PMA_COUNTERS_ENUM_FIELD_MAX = 0x7fffffff
+}; /* enum psif_epsc_csr_pma_counters_enum [32 bits] */
+
+/**
+ * \brief PSIF atomic op requester config values.
+ * \details
+ * \par Width
+ * 2 bit
+ * \par Used in
+ * psif_epsc_csr_config member `atomic_support`
+ * \par Classification
+ * driver
+ */
+enum psif_epsc_csr_atomic_op {
+ /** PSIF requests atomic operations for IB and SQS. */
+ PSIF_PCIE_ATOMIC_OP_BOTH = 0,
+ /** PSIF requests atomic operations for IB. */
+ PSIF_PCIE_ATOMIC_OP_IB,
+ /** PSIF requests atomic operations for SQS. */
+ PSIF_PCIE_ATOMIC_OP_SQS,
+ /** PSIF doesn't request atomic operations. */
+ PSIF_PCIE_ATOMIC_OP_NONE
+}; /* enum psif_epsc_csr_atomic_op [ 2 bits] */
+
+/*
+ * Completion notification states. Could take any of these values:
+ * PSIF_CQ_UNARMED PSIF_CQ_ARMED_SE PSIF_CQ_ARMED_ALL PSIF_CQ_TRIGGERED
+ */
+enum psif_cq_state {
+ PSIF_CQ_UNARMED,
+ PSIF_CQ_ARMED_SE,
+ PSIF_CQ_ARMED_ALL,
+ PSIF_CQ_TRIGGERED
+}; /* enum psif_cq_state [ 2 bits] */
+
+/*
+ * This is an indication if the RSS hash was generated with port inputs or
+ * not.
+ */
+enum psif_rss_hash_source {
+ RSS_WITHOUT_PORT,
+ RSS_WITH_PORT
+}; /* enum psif_rss_hash_source [ 1 bits] */
+
+#if defined (HOST_LITTLE_ENDIAN)
+#include "psif_hw_data_le.h"
+#elif defined (HOST_BIG_ENDIAN)
+#include "psif_hw_data_be.h"
+#else
+#error "Could not determine byte order in psif_hw_data.h !?"
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _PSIF_HW_DATA_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_data_be.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,3512 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PSIF_HW_DATA_H_BE
+#define _PSIF_HW_DATA_H_BE
+
+/*
+ * Context used by tsu_mmu when performing address translation. The structure
+ * is follows: [63:56] st [55:55] no_snoop [54:53] tph [52:52] ro [51:12]
+ * table_ptr [11:11] th [10:8] translation_type [7:4] page_size [3:3]
+ * wr_access [2:0] table_level
+ */
+struct psif_mmu_cntx {
+ /* PCIe steering tag. */
+ u64 st:8;
+ /* PCIe no snoop. */
+ u64 ns:1;
+ /* PCIe TLP hints. */
+ u64 tph:2;
+ /* PCIe relaxed ordering. */
+ u64 ro:1;
+ /*
+ * This is bit [51:12] of the table pointer. The lower twelve bits are always
+ * set to zero. The pointer is pointing to a certain level in the page table
+ * structure. Only applicable if translation_type is set.
+ */
+ u64 table_ptr:40;
+ /* Indicates that the TPH field is valid for the PCIe request. */
+ u64 th:1;
+ /*
+ * Translation types supported by the PSIF MMU. The modes are:
+ * MMU_PASS_THROUGH MMU_GVA2GPA_MODE, MMU_EPSA_MODE, MMU_EPSC_MODE
+ */
+ enum psif_mmu_translation translation_type:3;
+
+ /* Different supported page sizes. */
+ enum psif_page_size page_size:4;
+
+ /* Set for write access. */
+ u64 wr_access:1;
+ /*
+ * XXX: Should this be enumerated? XXX: Make sure description is added when
+ * encoding is decided...
+ */
+ u64 table_level:3;
+} PSIF_PACKED_ALIGNED; /* struct psif_mmu_cntx [ 8 byte] */
+
+/* Descriptor for hardware updated portion of XRC receive queue. */
+struct psif_xrq_hw { /* Subjected to copy and convert */
+ /*
+ * Do not evict this entry if this bit is set. There can only be a fixed
+ * number of descriptors with this bit set. XXX: Should this be used as a
+ * hint, or should it be fixed?
+ */
+ u32 sticky:1;
+ /* This is a shared receive queue. This is always set for XRCSRQs. */
+ u32 srq:1;
+ /* The shared receive queue is in error. */
+ u32 srq_err:1;
+ /* Reserved */
+ u32 noname:1;
+ /* This is indicating how many scatter entries are valid. */
+ u32 scatter:4;
+ /* pd(24[0] bits)Protection domain. */
+ u32 pd:24;
+ /* This is the shift value to use to find start of the receive queue element. */
+ u32 extent_log2:4;
+ /*
+ * Hardware modified index pointing to the head of the receive queue. TSU is
+ * using this to find the address of the receive queue entry.
+ */
+ u32 head_indx:14;
+ /*
+ * If set to something greater than zero, event notification is armed. An
+ * Affiliated Synchronous Event will be sent when number of WQE are less than
+ * srq_lim.
+ */
+ u32 srq_lim:14;
+ /* Base address for the receive queue in host memory. */
+ u64 base_addr;
+ /* Inlined rq : struct psif_rq_no_pad (256 bits) */
+ struct psif_mmu_cntx mmu_cntx;
+ /*
+ * Log2 size of the receive queue. Maximum number of entries in the receive
+ * queue. This is used for calculating when to wrap the head and tail
+ * indexes.
+ */
+ u64 size_log2:4;
+ /*
+ * Pre-fetch threshold (clog2) indicating when to read the software portion
+ * of the descriptor. If there are less entries than indicated by this
+ * threshold, the software portion of the descriptor must be read.
+ */
+ u64 prefetch_threshold_log2:4;
+ /* The desciptor is valid. */
+ u64 valid:1;
+ /* Reserved */
+ u64 noname1:7;
+ /*
+ * XRC domain used to check if this descriptor can be used for the incoming
+ * packet.
+ */
+ u64 xrc_domain:24;
+ /* Completion queue to use for the incoming packet. */
+ u64 cqd_id:24;
+} PSIF_PACKED_ALIGNED; /* struct psif_xrq_hw [32 byte] */
+
+/* Temp.definition of Shared receive queue content */
+struct psif_xrq { /* Subjected to copy and convert */
+ /* Content pt. not defined in ASIC XML */
+ u64 something_tbd;
+} PSIF_PACKED_ALIGNED; /* struct psif_xrq [ 8 byte] */
+
+struct psif_vlan_union_struct {
+ /* VLAN priority. */
+ u32 vlan_pri:4;
+ /* Reserved */
+ u32 noname:20;
+} PSIF_PACKED; /* struct psif_vlan_union_struct [ 3 byte] */
+
+/*
+ * Union between the CQ descriptor ID and VLAN pri. The CQ desc id is only
+ * used for privileged requests, and the vlan_pri is only used for EoIB
+ * offloading.
+ */
+union psif_cq_desc_vlan_pri {
+ /*
+ * This is only used for privileged requests. Completion queue descriptor
+ * index where completions for privileged requests end up. This index points
+ * to the completion queue to be used with this work request.
+ */
+ u32 cqd_id:24;
+ /* VLAN priority. */
+ struct psif_vlan_union_struct vlan_pri;
+} PSIF_PACKED; /* union psif_cq_desc_vlan_pri [ 3 byte] */
+
+/*
+ * Generic header for work requests to PSIF. This is present for all packet
+ * types.
+ */
+struct psif_wr_common {
+ /* Indicates shat type of request this is. */
+ enum psif_wr_type op:8;
+
+ /*
+ * QP sending this request. XXX: Should name be own_qp_num as defined in QP
+ * state?
+ */
+ u32 local_qp:24;
+ /*
+ * The TSL (Tsu SL) must be matched against the TSL in the QP State (XXX: or
+ * in the AHA?). If it is unequal, the QP should be put in error.
+ */
+ u16 tsu_sl:4;
+ /* Port number to use for QP0/1 packets. This field is ignored if not QP0/1. */
+ enum psif_port port:1;
+
+ /* Only applicable to UD. This is an indication that AHA should be used. */
+ enum psif_use_ah ud_pkt:1;
+
+ /*
+ * High Bandwidth/Low Latency BAR. The QoSL must be matched against the QoSL
+ * in the QP State. If it is unequal, the QP should be in error.
+ */
+ enum psif_tsu_qos tsu_qosl:1;
+
+ /* Length (number of bytes of valid data in the collect payload buffer). */
+ u16 collect_length:9;
+ /*
+ * Send queue sequence number. Used to map request to a particular work
+ * request in the send queue.
+ */
+ u16 sq_seq;
+ /* Solicited event bit to be set in IB packet. */
+ u64 se:1;
+ /* Dynamic MTU is enabled for this work request. */
+ u64 dynamic_mtu_enable:1;
+ /* L3 checksum enabled when set. This is used for EoIB and IPoIB packets. */
+ u64 l3_checksum_en:1;
+ /* L4 checksum enabled when set. This is used for EoIB and IPoIB packets. */
+ u64 l4_checksum_en:1;
+ /* Number of SGL entries are valid for this request. */
+ u64 num_sgl:4;
+ /* UF used for DR loopback packets. This field is ignored otherwise. */
+ u64 destuf:6;
+ /* Reserved */
+ u64 noname:2;
+ /*
+ * EPS tag - used by EPS to associate process and work request. This field is
+ * not used by non-EPS work requests.
+ */
+ u64 eps_tag:16;
+ /* Completion notification identifier. */
+ u64 completion:1;
+ /* Fence indicator. */
+ u64 fence:1;
+ /* UF used for all EPS-C QP0/1 packets. This field is ignored otherwise. */
+ u64 srcuf:6;
+ /* Union between VLAN priority and CQ descriptor ID. */
+ union psif_cq_desc_vlan_pri cq_desc_vlan_pri_union;
+ /*
+ * Checksum used for data protection and consistency between work request and
+ * QP state.
+ */
+ u32 checksum;
+ /* Info: Edge padding added (for endian convert) */
+ u32 space19;
+} PSIF_PACKED_ALIGNED; /* struct psif_wr_common [24 byte] */
+
+struct psif_wr_qp {
+ /* Reserved */
+ u32 noname:8;
+ /* QP number for the remote node. */
+ u32 remote_qp:24;
+ /* Q-Key for the remote node. */
+ u32 qkey;
+} PSIF_PACKED_ALIGNED; /* struct psif_wr_qp [ 8 byte] */
+
+/* Local address structure. */
+struct psif_wr_local {
+ /* Host address. */
+ u64 addr;
+ /* Local key used to validate the memory region this address is pointing to. */
+ u32 lkey;
+ /* This is the total length of the message. */
+ u32 length;
+} PSIF_PACKED_ALIGNED; /* struct psif_wr_local [16 byte] */
+
+struct psif_wr_addr {
+ /* Reserved */
+ u32 noname:8;
+ /* Index into the Address Handle Array. */
+ u32 ah_indx:24;
+} PSIF_PACKED; /* struct psif_wr_addr [ 4 byte] */
+
+/*
+ * This header is used for IB send operations. The header is a union and
+ * consists of either a connected mode header or a datagram mode header. The
+ * following opcodes are using this header: PSIF_WR_SEND PSIF_WR_SEND_IMM
+ * PSIF_WR_SPECIAL_QP_SEND PSIF_WR_QP0_SEND_DR_XMIT
+ * PSIF_WR_QP0_SEND_DR_LOOPBACK PSIF_WR_EPS_SPECIAL_QP_SEND
+ * PSIF_WR_EPS_QP0_SEND_DR_XMIT PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK PSIF_WR_LSO
+ */
+struct psif_wr_send_header_ud {
+ struct psif_wr_qp qp;
+ struct psif_wr_local local_addr;
+ /* Header used for IB send commands using UD mode. */
+ /* Inlined ud : struct psif_wr_ud_send (224 bits) */
+ struct psif_wr_addr remote_addr;
+ /* Reserved */
+ u32 noname:18;
+ /*
+ * Max segment size used for PSIF_WR_LSO. This field is not used for other
+ * operations.
+ */
+ u32 mss:14;
+} PSIF_PACKED_ALIGNED; /* struct psif_wr_send_header_ud [32 byte] */
+
+/*
+ * This header is used for IB send operations. The header is a union and
+ * consists of either a connected mode header or a datagram mode header. The
+ * following opcodes are using this header: PSIF_WR_SEND PSIF_WR_SEND_IMM
+ * PSIF_WR_SPECIAL_QP_SEND PSIF_WR_QP0_SEND_DR_XMIT
+ * PSIF_WR_QP0_SEND_DR_LOOPBACK PSIF_WR_EPS_SPECIAL_QP_SEND
+ * PSIF_WR_EPS_QP0_SEND_DR_XMIT PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK PSIF_WR_LSO
+ */
+struct psif_wr_send_header_uc_rc_xrc {
+ struct psif_wr_local local_addr;
+ /*
+ * Reserved. XXX: FIX ME - calculation of this field based on constant, not
+ * psif_wr_local_address_header as it should.
+ */
+ u32 reserved10[3];
+ /* Header used with IB send commands using connected mode. */
+ /* Inlined uc_rc_xrc : struct psif_wr_cm (224 bits) */
+ /* Reserved */
+ u32 noname:18;
+ /*
+ * Max segment size used for PSIF_WR_LSO. This field is not used for other
+ * operations.
+ */
+ u32 mss:14;
+} PSIF_PACKED_ALIGNED; /* struct psif_wr_send_header_uc_rc_xrc [32 byte] */
+
+/*
+ * This header is used for IB send operations. The header is a union and
+ * consists of either a connected mode header or a datagram mode header. The
+ * following opcodes are using this header: PSIF_WR_SEND PSIF_WR_SEND_IMM
+ * PSIF_WR_SPECIAL_QP_SEND PSIF_WR_QP0_SEND_DR_XMIT
+ * PSIF_WR_QP0_SEND_DR_LOOPBACK PSIF_WR_EPS_SPECIAL_QP_SEND
+ * PSIF_WR_EPS_QP0_SEND_DR_XMIT PSIF_WR_EPS_QP0_SEND_DR_LOOPBACK PSIF_WR_LSO
+ */
+union psif_wr_send_header {
+ /* Header used for IB send commands using UD mode. */
+ struct psif_wr_send_header_ud ud;
+ /* Header used with IB send commands using connected mode. */
+ struct psif_wr_send_header_uc_rc_xrc uc_rc_xrc;
+} PSIF_PACKED; /* union psif_wr_send_header [32 byte] */
+
+/* Remote address structure. */
+struct psif_wr_remote {
+ /* Address to the remote side. */
+ u64 addr;
+ /*
+ * Remote key used to validate the memory region the associated address is
+ * pointing to.
+ */
+ u32 rkey;
+ /* For RDMA and DM this is the length to add to dmalen in RETH of IB packet. */
+ u32 length;
+} PSIF_PACKED_ALIGNED; /* struct psif_wr_remote [16 byte] */
+
+/*
+ * This header is used for RDMA type operations. The following opcodes are
+ * using this header: PSIF_WR_RDMA_WR PSIF_WR_RDMA_WR_IMM PSIF_WR_RDMA_RD
+ * PSIF_WR_CMP_SWAP PSIF_WR_FETCH_ADD PSIF_WR_MASK_CMP_SWAP
+ * PSIF_WR_MASK_FETCH_ADD
+ */
+struct psif_wr_rdma {
+ struct psif_wr_local local_addr;
+ struct psif_wr_remote remote_addr;
+} PSIF_PACKED_ALIGNED; /* struct psif_wr_rdma [32 byte] */
+
+/* Send completion ID. */
+struct psif_send_completion_id {
+ /*
+ * Completion queue sequence number for the completion queue being re-armed.
+ * This is going into the completion for the privileged request.
+ */
+ u32 sequence_number;
+ /*
+ * Send queue sequence number. This is used to map the completion back to a
+ * request in the send queue.
+ */
+ u16 sq_seq_num;
+ /*
+ * This field is only valid for ring buffer send completions (proxy type send
+ * requests). In all other cases this field is ignored.
+ */
+ u16 eps_tag;
+} PSIF_PACKED_ALIGNED; /* struct psif_send_completion_id [ 8 byte] */
+
+/* Event completion ID. */
+struct psif_event_completion_id {
+ /* Reserved */
+ u64 noname:40;
+ /* Completion queue descriptor ID which is the source of the event. */
+ u64 cq_id:24;
+} PSIF_PACKED_ALIGNED; /* struct psif_event_completion_id [ 8 byte] */
+
+/* Union containing a send or receive completion ID. */
+union psif_completion_wc_id {
+ /*
+ * Receive Queue completion ID. This is the receive queue entry ID found as
+ * part of receive queue entry.
+ */
+ u64 rq_id;
+ /*
+ * Send Queue completion ID. This contain the send queue sequence number. In
+ * ring buffer send completions this field also conatain a valid EPS tag.
+ */
+ struct psif_send_completion_id sq_id;
+ /* Completion queue descriptor ID which is the source of the event. */
+ struct psif_event_completion_id ecq_id;
+} PSIF_PACKED; /* union psif_completion_wc_id [ 8 byte] */
+
+/*
+ * Union used for descriptor types used when operations on the descriptors
+ * themselves are done, like invalidation, resizing etc. It can the take the
+ * follwing types: rq_id xrq_id cq_id target_qp
+ */
+union psif_descriptor_union {
+ /*
+ * Receive queue descriptor used for the following request:
+ * PSIF_WR_SET_SRQ_LIM: this is the receive queue to set the new limit for.
+ * PSIF_WR_INVALIDATE_RQ: this is the receive queue to invalidate/flush from
+ * the descriptor cache.
+ */
+ u32 rq_id:24;
+ /*
+ * XRCSRQ descriptor used for the following request: PSIF_WR_SET_XRCSRQ_LIM:
+ * this is the XRCSRQ to set the new limit for. PSIF_WR_INVALIDATE_XRCSRQ:
+ * this is the XRCSRQ to invalidate/flush from the descriptor cache.
+ */
+ u32 xrq_id:24;
+ /*
+ * Completion queue descriptor ID used when operations are done on the CQ
+ * descriptor, no completion is sent to this CQ. This field is valid for
+ * PSIF_WR_INVALIDATE_CQ, PSIF_WR_RESIZE_CQ, PSIF_WR_REQ_CMPL_NOTIFY,
+ * PSIF_WR_CMPL_NOTIFY_RCVD, PSIF_WR_REARM_CMPL_EVENT.
+ */
+ u32 cq_id:24;
+ /*
+ * Target QP for PSIF_WR_INVALIDATE_SGL_CACHE command. This field is also
+ * valid for PSIF_WR_GENERATE_COMPLETION, then this is the QP number put in
+ * the completion.
+ */
+ u32 target_qp:24;
+} PSIF_PACKED; /* union psif_descriptor_union [ 3 byte] */
+
+/*
+ * This header is used for privileged operations. The following opcodes are
+ * using this header: PSIF_WR_INVALIDATE_LKEY PSIF_WR_INVALIDATE_RKEY
+ * PSIF_WR_INVALIDATE_BOTH_KEYS PSIF_WR_INVALIDATE_TLB PSIF_WR_RESIZE_CQ
+ * PSIF_WR_SET_SRQ_LIM PSIF_WR_SET_XRCSRQ_LIM PSIF_WR_REQ_CMPL_NOTIFY
+ * PSIF_WR_CMPL_NOTIFY_RCVD PSIF_WR_REARM_CMPL_EVENT
+ * PSIF_WR_GENERATE_COMPLETION PSIF_WR_INVALIDATE_RQ PSIF_WR_INVALIDATE_CQ
+ * PSIF_WR_INVALIDATE_XRCSRQ PSIF_WR_INVALIDATE_SGL_CACHE
+ */
+struct psif_wr_su {
+ /* PSIF_WR_GENERATE_COMPLETION: This is the WC ID to put in the completion. */
+ union psif_completion_wc_id wc_id;
+ /*
+ * PSIF_WR_INVALIDATE_TLB: this is the address vector to invalidate in the
+ * TLB. PSIF_WR_RESIZE_CQ: this is the new address of the CQ.
+ */
+ u64 addr;
+ /*
+ * PSIF_WR_INVALIDATE_LKEY: key to invalidate/flush from the DMA VT cache.
+ * PSIF_WR_INVALIDATE_RKEY: key to invalidate/flush from the DMA VT cache.
+ * PSIF_WR_INVALIDATE_BOTH_KEYS: key to invalidate/flush from the DMA VT
+ * cache. PSIF_WR_INVALIDATE_TLB: this is the address vector to invalidate in
+ * the TLB.
+ */
+ u32 key;
+ /*
+ * PSIF_WR_INVALIDATE_TLB: this is the length for invalidate in the TLB. Only
+ * the lower 16 bits are valid for specifying length of TLB invalidation.
+ * PSIF_WR_RESIZE_CQ: this is the new length of the CQ.
+ */
+ u32 length;
+ /* This is used by the PSIF_WR_SET_SRQ_LIM request. */
+ u64 srq_lim:14;
+ /* Reserved */
+ u64 noname:10;
+ /*
+ * This field is valid for PSIF_WR_GENERATE_COMPLETION. This is the opcode
+ * going into the completion.
+ */
+ enum psif_wc_opcode completion_opcode:8;
+
+ /*
+ * This field is valid for PSIF_WR_GENERATE_COMPLETION. This is the
+ * completion status to put in the completion.
+ */
+ enum psif_wc_status completion_status:8;
+
+ union psif_descriptor_union u2;
+} PSIF_PACKED_ALIGNED; /* struct psif_wr_su [32 byte] */
+
+/* SEND RDMA DM ATOMIC or PRIVILEGED data - depending on opcode. */
+union psif_wr_details {
+ union psif_wr_send_header send;
+ struct psif_wr_rdma rdma;
+ struct psif_wr_rdma atomic;
+ struct psif_wr_su su;
+} PSIF_PACKED; /* union psif_wr_details [32 byte] */
+
+struct psif_wr_xrc {
+ /* Reserved */
+ u32 noname:8;
+ /* Descriptor index for XRC SRQ. */
+ u32 xrqd_id:24;
+} PSIF_PACKED; /* struct psif_wr_xrc [ 4 byte] */
+
+/* PSIF work request. */
+struct psif_wr { /* Subjected to copy and convert */
+ /* Indicates shat type of request this is. */
+ enum psif_wr_type op:8;
+
+ /*
+ * QP sending this request. XXX: Should name be own_qp_num as defined in QP
+ * state?
+ */
+ u32 local_qp:24;
+ /*
+ * The TSL (Tsu SL) must be matched against the TSL in the QP State (XXX: or
+ * in the AHA?). If it is unequal, the QP should be put in error.
+ */
+ u16 tsu_sl:4;
+ /* Port number to use for QP0/1 packets. This field is ignored if not QP0/1. */
+ enum psif_port port:1;
+
+ /* Only applicable to UD. This is an indication that AHA should be used. */
+ enum psif_use_ah ud_pkt:1;
+
+ /*
+ * High Bandwidth/Low Latency BAR. The QoSL must be matched against the QoSL
+ * in the QP State. If it is unequal, the QP should be in error.
+ */
+ enum psif_tsu_qos tsu_qosl:1;
+
+ /* Length (number of bytes of valid data in the collect payload buffer). */
+ u16 collect_length:9;
+ /*
+ * Send queue sequence number. Used to map request to a particular work
+ * request in the send queue.
+ */
+ u16 sq_seq;
+ /* Solicited event bit to be set in IB packet. */
+ u64 se:1;
+ /* Dynamic MTU is enabled for this work request. */
+ u64 dynamic_mtu_enable:1;
+ /* L3 checksum enabled when set. This is used for EoIB and IPoIB packets. */
+ u64 l3_checksum_en:1;
+ /* L4 checksum enabled when set. This is used for EoIB and IPoIB packets. */
+ u64 l4_checksum_en:1;
+ /* Number of SGL entries are valid for this request. */
+ u64 num_sgl:4;
+ /* UF used for DR loopback packets. This field is ignored otherwise. */
+ u64 destuf:6;
+ /* Reserved */
+ u64 noname:2;
+ /*
+ * EPS tag - used by EPS to associate process and work request. This field is
+ * not used by non-EPS work requests.
+ */
+ u64 eps_tag:16;
+ /* Completion notification identifier. */
+ u64 completion:1;
+ /* Fence indicator. */
+ u64 fence:1;
+ /* UF used for all EPS-C QP0/1 packets. This field is ignored otherwise. */
+ u64 srcuf:6;
+ /* Union between VLAN priority and CQ descriptor ID. */
+ union psif_cq_desc_vlan_pri cq_desc_vlan_pri_union;
+ /* Inlined common : struct psif_wr_common (192 bits) */
+ /*
+ * Checksum used for data protection and consistency between work request and
+ * QP state.
+ */
+ u32 checksum;
+ /* Immediate data is only valid when indicated by the opcode. */
+ u64 imm:32;
+ union psif_wr_details details;
+ struct psif_wr_xrc xrc_hdr;
+ /* Manually added spacing to pad out wr */
+ u32 space20;
+} PSIF_PACKED_ALIGNED; /* struct psif_wr [64 byte] */
+
+/** \brief Table of TSU SL and QoS mappings
+ * \details
+ * Driver queries EPS-C for mapping of privileged QP and Infinband SL to
+ * TSU SL and QoS. These values then need to be applied in QP and WR
+ * as well as selecting hi or low PCIe BAR VCB (tqos) to obtain PSIF TSU
+ * internal traffic separation.
+ */
+struct psif_tsl_map {
+ /* PSIF TSU SL assignmnet */
+ u16 m7_tsl:4;
+ u16 noname:2;
+ /* PSIF TSU QoS selection */
+ enum psif_tsu_qos m7_tqos:1;
+
+ u16 noname1:1;
+ /* Inlined m6 : struct psif_tsl_map_entry (8 bits) */
+ /* PSIF TSU SL assignmnet */
+ u16 m6_tsl:4;
+ u16 noname2:2;
+ /* PSIF TSU QoS selection */
+ enum psif_tsu_qos m6_tqos:1;
+
+ u16 noname3:1;
+ /* Inlined m5 : struct psif_tsl_map_entry (8 bits) */
+ /* PSIF TSU SL assignmnet */
+ u16 m5_tsl:4;
+ u16 noname4:2;
+ /* PSIF TSU QoS selection */
+ enum psif_tsu_qos m5_tqos:1;
+
+ u16 noname5:1;
+ /* Inlined m4 : struct psif_tsl_map_entry (8 bits) */
+ /* PSIF TSU SL assignmnet */
+ u16 m4_tsl:4;
+ u16 noname6:2;
+ /* PSIF TSU QoS selection */
+ enum psif_tsu_qos m4_tqos:1;
+
+ u16 noname7:1;
+ /* Inlined m3 : struct psif_tsl_map_entry (8 bits) */
+ /* PSIF TSU SL assignmnet */
+ u16 m3_tsl:4;
+ u16 noname8:2;
+ /* PSIF TSU QoS selection */
+ enum psif_tsu_qos m3_tqos:1;
+
+ u16 noname9:1;
+ /* Inlined m2 : struct psif_tsl_map_entry (8 bits) */
+ /* PSIF TSU SL assignmnet */
+ u16 m2_tsl:4;
+ u16 noname10:2;
+ /* PSIF TSU QoS selection */
+ enum psif_tsu_qos m2_tqos:1;
+
+ u16 noname11:1;
+ /* Inlined m1 : struct psif_tsl_map_entry (8 bits) */
+ /* PSIF TSU SL assignmnet */
+ u16 m1_tsl:4;
+ u16 noname12:2;
+ /* PSIF TSU QoS selection */
+ enum psif_tsu_qos m1_tqos:1;
+
+ u16 noname13:1;
+ /* Inlined m0 : struct psif_tsl_map_entry (8 bits) */
+ /* PSIF TSU SL assignmnet */
+ u16 m0_tsl:4;
+ u16 noname14:2;
+ /* PSIF TSU QoS selection */
+ enum psif_tsu_qos m0_tqos:1;
+
+ u16 noname15:1;
+ /* Inlined m7 : struct psif_tsl_map_entry (8 bits) */
+} PSIF_PACKED_ALIGNED; /* struct psif_tsl_map [ 8 byte] */
+
+/* Hardware structure indicating what is the next QP. */
+struct psif_next {
+ /* QP number for the next QP to be processed. */
+ u32 next_qp_num:24;
+ /*
+ * If all high, the next pointer is null. If next_null == 1, it is transport
+ * timer on evicted QP
+ */
+ u32 next_null:8;
+} PSIF_PACKED; /* struct psif_next [ 4 byte] */
+
+/* Response (ACK) data structure used by the response queue descriptor. */
+struct psif_rspq_ack_data {
+ enum ib_opcode opcode:8;
+
+ /* ib_bth_psn(24[0] bits)Packet Sequence Number */
+ u32 psn:24;
+ /* ib_aeth_syndrome(8[0] bits)Syndrome */
+ u32 syndrome:8;
+ /* ib_aeth_msn(24[0] bits)Message Sequence Number */
+ u32 msn:24;
+} PSIF_PACKED_ALIGNED; /* struct psif_rspq_ack_data [ 8 byte] */
+
+/* Response descriptor structure used by the response queue descriptor. */
+struct psif_rspq_rsp_descriptor {
+ /* QP and UF to be processed next. */
+ struct psif_next rspq_next;
+ u32 rspq_done:1;
+ u32 head_dup_ack:1;
+ u32 head_ack:1;
+ /* resp_sched_sched_ptr(5[0] bits) * Write pointer type to rdma read and atomic data stored in reqsponse queue
+ * descriptor. Every time an rdma read and atomic is performed, this pointer
+ * is incremented.
+ */
+ u32 head_sched_ptr:5;
+ /* ib_bth_psn(24[0] bits)Packet Sequence Number */
+ u32 head_count_sched:24;
+ struct psif_rspq_ack_data tail_ack_aeth;
+ /* Reserved */
+ u64 noname:6;
+ /*
+ * This bit is set through the doorbell. SW should initialize this bit to 0
+ * when the QP is setup and check this bit plus psif_next = null to ensure SW
+ * can own the RSPQ descriptor
+ */
+ u64 destroyed:1;
+ u64 tail_ack:1;
+ /* Reserved */
+ u64 noname1:3;
+ /* resp_sched_sched_ptr(5[0] bits) * Write pointer type to rdma read and atomic data stored in reqsponse queue
+ * descriptor. Every time an rdma read and atomic is performed, this pointer
+ * is incremented.
+ */
+ u64 tail_sched_ptr:5;
+ /* ib_bth_psn(24[0] bits)Packet Sequence Number */
+ u64 tail_count_sched:24;
+ /* Reserved */
+ u64 noname2:7;
+ u64 tail_dup_ack:1;
+ /* Inlining rspq_ack_data_t tail_dup_ack_aeth due to bondary violation */
+ enum ib_opcode opcode:8;
+
+ /* psn divided in two to mitigate for 64 bit bondary crossing */
+ u16 psn_0_7:8;
+ u64 psn_8_23:16;
+ /* ib_aeth_syndrome(8[0] bits)Syndrome */
+ u64 syndrome:8;
+ /* ib_aeth_msn(24[0] bits)Message Sequence Number */
+ u64 msn:24;
+ /* Reserved */
+ u64 noname3:16;
+} PSIF_PACKED_ALIGNED; /* struct psif_rspq_rsp_descriptor [32 byte] */
+
+/* Temp.definition of content */
+struct psif_sq_tvl {
+ /* Content pt. not defined in ASIC XML */
+ u64 something_tbd[2];
+} PSIF_PACKED_ALIGNED; /* struct psif_sq_tvl [16 byte] */
+
+/* This is the portion of the descriptor which is updated by software. */
+struct psif_sq_sw { /* Subjected to copy and convert */
+ /* Reserved */
+ u16 noname:16;
+ /*
+ * Index to where elements are added to the send queue by SW. SW is
+ * responsibel for keeping track of how many entries there are in the send
+ * queue. I.e. SW needs to keep track of the head_index so it doesn't
+ * overwrite entries in the send queue which is not yet completed.
+ */
+ u16 tail_indx;
+ /* Info: Edge padding added (for endian convert) */
+ u32 space21;
+} PSIF_PACKED_ALIGNED; /* struct psif_sq_sw [ 8 byte] */
+
+/* Temp.definition of content */
+struct psif_sq_rspq {
+ /* Content pt. not defined in ASIC XML */
+ u64 something_tbd[52];
+} PSIF_PACKED_ALIGNED; /* struct psif_sq_rspq [416 byte] */
+
+/* Descriptor used by the send queue scheduler to operate on the send queue. */
+struct psif_sq_hw { /* Subjected to copy and convert */
+ /* QP and UF to be processed next. */
+ struct psif_next sq_next;
+ /*
+ * Send queue sequence number used by the SQS to maintain ordering and keep
+ * track of where which send queue elements to fetch. This field is not in
+ * sync with the field in qp_t. This number is typically a little bit before
+ * the number in the qp_t as SQS has to fetch the elements from host memory.
+ * This is also used as tail_index when checking if there are more elements
+ * in the send queue.
+ */
+ u16 last_seq;
+ u16 u_1;
+ u32 u_2;
+ /* Reserved */
+ u32 noname:4;
+ /*
+ * This bit is set through the doorbell. SW should check this bit plus
+ * psif_next = null to ensure SW can own the SQ descriptor.
+ */
+ u32 destroyed:1;
+ /*
+ * Done[0] is set when the last SQ WR is processed (sq_sequence_number ==
+ * tail_indx). When done[0] is set, SQS only process the SQ WR when
+ * sq_sequence_number != tail_index. Done[1] is set when done[0] is set and
+ * sq_sequence_number == tail_index.
+ */
+ u32 sq_done:2;
+ /*
+ * Timestamp qualifier. This bit is set when retry is entered to the queue
+ * and clear when the timestamp has expired.
+ */
+ u32 sq_timestamp_valid:1;
+ /*
+ * Indication if this QP is configured as a low latency or high throughput
+ * quality of service level.
+ */
+ u32 qos:1;
+ /*
+ * The size between each work queue element in the send queue. This is the
+ * shift value to use in order to find the start of a work queue element.
+ */
+ u32 extent_log2:5;
+ /* Maximum number of SGEs supported by this send queue. */
+ u32 sq_max_sge:5;
+ /* Maximum number of SGEs supported by this send queue. */
+ u32 size_log2:4;
+ /* Maximum inline data length supported by this send queue. */
+ u32 sq_max_inline:9;
+ /* The base address to the send queue. */
+ u64 base_addr;
+ /* The MMU context used to get the send queue. */
+ struct psif_mmu_cntx mmu_cntx;
+} PSIF_PACKED_ALIGNED; /* struct psif_sq_hw [32 byte] */
+
+/* Temp.definition of Send queue content */
+struct psif_sq_entry { /* Subjected to copy and convert */
+ /* Content pt. not defined in ASIC XML */
+ struct psif_wr wr;
+ u64 payload[32];
+} PSIF_PACKED_ALIGNED; /* struct psif_sq_entry [320 byte] */
+
+/**
+ * SQS ring buffer entry
+ */
+struct psif_sq_ring {
+ u64 something;
+} PSIF_PACKED_ALIGNED; /* struct psif_sq_ring [ 8 byte] */
+
+/* Temp.definition of the send queue entry cache for the completion block
+ * The only info used by the driver is the size of this struct,
+ * when allocating space for the cache in memory:
+ */
+struct psif_sq_cmpl {
+ /* Content pt. not defined in ASIC XML */
+ u64 payload[8];
+} PSIF_PACKED_ALIGNED; /* struct psif_sq_cmpl [64 byte] */
+
+/* Recveive queue scatter entry. */
+struct psif_rq_scatter {
+ /* Base address for this scatter element. */
+ u64 base_addr;
+ /* Length of scatter element. */
+ u32 length;
+ /* L-Key to be used for this scatter element. */
+ u32 lkey;
+} PSIF_PACKED_ALIGNED; /* struct psif_rq_scatter [16 byte] */
+
+/* Data type for TSU_RQH_QP_BASE_ADDR - rq scratch pad
+ * Layout as defined by struct psif_rq_entry
+ */
+struct psif_rqsp {
+ /*
+ * Receive queue entry ID. This is added to the receive completion using this
+ * receive queue entry.
+ */
+ u64 rqe_id;
+ /* Scatter entries for this receive queue element. */
+ struct psif_rq_scatter scatter[16];
+} PSIF_PACKED_ALIGNED; /* struct psif_rqsp [264 byte] */
+
+/* This is the part of the descriptor which is updated by SW (user space). */
+struct psif_rq_sw { /* Subjected to copy and convert */
+ /* Reserved */
+ u32 noname:18;
+ /* Software modified index pointing to the tail reecive entry in host memory. */
+ u32 tail_indx:14;
+ /* Info: Edge padding added (for endian convert) */
+ u32 space22;
+} PSIF_PACKED_ALIGNED; /* struct psif_rq_sw [ 8 byte] */
+
+struct psif_rq_hw { /* Subjected to copy and convert */
+ /*
+ * Do not evict this entry if this bit is set. There can only be a fixed
+ * number of descriptors with this bit set. XXX: Should this be used as a
+ * hint, or should it be fixed?
+ */
+ u32 sticky:1;
+ /* This is a shared receive queue. This is always set for XRCSRQs. */
+ u32 srq:1;
+ /* The shared receive queue is in error. */
+ u32 srq_err:1;
+ /* Reserved */
+ u32 noname:1;
+ /* This is indicating how many scatter entries are valid. */
+ u32 scatter:4;
+ /* pd(24[0] bits)Protection domain. */
+ u32 pd:24;
+ /* This is the shift value to use to find start of the receive queue element. */
+ u32 extent_log2:4;
+ /*
+ * Hardware modified index pointing to the head of the receive queue. TSU is
+ * using this to find the address of the receive queue entry.
+ */
+ u32 head_indx:14;
+ /*
+ * If set to something greater than zero, event notification is armed. An
+ * Affiliated Synchronous Event will be sent when number of WQE are less than
+ * srq_lim.
+ */
+ u32 srq_lim:14;
+ /* Base address for the receive queue in host memory. */
+ u64 base_addr;
+ /* Hardware updated portion of descriptor. */
+ /* Inlined hw_no_pad : struct psif_rq_no_pad (256 bits) */
+ struct psif_mmu_cntx mmu_cntx;
+ /*
+ * Log2 size of the receive queue. Maximum number of entries in the receive
+ * queue. This is used for calculating when to wrap the head and tail
+ * indexes.
+ */
+ u64 size_log2:4;
+ /*
+ * Pre-fetch threshold (clog2) indicating when to read the software portion
+ * of the descriptor. If there are less entries than indicated by this
+ * threshold, the software portion of the descriptor must be read.
+ */
+ u64 prefetch_threshold_log2:4;
+ /* The desciptor is valid. */
+ u64 valid:1;
+ /* Reserved */
+ u64 noname1:55;
+} PSIF_PACKED_ALIGNED; /* struct psif_rq_hw [32 byte] */
+
+/* A receive queue entry structure contianing scatter entries. */
+struct psif_rq_entry { /* Subjected to copy and convert */
+ /*
+ * Receive queue entry ID. This is added to the receive completion using this
+ * receive queue entry.
+ */
+ u64 rqe_id;
+ /* Scatter entries for this receive queue element. */
+ struct psif_rq_scatter scatter[16];
+} PSIF_PACKED_ALIGNED; /* struct psif_rq_entry [264 byte] */
+
+/* This is the portion of the descriptor which is updated by software. */
+struct psif_rb_sw { /* Subjected to copy and convert */
+ /* Index to ring buffer elements added by SW. */
+ u32 head_indx;
+ /* Info: Edge padding added (for endian convert) */
+ u32 space23;
+} PSIF_PACKED_ALIGNED; /* struct psif_rb_sw [ 8 byte] */
+
+/*
+ * Descriptor entry for a ring buffer. This entry is used to address into the
+ * ring buffer and write the correct entries. This structure is the hardware
+ * updateable part of the RB descriptor.
+ */
+struct psif_rb_hw { /* Subjected to copy and convert */
+ /* Do not evict this entry if this bit is set. */
+ u32 sticky:1;
+ /*
+ * This functionality is not valid unless armed is set. If set and incoming
+ * message has SE bit set, an event should be generated to the event queue
+ * indicated by eventq_dscr_id. If not set, an event is sent reqardless of
+ * the value of the SE bit in the incoming message.
+ */
+ u32 filter_se:1;
+ /*
+ * When this bit is set, the solicited bit is used in order to send events to
+ * event queues.
+ */
+ u32 armed:1;
+ /* The descriptor is valid. */
+ u32 valid:1;
+ /* rb_size_log2(5[0] bits)Log2 size of the ring buffer. */
+ u32 max_size_log2:5;
+ /* Reserved */
+ u32 noname:11;
+ /*
+ * Interrupt channel associated with the event queue. In the PSIF design the
+ * event queues are one to one with interrupt channel.
+ */
+ u32 int_channel:7;
+ /*
+ * Log2 size of the ring buffer. The entries are specified as 64B entities.
+ * The number indicates when the tail_index should wrap. If one message is
+ * running over the edge, the message is stored in consecutive entries
+ * outside the ring buffer. max_message_size additional space is added to the
+ * edge of the buffer.
+ */
+ u32 size_log2:5;
+ /* Index to ring buffer elements to be consumed by HW. */
+ u32 tail_indx;
+ struct psif_mmu_cntx mmu_cntx;
+ /*
+ * VA or PA of the base of the completion queue. If PA the MMU context above
+ * will be a bypass context. Updated by software. The head and tail pointers
+ * can be calculated by the following calculations: Address = base_ptr +
+ * (head * 64B ) Head Pointer and Tail Pointer will use the same MMU context
+ * as the base, and all need to be VA from one address space, or all need to
+ * be PA. In typical use, to allow direct user access to the head and tail
+ * pointer VAs are used.
+ */
+ u64 base_addr;
+ /* Reserved */
+ u32 noname1:3;
+ /*
+ * Pre-fetch threshold (clog2) indicating when to read the software portion
+ * of the descriptor. If there are less entries than indicated by this
+ * threshold, the software portion of the descriptor must be read.
+ */
+ u32 prefetch_threshold_log2:5;
+ /* pd(24[0] bits)Protection domain. */
+ u32 pd:24;
+ /* XXX: should this be defined as rb_sequence_number_t? */
+ u32 sequence_number;
+} PSIF_PACKED_ALIGNED; /* struct psif_rb_hw [32 byte] */
+
+/*
+ * Ring buffer header. A ring buffer header is preceding payload data when
+ * written to host memory. The full message with RB header and payload data
+ * is padded out to become a multiple of 64 bytes. The last 4 bytes of every
+ * 64B data written, will contain the ring buffer sequence number.
+ */
+struct psif_rb_entry { /* Subjected to copy and convert */
+ /*
+ * Defining the packet type the headers valid for this ring buffer.
+ * PSIF_RB_TYPE_INVALID PSIF_RB_TYPE_DM_PUT PSIF_RB_TYPE_DM_GET_RESP
+ * PSIF_RB_TYPE_RCV_PROXY_COMPLETION
+ * PSIF_RB_TYPE_RCV_PROXY_COMPLETION_AND_DATA
+ * PSIF_RB_TYPE_SEND_PROXY_COMPLETION PSIF_RB_TYPE_SEND_COMPLETION
+ */
+ enum psif_rb_type pkt_type:3;
+
+ /* Reserved */
+ u32 noname:3;
+ /* Applicable only if this is for EPS-A. */
+ enum psif_eps_a_core eps_a_core:2;
+
+ /* ib_bth_qp_number(24[0] bits)Queue Pair */
+ u32 qp_num:24;
+ /* Length of data associated with this ring buffer header. */
+ u32 byte_len;
+ /* Payload bulk */
+ u64 payload[6];
+ /* Payload last */
+ u32 payload_tail;
+ /* sequence number for sanity checking */
+ u32 seq_num;
+} PSIF_PACKED_ALIGNED; /* struct psif_rb_entry [64 byte] */
+
+/*
+ * QP state information as laid out in system memory. This structure should
+ * be used to cast the state information stored to a register.
+ */
+struct psif_qp_core { /* Subjected to copy and convert */
+ /*
+ * If set, this QP will not be evicted unless QP state is filled up by QPs
+ * with this bit set.
+ */
+ u32 do_not_evict:1;
+ /*
+ * When 1, indicates that the receive queue of this QP is a shared receive
+ * queue. This bit is used by tsu_err to classify errors.
+ */
+ u32 rq_is_srq:1;
+ /* Bit used internally in tsu_cmpl. */
+ u32 first_at_floor_seen:1;
+ /*
+ * Indication that a receive queue access is in progress. The bit is set on a
+ * Send First packet and cleared on a Send Last packet. It is used to
+ * indicate if there exists an RQ which can be re-used in the case of UC
+ * transport packet drop.
+ */
+ u32 dscr_rq_in_progress:1;
+ /*
+ * This is a multicast QP, and is creating UC multicasts. The is_multicast
+ * bit is based on the destination QP being the multicast QP number
+ * (0xffffff). When the QP is not a UD QP, this bit is forwarded to DMA as
+ * the is_multicast bit.
+ */
+ u32 is_multicast:1;
+ /*
+ * Current number of retired read or atomic requests. Initialze to zero.
+ * Updated by tsu_cmpl every time a read or atomic request is completed.
+ */
+ u32 current_retired:5;
+ /*
+ * Current number of outstanding read or atomic requests. Intialize to zero.
+ * It is updated by tsu_rqs every time a new read or atomic requests is
+ * transmitted.
+ */
+ u32 current_outstanding:5;
+ /* The size (log2 number of entries) of the send queue. */
+ u32 sq_clog2_size:4;
+ /* Send queue extent - the clog2 size between the work requests. */
+ u32 sq_clog2_extent:5;
+ /* A hit in the set locally spun out of tsu_cmpl is found. */
+ u32 spin_hit:1;
+ /*
+ * When 1, indicates that the receive queue of this QP is a shared receive
+ * queue. This bit is used by tsu_err to classify errors.
+ */
+ u32 cq_in_err:1;
+ /*
+ * Retry counter associated with retries to received NAK or implied NAK. If
+ * it expires, a path migration will be attempted if it is armed, or the QP
+ * will go to error state. Read by tsu_dma and used by tsu_cmpl.
+ */
+ u32 error_retry_count:3;
+ /*
+ * Error retry counter initial value. Read by tsu_dma and used by tsu_cmpl to
+ * calculate exp_backoff etc..
+ */
+ u32 error_retry_init:3;
+ /*
+ * The XRC domain is used to check against the XRC domain in the XRCSRQ
+ * descriptor indexed by the request. If the XRC domain matches, the
+ * protection domain in the XRCSRQ descriptor is used instead of the
+ * protection domain associated with the QP.
+ */
+ u32 xrc_domain:24;
+ /*
+ * If the DMA is getting an R-Key violation or an error from PCIe when
+ * fetching data for RDMA read responses, it has to set this bit. When set,
+ * all packets sitting behind the RDMA read on this QP (requests and
+ * responses), must be marked bad so they are not transmitted on IB.
+ */
+ u32 resp_access_error:1;
+ /*
+ * If the DMA is getting an L-Key violation or an error from PCIe when
+ * fetching data for requests, it has to set this bit. When set, all requests
+ * behind must be marked in error and not transmitted on IB. Responses are
+ * sent as normal.
+ */
+ u32 req_access_error:1;
+ /*
+ * This retry tag is updated by the error block when an error occur. If
+ * tsu_rqs reads this retry tag and it is different than the
+ * retry_tag_comitted, tsu_rqs must update retry_tag_comitted to the value of
+ * retry_tag_err when the sq_sequence_number indicates this is the valid
+ * request. The sq_sequence_number has been updated by tsu_err at the same
+ * time the retry_tag_err is updated.
+ */
+ u32 retry_tag_err:3;
+ /*
+ * This retry tag is the one used by tsu_rqs and added to the packets sent to
+ * tsu_dma. It is the responsibility of tsu_rqs to update this retry tag
+ * whenever the sq_sequence_number in QP state is equal to the one in the
+ * request.
+ */
+ u32 retry_tag_committed:3;
+ /* R-Key of received multipacket message. */
+ u32 rcv_rkey;
+ /* QP number for the remote node. */
+ u32 remote_qp:24;
+ /* QP State for this QP. */
+ enum psif_qp_state state:3;
+
+ /*
+ * Minium RNR NAK timeout. This is added to RNR NAK packets and the requester
+ * receiving the RNR NAK must wait until the timer has expired before the
+ * retry is sent.
+ */
+ u32 min_rnr_nak_time:5;
+ /* sq_seq(16[0] bits) * Send queue sequence number. This sequence number is used to make sure
+ * order is maintained for requests sent from the process/host.
+ */
+ u16 sq_seq;
+ /* sq_seq(16[0] bits) * Send queue sequence number. This sequence number is used to make sure
+ * order is maintained for requests sent from the process/host.
+ */
+ u16 retry_sq_seq;
+ /*
+ * Number of bytes received for in progress RDMA RD Responses. This is
+ * maintained by tsu_cmpl.
+ */
+ u32 rcv_bytes;
+ /*
+ * Completion queue sequence number. This is used for privileged requests,
+ * where sequence number for one CQ is added to a different completion.
+ */
+ u32 cq_seq;
+ /*
+ * Magic number used to verify use of QP state. This is done by calculating a
+ * checksum of the work request incorporating the magic number. This checksum
+ * is checked against the checksum in the work request.
+ */
+ u32 magic;
+ /*
+ * Sequence number of the last ACK received. Read and written by tsu_cmpl.
+ * Used to verify that the received response packet is a valid response.
+ */
+ u32 last_acked_psn:24;
+ /*
+ * This is set by CMPL when there are outstanding requests and a TX error is
+ * received from DMA. It is cleared when the error is sent on.
+ */
+ enum psif_cmpl_outstanding_error outstanding_error:4;
+
+ /*
+ * Bit used for internal use when QP is moved to error and error completions
+ * etc should be sent. Should alway be initialized to zero by SW.
+ */
+ u32 request_handled:1;
+ /*
+ * When 1, indicates that we have started a flush retry. SQ or QP in error.
+ * Must be cleared on modify QP - SQErr to RTS.
+ */
+ u32 flush_started:1;
+ /* When 1 indicates that we have a fence retry outstanding. */
+ u32 fence_retry_outstanding:1;
+ /* When 1 indicates that we have an IB retry outstanding. */
+ u32 ib_retry_outstanding:1;
+ /*
+ * Q-Key received in incoming IB packet is checked towards this Q-Key. Q-Key
+ * used on transmit if top bit of Q-Key in WR is set.
+ */
+ u32 qkey;
+ /*
+ * Expected packet sequence number: Sequence number on next expected packet.
+ */
+ u32 expected_psn:24;
+ /*
+ * When 1, indicates that a psn_nak has been sent. Need a valid request in
+ * order to clear the bit.
+ */
+ u32 psn_nak:1;
+ /*
+ * 2 bits (next_opcode) 0x0: No operation in progress 0x1: Expect SEND middle
+ * or last 0x2: Expect RDMA_WR middle or last
+ */
+ enum psif_expected_op expected_opcode:2;
+
+ /* Index to scatter element of in progress SEND. */
+ u32 scatter_indx:5;
+ /* Offset within scatter element of in progress SEND. */
+ u32 scatter_offs;
+ /* IB defined capability enable for receiving RDMA RD. */
+ u64 rdma_rd_enable:1;
+ /* IB defined capability enable for receiving RDMA WR. */
+ u64 rdma_wr_enable:1;
+ /* IB defined capability enable for receiving Atomic operations. */
+ u64 atomic_enable:1;
+ /* PSIF specific capability enable for receiving Masked Atomic operations. */
+ u64 masked_atomic_enable:1;
+ /* Reserved */
+ u64 noname:2;
+ /* Enable capability for RSS. */
+ u64 rss_enable:1;
+ /*
+ * This is a proxy QP. Packets less than a particular size are forwarded to
+ * EPS-A core indicated in the CQ descriptor.
+ */
+ u64 proxy_qp_enable:1;
+ /*
+ * Dynamic MTU is enabled - i.e. incoming requests can have 256B payload
+ * instead of MTU size specified in QP state.
+ */
+ u64 rcv_dynamic_mtu_enable:1;
+ /*
+ * Enable header/data split for offloading. Header and data should end up in
+ * separate scatter elements.
+ */
+ u64 hdr_split_enable:1;
+ /* This is an IB over IB QP. */
+ u64 ipoib_enable:1;
+ /* This is an Ethernet over IB QP. */
+ u64 eoib_enable:1;
+ /*
+ * Migration state (migrated, re-arm and armed). Since path migration is
+ * handled by tsu_qps, this is controlled by tsu_qps. XXX: Should error
+ * handler also be able to change the path?
+ */
+ enum psif_migration mstate:2;
+
+ /*
+ * TSU quality of service level. Can take values indicating low latency and
+ * high throughput. This is equivalent to high/low BAR when writing doorbells
+ * to PSIF. The qosl bit in the doorbell request must match this bit in the
+ * QP state, otherwise the QP must be put in error. This check only applies
+ * to tsu_rqs.
+ */
+ enum psif_tsu_qos qosl:1;
+
+ /*
+ * When 1, indicates that a NAK has been for committed_psn+1. Need a valid
+ * request in order to clear the bit. This means receiving a good first/only
+ * packet for the committed_psn+1.
+ */
+ u64 nak_sent:1;
+ /*
+ * Timeout timestamp - if the timer is running and the timestamp indicates a
+ * timeout, a retry iss issued.
+ */
+ u64 timeout_time:48;
+ /*
+ * Maximum number of outstanding read or atomic requests allowed by the
+ * remote HCA. Initialized by software.
+ */
+ u64 max_outstanding:5;
+ /*
+ * TSU Service Level used to decide the TSU VL for requests associated with
+ * this QP.
+ */
+ u64 tsl:4;
+ /* The timestamp is valid and will indicate when to time out the request.. */
+ u64 timer_running:1;
+ /*
+ * An error is found by tsu_cmpl. All packets on this QP is forwarded to
+ * tsu_err until this bit is cleared. The bit is cleared either from QP
+ * cleanup or when tsu_cmpl is receiving is_retry.
+ */
+ u64 rc_in_error:1;
+ /*
+ * Index to scatter element of in progress RDMA RD response. This field does
+ * not need to be written to host memory.
+ */
+ u64 resp_scatter_indx:5;
+ /*
+ * Retry transmit packet sequence number. This is the xmit_psn which should
+ * be used on the first packet of a retry. This is set by tsu_err. When
+ * tsu_dma see that a packet is the first of a retry, it must use this psn as
+ * the xmit_psn and write back xmit_psn as this psn+1.
+ */
+ u64 retry_xmit_psn:24;
+ /*
+ * Transmit packet sequence number. Read and updated by tsu_dma before
+ * sending packets to tsu_ibpb and tsu_cmpl.
+ */
+ u64 xmit_psn:24;
+ /* Receive capabilities enabled for this QP. */
+ /* Inlined rcv_cap : struct psif_qp_rcv_cap (64 bits) */
+ /*
+ * This is an index to a receive queue descriptor. The descriptor points to
+ * the next receive queue element to be used. Receive queues are used for IB
+ * Send and RDMA Writes with Immediate data.
+ */
+ u32 rq_indx:24;
+ /*
+ * When set, RQS should only check that the orig_checksum is equal to magic
+ * number. When not set, RQS should perform the checksum check towards the
+ * checksum in the psif_wr.
+ */
+ u32 no_checksum:1;
+ /*
+ * When this bit is set, ordering from the send queue is ignored. The
+ * sq_sequence_number check in the RQS is ignored. When the bit is not set,
+ * sq_sequence_number check is done. This bit must be set for QP0 and QP1.
+ */
+ u32 no_ordering:1;
+ /*
+ * Retry counter associated with RNR NAK retries. If it expires, a path
+ * migration will be attempted if it is armed, or the QP will go to error
+ * state.
+ */
+ u32 rnr_retry_count:3;
+ /* Send Queue RNR retry count initialization value. */
+ u32 rnr_retry_init:3;
+ /*
+ * DMA length found in first packet of inbound request. When last packet is
+ * received, it must be made sure the dmalen and received_bytes are equal.
+ */
+ u32 dmalen;
+ /*
+ * Number of bytes received of in progress RDMA Write or SEND. The data
+ * received for SENDs and RDMA WR w/Imm are needed for completions. This
+ * should be added to the msg_length.
+ */
+ u32 bytes_received;
+ /*
+ * This is an index to completion queue descriptor. The descriptor points to
+ * a receive completion queue, which may or may not be the same as the send
+ * completion queue. For XRC QPs, this field is written by the CQ descriptor
+ * received by the XRCSRQ on the first packet. This way we don't need to look
+ * up the XRCSRQ for every packet. of the message.
+ */
+ u32 rcv_cq_indx:24;
+ /* Reserved */
+ u32 noname1:5;
+ /*
+ * Transport type of the QP (RC, UC, UD, XRC, MANSP1). MANSP1 is set for
+ * privileged QPs.
+ */
+ enum psif_qp_trans transport_type:3;
+
+ /*
+ * This bit is set by RQS when a TSU_RQS_MAX_OUTSTANDING_REACHED_ERR or
+ * TSU_RQS_REQUEST_FENCED_ERR error is seen and cleared when the first packet
+ * of a retry is seen. While this bit is set, all packets towards DMA shall
+ * have the TSU_RQS_SEQNUM_ERR set.
+ */
+ u32 retry_needed:1;
+ /*
+ * Flag indicating if the swap in the last atomic swap operation was
+ * performed or not. If swapped, the next RDMA WR should be performed towards
+ * host memory. If not swapped, the next RDMA WR should not be performed
+ * towards host memory, but should be ACK'ed at the IB level as normal.
+ */
+ enum psif_bool swapped:1;
+
+ /*
+ * Set when entering response scheduling mode and cleared when going out of
+ * the mode. We exit this mode when resp_sched_count_sched ==
+ * resp_sched_count_done.
+ */
+ u32 resp_sched_mode:1;
+ /*
+ * Write pointer for the scheduling of responses. Host is updating and
+ * forwarding this to tsu_sqs.
+ */
+ u32 resp_sched_sched_ptr:5;
+ /*
+ * The counter is compared towards the resp_sched_count_done and incremented
+ * every time a packet is sent to the SQS.
+ */
+ u32 resp_sched_count_sched:24;
+ /*
+ * The counter is taken from the response packet and stored. tsu_host is
+ * using this value to decide if we go into or out of response scheduling
+ * mode.
+ */
+ u32 resp_sched_count_done:24;
+ /* Used for retry handling. */
+ u32 wait_for_psn:1;
+ /* Send capabilities enabled for this QP. */
+ /* Inlined send_cap : struct psif_qp_snd_cap (64 bits) */
+ /* This QP is running Ethernet over IB. */
+ u32 eoib:1;
+ /* This QP is running IP over IB. */
+ u32 ipoib:1;
+ /*
+ * Dynamic MTU is enabled - i.e. requests can use 256B payload instead of
+ * what is specified in QP state.
+ */
+ u32 send_dynamic_mtu_enable:1;
+ /*
+ * The privileged QP is not so privileged, which means that it is not allowed
+ * to perform all privileged requests.
+ */
+ u32 not_so_privileged:1;
+ /* PSIF specific exponential backoff enable. */
+ u32 exp_backoff_enable:1;
+ /*
+ * Offloading type for EoIB. Indicating how the Enforcement of EoIB is done
+ * by PSIF.
+ */
+ enum psif_eoib_type eoib_type:2;
+
+ /* This is inverted by the APM module when an event should be sent. */
+ u64 apm_success_event_needed:1;
+ /* This is inverted by the APM module when an event should be sent. */
+ u64 apm_failed_event_needed:1;
+ /*
+ * When this bit is not equal to apm_success_event_needed, CBLD should send
+ * an event and set this bit equal to apm_success_event_needed. When the QP
+ * is initialized, this value should be set equal to
+ * apm_success_event_needed.
+ */
+ u64 apm_success_event_sent:1;
+ /*
+ * When this bit is not equal to apm_failed_event_needed, CBLD should send an
+ * event and set this bit equal to apm_failed_event_needed. When the QP is
+ * initialized, this value should be set equal to apm_failed_event_needed.
+ */
+ u64 apm_failed_event_sent:1;
+ /*
+ * This is set when the field operation_successful == 0 from HOST. It is used
+ * to make sure that no good completion is to be sent after an atomic error
+ * has occurred. When set, the QP state is moved to error when seen on the
+ * exec side.
+ */
+ u64 atomic_error:1;
+ /*
+ * This bit indicates that the QP is now handling responses in a safe manner
+ * with respect to MSN values in the incoming IB packets.
+ */
+ u64 in_safe_mode:1;
+ /*
+ * This bit is set when a HOST initiated NAK is sent due to errors when
+ * handling an atomic. When this bit is set, no data is forwarded to EPS or
+ * XIU, and no responses or ACK/NAKs should be forwarded to RQS.
+ */
+ u64 host_sent_nak:1;
+ /* Reserved */
+ u64 noname2:41;
+ /*
+ * Combined 'Last Received MSN' and 'Last Outstanding MSN', used to maintain
+ * 'spin set floor' and indicate 'all retries completed', respectively.
+ */
+ u16 last_received_outstanding_msn;
+ /*
+ * Request address. In the case of RDMA WR, this is the current write
+ * pointer. In the case of a SEND, this is the address to the receive queue
+ * element.
+ */
+ u64 req_addr;
+ /*
+ * Offset within scatter element of in progress RDMA RD response. This field
+ * does not need to be written to host memory.
+ */
+ u32 resp_scatter_offs;
+ /* This PSN is committed - ACKs sent will contain this PSN. */
+ u32 committed_received_psn:24;
+ /*
+ * Communication established bit. When a packet is received when in RTR
+ * state, this bit should be set, and an asynchronous event should be sent.
+ */
+ enum psif_comm_live comm_established:1;
+
+ enum psif_path_mtu path_mtu:3;
+
+ /*
+ * Write pointer to atomic data stored in QP. Every time an atomic operation
+ * is performed, the original atomic data is stored in order be to returned
+ * in the event of duplicate atomic.
+ */
+ u32 orig_atomic_wr_ptr:4;
+ /*
+ * Committed MSN - the MSN of the newest committed request for this QP. Only
+ * the bottom 16 bits of the MSN is used.
+ */
+ u64 last_committed_msn:16;
+ /*
+ * This is an index to send completion queue descriptor. The descriptor
+ * points to a send completion queue, which may or may not be the same as the
+ * send completion queue.
+ */
+ u64 send_cq_indx:24;
+ /*
+ * Message sequence number used in AETH when sending ACKs. The number is
+ * incremented every time a new inbound message is processed.
+ */
+ u64 msn:24;
+ /*
+ * This is the eps_tag to be used in the case there is an outstanding error
+ * detected in CMPL. The field is owned CMPL and is used for internal
+ * handling.
+ */
+ u64 eps_tag:16;
+ /* pd(24[0] bits)Protection domain. */
+ u64 pd:24;
+ /* pd(24[0] bits)Protection domain. */
+ u64 srq_pd:24;
+} PSIF_PACKED_ALIGNED; /* struct psif_qp_core [128 byte] */
+
+/*
+ * Path specific information. This is information which can be different for
+ * primary and alternate path.
+ */
+struct psif_qp_path { /* Subjected to copy and convert */
+ u64 remote_gid_0;
+ u64 remote_gid_1;
+ /* Inlined grh : struct psif_grh (192 bits) */
+ /* ib_grh_flowl(20[0] bits)Flow Label */
+ u64 flowlabel:20;
+ /* ib_grh_tclass(8[0] bits)Traffic Class */
+ u64 tclass:8;
+ /* ib_grh_hoplmt(8[0] bits)Hop Limit */
+ u64 hoplmt:8;
+ /* Reserved */
+ u64 noname:4;
+ /* ib_lrh_sl(4[0] bits)Service Level */
+ u64 sl:4;
+ enum psif_use_grh use_grh:1;
+
+ enum psif_loopback loopback:1;
+
+ enum psif_port port:1;
+
+ /* gid_indx(1[0] bits)GID index indicating which of the UFs two GIDs are used. */
+ u64 gid_indx:1;
+ /* ib_lrh_lid(16[0] bits)Local ID */
+ u16 remote_lid;
+ /* pkey_indx(9[0] bits)Index into the P-Key table. */
+ u64 pkey_indx:9;
+ /*
+ * This is the LID path bits. This is used by tsu_ibpb when generating the
+ * SLID in the packet, and it is used by tsu_rcv when checking the DLID.
+ */
+ u64 local_lid_path:7;
+ /* Reserved */
+ u64 noname1:8;
+ /* ipd(8[0] bits)Inter packet delay. Encoded as specified in IB spec. */
+ u64 ipd:8;
+ /* timeout(5[0] bits) * Local ACK timeout. This is the exponent used to calculate the delay before
+ * an ACK is declared 'lost'
+ */
+ u64 local_ack_timeout:5;
+ /* Reserved field - used by hardware for error handling on PCIe errors. */
+ u64 path_invalid:1;
+ /* Reserved */
+ u64 noname2:26;
+} PSIF_PACKED_ALIGNED; /* struct psif_qp_path [32 byte] */
+
+/* Query QP structure. */
+struct psif_query_qp {
+ /* QP state information from query. */
+ struct psif_qp_core qp;
+ /* Primary path information. */
+ struct psif_qp_path primary_path;
+ /* Alternate path information. */
+ struct psif_qp_path alternate_path;
+} PSIF_PACKED_ALIGNED; /* struct psif_query_qp [192 byte] */
+
+/*
+ * Modify/query QP attributes. Bit mask indicating which field should be
+ * modified.
+ */
+struct psif_qp_attributes {
+ /* Manually added spacing to pad outpsif_qp_attributes */
+ u8 :7;
+ /* Change path req_access error if set. */
+ u8 req_access_error:1;
+ /* Change path MTU if set. */
+ u16 path_mtu:1;
+ /* Change expected PSN (RQ PSN) if set. */
+ u16 expected_psn:1;
+ /* Change primary path if set. */
+ u16 prim_path:1;
+ /*
+ * Change migration state if set. In some cases this might lead to a path
+ * migration.
+ */
+ u16 mig_state:1;
+ /* Change alternate path if set. */
+ u16 alt_path:1;
+ /* Change the state of the QP when set. */
+ u16 qp_state:1;
+ /* Change the receive capabilities when set. */
+ u16 qp_rcv_cap:1;
+ /* Change the Q-Key when set. */
+ u16 qkey:1;
+ /* Change P-Key index if set. */
+ u16 pkey_index:1;
+ /* Change the local ack timeout when set. */
+ u16 local_ack_timeout:1;
+ /* Change the RNR minimum timer value when set. */
+ u16 min_rnr_nak_time:1;
+ /* Change the retry count when set. */
+ u16 error_retry_count:1;
+ /* Change the RNR retry count when set. */
+ u16 rnr_retry_count:1;
+ /* Change the xmit psn (SQ PSN) when set. */
+ u16 xmit_psn:1;
+ /* Change max outstanding RD/ATOMIC towards destination. */
+ u16 max_outstanding:1;
+ /* Do not modify unless current state is as indicated in command. */
+ u16 use_current_state:1;
+} PSIF_PACKED; /* struct psif_qp_attributes [ 3 byte] */
+
+/* XXX: This is how the QP state in host memory is organized. */
+struct psif_qp { /* Subjected to copy and convert */
+ struct psif_qp_core state;
+ /*
+ * Path information for path A specific for this QP connection. This field
+ * only makes sense for QPs using connected mode. For datagram mode, this
+ * information comes from the AHA.
+ */
+ struct psif_qp_path path_a;
+ /*
+ * Path information for path B specific for this QP connection. This field
+ * only makes sense for QPs using connected mode. For datagram mode, this
+ * information comes from the AHA.
+ */
+ struct psif_qp_path path_b;
+} PSIF_PACKED_ALIGNED; /* struct psif_qp [192 byte] */
+
+/* Temp.definition of collect buffers */
+struct psif_cb { /* Subjected to copy and convert */
+ /* Content pt. not defined in ASIC XML */
+ struct psif_wr wr;
+ u64 payload[32];
+} PSIF_PACKED_ALIGNED; /* struct psif_cb [320 byte] */
+
+/* Temp.definition of PCIe WR BAR SQS WR layout = first 8 bytes of WR */
+struct psif_pcie_sqs_wr {
+ /*
+ * XXX: Naming - do we want to use opcode for this also, or should we use
+ * pkt_type.
+ */
+ enum psif_wr_type op:8;
+
+ /*
+ * QP sending this request. XXX: Should name be own_qp_num as defined in QP
+ * state?
+ */
+ u32 local_qp:24;
+ /*
+ * The TSL (Tsu SL) must be matched against the TSL in the QP State (XXX: or
+ * in the AHA?). If it is unequal, the QP should be put in error.
+ */
+ u16 tsu_sl:4;
+ /* Port number to use for QP0/1 packets. This field is ignored if not QP0/1. */
+ enum psif_port port:1;
+
+ /* Only applicable to UD. This is an indication that AHA should be used. */
+ enum psif_use_ah ud_pkt:1;
+
+ /*
+ * High Bandwidth/Low Latency BAR. The QoSL must be matched against the QoSL
+ * in the QP State. If it is unequal, the QP should be in error.
+ */
+ enum psif_tsu_qos tsu_qosl:1;
+
+ /* Length (number of bytes of valid data in the collect payload buffer). */
+ u16 collect_length:9;
+ /*
+ * Send queue sequence number. Used to map request to a particular work
+ * request in the send queue.
+ */
+ u16 sq_seq;
+} PSIF_PACKED_ALIGNED; /* struct psif_pcie_sqs_wr [ 8 byte] */
+
+/* Temp.definition of PCIe WR BAR layout */
+struct psif_pcie_wr {
+ struct psif_cb cb;
+ u64 reserved_1[464];
+ struct psif_pcie_sqs_wr sqs_wr;
+ u64 reserved_2[6];
+ u64 clear;
+} PSIF_PACKED_ALIGNED; /* struct psif_pcie_wr [4096 byte] */
+
+struct psif_mbox {
+ /* Host posting to EPS-x */
+
+ u64 in;
+ /* EPS-x posting to Host */
+
+ u64 out;
+} PSIF_PACKED_ALIGNED; /* struct psif_mbox [16 byte] */
+
+struct psif_pcie_mbox {
+ /* MBOX_EPS_MAX mbox'es for all the EPS's */
+
+ struct psif_mbox eps[5];
+ /* (Reset all mailboxes) */
+
+ u64 eps_reset;
+} PSIF_PACKED_ALIGNED; /* struct psif_pcie_mbox [88 byte] */
+
+/* Modify QP structure. */
+struct psif_modify_qp {
+ /* Q-Key received in incoming IB packet is checked towards this Q-Key. */
+ u32 rx_qkey;
+ /*
+ * If the DMA is getting an L-Key violation or an error from PCIe when
+ * fetching data for requests, it has to set this bit. When set, all requests
+ * behind must be marked in error and not transmitted on IB. Responses are
+ * sent as normal.
+ */
+ u16 req_access_error:1;
+ /*
+ * Retry counter associated with RNR NAK retries. If it expires, a path
+ * migration will be attempted if it is armed, or the QP will go to error
+ * state.
+ */
+ u16 rnr_retry_count:3;
+ /* Receive capabilities enabled for this QP. */
+ /* Inlined rcv_cap : struct psif_qp_rcv_cap (64 bits) */
+ /* IB defined capability enable for receiving RDMA RD. */
+ u16 rdma_rd_enable:1;
+ /* IB defined capability enable for receiving RDMA WR. */
+ u16 rdma_wr_enable:1;
+ /* IB defined capability enable for receiving Atomic operations. */
+ u16 atomic_enable:1;
+ /* PSIF specific capability enable for receiving Masked Atomic operations. */
+ u16 masked_atomic_enable:1;
+ /* Reserved */
+ u16 noname:2;
+ /* Enable capability for RSS. */
+ u16 rss_enable:1;
+ /*
+ * This is a proxy QP. Packets less than a particular size are forwarded to
+ * EPS-A core indicated in the CQ descriptor.
+ */
+ u16 proxy_qp_enable:1;
+ /*
+ * Dynamic MTU is enabled - i.e. incoming requests can have 256B payload
+ * instead of MTU size specified in QP state.
+ */
+ u16 rcv_dynamic_mtu_enable:1;
+ /*
+ * Enable header/data split for offloading. Header and data should end up in
+ * separate scatter elements.
+ */
+ u16 hdr_split_enable:1;
+ /* This is an IB over IB QP. */
+ u16 ipoib_enable:1;
+ /* This is an Ethernet over IB QP. */
+ u16 eoib_enable:1;
+ /*
+ * Error retry counter initial value. Read by tsu_dma and used by tsu_cmpl to
+ * calculate exp_backoff etc..
+ */
+ u16 error_retry_count:3;
+ /*
+ * Minium RNR NAK timeout. This is added to RNR NAK packets and the requester
+ * receiving the RNR NAK must wait until the timer has expired before the
+ * retry is sent.
+ */
+ u16 min_rnr_nak_time:5;
+ /* QP State for this QP. */
+ enum psif_qp_state state:3;
+
+ /*
+ * Current number of retired read or atomic requests. Initialze to zero.
+ * Updated by tsu_cmpl every time a read or atomic request is completed.
+ */
+ u16 max_outstanding:5;
+ /*
+ * Receive packet sequence number. Read and updated by tsu_dscr before
+ * passing packets to tsu_rqh.
+ */
+ u32 expected_psn:24;
+ /* Path MTU. */
+ enum psif_path_mtu path_mtu:3;
+
+ /* Reserved */
+ u32 noname1:3;
+ /*
+ * Migration state (migrated, re-arm and armed). Since path migration is
+ * handled by tsu_qps, this is controlled by tsu_qps. XXX: Should error
+ * handler also be able to change the path?
+ */
+ enum psif_migration mstate:2;
+
+ /* Reserved */
+ u32 noname2:8;
+ /*
+ * Transmit packet sequence number. Read and updated by tsu_dma before
+ * sending packets to tsu_ibpb and tsu_cmpl.
+ */
+ u32 xmit_psn:24;
+ /* Primary path information. */
+ struct psif_qp_path primary_path;
+ /* Alternate path information. */
+ struct psif_qp_path alternate_path;
+} PSIF_PACKED_ALIGNED; /* struct psif_modify_qp [80 byte] */
+
+/* QP number UF and command for either modify or query QP. */
+struct psif_modify_command {
+ /* Command indicating operation - query or modify. */
+ enum psif_qp_command cmd:2;
+
+ /* UF this QP belongs to. */
+ u8 uf:6;
+ /*
+ * Port number used for accesses to QP0/1. This field is don't care for all
+ * other QPs.
+ */
+ enum psif_port port_num:1;
+
+ /* Current state the QP must be in to do the modification. */
+ enum psif_qp_state current_state:3;
+
+ /* QP number for this operation. */
+ u32 qp_num:24;
+ /*
+ * This will arm interrupt to be sent when the refcount for the QP index used
+ * have reached zero. It should be used when modify to Reset - when interrupt
+ * is seen, there are no outstanding transactions towards RQs or CQs for the
+ * QP, and it should be safe to take these queues down.
+ */
+ u32 notify_when_zero:1;
+ /* Manually added spacing to pad out psif_modify_command */
+ u32 :3;
+} PSIF_PACKED; /* struct psif_modify_command [ 5 byte] */
+
+/*
+ * Structure defining DMA Key Validation entries. This structure is specific
+ * to IB and has information about R/L-Key states. One entry kan represent an
+ * R-Key, an L-Key or both at the same time. This is is decided bythe key
+ * states.
+ */
+struct psif_key {
+ /* R-key state for this DMA validation entry */
+ enum psif_dma_vt_key_states rkey_state:2;
+
+ /* L-key state for this DMA validation entry */
+ enum psif_dma_vt_key_states lkey_state:2;
+
+ /* Reserved */
+ u32 noname:4;
+ /* pd(24[0] bits)Protection domain. */
+ u32 pd:24;
+ /* Remote access rights. Used for R-Key accesses when this is a valid R-Key. */
+ /* Inlined remote_access : struct psif_dma_vt_mem_access (64 bits) */
+ /* Read access enabled. */
+ u32 remote_access_rd:1;
+ /* Write access enabled. */
+ u32 remote_access_wr:1;
+ /* Atomic access enabled. */
+ u32 remote_access_atomic:1;
+ /*
+ * Local access rights. Used for L-Key accesses when this is a valid L-Key.
+ * Must be set correctly by SW so that RD access is always set.
+ */
+ /* Inlined local_access : struct psif_dma_vt_mem_access (64 bits) */
+ /* Read access enabled. */
+ u32 local_access_rd:1;
+ /* Write access enabled. */
+ u32 local_access_wr:1;
+ /* Atomic access enabled. */
+ u32 local_access_atomic:1;
+ /*
+ * If this bit is set, it means that this memory region is enabled for
+ * conditional RDMA write. The bit must be added to the header at tsu_val and
+ * follow the request towards tsu_host. When tsu_host receives this bit, it
+ * is checking the 'swapped' bit in the QP state in order to decide if the
+ * payload is written to host memory or not.
+ */
+ u32 conditional_wr:1;
+ /*
+ * If this bit is set, the va in the key is used as an offset to the base
+ * address given in this descriptor.
+ */
+ u32 zero_based_addr_en:1;
+ /* Reserved */
+ u32 noname1:24;
+ /* Length of memory region this validation entry is associated with. */
+ u64 length;
+ struct psif_mmu_cntx mmu_context;
+ /* host_address(64[0] bits)Host address used for accesses to/from TSU HOST. */
+ u64 base_addr;
+} PSIF_PACKED_ALIGNED; /* struct psif_key [32 byte] */
+
+/**
+ * Flash image header format for application image
+ * extention of struct psif_flash_header_all
+ */
+struct psif_flash_header_app {
+ /* byte[4:7] image type */
+ enum psif_flash_image_type type:32;
+
+ /* byte[0:3] signature is 0xdeadbeef */
+ u32 signature;
+ /* byte[12:15] code/data size */
+ u32 image_length;
+ /* byte[8:11] SHRDMEM start address */
+ u32 exec_base;
+ /* byte[20:23] ZI size */
+ u32 zi_length;
+ /* byte[16:19] SHRDMEM ZI base address */
+ u32 zi_base;
+ /* byte[28:31] Execution start address */
+ u32 start_addr;
+ /* byte[24:27] Storage only used by boot loader */
+ u32 flash_base;
+ /* byte[36:39] Flash address base of low vectors */
+ u32 low_vec_flash_base;
+ /* byte[32:35] SHRDMEM address base of low vectors */
+ u32 low_vec_base;
+ /* byte[44:47] FLASH_DATE_LEN > = sizeof(__DATE__) */
+ u8 date[4];
+ /* byte[40:43] Size of low vectors */
+ u32 low_vec_length;
+ /* byte[48:55] */
+ u8 date_1[8];
+ /* byte[60:63] FLASH_TIME_LEN > = sizeof(__TIME__) */
+ u8 time[4];
+ /* byte[56:59] */
+ u8 date_2[4];
+ /* byte[64:71] */
+ u8 time_1[8];
+ /* byte[72:79] FLASH_REV_STR_LEN > = sizeof(REV_STRING) */
+ u8 rev_string[8];
+ /* byte[84:87] */
+ u32 app_vec_flash_base;
+ /* byte[80:83] checkssum_ptr - this value + 4 equals the size of the immage in bytes */
+ u32 checksum_ptr;
+ /* byte[92:95] */
+ u32 app_vec_length;
+ /* byte[88:91] */
+ u32 app_vec_base;
+} PSIF_PACKED_ALIGNED; /* struct psif_flash_header_app [96 byte] */
+
+/**
+ * Flash image header format
+ * Note: image length is not valid for the boot loader image itself (64k bytes)
+ * struct is always located at offset 0x800 within an image
+ */
+struct psif_flash_header_all {
+ /* byte[4:7] image type */
+ enum psif_flash_image_type type:32;
+
+ /* byte[0:3] signature of 0xdeadbeef */
+ u32 signature;
+ /* byte[12:15] image length.
+ The length is defined in bytes and starts at offset 0x0A00 into the image. */
+ u32 length;
+ /* byte[8:11] execution base */
+ u32 base;
+} PSIF_PACKED_ALIGNED; /* struct psif_flash_header_all [16 byte] */
+
+/* This is the portion of the descriptor which is updated by software. */
+struct psif_eq_sw {
+ /* Index to event elements consumed by SW. */
+ u32 head_indx;
+} PSIF_PACKED; /* struct psif_eq_sw [ 4 byte] */
+
+/*
+ * Descriptor entry for an event queue. This entry is used to address into
+ * the event queue and write the correct entries. This structure is the
+ * hardware updateable part of the EQ descriptor.
+ */
+struct psif_eq_hw {
+ /* Reserved */
+ u32 noname:21;
+ /* Inlined ctrl : struct psif_eq_ctrl (64 bits) */
+ /* The descriptor is valid. */
+ u32 valid:1;
+ /*
+ * The size between event queue entries. This is the shift value to find the
+ * start of the next entry.
+ */
+ u32 extent_log2:5;
+ /*
+ * The size (log2 number of entries) of the event queue. This is used for
+ * calculating when to wrap the head and tail indexes.
+ */
+ u32 size_log2:5;
+ /*
+ * Event queue sequence number. This is the sequence number to be used for
+ * this event. When used by a client, it is incremented and written back to
+ * this descriptor.
+ */
+ u32 sequence_number;
+ struct psif_mmu_cntx mmu_cntx;
+ /*
+ * VA or PA of the base of the queue. If PA the MMU context above will be a
+ * bypass context. Updated by software. The head and tail pointers can be
+ * calculated by the following calculations: Address = base_ptr + (head *
+ * ($bits(event_entry_t)/8 ) Head Pointer and Tail Pointer will use the same
+ * MMU context as the base, and all need to be VA from one address space, or
+ * all need to be PA. In typical use, to allow direct user access to the head
+ * and tail pointer VAs are used.
+ */
+ u64 base_addr;
+ /* Index to event queue elements added by HW. */
+ u32 tail_indx;
+ /* Info: Edge padding added (for endian convert) */
+ u32 space24;
+} PSIF_PACKED_ALIGNED; /* struct psif_eq_hw [32 byte] */
+
+/* Event queue entry. */
+struct psif_eq_entry {
+ /* PSIF_EVENT_PATH_MIGRATED. */
+ u16 event_status_path_migrated:1;
+ /* PSIF_EVENT_COMMUNICATION_ESTABLISHED. */
+ u16 event_status_communication_established:1;
+ /* PSIF_EVENT_SRQ_LIMIT_REACHED. */
+ u16 event_status_srq_limit_reached:1;
+ /* PSIF_EVENT_LAST_WQE_REACHED. */
+ u16 event_status_last_wqe_reached:1;
+ /* PSIF_EVENT_CQ_ERROR. */
+ u16 event_status_cq_error:1;
+ /* PSIF_EVENT_INVALID_REQUEST_LOCAL_WQ_ERROR. */
+ u16 event_status_invalid_request_local_wq_error:1;
+ /* PSIF_EVENT_LOCAL_ACCESS_VIOLATION_WQ_ERROR. */
+ u16 event_status_local_access_violation_wq_error:1;
+ /* PSIF_EVENT_PATH_MIGRATION_REQUEST_ERROR. */
+ u16 event_status_path_migration_request_error:1;
+ /* PSIF_EVENT_XRC_DOMAIN_VIOLATION. */
+ u16 event_status_xrc_domain_violation:1;
+ /* PSIF_EVENT_INVALID_XRCETH. */
+ u16 event_status_invalid_xrceth:1;
+ /* PSIF_EVENT_SRQ_CATASTROPHIC_ERROR. */
+ u16 event_status_srq_catastrophic_error:1;
+ /* PSIF_EVENT_LOCAL_WORK_QUEUE_CATASTROPHIC_ERROR. */
+ u16 event_status_local_work_queue_catastrophic_error:1;
+ /* PSIF_EVENT_PORT_ACTIVE. */
+ u16 event_status_port_active:1;
+ /* PSIF_EVENT_CLIENT_REGISTRATION. */
+ u16 event_status_client_registration:1;
+ /* PSIF_EVENT_PORT_CHANGED. */
+ u16 event_status_port_changed:1;
+ /* PSIF_EVENT_LOCAL_CATASTROPHIC_ERROR. */
+ u16 event_status_local_catastrophic_error:1;
+ /* PSIF_EVENT_PORT_ERROR. */
+ u16 event_status_port_error:1;
+ /* PSIF_EVENT_CMPL_NOTIFY. */
+ u16 event_status_cmpl_notify:1;
+ /* PSIF_EVENT_EPS_C. */
+ u16 event_status_eps_c:1;
+ /* PSIF_EVENT_EPS_A. */
+ u16 event_status_eps_a:1;
+ /*
+ * The port_flags are only applicable for port type events. These are not set
+ * from the TSU, but implemented from EPS.
+ */
+ u16 port_flags:4;
+ /* Error field indicating vendor error when this is an error event. */
+ enum psif_tsu_error_types vendor_error:8;
+
+ /* Completion queue descriptor ID. */
+ u32 cqd_id:24;
+ /* IB port number */
+ enum psif_port port:1;
+
+ /* vendor_fields(3[0] bits)Should this be an enum? */
+ u32 vendor_fields:3;
+ enum psif_eps_core_id eps_core_id:4;
+
+ /* Receive queue descriptor ID. */
+ u64 rqd_id:24;
+ /* QP number. */
+ u64 qp:24;
+ /* LID. */
+ u16 lid;
+ /* Inlined event_status : struct psif_event_status (64 bits) */
+ /* Completion queue sequence number causing the event to be sent. */
+ u32 cq_sequence_number;
+ /* Event type if port_flags is PSIF_EVENT_EXTENSION */
+ enum psif_event extension_type:32;
+
+ /* More info on event */
+ u64 event_info;
+ /* Additional data on event */
+ u64 event_data;
+ /* Padding out struct bulk */
+ u64 reserved[2];
+ /* Padding out struct last */
+ u32 noname:32;
+ /* sequence number for sanity checking */
+ u32 seq_num;
+} PSIF_PACKED_ALIGNED32; /* struct psif_eq_entry [64 byte] */
+
+struct psif_epsc_log_stat {
+ /* Owned by epsc runs all the way to 64 bit */
+ u64 produce_offset;
+ /* Owned by host */
+ u64 consume_offset;
+ /* Owned by host real offset modulo sz */
+ u64 size;
+ /* Allign to 32 byte */
+ u64 pad;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_log_stat [32 byte] */
+
+/**
+ * CSR Query port structure
+ */
+struct psif_epsc_port_attr {
+ /** port number */
+ u32 portNumber;
+ /** port state */
+ enum psif_epsc_port_state state:32;
+
+ /** maximum supported path MTU */
+ enum psif_epsc_path_mtu max_mtu:32;
+
+ /** currently configured path MTU */
+ enum psif_epsc_path_mtu active_mtu:32;
+
+ u32 gid_tbl_len;
+ u32 port_cap_flags;
+ u32 max_msg_sz;
+ u32 bad_pkey_cntr;
+ u32 qkey_viol_cntr;
+ u16 pkey_tbl_len;
+ u16 lid;
+ u16 sm_lid;
+ u16 lmc:8;
+ u16 max_vl_num:8;
+ u16 sm_sl:8;
+ u16 subnet_timeout:8;
+ u16 init_type_reply:8;
+ u16 active_width:8;
+ enum psif_port_speed active_speed:8;
+
+ u64 phys_state:8;
+ u64 noname:48;
+ u64 pad;
+} PSIF_PACKED_ALIGNED32; /* struct psif_epsc_port_attr [64 byte] */
+
+/**
+ * Query GID response in host memory
+ */
+struct psif_epsc_gid_attr {
+ u64 gid_0;
+ u64 gid_1;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_gid_attr [16 byte] */
+
+/**
+ * Populate MMU table
+ */
+struct psif_epsc_exercise_mmu {
+ /* Start adress */
+ u64 host_addr;
+ /* MMU context supplied by driver */
+ struct psif_mmu_cntx mmu_cntx;
+ /* Buffer length in bytes */
+ u64 length;
+ /* Stride in bytes */
+ u64 stride;
+ u64 reserved[7];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_exercise_mmu [88 byte] */
+
+/**
+ * CSR Query device structure
+ */
+struct psif_epsc_device_attr {
+ u64 fw_ver;
+ u64 sys_image_guid;
+ u64 node_guid;
+ u64 max_mr_size;
+ u64 page_size_cap;
+ u32 vendor_id;
+ u32 vendor_part_id;
+ u32 hw_ver;
+ u32 max_qp;
+ u32 max_qp_wr;
+ u32 device_cap_flags;
+ u32 max_sge;
+ u32 max_sge_rd;
+ u32 max_cq;
+ u32 max_cqe;
+ u32 max_mr;
+ u32 max_pd;
+ u32 max_qp_rd_atom;
+ u32 max_ee_rd_atom;
+ u32 max_res_rd_atom;
+ u32 max_qp_init_rd_atom;
+ u32 max_ee_init_rd_atom;
+ enum psif_epsc_atomic_cap atomic_cap:32;
+
+ enum psif_epsc_atomic_cap masked_atomic_cap:32;
+
+ u32 max_ee;
+ u32 max_rdd;
+ u32 max_mw;
+ u32 max_raw_ipv6_qp;
+ u32 max_raw_ethy_qp;
+ u32 max_mcast_grp;
+ u32 max_mcast_qp_attach;
+ u32 max_total_mcast_qp_attach;
+ u32 max_ah;
+ u32 max_fmr;
+ u32 max_map_per_fmr;
+ u32 max_srq;
+ u32 max_srq_wr;
+ u32 max_srq_sge;
+ u32 max_fast_reg_page_list_len;
+ u64 max_pkeys:16;
+ u64 local_ca_ack_delay:8;
+ u64 phys_port_cnt:32;
+ u64 noname:8;
+ u64 pad;
+} PSIF_PACKED_ALIGNED32; /* struct psif_epsc_device_attr [192 byte] */
+
+/**
+ * The eps-c fw csr to host sw completion
+ * Response to a CSR request
+ */
+struct psif_epsc_csr_rsp {
+ /* return status of operation */
+ enum psif_epsc_csr_status status:8;
+
+ /* enum psif_epsc_csr_opcode from request */
+ enum psif_epsc_csr_opcode opcode:8;
+
+ /* Data integrity */
+ u16 crc;
+ /* Address from request */
+ u32 addr;
+ /* Data from operation */
+ u64 data;
+ /* Info from operation */
+ u64 info;
+ /* Sequence number from request */
+ u64 seq_num;
+} PSIF_PACKED_ALIGNED32; /* struct psif_epsc_csr_rsp [32 byte] */
+
+struct psif_epsc_csr_opaque {
+ u64 data[11];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_opaque [88 byte] */
+
+struct psif_epsc_csr_single {
+ u64 data;
+ u64 reserved[10];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_single [88 byte] */
+
+/**
+ * \brief Padded base address structure
+ * \details
+ * With this structure the driver provides the information needed be the
+ * firmware to set up queue, queue pair and address handle descriptor base
+ * addresses before they can be used.
+ * \par Used in
+ * psif_epsc_csr_details for \ref EPSC_SET_BASEADDR and
+ * \ref EPSC_SET_BASEADDR_EQ mailbox requests
+ * \par Classification
+ * driver
+ */
+struct psif_epsc_csr_base_addr {
+ /** base address in host memory to be used for the descriptor */
+ u64 address;
+ /** MMU context for `address` */
+ struct psif_mmu_cntx mmu_context;
+ /** number of entries in the table */
+ u32 num_entries;
+ /** unused (padding) */
+ u32 noname:27;
+ /** size of an entry as log2 value. The address to an entry is calculated
+ * as host_addr + entry_num*(1 << extent_log2) */
+ u32 extent_log2:5;
+ /** MSI-X interrupt index only valid for EQ setup */
+ u32 msix_index;
+ /** unused (padding) */
+ u32 noname1:32;
+ /** unused (padding) */
+ u64 padding[7];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_base_addr [88 byte] */
+
+/* CSR automated type for TSU_QPS_MODIFY_QP_CTRL */
+/*
+ * Per UF modify/query QP command/attribute register. Only one register is
+ * implemented in hardware - one at a time. EPS implements one register per
+ * UF. When one is written, the modify data is written to modify_qp_data
+ * register before this register is written. The Modify or Query QP command
+ * is autmatically kicked when this register is written. Is one outstanding
+ * modify/query QP per UF ok, or do we need more?
+ */
+struct psif_csr_modify_qp_ctrl {
+ /* Command indicating operation - query or modify. */
+ enum psif_qp_command cmd:2;
+
+ /* UF this QP belongs to. */
+ u64 uf:6;
+ /*
+ * Port number used for accesses to QP0/1. This field is don't care for all
+ * other QPs.
+ */
+ enum psif_port port_num:1;
+
+ /* Current state the QP must be in to do the modification. */
+ enum psif_qp_state current_state:3;
+
+ /* QP number for this operation. */
+ u64 qp_num:24;
+ /*
+ * This will arm interrupt to be sent when the refcount for the QP index used
+ * have reached zero. It should be used when modify to Reset - when interrupt
+ * is seen, there are no outstanding transactions towards RQs or CQs for the
+ * QP, and it should be safe to take these queues down.
+ */
+ u64 notify_when_zero:1;
+ /* Manually added spacing to pad out psif_modify_command */
+ u64 :3;
+ /* Inlined cmd_attributes : struct psif_qp_attributes (24 bits) */
+ /* Manually added spacing to pad outpsif_qp_attributes */
+ u64 :7;
+ /* Change path req_access error if set. */
+ u64 req_access_error:1;
+ /* Change path MTU if set. */
+ u16 path_mtu:1;
+ /* Change expected PSN (RQ PSN) if set. */
+ u16 expected_psn:1;
+ /* Change primary path if set. */
+ u16 prim_path:1;
+ /*
+ * Change migration state if set. In some cases this might lead to a path
+ * migration.
+ */
+ u16 mig_state:1;
+ /* Change alternate path if set. */
+ u16 alt_path:1;
+ /* Change the state of the QP when set. */
+ u16 qp_state:1;
+ /* Change the receive capabilities when set. */
+ u16 qp_rcv_cap:1;
+ /* Change the Q-Key when set. */
+ u16 qkey:1;
+ /* Change P-Key index if set. */
+ u16 pkey_index:1;
+ /* Change the local ack timeout when set. */
+ u16 local_ack_timeout:1;
+ /* Change the RNR minimum timer value when set. */
+ u16 min_rnr_nak_time:1;
+ /* Change the retry count when set. */
+ u16 error_retry_count:1;
+ /* Change the RNR retry count when set. */
+ u16 rnr_retry_count:1;
+ /* Change the xmit psn (SQ PSN) when set. */
+ u16 xmit_psn:1;
+ /* Change max outstanding RD/ATOMIC towards destination. */
+ u16 max_outstanding:1;
+ /* Do not modify unless current state is as indicated in command. */
+ u16 use_current_state:1;
+ /* Inlined cmd : struct psif_modify_command (40 bits) */
+} PSIF_PACKED_ALIGNED; /* struct psif_csr_modify_qp_ctrl [ 8 byte] */
+
+/**
+ * Modify QP CSR structure
+ */
+struct psif_epsc_csr_modify_qp {
+ struct psif_csr_modify_qp_ctrl ctrl;
+ struct psif_modify_qp data;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_modify_qp [88 byte] */
+
+/**
+ * Query QP
+ *
+ * int ibv_query_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr, enum
+ * ibv_qp_attr_mask attr_mask, struct ibv_qp_init_attr *init_attr)
+ *
+ * Input Parameters:
+ * qp struct ibv_qp from ibv_create_qp
+ * attr_mask bitmask of items to query (see ibv_modify_qp)
+ * Output Parameters:
+ * attr struct ibv_qp_attr to be filled in with requested attributes
+ * init_attr struct ibv_qp_init_attr to be filled in with initial
+ * attributes
+ * Return Value:
+ * 0 on success, errno on failure.
+ */
+struct psif_epsc_csr_query_qp {
+ /* host_address(64[0] bits)Host address used for accesses to/from TSU HOST. */
+ u64 address;
+ struct psif_csr_modify_qp_ctrl ctrl;
+ /* MMU context supplied by driver */
+ struct psif_mmu_cntx mmu_cntx;
+ u64 padding[8];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_query_qp [88 byte] */
+
+/* CSR automated type for TSU_RQS_P{1,2}_OWN_LID_BASE */
+/*
+ * Own LIDs base and LMC. Potentially all own LID bits come from the QP state
+ * entry. The number of bits to use is based on the LMC. Per UF register.
+ */
+struct psif_csr_own_lid_base {
+ u64 noname:44;
+ /* ib_lrh_lid(16[0] bits)Local ID */
+ u64 lid_base:16;
+ /* lmc(3[0] bits)LID Mask Control data type. */
+ u64 lmc:3;
+ u64 gid_flag:1;
+} PSIF_PACKED_ALIGNED; /* struct psif_csr_own_lid_base [ 8 byte] */
+
+/* CSR automated type for TSU_IBPB_P{1,2}_OWN_LID_BASE */
+/*
+ * Own LIDs base and LMC. Potentially all own LID bits come from the QP state
+ * entry. The number of bits to use is based on the LMC. Per UF register.
+ */
+struct psif_csr_snd_lid {
+ u64 noname:45;
+ /* ib_lrh_lid(16[0] bits)Local ID */
+ u64 lid_base:16;
+ /* lmc(3[0] bits)LID Mask Control data type. */
+ u64 lmc:3;
+} PSIF_PACKED_ALIGNED; /* struct psif_csr_snd_lid [ 8 byte] */
+
+/* CSR automated type for TSU_IBPR_P{1,2}_OWN_LID_BASE */
+/*
+ * Own LIDs base and LMC. Potentially all own LID bits come from the QP state
+ * entry. The number of bits to use is based on the LMC. Per UF register.
+ */
+struct psif_csr_rcv_lid {
+ u64 noname:44;
+ /* Inlined data : struct psif_lid_base (64 bits) */
+ /* LID base. */
+ u64 lid_base:16;
+ /* LID mask control. */
+ u64 lmc:3;
+ /* If set GID routing must be used. */
+ u64 gid_flag:1;
+} PSIF_PACKED_ALIGNED; /* struct psif_csr_rcv_lid [ 8 byte] */
+
+/**
+ * EPSC_SET_LID
+ */
+struct psif_epsc_csr_set_lid {
+ struct psif_csr_own_lid_base lid_rqs;
+ struct psif_csr_snd_lid lid_snd;
+ struct psif_csr_rcv_lid lid_rcv;
+ u64 port:8;
+ /* Index pt. not used (PSIF.ARCH.03.12 and later) */
+ u64 index:8;
+ u64 noname:48;
+ u64 padding[7];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_set_lid [88 byte] */
+
+/**
+ * EPSC_SET_GID{,_P1,_P2}
+ */
+struct psif_epsc_csr_set_gid {
+ u64 gid_0;
+ u64 gid_1;
+ u64 port:8;
+ u64 index:8;
+ u64 noname:48;
+ u64 padding[8];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_set_gid [88 byte] */
+
+/**
+ * EPSC_SET_EOIB_MAC
+ */
+struct psif_epsc_csr_set_eoib_mac {
+ u64 mac;
+ u64 port:8;
+ u64 index:8;
+ u64 noname:48;
+ u64 padding[9];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_set_eoib_mac [88 byte] */
+
+/**
+ * Set EPSC_SET_VLINK_STATE
+ */
+struct psif_epsc_csr_vlink_state {
+ /* universal_function(6[0] bits)UF */
+ u64 uf:6;
+ enum psif_port port:1;
+
+ enum psif_vlink_state vlink_state:5;
+
+ u64 noname:52;
+ u64 padding[10];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_vlink_state [88 byte] */
+
+/**
+ * EPSC_QUERY_DEVICE, EPSC_QUERY_PORT, EPSC_QUERY_INFO,
+ */
+struct psif_epsc_csr_query_hw {
+ /* host_address(64[0] bits)Host address used for accesses to/from TSU HOST. */
+ u64 address;
+ /* MMU context supplied by driver */
+ struct psif_mmu_cntx mmu_cntx;
+ u64 padding[9];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_query_hw [88 byte] */
+
+/**
+ * EPSC_QUERY_PKEY, EPSC_QUERY_GID,
+ */
+struct psif_epsc_csr_query_table {
+ u64 port:8;
+ u64 index:16;
+ u64 noname:40;
+ u64 padding[10];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_query_table [88 byte] */
+
+/**
+ * EPSC_MC_ATTACH, EPSC_MC_DETACH, EPSC_QUERY_MC
+ */
+struct psif_epsc_csr_mc {
+ u32 port:8;
+ u32 qp:24;
+ u32 noname:32;
+ u64 mgid_0;
+ u64 mgid_1;
+ u64 padding[8];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_mc [88 byte] */
+
+/**
+ * EPSC_EVENT_ACK
+ */
+struct psif_epsc_csr_event {
+ u16 port:8;
+ u16 eq_num:8;
+ u16 noname:16;
+ u32 eq_index;
+ /* Will become : psif_eq_event event */
+ u64 event[8];
+ u64 padding[2];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_event [88 byte] */
+
+/**
+ * EPSC_MODIFY_DEVICE
+ */
+struct psif_epsc_csr_modify_device {
+ enum psif_epsc_csr_modify_device_flags modify_mask:16;
+
+ u64 noname:48;
+ u64 sys_image_guid;
+ u8 node_desc[64];
+ u64 padding;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_modify_device [88 byte] */
+
+/**
+ * EPSC_MODIFY_PORT_{1,2}
+ */
+struct psif_epsc_csr_modify_port {
+ enum psif_epsc_csr_modify_port_flags modify_mask:16;
+
+ u16 port:8;
+ u16 init_type:8;
+ u32 noname:32;
+ u32 set_port_cap_mask;
+ u32 clr_port_cap_mask;
+ u64 reserved[9];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_modify_port [88 byte] */
+
+/**
+ * Test operations : EPSC_TEST_HOST_RD & EPSC_TEST_HOST_WR
+ */
+struct psif_epsc_csr_test_host_wrd {
+ struct psif_mmu_cntx mmu_cntx;
+ u64 host_addr;
+ u32 epsc_offs;
+ u32 length;
+ /* pattern number 0..xxx */
+ u32 pattern;
+ u32 noname:32;
+ u64 reserved_2[7];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_test_host_wrd [88 byte] */
+
+/**
+ * Flash programming: EPSC_FLASH_START, EPSC_FLASH_RD,
+ * EPSC_FLASH_WR & EPSC_FLASH_STOP
+ */
+struct psif_epsc_csr_flash_access {
+ u32 offset;
+ u32 length;
+ struct psif_mmu_cntx mmu_cntx;
+ u64 host_addr;
+ u64 crc;
+ u64 reserved[7];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_flash_access [88 byte] */
+
+/**
+ * IB packet trace acquire : EPSC_TRACE_ACQUIRE
+ *
+ */
+struct psif_epsc_csr_trace_acquire {
+ /* Pointer to trace buffer */
+ u64 host_addr;
+ /* Buffer offset in bytes */
+ u32 offset;
+ /* Buffer length in bytes */
+ u32 maxtrace;
+ /* MMU context supplied by driver */
+ struct psif_mmu_cntx mmu_cntx;
+ u64 padding[8];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_trace_acquire [88 byte] */
+
+/**
+ * EPSC_FW_VERSION
+ */
+struct psif_epsc_csr_fw_version {
+ struct psif_mmu_cntx mmu_cntx;
+ u64 host_addr;
+ u64 data;
+ u64 reserved[8];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_fw_version [88 byte] */
+
+struct psif_epsc_csr_log_ctrl {
+ struct psif_mmu_cntx mmu_cntx;
+ /* Log level to use */
+ enum psif_epsc_log_level level:32;
+
+ /* Log mode to use */
+ enum psif_epsc_log_mode mode:32;
+
+ /* Fields only used by log mode EPSC_LOG_MODE_HOST:
+ Start address of the data area to write to */
+ u64 base;
+ /* pointer to a log_stat data area */
+ u64 stat_base;
+ /* Length in bytes of the buffer */
+ u64 length;
+ u64 reserved_2[6];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_log_ctrl [88 byte] */
+
+/**
+ * EPS-A to EPS-C
+ */
+struct psif_epsc_csr_epsa_cntrl {
+ /* Operation */
+ enum psif_epsc_csr_epsa_command command:32;
+
+ /* Which EPS-A core */
+ enum psif_eps_a_core epsa:2;
+
+ u32 noname:30;
+ /* Offset within flash */
+ u64 flash_addr;
+ /* Address in EPS-A memory */
+ u64 epsa_addr;
+ u64 reserved[8];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_epsa_cntrl [88 byte] */
+
+/**
+ * EPS-A to EPS-A
+ */
+struct psif_epsc_csr_epsa_cmd {
+ enum psif_epsa_command cmd:32;
+
+ u32 length;
+ /* MMU context supplied by driver */
+ struct psif_mmu_cntx mmu_cntx;
+ /* Buffer adress in host memory */
+ u64 host_addr;
+ u8 entry_point[16];
+ u32 key;
+ u32 qpnum;
+ u64 reserved[5];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_epsa_cmd [88 byte] */
+
+/**
+ * EPSC_CLI_ACCESS - buffer size is assumed to be 4K
+ */
+struct psif_epsc_csr_cli_access {
+ u64 host_addr;
+ struct psif_mmu_cntx mmu_cntx;
+ u8 command[72];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_cli_access [88 byte] */
+
+/**
+ * EPSC_MAD_PROCESS:
+ */
+struct psif_epsc_csr_mad_process {
+ u64 host_addr;
+ struct psif_mmu_cntx mmu_cntx;
+ /* ib_reth_dmalen(32[0] bits)Direct Memory Access Length */
+ u32 byte_len;
+ enum psif_wc_opcode opcode:8;
+
+ /* ib_bth_qp_number(24[0] bits)Queue Pair */
+ u32 qp:24;
+ enum psif_wc_status status:8;
+
+ /* Only valid for UD QPs. */
+ u32 src_qp:24;
+ /* Flags indicating GRH and immediate presence.Only valid if not privileged. */
+ /* Inlined wc_flags : struct psif_wc_flags (64 bits) */
+ u16 wc_flags_grh:1;
+ u16 wc_flags_with_imm:1;
+ /* P-Key index from UD packet. */
+ u16 pkey_indx:9;
+ /* Only valid for UD QPs. */
+ u16 sl:4;
+ /* IB portnumber this packet was received on. Only valid if not privileged. */
+ enum psif_port port:1;
+
+ /*
+ * SLID taken from the received packet. This is only valid for UD QPs. Only
+ * valid if not privileged.
+ */
+ u16 slid;
+ /*
+ * Path bits (lower 7 bits) taken from the DLID in the received packet. This
+ * is only valid for UD QPs. Only valid if not privileged.
+ */
+ u64 dlid_path_bits:7;
+ u64 noname:57;
+ u64 reserved_2[6];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_mad_process [88 byte] */
+
+/**
+ * EPSC_MAD_SEND_WR:
+ */
+struct psif_epsc_csr_mad_send_wr {
+ u64 host_addr;
+ struct psif_mmu_cntx mmu_cntx;
+ u64 reserved[9];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_mad_send_wr [88 byte] */
+
+struct psif_epsc_query_req {
+ enum psif_epsc_query_op op:32;
+
+ u32 index;
+ /* Value for EPSC_SET operation */
+ u64 value;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_query_req [16 byte] */
+
+/**
+ * Structure for EPSC_QUERY
+ *
+ */
+struct psif_epsc_csr_query {
+ /* UF number */
+ u32 uf;
+ /* Future */
+ u32 noname:32;
+ /* Query destin for the response data field */
+ struct psif_epsc_query_req data;
+ /* Query destin for the response info field */
+ struct psif_epsc_query_req info;
+ u64 reserved[6];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_query [88 byte] */
+
+/**
+ * Structure for EPSC_SET
+ *
+ */
+struct psif_epsc_csr_set {
+ /* UF number */
+ u32 uf;
+ /* Future */
+ u32 noname:32;
+ /* Set destin for the response data field */
+ struct psif_epsc_query_req data;
+ /* Set destin for the response info field */
+ struct psif_epsc_query_req info;
+ u64 reserved[6];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_set [88 byte] */
+
+/**
+ * EPSC_HOST_INT_COMMON_CTRL - PF only
+ */
+struct psif_epsc_csr_interrupt_common {
+ /* Moderate total interrupt generation. How many usecs to delay. */
+ u64 total_usec:16;
+ u64 noname:48;
+ u64 reserved_2[10];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_interrupt_common [88 byte] */
+
+/**
+ * EPSC_HOST_INT_CHANNEL_CTRL - PF + VF
+ */
+struct psif_interrupt_attributes {
+ u64 enable_adaptive:1;
+ u64 channel_rx_scale:1;
+ u64 channel_rate_low:1;
+ u64 channel_rate_high:1;
+ u64 channel_ausec:1;
+ u64 channel_ausec_low:1;
+ u64 channel_ausec_high:1;
+ u64 channel_pusec:1;
+ u64 channel_pusec_low:1;
+ u64 channel_pusec_high:1;
+ u64 noname:54;
+} PSIF_PACKED_ALIGNED; /* struct psif_interrupt_attributes [ 8 byte] */
+
+struct psif_epsc_csr_interrupt_channel {
+ /* Mask of attributes to set */
+ struct psif_interrupt_attributes attributes;
+ /* EQ number */
+ u64 int_channel:16;
+ /* Set to 1 for adaptive coalescing */
+ u64 enable_adaptive:1;
+ /* Future */
+ u64 noname:31;
+ /* rx-to-tx timer scaling factor 2-exponent value */
+ u16 channel_rx_scale;
+ /* Message rate in messages per second. Low rate threshold. */
+ u32 channel_rate_low;
+ /* Message rate in messages per second. High rate threshold. */
+ u64 channel_rate_high:32;
+ /* How many usecs to delay after first packet. */
+ u16 channel_ausec;
+ /* How many usecs to delay after first packet. Low rate value. */
+ u16 channel_ausec_low;
+ /* How many usecs to delay after first packet. High rate value. */
+ u16 channel_ausec_high;
+ /* How many usecs to delay after packet. */
+ u16 channel_pusec;
+ /* How many usecs to delay after packet. Low rate value. */
+ u16 channel_pusec_low;
+ /* How many usecs to delay after packet. High rate value. */
+ u16 channel_pusec_high;
+ /* Align to 64 bit */
+ u32 noname1:32;
+ u64 reserved_2[6];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_interrupt_channel [88 byte] */
+
+union psif_epsc_update_set_or_offset {
+ u32 offset;
+ enum psif_epsc_update_set set:32;
+
+} PSIF_PACKED; /* union psif_epsc_update_set_or_offset [ 4 byte] */
+
+/**
+ * Flash update: EPSC_UPDATE
+ */
+struct psif_epsc_csr_update {
+ enum psif_epsc_csr_update_opcode opcode:16;
+
+ enum psif_epsc_flash_slot slot:16;
+
+ union psif_epsc_update_set_or_offset u;
+ u32 length;
+ u32 id;
+ struct psif_mmu_cntx mmu_cntx;
+ u64 host_addr;
+ u64 reserved[7];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_update [88 byte] */
+
+/**
+ * UF maintenance: EPSC_UF_CTRL
+ */
+struct psif_epsc_csr_uf_ctrl {
+ enum psif_epsc_csr_uf_ctrl_opcode opcode:32;
+
+ u32 flags;
+ u64 uf_vector;
+ u64 reserved[9];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_uf_ctrl [88 byte] */
+
+/* CSR automated type for TSU_MMU_FLUSH_CACHES */
+/* Flush MMU and-or PTW Caches. */
+struct psif_csr_mmu_flush_caches {
+ u64 noname:60;
+ u64 ptw_cache_flushed:1;
+ u64 mmu_cache_flushed:1;
+ u64 flush_ptw_cache:1;
+ u64 flush_mmu_cache:1;
+} PSIF_PACKED_ALIGNED; /* struct psif_csr_mmu_flush_caches [ 8 byte] */
+
+/**
+ * Flush MMU and-or PTW Caches: EPSC_FLUSH_CACHES
+ */
+struct psif_epsc_flush_caches {
+ struct psif_csr_mmu_flush_caches flush_mmu_caches;
+ u64 reserved[10];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_flush_caches [88 byte] */
+
+/**
+ * Structure for EPSC_PMA_COUNTERS
+ * Common structure for virtual port per UF and
+ * external (physical) port per vSwitch.
+ */
+struct psif_epsc_csr_pma_counters {
+ /* UF number */
+ u32 uf;
+ /**
+ * If MSB is set then it's a physical port number.
+ * Otherwise it's a virtual port number.
+ */
+ u32 port;
+ /* Base address in host memory */
+ u64 host_addr;
+ struct psif_mmu_cntx mmu_cntx;
+ /**
+ * Bitmask to indicate which counters to clear. Bit
+ * positions are based on the response structure's enum.
+ */
+ u64 clear_mask;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_pma_counters [32 byte] */
+
+/** \brief Command params for opcode EPSC_VIMMA_CTRL_SET_VFP_VHCA_DEREGISTER
+ \note
+ This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
+ \par Classification
+ external
+ */
+struct psif_epsc_vimma_dereg {
+ /* size 5*u64 */
+ u32 noname:32;
+ /* lowest uf index set in array below */
+ u16 low_uf;
+ /* highest uf index set in array below */
+ u16 high_uf;
+ /* allows multi UF setting. bit0 = UF0 bit1 = UF1 etc. */
+ u64 uf_vector[4];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_vimma_dereg [40 byte] */
+
+/** \brief Struct defintion for vHCA registration details
+ \note
+ This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
+ \par Classification
+ external
+ */
+struct psif_epsc_vimma_vfp_reg {
+ /* size 5*u64 */
+ u16 uf;
+ u16 noname:16;
+ u32 vm_context;
+ u8 vm_id[16];
+ u32 vm_incarnation;
+ u16 vhca_instance;
+ u16 noname1:16;
+ u64 noname2:64;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_vimma_vfp_reg [40 byte] */
+
+/** \brief Command params for opcode EPSC_VIMMA_CTRL_SET_ADMIN_MODE
+ \note
+ This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
+ \par Classification
+ external
+ */
+struct psif_epsc_vimma_set_admmode {
+ /* size 5*u64 */
+ enum psif_epsc_vimma_admmode mode:16;
+
+ u16 noname:16;
+ /* lowest uf index set in array below */
+ u16 low_uf;
+ /* highest uf index set in array below */
+ u16 high_uf;
+ /* allows multi UF setting. bit0 = UF0 bit1 = UF1 etc. */
+ u64 uf_vector[4];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_vimma_set_admmode [40 byte] */
+
+/** \brief Command params for opcode EPSC_VIMMA_CTRL_SET_VFP_VHCA_REGISTER
+ \note
+ This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_VFP_CAPS
+ \par Classification
+ external
+ */
+struct psif_epsc_vimma_reg_info {
+ u32 noname:32;
+ /* lowest uf index set in array below */
+ u16 low_uf;
+ /* highest uf index set in array below */
+ u16 high_uf;
+ /* allows multi UF setting. bit0 = UF0 bit1 = UF1 etc. */
+ u64 uf_vector[4];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_vimma_reg_info [40 byte] */
+
+/** \brief Defining params for VIMMA opcodes
+ \par Classification
+ external
+ */
+union psif_epsc_vimma_ctrl_cmd {
+ /* all union elements are size 5*u64 */
+ struct psif_epsc_vimma_dereg dereg;
+ struct psif_epsc_vimma_vfp_reg vfp_reg;
+ struct psif_epsc_vimma_set_admmode adm_mode;
+ struct psif_epsc_vimma_reg_info reg_info;
+} PSIF_PACKED; /* union psif_epsc_vimma_ctrl_cmd [40 byte] */
+
+/** \brief Defines the complete command params for VIMMA opcodes
+ \note
+ This struct belongs to capability: EPSC_VIMMA_CTRL_CAP_PSIF_BASIC_CAPS
+ and should never change in an incompatible way.
+ \par Classification
+ external
+ */
+struct psif_epsc_csr_vimma_ctrl {
+ /* VIMMA sub-opcodes triggered by EPSC_VIMMA_CTRL */
+ enum psif_epsc_vimma_ctrl_opcode opcode:32;
+
+ /* length of DMA response buffer pinned in host memory */
+ u32 length;
+ /* Size 5*64 bits: union of the params for the various opcodes */
+ union psif_epsc_vimma_ctrl_cmd u;
+ /* Size 64 bits */
+ struct psif_mmu_cntx mmu_cntx;
+ /* Place to DMA back longer responses during retrieval */
+ u64 host_addr;
+ /* Summing up to 11 * u64 which is total and max */
+ u64 reserved[3];
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_vimma_ctrl [88 byte] */
+
+/* Public API for mailbox requests details */
+union psif_epsc_csr_details {
+ /* Anonymous data */
+ struct psif_epsc_csr_opaque opaque;
+ /* Single data to write */
+ struct psif_epsc_csr_single single;
+ /* Descriptor base address */
+ struct psif_epsc_csr_base_addr base_addr;
+ /* Modify QP request */
+ struct psif_epsc_csr_modify_qp modify_qp;
+ /* Query QP */
+ struct psif_epsc_csr_query_qp query_qp;
+ /* Set LID entry (backdoor setup) */
+ struct psif_epsc_csr_set_lid set_lid;
+ /* Set GID entry (backdoor setup) */
+ struct psif_epsc_csr_set_gid set_gid;
+ /* Set EoIB MAC address (backdoor setup) */
+ struct psif_epsc_csr_set_eoib_mac set_eoib_mac;
+ /* Set vlink state */
+ struct psif_epsc_csr_vlink_state set_vlink;
+ /* Query HW state of device port or other */
+ struct psif_epsc_csr_query_hw query_hw;
+ /* Query table info pkey or gid */
+ struct psif_epsc_csr_query_table query_table;
+ /* MC subscription */
+ struct psif_epsc_csr_mc mc;
+ /* Asynchronous event */
+ struct psif_epsc_csr_event event;
+ /* EPSC_MODIFY_DEVICE */
+ struct psif_epsc_csr_modify_device device;
+ /* EPSC_MODIFY_PORT_{1 2} */
+ struct psif_epsc_csr_modify_port port;
+ /* EPSC_TEST_HOST_RD & EPSC_TEST_HOST_WR */
+ struct psif_epsc_csr_test_host_wrd host_wrd;
+ /* EPSC_FLASH_START EPSC_FLASH_RD EPSC_FLASH_WR & EPSC_FLASH_STOP */
+ struct psif_epsc_csr_flash_access flash;
+ /* EPSC_TRACE_ACQUIRE */
+ struct psif_epsc_csr_trace_acquire trace_acquire;
+ /* EPSC_FW_VERSION */
+ struct psif_epsc_csr_fw_version fw_version;
+ /* EPSC_LOG_CTRL */
+ struct psif_epsc_csr_log_ctrl log_ctrl;
+ /* Control epsa */
+ struct psif_epsc_csr_epsa_cntrl epsa_cntrl;
+ struct psif_epsc_csr_epsa_cmd epsa_cmd;
+ /* Issue commands to serial console */
+ struct psif_epsc_csr_cli_access cli;
+ /* Process incomming (QP 1) packet from host */
+ struct psif_epsc_csr_mad_process mad_process;
+ /* Send MAD formated WR to host for sending */
+ struct psif_epsc_csr_mad_send_wr mad_send_wr;
+ /* Single value query */
+ struct psif_epsc_csr_query query;
+ /* Single value set */
+ struct psif_epsc_csr_set set;
+ /* Setup interrupt control */
+ struct psif_epsc_csr_interrupt_common int_common;
+ struct psif_epsc_csr_interrupt_channel int_channel;
+ /* EPSC_UPDATE (update firmware) */
+ struct psif_epsc_csr_update update;
+ /* EPSC_UF_CTRL: UF maintenance functions */
+ struct psif_epsc_csr_uf_ctrl uf_ctrl;
+ /* EPSC_FLUSH_CACHES: Flush MMU and-or PTW Caches */
+ struct psif_epsc_flush_caches flush_caches;
+ /* PMA counters query */
+ struct psif_epsc_csr_pma_counters pma_counters;
+ /* EPSC_VIMMA_CTRL: VIMMA functions */
+ struct psif_epsc_csr_vimma_ctrl vimma_ctrl;
+} PSIF_PACKED; /* union psif_epsc_csr_details [88 byte] */
+
+/**
+ * The host sw to eps-c fw csr workrequest
+ *
+ * The EPSC will post the completion responses for request `#seq_num`
+ * into the completion queue at :
+ * `index = #seq_num % epsc_cq.base_addr.num_entries`
+ * as provided by the initial EPSC_SETUP work request:
+ */
+struct psif_epsc_csr_req {
+ enum psif_epsc_csr_opcode opcode:8;
+
+ enum psif_epsc_csr_flags flags:8;
+
+ /* Sequence number - included in response */
+ u16 seq_num;
+ /* UF - only valid for UF 0 - must be 0 otherwise */
+ u16 uf;
+ /* Data integrity */
+ u16 crc;
+ /* Register offset or port number */
+ u64 addr;
+ /* Operation specific data */
+ union psif_epsc_csr_details u;
+ u64 reserved[3];
+} PSIF_PACKED_ALIGNED32; /* struct psif_epsc_csr_req [128 byte] */
+
+/** Doorbel/mail-box register layout */
+struct psif_epsc_csr_doorbell {
+ /** Transfer index */
+ u64 head:16;
+ /** Payload or info */
+ u64 data:32;
+ /** Identical to head to assure 8 byte atomic write */
+ u16 tail;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_doorbell [ 8 byte] */
+
+/**
+ * Basic configuration data for each UF
+ */
+struct psif_epsc_csr_config {
+ /** Minor protocol version identifier. */
+ u32 minor_ver;
+ /** Major protocol version identifier. */
+ u32 major_ver;
+ /** Request base address. */
+ u64 request;
+ /** Respose base address. */
+ u64 response;
+ /** Number of entries in table. */
+ u32 entries;
+ /** Size of request entry. */
+ u16 extent_req;
+ /** Size of response entry. */
+ u16 extent_rsp;
+ /** MMU context for mailbox. */
+ struct psif_mmu_cntx mmu_cntx;
+ /** PCI access: setup for sparc memory layout (PF only). */
+ u64 sparc_pages:1;
+ /** PCI access: enable atomic support from SIF (PF only). */
+ enum psif_epsc_csr_atomic_op atomic_support:2;
+
+ /** Flush SIF pipeline similar to FLR (PF and VF). */
+ u64 clean_state:1;
+ /** PCI access: Select host endian memory layout (PF only). */
+ u64 big_endian:1;
+ /** VCB access: Exact length for scoreboard data copy (PF only). */
+ u64 vcb_exact:1;
+ /** Enable all VFs to receive SMPs at startup (PF only). */
+ u64 enable_vf_smp:1;
+ /** Connect all vlinks to external port (PF only). */
+ u64 vlink_connect:1;
+ /** Setup CMPL spin set mode to be fast - default is safe (PF only). */
+ u64 fast_spin:1;
+ /** Padded field. */
+ u64 noname:55;
+} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_config [48 byte] */
+
+/* This is the portion of the descriptor which is updated by software. */
+struct psif_cq_sw { /* Subjected to copy and convert */
+ /* Index to completion elements added by SW. */
+ u32 head_indx;
+ /* Info: Edge padding added (for endian convert) */
+ u32 space25;
+} PSIF_PACKED_ALIGNED; /* struct psif_cq_sw [ 8 byte] */
+
+/*
+ * Descriptor entry for a completion queue. This entry is used to address
+ * into the completion queue and write the correct entries. This structure is
+ * the hardware updateable part of the CQ descriptor.
+ */
+struct psif_cq_hw { /* Subjected to copy and convert */
+ /* Do not evict this entry if this bit is set. */
+ u32 sticky:1;
+ /*
+ * CQ notification states. The use of these are as defined in the description
+ * of the PSIF interrupt coalsecing scheme.
+ */
+ enum psif_cq_state cq_not_state:2;
+
+ /* The descriptor is valid. */
+ u32 valid:1;
+ /*
+ * Log2 size of the completion queue. Maximum number of entries in the
+ * completion queue. This is used for calculating when to wrap the head and
+ * tail indexes.
+ */
+ u32 size_log2:5;
+ /*
+ * If set, this completion queue is proxy enabled and should send completions
+ * to EPS core indicated by the eps_core field.
+ */
+ u32 proxy_en:1;
+ /*
+ * EPS-A core number completions are forwarded to if the proxy_enabled bit is
+ * set.
+ */
+ enum psif_eps_a_core eps_core:2;
+
+ /*
+ * Pre-fetch threshold (clog2) indicating when to read the software portion
+ * of the descriptor. If there are less entries than indicated by this
+ * threshold, the software portion of the descriptor must be read.
+ */
+ u32 prefetch_threshold_log2:5;
+ /* Reserved */
+ u32 noname:7;
+ /*
+ * Set by DSCR when CQ overrun async event is sent for this CQ. Not cleared
+ * before CQ is destroyed.
+ */
+ u32 cq_overrun_event_sent:1;
+ /*
+ * Interrupt channel associated with the event queue. In the PSIF design the
+ * event queues are one to one with interrupt channel.
+ */
+ u32 int_channel:7;
+ /* cq_max_msg(32[0] bits)Maximum message size in bytes. */
+ u32 max_size;
+ struct psif_mmu_cntx mmu_cntx;
+ /*
+ * VA or PA of the base of the completion queue. If PA the MMU context above
+ * will be a bypass context. Updated by software. The head and tail pointers
+ * can be calculated by the following calculations: Address = base_ptr +
+ * (head * ($bits(completion_entry_t)/8 ) Head Pointer and Tail Pointer will
+ * use the same MMU context as the base, and all need to be VA from one
+ * address space, or all need to be PA. In typical use, to allow direct user
+ * access to the head and tail pointer VAs are used.
+ */
+ u64 base_addr;
+ /* Index to completion elements to be consumed by HW. */
+ u32 tail_indx;
+ /*
+ * Completion queue sequence number. This is the sequence number to be used
+ * for this completion. When used by a client, it is incremented and written
+ * back to this descriptor.
+ */
+ u32 sequence_number;
+} PSIF_PACKED_ALIGNED; /* struct psif_cq_hw [32 byte] */
+
+/*
+ * Union between CQ sequence number and immediate date. CQ sequence number is
+ * only valid for privileged QP requests.
+ */
+union psif_seq_num_immdt {
+ /*
+ * Completion queue sequence number for arming of completion queues. This is
+ * the CQ sequence number for the completion queue which was armed.
+ */
+ u32 cq_sequence_number;
+ /* ib_immediate(32[0] bits)Immediate Data */
+ u32 imm;
+} PSIF_PACKED; /* union psif_seq_num_immdt [ 4 byte] */
+
+struct psif_offload_info {
+ /* RSS hash. Only valid if not privileged. */
+ u32 rss_hash;
+ /*
+ * Packet classification structure for offloading packets. Only valid if not
+ * privileged.
+ */
+ /* Inlined packet_classification : struct psif_packet_classification (64 bits) */
+ /*
+ * 0: means LLC_SNAP, 1: means Ethernet type 2. (L2 packet classification.)
+ * This field is applicable for EoIB only.
+ */
+ u32 packet_classification_eth2:1;
+ /* L3/L4 packet classification. */
+ /* Inlined packet_classification_ip_class : struct psif_ip_class (64 bits) */
+ /* This is set for IPv4 packets only. */
+ u32 packet_classification_ipv4:1;
+ /* This is set for IPv6 packets only. */
+ u32 packet_classification_ipv6:1;
+ /* IP fragment. */
+ u32 packet_classification_ip_frag:1;
+ /* IPv4 options or IPv6 extension headers present. */
+ u32 packet_classification_ip_options:1;
+ /* Packet is ARP */
+ u32 packet_classification_arp:1;
+ /* Packet is ARP reply */
+ u32 packet_classification_arp_reply:1;
+ /* Unsupported IPv6 extension headers detected. */
+ u32 packet_classification_ip6_unsupported_exthdr:1;
+ /* L4 is TCP. */
+ u32 packet_classification_tcp:1;
+ /* L4 is UDP. */
+ u32 packet_classification_udp:1;
+ /*
+ * L3 checksum calculated ok. This is either an IPv6 packet or a correctly
+ * checksummed IPv4 header. Only valid if not privileged.
+ */
+ u32 l3_checksum_ok:1;
+ /*
+ * L4 checksum calculated ok. This is either correct TCP/UDP checksum or UDP
+ * checksum not generated by the transmitter. Only valid if not privileged.
+ */
+ u32 l4_checksum_ok:1;
+ /*
+ * Original UF for QP0/1 packets going to the EPS-C. Only valid if not
+ * privileged.
+ */
+ u32 orig_uf:6;
+ /* This is set if the packet was a DR packet. Only valid if not privileged. */
+ u32 is_dr:1;
+ /*
+ * When valid, header/data split is performed and the header length is given
+ * in hdr_length.
+ */
+ /* Inlined hdr_split : struct psif_hdr_split_offload (64 bits) */
+ /* The header length is valid for header/data split offloading. */
+ u32 hdr_split_valid:1;
+ /*
+ * Header length used for header/data split offloading. The length of this
+ * header is added to one scatter element.
+ */
+ u32 hdr_split_hdr_length:9;
+ /*
+ * Receive Tossed Packet. PSIF thought there was something wrong with this
+ * offloaded packet so it should be tossed.
+ */
+ u32 rtp:1;
+ /*
+ * This bit is set if the incoming request is a conditional RDMA WR w/Imm
+ * which is not written to memory.
+ */
+ u32 not_written:1;
+ /* Reserved */
+ u32 noname:1;
+} PSIF_PACKED_ALIGNED; /* struct psif_offload_info [ 8 byte] */
+
+/*
+ * Union - offload is valid for normal QPs. For privileged QPs, it is the WC
+ * ID needed to completed if outstanding is set.
+ */
+union psif_offload_wc_id {
+ /*
+ * This is used if this is a privileged commend INVALIDATE_SGL_CACHE.
+ * Software must figure out if this WC_ID is valid or not.
+ */
+ union psif_completion_wc_id wc_id;
+ /* This countain offload or PSIF specific infornation. */
+ struct psif_offload_info offload;
+} PSIF_PACKED; /* union psif_offload_wc_id [ 8 byte] */
+
+/*
+ * Completion entry. A completion entry written to host memory, will be
+ * padded out to 64 bytes. The last 4 bytes will contain a completion queue
+ * sequence number.
+ */
+struct psif_cq_entry { /* Subjected to copy and convert */
+ /*
+ * Work queue completion ID. For receive completions this is the entry number
+ * in the receive queue and the receive queue descriptor index. For send
+ * completions this is the sq_sequence number.
+ */
+ union psif_completion_wc_id wc_id;
+ /* Length of message. Only valid if not privileged. */
+ u32 byte_len;
+ enum psif_wc_opcode opcode:8;
+
+ /* ib_bth_qp_number(24[0] bits)Queue Pair */
+ u32 qp:24;
+ union psif_seq_num_immdt seq_num_imm;
+ enum psif_wc_status status:8;
+
+ /* Only valid for UD QPs. */
+ u32 src_qp:24;
+ u16 grh:1;
+ u16 with_imm:1;
+ /* P-Key index from UD packet. */
+ u16 pkey_indx:9;
+ /* Only valid for UD QPs. */
+ u16 sl:4;
+ /* IB portnumber this packet was received on. Only valid if not privileged. */
+ enum psif_port port:1;
+
+ /*
+ * SLID taken from the received packet. This is only valid for UD QPs. Only
+ * valid if not privileged.
+ */
+ u16 slid;
+ /*
+ * Path bits (lower 7 bits) taken from the DLID in the received packet. This
+ * is only valid for UD QPs. Only valid if not privileged.
+ */
+ u32 dlid_path_bits:7;
+ /*
+ * Checksum with error. This is not inverted for UDP if zero result from
+ * check. It can be either a full or partial checksum. Only valid if not
+ * privileged.
+ */
+ u32 error_checksum:16;
+ enum psif_tsu_error_types vendor_err:8;
+
+ /* RSS source. Only valid if not privileged. */
+ enum psif_rss_hash_source rss_hash_src:1;
+
+ /*
+ * For normal QPs, this is offload information. For privileged QPs, this is
+ * WC ID for in progress RQE.
+ */
+ union psif_offload_wc_id offload_wc_id;
+ /* Flags indicating GRH and immediate presence.Only valid if not privileged. */
+ /* Inlined wc_flags : struct psif_wc_flags (64 bits) */
+ /* Padding out struct bulk */
+ u64 reserved[2];
+ /* Padding out struct last */
+ u32 noname:32;
+ /* sequence number for sanity checking */
+ u32 seq_num;
+} PSIF_PACKED_ALIGNED; /* struct psif_cq_entry [64 byte] */
+
+/* Generic CSR */
+struct psif_csr_generic {
+ u64 data;
+} PSIF_PACKED_ALIGNED; /* struct psif_csr_generic [ 8 byte] */
+
+/* Compact Base Address Register format. Not for use in register definitions. */
+struct psif_base_addr { /* Subjected to copy and convert */
+ /* host_address(64[0] bits)Host address used for accesses to/from TSU HOST. */
+ u64 address;
+ struct psif_mmu_cntx mmu_context;
+ /* Number of entries in table. */
+ u32 num_entries;
+ /* Manually added spacing to pad out base addr */
+ u32 :27;
+ /*
+ * clog2_extent used for entry alignment. This field used to calculate
+ * address for a particular entry. Address to an entry is calculated as
+ * follows: host_addr + entry_num*(1 (leftshift) clog2_extent)
+ */
+ u32 extent_log2:5;
+} PSIF_PACKED_ALIGNED; /* struct psif_base_addr [24 byte] */
+
+/* Retry data for one atomic request. Layout per BugZilla 3710 */
+struct psif_atomic_retry_element {
+ /* [255:192] response atomic data */
+ u64 orig_data;
+ /* [191:184] padding. always zero */
+ u32 zero:8;
+ /* [183:160] psn */
+ u32 psn:24;
+ /* [159] When set to one entry has been used. When set to zero
+ no duplicate has been written in this entry. */
+ u32 used:1;
+ /* [158] This atomic response was in error. */
+ u32 response_error:1;
+ /* [157:0] Padding. Always set to zero. */
+ u32 padding:30;
+ u64 reserved[2];
+} PSIF_PACKED_ALIGNED; /* struct psif_atomic_retry_element [32 byte] */
+
+/* Data type for TSU_HOST_QP_BASE_ADDR - atomic replay scratch pad
+ * Layout as of 16 deep atomic queue - elements padded to 32 byte
+ */
+struct psif_atsp {
+ struct psif_atomic_retry_element retry[16];
+} PSIF_PACKED_ALIGNED; /* struct psif_atsp [512 byte] */
+
+/*
+ * Address handle array entry used for sending UD packets. The structure
+ * contains information about the destination for a request.
+ */
+struct psif_ah { /* Subjected to copy and convert */
+ u64 grh_remote_gid_0;
+ u64 grh_remote_gid_1;
+ /* Inlined grh : struct psif_grh (192 bits) */
+ /* ib_grh_flowl(20[0] bits)Flow Label */
+ u64 grh_flowlabel:20;
+ /* ib_grh_tclass(8[0] bits)Traffic Class */
+ u64 grh_tclass:8;
+ /* ib_grh_hoplmt(8[0] bits)Hop Limit */
+ u64 grh_hoplmt:8;
+ /* Reserved */
+ u64 noname:4;
+ /* ib_lrh_sl(4[0] bits)Service Level */
+ u64 sl:4;
+ enum psif_use_grh use_grh:1;
+
+ enum psif_loopback loopback:1;
+
+ enum psif_port port:1;
+
+ /* gid_indx(1[0] bits)GID index indicating which of the UFs two GIDs are used. */
+ u64 gid_indx:1;
+ /* ib_lrh_lid(16[0] bits)Local ID */
+ u16 remote_lid;
+ /* Reserved */
+ u64 noname1:9;
+ /* ib_lrh_lid_path_bits(7[0] bits)Path bits for the LID. Used as the least signficant bits in a LID */
+ u64 local_lid_path:7;
+ /* Reserved */
+ u64 noname2:8;
+ /* ipd(8[0] bits)Inter packet delay. Encoded as specified in IB spec. */
+ u64 ipd:8;
+ /*
+ * The protection domain is checked against the protection domain in the QP
+ * state. As long as they are equal, the QP is allowed to use this AHA entry.
+ */
+ u64 pd:24;
+ /* Reserved */
+ u64 noname3:8;
+} PSIF_PACKED_ALIGNED; /* struct psif_ah [32 byte] */
+
+/* CSR automated type for TSU_IBPR_P{1,2}_EOIB_MAC1 */
+/* Per vHCA + EPS-C ethernet MAC address register. */
+struct psif_csr_ibpr_eoib_mac1 {
+ u64 noname:15;
+ u64 valid:1;
+ u64 mac1:48;
+} PSIF_PACKED_ALIGNED; /* struct psif_csr_ibpr_eoib_mac1 [ 8 byte] */
+
+
+
+#endif /* _PSIF_HW_DATA_H_BE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_macro.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,673 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PSIF_HW_MACRO_H
+#define _PSIF_HW_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "psif_api.h"
+
+#include "psif_endian.h"
+#if !defined(__KERNEL__)
+#include "os_header.h"
+#endif
+
+
+/*
+ * PSIF_WR_INVALIDATE_LKEY: key to invalidate/flush from the DMA VT cache.
+ * PSIF_WR_INVALIDATE_RKEY: key to invalidate/flush from the DMA VT cache.
+ * PSIF_WR_INVALIDATE_BOTH_KEYS: key to invalidate/flush from the DMA VT
+ * cache. PSIF_WR_INVALIDATE_TLB: this is the address vector to invalidate in
+ * the TLB.
+ */
+#define PSIF_WR_SU_KEY_OFFSET 2
+#define PSIF_WR_SU_2_KEY_SHIFT 32
+#define PSIF_WR_SU_2_KEY_BITS 32
+#define PSIF_WR_SU_2_KEY_MASK 0xffffffff00000000ull
+
+/*
+ * Send queue sequence number. Used to map request to a particular work
+ * request in the send queue.
+ */
+#define PSIF_WR_SQ_SEQ_OFFSET 0
+#define PSIF_WR_SQ_SEQ_SHIFT 0
+#define PSIF_WR_SQ_SEQ_BITS 16
+#define PSIF_WR_SQ_SEQ_MASK 0x000000000000ffffull
+
+/*
+ * QP sending this request. XXX: Should name be own_qp_num as defined in QP
+ * state?
+ */
+#define PSIF_WR_LOCAL_QP_OFFSET 0
+#define PSIF_WR_LOCAL_QP_SHIFT 32
+#define PSIF_WR_LOCAL_QP_BITS 24
+#define PSIF_WR_LOCAL_QP_MASK 0x00ffffff00000000ull
+
+/* Completion notification identifier. */
+#define PSIF_WR_COMPLETION_OFFSET 1
+#define PSIF_WR_1_COMPLETION_BIT_POSITION 31
+#define PSIF_WR_1_COMPLETION_BIT 0x0000000080000000ull
+
+/*
+ * Checksum used for data protection and consistency between work request and
+ * QP state.
+ */
+#define PSIF_WR_CHECKSUM_OFFSET 2
+#define PSIF_WR_2_CHECKSUM_SHIFT 32
+#define PSIF_WR_2_CHECKSUM_BITS 32
+#define PSIF_WR_2_CHECKSUM_MASK 0xffffffff00000000ull
+
+/*
+ * Index to where elements are added to the send queue by SW. SW is
+ * responsibel for keeping track of how many entries there are in the send
+ * queue. I.e. SW needs to keep track of the head_index so it doesn't
+ * overwrite entries in the send queue which is not yet completed.
+ */
+#define PSIF_SQ_SW_TAIL_INDX_OFFSET 0
+#define PSIF_SQ_SW_TAIL_INDX_SHIFT 32
+#define PSIF_SQ_SW_TAIL_INDX_BITS 16
+#define PSIF_SQ_SW_TAIL_INDX_MASK 0x0000ffff00000000ull
+
+/*
+ * Send queue sequence number used by the SQS to maintain ordering and keep
+ * track of where which send queue elements to fetch. This field is not in
+ * sync with the field in qp_t. This number is typically a little bit before
+ * the number in the qp_t as SQS has to fetch the elements from host memory.
+ * This is also used as tail_index when checking if there are more elements
+ * in the send queue.
+ */
+#define PSIF_SQ_HW_LAST_SEQ_OFFSET 0
+#define PSIF_SQ_HW_LAST_SEQ_SHIFT 16
+#define PSIF_SQ_HW_LAST_SEQ_BITS 16
+#define PSIF_SQ_HW_LAST_SEQ_MASK 0x00000000ffff0000ull
+
+/* QP and UF to be processed next. */
+#define PSIF_SQ_HW_SQ_NEXT_OFFSET 0
+#define PSIF_SQ_HW_SQ_NEXT_SHIFT 32
+#define PSIF_SQ_HW_SQ_NEXT_BITS 32
+#define PSIF_SQ_HW_SQ_NEXT_MASK 0xffffffff00000000ull
+
+/*
+ * This bit is set through the doorbell. SW should check this bit plus
+ * psif_next = null to ensure SW can own the SQ descriptor.
+ */
+#define PSIF_SQ_HW_DESTROYED_OFFSET 1
+#define PSIF_SQ_HW_1_DESTROYED_BIT_POSITION 27
+#define PSIF_SQ_HW_1_DESTROYED_BIT 0x0000000008000000ull
+
+/* Software modified index pointing to the tail reecive entry in host memory. */
+#define PSIF_RQ_SW_TAIL_INDX_OFFSET 0
+#define PSIF_RQ_SW_TAIL_INDX_SHIFT 32
+#define PSIF_RQ_SW_TAIL_INDX_BITS 14
+#define PSIF_RQ_SW_TAIL_INDX_MASK 0x00003fff00000000ull
+
+/*
+ * Hardware modified index pointing to the head of the receive queue. TSU is
+ * using this to find the address of the receive queue entry.
+ */
+#define PSIF_RQ_HW_HEAD_INDX_OFFSET 0
+#define PSIF_RQ_HW_HEAD_INDX_SHIFT 14
+#define PSIF_RQ_HW_HEAD_INDX_BITS 14
+#define PSIF_RQ_HW_HEAD_INDX_MASK 0x000000000fffc000ull
+
+/* The desciptor is valid. */
+#define PSIF_RQ_HW_VALID_OFFSET 3
+#define PSIF_RQ_HW_3_VALID_BIT_POSITION 55
+#define PSIF_RQ_HW_3_VALID_BIT 0x0080000000000000ull
+
+/*
+ * Receive queue entry ID. This is added to the receive completion using this
+ * receive queue entry.
+ */
+#define PSIF_RQ_ENTRY_RQE_ID_OFFSET 0
+#define PSIF_RQ_ENTRY_RQE_ID_SHIFT 0
+#define PSIF_RQ_ENTRY_RQE_ID_BITS 64
+#define PSIF_RQ_ENTRY_RQE_ID_MASK 0xffffffffffffffffull
+
+/*
+ * This retry tag is the one used by tsu_rqs and added to the packets sent to
+ * tsu_dma. It is the responsibility of tsu_rqs to update this retry tag
+ * whenever the sq_sequence_number in QP state is equal to the one in the
+ * request.
+ */
+#define PSIF_QP_CORE_RETRY_TAG_COMMITTED_OFFSET 0
+#define PSIF_QP_CORE_RETRY_TAG_COMMITTED_SHIFT 0
+#define PSIF_QP_CORE_RETRY_TAG_COMMITTED_BITS 3
+#define PSIF_QP_CORE_RETRY_TAG_COMMITTED_MASK 0x0000000000000007ull
+
+/*
+ * This retry tag is updated by the error block when an error occur. If
+ * tsu_rqs reads this retry tag and it is different than the
+ * retry_tag_comitted, tsu_rqs must update retry_tag_comitted to the value of
+ * retry_tag_err when the sq_sequence_number indicates this is the valid
+ * request. The sq_sequence_number has been updated by tsu_err at the same
+ * time the retry_tag_err is updated.
+ */
+#define PSIF_QP_CORE_RETRY_TAG_ERR_OFFSET 0
+#define PSIF_QP_CORE_RETRY_TAG_ERR_SHIFT 3
+#define PSIF_QP_CORE_RETRY_TAG_ERR_BITS 3
+#define PSIF_QP_CORE_RETRY_TAG_ERR_MASK 0x0000000000000038ull
+
+/*
+ * Error retry counter initial value. Read by tsu_dma and used by tsu_cmpl to
+ * calculate exp_backoff etc..
+ */
+#define PSIF_QP_CORE_ERROR_RETRY_INIT_OFFSET 0
+#define PSIF_QP_CORE_ERROR_RETRY_INIT_SHIFT 32
+#define PSIF_QP_CORE_ERROR_RETRY_INIT_BITS 3
+#define PSIF_QP_CORE_ERROR_RETRY_INIT_MASK 0x0000000700000000ull
+
+/*
+ * Retry counter associated with retries to received NAK or implied NAK. If
+ * it expires, a path migration will be attempted if it is armed, or the QP
+ * will go to error state. Read by tsu_dma and used by tsu_cmpl.
+ */
+#define PSIF_QP_CORE_ERROR_RETRY_COUNT_OFFSET 0
+#define PSIF_QP_CORE_ERROR_RETRY_COUNT_SHIFT 35
+#define PSIF_QP_CORE_ERROR_RETRY_COUNT_BITS 3
+#define PSIF_QP_CORE_ERROR_RETRY_COUNT_MASK 0x0000003800000000ull
+
+/* A hit in the set locally spun out of tsu_cmpl is found. */
+#define PSIF_QP_CORE_SPIN_HIT_OFFSET 0
+#define PSIF_QP_CORE_SPIN_HIT_BIT_POSITION 39
+#define PSIF_QP_CORE_SPIN_HIT_BIT 0x0000008000000000ull
+
+/*
+ * Minium RNR NAK timeout. This is added to RNR NAK packets and the requester
+ * receiving the RNR NAK must wait until the timer has expired before the
+ * retry is sent.
+ */
+#define PSIF_QP_CORE_MIN_RNR_NAK_TIME_OFFSET 1
+#define PSIF_QP_CORE_1_MIN_RNR_NAK_TIME_SHIFT 0
+#define PSIF_QP_CORE_1_MIN_RNR_NAK_TIME_BITS 5
+#define PSIF_QP_CORE_1_MIN_RNR_NAK_TIME_MASK 0x000000000000001full
+
+/* QP State for this QP. */
+#define PSIF_QP_CORE_STATE_OFFSET 1
+#define PSIF_QP_CORE_1_STATE_SHIFT 5
+#define PSIF_QP_CORE_1_STATE_BITS 3
+#define PSIF_QP_CORE_1_STATE_MASK 0x00000000000000e0ull
+
+/* QP number for the remote node. */
+#define PSIF_QP_CORE_REMOTE_QP_OFFSET 1
+#define PSIF_QP_CORE_1_REMOTE_QP_SHIFT 8
+#define PSIF_QP_CORE_1_REMOTE_QP_BITS 24
+#define PSIF_QP_CORE_1_REMOTE_QP_MASK 0x00000000ffffff00ull
+
+#define PSIF_QP_CORE_RETRY_SQ_SEQ_OFFSET 2
+#define PSIF_QP_CORE_2_RETRY_SQ_SEQ_SHIFT 32
+#define PSIF_QP_CORE_2_RETRY_SQ_SEQ_BITS 16
+#define PSIF_QP_CORE_2_RETRY_SQ_SEQ_MASK 0x0000ffff00000000ull
+
+#define PSIF_QP_CORE_SQ_SEQ_OFFSET 2
+#define PSIF_QP_CORE_2_SQ_SEQ_SHIFT 48
+#define PSIF_QP_CORE_2_SQ_SEQ_BITS 16
+#define PSIF_QP_CORE_2_SQ_SEQ_MASK 0xffff000000000000ull
+
+/*
+ * Magic number used to verify use of QP state. This is done by calculating a
+ * checksum of the work request incorporating the magic number. This checksum
+ * is checked against the checksum in the work request.
+ */
+#define PSIF_QP_CORE_MAGIC_OFFSET 3
+#define PSIF_QP_CORE_3_MAGIC_SHIFT 0
+#define PSIF_QP_CORE_3_MAGIC_BITS 32
+#define PSIF_QP_CORE_3_MAGIC_MASK 0x00000000ffffffffull
+
+/*
+ * Q-Key received in incoming IB packet is checked towards this Q-Key. Q-Key
+ * used on transmit if top bit of Q-Key in WR is set.
+ */
+#define PSIF_QP_CORE_QKEY_OFFSET 4
+#define PSIF_QP_CORE_4_QKEY_SHIFT 0
+#define PSIF_QP_CORE_4_QKEY_BITS 32
+#define PSIF_QP_CORE_4_QKEY_MASK 0x00000000ffffffffull
+
+/*
+ * Sequence number of the last ACK received. Read and written by tsu_cmpl.
+ * Used to verify that the received response packet is a valid response.
+ */
+#define PSIF_QP_CORE_LAST_ACKED_PSN_OFFSET 4
+#define PSIF_QP_CORE_4_LAST_ACKED_PSN_SHIFT 40
+#define PSIF_QP_CORE_4_LAST_ACKED_PSN_BITS 24
+#define PSIF_QP_CORE_4_LAST_ACKED_PSN_MASK 0xffffff0000000000ull
+
+/* Index to scatter element of in progress SEND. */
+#define PSIF_QP_CORE_SCATTER_INDX_OFFSET 5
+#define PSIF_QP_CORE_5_SCATTER_INDX_SHIFT 32
+#define PSIF_QP_CORE_5_SCATTER_INDX_BITS 5
+#define PSIF_QP_CORE_5_SCATTER_INDX_MASK 0x0000001f00000000ull
+
+/*
+ * Expected packet sequence number: Sequence number on next expected packet.
+ */
+#define PSIF_QP_CORE_EXPECTED_PSN_OFFSET 5
+#define PSIF_QP_CORE_5_EXPECTED_PSN_SHIFT 40
+#define PSIF_QP_CORE_5_EXPECTED_PSN_BITS 24
+#define PSIF_QP_CORE_5_EXPECTED_PSN_MASK 0xffffff0000000000ull
+
+/*
+ * TSU quality of service level. Can take values indicating low latency and
+ * high throughput. This is equivalent to high/low BAR when writing doorbells
+ * to PSIF. The qosl bit in the doorbell request must match this bit in the
+ * QP state, otherwise the QP must be put in error. This check only applies
+ * to tsu_rqs.
+ */
+#define PSIF_QP_CORE_QOSL_OFFSET 6
+#define PSIF_QP_CORE_6_QOSL_BIT_POSITION 49
+#define PSIF_QP_CORE_6_QOSL_BIT 0x0002000000000000ull
+
+/*
+ * Migration state (migrated, re-arm and armed). Since path migration is
+ * handled by tsu_qps, this is controlled by tsu_qps. XXX: Should error
+ * handler also be able to change the path?
+ */
+#define PSIF_QP_CORE_MSTATE_OFFSET 6
+#define PSIF_QP_CORE_6_MSTATE_SHIFT 50
+#define PSIF_QP_CORE_6_MSTATE_BITS 2
+#define PSIF_QP_CORE_6_MSTATE_MASK 0x000c000000000000ull
+
+/* This is an IB over IB QP. */
+#define PSIF_QP_CORE_IPOIB_ENABLE_OFFSET 6
+#define PSIF_QP_CORE_6_IPOIB_ENABLE_BIT_POSITION 53
+#define PSIF_QP_CORE_6_IPOIB_ENABLE_BIT 0x0020000000000000ull
+
+/* IB defined capability enable for receiving Atomic operations. */
+#define PSIF_QP_CORE_ATOMIC_ENABLE_OFFSET 6
+#define PSIF_QP_CORE_6_ATOMIC_ENABLE_BIT_POSITION 61
+#define PSIF_QP_CORE_6_ATOMIC_ENABLE_BIT 0x2000000000000000ull
+
+/* IB defined capability enable for receiving RDMA WR. */
+#define PSIF_QP_CORE_RDMA_WR_ENABLE_OFFSET 6
+#define PSIF_QP_CORE_6_RDMA_WR_ENABLE_BIT_POSITION 62
+#define PSIF_QP_CORE_6_RDMA_WR_ENABLE_BIT 0x4000000000000000ull
+
+/* IB defined capability enable for receiving RDMA RD. */
+#define PSIF_QP_CORE_RDMA_RD_ENABLE_OFFSET 6
+#define PSIF_QP_CORE_6_RDMA_RD_ENABLE_BIT_POSITION 63
+#define PSIF_QP_CORE_6_RDMA_RD_ENABLE_BIT 0x8000000000000000ull
+
+/*
+ * Transmit packet sequence number. Read and updated by tsu_dma before
+ * sending packets to tsu_ibpb and tsu_cmpl.
+ */
+#define PSIF_QP_CORE_XMIT_PSN_OFFSET 7
+#define PSIF_QP_CORE_7_XMIT_PSN_SHIFT 0
+#define PSIF_QP_CORE_7_XMIT_PSN_BITS 24
+#define PSIF_QP_CORE_7_XMIT_PSN_MASK 0x0000000000ffffffull
+
+/*
+ * TSU Service Level used to decide the TSU VL for requests associated with
+ * this QP.
+ */
+#define PSIF_QP_CORE_TSL_OFFSET 7
+#define PSIF_QP_CORE_7_TSL_SHIFT 55
+#define PSIF_QP_CORE_7_TSL_BITS 4
+#define PSIF_QP_CORE_7_TSL_MASK 0x0780000000000000ull
+
+/*
+ * Maximum number of outstanding read or atomic requests allowed by the
+ * remote HCA. Initialized by software.
+ */
+#define PSIF_QP_CORE_MAX_OUTSTANDING_OFFSET 7
+#define PSIF_QP_CORE_7_MAX_OUTSTANDING_SHIFT 59
+#define PSIF_QP_CORE_7_MAX_OUTSTANDING_BITS 5
+#define PSIF_QP_CORE_7_MAX_OUTSTANDING_MASK 0xf800000000000000ull
+
+/* Send Queue RNR retry count initialization value. */
+#define PSIF_QP_CORE_RNR_RETRY_INIT_OFFSET 8
+#define PSIF_QP_CORE_8_RNR_RETRY_INIT_SHIFT 32
+#define PSIF_QP_CORE_8_RNR_RETRY_INIT_BITS 3
+#define PSIF_QP_CORE_8_RNR_RETRY_INIT_MASK 0x0000000700000000ull
+
+/*
+ * Retry counter associated with RNR NAK retries. If it expires, a path
+ * migration will be attempted if it is armed, or the QP will go to error
+ * state.
+ */
+#define PSIF_QP_CORE_RNR_RETRY_COUNT_OFFSET 8
+#define PSIF_QP_CORE_8_RNR_RETRY_COUNT_SHIFT 35
+#define PSIF_QP_CORE_8_RNR_RETRY_COUNT_BITS 3
+#define PSIF_QP_CORE_8_RNR_RETRY_COUNT_MASK 0x0000003800000000ull
+
+/*
+ * When set, RQS should only check that the orig_checksum is equal to magic
+ * number. When not set, RQS should perform the checksum check towards the
+ * checksum in the psif_wr.
+ */
+#define PSIF_QP_CORE_NO_CHECKSUM_OFFSET 8
+#define PSIF_QP_CORE_8_NO_CHECKSUM_BIT_POSITION 39
+#define PSIF_QP_CORE_8_NO_CHECKSUM_BIT 0x0000008000000000ull
+
+/*
+ * Transport type of the QP (RC, UC, UD, XRC, MANSP1). MANSP1 is set for
+ * privileged QPs.
+ */
+#define PSIF_QP_CORE_TRANSPORT_TYPE_OFFSET 9
+#define PSIF_QP_CORE_9_TRANSPORT_TYPE_SHIFT 0
+#define PSIF_QP_CORE_9_TRANSPORT_TYPE_BITS 3
+#define PSIF_QP_CORE_9_TRANSPORT_TYPE_MASK 0x0000000000000007ull
+
+/*
+ * Number of bytes received of in progress RDMA Write or SEND. The data
+ * received for SENDs and RDMA WR w/Imm are needed for completions. This
+ * should be added to the msg_length.
+ */
+#define PSIF_QP_CORE_BYTES_RECEIVED_OFFSET 9
+#define PSIF_QP_CORE_9_BYTES_RECEIVED_SHIFT 32
+#define PSIF_QP_CORE_9_BYTES_RECEIVED_BITS 32
+#define PSIF_QP_CORE_9_BYTES_RECEIVED_MASK 0xffffffff00000000ull
+
+/* This QP is running IP over IB. */
+#define PSIF_QP_CORE_IPOIB_OFFSET 10
+#define PSIF_QP_CORE_10_IPOIB_BIT_POSITION 5
+#define PSIF_QP_CORE_10_IPOIB_BIT 0x0000000000000020ull
+
+/*
+ * Combined 'Last Received MSN' and 'Last Outstanding MSN', used to maintain
+ * 'spin set floor' and indicate 'all retries completed', respectively.
+ */
+#define PSIF_QP_CORE_LAST_RECEIVED_OUTSTANDING_MSN_OFFSET 11
+#define PSIF_QP_CORE_11_LAST_RECEIVED_OUTSTANDING_MSN_SHIFT 0
+#define PSIF_QP_CORE_11_LAST_RECEIVED_OUTSTANDING_MSN_BITS 16
+#define PSIF_QP_CORE_11_LAST_RECEIVED_OUTSTANDING_MSN_MASK 0x000000000000ffffull
+
+#define PSIF_QP_CORE_PATH_MTU_OFFSET 13
+#define PSIF_QP_CORE_13_PATH_MTU_SHIFT 4
+#define PSIF_QP_CORE_13_PATH_MTU_BITS 3
+#define PSIF_QP_CORE_13_PATH_MTU_MASK 0x0000000000000070ull
+
+/* This PSN is committed - ACKs sent will contain this PSN. */
+#define PSIF_QP_CORE_COMMITTED_RECEIVED_PSN_OFFSET 13
+#define PSIF_QP_CORE_13_COMMITTED_RECEIVED_PSN_SHIFT 8
+#define PSIF_QP_CORE_13_COMMITTED_RECEIVED_PSN_BITS 24
+#define PSIF_QP_CORE_13_COMMITTED_RECEIVED_PSN_MASK 0x00000000ffffff00ull
+
+/*
+ * Message sequence number used in AETH when sending ACKs. The number is
+ * incremented every time a new inbound message is processed.
+ */
+#define PSIF_QP_CORE_MSN_OFFSET 14
+#define PSIF_QP_CORE_14_MSN_SHIFT 0
+#define PSIF_QP_CORE_14_MSN_BITS 24
+#define PSIF_QP_CORE_14_MSN_MASK 0x0000000000ffffffull
+
+/*
+ * This is an index to send completion queue descriptor. The descriptor
+ * points to a send completion queue, which may or may not be the same as the
+ * send completion queue.
+ */
+#define PSIF_QP_CORE_SEND_CQ_INDX_OFFSET 14
+#define PSIF_QP_CORE_14_SEND_CQ_INDX_SHIFT 24
+#define PSIF_QP_CORE_14_SEND_CQ_INDX_BITS 24
+#define PSIF_QP_CORE_14_SEND_CQ_INDX_MASK 0x0000ffffff000000ull
+
+/*
+ * Committed MSN - the MSN of the newest committed request for this QP. Only
+ * the bottom 16 bits of the MSN is used.
+ */
+#define PSIF_QP_CORE_LAST_COMMITTED_MSN_OFFSET 14
+#define PSIF_QP_CORE_14_LAST_COMMITTED_MSN_SHIFT 48
+#define PSIF_QP_CORE_14_LAST_COMMITTED_MSN_BITS 16
+#define PSIF_QP_CORE_14_LAST_COMMITTED_MSN_MASK 0xffff000000000000ull
+
+#define PSIF_QP_CORE_SRQ_PD_OFFSET 15
+#define PSIF_QP_CORE_15_SRQ_PD_SHIFT 0
+#define PSIF_QP_CORE_15_SRQ_PD_BITS 24
+#define PSIF_QP_CORE_15_SRQ_PD_MASK 0x0000000000ffffffull
+
+#define PSIF_QP_PATH_REMOTE_GID_0_OFFSET 0
+#define PSIF_QP_PATH_REMOTE_GID_0_SHIFT 0
+#define PSIF_QP_PATH_REMOTE_GID_0_BITS 64
+#define PSIF_QP_PATH_REMOTE_GID_0_MASK 0xffffffffffffffffull
+
+#define PSIF_QP_PATH_REMOTE_GID_1_OFFSET 1
+#define PSIF_QP_PATH_1_REMOTE_GID_1_SHIFT 0
+#define PSIF_QP_PATH_1_REMOTE_GID_1_BITS 64
+#define PSIF_QP_PATH_1_REMOTE_GID_1_MASK 0xffffffffffffffffull
+
+#define PSIF_QP_PATH_REMOTE_LID_OFFSET 2
+#define PSIF_QP_PATH_2_REMOTE_LID_SHIFT 0
+#define PSIF_QP_PATH_2_REMOTE_LID_BITS 16
+#define PSIF_QP_PATH_2_REMOTE_LID_MASK 0x000000000000ffffull
+
+#define PSIF_QP_PATH_PORT_OFFSET 2
+#define PSIF_QP_PATH_2_PORT_BIT_POSITION 17
+#define PSIF_QP_PATH_2_PORT_BIT 0x0000000000020000ull
+
+#define PSIF_QP_PATH_LOOPBACK_OFFSET 2
+#define PSIF_QP_PATH_2_LOOPBACK_BIT_POSITION 18
+#define PSIF_QP_PATH_2_LOOPBACK_BIT 0x0000000000040000ull
+
+#define PSIF_QP_PATH_USE_GRH_OFFSET 2
+#define PSIF_QP_PATH_2_USE_GRH_BIT_POSITION 19
+#define PSIF_QP_PATH_2_USE_GRH_BIT 0x0000000000080000ull
+
+#define PSIF_QP_PATH_SL_OFFSET 2
+#define PSIF_QP_PATH_2_SL_SHIFT 20
+#define PSIF_QP_PATH_2_SL_BITS 4
+#define PSIF_QP_PATH_2_SL_MASK 0x0000000000f00000ull
+
+#define PSIF_QP_PATH_HOPLMT_OFFSET 2
+#define PSIF_QP_PATH_2_HOPLMT_SHIFT 28
+#define PSIF_QP_PATH_2_HOPLMT_BITS 8
+#define PSIF_QP_PATH_2_HOPLMT_MASK 0x0000000ff0000000ull
+
+#define PSIF_QP_PATH_FLOWLABEL_OFFSET 2
+#define PSIF_QP_PATH_2_FLOWLABEL_SHIFT 44
+#define PSIF_QP_PATH_2_FLOWLABEL_BITS 20
+#define PSIF_QP_PATH_2_FLOWLABEL_MASK 0xfffff00000000000ull
+
+#define PSIF_QP_PATH_LOCAL_ACK_TIMEOUT_OFFSET 3
+#define PSIF_QP_PATH_3_LOCAL_ACK_TIMEOUT_SHIFT 27
+#define PSIF_QP_PATH_3_LOCAL_ACK_TIMEOUT_BITS 5
+#define PSIF_QP_PATH_3_LOCAL_ACK_TIMEOUT_MASK 0x00000000f8000000ull
+
+#define PSIF_QP_PATH_IPD_OFFSET 3
+#define PSIF_QP_PATH_3_IPD_SHIFT 32
+#define PSIF_QP_PATH_3_IPD_BITS 8
+#define PSIF_QP_PATH_3_IPD_MASK 0x000000ff00000000ull
+
+/*
+ * This is the LID path bits. This is used by tsu_ibpb when generating the
+ * SLID in the packet, and it is used by tsu_rcv when checking the DLID.
+ */
+#define PSIF_QP_PATH_LOCAL_LID_PATH_OFFSET 3
+#define PSIF_QP_PATH_3_LOCAL_LID_PATH_SHIFT 48
+#define PSIF_QP_PATH_3_LOCAL_LID_PATH_BITS 7
+#define PSIF_QP_PATH_3_LOCAL_LID_PATH_MASK 0x007f000000000000ull
+
+#define PSIF_QP_PATH_PKEY_INDX_OFFSET 3
+#define PSIF_QP_PATH_3_PKEY_INDX_SHIFT 55
+#define PSIF_QP_PATH_3_PKEY_INDX_BITS 9
+#define PSIF_QP_PATH_3_PKEY_INDX_MASK 0xff80000000000000ull
+
+/* L-key state for this DMA validation entry */
+#define PSIF_KEY_LKEY_STATE_OFFSET 0
+#define PSIF_KEY_LKEY_STATE_SHIFT 60
+#define PSIF_KEY_LKEY_STATE_BITS 2
+#define PSIF_KEY_LKEY_STATE_MASK 0x3000000000000000ull
+
+/* R-key state for this DMA validation entry */
+#define PSIF_KEY_RKEY_STATE_OFFSET 0
+#define PSIF_KEY_RKEY_STATE_SHIFT 62
+#define PSIF_KEY_RKEY_STATE_BITS 2
+#define PSIF_KEY_RKEY_STATE_MASK 0xc000000000000000ull
+
+/* Length of memory region this validation entry is associated with. */
+#define PSIF_KEY_LENGTH_OFFSET 1
+#define PSIF_KEY_1_LENGTH_SHIFT 0
+#define PSIF_KEY_1_LENGTH_BITS 64
+#define PSIF_KEY_1_LENGTH_MASK 0xffffffffffffffffull
+
+#define PSIF_KEY_MMU_CONTEXT_OFFSET 2
+#define PSIF_KEY_2_MMU_CONTEXT_SHIFT 0
+#define PSIF_KEY_2_MMU_CONTEXT_BITS 64
+#define PSIF_KEY_2_MMU_CONTEXT_MASK 0xffffffffffffffffull
+
+#define PSIF_KEY_BASE_ADDR_OFFSET 3
+#define PSIF_KEY_3_BASE_ADDR_SHIFT 0
+#define PSIF_KEY_3_BASE_ADDR_BITS 64
+#define PSIF_KEY_3_BASE_ADDR_MASK 0xffffffffffffffffull
+
+/* sequence number for sanity checking */
+#define PSIF_EQ_ENTRY_SEQ_NUM_OFFSET 7
+#define PSIF_EQ_ENTRY_7_SEQ_NUM_SHIFT 0
+#define PSIF_EQ_ENTRY_7_SEQ_NUM_BITS 32
+#define PSIF_EQ_ENTRY_7_SEQ_NUM_MASK 0x00000000ffffffffull
+
+/* enum psif_epsc_csr_opcode from request */
+#define PSIF_EPSC_CSR_RSP_OPCODE_OFFSET 0
+#define PSIF_EPSC_CSR_RSP_OPCODE_SHIFT 48
+#define PSIF_EPSC_CSR_RSP_OPCODE_BITS 8
+#define PSIF_EPSC_CSR_RSP_OPCODE_MASK 0x00ff000000000000ull
+
+/* Sequence number from request */
+#define PSIF_EPSC_CSR_RSP_SEQ_NUM_OFFSET 3
+#define PSIF_EPSC_CSR_RSP_3_SEQ_NUM_SHIFT 0
+#define PSIF_EPSC_CSR_RSP_3_SEQ_NUM_BITS 64
+#define PSIF_EPSC_CSR_RSP_3_SEQ_NUM_MASK 0xffffffffffffffffull
+
+/* Sequence number - included in response */
+#define PSIF_EPSC_CSR_REQ_SEQ_NUM_OFFSET 0
+#define PSIF_EPSC_CSR_REQ_SEQ_NUM_SHIFT 32
+#define PSIF_EPSC_CSR_REQ_SEQ_NUM_BITS 16
+#define PSIF_EPSC_CSR_REQ_SEQ_NUM_MASK 0x0000ffff00000000ull
+
+#define PSIF_EPSC_CSR_REQ_OPCODE_OFFSET 0
+#define PSIF_EPSC_CSR_REQ_OPCODE_SHIFT 56
+#define PSIF_EPSC_CSR_REQ_OPCODE_BITS 8
+#define PSIF_EPSC_CSR_REQ_OPCODE_MASK 0xff00000000000000ull
+
+/* Index to completion elements added by SW. */
+#define PSIF_CQ_SW_HEAD_INDX_OFFSET 0
+#define PSIF_CQ_SW_HEAD_INDX_SHIFT 32
+#define PSIF_CQ_SW_HEAD_INDX_BITS 32
+#define PSIF_CQ_SW_HEAD_INDX_MASK 0xffffffff00000000ull
+
+/*
+ * EPS-A core number completions are forwarded to if the proxy_enabled bit is
+ * set.
+ */
+#define PSIF_CQ_HW_EPS_CORE_OFFSET 0
+#define PSIF_CQ_HW_EPS_CORE_SHIFT 52
+#define PSIF_CQ_HW_EPS_CORE_BITS 2
+#define PSIF_CQ_HW_EPS_CORE_MASK 0x0030000000000000ull
+
+/*
+ * If set, this completion queue is proxy enabled and should send completions
+ * to EPS core indicated by the eps_core field.
+ */
+#define PSIF_CQ_HW_PROXY_EN_OFFSET 0
+#define PSIF_CQ_HW_PROXY_EN_BIT_POSITION 54
+#define PSIF_CQ_HW_PROXY_EN_BIT 0x0040000000000000ull
+
+/* The descriptor is valid. */
+#define PSIF_CQ_HW_VALID_OFFSET 0
+#define PSIF_CQ_HW_VALID_BIT_POSITION 60
+#define PSIF_CQ_HW_VALID_BIT 0x1000000000000000ull
+
+/*
+ * VA or PA of the base of the completion queue. If PA the MMU context above
+ * will be a bypass context. Updated by software. The head and tail pointers
+ * can be calculated by the following calculations: Address = base_ptr +
+ * (head * ($bits(completion_entry_t)/8 ) Head Pointer and Tail Pointer will
+ * use the same MMU context as the base, and all need to be VA from one
+ * address space, or all need to be PA. In typical use, to allow direct user
+ * access to the head and tail pointer VAs are used.
+ */
+#define PSIF_CQ_HW_BASE_ADDR_OFFSET 2
+#define PSIF_CQ_HW_2_BASE_ADDR_SHIFT 0
+#define PSIF_CQ_HW_2_BASE_ADDR_BITS 64
+#define PSIF_CQ_HW_2_BASE_ADDR_MASK 0xffffffffffffffffull
+
+/* Index to completion elements to be consumed by HW. */
+#define PSIF_CQ_HW_TAIL_INDX_OFFSET 3
+#define PSIF_CQ_HW_3_TAIL_INDX_SHIFT 32
+#define PSIF_CQ_HW_3_TAIL_INDX_BITS 32
+#define PSIF_CQ_HW_3_TAIL_INDX_MASK 0xffffffff00000000ull
+
+/*
+ * Work queue completion ID. For receive completions this is the entry number
+ * in the receive queue and the receive queue descriptor index. For send
+ * completions this is the sq_sequence number.
+ */
+#define PSIF_CQ_ENTRY_WC_ID_OFFSET 0
+#define PSIF_CQ_ENTRY_WC_ID_SHIFT 0
+#define PSIF_CQ_ENTRY_WC_ID_BITS 64
+#define PSIF_CQ_ENTRY_WC_ID_MASK 0xffffffffffffffffull
+
+#define PSIF_CQ_ENTRY_QP_OFFSET 1
+#define PSIF_CQ_ENTRY_1_QP_SHIFT 0
+#define PSIF_CQ_ENTRY_1_QP_BITS 24
+#define PSIF_CQ_ENTRY_1_QP_MASK 0x0000000000ffffffull
+
+#define PSIF_CQ_ENTRY_OPCODE_OFFSET 1
+#define PSIF_CQ_ENTRY_1_OPCODE_SHIFT 24
+#define PSIF_CQ_ENTRY_1_OPCODE_BITS 8
+#define PSIF_CQ_ENTRY_1_OPCODE_MASK 0x00000000ff000000ull
+
+#define PSIF_CQ_ENTRY_STATUS_OFFSET 2
+#define PSIF_CQ_ENTRY_2_STATUS_SHIFT 24
+#define PSIF_CQ_ENTRY_2_STATUS_BITS 8
+#define PSIF_CQ_ENTRY_2_STATUS_MASK 0x00000000ff000000ull
+
+/* sequence number for sanity checking */
+#define PSIF_CQ_ENTRY_SEQ_NUM_OFFSET 7
+#define PSIF_CQ_ENTRY_7_SEQ_NUM_SHIFT 0
+#define PSIF_CQ_ENTRY_7_SEQ_NUM_BITS 32
+#define PSIF_CQ_ENTRY_7_SEQ_NUM_MASK 0x00000000ffffffffull
+
+#define PSIF_AH_REMOTE_LID_OFFSET 2
+#define PSIF_AH_2_REMOTE_LID_SHIFT 0
+#define PSIF_AH_2_REMOTE_LID_BITS 16
+#define PSIF_AH_2_REMOTE_LID_MASK 0x000000000000ffffull
+
+#define PSIF_AH_SL_OFFSET 2
+#define PSIF_AH_2_SL_SHIFT 20
+#define PSIF_AH_2_SL_BITS 4
+#define PSIF_AH_2_SL_MASK 0x0000000000f00000ull
+#if defined (HOST_LITTLE_ENDIAN)
+#elif defined (HOST_BIG_ENDIAN)
+#else
+#error "Could not determine byte order in psif_hw_macro.h !?"
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _PSIF_HW_MACRO_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_print.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PSIF_HW_PRINT_H
+#define _PSIF_HW_PRINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "psif_api.h"
+
+#include "psif_hw_data.h"
+#if !defined(XFILE)
+#define XFILE FILE
+#endif
+
+void write_bits_u8(XFILE *fd, int extent, u8 data);
+void write_bits_u16(XFILE *fd, int extent, u16 data);
+void write_bits_u32(XFILE *fd, int extent, u32 data);
+void write_bits_u64(XFILE *fd, int extent, u64 data);
+const char* string_enum_psif_mmu_translation(enum psif_mmu_translation val);
+void write_enum_psif_mmu_translation(XFILE *fd, enum psif_mmu_translation data);
+const char* string_enum_psif_page_size(enum psif_page_size val);
+void write_enum_psif_page_size(XFILE *fd, enum psif_page_size data);
+const char* string_enum_psif_wr_type(enum psif_wr_type val);
+void write_enum_psif_wr_type(XFILE *fd, enum psif_wr_type data);
+const char* string_enum_psif_port(enum psif_port val);
+void write_enum_psif_port(XFILE *fd, enum psif_port data);
+const char* string_enum_psif_use_ah(enum psif_use_ah val);
+void write_enum_psif_use_ah(XFILE *fd, enum psif_use_ah data);
+const char* string_enum_psif_tsu_qos(enum psif_tsu_qos val);
+void write_enum_psif_tsu_qos(XFILE *fd, enum psif_tsu_qos data);
+const char* string_enum_psif_wc_opcode(enum psif_wc_opcode val);
+void write_enum_psif_wc_opcode(XFILE *fd, enum psif_wc_opcode data);
+const char* string_enum_psif_wc_status(enum psif_wc_status val);
+void write_enum_psif_wc_status(XFILE *fd, enum psif_wc_status data);
+const char* string_enum_ib_opcode(enum ib_opcode val);
+void write_enum_ib_opcode(XFILE *fd, enum ib_opcode data);
+const char* string_enum_psif_eps_a_core(enum psif_eps_a_core val);
+void write_enum_psif_eps_a_core(XFILE *fd, enum psif_eps_a_core data);
+const char* string_enum_psif_qp_state(enum psif_qp_state val);
+void write_enum_psif_qp_state(XFILE *fd, enum psif_qp_state data);
+const char* string_enum_psif_cmpl_outstanding_error(enum psif_cmpl_outstanding_error val);
+void write_enum_psif_cmpl_outstanding_error(XFILE *fd, enum psif_cmpl_outstanding_error data);
+const char* string_enum_psif_expected_op(enum psif_expected_op val);
+void write_enum_psif_expected_op(XFILE *fd, enum psif_expected_op data);
+const char* string_enum_psif_migration(enum psif_migration val);
+void write_enum_psif_migration(XFILE *fd, enum psif_migration data);
+const char* string_enum_psif_qp_trans(enum psif_qp_trans val);
+void write_enum_psif_qp_trans(XFILE *fd, enum psif_qp_trans data);
+const char* string_enum_psif_bool(enum psif_bool val);
+void write_enum_psif_bool(XFILE *fd, enum psif_bool data);
+const char* string_enum_psif_eoib_type(enum psif_eoib_type val);
+void write_enum_psif_eoib_type(XFILE *fd, enum psif_eoib_type data);
+const char* string_enum_psif_comm_live(enum psif_comm_live val);
+void write_enum_psif_comm_live(XFILE *fd, enum psif_comm_live data);
+const char* string_enum_psif_path_mtu(enum psif_path_mtu val);
+void write_enum_psif_path_mtu(XFILE *fd, enum psif_path_mtu data);
+const char* string_enum_psif_use_grh(enum psif_use_grh val);
+void write_enum_psif_use_grh(XFILE *fd, enum psif_use_grh data);
+const char* string_enum_psif_loopback(enum psif_loopback val);
+void write_enum_psif_loopback(XFILE *fd, enum psif_loopback data);
+const char* string_enum_psif_qp_command(enum psif_qp_command val);
+void write_enum_psif_qp_command(XFILE *fd, enum psif_qp_command data);
+const char* string_enum_psif_mbox_type(enum psif_mbox_type val);
+void write_enum_psif_mbox_type(XFILE *fd, enum psif_mbox_type data);
+const char* string_enum_psif_dma_vt_key_states(enum psif_dma_vt_key_states val);
+void write_enum_psif_dma_vt_key_states(XFILE *fd, enum psif_dma_vt_key_states data);
+const char* string_enum_psif_flash_image_type(enum psif_flash_image_type val);
+void write_enum_psif_flash_image_type(XFILE *fd, enum psif_flash_image_type data);
+const char* string_enum_psif_event(enum psif_event val);
+void write_enum_psif_event(XFILE *fd, enum psif_event data);
+const char* string_enum_psif_tsu_error_types(enum psif_tsu_error_types val);
+void write_enum_psif_tsu_error_types(XFILE *fd, enum psif_tsu_error_types data);
+const char* string_enum_psif_eps_core_id(enum psif_eps_core_id val);
+void write_enum_psif_eps_core_id(XFILE *fd, enum psif_eps_core_id data);
+const char* string_enum_psif_epsc_log_mode(enum psif_epsc_log_mode val);
+void write_enum_psif_epsc_log_mode(XFILE *fd, enum psif_epsc_log_mode data);
+const char* string_enum_psif_epsc_log_level(enum psif_epsc_log_level val);
+void write_enum_psif_epsc_log_level(XFILE *fd, enum psif_epsc_log_level data);
+const char* string_enum_psif_epsc_port_state(enum psif_epsc_port_state val);
+void write_enum_psif_epsc_port_state(XFILE *fd, enum psif_epsc_port_state data);
+const char* string_enum_psif_epsc_interrupt_source(enum psif_epsc_interrupt_source val);
+void write_enum_psif_epsc_interrupt_source(XFILE *fd, enum psif_epsc_interrupt_source data);
+const char* string_enum_psif_epsc_interrupt_pri(enum psif_epsc_interrupt_pri val);
+void write_enum_psif_epsc_interrupt_pri(XFILE *fd, enum psif_epsc_interrupt_pri data);
+const char* string_enum_psif_epsc_csr_status(enum psif_epsc_csr_status val);
+void write_enum_psif_epsc_csr_status(XFILE *fd, enum psif_epsc_csr_status data);
+const char* string_enum_psif_epsc_csr_opcode(enum psif_epsc_csr_opcode val);
+void write_enum_psif_epsc_csr_opcode(XFILE *fd, enum psif_epsc_csr_opcode data);
+const char* string_enum_psif_epsc_csr_flags(enum psif_epsc_csr_flags val);
+void write_enum_psif_epsc_csr_flags(XFILE *fd, enum psif_epsc_csr_flags data);
+const char* string_enum_psif_vlink_state(enum psif_vlink_state val);
+void write_enum_psif_vlink_state(XFILE *fd, enum psif_vlink_state data);
+const char* string_enum_psif_epsc_csr_modify_device_flags(enum psif_epsc_csr_modify_device_flags val);
+void write_enum_psif_epsc_csr_modify_device_flags(XFILE *fd, enum psif_epsc_csr_modify_device_flags data);
+const char* string_enum_psif_epsc_csr_modify_port_flags(enum psif_epsc_csr_modify_port_flags val);
+void write_enum_psif_epsc_csr_modify_port_flags(XFILE *fd, enum psif_epsc_csr_modify_port_flags data);
+const char* string_enum_psif_epsc_csr_epsa_command(enum psif_epsc_csr_epsa_command val);
+void write_enum_psif_epsc_csr_epsa_command(XFILE *fd, enum psif_epsc_csr_epsa_command data);
+const char* string_enum_psif_epsa_command(enum psif_epsa_command val);
+void write_enum_psif_epsa_command(XFILE *fd, enum psif_epsa_command data);
+const char* string_enum_psif_epsc_query_op(enum psif_epsc_query_op val);
+void write_enum_psif_epsc_query_op(XFILE *fd, enum psif_epsc_query_op data);
+const char* string_enum_psif_epsc_csr_update_opcode(enum psif_epsc_csr_update_opcode val);
+void write_enum_psif_epsc_csr_update_opcode(XFILE *fd, enum psif_epsc_csr_update_opcode data);
+const char* string_enum_psif_epsc_flash_slot(enum psif_epsc_flash_slot val);
+void write_enum_psif_epsc_flash_slot(XFILE *fd, enum psif_epsc_flash_slot data);
+const char* string_enum_psif_epsc_update_set(enum psif_epsc_update_set val);
+void write_enum_psif_epsc_update_set(XFILE *fd, enum psif_epsc_update_set data);
+const char* string_enum_psif_epsc_csr_uf_ctrl_opcode(enum psif_epsc_csr_uf_ctrl_opcode val);
+void write_enum_psif_epsc_csr_uf_ctrl_opcode(XFILE *fd, enum psif_epsc_csr_uf_ctrl_opcode data);
+const char* string_enum_psif_epsc_vimma_ctrl_opcode(enum psif_epsc_vimma_ctrl_opcode val);
+void write_enum_psif_epsc_vimma_ctrl_opcode(XFILE *fd, enum psif_epsc_vimma_ctrl_opcode data);
+const char* string_enum_psif_epsc_vimma_admmode(enum psif_epsc_vimma_admmode val);
+void write_enum_psif_epsc_vimma_admmode(XFILE *fd, enum psif_epsc_vimma_admmode data);
+const char* string_enum_psif_cq_state(enum psif_cq_state val);
+void write_enum_psif_cq_state(XFILE *fd, enum psif_cq_state data);
+const char* string_enum_psif_rss_hash_source(enum psif_rss_hash_source val);
+void write_enum_psif_rss_hash_source(XFILE *fd, enum psif_rss_hash_source data);
+
+#if !defined(PSIF_EXCLUDE_WRITE_STRUCTS)
+
+void write_struct_psif_mmu_cntx(XFILE *fd, int network_order, const struct psif_mmu_cntx *data);
+void write_struct_psif_vlan_union_struct(XFILE *fd, int network_order, const struct psif_vlan_union_struct *data);
+void write_union_psif_cq_desc_vlan_pri(XFILE *fd, int network_order, const union psif_cq_desc_vlan_pri *data);
+void write_struct_psif_wr_common(XFILE *fd, int network_order, const struct psif_wr_common *data);
+void write_struct_psif_wr_qp(XFILE *fd, int network_order, const struct psif_wr_qp *data);
+void write_struct_psif_wr_local(XFILE *fd, int network_order, const struct psif_wr_local *data);
+void write_struct_psif_wr_addr(XFILE *fd, int network_order, const struct psif_wr_addr *data);
+void write_struct_psif_wr_send_header_ud(XFILE *fd, int network_order, const struct psif_wr_send_header_ud *data);
+void write_struct_psif_wr_send_header_uc_rc_xrc(XFILE *fd, int network_order, const struct psif_wr_send_header_uc_rc_xrc *data);
+void write_union_psif_wr_send_header(XFILE *fd, int network_order, const union psif_wr_send_header *data);
+void write_struct_psif_wr_remote(XFILE *fd, int network_order, const struct psif_wr_remote *data);
+void write_struct_psif_wr_rdma(XFILE *fd, int network_order, const struct psif_wr_rdma *data);
+void write_struct_psif_send_completion_id(XFILE *fd, int network_order, const struct psif_send_completion_id *data);
+void write_struct_psif_event_completion_id(XFILE *fd, int network_order, const struct psif_event_completion_id *data);
+void write_union_psif_completion_wc_id(XFILE *fd, int network_order, const union psif_completion_wc_id *data);
+void write_union_psif_descriptor_union(XFILE *fd, int network_order, const union psif_descriptor_union *data);
+void write_struct_psif_wr_su(XFILE *fd, int network_order, const struct psif_wr_su *data);
+void write_union_psif_wr_details(XFILE *fd, int network_order, const union psif_wr_details *data);
+void write_struct_psif_wr_xrc(XFILE *fd, int network_order, const struct psif_wr_xrc *data);
+void write_struct_psif_wr(XFILE *fd, int network_order, const struct psif_wr *data);
+void write_struct_psif_wr_expand(XFILE *fd, int network_order, const struct psif_wr *data);
+void write_struct_psif_next(XFILE *fd, int network_order, const struct psif_next *data);
+void write_struct_psif_sq_sw(XFILE *fd, int network_order, const struct psif_sq_sw *data);
+void write_struct_psif_sq_hw(XFILE *fd, int network_order, const struct psif_sq_hw *data);
+void write_struct_psif_sq_entry(XFILE *fd, int network_order, const struct psif_sq_entry *data);
+void write_struct_psif_rq_scatter(XFILE *fd, int network_order, const struct psif_rq_scatter *data);
+void write_struct_psif_rq_sw(XFILE *fd, int network_order, const struct psif_rq_sw *data);
+void write_struct_psif_rq_hw(XFILE *fd, int network_order, const struct psif_rq_hw *data);
+void write_struct_psif_rq_entry(XFILE *fd, int network_order, const struct psif_rq_entry *data);
+void write_struct_psif_qp_core(XFILE *fd, int network_order, const struct psif_qp_core *data);
+void write_struct_psif_qp_path(XFILE *fd, int network_order, const struct psif_qp_path *data);
+void write_struct_psif_query_qp(XFILE *fd, int network_order, const struct psif_query_qp *data);
+void write_struct_psif_qp(XFILE *fd, int network_order, const struct psif_qp *data);
+void write_struct_psif_cb(XFILE *fd, int network_order, const struct psif_cb *data);
+void write_struct_psif_modify_qp(XFILE *fd, int network_order, const struct psif_modify_qp *data);
+void write_struct_psif_key(XFILE *fd, int network_order, const struct psif_key *data);
+void write_struct_psif_flash_header_app(XFILE *fd, int network_order, const struct psif_flash_header_app *data);
+void write_struct_psif_flash_header_all(XFILE *fd, int network_order, const struct psif_flash_header_all *data);
+void write_struct_psif_eq_entry(XFILE *fd, int network_order, const struct psif_eq_entry *data);
+void write_struct_psif_epsc_exercise_mmu(XFILE *fd, int network_order, const struct psif_epsc_exercise_mmu *data);
+void write_struct_psif_epsc_csr_rsp(XFILE *fd, int network_order, const struct psif_epsc_csr_rsp *data);
+void write_struct_psif_epsc_csr_opaque(XFILE *fd, int network_order, const struct psif_epsc_csr_opaque *data);
+void write_struct_psif_epsc_csr_single(XFILE *fd, int network_order, const struct psif_epsc_csr_single *data);
+void write_struct_psif_epsc_csr_base_addr(XFILE *fd, int network_order, const struct psif_epsc_csr_base_addr *data);
+void write_struct_psif_csr_modify_qp_ctrl(XFILE *fd, int network_order, const struct psif_csr_modify_qp_ctrl *data);
+void write_struct_psif_epsc_csr_modify_qp(XFILE *fd, int network_order, const struct psif_epsc_csr_modify_qp *data);
+void write_struct_psif_epsc_csr_query_qp(XFILE *fd, int network_order, const struct psif_epsc_csr_query_qp *data);
+void write_struct_psif_csr_own_lid_base(XFILE *fd, int network_order, const struct psif_csr_own_lid_base *data);
+void write_struct_psif_csr_snd_lid(XFILE *fd, int network_order, const struct psif_csr_snd_lid *data);
+void write_struct_psif_csr_rcv_lid(XFILE *fd, int network_order, const struct psif_csr_rcv_lid *data);
+void write_struct_psif_epsc_csr_set_lid(XFILE *fd, int network_order, const struct psif_epsc_csr_set_lid *data);
+void write_struct_psif_epsc_csr_set_gid(XFILE *fd, int network_order, const struct psif_epsc_csr_set_gid *data);
+void write_struct_psif_epsc_csr_set_eoib_mac(XFILE *fd, int network_order, const struct psif_epsc_csr_set_eoib_mac *data);
+void write_struct_psif_epsc_csr_vlink_state(XFILE *fd, int network_order, const struct psif_epsc_csr_vlink_state *data);
+void write_struct_psif_epsc_csr_query_hw(XFILE *fd, int network_order, const struct psif_epsc_csr_query_hw *data);
+void write_struct_psif_epsc_csr_query_table(XFILE *fd, int network_order, const struct psif_epsc_csr_query_table *data);
+void write_struct_psif_epsc_csr_mc(XFILE *fd, int network_order, const struct psif_epsc_csr_mc *data);
+void write_struct_psif_epsc_csr_event(XFILE *fd, int network_order, const struct psif_epsc_csr_event *data);
+void write_struct_psif_epsc_csr_modify_device(XFILE *fd, int network_order, const struct psif_epsc_csr_modify_device *data);
+void write_struct_psif_epsc_csr_modify_port(XFILE *fd, int network_order, const struct psif_epsc_csr_modify_port *data);
+void write_struct_psif_epsc_csr_test_host_wrd(XFILE *fd, int network_order, const struct psif_epsc_csr_test_host_wrd *data);
+void write_struct_psif_epsc_csr_flash_access(XFILE *fd, int network_order, const struct psif_epsc_csr_flash_access *data);
+void write_struct_psif_epsc_csr_trace_acquire(XFILE *fd, int network_order, const struct psif_epsc_csr_trace_acquire *data);
+void write_struct_psif_epsc_csr_fw_version(XFILE *fd, int network_order, const struct psif_epsc_csr_fw_version *data);
+void write_struct_psif_epsc_csr_log_ctrl(XFILE *fd, int network_order, const struct psif_epsc_csr_log_ctrl *data);
+void write_struct_psif_epsc_csr_epsa_cntrl(XFILE *fd, int network_order, const struct psif_epsc_csr_epsa_cntrl *data);
+void write_struct_psif_epsc_csr_epsa_cmd(XFILE *fd, int network_order, const struct psif_epsc_csr_epsa_cmd *data);
+void write_struct_psif_epsc_csr_cli_access(XFILE *fd, int network_order, const struct psif_epsc_csr_cli_access *data);
+void write_struct_psif_epsc_csr_mad_process(XFILE *fd, int network_order, const struct psif_epsc_csr_mad_process *data);
+void write_struct_psif_epsc_csr_mad_send_wr(XFILE *fd, int network_order, const struct psif_epsc_csr_mad_send_wr *data);
+void write_struct_psif_epsc_query_req(XFILE *fd, int network_order, const struct psif_epsc_query_req *data);
+void write_struct_psif_epsc_csr_query(XFILE *fd, int network_order, const struct psif_epsc_csr_query *data);
+void write_struct_psif_epsc_csr_set(XFILE *fd, int network_order, const struct psif_epsc_csr_set *data);
+void write_struct_psif_epsc_csr_interrupt_common(XFILE *fd, int network_order, const struct psif_epsc_csr_interrupt_common *data);
+void write_struct_psif_interrupt_attributes(XFILE *fd, int network_order, const struct psif_interrupt_attributes *data);
+void write_struct_psif_epsc_csr_interrupt_channel(XFILE *fd, int network_order, const struct psif_epsc_csr_interrupt_channel *data);
+void write_union_psif_epsc_update_set_or_offset(XFILE *fd, int network_order, const union psif_epsc_update_set_or_offset *data);
+void write_struct_psif_epsc_csr_update(XFILE *fd, int network_order, const struct psif_epsc_csr_update *data);
+void write_struct_psif_epsc_csr_uf_ctrl(XFILE *fd, int network_order, const struct psif_epsc_csr_uf_ctrl *data);
+void write_struct_psif_csr_mmu_flush_caches(XFILE *fd, int network_order, const struct psif_csr_mmu_flush_caches *data);
+void write_struct_psif_epsc_flush_caches(XFILE *fd, int network_order, const struct psif_epsc_flush_caches *data);
+void write_struct_psif_epsc_csr_pma_counters(XFILE *fd, int network_order, const struct psif_epsc_csr_pma_counters *data);
+void write_struct_psif_epsc_vimma_dereg(XFILE *fd, int network_order, const struct psif_epsc_vimma_dereg *data);
+void write_struct_psif_epsc_vimma_vfp_reg(XFILE *fd, int network_order, const struct psif_epsc_vimma_vfp_reg *data);
+void write_struct_psif_epsc_vimma_set_admmode(XFILE *fd, int network_order, const struct psif_epsc_vimma_set_admmode *data);
+void write_struct_psif_epsc_vimma_reg_info(XFILE *fd, int network_order, const struct psif_epsc_vimma_reg_info *data);
+void write_union_psif_epsc_vimma_ctrl_cmd(XFILE *fd, int network_order, const union psif_epsc_vimma_ctrl_cmd *data);
+void write_struct_psif_epsc_csr_vimma_ctrl(XFILE *fd, int network_order, const struct psif_epsc_csr_vimma_ctrl *data);
+void write_union_psif_epsc_csr_details(XFILE *fd, int network_order, const union psif_epsc_csr_details *data);
+void write_struct_psif_epsc_csr_req(XFILE *fd, int network_order, const struct psif_epsc_csr_req *data);
+void write_struct_psif_epsc_csr_req_expand(XFILE *fd, int network_order, const struct psif_epsc_csr_req *data);
+void write_struct_psif_epsc_csr_doorbell(XFILE *fd, int network_order, const struct psif_epsc_csr_doorbell *data);
+void write_struct_psif_cq_sw(XFILE *fd, int network_order, const struct psif_cq_sw *data);
+void write_struct_psif_cq_hw(XFILE *fd, int network_order, const struct psif_cq_hw *data);
+void write_union_psif_seq_num_immdt(XFILE *fd, int network_order, const union psif_seq_num_immdt *data);
+void write_struct_psif_offload_info(XFILE *fd, int network_order, const struct psif_offload_info *data);
+void write_union_psif_offload_wc_id(XFILE *fd, int network_order, const union psif_offload_wc_id *data);
+void write_struct_psif_cq_entry(XFILE *fd, int network_order, const struct psif_cq_entry *data);
+void write_struct_psif_csr_generic(XFILE *fd, int network_order, const struct psif_csr_generic *data);
+void write_struct_psif_base_addr(XFILE *fd, int network_order, const struct psif_base_addr *data);
+void write_struct_psif_ah(XFILE *fd, int network_order, const struct psif_ah *data);
+void write_struct_psif_csr_ibpr_eoib_mac1(XFILE *fd, int network_order, const struct psif_csr_ibpr_eoib_mac1 *data);
+
+#endif /* !defined(PSIF_EXCLUDE_WRITE_STRUCTS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _PSIF_HW_PRINT_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/psif_hw_setget.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,1474 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PSIF_HW_SETGET_H
+#define _PSIF_HW_SETGET_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "psif_api.h"
+
+#if defined(__arm__)
+#include "epsfw_misc.h"
+# define htobe64(x) eps_htobe64(x)
+# define be64toh(x) eps_be64toh(x)
+#endif /* __arm__ */
+#include "psif_endian.h"
+#if !defined(__KERNEL__)
+#include "os_header.h"
+#endif
+
+
+/*
+ * PSIF_WR_INVALIDATE_LKEY: key to invalidate/flush from the DMA VT cache.
+ * PSIF_WR_INVALIDATE_RKEY: key to invalidate/flush from the DMA VT cache.
+ * PSIF_WR_INVALIDATE_BOTH_KEYS: key to invalidate/flush from the DMA VT
+ * cache. PSIF_WR_INVALIDATE_TLB: this is the address vector to invalidate in
+ * the TLB.
+ */
+static inline void set_psif_wr_su__key(volatile struct psif_wr_su *ptr, u32 data)
+{
+ /* group=2 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0x00000000ffffffffull) |
+ ((((u64)(data)) & 0x00000000ffffffffull) << 32));
+}
+static inline u32 get_psif_wr_su__key(volatile struct psif_wr_su *ptr)
+{
+ /* group=2 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[2]) >> 32) & 0x00000000ffffffffull));
+}
+
+/*
+ * Send queue sequence number. Used to map request to a particular work
+ * request in the send queue.
+ */
+static inline void set_psif_wr__sq_seq(volatile struct psif_wr *ptr, u16 data)
+{
+ /* group=0 shift=0 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xffffffffffff0000ull) |
+ ((((u64)(data)) & 0x000000000000ffffull) << 0));
+}
+static inline u16 get_psif_wr__sq_seq(volatile struct psif_wr *ptr)
+{
+ /* group=0 shift=0 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[0]) >> 0) & 0x000000000000ffffull));
+}
+
+/*
+ * QP sending this request. XXX: Should name be own_qp_num as defined in QP
+ * state?
+ */
+static inline void set_psif_wr__local_qp(volatile struct psif_wr *ptr, u32 data)
+{
+ /* group=0 shift=32 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xff000000ffffffffull) |
+ ((((u64)(data)) & 0x0000000000ffffffull) << 32));
+}
+static inline u32 get_psif_wr__local_qp(volatile struct psif_wr *ptr)
+{
+ /* group=0 shift=32 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[0]) >> 32) & 0x0000000000ffffffull));
+}
+
+/* Completion notification identifier. */
+static inline void set_psif_wr__completion(volatile struct psif_wr *ptr, u8 data)
+{
+ /* group=1 shift=31 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[1] = htobe64((be64toh(pte[1]) & 0xffffffff7fffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 31));
+}
+static inline u8 get_psif_wr__completion(volatile struct psif_wr *ptr)
+{
+ /* group=1 shift=31 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[1]) >> 31) & 0x0000000000000001ull));
+}
+
+/*
+ * Checksum used for data protection and consistency between work request and
+ * QP state.
+ */
+static inline void set_psif_wr__checksum(volatile struct psif_wr *ptr, u32 data)
+{
+ /* group=2 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0x00000000ffffffffull) |
+ ((((u64)(data)) & 0x00000000ffffffffull) << 32));
+}
+static inline u32 get_psif_wr__checksum(volatile struct psif_wr *ptr)
+{
+ /* group=2 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[2]) >> 32) & 0x00000000ffffffffull));
+}
+
+/*
+ * Index to where elements are added to the send queue by SW. SW is
+ * responsibel for keeping track of how many entries there are in the send
+ * queue. I.e. SW needs to keep track of the head_index so it doesn't
+ * overwrite entries in the send queue which is not yet completed.
+ */
+static inline void set_psif_sq_sw__tail_indx(volatile struct psif_sq_sw *ptr, u16 data)
+{
+ /* group=0 shift=32 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xffff0000ffffffffull) |
+ ((((u64)(data)) & 0x000000000000ffffull) << 32));
+}
+static inline u16 get_psif_sq_sw__tail_indx(volatile struct psif_sq_sw *ptr)
+{
+ /* group=0 shift=32 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[0]) >> 32) & 0x000000000000ffffull));
+}
+
+/*
+ * Send queue sequence number used by the SQS to maintain ordering and keep
+ * track of where which send queue elements to fetch. This field is not in
+ * sync with the field in qp_t. This number is typically a little bit before
+ * the number in the qp_t as SQS has to fetch the elements from host memory.
+ * This is also used as tail_index when checking if there are more elements
+ * in the send queue.
+ */
+static inline void set_psif_sq_hw__last_seq(volatile struct psif_sq_hw *ptr, u16 data)
+{
+ /* group=0 shift=16 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xffffffff0000ffffull) |
+ ((((u64)(data)) & 0x000000000000ffffull) << 16));
+}
+static inline u16 get_psif_sq_hw__last_seq(volatile struct psif_sq_hw *ptr)
+{
+ /* group=0 shift=16 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[0]) >> 16) & 0x000000000000ffffull));
+}
+
+/* QP and UF to be processed next. */
+static inline void set_psif_sq_hw__sq_next(volatile struct psif_sq_hw *ptr, u32 data)
+{
+ /* group=0 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0x00000000ffffffffull) |
+ ((((u64)(data)) & 0x00000000ffffffffull) << 32));
+}
+static inline u32 get_psif_sq_hw__sq_next(volatile struct psif_sq_hw *ptr)
+{
+ /* group=0 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[0]) >> 32) & 0x00000000ffffffffull));
+}
+
+/*
+ * This bit is set through the doorbell. SW should check this bit plus
+ * psif_next = null to ensure SW can own the SQ descriptor.
+ */
+static inline void set_psif_sq_hw__destroyed(volatile struct psif_sq_hw *ptr, u8 data)
+{
+ /* group=1 shift=27 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[1] = htobe64((be64toh(pte[1]) & 0xfffffffff7ffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 27));
+}
+static inline u8 get_psif_sq_hw__destroyed(volatile struct psif_sq_hw *ptr)
+{
+ /* group=1 shift=27 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[1]) >> 27) & 0x0000000000000001ull));
+}
+
+/* Software modified index pointing to the tail reecive entry in host memory. */
+static inline void set_psif_rq_sw__tail_indx(volatile struct psif_rq_sw *ptr, u16 data)
+{
+ /* group=0 shift=32 bits=14 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xffffc000ffffffffull) |
+ ((((u64)(data)) & 0x0000000000003fffull) << 32));
+}
+static inline u16 get_psif_rq_sw__tail_indx(volatile struct psif_rq_sw *ptr)
+{
+ /* group=0 shift=32 bits=14 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[0]) >> 32) & 0x0000000000003fffull));
+}
+
+/*
+ * Hardware modified index pointing to the head of the receive queue. TSU is
+ * using this to find the address of the receive queue entry.
+ */
+static inline void set_psif_rq_hw__head_indx(volatile struct psif_rq_hw *ptr, u16 data)
+{
+ /* group=0 shift=14 bits=14 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xfffffffff0003fffull) |
+ ((((u64)(data)) & 0x0000000000003fffull) << 14));
+}
+static inline u16 get_psif_rq_hw__head_indx(volatile struct psif_rq_hw *ptr)
+{
+ /* group=0 shift=14 bits=14 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[0]) >> 14) & 0x0000000000003fffull));
+}
+
+/* The desciptor is valid. */
+static inline void set_psif_rq_hw__valid(volatile struct psif_rq_hw *ptr, u8 data)
+{
+ /* group=3 shift=55 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[3] = htobe64((be64toh(pte[3]) & 0xff7fffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 55));
+}
+static inline u8 get_psif_rq_hw__valid(volatile struct psif_rq_hw *ptr)
+{
+ /* group=3 shift=55 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[3]) >> 55) & 0x0000000000000001ull));
+}
+
+/*
+ * Receive queue entry ID. This is added to the receive completion using this
+ * receive queue entry.
+ */
+static inline void set_psif_rq_entry__rqe_id(volatile struct psif_rq_entry *ptr, u64 data)
+{
+ /* group=0 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((__be64)data);
+}
+static inline u64 get_psif_rq_entry__rqe_id(volatile struct psif_rq_entry *ptr)
+{
+ /* group=0 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u64)be64toh(pte[0]));
+}
+
+/*
+ * This retry tag is the one used by tsu_rqs and added to the packets sent to
+ * tsu_dma. It is the responsibility of tsu_rqs to update this retry tag
+ * whenever the sq_sequence_number in QP state is equal to the one in the
+ * request.
+ */
+static inline void set_psif_qp_core__retry_tag_committed(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=0 shift=0 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xfffffffffffffff8ull) |
+ ((((u64)(data)) & 0x0000000000000007ull) << 0));
+}
+static inline u8 get_psif_qp_core__retry_tag_committed(volatile struct psif_qp_core *ptr)
+{
+ /* group=0 shift=0 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[0]) >> 0) & 0x0000000000000007ull));
+}
+
+/*
+ * This retry tag is updated by the error block when an error occur. If
+ * tsu_rqs reads this retry tag and it is different than the
+ * retry_tag_comitted, tsu_rqs must update retry_tag_comitted to the value of
+ * retry_tag_err when the sq_sequence_number indicates this is the valid
+ * request. The sq_sequence_number has been updated by tsu_err at the same
+ * time the retry_tag_err is updated.
+ */
+static inline void set_psif_qp_core__retry_tag_err(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=0 shift=3 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xffffffffffffffc7ull) |
+ ((((u64)(data)) & 0x0000000000000007ull) << 3));
+}
+static inline u8 get_psif_qp_core__retry_tag_err(volatile struct psif_qp_core *ptr)
+{
+ /* group=0 shift=3 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[0]) >> 3) & 0x0000000000000007ull));
+}
+
+/*
+ * Error retry counter initial value. Read by tsu_dma and used by tsu_cmpl to
+ * calculate exp_backoff etc..
+ */
+static inline void set_psif_qp_core__error_retry_init(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=0 shift=32 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xfffffff8ffffffffull) |
+ ((((u64)(data)) & 0x0000000000000007ull) << 32));
+}
+static inline u8 get_psif_qp_core__error_retry_init(volatile struct psif_qp_core *ptr)
+{
+ /* group=0 shift=32 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[0]) >> 32) & 0x0000000000000007ull));
+}
+
+/*
+ * Retry counter associated with retries to received NAK or implied NAK. If
+ * it expires, a path migration will be attempted if it is armed, or the QP
+ * will go to error state. Read by tsu_dma and used by tsu_cmpl.
+ */
+static inline void set_psif_qp_core__error_retry_count(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=0 shift=35 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xffffffc7ffffffffull) |
+ ((((u64)(data)) & 0x0000000000000007ull) << 35));
+}
+static inline u8 get_psif_qp_core__error_retry_count(volatile struct psif_qp_core *ptr)
+{
+ /* group=0 shift=35 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[0]) >> 35) & 0x0000000000000007ull));
+}
+
+/* A hit in the set locally spun out of tsu_cmpl is found. */
+static inline void set_psif_qp_core__spin_hit(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=0 shift=39 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xffffff7fffffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 39));
+}
+static inline u8 get_psif_qp_core__spin_hit(volatile struct psif_qp_core *ptr)
+{
+ /* group=0 shift=39 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[0]) >> 39) & 0x0000000000000001ull));
+}
+
+/*
+ * Minium RNR NAK timeout. This is added to RNR NAK packets and the requester
+ * receiving the RNR NAK must wait until the timer has expired before the
+ * retry is sent.
+ */
+static inline void set_psif_qp_core__min_rnr_nak_time(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=1 shift=0 bits=5 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[1] = htobe64((be64toh(pte[1]) & 0xffffffffffffffe0ull) |
+ ((((u64)(data)) & 0x000000000000001full) << 0));
+}
+static inline u8 get_psif_qp_core__min_rnr_nak_time(volatile struct psif_qp_core *ptr)
+{
+ /* group=1 shift=0 bits=5 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[1]) >> 0) & 0x000000000000001full));
+}
+
+/* QP State for this QP. */
+static inline void set_psif_qp_core__state(volatile struct psif_qp_core *ptr, enum psif_qp_state data)
+{
+ /* group=1 shift=5 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[1] = htobe64((be64toh(pte[1]) & 0xffffffffffffff1full) |
+ ((((u64)(data)) & 0x0000000000000007ull) << 5));
+}
+static inline enum psif_qp_state get_psif_qp_core__state(volatile struct psif_qp_core *ptr)
+{
+ /* group=1 shift=5 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_qp_state)((be64toh(pte[1]) >> 5) & 0x0000000000000007ull));
+}
+
+/* QP number for the remote node. */
+static inline void set_psif_qp_core__remote_qp(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=1 shift=8 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[1] = htobe64((be64toh(pte[1]) & 0xffffffff000000ffull) |
+ ((((u64)(data)) & 0x0000000000ffffffull) << 8));
+}
+static inline u32 get_psif_qp_core__remote_qp(volatile struct psif_qp_core *ptr)
+{
+ /* group=1 shift=8 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[1]) >> 8) & 0x0000000000ffffffull));
+}
+
+static inline void set_psif_qp_core__retry_sq_seq(volatile struct psif_qp_core *ptr, u16 data)
+{
+ /* group=2 shift=32 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0xffff0000ffffffffull) |
+ ((((u64)(data)) & 0x000000000000ffffull) << 32));
+}
+static inline u16 get_psif_qp_core__retry_sq_seq(volatile struct psif_qp_core *ptr)
+{
+ /* group=2 shift=32 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[2]) >> 32) & 0x000000000000ffffull));
+}
+
+static inline void set_psif_qp_core__sq_seq(volatile struct psif_qp_core *ptr, u16 data)
+{
+ /* group=2 shift=48 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0x0000ffffffffffffull) |
+ ((((u64)(data)) & 0x000000000000ffffull) << 48));
+}
+static inline u16 get_psif_qp_core__sq_seq(volatile struct psif_qp_core *ptr)
+{
+ /* group=2 shift=48 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[2]) >> 48) & 0x000000000000ffffull));
+}
+
+/*
+ * Magic number used to verify use of QP state. This is done by calculating a
+ * checksum of the work request incorporating the magic number. This checksum
+ * is checked against the checksum in the work request.
+ */
+static inline void set_psif_qp_core__magic(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=3 shift=0 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[3] = htobe64((be64toh(pte[3]) & 0xffffffff00000000ull) |
+ ((((u64)(data)) & 0x00000000ffffffffull) << 0));
+}
+static inline u32 get_psif_qp_core__magic(volatile struct psif_qp_core *ptr)
+{
+ /* group=3 shift=0 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[3]) >> 0) & 0x00000000ffffffffull));
+}
+
+/*
+ * Q-Key received in incoming IB packet is checked towards this Q-Key. Q-Key
+ * used on transmit if top bit of Q-Key in WR is set.
+ */
+static inline void set_psif_qp_core__qkey(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=4 shift=0 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[4] = htobe64((be64toh(pte[4]) & 0xffffffff00000000ull) |
+ ((((u64)(data)) & 0x00000000ffffffffull) << 0));
+}
+static inline u32 get_psif_qp_core__qkey(volatile struct psif_qp_core *ptr)
+{
+ /* group=4 shift=0 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[4]) >> 0) & 0x00000000ffffffffull));
+}
+
+/*
+ * Sequence number of the last ACK received. Read and written by tsu_cmpl.
+ * Used to verify that the received response packet is a valid response.
+ */
+static inline void set_psif_qp_core__last_acked_psn(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=4 shift=40 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[4] = htobe64((be64toh(pte[4]) & 0x000000ffffffffffull) |
+ ((((u64)(data)) & 0x0000000000ffffffull) << 40));
+}
+static inline u32 get_psif_qp_core__last_acked_psn(volatile struct psif_qp_core *ptr)
+{
+ /* group=4 shift=40 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[4]) >> 40) & 0x0000000000ffffffull));
+}
+
+/* Index to scatter element of in progress SEND. */
+static inline void set_psif_qp_core__scatter_indx(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=5 shift=32 bits=5 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[5] = htobe64((be64toh(pte[5]) & 0xffffffe0ffffffffull) |
+ ((((u64)(data)) & 0x000000000000001full) << 32));
+}
+static inline u8 get_psif_qp_core__scatter_indx(volatile struct psif_qp_core *ptr)
+{
+ /* group=5 shift=32 bits=5 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[5]) >> 32) & 0x000000000000001full));
+}
+
+/*
+ * Expected packet sequence number: Sequence number on next expected packet.
+ */
+static inline void set_psif_qp_core__expected_psn(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=5 shift=40 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[5] = htobe64((be64toh(pte[5]) & 0x000000ffffffffffull) |
+ ((((u64)(data)) & 0x0000000000ffffffull) << 40));
+}
+static inline u32 get_psif_qp_core__expected_psn(volatile struct psif_qp_core *ptr)
+{
+ /* group=5 shift=40 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[5]) >> 40) & 0x0000000000ffffffull));
+}
+
+/*
+ * TSU quality of service level. Can take values indicating low latency and
+ * high throughput. This is equivalent to high/low BAR when writing doorbells
+ * to PSIF. The qosl bit in the doorbell request must match this bit in the
+ * QP state, otherwise the QP must be put in error. This check only applies
+ * to tsu_rqs.
+ */
+static inline void set_psif_qp_core__qosl(volatile struct psif_qp_core *ptr, enum psif_tsu_qos data)
+{
+ /* group=6 shift=49 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[6] = htobe64((be64toh(pte[6]) & 0xfffdffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 49));
+}
+static inline enum psif_tsu_qos get_psif_qp_core__qosl(volatile struct psif_qp_core *ptr)
+{
+ /* group=6 shift=49 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_tsu_qos)((be64toh(pte[6]) >> 49) & 0x0000000000000001ull));
+}
+
+/*
+ * Migration state (migrated, re-arm and armed). Since path migration is
+ * handled by tsu_qps, this is controlled by tsu_qps. XXX: Should error
+ * handler also be able to change the path?
+ */
+static inline void set_psif_qp_core__mstate(volatile struct psif_qp_core *ptr, enum psif_migration data)
+{
+ /* group=6 shift=50 bits=2 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[6] = htobe64((be64toh(pte[6]) & 0xfff3ffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000003ull) << 50));
+}
+static inline enum psif_migration get_psif_qp_core__mstate(volatile struct psif_qp_core *ptr)
+{
+ /* group=6 shift=50 bits=2 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_migration)((be64toh(pte[6]) >> 50) & 0x0000000000000003ull));
+}
+
+/* This is an IB over IB QP. */
+static inline void set_psif_qp_core__ipoib_enable(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=6 shift=53 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[6] = htobe64((be64toh(pte[6]) & 0xffdfffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 53));
+}
+static inline u8 get_psif_qp_core__ipoib_enable(volatile struct psif_qp_core *ptr)
+{
+ /* group=6 shift=53 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[6]) >> 53) & 0x0000000000000001ull));
+}
+
+/* IB defined capability enable for receiving Atomic operations. */
+static inline void set_psif_qp_core__atomic_enable(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=6 shift=61 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[6] = htobe64((be64toh(pte[6]) & 0xdfffffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 61));
+}
+static inline u8 get_psif_qp_core__atomic_enable(volatile struct psif_qp_core *ptr)
+{
+ /* group=6 shift=61 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[6]) >> 61) & 0x0000000000000001ull));
+}
+
+/* IB defined capability enable for receiving RDMA WR. */
+static inline void set_psif_qp_core__rdma_wr_enable(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=6 shift=62 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[6] = htobe64((be64toh(pte[6]) & 0xbfffffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 62));
+}
+static inline u8 get_psif_qp_core__rdma_wr_enable(volatile struct psif_qp_core *ptr)
+{
+ /* group=6 shift=62 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[6]) >> 62) & 0x0000000000000001ull));
+}
+
+/* IB defined capability enable for receiving RDMA RD. */
+static inline void set_psif_qp_core__rdma_rd_enable(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=6 shift=63 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[6] = htobe64((be64toh(pte[6]) & 0x7fffffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 63));
+}
+static inline u8 get_psif_qp_core__rdma_rd_enable(volatile struct psif_qp_core *ptr)
+{
+ /* group=6 shift=63 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[6]) >> 63) & 0x0000000000000001ull));
+}
+
+/*
+ * Transmit packet sequence number. Read and updated by tsu_dma before
+ * sending packets to tsu_ibpb and tsu_cmpl.
+ */
+static inline void set_psif_qp_core__xmit_psn(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=7 shift=0 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[7] = htobe64((be64toh(pte[7]) & 0xffffffffff000000ull) |
+ ((((u64)(data)) & 0x0000000000ffffffull) << 0));
+}
+static inline u32 get_psif_qp_core__xmit_psn(volatile struct psif_qp_core *ptr)
+{
+ /* group=7 shift=0 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[7]) >> 0) & 0x0000000000ffffffull));
+}
+
+/*
+ * TSU Service Level used to decide the TSU VL for requests associated with
+ * this QP.
+ */
+static inline void set_psif_qp_core__tsl(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=7 shift=55 bits=4 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[7] = htobe64((be64toh(pte[7]) & 0xf87fffffffffffffull) |
+ ((((u64)(data)) & 0x000000000000000full) << 55));
+}
+static inline u8 get_psif_qp_core__tsl(volatile struct psif_qp_core *ptr)
+{
+ /* group=7 shift=55 bits=4 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[7]) >> 55) & 0x000000000000000full));
+}
+
+/*
+ * Maximum number of outstanding read or atomic requests allowed by the
+ * remote HCA. Initialized by software.
+ */
+static inline void set_psif_qp_core__max_outstanding(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=7 shift=59 bits=5 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[7] = htobe64((be64toh(pte[7]) & 0x07ffffffffffffffull) |
+ ((((u64)(data)) & 0x000000000000001full) << 59));
+}
+static inline u8 get_psif_qp_core__max_outstanding(volatile struct psif_qp_core *ptr)
+{
+ /* group=7 shift=59 bits=5 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[7]) >> 59) & 0x000000000000001full));
+}
+
+/* Send Queue RNR retry count initialization value. */
+static inline void set_psif_qp_core__rnr_retry_init(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=8 shift=32 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[8] = htobe64((be64toh(pte[8]) & 0xfffffff8ffffffffull) |
+ ((((u64)(data)) & 0x0000000000000007ull) << 32));
+}
+static inline u8 get_psif_qp_core__rnr_retry_init(volatile struct psif_qp_core *ptr)
+{
+ /* group=8 shift=32 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[8]) >> 32) & 0x0000000000000007ull));
+}
+
+/*
+ * Retry counter associated with RNR NAK retries. If it expires, a path
+ * migration will be attempted if it is armed, or the QP will go to error
+ * state.
+ */
+static inline void set_psif_qp_core__rnr_retry_count(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=8 shift=35 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[8] = htobe64((be64toh(pte[8]) & 0xffffffc7ffffffffull) |
+ ((((u64)(data)) & 0x0000000000000007ull) << 35));
+}
+static inline u8 get_psif_qp_core__rnr_retry_count(volatile struct psif_qp_core *ptr)
+{
+ /* group=8 shift=35 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[8]) >> 35) & 0x0000000000000007ull));
+}
+
+/*
+ * When set, RQS should only check that the orig_checksum is equal to magic
+ * number. When not set, RQS should perform the checksum check towards the
+ * checksum in the psif_wr.
+ */
+static inline void set_psif_qp_core__no_checksum(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=8 shift=39 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[8] = htobe64((be64toh(pte[8]) & 0xffffff7fffffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 39));
+}
+static inline u8 get_psif_qp_core__no_checksum(volatile struct psif_qp_core *ptr)
+{
+ /* group=8 shift=39 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[8]) >> 39) & 0x0000000000000001ull));
+}
+
+/*
+ * Transport type of the QP (RC, UC, UD, XRC, MANSP1). MANSP1 is set for
+ * privileged QPs.
+ */
+static inline void set_psif_qp_core__transport_type(volatile struct psif_qp_core *ptr, enum psif_qp_trans data)
+{
+ /* group=9 shift=0 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[9] = htobe64((be64toh(pte[9]) & 0xfffffffffffffff8ull) |
+ ((((u64)(data)) & 0x0000000000000007ull) << 0));
+}
+static inline enum psif_qp_trans get_psif_qp_core__transport_type(volatile struct psif_qp_core *ptr)
+{
+ /* group=9 shift=0 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_qp_trans)((be64toh(pte[9]) >> 0) & 0x0000000000000007ull));
+}
+
+/*
+ * Number of bytes received of in progress RDMA Write or SEND. The data
+ * received for SENDs and RDMA WR w/Imm are needed for completions. This
+ * should be added to the msg_length.
+ */
+static inline void set_psif_qp_core__bytes_received(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=9 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[9] = htobe64((be64toh(pte[9]) & 0x00000000ffffffffull) |
+ ((((u64)(data)) & 0x00000000ffffffffull) << 32));
+}
+static inline u32 get_psif_qp_core__bytes_received(volatile struct psif_qp_core *ptr)
+{
+ /* group=9 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[9]) >> 32) & 0x00000000ffffffffull));
+}
+
+/* This QP is running IP over IB. */
+static inline void set_psif_qp_core__ipoib(volatile struct psif_qp_core *ptr, u8 data)
+{
+ /* group=10 shift=5 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[10] = htobe64((be64toh(pte[10]) & 0xffffffffffffffdfull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 5));
+}
+static inline u8 get_psif_qp_core__ipoib(volatile struct psif_qp_core *ptr)
+{
+ /* group=10 shift=5 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[10]) >> 5) & 0x0000000000000001ull));
+}
+
+/*
+ * Combined 'Last Received MSN' and 'Last Outstanding MSN', used to maintain
+ * 'spin set floor' and indicate 'all retries completed', respectively.
+ */
+static inline void set_psif_qp_core__last_received_outstanding_msn(volatile struct psif_qp_core *ptr, u16 data)
+{
+ /* group=11 shift=0 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[11] = htobe64((be64toh(pte[11]) & 0xffffffffffff0000ull) |
+ ((((u64)(data)) & 0x000000000000ffffull) << 0));
+}
+static inline u16 get_psif_qp_core__last_received_outstanding_msn(volatile struct psif_qp_core *ptr)
+{
+ /* group=11 shift=0 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[11]) >> 0) & 0x000000000000ffffull));
+}
+
+static inline void set_psif_qp_core__path_mtu(volatile struct psif_qp_core *ptr, enum psif_path_mtu data)
+{
+ /* group=13 shift=4 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[13] = htobe64((be64toh(pte[13]) & 0xffffffffffffff8full) |
+ ((((u64)(data)) & 0x0000000000000007ull) << 4));
+}
+static inline enum psif_path_mtu get_psif_qp_core__path_mtu(volatile struct psif_qp_core *ptr)
+{
+ /* group=13 shift=4 bits=3 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_path_mtu)((be64toh(pte[13]) >> 4) & 0x0000000000000007ull));
+}
+
+/* This PSN is committed - ACKs sent will contain this PSN. */
+static inline void set_psif_qp_core__committed_received_psn(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=13 shift=8 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[13] = htobe64((be64toh(pte[13]) & 0xffffffff000000ffull) |
+ ((((u64)(data)) & 0x0000000000ffffffull) << 8));
+}
+static inline u32 get_psif_qp_core__committed_received_psn(volatile struct psif_qp_core *ptr)
+{
+ /* group=13 shift=8 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[13]) >> 8) & 0x0000000000ffffffull));
+}
+
+/*
+ * Message sequence number used in AETH when sending ACKs. The number is
+ * incremented every time a new inbound message is processed.
+ */
+static inline void set_psif_qp_core__msn(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=14 shift=0 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[14] = htobe64((be64toh(pte[14]) & 0xffffffffff000000ull) |
+ ((((u64)(data)) & 0x0000000000ffffffull) << 0));
+}
+static inline u32 get_psif_qp_core__msn(volatile struct psif_qp_core *ptr)
+{
+ /* group=14 shift=0 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[14]) >> 0) & 0x0000000000ffffffull));
+}
+
+/*
+ * This is an index to send completion queue descriptor. The descriptor
+ * points to a send completion queue, which may or may not be the same as the
+ * send completion queue.
+ */
+static inline void set_psif_qp_core__send_cq_indx(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=14 shift=24 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[14] = htobe64((be64toh(pte[14]) & 0xffff000000ffffffull) |
+ ((((u64)(data)) & 0x0000000000ffffffull) << 24));
+}
+static inline u32 get_psif_qp_core__send_cq_indx(volatile struct psif_qp_core *ptr)
+{
+ /* group=14 shift=24 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[14]) >> 24) & 0x0000000000ffffffull));
+}
+
+/*
+ * Committed MSN - the MSN of the newest committed request for this QP. Only
+ * the bottom 16 bits of the MSN is used.
+ */
+static inline void set_psif_qp_core__last_committed_msn(volatile struct psif_qp_core *ptr, u16 data)
+{
+ /* group=14 shift=48 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[14] = htobe64((be64toh(pte[14]) & 0x0000ffffffffffffull) |
+ ((((u64)(data)) & 0x000000000000ffffull) << 48));
+}
+static inline u16 get_psif_qp_core__last_committed_msn(volatile struct psif_qp_core *ptr)
+{
+ /* group=14 shift=48 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[14]) >> 48) & 0x000000000000ffffull));
+}
+
+static inline void set_psif_qp_core__srq_pd(volatile struct psif_qp_core *ptr, u32 data)
+{
+ /* group=15 shift=0 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[15] = htobe64((be64toh(pte[15]) & 0xffffffffff000000ull) |
+ ((((u64)(data)) & 0x0000000000ffffffull) << 0));
+}
+static inline u32 get_psif_qp_core__srq_pd(volatile struct psif_qp_core *ptr)
+{
+ /* group=15 shift=0 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[15]) >> 0) & 0x0000000000ffffffull));
+}
+
+static inline void set_psif_qp_path__remote_gid_0(volatile struct psif_qp_path *ptr, u64 data)
+{
+ /* group=0 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((__be64)data);
+}
+static inline u64 get_psif_qp_path__remote_gid_0(volatile struct psif_qp_path *ptr)
+{
+ /* group=0 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u64)be64toh(pte[0]));
+}
+
+static inline void set_psif_qp_path__remote_gid_1(volatile struct psif_qp_path *ptr, u64 data)
+{
+ /* group=1 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[1] = htobe64((__be64)data);
+}
+static inline u64 get_psif_qp_path__remote_gid_1(volatile struct psif_qp_path *ptr)
+{
+ /* group=1 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u64)be64toh(pte[1]));
+}
+
+static inline void set_psif_qp_path__remote_lid(volatile struct psif_qp_path *ptr, u16 data)
+{
+ /* group=2 shift=0 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0xffffffffffff0000ull) |
+ ((((u64)(data)) & 0x000000000000ffffull) << 0));
+}
+static inline u16 get_psif_qp_path__remote_lid(volatile struct psif_qp_path *ptr)
+{
+ /* group=2 shift=0 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[2]) >> 0) & 0x000000000000ffffull));
+}
+
+static inline void set_psif_qp_path__port(volatile struct psif_qp_path *ptr, enum psif_port data)
+{
+ /* group=2 shift=17 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0xfffffffffffdffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 17));
+}
+static inline enum psif_port get_psif_qp_path__port(volatile struct psif_qp_path *ptr)
+{
+ /* group=2 shift=17 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_port)((be64toh(pte[2]) >> 17) & 0x0000000000000001ull));
+}
+
+static inline void set_psif_qp_path__loopback(volatile struct psif_qp_path *ptr, enum psif_loopback data)
+{
+ /* group=2 shift=18 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0xfffffffffffbffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 18));
+}
+static inline enum psif_loopback get_psif_qp_path__loopback(volatile struct psif_qp_path *ptr)
+{
+ /* group=2 shift=18 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_loopback)((be64toh(pte[2]) >> 18) & 0x0000000000000001ull));
+}
+
+static inline void set_psif_qp_path__use_grh(volatile struct psif_qp_path *ptr, enum psif_use_grh data)
+{
+ /* group=2 shift=19 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0xfffffffffff7ffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 19));
+}
+static inline enum psif_use_grh get_psif_qp_path__use_grh(volatile struct psif_qp_path *ptr)
+{
+ /* group=2 shift=19 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_use_grh)((be64toh(pte[2]) >> 19) & 0x0000000000000001ull));
+}
+
+static inline void set_psif_qp_path__sl(volatile struct psif_qp_path *ptr, u8 data)
+{
+ /* group=2 shift=20 bits=4 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0xffffffffff0fffffull) |
+ ((((u64)(data)) & 0x000000000000000full) << 20));
+}
+static inline u8 get_psif_qp_path__sl(volatile struct psif_qp_path *ptr)
+{
+ /* group=2 shift=20 bits=4 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[2]) >> 20) & 0x000000000000000full));
+}
+
+static inline void set_psif_qp_path__hoplmt(volatile struct psif_qp_path *ptr, u8 data)
+{
+ /* group=2 shift=28 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0xfffffff00fffffffull) |
+ ((((u64)(data)) & 0x00000000000000ffull) << 28));
+}
+static inline u8 get_psif_qp_path__hoplmt(volatile struct psif_qp_path *ptr)
+{
+ /* group=2 shift=28 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[2]) >> 28) & 0x00000000000000ffull));
+}
+
+static inline void set_psif_qp_path__flowlabel(volatile struct psif_qp_path *ptr, u32 data)
+{
+ /* group=2 shift=44 bits=20 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0x00000fffffffffffull) |
+ ((((u64)(data)) & 0x00000000000fffffull) << 44));
+}
+static inline u32 get_psif_qp_path__flowlabel(volatile struct psif_qp_path *ptr)
+{
+ /* group=2 shift=44 bits=20 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[2]) >> 44) & 0x00000000000fffffull));
+}
+
+static inline void set_psif_qp_path__local_ack_timeout(volatile struct psif_qp_path *ptr, u8 data)
+{
+ /* group=3 shift=27 bits=5 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[3] = htobe64((be64toh(pte[3]) & 0xffffffff07ffffffull) |
+ ((((u64)(data)) & 0x000000000000001full) << 27));
+}
+static inline u8 get_psif_qp_path__local_ack_timeout(volatile struct psif_qp_path *ptr)
+{
+ /* group=3 shift=27 bits=5 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[3]) >> 27) & 0x000000000000001full));
+}
+
+static inline void set_psif_qp_path__ipd(volatile struct psif_qp_path *ptr, u8 data)
+{
+ /* group=3 shift=32 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[3] = htobe64((be64toh(pte[3]) & 0xffffff00ffffffffull) |
+ ((((u64)(data)) & 0x00000000000000ffull) << 32));
+}
+static inline u8 get_psif_qp_path__ipd(volatile struct psif_qp_path *ptr)
+{
+ /* group=3 shift=32 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[3]) >> 32) & 0x00000000000000ffull));
+}
+
+/*
+ * This is the LID path bits. This is used by tsu_ibpb when generating the
+ * SLID in the packet, and it is used by tsu_rcv when checking the DLID.
+ */
+static inline void set_psif_qp_path__local_lid_path(volatile struct psif_qp_path *ptr, u8 data)
+{
+ /* group=3 shift=48 bits=7 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[3] = htobe64((be64toh(pte[3]) & 0xff80ffffffffffffull) |
+ ((((u64)(data)) & 0x000000000000007full) << 48));
+}
+static inline u8 get_psif_qp_path__local_lid_path(volatile struct psif_qp_path *ptr)
+{
+ /* group=3 shift=48 bits=7 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[3]) >> 48) & 0x000000000000007full));
+}
+
+static inline void set_psif_qp_path__pkey_indx(volatile struct psif_qp_path *ptr, u16 data)
+{
+ /* group=3 shift=55 bits=9 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[3] = htobe64((be64toh(pte[3]) & 0x007fffffffffffffull) |
+ ((((u64)(data)) & 0x00000000000001ffull) << 55));
+}
+static inline u16 get_psif_qp_path__pkey_indx(volatile struct psif_qp_path *ptr)
+{
+ /* group=3 shift=55 bits=9 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[3]) >> 55) & 0x00000000000001ffull));
+}
+
+/* L-key state for this DMA validation entry */
+static inline void set_psif_key__lkey_state(volatile struct psif_key *ptr, enum psif_dma_vt_key_states data)
+{
+ /* group=0 shift=60 bits=2 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xcfffffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000003ull) << 60));
+}
+static inline enum psif_dma_vt_key_states get_psif_key__lkey_state(volatile struct psif_key *ptr)
+{
+ /* group=0 shift=60 bits=2 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_dma_vt_key_states)((be64toh(pte[0]) >> 60) & 0x0000000000000003ull));
+}
+
+/* R-key state for this DMA validation entry */
+static inline void set_psif_key__rkey_state(volatile struct psif_key *ptr, enum psif_dma_vt_key_states data)
+{
+ /* group=0 shift=62 bits=2 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0x3fffffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000003ull) << 62));
+}
+static inline enum psif_dma_vt_key_states get_psif_key__rkey_state(volatile struct psif_key *ptr)
+{
+ /* group=0 shift=62 bits=2 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_dma_vt_key_states)((be64toh(pte[0]) >> 62) & 0x0000000000000003ull));
+}
+
+/* Length of memory region this validation entry is associated with. */
+static inline void set_psif_key__length(volatile struct psif_key *ptr, u64 data)
+{
+ /* group=1 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[1] = htobe64((__be64)data);
+}
+static inline u64 get_psif_key__length(volatile struct psif_key *ptr)
+{
+ /* group=1 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u64)be64toh(pte[1]));
+}
+
+static inline void set_psif_key__mmu_context(volatile struct psif_key *ptr, u64 data)
+{
+ /* group=2 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((__be64)data);
+}
+static inline u64 get_psif_key__mmu_context(volatile struct psif_key *ptr)
+{
+ /* group=2 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u64)be64toh(pte[2]));
+}
+
+static inline void set_psif_key__base_addr(volatile struct psif_key *ptr, u64 data)
+{
+ /* group=3 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[3] = htobe64((__be64)data);
+}
+static inline u64 get_psif_key__base_addr(volatile struct psif_key *ptr)
+{
+ /* group=3 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u64)be64toh(pte[3]));
+}
+
+/* sequence number for sanity checking */
+static inline void set_psif_eq_entry__seq_num(volatile struct psif_eq_entry *ptr, u32 data)
+{
+ /* group=7 shift=0 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[7] = htobe64((be64toh(pte[7]) & 0xffffffff00000000ull) |
+ ((((u64)(data)) & 0x00000000ffffffffull) << 0));
+}
+static inline u32 get_psif_eq_entry__seq_num(volatile struct psif_eq_entry *ptr)
+{
+ /* group=7 shift=0 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[7]) >> 0) & 0x00000000ffffffffull));
+}
+
+/* enum psif_epsc_csr_opcode from request */
+static inline void set_psif_epsc_csr_rsp__opcode(volatile struct psif_epsc_csr_rsp *ptr, enum psif_epsc_csr_opcode data)
+{
+ /* group=0 shift=48 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xff00ffffffffffffull) |
+ ((((u64)(data)) & 0x00000000000000ffull) << 48));
+}
+static inline enum psif_epsc_csr_opcode get_psif_epsc_csr_rsp__opcode(volatile struct psif_epsc_csr_rsp *ptr)
+{
+ /* group=0 shift=48 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_epsc_csr_opcode)((be64toh(pte[0]) >> 48) & 0x00000000000000ffull));
+}
+
+/* Sequence number from request */
+static inline void set_psif_epsc_csr_rsp__seq_num(volatile struct psif_epsc_csr_rsp *ptr, u64 data)
+{
+ /* group=3 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[3] = htobe64((__be64)data);
+}
+static inline u64 get_psif_epsc_csr_rsp__seq_num(volatile struct psif_epsc_csr_rsp *ptr)
+{
+ /* group=3 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u64)be64toh(pte[3]));
+}
+
+/* Sequence number - included in response */
+static inline void set_psif_epsc_csr_req__seq_num(volatile struct psif_epsc_csr_req *ptr, u16 data)
+{
+ /* group=0 shift=32 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xffff0000ffffffffull) |
+ ((((u64)(data)) & 0x000000000000ffffull) << 32));
+}
+static inline u16 get_psif_epsc_csr_req__seq_num(volatile struct psif_epsc_csr_req *ptr)
+{
+ /* group=0 shift=32 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[0]) >> 32) & 0x000000000000ffffull));
+}
+
+static inline void set_psif_epsc_csr_req__opcode(volatile struct psif_epsc_csr_req *ptr, enum psif_epsc_csr_opcode data)
+{
+ /* group=0 shift=56 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0x00ffffffffffffffull) |
+ ((((u64)(data)) & 0x00000000000000ffull) << 56));
+}
+static inline enum psif_epsc_csr_opcode get_psif_epsc_csr_req__opcode(volatile struct psif_epsc_csr_req *ptr)
+{
+ /* group=0 shift=56 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_epsc_csr_opcode)((be64toh(pte[0]) >> 56) & 0x00000000000000ffull));
+}
+
+/* Index to completion elements added by SW. */
+static inline void set_psif_cq_sw__head_indx(volatile struct psif_cq_sw *ptr, u32 data)
+{
+ /* group=0 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0x00000000ffffffffull) |
+ ((((u64)(data)) & 0x00000000ffffffffull) << 32));
+}
+static inline u32 get_psif_cq_sw__head_indx(volatile struct psif_cq_sw *ptr)
+{
+ /* group=0 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[0]) >> 32) & 0x00000000ffffffffull));
+}
+
+/*
+ * EPS-A core number completions are forwarded to if the proxy_enabled bit is
+ * set.
+ */
+static inline void set_psif_cq_hw__eps_core(volatile struct psif_cq_hw *ptr, enum psif_eps_a_core data)
+{
+ /* group=0 shift=52 bits=2 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xffcfffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000003ull) << 52));
+}
+static inline enum psif_eps_a_core get_psif_cq_hw__eps_core(volatile struct psif_cq_hw *ptr)
+{
+ /* group=0 shift=52 bits=2 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_eps_a_core)((be64toh(pte[0]) >> 52) & 0x0000000000000003ull));
+}
+
+/*
+ * If set, this completion queue is proxy enabled and should send completions
+ * to EPS core indicated by the eps_core field.
+ */
+static inline void set_psif_cq_hw__proxy_en(volatile struct psif_cq_hw *ptr, u8 data)
+{
+ /* group=0 shift=54 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xffbfffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 54));
+}
+static inline u8 get_psif_cq_hw__proxy_en(volatile struct psif_cq_hw *ptr)
+{
+ /* group=0 shift=54 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[0]) >> 54) & 0x0000000000000001ull));
+}
+
+/* The descriptor is valid. */
+static inline void set_psif_cq_hw__valid(volatile struct psif_cq_hw *ptr, u8 data)
+{
+ /* group=0 shift=60 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xefffffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000001ull) << 60));
+}
+static inline u8 get_psif_cq_hw__valid(volatile struct psif_cq_hw *ptr)
+{
+ /* group=0 shift=60 bits=1 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[0]) >> 60) & 0x0000000000000001ull));
+}
+
+/*
+ * VA or PA of the base of the completion queue. If PA the MMU context above
+ * will be a bypass context. Updated by software. The head and tail pointers
+ * can be calculated by the following calculations: Address = base_ptr +
+ * (head * ($bits(completion_entry_t)/8 ) Head Pointer and Tail Pointer will
+ * use the same MMU context as the base, and all need to be VA from one
+ * address space, or all need to be PA. In typical use, to allow direct user
+ * access to the head and tail pointer VAs are used.
+ */
+static inline void set_psif_cq_hw__base_addr(volatile struct psif_cq_hw *ptr, u64 data)
+{
+ /* group=2 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((__be64)data);
+}
+static inline u64 get_psif_cq_hw__base_addr(volatile struct psif_cq_hw *ptr)
+{
+ /* group=2 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u64)be64toh(pte[2]));
+}
+
+/* Index to completion elements to be consumed by HW. */
+static inline void set_psif_cq_hw__tail_indx(volatile struct psif_cq_hw *ptr, u32 data)
+{
+ /* group=3 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[3] = htobe64((be64toh(pte[3]) & 0x00000000ffffffffull) |
+ ((((u64)(data)) & 0x00000000ffffffffull) << 32));
+}
+static inline u32 get_psif_cq_hw__tail_indx(volatile struct psif_cq_hw *ptr)
+{
+ /* group=3 shift=32 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[3]) >> 32) & 0x00000000ffffffffull));
+}
+
+/*
+ * Work queue completion ID. For receive completions this is the entry number
+ * in the receive queue and the receive queue descriptor index. For send
+ * completions this is the sq_sequence number.
+ */
+static inline void set_psif_cq_entry__wc_id(volatile struct psif_cq_entry *ptr, u64 data)
+{
+ /* group=0 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[0] = htobe64((__be64)data);
+}
+static inline u64 get_psif_cq_entry__wc_id(volatile struct psif_cq_entry *ptr)
+{
+ /* group=0 shift=0 bits=64 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u64)be64toh(pte[0]));
+}
+
+static inline void set_psif_cq_entry__qp(volatile struct psif_cq_entry *ptr, u32 data)
+{
+ /* group=1 shift=0 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[1] = htobe64((be64toh(pte[1]) & 0xffffffffff000000ull) |
+ ((((u64)(data)) & 0x0000000000ffffffull) << 0));
+}
+static inline u32 get_psif_cq_entry__qp(volatile struct psif_cq_entry *ptr)
+{
+ /* group=1 shift=0 bits=24 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[1]) >> 0) & 0x0000000000ffffffull));
+}
+
+static inline void set_psif_cq_entry__opcode(volatile struct psif_cq_entry *ptr, enum psif_wc_opcode data)
+{
+ /* group=1 shift=24 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[1] = htobe64((be64toh(pte[1]) & 0xffffffff00ffffffull) |
+ ((((u64)(data)) & 0x00000000000000ffull) << 24));
+}
+static inline enum psif_wc_opcode get_psif_cq_entry__opcode(volatile struct psif_cq_entry *ptr)
+{
+ /* group=1 shift=24 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_wc_opcode)((be64toh(pte[1]) >> 24) & 0x00000000000000ffull));
+}
+
+static inline void set_psif_cq_entry__status(volatile struct psif_cq_entry *ptr, enum psif_wc_status data)
+{
+ /* group=2 shift=24 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0xffffffff00ffffffull) |
+ ((((u64)(data)) & 0x00000000000000ffull) << 24));
+}
+static inline enum psif_wc_status get_psif_cq_entry__status(volatile struct psif_cq_entry *ptr)
+{
+ /* group=2 shift=24 bits=8 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((enum psif_wc_status)((be64toh(pte[2]) >> 24) & 0x00000000000000ffull));
+}
+
+/* sequence number for sanity checking */
+static inline void set_psif_cq_entry__seq_num(volatile struct psif_cq_entry *ptr, u32 data)
+{
+ /* group=7 shift=0 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[7] = htobe64((be64toh(pte[7]) & 0xffffffff00000000ull) |
+ ((((u64)(data)) & 0x00000000ffffffffull) << 0));
+}
+static inline u32 get_psif_cq_entry__seq_num(volatile struct psif_cq_entry *ptr)
+{
+ /* group=7 shift=0 bits=32 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u32)((be64toh(pte[7]) >> 0) & 0x00000000ffffffffull));
+}
+
+static inline void set_psif_ah__remote_lid(volatile struct psif_ah *ptr, u16 data)
+{
+ /* group=2 shift=0 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0xffffffffffff0000ull) |
+ ((((u64)(data)) & 0x000000000000ffffull) << 0));
+}
+static inline u16 get_psif_ah__remote_lid(volatile struct psif_ah *ptr)
+{
+ /* group=2 shift=0 bits=16 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u16)((be64toh(pte[2]) >> 0) & 0x000000000000ffffull));
+}
+
+static inline void set_psif_ah__sl(volatile struct psif_ah *ptr, u8 data)
+{
+ /* group=2 shift=20 bits=4 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ pte[2] = htobe64((be64toh(pte[2]) & 0xffffffffff0fffffull) |
+ ((((u64)(data)) & 0x000000000000000full) << 20));
+}
+static inline u8 get_psif_ah__sl(volatile struct psif_ah *ptr)
+{
+ /* group=2 shift=20 bits=4 */
+ volatile __be64 *const pte = (__be64 *)ptr;
+ return((u8)((be64toh(pte[2]) >> 20) & 0x000000000000000full));
+}
+static inline void set_psif_csr_mmu_config__ta_upper_twelve(volatile void *ptr, u16 data)
+{
+ /* group=0 shift=32 bits=12 */
+ volatile __be64 *pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xfffff000ffffffffull) |
+ ((((u64)(data)) & 0x0000000000000fffull) << 32));
+}
+static inline void set_psif_csr_mmu_config__pa_upper_twelve(volatile void *ptr, u16 data)
+{
+ /* group=0 shift=48 bits=12 */
+ volatile __be64 *pte = (__be64 *)ptr;
+ pte[0] = htobe64((be64toh(pte[0]) & 0xf000ffffffffffffull) |
+ ((((u64)(data)) & 0x0000000000000fffull) << 48));
+}
+
+#if defined (HOST_LITTLE_ENDIAN)
+#elif defined (HOST_BIG_ENDIAN)
+#else
+#error "Could not determine byte order in psif_hw_setget.h !?"
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _PSIF_HW_SETGET_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/psifapi/solaris.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SOLARIS_H
+#define _SOLARIS_H
+
+/*
+ * Definitions of __* types
+ */
+typedef uint64_t __u64;
+typedef uint32_t __u32;
+typedef uint16_t __u16;
+typedef uint8_t __u8;
+
+/*
+ * Endian specific conversion macros
+ */
+#if defined(_LITTLE_ENDIAN)
+#define htobe64(x) htonll(x)
+#define be64toh(x) htonll(x)
+#else /* BIG_ENDIAN */
+#define htobe64(x) (x)
+#define be64toh(x) (x)
+#endif /* BIG_ENDIAN */
+
+#endif /* _SOLARIS_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/sif/sif_int_user.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * sif_int_user.h: This file defines special internal data structures used
+ * to communicate between libsif and the sif driver.
+ * This file is included both from user space and kernel space so
+ * it must not contain any kernel/user specific header file includes.
+ * This file is internal to libsif/sif driver since it relies on HW specific
+ * include files.
+ */
+
+#ifndef _SIF_INT_USER_H
+#define _SIF_INT_USER_H
+
+
+#include <psif_hw_data.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SIF_CACHE_BYTES 64
+
+/*
+ * We use the extension here to communicate with the driver
+ * (for correct debugfs reporting)
+ */
+typedef struct sif_sq_sw {
+ struct psif_sq_sw d; /* Hardware visible descriptor */
+ /* separate the cache lines */
+ __u8 fill[SIF_CACHE_BYTES - sizeof (struct psif_sq_sw)];
+ __u16 last_seq; /* Last used sq seq.num (req. sq->lock) */
+ /* Last sq seq.number seen in a compl (req. cq->lock) */
+ volatile __u16 head_seq;
+}sif_sq_sw_t;
+
+typedef struct sif_rq_sw {
+ struct psif_rq_sw d; /* Hardware visible descriptor */
+ /* separate the cache lines */
+ __u8 fill[SIF_CACHE_BYTES - sizeof (struct psif_rq_sw)];
+ /* current length of queue as #posted - #completed */
+ volatile uint32_t length;
+ __u32 next_seq; /* First unused sequence number */
+}sif_rq_sw_t;
+
+typedef struct sif_cq_sw {
+ struct psif_cq_sw d; /* Hardware visible descriptor */
+ /* separate the cache lines */
+ __u8 fill[SIF_CACHE_BYTES - sizeof (struct psif_cq_sw)];
+ __u32 next_seq; /* First unused sequence number */
+ /* Local copy kept in sync w/hw visible head_indx */
+ __u32 cached_head;
+ /* Last next_seq reported in completion for req_notify_cq */
+ __u32 last_hw_seq;
+ /* Set if req_notify_cq has been called but event not processed */
+ __u32 armed;
+ /* Number of in-flight completions observed by poll_cq */
+ __u32 miss_cnt;
+ /* Number of times 1 or more in-flight completions was seen */
+ __u32 miss_occ;
+}sif_cq_sw_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SIF_INT_USER_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/sif/sif_ireg.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Driver for Oracle PSIF Infiniband PCI Express host channel adapter (HCA)
+ *
+ * sif_ireg.h: Functions to interface with IBTF
+ */
+
+
+#ifndef _PSIF_IREG_H
+#define _PSIF_IREG_H
+
+#include <sif.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+/* IB Device Registration */
+int psif_register_ib_device(psif_t *psifp);
+int psif_unregister_ib_device(psif_t *psifp);
+
+/* Agent handling Registration */
+int psif_agent_handlers_init(psif_t *psifp);
+int psif_agent_handlers_fini(psif_t *psifp);
+
+/* HCA and port related operations */
+ibt_status_t psif_ci_query_hca_ports(ibc_hca_hdl_t, uint8_t,
+ ibt_hca_portinfo_t *);
+ibt_status_t psif_ci_modify_ports(ibc_hca_hdl_t, uint8_t,
+ ibt_port_modify_flags_t, uint8_t);
+ibt_status_t psif_ci_modify_system_image(ibc_hca_hdl_t, ib_guid_t);
+
+
+/* Reliable Datagram Domains */
+ibt_status_t psif_ci_alloc_rdd(ibc_hca_hdl_t, ibc_rdd_flags_t,
+ ibc_rdd_hdl_t *);
+ibt_status_t psif_ci_free_rdd(ibc_hca_hdl_t, ibc_rdd_hdl_t);
+
+/* EE Contexts */
+ibt_status_t psif_ci_alloc_eec(ibc_hca_hdl_t, ibc_eec_flags_t,
+ ibt_eec_hdl_t, ibc_rdd_hdl_t, ibc_eec_hdl_t *);
+ibt_status_t psif_ci_free_eec(ibc_hca_hdl_t, ibc_eec_hdl_t);
+ibt_status_t psif_ci_query_eec(ibc_hca_hdl_t, ibc_eec_hdl_t,
+ ibt_eec_query_attr_t *);
+ibt_status_t psif_ci_modify_eec(ibc_hca_hdl_t, ibc_eec_hdl_t,
+ ibt_cep_modify_flags_t, ibt_eec_info_t *);
+
+/* Memory Windows */
+ibt_status_t psif_ci_alloc_mw(ibc_hca_hdl_t, ibc_pd_hdl_t,
+ ibt_mw_flags_t, ibc_mw_hdl_t *, ibt_rkey_t *);
+ibt_status_t psif_ci_free_mw(ibc_hca_hdl_t, ibc_mw_hdl_t);
+ibt_status_t psif_ci_query_mw(ibc_hca_hdl_t, ibc_mw_hdl_t,
+ ibt_mw_query_attr_t *);
+
+/* Multicast Groups */
+ibt_status_t psif_ci_attach_mcg(ibc_hca_hdl_t, ibc_qp_hdl_t,
+ ib_gid_t, ib_lid_t);
+ibt_status_t psif_ci_detach_mcg(ibc_hca_hdl_t, ibc_qp_hdl_t,
+ ib_gid_t, ib_lid_t);
+
+/* Work Request and Completion Processing */
+ibt_status_t psif_ci_post_send(ibc_hca_hdl_t, ibc_qp_hdl_t,
+ ibt_send_wr_t *, uint_t, uint_t *);
+ibt_status_t psif_ci_post_recv(ibc_hca_hdl_t, ibc_qp_hdl_t,
+ ibt_recv_wr_t *, uint_t, uint_t *);
+ibt_status_t psif_ci_poll_cq(ibc_hca_hdl_t, ibc_cq_hdl_t,
+ ibt_wc_t *, uint_t, uint_t *);
+ibt_status_t psif_ci_notify_cq(ibc_hca_hdl_t, ibc_cq_hdl_t,
+ ibt_cq_notify_flags_t);
+
+/* CI Object Private Data */
+ibt_status_t psif_ci_ci_data_in(ibc_hca_hdl_t, ibt_ci_data_flags_t,
+ ibt_object_type_t, void *, void *, size_t);
+
+/* CI Object Private Data */
+ibt_status_t psif_ci_ci_data_out(ibc_hca_hdl_t, ibt_ci_data_flags_t,
+ ibt_object_type_t, void *, void *, size_t);
+
+
+/* Address translation */
+ibt_status_t psif_ci_map_mem_area(ibc_hca_hdl_t, ibt_va_attr_t *,
+ void *, uint_t, ibt_reg_req_t *, ibc_ma_hdl_t *);
+ibt_status_t psif_ci_unmap_mem_area(ibc_hca_hdl_t, ibc_ma_hdl_t);
+ibt_status_t psif_ci_map_mem_iov(ibc_hca_hdl_t, ibt_iov_attr_t *,
+ ibt_all_wr_t *, ibc_mi_hdl_t *);
+ibt_status_t psif_ci_unmap_mem_iov(ibc_hca_hdl_t, ibc_mi_hdl_t);
+
+/* Allocate L_Key */
+ibt_status_t psif_ci_alloc_lkey(ibc_hca_hdl_t, ibc_pd_hdl_t,
+ ibt_lkey_flags_t, uint_t, ibc_mr_hdl_t *, ibt_pmr_desc_t *);
+
+/* Physical Register Memory Region */
+ibt_status_t psif_ci_register_physical_mr(ibc_hca_hdl_t, ibc_pd_hdl_t,
+ ibt_pmr_attr_t *, void *, ibc_mr_hdl_t *, ibt_pmr_desc_t *);
+ibt_status_t psif_ci_reregister_physical_mr(ibc_hca_hdl_t,
+ ibc_mr_hdl_t, ibc_pd_hdl_t, ibt_pmr_attr_t *, void *, ibc_mr_hdl_t *,
+ ibt_pmr_desc_t *);
+
+/* Mellanox FMR */
+ibt_status_t psif_ci_create_fmr_pool(ibc_hca_hdl_t, ibc_pd_hdl_t,
+ ibt_fmr_pool_attr_t *, ibc_fmr_pool_hdl_t *);
+ibt_status_t psif_ci_destroy_fmr_pool(ibc_hca_hdl_t,
+ ibc_fmr_pool_hdl_t);
+ibt_status_t psif_ci_flush_fmr_pool(ibc_hca_hdl_t, ibc_fmr_pool_hdl_t);
+ibt_status_t psif_ci_register_physical_fmr(ibc_hca_hdl_t,
+ ibc_fmr_pool_hdl_t, ibt_pmr_attr_t *, void *, ibc_mr_hdl_t *,
+ ibt_pmr_desc_t *);
+ibt_status_t psif_ci_deregister_fmr(ibc_hca_hdl_t hca, ibc_mr_hdl_t mr);
+
+/* Memory Allocation/Deallocation */
+
+ibt_status_t
+psif_ci_alloc_io_mem(ibc_hca_hdl_t, size_t, ibt_mr_flags_t, caddr_t *,
+ ibt_mem_alloc_hdl_t);
+
+ibt_status_t
+psif_ci_get_hca_port_counters(ibc_hca_hdl_t, uint8_t,
+ ibt_hca_port_cntr_flags_t, ibt_hca_port_counters_t *);
+
+ibt_status_t
+psif_ci_set_ibtl_private(ibc_hca_hdl_t, ibt_object_type_t, void *, void *);
+ibt_status_t
+psif_ci_get_ibtl_private(ibc_hca_hdl_t, ibt_object_type_t, void *, void **);
+
+ibt_status_t
+psif_ci_get_hca_resource_counters(ibc_hca_hdl_t,
+ ibt_hca_resource_counters_t *);
+
+ibt_status_t
+psif_ci_alloc_counter(ibc_hca_hdl_t, ibt_ci_counter_type_t,
+ ibc_counter_hdl_t *);
+ibt_status_t
+psif_ci_free_counter(ibc_hca_hdl_t, ibc_counter_hdl_t);
+ibt_status_t
+psif_ci_query_counter(ibc_hca_hdl_t, ibc_counter_hdl_t,
+ ibt_ci_counters_t *);
+ibt_status_t
+psif_ci_reset_counter(ibc_hca_hdl_t, ibc_counter_hdl_t);
+ibt_status_t
+psif_ci_set_qp_counter(ibc_hca_hdl_t, ibc_counter_hdl_t,
+ibc_qp_hdl_t *, uint_t);
+ibt_status_t
+psif_ci_get_qp_counter(ibc_hca_hdl_t, ibc_qp_hdl_t *,
+ ibc_counter_hdl_t *, uint_t);
+ibt_status_t psif_ci_not_supported();
+
+
+/* Dma handle struct for the kmem cache */
+typedef struct psif_dmahdl_cache_s {
+ ddi_dma_handle_t h_dmahdl;
+} psif_dmahdl_cache_t;
+_NOTE(SCHEME_PROTECTS_DATA("safe sharing", psif_dmahdl_cache_s::h_dmahdl))
+
+/* Address translation */
+struct ibc_ma_s {
+ int h_ma_addr_list_len;
+ void *h_ma_addr_list;
+ psif_dmahdl_cache_t *h_ma_dmahdlp; /* not FRWR */
+ ddi_dma_handle_t h_ma_dmahdl; /* FRWR-only */
+ ddi_dma_handle_t h_ma_list_hdl;
+ ddi_acc_handle_t h_ma_list_acc_hdl;
+ size_t h_ma_real_len;
+ caddr_t h_ma_kaddr;
+ ibt_phys_addr_t h_ma_list_cookie;
+ ddi_umem_cookie_t h_ma_umem_cookie;
+ ibc_mr_hdl_t h_ma_mr_hdl; /* used for umem callback */
+};
+_NOTE(SCHEME_PROTECTS_DATA("protected via umapdb scheme",
+ ibc_ma_s::h_ma_mr_hdl))
+
+extern uint32_t psif_max_cq_size;
+extern uint32_t psif_max_srq_size;
+extern uint32_t psif_max_sq_size;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PSIF_IREG_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/include/sif/sif_user.h Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Userspace library for Oracle SIF Infiniband PCI Express
+ * host channel adapter (HCA)
+ *
+ * sif_user.h: This file defines sif specific verbs extension request/response.
+ * This file is included both from user space and kernel space so
+ * it must not contain any kernel/user specific header file includes.
+ */
+
+#ifndef _SIF_USER_H
+#define _SIF_USER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Binary interface control:
+ * Major version difference indicate backward incompatible changes
+ * Minor version difference indicate that only a common subset of
+ * features are available.
+ *
+ */
+#define SIF_UVERBS_ABI_MAJOR_VERSION 3
+#define SIF_UVERBS_ABI_MINOR_VERSION 4
+
+/* Bw comp */
+#define SIF_UVERBS_VERSION(x, y) ((x) << 8 | (y))
+#define SIF_UVERBS_ABI_VERSION \
+ SIF_UVERBS_VERSION(SIF_UVERBS_ABI_MAJOR_VERSION, \
+ SIF_UVERBS_ABI_MINOR_VERSION)
+
+/*
+ * Bit 5 is not used by the PSIF_WC_OPCODE_FOO_BAR enums. Hence, using
+ * it to indicate if QP has been destroyed before the CQE has been
+ * polled
+ */
+#define SIF_WC_QP_DESTROYED (1<<5)
+
+/*
+ * This struct will be amended to an un-polled cqe, in case the QP has
+ * been destroyed before the CQEs are polled. The information is
+ * needed in order to handle flushing of SRQs and generation of Last
+ * WQE Reached event.
+ *
+ * The information amended to the CQE is _only_ valid if the CQE has
+ * been marked with SIF_WC_QP_DESTROYED.
+ */
+struct sif_post_mortem_qp_info_in_cqe {
+ int was_srq;
+ int srq_idx;
+ int qpn; /* Could be useful for de-bugging/logging */
+};
+
+#ifndef __u32
+#define __u32 uint32_t
+#endif
+
+/*
+ * These definitions must be kept in sync with
+ * the ones in libsif's sif.h
+ */
+typedef enum sif_vendor_flags {
+ /*
+ * Use special mmu setup in associated mappings
+ * NB! Modifies input to ibv_reg_mr!
+ */
+ MMU_special = 0x1,
+ /* Trigger send queue mode instead of using VCBs */
+ SQ_mode = 0x2,
+ /* Enable EPS-A proxying - requires the eps_a field to be set */
+ proxy_mode = 0x4,
+ /* Enable kernel mode - default is direct user mode */
+ SVF_kernel_mode = 0x8,
+ /* Value to use for the qosl bit in the qp state */
+ tsu_qosl = 0x10
+} sif_vendor_flags_t;
+
+typedef enum sif_mem_type {
+ SIFMT_BYPASS, /* Use MMU bypass in associated mmu contexts */
+ SIFMT_UMEM, /* Normal default umem based user level mapping */
+ /* Mapping of user memory based on the process' own page table */
+ SIFMT_UMEM_SPT,
+ /*
+ * A large (sparsely populated) SIF only vaddr mapping
+ * (used for a.o.SQ CMPL)
+ */
+ SIFMT_CS,
+ /* Special mapping of a vaddr range to a single page (see #1931) */
+ SIFMT_ZERO,
+ /* MMU bypass mapped read only for device (requires IOMMU enabled) */
+ SIFMT_BYPASS_RO,
+ /* GVA2GPA mapped read only for device (requires IOMMU enabled) */
+ SIFMT_UMEM_RO,
+ /* Use GVA2GPA but input is based on a phys_buf array instead of umem */
+ SIFMT_PHYS,
+ /*
+ * Use GVA2GPA but input is based on a page address array instead
+ * of umem
+ */
+ SIFMT_FMR,
+ /* Similar to FMR but input pages are 2M instead of 4K */
+ SIFMT_2M,
+ /* Bypass mode - special kernel mappings with no memory allocated */
+ SIFMT_NOMEM,
+ /* sif_kmem based 4K page allocation - mostly for test purposes */
+ SIFMT_4K,
+ SIFMT_RDMA,
+ SIFMT_PTONLY,
+ SIFMT_CTRL_PT,
+ SIFMT_MAX
+} sif_mem_type_t;
+
+typedef enum sif_proxy_type {
+ SIFPX_OFF, /* Default value - no proxying */
+ SIFPX_EPSA_1,
+ SIFPX_EPSA_2,
+ SIFPX_EPSA_3,
+ SIFPX_EPSA_4
+} sif_proxy_type_t;
+
+
+typedef enum sif_flush_type {
+ NO_FLUSH,
+ FLUSH_SQ,
+ FLUSH_RQ
+} sif_flush_type_t;
+
+/* These should be multiple of 64 bytes and densely packed: */
+
+typedef struct sif_get_context_ext {
+ uint32_t abi_version;
+ uint32_t reserved;
+} sif_get_context_ext_t;
+
+typedef struct sif_get_context_resp_ext {
+ /* Distance in bytes between descriptor elements */
+ uint32_t sq_sw_ext_sz;
+ uint32_t rq_ext_sz;
+ uint32_t cq_ext_sz;
+ /* Number of entries per block of descriptors */
+ uint32_t sq_entry_per_block;
+ uint32_t rq_entry_per_block;
+ uint32_t cq_entry_per_block;
+ /* Dist between sq hw descriptor elms, from >= v.3.3 */
+ uint32_t sq_hw_ext_sz;
+ uint32_t reserved;
+} sif_get_context_resp_ext_t;
+
+typedef struct sif_alloc_pd_resp_ext {
+ /* The virtual collect buffer to use by this protection domain */
+ int cb_idx;
+ uint32_t reserved;
+} sif_alloc_pd_resp_ext_t;
+
+typedef struct sif_create_cq_ext {
+ enum sif_vendor_flags flags;
+ enum sif_proxy_type proxy;
+} sif_create_cq_ext_t;
+
+typedef struct sif_create_cq_resp_ext {
+ uint32_t cq_idx;
+ uint32_t reserved;
+ uint32_t cq_entries;
+} sif_create_cq_resp_ext_t;
+
+
+typedef struct sif_create_qp_ext {
+ enum sif_vendor_flags flags;
+ enum sif_proxy_type proxy;
+} sif_create_qp_ext_t;
+
+typedef struct sif_create_qp_resp_ext {
+ uint32_t qp_idx;
+ uint32_t rq_idx;
+ uint32_t magic;
+ uint32_t sq_extent;
+ uint32_t rq_extent;
+ uint32_t sq_sgl_offset;
+ uint32_t sq_mr_idx;
+ uint32_t reserved;
+ uint64_t sq_dma_handle;
+} sif_create_qp_resp_ext_t;
+
+typedef struct sif_modify_qp_ext
+{
+ enum sif_flush_type flush;
+ uint32_t reserved;
+} sif_modify_qp_ext_t;
+
+
+typedef struct sif_reg_mr_ext {
+ enum sif_vendor_flags flags;
+ enum sif_mem_type mem_type;
+ /* Used by gva_type SIFGT_ZERO - indicates psif vmap length */
+ uint64_t map_length;
+ /* Used by gva_type SIFGT_ZERO - indicates valid memory length */
+ uint64_t phys_length;
+} sif_reg_mr_ext_t;
+
+typedef struct sif_reg_mr_resp_ext {
+ uint64_t uv2dma; /* Used to support bypass mode */
+} sif_reg_mr_resp_ext_t;
+
+typedef struct sif_create_srq_ext {
+ enum sif_vendor_flags flags;
+ uint32_t res1;
+} sif_create_srq_ext_t;
+
+typedef struct sif_create_srq_resp_ext {
+ uint32_t index;
+ uint32_t extent;
+} sif_create_srq_resp_ext_t;
+
+typedef struct sif_create_ah_resp_ext {
+ uint32_t index;
+ uint32_t reserved;
+} sif_create_ah_resp_ext_t;
+
+/* mmap offset encoding */
+
+enum sif_mmap_cmd {
+ SIF_MAP_NONE, /* No mapping */
+ /* Map a collect buffer - cb index as argument */
+ SIF_MAP_CB,
+ /* Map an SQ, RQ or CQ (entries) - queue index as argument */
+ SIF_MAP_SQ,
+ SIF_MAP_RQ,
+ SIF_MAP_CQ,
+ /*
+ * Map a block of SQ, RQ or CQ software descriptors -
+ * block index as argument
+ */
+ SIF_MAP_SQ_SW,
+ SIF_MAP_RQ_SW,
+ SIF_MAP_CQ_SW,
+ /* These are safe to map read-only (so far only sq_hw in use) */
+ /* Map a block of qp descriptors - block index as argument */
+ SIF_MAP_QP,
+ /*
+ * Map a block of SQ, RQ or CQ hardware descriptors -
+ * block index as argument
+ */
+ SIF_MAP_SQ_HW,
+ SIF_MAP_RQ_HW,
+ SIF_MAP_CQ_HW,
+ SIF_MAP_MAX
+};
+
+static inline uint64_t mmap_set_cmd(enum sif_mmap_cmd cmd, uint32_t index)
+{
+ return ((uint64_t)cmd << 44) | ((uint64_t)index << 13);
+}
+
+static inline void mmap_get_cmd(uint64_t offset, enum sif_mmap_cmd *cmdp,
+ uint32_t *idxp)
+{
+ *cmdp = (offset >> 44) & 0xff;
+ *idxp = (offset >> 13) & 0x7fffffff;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SIF_USER_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/libsif.license Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,31 @@
+Copyright (c) 2016, Oracle America, Inc. and its Affiliates
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above
+copyright notice, this list of conditions and the following
+disclaimer in the documentation and/or other materials provided
+with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its
+contributors may be used to endorse or promote products derived
+from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+THE POSSIBILITY OF SUCH DAMAGE.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/patches/001-libsif-config.patch Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,139 @@
+# This patch does the config changes specific to solaris.
+# It is developed By solaris PSIF team. We plan to have a common upstream repo
+# and submit these changes to it, but do not yet have a target date of doing it.
+diff -r 1584d5cbb44d Makefile.am
+--- a/Makefile.am Wed Feb 10 12:40:22 2016 +0530
++++ b/Makefile.am Tue Mar 01 16:24:16 2016 +0530
+@@ -9,7 +9,11 @@
+ -avoid-version \
+ -release @IBV_DEVICE_LIBRARY_EXTENSION@
+
+-lib_LTLIBRARIES = src/libsif.la src/libsifwa.la
++lib_LTLIBRARIES = src/libsif.la
++if !SIF_SOLARIS
++lib_LTLIBRARIES += src/libsifwa.la
++endif
++
+ src_libsif_la_SOURCES = \
+ src/cpu_features.c \
+ src/cq.c \
+@@ -24,14 +28,20 @@
+
+ src_libsif_la_LDFLAGS = $(SIF_LDFLAGS) $(sif_version_script)
+
++if SIF_SOLARIS
++sifconfdir = $(datadir)/libibverbs.d
++else
+ src_libsifwa_la_SOURCES = src/sif_eps.c
+ src_libsifwa_la_CFLAGS = $(AM_CFLAGS) $(NETLINK_CFLAGS)
+ src_libsifwa_la_LDFLAGS = $(SIF_LDFLAGS) $(NETLINK_LIBS) $(sifwa_version_script)
+
+ sifconfdir = $(sysconfdir)/libibverbs.d
++endif
+ sifconf_DATA = sif.driver
+
++if !SIF_SOLARIS
+ -include $(srcdir)/genrules.mk
++endif
+
+ EXTRA_DIST = \
+ libsif.spec.in \
+@@ -67,8 +77,10 @@
+ src/psif_hw_print.c
+
+ libsif_includedir = $(includedir)/infiniband
+-libsif_include_HEADERS = src/sif.h src/sif_eps.h src/sif_drvapi.h
+-
++libsif_include_HEADERS = src/sif.h
++if !SIF_SOLARIS
++libsif_include_HEADERS += src/sif_eps.h src/sif_drvapi.h
++endif
+
+ dist-hook:
+ @rm -f $(distdir)/m4/{sifdrv,psifapi}.m4
+diff -r 1584d5cbb44d configure.ac
+--- a/configure.ac Wed Feb 10 12:40:22 2016 +0530
++++ b/configure.ac Tue Mar 01 16:24:16 2016 +0530
+@@ -10,6 +10,10 @@
+ # Silent rules by default - use make V=1 for verbose
+ AM_SILENT_RULES([yes])
+
++AS_IF([test "x$os_type" = "x" ],
++ [os_type=`uname -a | awk 'BEGIN { FS=" " } { print $1; }'`],
++ [])
++
+ AC_CONFIG_MACRO_DIR([m4])
+ m4_ifdef([AM_PROG_AR], [AM_PROG_AR])
+
+@@ -30,7 +34,7 @@
+
+ dnl Checks for programs
+ AC_PROG_CC
+-
++AM_CONDITIONAL(SIF_SOLARIS, test $os_type != Linux)
+
+
+
+@@ -40,6 +44,7 @@
+ AC_MSG_ERROR(
+ [ibv_get_device_list() not found. libsif requires libibverbs.]))
+
++if test $os_type = Linux; then
+ PKG_CHECK_MODULES(LIBNL3, libnl-3.0 >= 3.1, [have_libnl3=yes],[ dnl
+ have_libnl3=no
+ PKG_CHECK_MODULES([NETLINK], [libnl-1 >= 1.1])
+@@ -52,7 +57,7 @@
+ else
+ LIBS+=" $NETLINK_LIBS"
+ fi
+-
++fi
+ dnl Checks for header files.
+ AC_CHECK_HEADER(infiniband/driver.h, [],
+ AC_MSG_ERROR([<infiniband/driver.h> not found. libsif requires libibverbs.]))
+@@ -86,11 +91,34 @@
+ AC_SUBST(IBV_DEVICE_LIBRARY_EXTENSION)
+
+ SIF_GET_CONTEXT_CONTAINER="return container_of(ibctx, struct sif_context, ibv_ctx);"
++SIF_GET_QP_CONTAINER="return container_of(ibqp, struct sif_qp, ibv_qp);"
++SIF_GET_SRQ_CONTAINER="return container_of(ibsrq, struct sif_rq, ibv_srq);"
++SIF_GET_STRUCT="ibv"
+
+-AM_CONDITIONAL([HAVE_VERBS_REGISTER_DRIVER],dnl
++if test $os_type = Linux; then
++ AM_CONDITIONAL([HAVE_VERBS_REGISTER_DRIVER],dnl
+ [SIF_GET_CONTEXT_CONTAINER="return container_of(ibctx, struct sif_context, verbs_ctx.context);"])
++ AM_CONDITIONAL([HAVE_VERBS_REGISTER_DRIVER],dnl
++ [SIF_GET_QP_CONTAINER="return container_of(ibqp, struct sif_qp, verbs_qp.qp);"])
++ AM_CONDITIONAL([HAVE_VERBS_REGISTER_DRIVER],dnl
++ [SIF_GET_SRQ_CONTAINER="return container_of(ibsrq, struct sif_rq, verbs_srq.srq);"])
++ AM_CONDITIONAL([HAVE_VERBS_REGISTER_DRIVER], [SIF_GET_STRUCT="verbs"])
++fi
++
++if test $os_type = SunOS ; then
++ AM_CONDITIONAL([HAVE_VERBS_REGISTER_DRIVER],dnl
++ [SIF_GET_CONTEXT_CONTAINER="return container_of(ibctx, struct sif_context, ibv_ctx);"])
++ AM_CONDITIONAL([HAVE_VERBS_REGISTER_DRIVER],dnl
++ [SIF_GET_QP_CONTAINER="return container_of(ibqp, struct sif_qp, ibv_qp);"])
++ AM_CONDITIONAL([HAVE_VERBS_REGISTER_DRIVER],dnl
++ [SIF_GET_SRQ_CONTAINER="return container_of(ibsrq, struct sif_rq, ibv_srq);"])
++ AM_CONDITIONAL([HAVE_VERBS_REGISTER_DRIVER], [SIF_GET_STRUCT="ibv"])
++fi
+
+ AC_SUBST([SIF_GET_CONTEXT_CONTAINER])
++AC_SUBST([SIF_GET_STRUCT])
++AC_SUBST([SIF_GET_QP_CONTAINER])
++AC_SUBST([SIF_GET_SRQ_CONTAINER])
+
+ AC_CACHE_CHECK(whether ld accepts --version-script, ac_cv_version_script,
+ [if test -n "`$LD --help < /dev/null 2>/dev/null | grep version-script`"; then
+diff -r 1584d5cbb44d sif.driver
+--- a/sif.driver Wed Feb 10 12:40:22 2016 +0530
++++ b/sif.driver Tue Mar 01 16:24:16 2016 +0530
+@@ -1,1 +1,6 @@
++#
++# Copyright (c) 2014, 2016, Oracle America, Inc. and its Affiliates
++# All rights reserved.
++#
++# WARNING: Do not change these settings unless you know what you are doing.
+ driver sif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/components/open-fabrics/libsif/patches/002-libsif-src.patch Tue Mar 08 21:43:23 2016 -0800
@@ -0,0 +1,1480 @@
+# This patch does the src changes specific to solaris.
+# It is developed By solaris PSIF team. We plan to have a common upstream repo
+# and submit these changes to it, but do not yet have a target date of doing it.
+diff -r 1584d5cbb44d src/cq.c
+--- a/src/cq.c Wed Feb 10 12:40:22 2016 +0530
++++ b/src/cq.c Tue Mar 08 15:00:55 2016 +0530
+@@ -43,7 +43,9 @@
+ #include <strings.h>
+ #include <pthread.h>
+ #include <errno.h>
++#if !(defined(__SVR4) && defined(__sun))
+ #include <endian.h>
++#endif
+ #include <string.h>
+
+ #include "sif.h"
+@@ -139,7 +141,7 @@
+ qp->sq.sw->head_seq = sq_seq_num;
+
+ sif_log(uc, SIF_CQ,
+- "wr_id 0x%lx on qp/sq %d sq_seq_num %d",
++ "wr_id 0x%"PRIx64" on qp/sq %d sq_seq_num %d",
+ wc->wr_id, cqe->qp, sq_seq_num);
+
+ if (uc->debug_mask & SIF_SQSOVRN)
+@@ -154,9 +156,11 @@
+ */
+ struct sif_rq *find_rq(struct sif_qp *qp, struct sif_cq *cq)
+ {
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ if (qp->verbs_qp.qp.qp_type == IBV_QPT_XRC_RECV)
+ return cq->xsrq;
+ else
++#endif
+ return qp->rq;
+ }
+
+@@ -198,18 +202,23 @@
+ struct ibv_query_qp cmd;
+ int ret = 0;
+
++#ifdef HAVE_VERBS_REGISTER_DRIVER
++ struct ibv_qp *ibv_qp = &qp->verbs_qp.qp;
++#else
++ struct ibv_qp *ibv_qp = &qp->ibv_qp;
++#endif
+ memset(&attr, 0, sizeof(attr));
+ memset(&init_attr, 0, sizeof(init_attr));
+- ret = ibv_cmd_query_qp(&qp->verbs_qp.qp, &attr, IBV_QP_STATE, &init_attr,
++ ret = ibv_cmd_query_qp(ibv_qp, &attr, IBV_QP_STATE, &init_attr,
+ &cmd, sizeof cmd);
+ if (!ret && attr.qp_state == IBV_QPS_ERR) {
+- if (flush_qp(&qp->verbs_qp.qp, &attr, FLUSH_RQ))
++ if (flush_qp(ibv_qp, &attr, FLUSH_RQ))
+ sif_log(uc, SIF_INFO,"failed to flush RQ, QP %d", wc->qp_num);
+ }
+ }
+ #endif
+ /* TBD: Handle sg list case */
+- sif_log(uc, SIF_CQ,"wr_id 0x%lx queue len %d", wc->wr_id, rq_len);
++ sif_log(uc, SIF_CQ,"wr_id 0x%"PRIx64" queue len %d", wc->wr_id, rq_len);
+ return 0;
+ }
+
+@@ -253,7 +262,7 @@
+ */
+ sif_log(uc, log_level,
+ "error compl on cq %d, seq_num %d qpn 0x%x, "
+- "wc_id %Ld status %s(%d), vendor_err 0x%x",
++ "wc_id %"SIFPRIx64" status %s(%d), vendor_err 0x%x",
+ cq->index, lcqe.seq_num, qpn, lcqe.wc_id.rq_id,
+ string_enum_psif_wc_status(lcqe.status),
+ lcqe.status, lcqe.vendor_err);
+@@ -282,7 +291,7 @@
+ default:
+ sif_log(uc, SIF_WCE,
+ "unknown opcode on cq %d, seq_num %d qpn 0x%x, "
+- "wc_id %Ld status %s(%d), vendor_err 0x%x",
++ "wc_id %"SIFPRIx64" status %s(%d), vendor_err 0x%x",
+ cq->index, lcqe.seq_num, qpn, lcqe.wc_id.rq_id,
+ string_enum_psif_wc_status(lcqe.status),
+ lcqe.status, lcqe.vendor_err);
+diff -r 1584d5cbb44d src/encoding.h
+--- a/src/encoding.h Wed Feb 10 12:40:22 2016 +0530
++++ b/src/encoding.h Tue Mar 08 15:00:55 2016 +0530
+@@ -37,16 +37,25 @@
+ #define _SIF_ENCODING_H
+
+ #include <sys/types.h>
++#if !(defined(__SVR4) && defined(__sun))
+ #include "kernel_types.h"
++#endif
+ #include "psif_hw_data.h"
+
+ #define true 1
+ #define false 0
+ #define bool int
+
++#if defined(__SVR4) && defined(__sun)
++#include <sys/atomic.h>
++typedef volatile uint32_t atomic_t;
++#define atomic_inc_return(ptr) atomic_inc_32_nv(ptr)
++#define atomic_dec_return(ptr) atomic_dec_32_nv(ptr)
++#else
+ typedef volatile __u32 atomic_t;
+ #define atomic_inc_return(ptr) __sync_add_and_fetch(ptr, 1)
+ #define atomic_dec_return(ptr) __sync_sub_and_fetch(ptr, 1)
++#endif
+
+ #if 1
+ #define SIF_INFO 0x1L
+@@ -85,10 +94,17 @@
+ #endif
+ #define min(x,y) ((x) > (y) ? (y) : (x))
+
++#if defined(__SVR4) && defined(__sun)
++#define cpu_to_be32 htonl
++#define cpu_to_be64 htonll
++#define be32_to_cpu ntohl
++#define be64_to_cpu ntohll
++#else
+ #define cpu_to_be32 htobe32
+ #define cpu_to_be64 htobe64
+ #define be32_to_cpu be32toh
+ #define be64_to_cpu be64toh
++#endif
+
+ #ifdef __x86_64
+ #undef wmb
+diff -r 1584d5cbb44d src/hwprint.c
+--- a/src/hwprint.c Wed Feb 10 12:40:22 2016 +0530
++++ b/src/hwprint.c Tue Mar 08 15:00:55 2016 +0530
+@@ -34,6 +34,8 @@
+ * hwprint.c: User level wrapper for hardware (generated) struct print support
+ */
+ #include <sys/types.h>
++#if !(defined(__SVR4) && defined(__sun))
+ #define OS_PRIx64 "lx"
++#endif
+ #include "sif.h"
+ #include "psif_hw_print.c"
+diff -r 1584d5cbb44d src/mr.c
+--- a/src/mr.c Wed Feb 10 12:40:22 2016 +0530
++++ b/src/mr.c Tue Mar 08 15:00:55 2016 +0530
+@@ -45,6 +45,7 @@
+ #include "sif_abi.h"
+ #include "mr.h"
+ #include <assert.h>
++#include <errno.h>
+
+ struct ibv_mr *sif_reg_mr(struct ibv_pd *ibpd, void *addr,
+ size_t length, int access)
+@@ -103,7 +104,7 @@
+ sctx->bypass_mr_ref = malloc(ref_sz);
+ if (!sctx->bypass_mr_ref) {
+ sif_log(sctx, SIF_INFO,
+- "Failed to allocate 0x%lx bytes of storage for bypass MR references\n",
++ "Failed to allocate 0x%zx bytes of storage for bypass MR references\n",
+ ref_sz);
+ ret = ENOMEM;
+ goto bypass_ref_alloc_failed;
+@@ -169,6 +170,37 @@
+ return 0;
+ }
+
++#if defined(__SVR4) && defined(__sun)
++/*
++ * Libibverbs will not validate the function ptr for non-NULL value for fmr
++ * callbacks.If undefined, application will core dump if it uses any of
++ * these calls.
++ */
++struct ibv_mr *sif_reg_mr_relaxed(struct ibv_pd *ibpd, void *addr, size_t length, int access)
++{
++ struct sif_context *sctx = to_sctx(ibpd->context);
++
++ sif_log(sctx, SIF_INFO, "sif_reg_relaxed_mr Not Implemented");
++ errno = ENOTSUP;
++
++ return NULL;
++}
++
++int sif_dereg_mr_relaxed(struct ibv_mr *ibmr)
++{
++ struct sif_context *sctx = to_sctx(ibmr->context);
++ sif_log(sctx, SIF_INFO, "sif_dereg_relaxed_mr Not Implemented");
++ return ENOTSUP;
++}
++
++int sif_flush_relaxed_mr(struct ibv_pd *ibpd)
++{
++ struct sif_context *sctx = to_sctx(ibpd->context);
++ sif_log(sctx, SIF_INFO, "sif_flush_relaxed_mr Not Implemented");
++ return ENOTSUP;
++}
++#endif
++
+ struct ibv_mw *sif_alloc_mw(struct ibv_pd *ibpd, enum ibv_mw_type type)
+ {
+ fprintf(stderr, PFX "%s Not implemented\n", __func__);
+diff -r 1584d5cbb44d src/sif.c
+--- a/src/sif.c Wed Feb 10 12:40:22 2016 +0530
++++ b/src/sif.c Tue Mar 08 15:00:55 2016 +0530
+@@ -44,6 +44,7 @@
+ #include <sys/mman.h>
+ #include <pthread.h>
+ #include <string.h>
++#include <infiniband/verbs.h>
+
+ #ifndef HAVE_IBV_READ_SYSFS_FILE
+ #include <sys/types.h>
+@@ -76,6 +77,8 @@
+ HCA(SUN, PSIF_VF),
+ HCA(SUN, SIBS_PF),
+ HCA(SUN, SIBS_VF),
++ HCA(SUN, SIBS2_PF),
++ HCA(SUN, SIBS2_VF),
+ };
+
+ static struct ibv_context_ops sif_ctx_ops = {
+@@ -90,6 +93,12 @@
+ .rereg_mr = sif_rereg_mr,
+ .dereg_mr = sif_dereg_mr,
+
++#if defined(__SVR4) && defined(__sun)
++ .reg_mr_relaxed= sif_reg_mr_relaxed,
++ .dereg_mr_relaxed = sif_dereg_mr_relaxed,
++ .flush_relaxed_mr = sif_flush_relaxed_mr,
++#endif
++
+ .alloc_mw = sif_alloc_mw,
+ .bind_mw = sif_bind_mw,
+ .dealloc_mw = sif_dealloc_mw,
+@@ -159,6 +168,16 @@
+ struct sif_device *sdev = to_sdev(ibdev);
+ char value[20];
+ char param_path[IBV_SYSFS_PATH_MAX];
++#if defined(__SVR4) && defined(__sun)
++/*
++ * See CR 22214822,22245798:collect buffer mode disabled for solaris
++ * SQ gives better performance on SPARC mode for
++ * smaller message sizes.
++ */
++ const char *cb_mode;
++ int mode;
++ const char *user_cb_disable;
++#endif
+ const char* dbm;
+ const char *cfum;
+ const char *odm;
+@@ -170,6 +189,9 @@
+
+ #ifdef HAVE_VERBS_REGISTER_DRIVER
+ context = to_sctx(ibv_ctx);
++#if defined(__SVR4) && defined(__sun)
++ ibv_ctx->device = &v_device->device;
++#endif
+ #else
+ context = malloc(sizeof(*context));
+ if (!context)
+@@ -177,23 +199,20 @@
+ /* The sif specific part needs to be zeroed out */
+ memset(context, 0, sizeof(*context));
+ ibv_ctx = &context->ibv_ctx;
++#if defined(__SVR4) && defined(__sun)
++ context->ibv_ctx.device = ibdev;
++#endif
+ #endif
+
+ /* Satisfy valgrind */
+ memset(&cmd,0,sizeof(cmd));
+
+- /* Memory is allocated zeroed out by libsif */
+-
+- if (!sdev->min_resp_ms) {
+- if (ibv_read_sysfs_file(sdev->verbs_dev.device.ibdev_path, "min_resp_ms",
+- value, sizeof value) < 0)
+- sdev->min_resp_ms = 500;
+- else
+- sscanf(value, "%li", &sdev->min_resp_ms);
+- }
+-
+ /* Re-read the current kernel default flags */
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ sprintf(param_path, "%s/device/driver/module/parameters", sdev->verbs_dev.device.ibdev_path);
++#else
++ sprintf(param_path, "%s/device/driver/module/parameters", sdev->ibv_dev.ibdev_path);
++#endif
+ if (ibv_read_sysfs_file(param_path, "vendor_flags",
+ value, sizeof value) < 0)
+ context->kernel_flags = 0;
+@@ -207,8 +226,13 @@
+ (SIF_UVERBS_ABI_MINOR_VERSION & 0xff);
+ ibv_ctx->cmd_fd = cmd_fd;
+
++#if defined(__SVR4) && defined(__sun)
++ ret = ibv_cmd_get_context(ibv_ctx, &cmd.ibv_cmd,
++ sizeof cmd.ibv_cmd, &resp.ibv_resp, sizeof resp);
++#else
+ ret = ibv_cmd_get_context(ibv_ctx, &cmd.ibv_cmd,
+ sizeof cmd, &resp.ibv_resp, sizeof resp);
++#endif
+ if (ret)
+ goto err_free;
+
+@@ -230,6 +254,18 @@
+ context->opt_disable_mask = odm ? strtoll(odm, NULL, 0) : 0;
+ disa_x_wc = context->opt_disable_mask & SOD_EXPLICIT_WC;
+
++#if defined(__SVR4) && defined(__sun)
++ user_cb_disable = getenv("SIF_DISABLE_USER_CB");
++ context->user_cb_disable = user_cb_disable ? strtoll(user_cb_disable, NULL, 0) : 0;
++ /*
++ * SQ mode is the default mode on solaris
++ * set env variable SIF_CB_MODE = 1 to change to cb_mode
++ */
++ cb_mode = getenv("SIF_CB_MODE");
++ mode = cb_mode ? strtol(cb_mode, NULL, 0) : 0;
++ context->default_flags |= mode? 0: SQ_mode;
++ sif_log(context, SIF_INFO, "Mode: %s", mode? "CB/SQ": "SQ");
++#endif
+ probe_cpu_features();
+ sif_log(context, SIF_VERBS, "CPU features detected: %s",
+ cpu_features_to_str(feature_mnemonics_size, feature_mnemonics));
+@@ -369,6 +405,12 @@
+ dev->abi_version = abi_version;
+ dev->min_resp_ms = 0; /* Will be set by the first allocated context */
+
++#if defined(__SVR4) && defined(__sun)
++ /*
++ * SIFMT_BYPASS mode is not supported for userspace on Solaris, mr_size is
++ * not required */
++ dev->mr_size = 4096;
++#else
+ if (ibv_read_sysfs_file("/sys/module/sif", "parameters/mr_size",
+ value, sizeof value) < 0) {
+ fprintf(stderr, "Failed to read mr_size\n");
+@@ -376,6 +418,7 @@
+ return NULL;
+ }
+ sscanf(value, "%i", &dev->mr_size);
++#endif
+
+ #ifndef HAVE_VERBS_REGISTER_DRIVER
+ dev->ibv_dev.ops = sif_dev_ops;
+diff -r 1584d5cbb44d src/sif.h.in
+--- a/src/sif.h.in Wed Feb 10 12:40:22 2016 +0530
++++ b/src/sif.h.in Tue Mar 08 15:00:55 2016 +0530
+@@ -34,6 +34,9 @@
+ * sif.h.in: TBD: **insert desc here**
+ */
+
++#if HAVE_CONFIG_H
++#include <config.h>
++#endif /* HAVE_CONFIG_H */
+ #ifndef _SIF_H
+ #define _SIF_H
+ #if defined(__cplusplus)
+@@ -54,6 +57,8 @@
+ #define PCI_DEVICE_ID_PSIF_VF 0x2089
+ #define PCI_DEVICE_ID_SIBS_PF 0x2188
+ #define PCI_DEVICE_ID_SIBS_VF 0x2189
++#define PCI_DEVICE_ID_SIBS2_PF 0x2198
++#define PCI_DEVICE_ID_SIBS2_VF 0x2199
+ #endif
+
+ #define HIDDEN __attribute__((visibility ("hidden")))
+@@ -64,6 +69,19 @@
+ #define SOD_EXPLICIT_WC 0x1
+ #define SOD_WC_TO_SQ 0x2
+
++#if defined(__SVR4) && defined(__sun)
++#define SIF_PAGE_SHIFT 12
++#define SIF_PAGE_SIZE (1 << SIF_PAGE_SHIFT)
++
++#define SIF_DOORBELL_IOCTL 30464
++#define container_of(ptr, type, member) ({ \
++ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
++ (type *)( (char *)__mptr - offsetof(type,member) );})
++#define SIFPRIx64 PRIx64
++#include "sif_user.h"
++#else
++#define SIFPRIx64 "llx"
++
+ enum sif_vendor_flags
+ {
+ MMU_special = 0x1, /* Use special mmu setup in associated mappings
+@@ -102,9 +120,10 @@
+ FLUSH_SQ,
+ FLUSH_RQ
+ };
++#endif
+
+ struct sif_device {
+- struct verbs_device verbs_dev;
++ struct @SIF_GET_STRUCT@_device @SIF_GET_STRUCT@_dev;
+ uint16_t abi_version;
+ uint32_t mr_size; /* Maximal number of MRs in the system */
+ uint64_t min_resp_ms; /* Universal timeout scaling for sif */
+@@ -160,7 +179,7 @@
+
+ struct sif_rq {
+ struct sif_map m;
+- struct verbs_srq verbs_srq; /* Only used if this RQ is used a SRQ */
++ struct @SIF_GET_STRUCT@_srq @SIF_GET_STRUCT@_srq; /* Only used if this RQ is used a SRQ */
+ uint32_t index;
+ uint32_t entries;
+ uint32_t mask; /* entries - 1 for modulo using & */
+@@ -185,7 +204,7 @@
+ };
+
+ struct sif_context {
+- struct verbs_context verbs_ctx;
++ struct @SIF_GET_STRUCT@_context @SIF_GET_STRUCT@_ctx;
+ enum sif_vendor_flags default_flags;
+ enum sif_vendor_flags kernel_flags; /* Vendor flags set by the kernel */
+ enum sif_mem_type mem_type;
+@@ -198,6 +217,9 @@
+ struct sif_mr **bypass_mr_ref;
+ int bypass_cnt; /* Number of bypass MRs initiated - to avoid slow lookup unless bypass */
+ uint64_t debug_mask;
++#if defined(__SVR4) && defined(__sun)
++ uint64_t user_cb_disable;
++#endif
+ uint64_t opt_disable_mask;
+ void (* fast_copy)(void *dst, const void *src, int len);
+ };
+@@ -222,7 +244,7 @@
+ };
+
+ struct sif_qp {
+- struct verbs_qp verbs_qp;
++ struct @SIF_GET_STRUCT@_qp @SIF_GET_STRUCT@_qp;
+ uint32_t qp_idx;
+ uint32_t magic;
+ uint8_t qosl;
+@@ -245,7 +267,11 @@
+
+ struct sif_mr {
+ struct ibv_mr ibv_mr;
++#if defined(__SVR4) && defined(__sun)
++ off64_t uv2dma;
++#else
+ off_t uv2dma;
++#endif
+ enum sif_mem_type mem_type;
+ };
+
+@@ -298,12 +324,12 @@
+
+ static inline struct sif_qp *to_sqp(struct ibv_qp *ibqp)
+ {
+- return container_of(ibqp, struct sif_qp, verbs_qp.qp);
++ @SIF_GET_QP_CONTAINER@
+ }
+
+ static inline struct sif_rq *to_ssrq(struct ibv_srq *ibsrq)
+ {
+- return container_of(ibsrq, struct sif_rq, verbs_srq.srq);
++ @SIF_GET_SRQ_CONTAINER@
+ }
+
+ static inline struct sif_ah *to_sah(struct ibv_ah *ibah)
+@@ -353,6 +379,10 @@
+ struct ibv_pd *pd, void *addr, size_t length,
+ int access);
+ int sif_dereg_mr(struct ibv_mr *mr);
++struct ibv_mr *sif_reg_mr_relaxed(struct ibv_pd *pd, void *addr,
++ size_t length, int access);
++int sif_dereg_mr_relaxed(struct ibv_mr *mr);
++int sif_flush_relaxed_mr(struct ibv_pd *pd);
+ struct ibv_mw *sif_alloc_mw(struct ibv_pd *pd, enum ibv_mw_type type);
+ int sif_bind_mw(struct ibv_qp *qp, struct ibv_mw *mw, struct ibv_mw_bind *mw_bind);
+ int sif_dealloc_mw(struct ibv_mw *mw);
+@@ -366,9 +396,13 @@
+
+ struct ibv_qp *sif_create_qp(struct ibv_pd *pd,
+ struct ibv_qp_init_attr *attr);
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ struct ibv_qp *sif_create_qp_ex(struct ibv_context *context,
+ struct ibv_qp_init_attr_ex *qp_init_attr_ex);
+
++struct ibv_srq *sif_create_srq_ex(struct ibv_context *context,
++ struct ibv_srq_init_attr_ex *srq_init_attr_ex);
++#endif
+ int sif_query_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr,
+ int attr_mask, struct ibv_qp_init_attr *init_attr);
+ int sif_modify_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr,
+@@ -382,8 +416,6 @@
+
+ struct ibv_srq *sif_create_srq(struct ibv_pd *pd,
+ struct ibv_srq_init_attr *attr);
+-struct ibv_srq *sif_create_srq_ex(struct ibv_context *context,
+- struct ibv_srq_init_attr_ex *srq_init_attr_ex);
+
+ int sif_modify_srq(struct ibv_srq *srq, struct ibv_srq_attr *attr,
+ int attr_mask);
+diff -r 1584d5cbb44d src/sif_abi.h
+--- a/src/sif_abi.h Wed Feb 10 12:40:22 2016 +0530
++++ b/src/sif_abi.h Tue Mar 08 15:00:55 2016 +0530
+@@ -142,10 +142,12 @@
+ struct sif_create_srq_ext e;
+ };
+
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ struct sif_create_xsrq_cmd {
+ struct ibv_create_xsrq ibv_cmd;
+ struct sif_create_srq_ext e;
+ };
++#endif
+
+ struct sif_create_srq_resp {
+ struct ibv_create_srq_resp ibv_resp;
+diff -r 1584d5cbb44d src/sndrcv.c
+--- a/src/sndrcv.c Wed Feb 10 12:40:22 2016 +0530
++++ b/src/sndrcv.c Tue Mar 08 15:00:55 2016 +0530
+@@ -45,10 +45,15 @@
+ #include <errno.h>
+ #include <netinet/in.h>
+ #include <sys/mman.h>
+-#include <endian.h>
+-#include <string.h>
+-#if defined(__x86_64)
+-# include <immintrin.h>
++#if (defined(__SVR4) && defined(__sun))
++# include <unistd.h>
++# include <stropts.h>
++#else
++# include <endian.h>
++# include <string.h>
++# if defined(__x86_64)
++# include <immintrin.h>
++# endif
+ #endif
+ #include "sif.h"
+ #include "encoding.h"
+@@ -78,8 +83,8 @@
+ * WA for "SW might overtake SQS", bug #3595, comment 53, solution #2:
+ * Check SQS in SQ-mode before posting WQE
+ * if SQ-mode, ring SQ-doorbell
+- else post WQE to collect buffer
+- */
++ * else post WQE to collect buffer
++ */
+
+ while (wr) {
+ const int nmbr_wrs_to_bulk_process = 32;
+@@ -130,6 +135,11 @@
+ struct sif_rq *rq, struct ibv_recv_wr *wr,
+ struct ibv_recv_wr **bad_wr, bool is_srq)
+ {
++#ifdef HAVE_VERBS_REGISTER_DRIVER
++ struct ibv_qp *ibv_qp = &qp->verbs_qp.qp;
++#else
++ struct ibv_qp *ibv_qp = &qp->ibv_qp;
++#endif
+ int ret = 0;
+ u32 rq_len;
+
+@@ -154,6 +164,7 @@
+ sif_log(uc, SIF_INFO, "queue full - rq %d entries %d len %d",
+ rq->index, rq->entries, rq_len);
+ atomic_dec_return(&rq->sw->length);
++ errno = ENOMEM;
+ ret = -ENOMEM;
+ goto err_post_recv;
+ }
+@@ -161,6 +172,7 @@
+ sif_log(uc, SIF_INFO, "too many sges - rq %d sges configured %d, sges in wr %d",
+ rq->index, rq->sge_entries, wr->num_sge);
+ atomic_dec_return(&rq->sw->length);
++ errno = EINVAL;
+ ret = -EINVAL;
+ goto err_post_recv;
+ }
+@@ -177,7 +189,7 @@
+ sge[i].length = wr->sg_list[i].length;
+ sge[i].lkey = lkey;
+ sif_log(uc, SIF_RCV,
+- "sg_adr 0x%lx sg_len %d lkey %d",
++ "sg_adr 0x%"PRIx64" sg_len %d lkey %d",
+ wr->sg_list[i].addr, wr->sg_list[i].length, lkey);
+ }
+
+@@ -199,17 +211,18 @@
+
+ sif_log(uc, SIF_RCV, "Exit: success");
+ err_post_recv:
+- *bad_wr = wr;
++ if (bad_wr)
++ *bad_wr = wr;
+ pthread_mutex_unlock(&rq->lock);
+
+ #if SIF_UVERBS_ABI_VERSION > SIF_UVERBS_VERSION(3,3)
+ /* WA #622, issue RQ flush if QP in ERROR. */
+- if (!is_srq && qp->verbs_qp.qp.state == IBV_QPS_ERR) {
++ if (!is_srq && ibv_qp->state == IBV_QPS_ERR) {
+ struct ibv_qp_attr attr;
+ memset(&attr, 0, sizeof(attr));
+- if (flush_qp(&qp->verbs_qp.qp, &attr, FLUSH_RQ))
++ if (flush_qp(ibv_qp, &attr, FLUSH_RQ))
+ sif_log(uc, SIF_INFO,"failed to flush RQ, QP %d",
+- qp->verbs_qp.qp.qp_num);
++ ibv_qp->qp_num);
+ }
+ #endif
+ return ret;
+@@ -224,7 +237,11 @@
+ if (!rq->m.sz) /* no user space mappings, go via kernel */
+ return ibv_cmd_post_recv(ibqp, wr, bad_wr);
+
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ if (qp->verbs_qp.qp.state == IBV_QPS_RESET) {
++#else
++ if (qp->ibv_qp.state == IBV_QPS_RESET) {
++#endif
+ sif_log(uc, SIF_INFO, "Invalid QP state (IBV_QPS_RESET)");
+ return -EINVAL;
+ }
+@@ -276,12 +293,17 @@
+ char wr_copy[64+256] __attribute__((aligned(64)));
+ const int disa_wc2sq = uc->opt_disable_mask & SOD_WC_TO_SQ;
+
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ if (qp->verbs_qp.qp.state < IBV_QPS_RTS)
++#else
++ if (qp->ibv_qp.state < IBV_QPS_RTS)
++#endif
+ return -EINVAL; /* The qp is not ready */
+
+ if (wr->num_sge > sq->sge_entries) {
+ sif_log(uc, SIF_SND, "attempt to post wr with %d/%d sg entries",
+ wr->num_sge, sq->sge_entries);
++ errno = EINVAL;
+ return -EINVAL;
+ }
+
+@@ -290,6 +312,7 @@
+ sif_log(uc, SIF_SND,
+ "wr with more than 16 (%d/%d) sg entries not implemented yet",
+ wr->num_sge, sq->sge_entries);
++ errno = EINVAL;
+ return -EINVAL;
+ }
+
+@@ -302,6 +325,7 @@
+ sif_log(uc, SIF_INFO,
+ "queue full - head %d tail %d entries %d",
+ head, sq_seq, sq->entries);
++ errno = ENOMEM;
+ ret = -ENOMEM;
+ goto fail;
+ }
+@@ -400,8 +424,8 @@
+ wh->sq_seq = sq_seq;
+ wh->used = true;
+
+- sif_log(uc, SIF_SND, "wr_id %lx at tail 0x%x sq_seq_num %d%s",
+- wr->wr_id, sq_seq & sq->mask, wqe.wr.sq_seq, (wqe.wr.completion ? " [req.compl]" : ""));
++ sif_log(uc, SIF_SND, "wr_id %"PRIx64" at tail 0x%x sq_seq_num %d%s",
++ wr->wr_id, sq_seq & sq->mask, wqe.wr.sq_seq, (wqe.wr.completion ? " [req.compl]" : ""));
+
+ /* We can safely checksum any "hole" due to end misalignment + byte swap
+ * towards the end of the inline data
+@@ -473,7 +497,11 @@
+
+ void sif_cb_write(struct sif_context *uc, struct sif_qp *qp, const void *src, int cp_len)
+ {
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ struct sif_pd *pd = to_spd(qp->verbs_qp.qp.pd);
++#else
++ struct sif_pd *pd = to_spd(qp->ibv_qp.pd);
++#endif
+ pthread_mutex_lock(&pd->lock);
+ wmb();
+ uc->fast_copy(pd->cb.base, src, cp_len);
+@@ -589,8 +617,13 @@
+ void sif_doorbell_write(struct sif_qp *qp, struct psif_wr *wqe, bool start)
+ {
+ u16 doorbell_offset = start ? SQS_START_DOORBELL : SQS_STOP_DOORBELL;
+- struct sif_pd *pd = to_spd(qp->verbs_qp.qp.pd);
++#ifdef HAVE_VERBS_REGISTER_DRIVER
++ struct sif_pd *pd = to_spd(qp->verbs_qp.qp.pd);
+ struct sif_context *uc = to_sctx(qp->verbs_qp.qp.context);
++#else
++ struct sif_pd *pd = to_spd(qp->ibv_qp.pd);
++ struct sif_context *uc = to_sctx(qp->ibv_qp.context);
++#endif
+ sif_log(uc, SIF_QP, "%s sqs for qp %d sq_seq %d", (start ? "start" : "stop"),
+ qp->qp_idx, wqe->sq_seq);
+ pthread_mutex_lock(&pd->lock);
+@@ -608,10 +641,15 @@
+ void sif_doorbell_from_sqe(struct sif_qp *qp, u16 seq, bool start)
+ {
+ u16 doorbell_offset = start ? SQS_START_DOORBELL : SQS_STOP_DOORBELL;
+- struct sif_pd *pd = to_spd(qp->verbs_qp.qp.pd);
+ struct sif_sq *sq = &qp->sq;
+ u64 *wqe = (u64*)get_sq_entry(sq, seq);
++#ifdef HAVE_VERBS_REGISTER_DRIVER
++ struct sif_pd *pd = to_spd(qp->verbs_qp.qp.pd);
+ struct sif_context *uc = to_sctx(qp->verbs_qp.qp.context);
++#else
++ struct sif_pd *pd = to_spd(qp->ibv_qp.pd);
++ struct sif_context *uc = to_sctx(qp->ibv_qp.context);
++#endif
+
+ /* Pick the 1st 8 bytes directly from the sq entry: */
+ wmb();
+@@ -637,7 +675,11 @@
+ bool inlined, struct psif_wr_local* la, u32 sqe_seq)
+ {
+ int ret = 0;
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ struct sif_context *uc = to_sctx(qp->verbs_qp.qp.context);
++#else
++ struct sif_context *uc = to_sctx(qp->ibv_qp.context);
++#endif
+ struct psif_rq_scatter sge[16]; /* Temp.storage for buildup of LE sge list */
+
+ if (inlined)
+@@ -656,7 +698,7 @@
+ la->addr = wr->sg_list[0].addr + mr_uv2dma(uc,lkey);
+ la->lkey = lkey;
+ la->length += wr->sg_list[0].length;
+- sif_log(uc, SIF_SND, "single sge dma addr 0x%Lx, message len %d, key %d, uv2dma %Lx",
++ sif_log(uc, SIF_SND, "single sge dma addr 0x%"SIFPRIx64", message len %d, key %d, uv2dma %"SIFPRIx64"",
+ la->addr, la->length, lkey, mr_uv2dma(uc,lkey));
+ } else {
+ struct sif_sq *sq = &qp->sq;
+@@ -674,11 +716,11 @@
+ sge[i].length = wr->sg_list[i].length;
+ la->length += sge[i].length;
+ sif_log(uc, SIF_SND,
+- "sg_list[%d]: sge entry: dma addr 0x%Lx, len = %d, lkey %d",
++ "sg_list[%d]: sge entry: dma addr 0x%"SIFPRIx64", len = %d, lkey %d",
+ i, sge[i].base_addr, sge[i].length, sge[i].lkey);
+ }
+ sif_log(uc, SIF_SND,
+- "ready with sgl_start %p, sg list addr 0x%Lx, "
++ "ready with sgl_start %p, sg list addr 0x%"SIFPRIx64", "
+ "message len %d, lkey %d, sge %p",
+ sgl_start, la->addr, la->length, la->lkey, sge);
+
+@@ -697,9 +739,15 @@
+ {
+ struct sif_ah *ah = 0;
+ bool is_dr = false;
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ struct sif_context *uc = to_sctx(qp->verbs_qp.qp.context);
+
+ switch (qp->verbs_qp.qp.qp_type) {
++#else
++ struct sif_context *uc = to_sctx(qp->ibv_qp.context);
++
++ switch (qp->ibv_qp.qp_type) {
++#endif
+ case IBV_QPT_UD:
+ if (!wr->wr.ud.ah) {
+ sif_log(uc, SIF_INFO, "No ah supplied for ud packet");
+@@ -722,12 +770,19 @@
+ case IBV_QPT_RC:
+ wqe->wr.tsu_sl = qp->tsl;
+ break;
++#if !(defined(__SVR4) && defined(__sun))
+ case IBV_QPT_XRC_SEND:
+ wqe->wr.xrc_hdr.xrqd_id = wr->qp_type.xrc.remote_srqn;
+ break;
++#endif
+ default:
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ sif_log(uc, SIF_INFO,
+ "unhandled transport type %d", qp->verbs_qp.qp.qp_type);
++#else
++ sif_log(uc, SIF_INFO,
++ "unhandled transport type %d", qp->ibv_qp.qp_type);
++#endif
+ return -EINVAL;
+ }
+ wqe->wr.op = ib2sif_wr_op(wr->opcode, is_dr);
+@@ -774,7 +829,11 @@
+ int wr_len = 0;
+ struct sif_sq *sq;
+ struct psif_sq_entry *sqe;
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ struct sif_context *uc = to_sctx(qp->verbs_qp.qp.context);
++#else
++ struct sif_context *uc = to_sctx(qp->ibv_qp.context);
++#endif
+
+ /* collect buffer only supports 256 byte inlined, this first part
+ * of the inline data must be handled in host byte order to
+@@ -813,19 +872,6 @@
+ len = wr->sg_list[i].length;
+ addr = wr->sg_list[i].addr;
+
+-#if 0
+- if (len > 0) {
+- /* TBD: keys not available directly here */
+- key = safe_get_key(sdev, wr->sg_list[i].lkey);
+- if (!key || PSIF_DMA_KEY_INVALID == get_psif_key__lkey_state(key)) {
+- sif_log(uc, SIF_INFO,
+- "Attempt to do inline copying from an invalid MR "
+- "with lkey %d at addr 0x%Lx",
+- wr->sg_list[i].lkey, wr->sg_list[i].addr);
+- return -EPERM;
+- }
+- }
+-#endif
+ do_copy:
+ wr_len += len;
+ if (dbuf == buf && wr_len >= cb_len) {
+@@ -839,12 +885,13 @@
+ sif_log(uc, SIF_INFO,
+ "Inline space exhausted: available %d, copied %d, len %d",
+ space, copy, len);
++ errno = ENOMEM;
+ return -ENOMEM;
+ }
+
+- sif_log(uc, SIF_SND, "Copy sg len %d from user addr 0x%Lx to %p",
++ sif_log(uc, SIF_SND, "Copy sg len %d from user addr 0x%"SIFPRIx64" to %p",
+ len, addr, &dbuf[copy]);
+- memcpy(&dbuf[copy], (void *)addr, len);
++ memcpy(&dbuf[copy], (void *)(intptr_t)addr, len);
+ copy += len;
+ }
+
+diff -r 1584d5cbb44d src/sndrcv.h
+--- a/src/sndrcv.h Wed Feb 10 12:40:22 2016 +0530
++++ b/src/sndrcv.h Tue Mar 08 15:00:55 2016 +0530
+@@ -36,7 +36,9 @@
+
+ #ifndef _SIF_SNDRCV_H
+ #define _SIF_SNDRCV_H
++#if !(defined(__SVR4) && defined(__sun))
+ #include <kernel_types.h>
++#endif
+
+ /* ib verbs callbacks */
+ int sif_post_send(struct ibv_qp *ibqp, struct ibv_send_wr *wr, struct ibv_send_wr **bad_wr);
+diff -r 1584d5cbb44d src/uverbs.c
+--- a/src/uverbs.c Wed Feb 10 12:40:22 2016 +0530
++++ b/src/uverbs.c Tue Mar 08 15:00:55 2016 +0530
+@@ -50,8 +50,11 @@
+ #include "encoding.h"
+ #include "sif_user.h"
+ #include "sif_abi.h"
++#if !(defined(__SVR4) && defined(__sun))
+ #include "kernel_types.h"
++#endif
+ #include "psif_hw_setget.h"
++#include <unistd.h>
+
+ unsigned roundup_pwr2(unsigned x)
+ {
+@@ -74,16 +77,24 @@
+ }
+ }
+
++#if defined(__SVR4) && defined(__sun)
++uint64_t page_align(uint64_t addr)
++{
++ int mask = getpagesize() - 1;
++
++ return (addr + mask) & ~mask;
++}
++#endif
+
+ void* find_map_desc(struct sif_context *sctx, enum desc_type type, __u32 index,
+ struct sif_qp *qp)
+ {
+ int i;
+ void *base = NULL;
+-#ifdef HAVE_VERBS_REGISTER_DRIVER
++#if defined(__SVR4) && defined(__sun)
++ int fd = sctx->ibv_ctx.mmap_fd;
++#else
+ int fd = sctx->verbs_ctx.context.cmd_fd;
+-#else
+- int fd = sctx->ibv_ctx.cmd_fd;
+ #endif
+ struct sif_desc_cache* dc = &sctx->dc[type];
+ uint32_t blk_idx = index / sctx->dc[type].ba.entry_per_block;
+@@ -93,14 +104,22 @@
+ if (dc->d[i].cmd == SIF_MAP_NONE) {
+ enum sif_mmap_cmd cmd = dt_to_mmap(type);
+ /* The requested block is not mapped, try to map it: */
++#if defined(__SVR4) && defined(__sun)
++ off64_t offset = mmap_set_cmd(cmd, blk_idx);
++#else
+ off_t offset = mmap_set_cmd(cmd, blk_idx);
++#endif
+ int prot = PROT_READ;
+- if (i != SIFD_SQ_HW)
++ if (type != SIFD_SQ_HW)
+ prot |= PROT_WRITE;
++#if defined(__SVR4) && defined(__sun)
++ base = mmap64(NULL, dc->ba.block_sz, prot, MAP_SHARED, fd, offset);
++#else
+ base = mmap(NULL, dc->ba.block_sz, prot, MAP_SHARED, fd, offset);
+- if (base == MAP_FAILED) {
++#endif
++ if (base == MAP_FAILED) {
+ perror("find_map_desc");
+- fprintf(stderr, "type %d block sz %d offset 0x%lx\n", type, dc->ba.block_sz, offset);
++ fprintf(stderr, "type %d block sz %d offset 0x%"PRIx64"\n", type, dc->ba.block_sz, offset);
+ base = NULL;
+ break;
+ }
+@@ -204,10 +223,10 @@
+
+ int map_rq(struct sif_rq *rq, struct sif_context *sctx)
+ {
+-#ifdef HAVE_VERBS_REGISTER_DRIVER
++#if defined(__SVR4) && defined(__sun)
++ int fd = sctx->ibv_ctx.mmap_fd;
++#else
+ int fd = sctx->verbs_ctx.context.cmd_fd;
+-#else
+- int fd = sctx->ibv_ctx.cmd_fd;
+ #endif
+ rq->m.sz = rq->extent * rq->entries;
+
+@@ -225,8 +244,14 @@
+
+ if (rq->m.sz) {
+ /* Map the receive queue for this QP */
++#if defined(__SVR4) && defined(__sun)
++ rq->m.sz = page_align(rq->m.sz);
++ off64_t offset = mmap_set_cmd(SIF_MAP_RQ, rq->index);
++ rq->m.base = mmap64(NULL, rq->m.sz, PROT_WRITE|PROT_READ, MAP_SHARED, fd, offset);
++#else
+ off_t offset = mmap_set_cmd(SIF_MAP_RQ, rq->index);
+ rq->m.base = mmap(NULL, rq->m.sz, PROT_WRITE|PROT_READ, MAP_SHARED, fd, offset);
++#endif
+ if (rq->m.base == MAP_FAILED)
+ return errno;
+ } else {
+@@ -240,10 +265,18 @@
+
+ int sif_map_qp(struct sif_qp *qp)
+ {
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ struct ibv_context *ctx = qp->verbs_qp.qp.context;
++#else
++ struct ibv_context *ctx = qp->ibv_qp.context;
++#endif
+ struct sif_device *dev = to_sdev(ctx->device);
+ struct sif_context *sctx = to_sctx(ctx);
++#if defined(__SVR4) && defined(__sun)
++ int fd = ctx->mmap_fd;
++#else
+ int fd = ctx->cmd_fd;
++#endif
+ int ret;
+
+ qp->sq.m.sz = qp->sq.extent * qp->sq.entries;
+@@ -266,19 +299,29 @@
+ return errno;
+ }
+
+- if (qp->verbs_qp.qp.qp_type == IBV_QPT_XRC_RECV)
++#ifdef HAVE_IBV_XRC_OPS
++ if (ibv_qp->qp_type == IBV_QPT_XRC_RECV)
+ goto sq_done;
++#endif
+ if (qp->sq.m.sz) {
+ /* Map the send queue for this QP */
++#if defined(__SVR4) && defined(__sun)
++ off64_t offset = mmap_set_cmd(SIF_MAP_SQ, qp->qp_idx);
++ qp->sq.m.sz = page_align(qp->sq.m.sz);
++ qp->sq.m.base = mmap64(NULL, qp->sq.m.sz, PROT_WRITE|PROT_READ, MAP_SHARED, fd, offset);
++#else
+ off_t offset = mmap_set_cmd(SIF_MAP_SQ, qp->qp_idx);
+ qp->sq.m.base = mmap(NULL, qp->sq.m.sz, PROT_WRITE|PROT_READ, MAP_SHARED, fd, offset);
++#endif
+ if (qp->sq.m.base == MAP_FAILED)
+ return errno;
+ } else
+ fprintf(stderr, "sq sz 0\n");
+
++#ifdef HAVE_IBV_XRC_OPS
+ sq_done:
+- if (qp->rq && !qp->verbs_qp.qp.srq) {
++#endif
++ if (qp->rq && !qp->rq->m.sz) {
+ ret = map_rq(qp->rq, sctx);
+ if (ret)
+ goto rq_map_failed;
+@@ -301,7 +344,11 @@
+ if (ret)
+ return ret;
+ }
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ if (!qp->verbs_qp.qp.srq && qp->rq && qp->rq->m.sz) {
++#else
++ if (!qp->ibv_qp.srq && qp->rq && qp->rq->m.sz) {
++#endif
+ struct sif_rq *rq = qp->rq;
+ ret = munmap(rq->m.base, rq->m.sz);
+ rq->m.sz = 0;
+@@ -315,10 +362,14 @@
+ struct ibv_context *ctx = cq->ibv_cq.context;
+ struct sif_device *dev = to_sdev(ctx->device);
+ struct sif_context *sctx = to_sctx(ctx);
++#if defined(__SVR4) && defined(__sun)
++ int fd = ctx->mmap_fd;
++#else
+ int fd = ctx->cmd_fd;
+- int gross_cqe = roundup_pwr2(cq->ibv_cq.cqe);
+
+ cq->entries = cq->ibv_cq.cqe;
++#endif
++ int gross_cqe = roundup_pwr2(cq->entries);
+ cq->mask = gross_cqe - 1;
+ cq->extent = sizeof(struct psif_cq_entry);
+ cq->m.sz = gross_cqe * cq->extent;
+@@ -334,8 +385,14 @@
+ return errno;
+
+ if (cq->m.sz) {
++#if defined(__SVR4) && defined(__sun)
++ cq->m.sz = page_align(cq->m.sz);
++ off64_t offset = mmap_set_cmd(SIF_MAP_CQ, cq->index);
++ cq->m.base = mmap64(NULL, cq->m.sz, PROT_READ, MAP_SHARED, fd, offset);
++#else
+ off_t offset = mmap_set_cmd(SIF_MAP_CQ, cq->index);
+ cq->m.base = mmap(NULL, cq->m.sz, PROT_READ, MAP_SHARED, fd, offset);
++#endif
+ if (cq->m.base == MAP_FAILED)
+ return errno;
+ } else
+@@ -372,10 +429,15 @@
+ {
+ struct ibv_context *ctx = pd->ibv_pd.context;
+ struct sif_device *dev = to_sdev(ctx->device);
++#if defined(__SVR4) && defined(__sun)
++ int fd = ctx->mmap_fd;
++ off64_t offset;
++#else
+ int fd = ctx->cmd_fd;
+ off_t offset;
++#endif
+ struct sif_map *cb = &pd->cb;
+- size_t sz = 0x1000;
++ size_t sz = getpagesize();
+
+ if (dev->abi_version < abi_ver(3,0)) {
+ fprintf(stderr, "driver v.%d.%d does not support direct user level access\n",
+@@ -384,9 +446,16 @@
+ }
+
+ offset = mmap_set_cmd(SIF_MAP_CB, cb->index);
++#if defined(__SVR4) && defined(__sun)
++ cb->base = mmap64(NULL, sz, PROT_WRITE, MAP_SHARED, fd, offset);
++#else
+ cb->base = mmap(NULL, sz, PROT_WRITE, MAP_SHARED, fd, offset);
+- if (cb->base == MAP_FAILED)
++#endif
++ if (cb->base == MAP_FAILED) {
++ printf(" Cb size = %zx and offset = %lx \n", sz, offset);
++ printf("cb->base === MAP_FAILED \n");
+ return errno;
++ }
+
+ cb->sz = sz;
+ return 0;
+diff -r 1584d5cbb44d src/uverbs.h
+--- a/src/uverbs.h Wed Feb 10 12:40:22 2016 +0530
++++ b/src/uverbs.h Tue Mar 08 15:00:55 2016 +0530
+@@ -75,6 +75,10 @@
+
+ static inline bool has_srq(struct sif_qp *qp)
+ {
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ return qp->rq && qp->verbs_qp.qp.srq;
++#else
++ return qp->rq && qp->ibv_qp.srq;
++#endif
+ }
+ #endif
+diff -r 1584d5cbb44d src/verbs.c
+--- a/src/verbs.c Wed Feb 10 12:40:22 2016 +0530
++++ b/src/verbs.c Tue Mar 08 15:00:55 2016 +0530
+@@ -64,7 +64,7 @@
+ unsigned major, minor, sub_minor;
+ struct ibv_query_device cmd;
+ int ret;
+-
++
+ ret = ibv_cmd_query_device(context, attr, &raw_fw_ver, &cmd, sizeof cmd);
+ if (ret)
+ return ret;
+@@ -91,7 +91,7 @@
+ struct sif_pd *pd;
+ struct ibv_alloc_pd cmd;
+ struct sif_alloc_pd_resp resp;
+- int ret;
++ int ret = 0;
+
+ pd = malloc(sizeof *pd);
+ if (!pd)
+@@ -103,12 +103,19 @@
+ goto create_failed;
+
+ pd->cb.index = resp.e.cb_idx;
++
++#if defined(__SVR4) && defined(__sun)
++ if (resp.e.reserved == 1)
++ uc->default_flags |= SQ_mode;
++#endif
+ pthread_mutex_init(&pd->lock, NULL);
+
+ if (user_mode_verbs(context)) {
+- ret = sif_map_cb(pd);
+- if (ret)
+- goto create_failed;
++ ret = sif_map_cb(pd);
++ if (ret) {
++ printf(" sif_map_cb failed \n");
++ goto create_failed;
++ }
+ }
+
+ sif_log(uc, SIF_PD, "cb idx %d", pd->cb.index);
+@@ -129,7 +136,7 @@
+ if (user_mode_verbs(ibpd->context)) {
+ ret = sif_unmap_cb(pd);
+ if (ret) {
+- sif_log(uc, SIF_INFO, "failed to unmap cb %d (base %p sz %ld - errno %d",
++ sif_log(uc, SIF_INFO, "failed to unmap cb %d (base %p sz %"PRId64" - errno %d",
+ pd->cb.index, pd->cb.base, pd->cb.sz, errno);
+ return ret;
+ }
+@@ -159,6 +166,7 @@
+ return NULL;
+
+ memset(cq, 0, sizeof(*cq));
++ memset(&cmd, 0, sizeof (cmd));
+ cmd.e.flags = to_sctx(context)->default_flags;
+
+ /* support for proxy cqs */
+@@ -174,6 +182,9 @@
+ goto create_failed;
+
+ cq->index = resp.e.cq_idx;
++#if defined(__SVR4) && defined(__sun)
++ cq->entries = resp.e.cq_entries;
++#endif
+ pthread_mutex_init(&cq->lock, NULL);
+
+ if (user_mode_verbs(context)) {
+@@ -220,12 +231,6 @@
+ struct sif_cq *cq = to_scq(ibcq);
+ int ret;
+
+- if (user_mode_verbs(ibcq->context)) {
+- ret = sif_unmap_cq(cq);
+- if (ret)
+- return ret;
+- }
+-
+ ret = ibv_cmd_destroy_cq(ibcq);
+ if (ret) {
+ struct sif_context *uc = to_sctx(ibcq->context);
+@@ -233,6 +238,11 @@
+ cq->index, errno);
+ return ret;
+ }
++ if (user_mode_verbs(ibcq->context)) {
++ ret = sif_unmap_cq(cq);
++ if (ret)
++ return ret;
++ }
+
+ free(cq);
+ return 0;
+@@ -251,8 +261,98 @@
+ return rq;
+ }
+
++#ifndef HAVE_VERBS_REGISTER_DRIVER
++struct ibv_qp *__sif_create_qp(struct ibv_pd *ibpd,
++ struct ibv_qp_init_attr *attr)
++{
++ struct ibv_context *context = ibpd->context;
++ struct sif_context *uc = to_sctx(context);
++ struct sif_create_qp_resp resp;
++ struct sif_create_qp_cmd cmd;
++ struct sif_qp *qp;
++ struct sif_sq *sq;
++ size_t wr_hdl_sz;
++ int ret;
+
++ qp = malloc(sizeof *qp);
++ if (!qp)
++ return NULL;
+
++ memset(qp, 0, sizeof(*qp));
++ memset(&cmd, 0, sizeof(cmd));
++ cmd.e.flags = to_sctx(context)->default_flags;
++ /* support for proxy qps */
++
++ if (cmd.e.flags & proxy_mode)
++ cmd.e.proxy = to_sctx(context)->proxy;
++ ret = ibv_cmd_create_qp(ibpd, &qp->ibv_qp, attr, &cmd.ibv_cmd, sizeof cmd,
++ &resp.ibv_resp, sizeof resp);
++ if (ret) {
++ errno = ret;
++ goto create_failed;
++ }
++
++ if (attr->srq)
++ qp->rq = to_ssrq(attr->srq);
++ else {
++ struct sif_rq *rq = qp->rq = malloc(sizeof(*rq));
++ if (rq) {
++ memset(rq, 0, sizeof(*rq));
++ init_rq(rq, resp.e.rq_idx, attr->cap.max_recv_wr, resp.e.rq_extent,
++ attr->cap.max_recv_sge, to_scq(attr->recv_cq));
++ }
++ }
++ if (!qp->rq) {
++ errno = ENOMEM;
++ goto create_failed;
++ }
++
++ sq = &qp->sq;
++
++ qp->qp_idx = resp.e.qp_idx;
++ qp->magic = resp.e.magic;
++ qp->max_inline_data = attr->cap.max_inline_data;
++
++ sq->extent = resp.e.sq_extent;
++ sq->sgl_offset = resp.e.sq_sgl_offset;
++ sq->dma_handle = resp.e.sq_dma_handle;
++ sq->sg_mr_idx = resp.e.sq_mr_idx;
++ sq->entries = attr->cap.max_send_wr;
++ sq->sge_entries = attr->cap.max_send_sge;
++ sq->cq = to_scq(attr->send_cq);
++ sq->complete_all = attr->sq_sig_all ? 1 : 0;
++
++ if (cmd.e.flags & tsu_qosl)
++ qp->qosl = QOSL_LOW_LATENCY;
++ if (cmd.e.proxy != SIFPX_OFF)
++ qp->eps_tag |= EPS_TAG_FROM_HOST;
++ if (cmd.e.flags & SQ_mode)
++ qp->force_sq_mode = 1;
++ if (user_mode_verbs(context)) {
++ wr_hdl_sz = sizeof(struct sif_sq_hdl) * sq->entries;
++ sq->wr_hdl = malloc(wr_hdl_sz);
++ if (!sq->wr_hdl)
++ goto create_failed;
++ memset(sq->wr_hdl, 0, wr_hdl_sz);
++ pthread_mutex_init(&sq->lock, NULL);
++
++ ret = sif_map_qp(qp);
++ if (ret)
++ goto create_failed;
++ if (sq->sw)
++ sq->sw->last_seq = sq->sw->head_seq = 0;
++ sif_log(uc, SIF_INFO_V, "qp %d running in user mode", qp->qp_idx);
++ }
++ else
++ sif_log(uc, SIF_INFO_V, "qp %d running in kernel mode", qp->qp_idx);
++ return &qp->ibv_qp;
++
++ create_failed:
++ free(qp);
++ return NULL;
++}
++
++#else
+ struct ibv_qp *sif_create_qp_ex(struct ibv_context *context,
+ struct ibv_qp_init_attr_ex *attr)
+ {
+@@ -357,9 +457,13 @@
+ return NULL;
+ }
+
++#endif
+
+ struct ibv_qp *sif_create_qp(struct ibv_pd *ibpd, struct ibv_qp_init_attr *attr)
+ {
++#ifndef HAVE_VERBS_REGISTER_DRIVER
++ return __sif_create_qp(ibpd, attr);
++#else
+ struct ibv_qp_init_attr_ex ex_attr;
+ struct ibv_qp *qp;
+ ex_attr.qp_context = attr->qp_context;
+@@ -376,6 +480,7 @@
+ if (qp)
+ attr->cap = ex_attr.cap;
+ return qp;
++#endif
+ }
+
+
+@@ -392,9 +497,14 @@
+ enum sif_flush_type qtype)
+ {
+ struct sif_modify_qp_cmd mcmd;
++ int mask = 0;
+ memset(&mcmd, 0, sizeof(mcmd));
+ mcmd.e.flush = qtype;
+- return ibv_cmd_modify_qp(ibqp, attr, 0, &mcmd.ibv_cmd, sizeof(mcmd));
++#if defined(__SVR4) && defined(__sun)
++ mask = IBV_QP_STATE;
++ attr->qp_state = IBV_QPS_ERR;
++#endif
++ return ibv_cmd_modify_qp(ibqp, attr, mask, &mcmd.ibv_cmd, sizeof(mcmd));
+ }
+ #endif
+
+@@ -411,7 +521,11 @@
+
+ ret = ibv_cmd_modify_qp(ibqp, attr, attr_mask, &mcmd.ibv_cmd, sizeof mcmd);
+ #else
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ struct ibv_context *ctx = qp->verbs_qp.qp.context;
++#else
++ struct ibv_context *ctx = qp->ibv_qp.context;
++#endif
+ struct sif_device *dev = to_sdev(ctx->device);
+ struct ibv_modify_qp cmd;
+
+@@ -446,8 +560,6 @@
+ int ret;
+
+ sif_log(uc, SIF_INFO_V, "qp %d", qp->qp_idx);
+- if (user_mode_verbs(ibqp->context))
+- sif_unmap_qp(qp);
+
+ ret = ibv_cmd_destroy_qp(ibqp);
+ if (ret) {
+@@ -477,6 +589,7 @@
+ sif_log(uc, SIF_QP, "sif_fixup_cqes: fixed %d CQEs in rq.cq", nfixup);
+ }
+ }
++ sif_unmap_qp(qp);
+ }
+
+ if (qp->sq.wr_hdl)
+@@ -489,7 +602,50 @@
+ return 0;
+ }
+
++#ifndef HAVE_VERBS_REGISTER_DRIVER
++struct ibv_srq *__sif_create_srq(struct ibv_pd *ibpd, struct ibv_srq_init_attr *attr)
++{
++ struct sif_rq *rq;
++ struct sif_create_srq_cmd cmd;
++ struct sif_create_srq_resp resp;
++ struct sif_context *sctx = to_sctx(ibpd->context);
++ int ret;
+
++ rq = malloc(sizeof(*rq));
++ if (!rq)
++ return NULL;
++ memset(rq, 0, sizeof(*rq));
++ memset(&cmd, 0, sizeof(cmd));
++ cmd.e.flags = sif_get_default_flags(ibpd->context);
++ cmd.e.res1 = 0;
++
++ ret = ibv_cmd_create_srq(ibpd, &rq->ibv_srq,
++ attr, &cmd.ibv_cmd, sizeof(cmd),
++ &resp.ibv_resp, sizeof(resp));
++ if (ret) {
++ sif_log(sctx, SIF_INFO, "%s: failed to create qp, ret %d\n", __func__, ret);
++ free(rq);
++ return NULL;
++ }
++
++ pthread_mutex_init(&rq->lock, NULL);
++ rq->index = resp.e.index;
++ rq->extent = resp.e.extent;
++ rq->entries = attr->attr.max_wr;
++ rq->sge_entries = attr->attr.max_sge;
++ sif_log(sctx, SIF_SRQ, "created srq %d with extent %d, entries %d, sge_entries %d",
++ rq->index, rq->extent, rq->entries, rq->sge_entries);
++
++ if (user_mode_verbs(ibpd->context)) {
++ ret = map_rq(rq, sctx);
++ if (ret) {
++ free(rq);
++ return NULL;
++ }
++ }
++ return &rq->ibv_srq;
++}
++#else
+ struct ibv_srq *sif_create_srq_ex(struct ibv_context *context,
+ struct ibv_srq_init_attr_ex *attr)
+ {
+@@ -540,9 +696,13 @@
+ return &rq->verbs_srq.srq;
+ }
+
++#endif
+
+ struct ibv_srq *sif_create_srq(struct ibv_pd *ibpd, struct ibv_srq_init_attr *attr)
+ {
++#ifndef HAVE_VERBS_REGISTER_DRIVER
++ return __sif_create_srq(ibpd, attr);
++#else
+ struct ibv_srq_init_attr_ex attr_ex;
+ struct ibv_srq *srq;
+ attr_ex.srq_context = attr->srq_context;
+@@ -554,6 +714,7 @@
+ if (srq)
+ attr->attr = attr_ex.attr;
+ return srq;
++#endif
+ }
+
+
+@@ -577,11 +738,6 @@
+ int ret;
+ sif_log(sctx, SIF_SRQ, "rq %d", rq->index);
+
+- if (rq->m.sz) {
+- ret = munmap(rq->m.base, rq->m.sz);
+- rq->m.sz = 0;
+- }
+-
+ ret = ibv_cmd_destroy_srq(ibsrq);
+ if (ret) {
+ sif_log(sctx, SIF_INFO, "ibv_cmd_destroy_srq %d failed with errno %d",
+@@ -589,6 +745,11 @@
+ return ret;
+ }
+
++ if (rq->m.sz) {
++ ret = munmap(rq->m.base, rq->m.sz);
++ rq->m.sz = 0;
++ }
++
+ free(rq);
+ return 0;
+ }
+diff -r 1584d5cbb44d src/xrc.c
+--- a/src/xrc.c Wed Feb 10 12:40:22 2016 +0530
++++ b/src/xrc.c Tue Mar 08 15:00:55 2016 +0530
+@@ -44,6 +44,7 @@
+ #include "xrc.h"
+ #include "encoding.h"
+
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ struct ibv_xrcd *sif_open_xrcd(struct ibv_context *context,
+ struct ibv_xrcd_init_attr *attr)
+ {
+@@ -88,3 +89,4 @@
+ sif_log(sctx, SIF_INFO, "*** Not implemented **");
+ return NULL;
+ }
++#endif
+diff -r 1584d5cbb44d src/xrc.h
+--- a/src/xrc.h Wed Feb 10 12:40:22 2016 +0530
++++ b/src/xrc.h Tue Mar 08 15:00:55 2016 +0530
+@@ -34,12 +34,16 @@
+ * xrc.h: XRC support device specific calls.
+ */
+
++#if HAVE_CONFIG_H
++#include <config.h>
++#endif /* HAVE_CONFIG_H */
+ #ifndef _SIF_XRC_H
+ #define _SIF_XRC_H
+ #include <infiniband/driver.h>
+ #include <infiniband/arch.h>
+ #include <infiniband/verbs.h>
+
++#ifdef HAVE_VERBS_REGISTER_DRIVER
+ struct ibv_xrcd *sif_open_xrcd(struct ibv_context *context,
+ struct ibv_xrcd_init_attr *xrcd_init_attr);
+ int sif_close_xrcd(struct ibv_xrcd *xrcd);
+@@ -47,3 +51,4 @@
+ struct ibv_qp_open_attr *attr);
+
+ #endif
++#endif
--- a/components/open-fabrics/open-fabrics.p5m Tue Mar 08 15:34:08 2016 -0800
+++ b/components/open-fabrics/open-fabrics.p5m Tue Mar 08 21:43:23 2016 -0800
@@ -31,6 +31,7 @@
set name=info.classification \
value="org.opensolaris.category.2008:System/Administration and Configuration"
set name=info.source-url \
+ value=http://download.oracle.com/otn-pub/oss/networking/libsif-1.0.tar.gz \
value=http://www.openfabrics.org/downloads/ibutils/ibutils-1.5.7.tar.gz \
value=http://www.openfabrics.org/downloads/libibverbs/libibverbs-1.1.4-1.22.g7257cd3.tar.gz \
value=http://www.openfabrics.org/downloads/libmlx4/libmlx4-1.0.1-1.18.gb810a27.tar.gz \
@@ -172,6 +173,8 @@
link path=usr/lib/$(MACH64)/librdmacm.so target=librdmacm.so.1.0.0
link path=usr/lib/$(MACH64)/librdmacm.so.1 target=librdmacm.so.1.0.0
file path=usr/lib/$(MACH64)/librdmacm.so.1.0.0
+file path=usr/lib/$(MACH64)/libsif-rdmav2.so variant.arch=sparc
+link path=usr/lib/$(MACH64)/libsif.so target=libsif-rdmav2.so variant.arch=sparc
dir path=usr/lib/secure
dir path=usr/lib/secure/$(MACH64)
link path=usr/lib/secure/$(MACH64)/libsdp.so target=libsdp.so.1.0.0
@@ -235,6 +238,7 @@
file path=usr/sbin/solaris_set_nodedesc variant.opensolaris.zone=global
dir path=usr/share/libibverbs.d
file path=usr/share/libibverbs.d/mlx4.driver
+file path=usr/share/libibverbs.d/sif.driver variant.arch=sparc
dir path=usr/share/man
dir path=usr/share/man/man1
file path=usr/share/man/man1/ib_clock_test.1
@@ -396,6 +400,9 @@
legacy pkg=SUNWofusr \
desc="Oracle Solaris OpenFabrics userland libraries and applications" \
name="Oracle Solaris OpenFabrics userland libraries and applications"
+license libsif/libsif.license license=BSD3 \
+ com.oracle.info.description="The OpenFabrics Verbs support for Oracle SIF Driver" \
+ com.oracle.info.name=libsif com.oracle.info.version=1.0
license open-fabrics.license license=open-fabrics \
com.oracle.info.description="the OpenFabrics Enterprise Distribution" \
com.oracle.info.name=open-fabrics \