--- a/exception_lists/cstyle Sat Jun 30 11:33:30 2012 +0100
+++ b/exception_lists/cstyle Sun Aug 12 11:56:48 2012 +0100
@@ -656,15 +656,21 @@
usr/src/uts/common/gssapi/mechs/krb5/mech/verify.c
usr/src/uts/common/gssapi/mechs/krb5/mech/wrap_size_limit.c
usr/src/uts/common/io/ixgbe/ixgbe_82598.c
+usr/src/uts/common/io/ixgbe/ixgbe_82598.h
usr/src/uts/common/io/ixgbe/ixgbe_82599.c
+usr/src/uts/common/io/ixgbe/ixgbe_82599.h
usr/src/uts/common/io/ixgbe/ixgbe_api.c
usr/src/uts/common/io/ixgbe/ixgbe_api.h
usr/src/uts/common/io/ixgbe/ixgbe_common.c
usr/src/uts/common/io/ixgbe/ixgbe_common.h
+usr/src/uts/common/io/ixgbe/ixgbe_mbx.c
+usr/src/uts/common/io/ixgbe/ixgbe_mbx.h
usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
usr/src/uts/common/io/ixgbe/ixgbe_phy.c
usr/src/uts/common/io/ixgbe/ixgbe_phy.h
usr/src/uts/common/io/ixgbe/ixgbe_type.h
+usr/src/uts/common/io/ixgbe/ixgbe_x540.c
+usr/src/uts/common/io/ixgbe/ixgbe_x540.h
usr/src/uts/intel/io/acpica/debugger/dbcmds.c
usr/src/uts/intel/io/acpica/debugger/dbdisply.c
usr/src/uts/intel/io/acpica/debugger/dbexec.c
--- a/usr/src/Targetdirs Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/Targetdirs Sun Aug 12 11:56:48 2012 +0100
@@ -22,6 +22,7 @@
# Copyright (c) 1989, 2010, Oracle and/or its affiliates. All rights reserved.
# Copyright 2011, Richard Lowe
# Copyright 2011 Nexenta Systems, Inc. All rights reserved.
+# Copyright (c) 2012 by Delphix. All rights reserved.
#
#
@@ -1031,6 +1032,8 @@
$(ROOT)/usr/lib/libxnet.so:= REALPATH=../../lib/libxnet.so.1
$(ROOT)/usr/lib/libzfs.so.1:= REALPATH=../../lib/libzfs.so.1
$(ROOT)/usr/lib/libzfs.so:= REALPATH=../../lib/libzfs.so.1
+$(ROOT)/usr/lib/libzfs_core.so.1:= REALPATH=../../lib/libzfs_core.so.1
+$(ROOT)/usr/lib/libzfs_core.so:= REALPATH=../../lib/libzfs_core.so.1
$(ROOT)/usr/lib/llib-ladm.ln:= REALPATH=../../lib/llib-ladm.ln
$(ROOT)/usr/lib/llib-ladm:= REALPATH=../../lib/llib-ladm
$(ROOT)/usr/lib/llib-laio.ln:= REALPATH=../../lib/llib-laio.ln
@@ -1131,6 +1134,8 @@
$(ROOT)/usr/lib/llib-lxnet:= REALPATH=../../lib/llib-lxnet
$(ROOT)/usr/lib/llib-lzfs.ln:= REALPATH=../../lib/llib-lzfs.ln
$(ROOT)/usr/lib/llib-lzfs:= REALPATH=../../lib/llib-lzfs
+$(ROOT)/usr/lib/llib-lzfs_core.ln:= REALPATH=../../lib/llib-lzfs_core.ln
+$(ROOT)/usr/lib/llib-lzfs_core:= REALPATH=../../lib/llib-lzfs_core
$(ROOT)/usr/lib/nss_compat.so.1:= REALPATH=../../lib/nss_compat.so.1
$(ROOT)/usr/lib/nss_dns.so.1:= REALPATH=../../lib/nss_dns.so.1
$(ROOT)/usr/lib/nss_files.so.1:= REALPATH=../../lib/nss_files.so.1
@@ -1377,6 +1382,10 @@
REALPATH=../../../lib/$(MACH64)/libzfs.so.1
$(ROOT)/usr/lib/$(MACH64)/libzfs.so.1:= \
REALPATH=../../../lib/$(MACH64)/libzfs.so.1
+$(ROOT)/usr/lib/$(MACH64)/libzfs_core.so:= \
+ REALPATH=../../../lib/$(MACH64)/libzfs_core.so.1
+$(ROOT)/usr/lib/$(MACH64)/libzfs_core.so.1:= \
+ REALPATH=../../../lib/$(MACH64)/libzfs_core.so.1
$(ROOT)/usr/lib/$(MACH64)/libfdisk.so.1:= \
REALPATH=../../../lib/$(MACH64)/libfdisk.so.1
$(ROOT)/usr/lib/$(MACH64)/libfdisk.so:= \
@@ -1473,6 +1482,8 @@
REALPATH=../../../lib/$(MACH64)/llib-lxnet.ln
$(ROOT)/usr/lib/$(MACH64)/llib-lzfs.ln:= \
REALPATH=../../../lib/$(MACH64)/llib-lzfs.ln
+$(ROOT)/usr/lib/$(MACH64)/llib-lzfs_core.ln:= \
+ REALPATH=../../../lib/$(MACH64)/llib-lzfs_core.ln
$(ROOT)/usr/lib/$(MACH64)/llib-lfdisk.ln:= \
REALPATH=../../../lib/$(MACH64)/llib-lfdisk.ln
$(ROOT)/usr/lib/$(MACH64)/nss_compat.so.1:= \
@@ -1627,6 +1638,8 @@
/usr/lib/libxnet.so.1 \
/usr/lib/libzfs.so \
/usr/lib/libzfs.so.1 \
+ /usr/lib/libzfs_core.so \
+ /usr/lib/libzfs_core.so.1 \
/usr/lib/llib-ladm \
/usr/lib/llib-ladm.ln \
/usr/lib/llib-laio \
@@ -1725,6 +1738,8 @@
/usr/lib/llib-lxnet.ln \
/usr/lib/llib-lzfs \
/usr/lib/llib-lzfs.ln \
+ /usr/lib/llib-lzfs_core \
+ /usr/lib/llib-lzfs_core.ln \
/usr/lib/nss_compat.so.1 \
/usr/lib/nss_dns.so.1 \
/usr/lib/nss_files.so.1 \
@@ -1863,6 +1878,8 @@
/usr/lib/$(MACH64)/libxnet.so.1 \
/usr/lib/$(MACH64)/libzfs.so \
/usr/lib/$(MACH64)/libzfs.so.1 \
+ /usr/lib/$(MACH64)/libzfs_core.so \
+ /usr/lib/$(MACH64)/libzfs_core.so.1 \
/usr/lib/$(MACH64)/llib-ladm.ln \
/usr/lib/$(MACH64)/llib-laio.ln \
/usr/lib/$(MACH64)/llib-lavl.ln \
@@ -1909,6 +1926,7 @@
/usr/lib/$(MACH64)/llib-luuid.ln \
/usr/lib/$(MACH64)/llib-lxnet.ln \
/usr/lib/$(MACH64)/llib-lzfs.ln \
+ /usr/lib/$(MACH64)/llib-lzfs_core.ln \
/usr/lib/$(MACH64)/nss_compat.so.1 \
/usr/lib/$(MACH64)/nss_dns.so.1 \
/usr/lib/$(MACH64)/nss_files.so.1 \
--- a/usr/src/cmd/beadm/beadm.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/beadm/beadm.c Sun Aug 12 11:56:48 2012 +0100
@@ -123,21 +123,21 @@
"\n"
"\tsubcommands:\n"
"\n"
- "\tbeadm activate beName\n"
- "\tbeadm create [-d BE_desc]\n"
+ "\tbeadm activate [-v] beName\n"
+ "\tbeadm create [-a] [-d BE_desc]\n"
"\t\t[-o property=value] ... [-p zpool] \n"
- "\t\t[-e nonActiveBe | beName@snapshot] beName\n"
+ "\t\t[-e nonActiveBe | beName@snapshot] [-v] beName\n"
"\tbeadm create [-d BE_desc]\n"
- "\t\t[-o property=value] ... [-p zpool] beName@snapshot\n"
- "\tbeadm destroy [-Ffs] beName \n"
- "\tbeadm destroy [-F] beName@snapshot \n"
- "\tbeadm list [[-a] | [-d] [-s]] [-H] [beName]\n"
- "\tbeadm mount [-s ro|rw] beName [mountpoint]\n"
- "\tbeadm unmount [-f] beName | mountpoint\n"
- "\tbeadm umount [-f] beName | mountpoint\n"
- "\tbeadm rename origBeName newBeName\n"
- "\tbeadm rollback beName snapshot\n"
- "\tbeadm rollback beName@snapshot\n"));
+ "\t\t[-o property=value] ... [-p zpool] [-v] beName@snapshot\n"
+ "\tbeadm destroy [-Ffsv] beName \n"
+ "\tbeadm destroy [-Fv] beName@snapshot \n"
+ "\tbeadm list [[-a] | [-d] [-s]] [-H] [-v] [beName]\n"
+ "\tbeadm mount [-s ro|rw] [-v] beName [mountpoint]\n"
+ "\tbeadm unmount [-fv] beName | mountpoint\n"
+ "\tbeadm umount [-fv] beName | mountpoint\n"
+ "\tbeadm rename [-v] origBeName newBeName\n"
+ "\tbeadm rollback [-v] beName snapshot\n"
+ "\tbeadm rollback [-v] beName@snapshot\n"));
}
static int
@@ -664,8 +664,20 @@
{
nvlist_t *be_attrs;
int err = 1;
+ int c;
char *obe_name;
+ while ((c = getopt(argc, argv, "v")) != -1) {
+ switch (c) {
+ case 'v':
+ libbe_print_errors(B_TRUE);
+ break;
+ default:
+ usage();
+ return (1);
+ }
+ }
+
argc -= optind;
argv += optind;
@@ -728,7 +740,7 @@
char *propval = NULL;
char *strval = NULL;
- while ((c = getopt(argc, argv, "ad:e:io:p:")) != -1) {
+ while ((c = getopt(argc, argv, "ad:e:io:p:v")) != -1) {
switch (c) {
case 'a':
activate = B_TRUE;
@@ -766,6 +778,9 @@
case 'p':
nbe_zpool = optarg;
break;
+ case 'v':
+ libbe_print_errors(B_TRUE);
+ break;
default:
usage();
goto out2;
@@ -939,7 +954,7 @@
char *snap_name;
char *be_name;
- while ((c = getopt(argc, argv, "fFs")) != -1) {
+ while ((c = getopt(argc, argv, "fFsv")) != -1) {
switch (c) {
case 'f':
destroy_flags |= BE_DESTROY_FLAG_FORCE_UNMOUNT;
@@ -947,6 +962,9 @@
case 's':
destroy_flags |= BE_DESTROY_FLAG_SNAPSHOTS;
break;
+ case 'v':
+ libbe_print_errors(B_TRUE);
+ break;
case 'F':
suppress_prompt = B_TRUE;
break;
@@ -1061,7 +1079,7 @@
int c = 0;
char *be_name = NULL;
- while ((c = getopt(argc, argv, "nadsH")) != -1) {
+ while ((c = getopt(argc, argv, "adsvH")) != -1) {
switch (c) {
case 'a':
all = B_TRUE;
@@ -1072,6 +1090,9 @@
case 's':
snaps = B_TRUE;
break;
+ case 'v':
+ libbe_print_errors(B_TRUE);
+ break;
case 'H':
parsable = B_TRUE;
break;
@@ -1145,7 +1166,7 @@
char *mountpoint;
char *tmp_mp = NULL;
- while ((c = getopt(argc, argv, "s:")) != -1) {
+ while ((c = getopt(argc, argv, "s:v")) != -1) {
switch (c) {
case 's':
shared_fs = B_TRUE;
@@ -1162,6 +1183,9 @@
}
break;
+ case 'v':
+ libbe_print_errors(B_TRUE);
+ break;
default:
usage();
return (1);
@@ -1223,7 +1247,6 @@
(void) printf(_("Mounted successfully on: '%s'\n"), mountpoint);
break;
case BE_ERR_BE_NOENT:
- err = 1;
(void) fprintf(stderr, _("%s does not exist or appear "
"to be a valid BE.\nPlease check that the name of "
"the BE provided is correct.\n"), obe_name);
@@ -1235,13 +1258,11 @@
break;
case BE_ERR_PERM:
case BE_ERR_ACCESS:
- err = 1;
(void) fprintf(stderr, _("Unable to mount %s.\n"), obe_name);
(void) fprintf(stderr, _("You have insufficient privileges to "
"execute this command.\n"));
break;
default:
- err = 1;
(void) fprintf(stderr, _("Unable to mount %s.\n"), obe_name);
(void) fprintf(stderr, "%s\n", be_err_to_str(err));
}
@@ -1262,11 +1283,14 @@
int c;
int unmount_flags = 0;
- while ((c = getopt(argc, argv, "f")) != -1) {
+ while ((c = getopt(argc, argv, "fv")) != -1) {
switch (c) {
case 'f':
unmount_flags |= BE_UNMOUNT_FLAG_FORCE;
break;
+ case 'v':
+ libbe_print_errors(B_TRUE);
+ break;
default:
usage();
return (1);
@@ -1337,6 +1361,18 @@
char *obe_name;
char *nbe_name;
int err = 1;
+ int c;
+
+ while ((c = getopt(argc, argv, "v")) != -1) {
+ switch (c) {
+ case 'v':
+ libbe_print_errors(B_TRUE);
+ break;
+ default:
+ usage();
+ return (1);
+ }
+ }
argc -= optind;
argv += optind;
@@ -1394,6 +1430,18 @@
char *obe_name;
char *snap_name;
int err = 1;
+ int c;
+
+ while ((c = getopt(argc, argv, "v")) != -1) {
+ switch (c) {
+ case 'v':
+ libbe_print_errors(B_TRUE);
+ break;
+ default:
+ usage();
+ return (1);
+ }
+ }
argc -= optind;
argv += optind;
--- a/usr/src/cmd/cmd-inet/usr.sbin/ifconfig/ifconfig.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/cmd-inet/usr.sbin/ifconfig/ifconfig.c Sun Aug 12 11:56:48 2012 +0100
@@ -1,3 +1,6 @@
+/*
+ * Copyright 2012, Daniil Lunev. All rights reserved.
+ */
/*
* Copyright (c) 1990, 2010, Oracle and/or its affiliates. All rights reserved.
*/
@@ -380,15 +383,16 @@
lifc_flags = LIFC_DEFAULT;
if (argc < 2) {
- usage();
- exit(1);
+ (void) strncpy(name, "-a", sizeof (name));
+ } else {
+ argc--, argv++;
+ if (strlen(*argv) > sizeof (name) - 1) {
+ (void) fprintf(stderr, "%s: interface name too long\n",
+ *argv);
+ exit(1);
+ }
+ (void) strncpy(name, *argv, sizeof (name));
}
- argc--, argv++;
- if (strlen(*argv) > sizeof (name) - 1) {
- (void) fprintf(stderr, "%s: interface name too long\n", *argv);
- exit(1);
- }
- (void) strncpy(name, *argv, sizeof (name));
name[sizeof (name) - 1] = '\0';
(void) strncpy(origname, name, sizeof (origname)); /* For addif */
default_ip_str = NULL;
@@ -452,7 +456,7 @@
int c;
char *av[2] = { "ifconfig", name };
- while ((c = getopt(2, av, "audDXZ46v")) != -1) {
+ while ((c = getopt(2, av, "audhDXZ46v")) != -1) {
switch ((char)c) {
case 'a':
all = 1;
@@ -491,6 +495,7 @@
case 'v':
verbose = 1;
break;
+ case 'h':
case '?':
usage();
exit(1);
--- a/usr/src/cmd/cmd-inet/usr.sbin/ipadm/ipadm.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/cmd-inet/usr.sbin/ipadm/ipadm.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
#include <arpa/inet.h>
#include <errno.h>
@@ -85,13 +86,11 @@
/* address management related sub-commands */
{ "create-addr", do_create_addr,
- "\tcreate-addr\t[-t] {-T static <static_args> |"
- " -T dhcp <dhcp_args> |\n"
- "\t\t\t-T addrconf <addrconf_args>} <addrobj>\n"
- "\t\t\tstatic_args = <[-d] -a {local|remote}=addr[/prefixlen]>\n"
- "\t\t\tdhcp_args = <[-w <seconds> | forever]>\n"
- "\t\t\taddrconf_args = <[-i interface-id]\n"
- "\t\t\t\t\t[-p {stateful|stateless}={yes|no}]>" },
+ "\tcreate-addr\t[-t] -T static [-d] "
+ "-a{local|remote}=addr[/prefixlen]\n\t\t\t<addrobj>\n"
+ "\tcreate-addr\t[-t] -T dhcp [-w <seconds> | forever] <addrobj>\n"
+ "\tcreate-addr\t[-t] -T addrconf [-i interface-id]\n"
+ "\t\t\t[-p {stateful|stateless}={yes|no}] <addrobj>" },
{ "down-addr", do_down_addr, "\tdown-addr\t[-t] <addrobj>" },
{ "up-addr", do_up_addr, "\tup-addr\t\t[-t] <addrobj>" },
{ "disable-addr", do_disable_addr, "\tdisable-addr\t-t <addrobj>" },
@@ -1194,6 +1193,8 @@
case P_STATELESS:
if (stateless_arg)
die("Duplicate option");
+ if (val == NULL)
+ die("Invalid argument");
if (strcmp(val, "yes") == 0)
stateless = _B_TRUE;
else if (strcmp(val, "no") == 0)
@@ -1205,6 +1206,8 @@
case P_STATEFUL:
if (stateful_arg)
die("Duplicate option");
+ if (val == NULL)
+ die("Invalid argument");
if (strcmp(val, "yes") == 0)
stateful = _B_TRUE;
else if (strcmp(val, "no") == 0)
--- a/usr/src/cmd/cpio/cpio.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/cpio/cpio.c Sun Aug 12 11:56:48 2012 +0100
@@ -21,6 +21,7 @@
/*
* Copyright (c) 1988, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright 2012 Milan Jurik. All rights reserved.
+ * Copyright (c) 2012 Gary Mills
*/
/* Copyright (c) 1983, 1984, 1985, 1986, 1987, 1988, 1989 AT&T */
@@ -825,8 +826,11 @@
if (close(Archive) != 0)
msg(EXTN, "close error");
}
- Blocks = (u_longlong_t)(Blocks * Bufsize + SBlocks + 0x1FF) >> 9;
- msg(EPOST, "%lld blocks", Blocks);
+ if ((Args & OCq) == 0) {
+ Blocks = (u_longlong_t)(Blocks * Bufsize + SBlocks +
+ 0x1FF) >> 9;
+ msg(EPOST, "%lld blocks", Blocks);
+ }
if (Error_cnt)
msg(EPOST, "%d error(s)", Error_cnt);
return (EXIT_CODE);
@@ -6379,24 +6383,24 @@
#if defined(O_XATTR)
#if defined(_PC_SATTR_ENABLED)
#ifdef WAITAROUND
- char *opts_p = "zabcdfiklmoprstuvABC:DE:H:I:LM:O:PR:SV6@/";
+ char *opts_p = "zabcdfiklmopqrstuvABC:DE:H:I:LM:O:PR:SV6@/";
#else
- char *opts_p = "abcdfiklmoprstuvABC:DE:H:I:LM:O:PR:SV6@/";
+ char *opts_p = "abcdfiklmopqrstuvABC:DE:H:I:LM:O:PR:SV6@/";
#endif /* WAITAROUND */
#else /* _PC_SATTR_ENABLED */
#ifdef WAITAROUND
- char *opts_p = "zabcdfiklmoprstuvABC:DE:H:I:LM:O:PR:SV6@";
+ char *opts_p = "zabcdfiklmopqrstuvABC:DE:H:I:LM:O:PR:SV6@";
#else
- char *opts_p = "abcdfiklmoprstuvABC:DE:H:I:LM:O:PR:SV6@";
+ char *opts_p = "abcdfiklmopqrstuvABC:DE:H:I:LM:O:PR:SV6@";
#endif /* WAITAROUND */
#endif /* _PC_SATTR_ENABLED */
#else /* O_XATTR */
#ifdef WAITAROUND
- char *opts_p = "zabcdfiklmoprstuvABC:DE:H:I:LM:O:PR:SV6";
+ char *opts_p = "zabcdfiklmopqrstuvABC:DE:H:I:LM:O:PR:SV6";
#else
- char *opts_p = "abcdfiklmoprstuvABC:DE:H:I:LM:O:PR:SV6";
+ char *opts_p = "abcdfiklmopqrstuvABC:DE:H:I:LM:O:PR:SV6";
#endif /* WAITAROUND */
#endif /* O_XATTR */
@@ -6468,6 +6472,9 @@
Max_namesz = APATH;
Args |= OCp;
break;
+ case 'q': /* "quiet" */
+ Args |= OCq;
+ break;
case 'r': /* rename files interactively */
Args |= OCr;
break;
@@ -6867,7 +6874,7 @@
(void) fflush(stdout);
#if defined(O_XATTR)
(void) fprintf(stderr, gettext("USAGE:\n"
- "\tcpio -i[bcdfkmrstuv@BSV6] [-C size] "
+ "\tcpio -i[bcdfkmqrstuv@BSV6] [-C size] "
"[-E file] [-H hdr] [-I file [-M msg]] "
"[-R id] [patterns]\n"
"\tcpio -o[acv@ABLV] [-C size] "
@@ -6875,7 +6882,7 @@
"\tcpio -p[adlmuv@LV] [-R id] directory\n"));
#else
(void) fprintf(stderr, gettext("USAGE:\n"
- "\tcpio -i[bcdfkmrstuvBSV6] [-C size] "
+ "\tcpio -i[bcdfkmqrstuvBSV6] [-C size] "
"[-E file] [-H hdr] [-I file [-M msg]] "
"[-R id] [patterns]\n"
"\tcpio -o[acvABLV] [-C size] "
--- a/usr/src/cmd/cpio/cpio.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/cpio/cpio.h Sun Aug 12 11:56:48 2012 +0100
@@ -19,6 +19,8 @@
* CDDL HEADER END
*/
/*
+ * Copyright (c) 2012 Gary Mills
+ *
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
@@ -69,6 +71,7 @@
#define OC6 0x10000000
#define BSM 0x20000000
#define OCP 0x40000000
+#define OCq 0x80000000
/* Sparse file support */
#define C_ISSPARSE 0200000
--- a/usr/src/cmd/dtrace/dtrace.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/dtrace/dtrace.c Sun Aug 12 11:56:48 2012 +0100
@@ -23,8 +23,9 @@
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
-
-#pragma ident "%Z%%M% %I% %E% SMI"
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
#include <sys/types.h>
#include <sys/stat.h>
@@ -1339,6 +1340,7 @@
(void) dtrace_setopt(g_dtp, "bufsize", "4m");
(void) dtrace_setopt(g_dtp, "aggsize", "4m");
+ (void) dtrace_setopt(g_dtp, "temporal", "yes");
/*
* If -G is specified, enable -xlink=dynamic and -xunodefs to permit
--- a/usr/src/cmd/dtrace/test/cmd/scripts/dtest.pl Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/dtrace/test/cmd/scripts/dtest.pl Sun Aug 12 11:56:48 2012 +0100
@@ -27,6 +27,7 @@
#
# Copyright (c) 2011, Joyent, Inc. All rights reserved.
+# Copyright (c) 2012 by Delphix. All rights reserved.
#
require 5.8.4;
@@ -612,6 +613,8 @@
die "$PNAME: failed to open $PNAME.$$.log: $!\n"
unless (!$opt_l || open(LOG, ">$PNAME.$$.log"));
+$ENV{'DTRACE_DEBUG_REGSET'} = 'true';
+
if ($opt_g) {
$ENV{'UMEM_DEBUG'} = 'default,verbose';
$ENV{'UMEM_LOGGING'} = 'fail,contents';
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/aggs/tst.sizedkeys.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,35 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+#pragma D option quiet
+
+/*
+ * Make sure the sizes of compatible keys doesn't affect the sort order.
+ */
+
+BEGIN
+{
+ @[(int)1, 0] = sum(10);
+ @[(uint64_t)2, 0] = sum(20);
+ @[(int)3, 0] = sum(30);
+ @[(uint64_t)4, 0] = sum(40);
+ printa(@);
+
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/aggs/tst.sizedkeys.d.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,6 @@
+
+ 1 0 10
+ 2 0 20
+ 3 0 30
+ 4 0 40
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/arithmetic/tst.basics.d.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,8 @@
+The value of i is 6
+The value of i is 18
+The value of i is 72
+The value of i is 25920
+The value of i is 935761216
+The value of i is -91738734
+The value of i is -91738729
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/arithmetic/tst.compcast.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,50 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+/*
+ * Test compile-time casting between integer types of different size.
+ */
+
+#pragma D option quiet
+
+int64_t x;
+
+BEGIN
+{
+ x = (int32_t)(int16_t)0xfff0;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (int32_t)(uint16_t)0xfff0;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (uint32_t)(int16_t)0xfff0;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (uint32_t)(uint16_t)0xfff0;
+ printf("%16x %20d %20u\n", x, x, x);
+ printf("\n");
+
+ x = (int16_t)(int32_t)0xfff0;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (int16_t)(uint32_t)0xfff0;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (uint16_t)(int32_t)0xfff0;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (uint16_t)(uint32_t)0xfff0;
+ printf("%16x %20d %20u\n", x, x, x);
+
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/arithmetic/tst.compcast.d.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,10 @@
+fffffffffffffff0 -16 18446744073709551600
+ fff0 65520 65520
+ fffffff0 4294967280 4294967280
+ fff0 65520 65520
+
+fffffffffffffff0 -16 18446744073709551600
+fffffffffffffff0 -16 18446744073709551600
+ fff0 65520 65520
+ fff0 65520 65520
+
--- a/usr/src/cmd/dtrace/test/tst/common/arithmetic/tst.complex.d Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
- * Use is subject to license terms.
- */
-
-#pragma ident "%Z%%M% %I% %E% SMI"
-
-/*
- * ASSERTION:
- * Complex expressions.
- * Call complex expressions and make sure test succeeds.
- * Match expected output in tst.complex.d.out
- *
- * SECTION: Types, Operators, and Expressions/Arithmetic Operators
- *
- */
-
-#pragma D option quiet
-
-BEGIN
-{
- i = 0;
- i = i++ + ++i;
- printf("The value of i is %d\n", i);
- i = i-- - --i;
- printf("The value of i is %d\n", i);
- i = i-- + ++i;
- printf("The value of i is %d\n", i);
- i += i++ + -- i + ++i - ++i * i ;
- printf("The value of i is %d\n", i);
- i -= i++ * 3;
- printf("The value of i is %d\n", i);
- i = i++/i--+i++-++i-++i;
- printf("The value of i is %d\n", i);
- exit (0);
-}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/arithmetic/tst.compnarrowassign.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,36 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+/*
+ * Test narrowing at assignment.
+ */
+
+#pragma D option quiet
+
+uint16_t x;
+uint32_t y;
+
+BEGIN
+{
+ x = 0xbeefcafe;
+ y = x;
+ printf("%x", y); /* where's the beef? */
+
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/arithmetic/tst.compnarrowassign.d.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,1 @@
+cafe
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/arithmetic/tst.execcast.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,52 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+/*
+ * Test execution-time casting between integer types of different size.
+ */
+
+#pragma D option quiet
+
+int64_t x;
+
+BEGIN
+{
+ z = 0xfff0;
+
+ x = (int32_t)(int16_t)z;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (int32_t)(uint16_t)z;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (uint32_t)(int16_t)z;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (uint32_t)(uint16_t)z;
+ printf("%16x %20d %20u\n", x, x, x);
+ printf("\n");
+
+ x = (int16_t)(int32_t)z;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (int16_t)(uint32_t)z;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (uint16_t)(int32_t)z;
+ printf("%16x %20d %20u\n", x, x, x);
+ x = (uint16_t)(uint32_t)z;
+ printf("%16x %20d %20u\n", x, x, x);
+
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/arithmetic/tst.execcast.d.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,10 @@
+fffffffffffffff0 -16 18446744073709551600
+ fff0 65520 65520
+ fffffff0 4294967280 4294967280
+ fff0 65520 65520
+
+fffffffffffffff0 -16 18446744073709551600
+fffffffffffffff0 -16 18446744073709551600
+ fff0 65520 65520
+ fff0 65520 65520
+
--- a/usr/src/cmd/dtrace/test/tst/common/buffering/tst.fill1.d Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/dtrace/test/tst/common/buffering/tst.fill1.d Sun Aug 12 11:56:48 2012 +0100
@@ -23,26 +23,29 @@
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
-
-#pragma ident "%Z%%M% %I% %E% SMI"
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
/*
* ASSERTION:
* Positive test for fill buffer policy.
*
* SECTION: Buffers and Buffering/fill Policy;
- * Buffers and Buffering/Buffer Sizes;
+ * Buffers and Buffering/Buffer Sizes;
* Options and Tunables/bufsize;
* Options and Tunables/bufpolicy;
* Options and Tunables/statusrate
*/
/*
- * This is a brute-force way of testing fill buffers. We assume that each
- * printf() stores 8 bytes. Because each fill buffer is per-CPU, we must
- * fill up our buffer in one series of enablings on a single CPU.
+ * This is a brute-force way of testing fill buffers. We assume that
+ * each printf() stores 16 bytes (4x 32-bit words for EPID, timestamp
+ * lo, timestamp hi, and the variable i). Because each fill buffer is
+ * per-CPU, we must fill up our buffer in one series of enablings on a
+ * single CPU.
*/
#pragma D option bufpolicy=fill
-#pragma D option bufsize=64
+#pragma D option bufsize=128
#pragma D option statusrate=10ms
#pragma D option quiet
--- a/usr/src/cmd/dtrace/test/tst/common/buffering/tst.ring3.d Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/dtrace/test/tst/common/buffering/tst.ring3.d Sun Aug 12 11:56:48 2012 +0100
@@ -23,8 +23,9 @@
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
-
-#pragma ident "%Z%%M% %I% %E% SMI"
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
/*
* ASSERTION:
@@ -37,19 +38,20 @@
*/
/*
- * We make some regrettable assumptions about the implementation in this test.
- * First, we assume that each entry for the printf() of an int takes _exactly_
- * eight bytes (four bytes for the EPID, four bytes for the payload). Second,
- * we assume that by allocating storage for n + 1 records, we will get exactly
- * n. Here is why: the final predicate that evaluates to false will reserve
- * space that it won't use. This act of reservation will advance the wrapped
- * offset. That record won't be subsequently used, but the wrapped offset has
- * advanced. (And in this case, that old record is clobbered by the exit()
- * anyway.) Thirdly: we rely on t_cpu/cpu_id. Finally: we rely on being
- * able to run on the CPU that we first ran on.
+ * We make some regrettable assumptions about the implementation in this
+ * test. First, we assume that each entry for the printf() of an int
+ * takes _exactly_ 16 bytes (4 bytes for the EPID, 8 bytes for the
+ * timestamp, 4 bytes for the payload). Second, we assume that by
+ * allocating storage for n + 1 records, we will get exactly n. Here is
+ * why: the final predicate that evaluates to false will reserve space
+ * that it won't use. This act of reservation will advance the wrapped
+ * offset. That record won't be subsequently used, but the wrapped
+ * offset has advanced. (And in this case, that old record is clobbered
+ * by the exit() anyway.) Thirdly: we rely on t_cpu/cpu_id. Finally:
+ * we rely on being able to run on the CPU that we first ran on.
*/
#pragma D option bufpolicy=ring
-#pragma D option bufsize=40
+#pragma D option bufsize=80
#pragma D option quiet
int n;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/cg/err.D_NOREG.noreg.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,41 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+/*
+ * Compile some code that requires exactly 9 registers. This should run out
+ * of registers.
+ *
+ * Changes to the code generator might cause this test to succeeed in which
+ * case the code should be changed to another sequence that exhausts the
+ * available internal registers.
+ *
+ * Note that this and err.baddif.d should be kept in sync.
+ */
+
+BEGIN
+{
+ a = 4;
+ trace((a + a) * ((a + a) * ((a + a) * ((a + a) * ((a + a) *
+ ((a + a) * (a + a)))))));
+}
+
+BEGIN
+{
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/cg/err.baddif.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,44 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+/*
+ * Compile some code that requires exactly 9 registers. This should generate
+ * invalid DIF because the kernel will flag the fact that we're using more
+ * registers than are available internally.
+ *
+ * Changes to the code generator might cause this test to succeeed in which
+ * case the code should be changed to another sequence that exhausts the
+ * available internal registers.
+ *
+ * Note that this and err.D_NOREG.noreg.d should be kept in sync.
+ */
+
+#pragma D option iregs=9
+
+BEGIN
+{
+ a = 4;
+ trace((a + a) * ((a + a) * ((a + a) * ((a + a) * ((a + a) *
+ ((a + a) * (a + a)))))));
+}
+
+BEGIN
+{
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/err.D_PRAGMA_OPTSET.setfromscript.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,25 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+#pragma D option setenv=balloon=something_bad_happens
+
+BEGIN
+{
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/err.D_PRAGMA_OPTSET.unsetfromscript.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,25 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+#pragma D option unsetenv=rectalexambot
+
+BEGIN
+{
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/tst.ld_nolazyload.ksh Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,33 @@
+#
+# CDDL HEADER START
+#
+# This file and its contents are supplied under the terms of the
+# Common Development and Distribution License ("CDDL"), version 1.0.
+# You may only use this file in accordance with the terms of version
+# 1.0 of the CDDL.
+#
+# A full copy of the text of the CDDL should have accompanied this
+# source. A copy of the CDDL is also available via the Internet at
+# http://www.illumos.org/license/CDDL.
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+#
+# Check that the LD_NOLAZYLOAD variable is set to 1 as expected.
+#
+
+if [ $# != 1 ]; then
+ echo expected one argument: '<'dtrace-path'>'
+ exit 2
+fi
+
+dtrace=$1
+
+$dtrace -q -Z -n doogle -c 'printenv LD_NOLAZYLOAD'
+
+exit $?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/tst.ld_nolazyload.ksh.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,2 @@
+1
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/tst.setenv1.ksh Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,33 @@
+#
+# CDDL HEADER START
+#
+# This file and its contents are supplied under the terms of the
+# Common Development and Distribution License ("CDDL"), version 1.0.
+# You may only use this file in accordance with the terms of version
+# 1.0 of the CDDL.
+#
+# A full copy of the text of the CDDL should have accompanied this
+# source. A copy of the CDDL is also available via the Internet at
+# http://www.illumos.org/license/CDDL.
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+#
+# Reset an environment variable we already know to be set.
+#
+
+if [ $# != 1 ]; then
+ echo expected one argument: '<'dtrace-path'>'
+ exit 2
+fi
+
+dtrace=$1
+
+$dtrace -q -Z -n doogle -xsetenv=LD_NOLAZYLOAD=0 -c 'printenv LD_NOLAZYLOAD'
+
+exit $?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/tst.setenv1.ksh.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,2 @@
+0
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/tst.setenv2.ksh Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,33 @@
+#
+# CDDL HEADER START
+#
+# This file and its contents are supplied under the terms of the
+# Common Development and Distribution License ("CDDL"), version 1.0.
+# You may only use this file in accordance with the terms of version
+# 1.0 of the CDDL.
+#
+# A full copy of the text of the CDDL should have accompanied this
+# source. A copy of the CDDL is also available via the Internet at
+# http://www.illumos.org/license/CDDL.
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+#
+# Test setting a variable that we isn't already set.
+#
+
+if [ $# != 1 ]; then
+ echo expected one argument: '<'dtrace-path'>'
+ exit 2
+fi
+
+dtrace=$1
+
+$dtrace -q -Z -n doogle -xsetenv=CORPORATIONS=PEOPLE -c 'printenv CORPORATIONS'
+
+exit $?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/tst.setenv2.ksh.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,2 @@
+PEOPLE
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/tst.unsetenv1.ksh Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,33 @@
+#
+# CDDL HEADER START
+#
+# This file and its contents are supplied under the terms of the
+# Common Development and Distribution License ("CDDL"), version 1.0.
+# You may only use this file in accordance with the terms of version
+# 1.0 of the CDDL.
+#
+# A full copy of the text of the CDDL should have accompanied this
+# source. A copy of the CDDL is also available via the Internet at
+# http://www.illumos.org/license/CDDL.
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+#
+# Test unsetting a variable we know to be set.
+#
+
+if [ $# != 1 ]; then
+ echo expected one argument: '<'dtrace-path'>'
+ exit 2
+fi
+
+dtrace=$1
+
+$dtrace -q -Z -n doogle -xunsetenv=LD_NOLAZYLOAD -c 'printenv LD_NOLAZYLOAD'
+
+exit $?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/tst.unsetenv1.ksh.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,1 @@
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/tst.unsetenv2.ksh Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,35 @@
+#
+# CDDL HEADER START
+#
+# This file and its contents are supplied under the terms of the
+# Common Development and Distribution License ("CDDL"), version 1.0.
+# You may only use this file in accordance with the terms of version
+# 1.0 of the CDDL.
+#
+# A full copy of the text of the CDDL should have accompanied this
+# source. A copy of the CDDL is also available via the Internet at
+# http://www.illumos.org/license/CDDL.
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+#
+# Test invalid syntax to the unsetenv option.
+#
+
+if [ $# != 1 ]; then
+ echo expected one argument: '<'dtrace-path'>'
+ exit 2
+fi
+
+dtrace=$1
+
+$dtrace -q -Z -n doogle -xunsetenv=ed=screven -c 'true' 2>&1
+
+[[ $? -eq 1 ]] && exit 0
+
+exit 1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/env/tst.unsetenv2.ksh.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,1 @@
+dtrace: failed to set -x unsetenv: Invalid value for specified option
--- a/usr/src/cmd/dtrace/test/tst/common/pid/tst.newprobes.ksh Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/dtrace/test/tst/common/pid/tst.newprobes.ksh Sun Aug 12 11:56:48 2012 +0100
@@ -24,7 +24,9 @@
# Copyright 2008 Sun Microsystems, Inc. All rights reserved.
# Use is subject to license terms.
#
-# ident "%Z%%M% %I% %E% SMI"
+
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
#
if [ $# != 1 ]; then
@@ -49,13 +51,13 @@
tick-1s
/(i % 2) == 0/
{
- system("dtrace -c date -ln 'pid\$target::main:entry' >/dev/null");
+ system("dtrace -c date -n 'pid\$target::main:entry' >/dev/null");
}
tick-1s
/(i % 2) == 1/
{
- system("dtrace -c date -ln 'pid\$target::main:return' >/dev/null");
+ system("dtrace -c date -n 'pid\$target::main:return' >/dev/null");
}
EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/pointers/tst.assigncast1.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,28 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+BEGIN
+{
+ *((int *)alloca(4)) = 1;
+}
+
+BEGIN
+{
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/pointers/tst.assigncast2.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,29 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+BEGIN
+{
+ this->a = alloca(4);
+ *((int *)this->a) = 1;
+}
+
+BEGIN
+{
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/pragma/tst.temporal.ksh Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,106 @@
+#!/bin/ksh -p
+#
+# CDDL HEADER START
+#
+# This file and its contents are supplied under the terms of the
+# Common Development and Distribution License ("CDDL"), version 1.0.
+# You may only use this file in accordance with the terms of version
+# 1.0 of the CDDL.
+#
+# A full copy of the text of the CDDL should have accompanied this
+# source. A copy of the CDDL is also available via the Internet at
+# http://www.illumos.org/license/CDDL.
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+############################################################################
+# ASSERTION:
+# temporal option causes output to be sorted
+#
+# SECTION: Pragma
+#
+# NOTES: The temporal option has no effect on a single-CPU system, so
+# this needs to be run on a multi-CPU system to effectively test the
+# temporal option.
+#
+############################################################################
+
+if [ $# != 1 ]; then
+ echo expected one argument: '<'dtrace-path'>'
+ exit 2
+fi
+
+dtrace=$1
+file=/tmp/out.$$
+
+rm -f $file
+
+$dtrace -o $file -c 'sleep 3' -s /dev/stdin <<EOF
+ #pragma D option quiet
+ #pragma D option temporal
+
+ BEGIN
+ {
+ @lines = count();
+ printf("0 begin\n");
+ }
+
+ END
+ {
+ /* Bump @lines every time we print a line. */
+ @lines = count();
+ printf("%u end\n", timestamp);
+ @lines = count();
+ printa("99999999999999999 lines %@u\n", @lines);
+ }
+
+ profile-97hz
+ {
+ @lines = count();
+ printf("%u\n", timestamp);
+ }
+EOF
+
+status=$?
+if [ "$status" -ne 0 ]; then
+ echo $tst: dtrace failed
+ exit $status
+fi
+
+# dtrace outputs a blank line at the end, which will sort to the beginning,
+# so use head to remove the blank line.
+head -n -1 $file > $file.2
+
+sort -n $file.2 | diff $file.2 -
+status=$?
+if [ "$status" -ne 0 ]; then
+ echo $tst: output is not sorted
+ exit $status
+fi
+
+head -n 1 $file.2 | grep begin >/dev/null
+status=$?
+if [ "$status" -ne 0 ]; then
+ echo $tst: begin probe did not fire
+ exit $status
+fi
+
+tail -n 2 $file.2 | grep end >/dev/null
+status=$?
+if [ "$status" -ne 0 ]; then
+ echo $tst: end probe did not fire
+ exit $status
+fi
+
+if [ $(tail -n 1 $file.2 | cut -f3 -d ' ') -ne \
+ $(wc -l $file.2) ]; then
+ echo $tst: incorrect number of lines output
+ exit 1
+fi
+
+exit $status
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/pragma/tst.temporal2.ksh Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,102 @@
+#!/bin/ksh -p
+#
+# CDDL HEADER START
+#
+# This file and its contents are supplied under the terms of the
+# Common Development and Distribution License ("CDDL"), version 1.0.
+# You may only use this file in accordance with the terms of version
+# 1.0 of the CDDL.
+#
+# A full copy of the text of the CDDL should have accompanied this
+# source. A copy of the CDDL is also available via the Internet at
+# http://www.illumos.org/license/CDDL.
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+############################################################################
+# ASSERTION:
+# temporal option causes output to be sorted, even when some
+# buffers are empty
+#
+# SECTION: Pragma
+#
+# NOTES: The temporal option has no effect on a single-CPU system, so
+# this needs to be run on a multi-CPU system to effectively test the
+# temporal option.
+#
+############################################################################
+
+if [ $# != 1 ]; then
+ echo expected one argument: '<'dtrace-path'>'
+ exit 2
+fi
+
+dtrace=$1
+file=/tmp/out.$$
+
+rm -f $file
+
+$dtrace -o $file -s /dev/stdin <<EOF
+ #pragma D option quiet
+ #pragma D option destructive
+ #pragma D option temporal
+ #pragma D option switchrate=1000hz
+
+ /*
+ * Use two enablings of the same probe, so that cpu 0 will always
+ * record its data just a little bit before the other cpus.
+ * We don't want to use the chill() action in the same enabling
+ * that we record the timestamp, because chill() causes the
+ * timestamp to be re-read, and thus not match the timestamp
+ * which libdtrace uses to sort the records.
+ */
+
+ profile-401
+ /cpu == 0/
+ {
+ printf("%d\n", timestamp);
+ }
+
+ profile-401
+ /cpu != 0/
+ {
+ chill(1000); /* one microsecond */
+ }
+
+ profile-401
+ /cpu != 0/
+ {
+ printf("%d\n", timestamp);
+ }
+
+ tick-1s
+ /k++ == 10/
+ {
+ printf("%d\n", timestamp);
+ exit(0);
+ }
+EOF
+
+status=$?
+if [ "$status" -ne 0 ]; then
+ echo $tst: dtrace failed
+ exit $status
+fi
+
+# dtrace outputs a blank line at the end, which will sort to the beginning,
+# so use grep to remove the blank line.
+head -n -1 $file > $file.2
+
+sort -n $file.2 | diff $file.2 -
+status=$?
+if [ "$status" -ne 0 ]; then
+ echo $tst: output is not sorted
+ exit $status
+fi
+
+exit $status
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/pragma/tst.temporal3.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,48 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+/*
+ * This test excercises the "remnant" handling of the temporal option.
+ * At the end of one pass of retrieving and printing data from all CPUs,
+ * some unprocessed data will remain, because its timestamp is after the
+ * time covered by all CPUs' buffers. This unprocessed data is
+ * rearranged in a more space-efficient manner. If this is done
+ * incorrectly, an alignment error may occur. To test this, we use a
+ * high-frequency probe so that data will be recorded in subsequent
+ * CPU's buffers after the first CPU's buffer is obtained. The
+ * combination of data traced here (a 8-byte value and a 4-byte value)
+ * is effective to cause alignment problems with an incorrect
+ * implementation.
+ *
+ * This test needs to be run on a multi-CPU system to be effective.
+ */
+
+#pragma D option quiet
+#pragma D option temporal
+
+profile-4997
+{
+ printf("%u %u", 1ULL, 2);
+}
+
+tick-1
+/i++ == 10/
+{
+ exit(0);
+}
--- a/usr/src/cmd/dtrace/test/tst/common/predicates/tst.predcache.ksh Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,197 +0,0 @@
-#
-# CDDL HEADER START
-#
-# The contents of this file are subject to the terms of the
-# Common Development and Distribution License (the "License").
-# You may not use this file except in compliance with the License.
-#
-# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
-# or http://www.opensolaris.org/os/licensing.
-# See the License for the specific language governing permissions
-# and limitations under the License.
-#
-# When distributing Covered Code, include this CDDL HEADER in each
-# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
-# If applicable, add the following below this CDDL HEADER, with the
-# fields enclosed by brackets "[]" replaced with your own identifying
-# information: Portions Copyright [yyyy] [name of copyright owner]
-#
-# CDDL HEADER END
-#
-
-#
-# Copyright 2007 Sun Microsystems, Inc. All rights reserved.
-# Use is subject to license terms.
-#
-# ident "%Z%%M% %I% %E% SMI"
-
-unload()
-{
- #
- # Get the list of services whose processes have USDT probes. Ideally
- # it would be possible to unload the fasttrap provider while USDT
- # probes exist -- once that fix is integrated, this hack can go away
- # We create two lists -- one of regular SMF services and one of legacy
- # services -- since each must be enabled and disabled using a specific
- # mechanism.
- #
- pids=$(dtrace -l | \
- perl -ne 'print "$1\n" if (/^\s*\S+\s+\S*\D(\d+)\s+/);' | \
- sort | uniq | tr '\n' ',')
-
- ctids=$(ps -p $pids -o ctid | tail +2 | sort | uniq)
- svcs=
- lrcs=
-
- for ct in $ctids
- do
- line=$(svcs -o fmri,ctid | grep " $ct\$")
- svc=$(echo $line | cut -d' ' -f1)
-
- if [[ $(svcs -Ho STA $svc) == "LRC" ]]; then
- lrc=$(svcs -Ho SVC $svc | tr _ '?')
- lrcs="$lrcs $lrc"
- else
- svcs="$svcs $svc"
- fi
- done
-
- for svc in $svcs
- do
- svcadm disable -ts $svc
- done
-
- for lrc in $lrcs
- do
- #
- # Does it seem a little paternalistic that lsvcrun requires
- # this environment variable to be set? I'd say so...
- #
- SMF_RESTARTER=svc:/system/svc/restarter:default \
- /lib/svc/bin/lsvcrun $lrc stop
- done
-
- modunload -i 0
- modunload -i 0
- modunload -i 0
- modinfo | grep dtrace
- success=$?
-
- for svc in $svcs
- do
- svcadm enable -ts $svc
- done
-
- for lrc in $lrcs
- do
- SMF_RESTARTER=svc:/system/svc/restarter:default \
- /lib/svc/bin/lsvcrun $lrc start
- done
-
- if [ ! $success ]; then
- echo $tst: could not unload dtrace
- exit 1
- fi
-}
-
-script1()
-{
- $dtrace -s /dev/stdin <<EOF
- syscall:::entry
- /pid != $ppid/
- {
- @a[probefunc] = count();
- }
-
- tick-1sec
- /i++ == 5/
- {
- exit(0);
- }
-EOF
-}
-
-script2()
-{
- $dtrace -s /dev/stdin <<EOF
-
- #pragma D option statusrate=1ms
-
- syscall:::entry
- /pid == $ppid/
- {
- ttl++;
- }
-
- tick-1sec
- /i++ == 5/
- {
- exit(2);
- }
-
- END
- /ttl/
- {
- printf("success; ttl is %d", ttl);
- exit(0);
- }
-
- END
- /ttl == 0/
- {
- printf("error -- total should be non-zero");
- exit(1);
- }
-EOF
-}
-
-if [ $# != 1 ]; then
- echo expected one argument: '<'dtrace-path'>'
- exit 2
-fi
-
-ppid=$$
-dtrace=$1
-
-unload
-script1 &
-child=$!
-
-let waited=0
-
-while [ "$waited" -lt 5 ]; do
- seconds=`date +%S`
-
- if [ "$seconds" -ne "$last" ]; then
- last=$seconds
- let waited=waited+1
- fi
-done
-
-wait $child
-status=$?
-
-if [ "$status" -ne 0 ]; then
- echo $tst: first dtrace failed
- exit $status
-fi
-
-unload
-script2 &
-child=$!
-
-let waited=0
-
-while [ "$waited" -lt 10 ]; do
- seconds=`date +%S`
-
- if [ "$seconds" -ne "$last" ]; then
- last=$seconds
- let waited=waited+1
- fi
-done
-
-wait $child
-status=$?
-
-exit $status
--- a/usr/src/cmd/dtrace/test/tst/common/print/err.D_PRINT_DYN.bad.d Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,29 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright (c) 2011 by Delphix. All rights reserved.
- */
-
-BEGIN
-{
- print(*curpsinfo);
-}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/print/tst.dyn.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,28 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+BEGIN
+{
+ print(*curpsinfo);
+}
+
+BEGIN
+{
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/print/tst.xlate.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,42 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+#pragma D option quiet
+
+typedef struct pancakes {
+ int i;
+ string s;
+ timespec_t t;
+} pancakes_t;
+
+translator pancakes_t < void *V > {
+ i = 2 * 10;
+ s = strjoin("I like ", "pancakes");
+ t = *(timespec_t *)`dtrace_zero;
+};
+
+BEGIN
+{
+ print(*(xlate < pancakes_t * > ((void *)NULL)));
+}
+
+BEGIN
+{
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/print/tst.xlate.d.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,8 @@
+pancakes_t {
+ int i = 0x14
+ string s = [ "I like pancakes" ]
+ timespec_t t = {
+ time_t tv_sec = 0
+ long tv_nsec = 0
+ }
+}
--- a/usr/src/cmd/dtrace/test/tst/common/printf/tst.ints.d.out Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/dtrace/test/tst/common/printf/tst.ints.d.out Sun Aug 12 11:56:48 2012 +0100
@@ -1,6 +1,6 @@
-239
-52719
+-17
+-12817
-1867788817
1311768467294899695
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/printf/tst.signs.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,38 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+/*
+ * Check %d v. %i v. %u.
+ */
+
+#pragma D option quiet
+
+uint16_t x;
+int16_t y;
+
+BEGIN
+{
+ x = 0xffffffff;
+ y = 0xffffffff;
+
+ printf("%d %i %u\n", x, x, x);
+ printf("%d %i %u\n", y, y, y);
+
+ exit(0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/printf/tst.signs.d.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,3 @@
+65535 -1 65535
+-1 -1 65535
+
--- a/usr/src/cmd/dtrace/test/tst/common/speculation/err.BufSizeVariations1.d Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/dtrace/test/tst/common/speculation/err.BufSizeVariations1.d Sun Aug 12 11:56:48 2012 +0100
@@ -24,7 +24,10 @@
* Use is subject to license terms.
*/
-#pragma ident "%Z%%M% %I% %E% SMI"
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
/*
* ASSERTION:
@@ -35,17 +38,10 @@
*
* NOTES: This test behaves differently depending on the values
* assigned to bufsize.
- * 1. 0 > bufsize.
- * 2. 0 == bufsize.
- * 3. 0 < bufsize <= 7
- * 4. 8 <= bufsize <= 31
- * 5. 32 <= bufsize <= 47
- * 6. 48 <= bufsize <= 71
- * 7. 72 <= bufsize
*/
#pragma D option quiet
-#pragma D option bufsize=41
+#pragma D option bufsize=49
BEGIN
{
--- a/usr/src/cmd/dtrace/test/tst/common/speculation/tst.SpecSizeVariations3.d Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/dtrace/test/tst/common/speculation/tst.SpecSizeVariations3.d Sun Aug 12 11:56:48 2012 +0100
@@ -24,7 +24,10 @@
* Use is subject to license terms.
*/
-#pragma ident "%Z%%M% %I% %E% SMI"
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
/*
* ASSERTION:
* Verify the behavior of speculations with changes in specsize.
@@ -35,7 +38,7 @@
*/
#pragma D option quiet
-#pragma D option specsize=40
+#pragma D option specsize=48
BEGIN
{
--- a/usr/src/cmd/dtrace/test/tst/common/trace/err.D_TRACE_DYN.bad.d Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,29 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright (c) 2011 by Delphix. All rights reserved.
- */
-
-BEGIN
-{
- trace(*curpsinfo);
-}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/trace/tst.dyn.d Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,28 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+BEGIN
+{
+ trace(*curpsinfo);
+}
+
+BEGIN
+{
+ exit(0);
+}
--- a/usr/src/cmd/dtrace/test/tst/common/translators/man.TestTransStability.d Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,61 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
- * Use is subject to license terms.
- */
-
-#pragma ident "%Z%%M% %I% %E% SMI"
-
-/*
- * ASSERTION:
- * The D inline translation mechanism can be used to facilitate stable
- * translations.
- *
- * SECTION: Translators/ Translator Declarations
- * SECTION: Translators/ Translate Operator
- * SECTION: Translators/Stable Translations
- *
- * NOTES: Uncomment the pragma that explicitly resets the attributes of
- * myinfo identifier to Stable/Stable/Common from Private/Private/Unknown.
- * Run the program with and without the comments as:
- * /usr/sbin/dtrace -vs man.TestTransStability.d
- */
-
-#pragma D option quiet
-
-inline lwpsinfo_t *myinfo = xlate < lwpsinfo_t *> (curthread);
-
-/*
-#pragma D attributes Stable/Stable/Common myinfo
-*/
-
-BEGIN
-{
- trace(myinfo->pr_flag);
- exit(0);
-}
-
-ERROR
-{
- exit(1);
-}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/translators/tst.TestTransStability1.ksh Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,62 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright 2006 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+#
+# Test the output for stable translations.
+#
+
+if [ $# != 1 ]; then
+ echo expected one argument: '<'dtrace-path'>'
+ exit 2
+fi
+
+dtrace=$1
+
+$dtrace -v -s /dev/stdin <<EOF
+
+#pragma D option quiet
+
+inline lwpsinfo_t *myinfo = xlate < lwpsinfo_t *> (curthread);
+
+#pragma D attributes Stable/Stable/Common myinfo
+
+BEGIN
+{
+ this->a = myinfo->pr_flag;
+ exit(0);
+}
+
+BEGIN
+{
+ exit(1);
+}
+EOF
+
+exit $?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/translators/tst.TestTransStability1.ksh.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,14 @@
+
+Stability attributes for script /dev/stdin:
+
+ Minimum Probe Description Attributes
+ Identifier Names: Unstable
+ Data Semantics: Unstable
+ Dependency Class: Common
+
+ Minimum Statement Attributes
+ Identifier Names: Stable
+ Data Semantics: Stable
+ Dependency Class: Common
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/translators/tst.TestTransStability2.ksh Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,60 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright 2006 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+#
+# Test the output of unstable translations.
+#
+
+if [ $# != 1 ]; then
+ echo expected one argument: '<'dtrace-path'>'
+ exit 2
+fi
+
+dtrace=$1
+
+$dtrace -v -s /dev/stdin <<EOF
+
+#pragma D option quiet
+
+inline lwpsinfo_t *myinfo = xlate < lwpsinfo_t *> (curthread);
+
+BEGIN
+{
+ this->a = myinfo->pr_flag;
+ exit(0);
+}
+
+BEGIN
+{
+ exit(1);
+}
+EOF
+
+exit $?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/cmd/dtrace/test/tst/common/translators/tst.TestTransStability2.ksh.out Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,14 @@
+
+Stability attributes for script /dev/stdin:
+
+ Minimum Probe Description Attributes
+ Identifier Names: Unstable
+ Data Semantics: Unstable
+ Dependency Class: Common
+
+ Minimum Statement Attributes
+ Identifier Names: Private
+ Data Semantics: Private
+ Dependency Class: Unknown
+
+
--- a/usr/src/cmd/format/menu_command.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/format/menu_command.c Sun Aug 12 11:56:48 2012 +0100
@@ -1563,20 +1563,24 @@
fmt_print("[1] EFI Label\n");
ioparam.io_bounds.lower = 0;
ioparam.io_bounds.upper = 1;
- if (cur_label == L_TYPE_SOLARIS)
- deflt = 0;
+ if ((cur_label == L_TYPE_SOLARIS) &&
+ (cur_disk->fdisk_part.systid != EFI_PMBR))
+ deflt = L_TYPE_SOLARIS;
else
- deflt = 1;
+ deflt = L_TYPE_EFI;
defltptr = &deflt;
choice = input(FIO_INT, "Specify Label type", ':',
&ioparam, defltptr, DATA_INPUT);
- if ((choice == 0) && (cur_label == L_TYPE_SOLARIS)) {
+ if ((choice == L_TYPE_SOLARIS) &&
+ (cur_label == L_TYPE_SOLARIS) &&
+ (cur_disk->fdisk_part.systid != EFI_PMBR)) {
goto expert_end;
- } else if ((choice == 1) && (cur_label == L_TYPE_EFI)) {
+ } else if ((choice == L_TYPE_EFI) &&
+ (cur_label == L_TYPE_EFI)) {
goto expert_end;
}
switch (choice) {
- case 0:
+ case L_TYPE_SOLARIS:
/*
* EFI label to SMI label
*/
@@ -1648,17 +1652,19 @@
}
- case 1:
+ case L_TYPE_EFI:
/*
* SMI label to EFI label
*/
-
- fmt_print("Warning: This disk has an SMI label. Changing to "
- "EFI label will erase all\ncurrent partitions.\n");
-
- if (check("Continue")) {
- return (-1);
+ if ((cur_disk->fdisk_part.systid == SUNIXOS) ||
+ (cur_disk->fdisk_part.systid == SUNIXOS2)) {
+ fmt_print("Warning: This disk has an SMI label. "
+ "Changing to EFI label will erase all\ncurrent "
+ "partitions.\n");
+ if (check("Continue")) {
+ return (-1);
+ }
}
if (get_disk_info(cur_file, &efinfo) != 0) {
--- a/usr/src/cmd/fs.d/hsfs/fstyp/fstyp.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/fs.d/hsfs/fstyp/fstyp.c Sun Aug 12 11:56:48 2012 +0100
@@ -23,8 +23,6 @@
* Use is subject to license terms.
*/
-#pragma ident "%Z%%M% %I% %E% SMI"
-
/*
* libfstyp module for hsfs
*/
@@ -42,9 +40,9 @@
#include <sys/dkio.h>
#include <libnvpair.h>
#include <libfstyp_module.h>
-#include "hsfs_spec.h"
-#include "iso_spec.h"
-#include "iso_impl.h"
+
+#include <sys/fs/hsfs_spec.h>
+#include <sys/fs/hsfs_isospec.h>
typedef struct fstyp_hsfs {
int fd;
--- a/usr/src/cmd/fs.d/hsfs/fstyp/hsfs_spec.h Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,268 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License"). You may not use this file except in compliance
- * with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-#pragma ident "%Z%%M% %I% %E% SMI"
-
-/*
- * High Sierra filesystem specification
- * Copyright (c) 1989 by Sun Microsystem, Inc.
- */
-
-#ifndef _HSFS_SPEC_H_
-#define _HSFS_SPEC_H_
-
-#include <sys/isa_defs.h> /* for ENDIAN defines */
-
-/* routines required for date parsing */
-extern void hs_parse_dirdate(); /* parse date in directory */
-extern void hs_parse_longdate(); /* parse date in volume id */
-
-/* macros to parse binary integers */
-#define ZERO(x) (u_int) (((u_char *)(x))[0])
-#define ONE(x) (u_int) (((u_char *)(x))[1])
-#define TWO(x) (u_int) (((u_char *)(x))[2])
-#define THREE(x) (u_int) (((u_char *)(x))[3])
-
-#define MSB_INT(x) \
- ((((((ZERO(x) << 8) | ONE(x)) << 8) | TWO(x)) << 8) | THREE(x))
-#define LSB_INT(x) \
- ((((((THREE(x) << 8) | TWO(x)) << 8) | ONE(x)) << 8) | ZERO(x))
-#define MSB_SHORT(x) ((ZERO(x) << 8) | ONE(x))
-#define LSB_SHORT(x) ((ONE(x) << 8) | ZERO(x))
-
-#if defined(_LITTLE_ENDIAN)
-#define BOTH_SHORT(x) (short) *((short *)x)
-#define BOTH_INT(x) (int) *((int *)x)
-#endif
-
-/*
- * The following describes actual on-disk structures.
- * To achieve portability, all structures are #defines
- * rather than a structure definition. Macros are provided
- * to get either the data or address of individual fields.
- */
-
-/* Overall High Sierra disk structure */
-#define HS_SECTOR_SIZE 2048 /* bytes per logical sector */
-#define HS_SECTOR_SHIFT 11 /* sector<->byte shift count */
-#define HS_SEC_PER_PAGE (PAGESIZE/HS_SECTOR_SIZE) /* sectors per page */
-#define HS_SYSAREA_SEC 0 /* 1st sector of system area */
-#define HS_VOLDESC_SEC 16 /* 1st sector of volume descriptors */
-#define MAXHSOFFSET (HS_SECTOR_SIZE - 1)
-#define MAXHSMASK (~MAXHSOFFSET)
-
-/* Standard File Structure Volume Descriptor */
-
-enum hs_voldesc_type {
- VD_BOOT=0, VD_SFS=1, VD_CCFS=2, VD_UNSPEC=3, VD_EOV=255
-};
-#define HSV_ID_STRING "CDROM" /* HSV_std_id field */
-#define HSV_ID_STRLEN 5 /* HSV_std_id field length */
-#define HSV_ID_VER 1 /* HSV_std_ver field */
-#define HSV_FILE_STRUCT_ID_VER 1 /* HSV_file_struct_ver field */
-#define HSV_SYS_ID_STRLEN 32 /* HSV_sys_id field length */
-#define HSV_VOL_ID_STRLEN 32 /* HSV_vol_id field length */
-#define HSV_VOL_SET_ID_STRLEN 128 /* HSV_vol_set_id field length */
-#define HSV_PUB_ID_STRLEN 128 /* HSV_pub_id field length */
-#define HSV_PREP_ID_STRLEN 128 /* HSV_prep_id field length */
-#define HSV_APPL_ID_STRLEN 128 /* HSV_appl_id field length */
-#define HSV_COPYR_ID_STRLEN 32 /* HSV_copyr_id field length */
-#define HSV_ABSTR_ID_STRLEN 32 /* HSV_abstr_id field length */
-#define HSV_DATE_LEN 16 /* HSV date filed length */
-
-/* macros to get the address of each field */
-#define HSV_desc_lbn(x) (&((u_char *)x)[0])
-#define HSV_desc_type(x) (&((u_char *)x)[8])
-#define HSV_std_id(x) (&((u_char *)x)[9])
-#define HSV_std_ver(x) (&((u_char *)x)[14])
-#define HSV_sys_id(x) (&((u_char *)x)[16])
-#define HSV_vol_id(x) (&((u_char *)x)[48])
-#define HSV_vol_size(x) (&((u_char *)x)[88])
-#define HSV_set_size(x) (&((u_char *)x)[128])
-#define HSV_set_seq(x) (&((u_char *)x)[132])
-#define HSV_blk_size(x) (&((u_char *)x)[136])
-#define HSV_ptbl_size(x) (&((u_char *)x)[140])
-#define HSV_ptbl_man_ls(x) (&((u_char *)x)[148])
-#define HSV_ptbl_opt_ls1(x) (&((u_char *)x)[152])
-#define HSV_ptbl_opt_ls2(x) (&((u_char *)x)[156])
-#define HSV_ptbl_opt_ls3(x) (&((u_char *)x)[160])
-#define HSV_ptbl_man_ms(x) (&((u_char *)x)[164])
-#define HSV_ptbl_opt_ms1(x) (&((u_char *)x)[168])
-#define HSV_ptbl_opt_ms2(x) (&((u_char *)x)[172])
-#define HSV_ptbl_opt_ms3(x) (&((u_char *)x)[176])
-#define HSV_root_dir(x) (&((u_char *)x)[180])
-#define HSV_vol_set_id(x) (&((u_char *)x)[214])
-#define HSV_pub_id(x) (&((u_char *)x)[342])
-#define HSV_prep_id(x) (&((u_char *)x)[470])
-#define HSV_appl_id(x) (&((u_char *)x)[598])
-#define HSV_copyr_id(x) (&((u_char *)x)[726])
-#define HSV_abstr_id(x) (&((u_char *)x)[758])
-#define HSV_cre_date(x) (&((u_char *)x)[790])
-#define HSV_mod_date(x) (&((u_char *)x)[806])
-#define HSV_exp_date(x) (&((u_char *)x)[822])
-#define HSV_eff_date(x) (&((u_char *)x)[838])
-#define HSV_file_struct_ver(x) (&((u_char *)x)[854])
-
-/* macros to get the values of each field (strings are returned as ptrs) */
-#define HSV_DESC_LBN(x) BOTH_INT(HSV_desc_lbn(x))
-#define HSV_DESC_TYPE(x) ((enum hs_voldesc_type)*(HSV_desc_type(x)))
-#define HSV_STD_ID(x) HSV_std_id(x)
-#define HSV_STD_VER(x) *(HSV_std_ver(x))
-#define HSV_SYS_ID(x) HSV_sys_id(x)
-#define HSV_VOL_ID(x) HSV_vol_id(x)
-#define HSV_VOL_SIZE(x) BOTH_INT(HSV_vol_size(x))
-#define HSV_SET_SIZE(x) BOTH_SHORT(HSV_set_size(x))
-#define HSV_SET_SEQ(x) BOTH_SHORT(HSV_set_seq(x))
-#define HSV_BLK_SIZE(x) BOTH_SHORT(HSV_blk_size(x))
-#define HSV_PTBL_SIZE(x) BOTH_INT(HSV_ptbl_size(x))
-#define HSV_PTBL_MAN_LS(x) LSB_INT(HSV_ptbl_man_ls(x))
-#define HSV_PTBL_OPT_LS1(x) LSB_INT(HSV_ptbl_opt_ls1(x))
-#define HSV_PTBL_OPT_LS2(x) LSB_INT(HSV_ptbl_opt_ls2(x))
-#define HSV_PTBL_OPT_LS3(x) LSB_INT(HSV_ptbl_opt_ls3(x))
-#define HSV_PTBL_MAN_MS(x) MSB_INT(HSV_ptbl_man_ms(x))
-#define HSV_PTBL_OPT_MS1(x) MSB_INT(HSV_ptbl_opt_ms1(x))
-#define HSV_PTBL_OPT_MS2(x) MSB_INT(HSV_ptbl_opt_ms2(x))
-#define HSV_PTBL_OPT_MS3(x) MSB_INT(HSV_ptbl_opt_ms3(x))
-#define HSV_ROOT_DIR(x) HSV_root_dir(x)
-#define HSV_VOL_SET_ID(x) HSV_vol_set_id(x)
-#define HSV_PUB_ID(x) HSV_pub_id(x)
-#define HSV_PREP_ID(x) HSV_prep_id(x)
-#define HSV_APPL_ID(x) HSV_appl_id(x)
-#define HSV_COPYR_ID(x) HSV_copyr_id(x)
-#define HSV_ABSTR_ID(x) HSV_abstr_id(x)
-#define HSV_CRE_DATE(x) HSV_cre_date(x)
-#define HSV_MOD_DATE(x) HSV_mod_date(x)
-#define HSV_EXP_DATE(x) HSV_exp_date(x)
-#define HSV_EFF_DATE(x) HSV_eff_date(x)
-#define HSV_FILE_STRUCT_VER(x) *(HSV_file_struct_ver(x))
-
-/* Standard File Structure Volume Descriptor date fields */
-#define HSV_DATE_2DIG(x) ( (((x)[0] - '0') * 10) + \
- ((x)[1] - '0') )
-#define HSV_DATE_4DIG(x) ( (((x)[0] - '0') * 1000) + \
- (((x)[1] - '0') * 100) + \
- (((x)[2] - '0') * 10) + \
- ((x)[3] - '0') )
-#define HSV_DATE_YEAR(x) HSV_DATE_4DIG(&((u_char *)x)[0])
-#define HSV_DATE_MONTH(x) HSV_DATE_2DIG(&((u_char *)x)[4])
-#define HSV_DATE_DAY(x) HSV_DATE_2DIG(&((u_char *)x)[6])
-#define HSV_DATE_HOUR(x) HSV_DATE_2DIG(&((u_char *)x)[8])
-#define HSV_DATE_MIN(x) HSV_DATE_2DIG(&((u_char *)x)[10])
-#define HSV_DATE_SEC(x) HSV_DATE_2DIG(&((u_char *)x)[12])
-#define HSV_DATE_HSEC(x) HSV_DATE_2DIG(&((u_char *)x)[14])
-
-/* Path table enry */
-/* fix size of path table entry */
-#define HPE_FPESIZE 8
-/* macros to get the address of each field */
-#define HPE_ext_lbn(x) (&((u_char *)x)[0])
-#define HPE_xar_len(x) (&((u_char *)x)[4])
-#define HPE_name_len(x) (&((u_char *)x)[5])
-#define HPE_parent_no(x) (&((u_char *)x)[6])
-#define HPE_name(x) (&((u_char *)x)[8])
-
-/* macros to get the values of each field */
-#if sun4
-#define HPE_EXT_LBN(x) (MSB_INT(HPE_ext_lbn(x)))
-#else
-#define HPE_EXT_LBN(x) *(int *)(HPE_ext_lbn(x))
-#endif
-#define HPE_XAR_LEN(x) *(HPE_xar_len(x))
-#define HPE_NAME_LEN(x) *(HPE_name_len(x))
-#define HPE_PARENT_NO(x) *(short *)(HPE_parent_no(x))
-#define HPE_NAME(x) HPE_name(x)
-
-/* root record */
-#define HDE_ROOT_DIR_REC_SIZE 34 /* size of root directory record */
-#define HDE_FDESIZE 33 /* fixed size for hsfs directory area */
-#define HDE_FUSIZE 12 /* fixed size for unix areaa */
- /* max size of a name */
-#define HDE_MAX_NAME_LEN (255 - HDE_FDESIZE - HDE_FUSIZE)
-
-/* Directory Entry (Directory Record) */
-
-#define UNIX_TO_HDE_DATE(t,p) parse_unixdate(t, p) /* return val at p */
-
-/* macros to get the address of each field */
-#define HDE_dir_len(x) (&((u_char *)x)[0])
-#define HDE_xar_len(x) (&((u_char *)x)[1])
-#define HDE_ext_lbn(x) (&((u_char *)x)[2])
-#define HDE_ext_size(x) (&((u_char *)x)[10])
-#define HDE_cdate(x) (&((u_char *)x)[18])
-#define HDE_flags(x) (&((u_char *)x)[24])
-#define HDE_reserved(x) (&((u_char *)x)[25])
-#define HDE_intrlv_size(x) (&((u_char *)x)[26])
-#define HDE_intrlv_skip(x) (&((u_char *)x)[27])
-#define HDE_vol_set(x) (&((u_char *)x)[28])
-#define HDE_name_len(x) (&((u_char *)x)[32])
-#define HDE_name(x) (&((u_char *)x)[33])
-
-/***UNIX extension****/
-#define HDE_mode(x) (&((u_char *)x)[0])
-#define HDE_uid(x) (&((u_char *)x)[4])
-#define HDE_gid(x) (&((u_char *)x)[8])
-
-/* macros to get the values of each field (strings are returned as ptrs) */
-#define HDE_DIR_LEN(x) *(HDE_dir_len(x))
-#define HDE_XAR_LEN(x) *(HDE_xar_len(x))
-#define HDE_EXT_LBN(x) BOTH_INT(HDE_ext_lbn(x))
-#define HDE_EXT_SIZE(x) BOTH_INT(HDE_ext_size(x))
-#define HDE_CDATE(x) HDE_cdate(x)
-#define HDE_FLAGS(x) *(HDE_flags(x))
-#define HDE_RESERVED(x) *(HDE_reserved(x))
-#define HDE_INTRLV_SIZE(x) *(HDE_intrlv_size(x))
-#define HDE_INTRLV_SKIP(x) *(HDE_intrlv_skip(x))
-#define HDE_VOL_SET(x) BOTH_SHORT(HDE_vol_set(x))
-#define HDE_NAME_LEN(x) *(HDE_name_len(x))
-#define HDE_NAME(x) HDE_name(x)
-
-/***UNIX EXTENSION*****/
-#define HDE_MODE(x) *(HDE_mode(x))
-#define HDE_UID(x) *(HDE_uid(x))
-#define HDE_GID(x) *(HDE_gid(x))
-
-/* mask bits for HDE_FLAGS */
-#define HDE_EXISTENCE 0x01 /* zero if file exists */
-#define HDE_DIRECTORY 0x02 /* zero if file is not a directory */
-#define HDE_ASSOCIATED 0x04 /* zero if file is not Associated */
-#define HDE_RECORD 0x08 /* zero if no record attributes */
-#define HDE_PROTECTION 0x10 /* zero if no protection attributes */
-#define HDE_UNUSED_FLAGS 0x60
-#define HDE_LAST_EXTENT 0x80 /* zero if last extent in file */
-#define HDE_PROHIBITED (HDE_DIRECTORY | HDE_ASSOCIATED | HDE_RECORD | \
- HDE_LAST_EXTENT | HDE_UNUSED_FLAGS)
-
-/* Directory Record date fields */
-#define HDE_DATE_YEAR(x) (((u_char *)x)[0] + 1900)
-#define HDE_DATE_MONTH(x) (((u_char *)x)[1])
-#define HDE_DATE_DAY(x) (((u_char *)x)[2])
-#define HDE_DATE_HOUR(x) (((u_char *)x)[3])
-#define HDE_DATE_MIN(x) (((u_char *)x)[4])
-#define HDE_DATE_SEC(x) (((u_char *)x)[5])
-
-/* tests for Interchange Levels 1 & 2 file types */
-#define HDE_REGULAR_FILE(x) (((x) & HDE_PROHIBITED) == 0)
-#define HDE_REGULAR_DIR(x) (((x) & HDE_PROHIBITED) == HDE_DIRECTORY)
-
-#define HS_DIR_NAMELEN 31 /* max length of a directory name */
-#define HS_FILE_NAMELEN 31 /* max length of a filename */
-
-#endif /*!_HSFS_SPEC_H_*/
--- a/usr/src/cmd/fs.d/hsfs/fstyp/iso_impl.h Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,137 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License"). You may not use this file except in compliance
- * with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-/*
- * Copyright 2000 Sun Microsystems, Inc. All rights reserved.
- * Use is subject to license terms.
- */
-/**************************************************************************
- *
- * iso_impl.h internal macros for /usr/etc/fs/HSFS/mkproto
- *
- ***************************************************************************/
-
-#pragma ident "%Z%%M% %I% %E% SMI"
-
-/*
- * Macros for counting and rounding.
- */
-#ifdef howmany
-#undef howmany
-#endif
-
-#if defined(sun386) || defined(i386)
-#define howmany(x, y) ((((u_int)(x))+(((u_int)(y))-1))/((u_int)(y)))
-#define roundup(x, y) ((((u_int)(x)+((u_int)(y)-1))/(u_int)(y))*(u_int)(y))
-#else
-#define howmany(x, y) (((x)+((y)-1))/(y))
-#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
-#endif
-
-extern int cdout;
-extern int set_size;
-extern int set_seq;
-extern int blk_size;
-extern int nlbn_per_sec;
-extern char u[], v[];
-extern long unix_voldesc_sec;
-extern int prototype;
-
-#define PUTSECTOR(buf, secno, nosec) (putdisk(buf, (secno)*ISO_SECTOR_SIZE, \
- (nosec)*ISO_SECTOR_SIZE))
-#define GETSECTOR(buf, secno, nosec) (getdisk(buf, (secno)*ISO_SECTOR_SIZE, \
- (nosec)*ISO_SECTOR_SIZE))
-#define PUTLBN(buf, secno, nosec) (putdisk(buf, (secno)*blk_size, \
- (nosec)*blk_size))
-#define GETLBN(buf, lbn, nolbn) (getdisk(buf, (lbn)*blk_size, \
- (nolbn)*blk_size))
-#define LBN_TO_SEC(lbn) ((lbn)/nlbn_per_sec)
-#define SEC_TO_LBN(sec) ((sec)*nlbn_per_sec)
-#define LBN_TO_BYTE(lbn) ((lbn)*blk_size)
-#define BYTE_TO_SEC(byte) (byte/ISO_SECTOR_SIZE)
-
-#define CD_UNIX 0
-#define CD_ISO 1
-
-#define CD_MSB 0
-#define CD_LSB 1
-
-#define CD_REGULAR 1
-#define CD_FILE 2
-#define CD_DIRECTORY 4
-#define CD_DOT 8
-#define CD_DOTDOT 16
-
-#define UNIX_VOLDESC_SEC ISO_VOLDESC_SEC+1
-
-/* internal data structure */
-/* unix file info - to be copied to a cd-rom image */
-struct ufname {
- int fsize; /* size of file in byte */
- char fname[1]; /* file name, should be longer */
-};
-
-/* dlist - individual element of a directory tree */
-struct dlist {
- struct dlist *dnext; /* point to next */
- struct dlist *pdp; /* point to parent */
- struct dlist *cdp; /* point to child */
- struct dlist *ucdp; /* point to first unix child */
- struct dlist *icdp; /* point to first iso child */
- struct dlist *unext; /* pointer to next in UNIX fname order */
- struct dlist *inext; /* pointer to next in ISO fname order */
- struct dlist *idirnext; /* pointer to next dir in iso, breadth first order */
- struct dlist *udirnext; /* pointer to next dir in unix, breadth first order */
- int idno; /* directory number in iso, in breadth first order */
- int udno; /* directory number in unix, in breadth first order */
- int ipoffset; /* offset in iso path table - directory only */
- int upoffset; /* offset in unix path table - directory only */
- int idlbn; /* lbn of parent in iso directory */
- int idoffset; /* offset of parent in iso directory */
- int udlbn; /* lbn of parent in unix directory */
- int udoffset; /* offset of parent in unix directory */
- int idextlbn; /* lbn of extent in iso */
- int udextlbn; /* lbn of extent in unix */
- int idsize; /* iso directory size */
- int udsize; /* unix directory size */
- int extlbn; /* location of the data */
- int fsize; /* size of the data */
- time_t mtime; /* las modification time */
- long duid; /* owner's user id */
- long dgid; /* owner's group id */
- long dmode; /* mode and type of file */
- long nlink; /* no. of links */
- struct ufname *ufnp; /* pointer to the corresponding UNIX file */
- char isofname[32]; /* iso file name */
- char unixfname[1]; /* unix file name, should be longer */
-};
-
-void update_pvd();
-void update_uvd();
-void update_pvd_ptbl();
-void update_uvd_ptbl();
-
-struct dlist * mkdlist();
-struct dlist * mkdlist_proto();
-struct dlist * mkdlist_path();
-void sortdlist();
-
-
--- a/usr/src/cmd/fs.d/hsfs/fstyp/iso_spec.h Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,359 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License"). You may not use this file except in compliance
- * with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-/*
- * Copyright 2000 Sun Microsystems, Inc. All rights reserved.
- * Use is subject to license terms.
- */
-#pragma ident "%Z%%M% %I% %E% SMI"
-
-/*
- * ISO 9660 filesystem specification
- */
-
-#ifndef _ISO_SPEC_H_
-#define _ISO_SPEC_H_
-
-#include <sys/isa_defs.h>
-
-/* routines required for date parsing */
-extern struct timeval iso_parse_dirdate(); /* parse date in directory */
-extern struct timeval iso__parse_longdate(); /* parse date in volume id */
-
-/* macros to parse binary integers */
-#define ZERO(x) (u_int) (((u_char *)(x))[0])
-#define ONE(x) (u_int) (((u_char *)(x))[1])
-#define TWO(x) (u_int) (((u_char *)(x))[2])
-#define THREE(x) (u_int) (((u_char *)(x))[3])
-
-#define MSB_INT(x) \
- ((((((ZERO(x) << 8) | ONE(x)) << 8) | TWO(x)) << 8) | THREE(x))
-#define LSB_INT(x) \
- ((((((THREE(x) << 8) | TWO(x)) << 8) | ONE(x)) << 8) | ZERO(x))
-#define MSB_SHORT(x) ((ZERO(x) << 8) | ONE(x))
-#define LSB_SHORT(x) ((ONE(x) << 8) | ZERO(x))
-
-#if defined(sparc)
-/*
- * Sparc machines requires that integer must
- * be in a full word boundary. CD-ROM data aligns
- * to even word boundary only. Because of this mismatch,
- * we have to move integer data from CD-ROM to memory one
- * byte at a time. LSB data starts first. We therefore
- * use this to do byte by byte copying.
- */
-#define BOTH_SHORT(x) LSB_SHORT(x)
-#define BOTH_INT(x) LSB_INT(x)
-
-#elif defined(_LITTLE_ENDIAN)
-#define BOTH_SHORT(x) (short) *((short *)x)
-#define BOTH_INT(x) (int) *((int *)x)
-
-#elif defined(_BIG_ENDIAN)
-#define BOTH_SHORT(x) (short) *((short *)x + 1)
-#define BOTH_INT(x) (int) *((int *)x + 1)
-#else
-#error One of _BIG_ENDIAN and _LITTLE_ENDIAN must be defined
-#endif
-
-/*
- * conversions to/from little endian format
- */
-#if defined(_LITTLE_ENDIAN)
-/* little endian machines */
-#define ltohs(S) (S)
-#define ltohl(L) (L)
-#define htols(S) (S)
-#define htoll(L) (L)
-#else
-/* big endian machines */
-#define ltohs(S) LSB_SHORT((char *) (S))
-#define ltohl(L) LSB_INT((char *) (L))
-#define htols(S) LSB_SHORT((char *) (S))
-#define htoll(L) LSB_INT((char *) (L))
-#endif
-
-/*
- * The following describes actual on-disk structures.
- * To achieve portability, all structures are #defines
- * rather than a structure definition. Macros are provided
- * to get either the data or address of individual fields.
- */
-
-/* Overall High Sierra disk structure */
-#define ISO_SECTOR_SIZE 2048 /* bytes per logical sector */
-#define ISO_SECTOR_SHIFT 11 /* sector<->byte shift count */
-#define ISO_SEC_PER_PAGE (PAGESIZE/HS_SECTOR_SIZE) /* sectors per page */
-#define ISO_SYSAREA_SEC 0 /* 1st sector of system area */
-#define ISO_VOLDESC_SEC 16 /* 1st sector of volume descriptors */
-#define MAXISOOFFSET (ISO_SECTOR_SIZE - 1)
-#define MAXISOMASK (~MAXISOOFFSET)
-
-
-/* Standard File Structure Volume Descriptor */
-
-enum iso_voldesc_type {
- ISO_VD_BOOT=0, ISO_VD_PVD=1, ISO_VD_SVD=2, ISO_VD_VPD=3,
- ISO_VD_UNIX=4, /* UNIX extension */
- ISO_VD_EOV=255
-};
-#define ISO_ID_STRING "CD001" /* ISO_std_id field */
-#define ISO_ID_STRLEN 5 /* ISO_std_id field length */
-#define ISO_ID_VER 1 /* ISO_std_ver field */
-#define ISO_FILE_STRUCT_ID_VER 1 /* ISO_file structure version field */
-#define ISO_DATE_TO_UNIX(x) iso_parse_longdate(x) /* returns a timeval */
-#define ISO_SYS_ID_STRLEN 32
-#define ISO_VOL_ID_STRLEN 32
-#define ISO_VOL_SET_ID_STRLEN 128
-#define ISO_PUB_ID_STRLEN 128
-#define ISO_PREP_ID_STRLEN 128
-#define ISO_APPL_ID_STRLEN 128
-#define ISO_COPYR_ID_STRLEN 37
-#define ISO_ABSTR_ID_STRLEN 37
-#define ISO_DATE_LEN 17
-
-
-
-/* macros to get the address of each field */
-#define ISO_desc_type(x) (&((u_char *)x)[0])
-#define ISO_std_id(x) (&((u_char *)x)[1])
-#define ISO_std_ver(x) (&((u_char *)x)[6])
-#define ISO_sys_id(x) (&((u_char *)x)[8])
-#define ISO_vol_id(x) (&((u_char *)x)[40])
-#define ISO_vol_size(x) (&((u_char *)x)[80])
-#define ISO_set_size(x) (&((u_char *)x)[120])
-#define ISO_set_seq(x) (&((u_char *)x)[124])
-#define ISO_blk_size(x) (&((u_char *)x)[128])
-#define ISO_ptbl_size(x) (&((u_char *)x)[132])
-#define ISO_ptbl_man_ls(x) (&((u_char *)x)[140])
-#define ISO_ptbl_opt_ls1(x) (&((u_char *)x)[144])
-#define ISO_ptbl_man_ms(x) (&((u_char *)x)[148])
-#define ISO_ptbl_opt_ms1(x) (&((u_char *)x)[152])
-#define ISO_root_dir(x) (&((u_char *)x)[156])
-#define ISO_vol_set_id(x) (&((u_char *)x)[190])
-#define ISO_pub_id(x) (&((u_char *)x)[318])
-#define ISO_prep_id(x) (&((u_char *)x)[446])
-#define ISO_appl_id(x) (&((u_char *)x)[574])
-#define ISO_copyr_id(x) (&((u_char *)x)[702])
-#define ISO_abstr_id(x) (&((u_char *)x)[739])
-#define ISO_bibli_id(x) (&((u_char *)x)[776])
-#define ISO_cre_date(x) (&((u_char *)x)[813])
-#define ISO_mod_date(x) (&((u_char *)x)[830])
-#define ISO_exp_date(x) (&((u_char *)x)[847])
-#define ISO_eff_date(x) (&((u_char *)x)[864])
-#define ISO_file_struct_ver(x) (&((u_char *)x)[881])
-
-/* macros to get the values of each field (strings are returned as ptrs) */
-#define ISO_DESC_TYPE(x) ((enum hs_voldesc_type)*(ISO_desc_type(x)))
-#define ISO_STD_ID(x) ISO_std_id(x)
-#define ISO_STD_VER(x) *(ISO_std_ver(x))
-#define ISO_SYS_ID(x) ISO_sys_id(x)
-#define ISO_VOL_ID(x) ISO_vol_id(x)
-#define ISO_VOL_SIZE(x) BOTH_INT(ISO_vol_size(x))
-#define ISO_SET_SIZE(x) BOTH_SHORT(ISO_set_size(x))
-#define ISO_SET_SEQ(x) BOTH_SHORT(ISO_set_seq(x))
-#define ISO_BLK_SIZE(x) BOTH_SHORT(ISO_blk_size(x))
-#define ISO_PTBL_SIZE(x) BOTH_INT(ISO_ptbl_size(x))
-#define ISO_PTBL_MAN_LS(x) LSB_INT(ISO_ptbl_man_ls(x))
-#define ISO_PTBL_OPT_LS1(x) LSB_INT(ISO_ptbl_opt_ls1(x))
-#define ISO_PTBL_MAN_MS(x) MSB_INT(ISO_ptbl_man_ms(x))
-#define ISO_PTBL_OPT_MS1(x) MSB_INT(ISO_ptbl_opt_ms1(x))
-#define ISO_ROOT_DIR(x) ISO_root_dir(x)
-#define ISO_VOL_SET_ID(x) ISO_vol_set_id(x)
-#define ISO_PUB_ID(x) ISO_pub_id(x)
-#define ISO_PREP_ID(x) ISO_prep_id(x)
-#define ISO_APPL_ID(x) ISO_appl_id(x)
-#define ISO_COPYR_ID(x) ISO_copyr_id(x)
-#define ISO_ABSTR_ID(x) ISO_abstr_id(x)
-#define ISO_BIBLI_ID(x) ISO_bibli_id(x)
-#define ISO_CRE_DATE(x) ISO_DATE_TO_UNIX(HSV_cre_date(x))
-#define ISO_MOD_DATE(x) ISO_DATE_TO_UNIX(HSV_mod_date(x))
-#define ISO_EXP_DATE(x) ISO_DATE_TO_UNIX(HSV_exp_date(x))
-#define ISO_EFF_DATE(x) ISO_DATE_TO_UNIX(HSV_eff_date(x))
-#define ISO_FILE_STRUCT_VER(x) *(ISO_file_struct_ver(x))
-
-/* Standard File Structure Volume Descriptor date fields */
-#define ISO_DATE_2DIG(x) ( (((x)[0] - '0') * 10) + \
- ((x)[1] - '0') )
-#define ISO_DATE_4DIG(x) ( (((x)[0] - '0') * 1000) + \
- (((x)[1] - '0') * 100) + \
- (((x)[2] - '0') * 10) + \
- ((x)[3] - '0') )
-#define ISO_DATE_YEAR(x) ISO_DATE_4DIG(&((u_char *)x)[0])
-#define ISO_DATE_MONTH(x) ISO_DATE_2DIG(&((u_char *)x)[4])
-#define ISO_DATE_DAY(x) ISO_DATE_2DIG(&((u_char *)x)[6])
-#define ISO_DATE_HOUR(x) ISO_DATE_2DIG(&((u_char *)x)[8])
-#define ISO_DATE_MIN(x) ISO_DATE_2DIG(&((u_char *)x)[10])
-#define ISO_DATE_SEC(x) ISO_DATE_2DIG(&((u_char *)x)[12])
-#define ISO_DATE_HSEC(x) ISO_DATE_2DIG(&((u_char *)x)[14])
-
-
-
-/* Directory Entry (Directory Record) */
-#define IDE_ROOT_DIR_REC_SIZE 34 /* size of root directory record */
-#define IDE_FDESIZE 33 /* fixed size for hsfs directory area */
- /* max size of a name */
-#define IDE_MAX_NAME_LEN (255 - IDE_FDESIZE)
-
-
-#define IDE_DATE_TO_UNIX(x) iso_parse_dirdate(x) /* returns a timeval */
-
-/* macros to get the address of each field */
-#define IDE_dir_len(x) (&((u_char *)x)[0])
-#define IDE_xar_len(x) (&((u_char *)x)[1])
-#define IDE_ext_lbn(x) (&((u_char *)x)[2])
-#define IDE_ext_size(x) (&((u_char *)x)[10])
-#define IDE_cdate(x) (&((u_char *)x)[18])
-#define IDE_flags(x) (&((u_char *)x)[25])
-#define IDE_intrlv_size(x) (&((u_char *)x)[26])
-#define IDE_intrlv_skip(x) (&((u_char *)x)[27])
-#define IDE_vol_set(x) (&((u_char *)x)[28])
-#define IDE_name_len(x) (&((u_char *)x)[32])
-#define IDE_name(x) (&((u_char *)x)[33])
-
-/* macros to get the values of each field (strings are returned as ptrs) */
-#define IDE_DIR_LEN(x) *(IDE_dir_len(x))
-#define IDE_XAR_LEN(x) *(IDE_xar_len(x))
-#define IDE_EXT_LBN(x) BOTH_INT(IDE_ext_lbn(x))
-#define IDE_EXT_SIZE(x) BOTH_INT(IDE_ext_size(x))
-#define IDE_CDATE(x) IDE_DATE_TO_UNIX(HDE_cdate(x))
-#define IDE_FLAGS(x) *(IDE_flags(x))
-#define IDE_INTRLV_SIZE(x) *(IDE_intrlv_size(x))
-#define IDE_INTRLV_SKIP(x) *(IDE_intrlv_skip(x))
-#define IDE_VOL_SET(x) BOTH_SHORT(IDE_vol_set(x))
-#define IDE_NAME_LEN(x) *(IDE_name_len(x))
-#define IDE_NAME(x) IDE_name(x)
-
-/* mask bits for IDE_FLAGS */
-#define IDE_EXISTENCE 0x01 /* zero if file exists */
-#define IDE_DIRECTORY 0x02 /* zero if file is not a directory */
-#define IDE_ASSOCIATED 0x04 /* zero if file is not Associated */
-#define IDE_RECORD 0x08 /* zero if no record attributes */
-#define IDE_PROTECTION 0x10 /* zero if no protection attributes */
-#define IDE_UNUSED_FLAGS 0x60
-#define IDE_LAST_EXTENT 0x80 /* zero if last extent in file */
-#define IDE_PROHIBITED (IDE_DIRECTORY | HDE_ASSOCIATED | HDE_RECORD | \
- IDE_LAST_EXTENT | IDE_UNUSED_FLAGS)
-
-/* Directory Record date fields */
-#define IDE_DATE_YEAR(x) (((u_char *)x)[0] + 1900)
-#define IDE_DATE_MONTH(x) (((u_char *)x)[1])
-#define IDE_DATE_DAY(x) (((u_char *)x)[2])
-#define IDE_DATE_HOUR(x) (((u_char *)x)[3])
-#define IDE_DATE_MIN(x) (((u_char *)x)[4])
-#define IDE_DATE_SEC(x) (((u_char *)x)[5])
-
-/* tests for Interchange Levels 1 & 2 file types */
-#define IDE_REGULAR_FILE(x) (((x) & IDE_PROHIBITED) == 0)
-#define IDE_REGULAR_DIR(x) (((x) & IDE_PROHIBITED) == IDE_DIRECTORY)
-
-#define ISO_DIR_NAMELEN 31 /* max length of a directory name */
-#define ISO_FILE_NAMELEN 31 /* max length of a filename */
-
-/* Path table enry */
-/* fix size of path table entry */
-#define IPE_FPESIZE 8
-/* macros to get the address of each field */
-#define IPE_name_len(x) (&((u_char *)x)[0])
-#define IPE_xar_len(x) (&((u_char *)x)[1])
-#define IPE_ext_lbn(x) (&((u_char *)x)[2])
-#define IPE_parent_no(x) (&((u_char *)x)[6])
-#define IPE_name(x) (&((u_char *)x)[8])
-
-/* macros to get the values of each field */
-#define IPE_EXT_LBN(x) (MSB_INT(IPE_ext_lbn(x)))
-#define IPE_XAR_LEN(x) *(IPE_xar_len(x))
-#define IPE_NAME_LEN(x) *(IPE_name_len(x))
-#define IPE_PARENT_NO(x) *(short *)(IPE_parent_no(x))
-#define IPE_NAME(x) IPE_name(x)
-
-/* cdrom UNIX extension */
-/* UNIX Volume Descriptor */
-#define ISO_UNIX_ID_STRING "UNIXCD01" /* ISO_UNIX_std_id field */
-#define ISO_UNIX_ID_STRLEN 8 /* ISO_UNIX_std_id length */
-#define ISO_UNIX_FEATURE_SYMLNK 0x01 /* CD-ROM supports symbolic links */
-#define ISO_UNIX_FEATURE_LONGFN 0x02 /* CD-ROM supports long BSD file names */
-
-#define ISO_UNIX_feature(x) (&((u_char *)x)[7])
-#define ISO_UNIX_root_dir(x) (&((u_char *)x)[1395])
-#define ISO_UNIX_signature(x) (&((u_char *)x)[2040])
-
-#define ISO_UNIX_FEATURE(x) *(ISO_UNIX_feature(x))
-#define ISO_UNIX_ROOT_DIR(x) ISO_UNIX_root_dir(x)
-#define ISO_UNIX_SIGNATURE(x) ISO_UNIX_signature(x)
-
-/* UNIX extension to path table entry */
-/* fix size of path table entry */
-#define IPE_UNIX_FPESIZE 20
-
-#define IPE_UNIX_mode(x) (&((u_char *)x)[0])
-#define IPE_UNIX_uid(x) (&((u_char *)x)[4])
-#define IPE_UNIX_gid(x) (&((u_char *)x)[8])
-
-/* macros to get the values of each field */
-#define IPE_UNIX_MODE(x) (MSB_INT(IPE_UNIX_mode(x)))
-#define IPE_UNIX_UID(x) (MSB_INT(IPE_UNIX_uid(x)))
-#define IPE_UNIX_GID(x) (MSB_INT(IPE_UNIX_gid(x)))
-
-/* UNIX extension to directory entry */
-#define IDE_UNIX_SIG_UX "UX" /* UNIX extension signature */
-#define IDE_UNIX_SIG_TI "TI" /* UNIX extension signature for time */
-#define IDE_UNIX_USE_ID_VER 1 /* UNIX extension sys use id */
-#define IDE_UNIX_UX_LEN 36 /* length of UX */
-#define IDE_UNIX_TI_LEN 40 /* length of TI */
-
-#define IDE_UNIX_signature(x) (&((u_char *)x)[0])
-#define IDE_UNIX_ext_len(x) (&((u_char *)x)[2])
-#define IDE_UNIX_use_id(x) (&((u_char *)x)[3])
-#define IDE_UNIX_mode(x) (&((u_char *)x)[4])
-#define IDE_UNIX_nlink(x) (&((u_char *)x)[12])
-#define IDE_UNIX_uid(x) (&((u_char *)x)[20])
-#define IDE_UNIX_gid(x) (&((u_char *)x)[28])
-
-
-#define IDE_UNIX_cre_date(x) (&((u_char *)x)[4])
-#define IDE_UNIX_mod_date(x) (&((u_char *)x)[11])
-#define IDE_UNIX_exp_date(x) (&((u_char *)x)[18])
-#define IDE_UNIX_eff_date(x) (&((u_char *)x)[25])
-#define IDE_UNIX_acc_date(x) (&((u_char *)x)[32])
-#define IDE_UNIX_reserved(x) (&((u_char *)x)[39])
-
-#define IDE_UNIX_SIGNATURE(x) IDE_UNIX_signature(x)
-#define IDE_UNIX_EXT_LEN(x) *(IDE_UNIX_ext_len(x))
-#define IDE_UNIX_USE_ID(x) *(IDE_UNIX_use_id(x))
-#define IDE_UNIX_MODE(x) BOTH_INT(IDE_UNIX_mode(x))
-#define IDE_UNIX_NLINK(x) BOTH_INT(IDE_UNIX_nlink(x))
-#define IDE_UNIX_UID(x) BOTH_INT(IDE_UNIX_uid(x))
-#define IDE_UNIX_GID(x) BOTH_INT(IDE_UNIX_gid(x))
-
-#define IDE_UNIX_CRE_DATE(x) IDE_UNIX_cre_date(x)
-#define IDE_UNIX_MOD_DATE(x) IDE_UNIX_mod_date(x)
-#define IDE_UNIX_EXP_DATE(x) IDE_UNIX_exp_date(x)
-#define IDE_UNIX_EFF_DATE(x) IDE_UNIX_eff_date(x)
-#define IDE_UNIX_ACC_DATE(x) IDE_UNIX_acc_date(x)
-#define IDE_UNIX_RESERVED(x) *(IDE_UNIX_reserved(x))
-
-/* root record */
-/* size of root directory record */
-#define IDE_UNIX_ROOT_DIR_REC_SIZE 34+IDE_UNIX_UX_LEN
-#define IDE_UNIX_MAX_NAME_LEN IDE_MAX_NAME_LEN - IDE_UNIX_UX_LEN
-
-#endif /*!_ISO_SPEC_H_*/
--- a/usr/src/cmd/fs.d/hsfs/labelit/hsfs_spec.h Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,269 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License"). You may not use this file except in compliance
- * with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-#pragma ident "%Z%%M% %I% %E% SMI"
-
-/*
- * High Sierra filesystem specification
- * Copyright (c) 1989 by Sun Microsystem, Inc.
- */
-
-#ifndef _HSFS_SPEC_H_
-#define _HSFS_SPEC_H_
-
-#include <sys/isa_defs.h> /* for ENDIAN defines */
-
-/* routines required for date parsing */
-extern void hs_parse_dirdate(); /* parse date in directory */
-extern void hs_parse_longdate(); /* parse date in volume id */
-
-/* macros to parse binary integers */
-#define ZERO(x) (u_int) (((u_char *)(x))[0])
-#define ONE(x) (u_int) (((u_char *)(x))[1])
-#define TWO(x) (u_int) (((u_char *)(x))[2])
-#define THREE(x) (u_int) (((u_char *)(x))[3])
-
-#define MSB_INT(x) \
- ((((((ZERO(x) << 8) | ONE(x)) << 8) | TWO(x)) << 8) | THREE(x))
-#define LSB_INT(x) \
- ((((((THREE(x) << 8) | TWO(x)) << 8) | ONE(x)) << 8) | ZERO(x))
-#define MSB_SHORT(x) ((ZERO(x) << 8) | ONE(x))
-#define LSB_SHORT(x) ((ONE(x) << 8) | ZERO(x))
-
-/* for sun 3 only */
-#if defined(_LITTLE_ENDIAN)
-#define BOTH_SHORT(x) (short) *((short *)x)
-#define BOTH_INT(x) (int) *((int *)x)
-#endif
-
-/*
- * The following describes actual on-disk structures.
- * To achieve portability, all structures are #defines
- * rather than a structure definition. Macros are provided
- * to get either the data or address of individual fields.
- */
-
-/* Overall High Sierra disk structure */
-#define HS_SECTOR_SIZE 2048 /* bytes per logical sector */
-#define HS_SECTOR_SHIFT 11 /* sector<->byte shift count */
-#define HS_SEC_PER_PAGE (PAGESIZE/HS_SECTOR_SIZE) /* sectors per page */
-#define HS_SYSAREA_SEC 0 /* 1st sector of system area */
-#define HS_VOLDESC_SEC 16 /* 1st sector of volume descriptors */
-#define MAXHSOFFSET (HS_SECTOR_SIZE - 1)
-#define MAXHSMASK (~MAXHSOFFSET)
-
-/* Standard File Structure Volume Descriptor */
-
-enum hs_voldesc_type {
- VD_BOOT=0, VD_SFS=1, VD_CCFS=2, VD_UNSPEC=3, VD_EOV=255
-};
-#define HSV_ID_STRING "CDROM" /* HSV_std_id field */
-#define HSV_ID_STRLEN 5 /* HSV_std_id field length */
-#define HSV_ID_VER 1 /* HSV_std_ver field */
-#define HSV_FILE_STRUCT_ID_VER 1 /* HSV_file_struct_ver field */
-#define HSV_SYS_ID_STRLEN 32 /* HSV_sys_id field length */
-#define HSV_VOL_ID_STRLEN 32 /* HSV_vol_id field length */
-#define HSV_VOL_SET_ID_STRLEN 128 /* HSV_vol_set_id field length */
-#define HSV_PUB_ID_STRLEN 128 /* HSV_pub_id field length */
-#define HSV_PREP_ID_STRLEN 128 /* HSV_prep_id field length */
-#define HSV_APPL_ID_STRLEN 128 /* HSV_appl_id field length */
-#define HSV_COPYR_ID_STRLEN 32 /* HSV_copyr_id field length */
-#define HSV_ABSTR_ID_STRLEN 32 /* HSV_abstr_id field length */
-#define HSV_DATE_LEN 16 /* HSV date filed length */
-
-/* macros to get the address of each field */
-#define HSV_desc_lbn(x) (&((u_char *)x)[0])
-#define HSV_desc_type(x) (&((u_char *)x)[8])
-#define HSV_std_id(x) (&((u_char *)x)[9])
-#define HSV_std_ver(x) (&((u_char *)x)[14])
-#define HSV_sys_id(x) (&((u_char *)x)[16])
-#define HSV_vol_id(x) (&((u_char *)x)[48])
-#define HSV_vol_size(x) (&((u_char *)x)[88])
-#define HSV_set_size(x) (&((u_char *)x)[128])
-#define HSV_set_seq(x) (&((u_char *)x)[132])
-#define HSV_blk_size(x) (&((u_char *)x)[136])
-#define HSV_ptbl_size(x) (&((u_char *)x)[140])
-#define HSV_ptbl_man_ls(x) (&((u_char *)x)[148])
-#define HSV_ptbl_opt_ls1(x) (&((u_char *)x)[152])
-#define HSV_ptbl_opt_ls2(x) (&((u_char *)x)[156])
-#define HSV_ptbl_opt_ls3(x) (&((u_char *)x)[160])
-#define HSV_ptbl_man_ms(x) (&((u_char *)x)[164])
-#define HSV_ptbl_opt_ms1(x) (&((u_char *)x)[168])
-#define HSV_ptbl_opt_ms2(x) (&((u_char *)x)[172])
-#define HSV_ptbl_opt_ms3(x) (&((u_char *)x)[176])
-#define HSV_root_dir(x) (&((u_char *)x)[180])
-#define HSV_vol_set_id(x) (&((u_char *)x)[214])
-#define HSV_pub_id(x) (&((u_char *)x)[342])
-#define HSV_prep_id(x) (&((u_char *)x)[470])
-#define HSV_appl_id(x) (&((u_char *)x)[598])
-#define HSV_copyr_id(x) (&((u_char *)x)[726])
-#define HSV_abstr_id(x) (&((u_char *)x)[758])
-#define HSV_cre_date(x) (&((u_char *)x)[790])
-#define HSV_mod_date(x) (&((u_char *)x)[806])
-#define HSV_exp_date(x) (&((u_char *)x)[822])
-#define HSV_eff_date(x) (&((u_char *)x)[838])
-#define HSV_file_struct_ver(x) (&((u_char *)x)[854])
-
-/* macros to get the values of each field (strings are returned as ptrs) */
-#define HSV_DESC_LBN(x) BOTH_INT(HSV_desc_lbn(x))
-#define HSV_DESC_TYPE(x) ((enum hs_voldesc_type)*(HSV_desc_type(x)))
-#define HSV_STD_ID(x) HSV_std_id(x)
-#define HSV_STD_VER(x) *(HSV_std_ver(x))
-#define HSV_SYS_ID(x) HSV_sys_id(x)
-#define HSV_VOL_ID(x) HSV_vol_id(x)
-#define HSV_VOL_SIZE(x) BOTH_INT(HSV_vol_size(x))
-#define HSV_SET_SIZE(x) BOTH_SHORT(HSV_set_size(x))
-#define HSV_SET_SEQ(x) BOTH_SHORT(HSV_set_seq(x))
-#define HSV_BLK_SIZE(x) BOTH_SHORT(HSV_blk_size(x))
-#define HSV_PTBL_SIZE(x) BOTH_INT(HSV_ptbl_size(x))
-#define HSV_PTBL_MAN_LS(x) LSB_INT(HSV_ptbl_man_ls(x))
-#define HSV_PTBL_OPT_LS1(x) LSB_INT(HSV_ptbl_opt_ls1(x))
-#define HSV_PTBL_OPT_LS2(x) LSB_INT(HSV_ptbl_opt_ls2(x))
-#define HSV_PTBL_OPT_LS3(x) LSB_INT(HSV_ptbl_opt_ls3(x))
-#define HSV_PTBL_MAN_MS(x) MSB_INT(HSV_ptbl_man_ms(x))
-#define HSV_PTBL_OPT_MS1(x) MSB_INT(HSV_ptbl_opt_ms1(x))
-#define HSV_PTBL_OPT_MS2(x) MSB_INT(HSV_ptbl_opt_ms2(x))
-#define HSV_PTBL_OPT_MS3(x) MSB_INT(HSV_ptbl_opt_ms3(x))
-#define HSV_ROOT_DIR(x) HSV_root_dir(x)
-#define HSV_VOL_SET_ID(x) HSV_vol_set_id(x)
-#define HSV_PUB_ID(x) HSV_pub_id(x)
-#define HSV_PREP_ID(x) HSV_prep_id(x)
-#define HSV_APPL_ID(x) HSV_appl_id(x)
-#define HSV_COPYR_ID(x) HSV_copyr_id(x)
-#define HSV_ABSTR_ID(x) HSV_abstr_id(x)
-#define HSV_CRE_DATE(x) HSV_cre_date(x)
-#define HSV_MOD_DATE(x) HSV_mod_date(x)
-#define HSV_EXP_DATE(x) HSV_exp_date(x)
-#define HSV_EFF_DATE(x) HSV_eff_date(x)
-#define HSV_FILE_STRUCT_VER(x) *(HSV_file_struct_ver(x))
-
-/* Standard File Structure Volume Descriptor date fields */
-#define HSV_DATE_2DIG(x) ( (((x)[0] - '0') * 10) + \
- ((x)[1] - '0') )
-#define HSV_DATE_4DIG(x) ( (((x)[0] - '0') * 1000) + \
- (((x)[1] - '0') * 100) + \
- (((x)[2] - '0') * 10) + \
- ((x)[3] - '0') )
-#define HSV_DATE_YEAR(x) HSV_DATE_4DIG(&((u_char *)x)[0])
-#define HSV_DATE_MONTH(x) HSV_DATE_2DIG(&((u_char *)x)[4])
-#define HSV_DATE_DAY(x) HSV_DATE_2DIG(&((u_char *)x)[6])
-#define HSV_DATE_HOUR(x) HSV_DATE_2DIG(&((u_char *)x)[8])
-#define HSV_DATE_MIN(x) HSV_DATE_2DIG(&((u_char *)x)[10])
-#define HSV_DATE_SEC(x) HSV_DATE_2DIG(&((u_char *)x)[12])
-#define HSV_DATE_HSEC(x) HSV_DATE_2DIG(&((u_char *)x)[14])
-
-/* Path table enry */
-/* fix size of path table entry */
-#define HPE_FPESIZE 8
-/* macros to get the address of each field */
-#define HPE_ext_lbn(x) (&((u_char *)x)[0])
-#define HPE_xar_len(x) (&((u_char *)x)[4])
-#define HPE_name_len(x) (&((u_char *)x)[5])
-#define HPE_parent_no(x) (&((u_char *)x)[6])
-#define HPE_name(x) (&((u_char *)x)[8])
-
-/* macros to get the values of each field */
-#if sun4
-#define HPE_EXT_LBN(x) (MSB_INT(HPE_ext_lbn(x)))
-#else
-#define HPE_EXT_LBN(x) *(int *)(HPE_ext_lbn(x))
-#endif
-#define HPE_XAR_LEN(x) *(HPE_xar_len(x))
-#define HPE_NAME_LEN(x) *(HPE_name_len(x))
-#define HPE_PARENT_NO(x) *(short *)(HPE_parent_no(x))
-#define HPE_NAME(x) HPE_name(x)
-
-/* root record */
-#define HDE_ROOT_DIR_REC_SIZE 34 /* size of root directory record */
-#define HDE_FDESIZE 33 /* fixed size for hsfs directory area */
-#define HDE_FUSIZE 12 /* fixed size for unix areaa */
- /* max size of a name */
-#define HDE_MAX_NAME_LEN (255 - HDE_FDESIZE - HDE_FUSIZE)
-
-/* Directory Entry (Directory Record) */
-
-#define UNIX_TO_HDE_DATE(t,p) parse_unixdate(t, p) /* return val at p */
-
-/* macros to get the address of each field */
-#define HDE_dir_len(x) (&((u_char *)x)[0])
-#define HDE_xar_len(x) (&((u_char *)x)[1])
-#define HDE_ext_lbn(x) (&((u_char *)x)[2])
-#define HDE_ext_size(x) (&((u_char *)x)[10])
-#define HDE_cdate(x) (&((u_char *)x)[18])
-#define HDE_flags(x) (&((u_char *)x)[24])
-#define HDE_reserved(x) (&((u_char *)x)[25])
-#define HDE_intrlv_size(x) (&((u_char *)x)[26])
-#define HDE_intrlv_skip(x) (&((u_char *)x)[27])
-#define HDE_vol_set(x) (&((u_char *)x)[28])
-#define HDE_name_len(x) (&((u_char *)x)[32])
-#define HDE_name(x) (&((u_char *)x)[33])
-
-/***UNIX extension****/
-#define HDE_mode(x) (&((u_char *)x)[0])
-#define HDE_uid(x) (&((u_char *)x)[4])
-#define HDE_gid(x) (&((u_char *)x)[8])
-
-/* macros to get the values of each field (strings are returned as ptrs) */
-#define HDE_DIR_LEN(x) *(HDE_dir_len(x))
-#define HDE_XAR_LEN(x) *(HDE_xar_len(x))
-#define HDE_EXT_LBN(x) BOTH_INT(HDE_ext_lbn(x))
-#define HDE_EXT_SIZE(x) BOTH_INT(HDE_ext_size(x))
-#define HDE_CDATE(x) HDE_cdate(x)
-#define HDE_FLAGS(x) *(HDE_flags(x))
-#define HDE_RESERVED(x) *(HDE_reserved(x))
-#define HDE_INTRLV_SIZE(x) *(HDE_intrlv_size(x))
-#define HDE_INTRLV_SKIP(x) *(HDE_intrlv_skip(x))
-#define HDE_VOL_SET(x) BOTH_SHORT(HDE_vol_set(x))
-#define HDE_NAME_LEN(x) *(HDE_name_len(x))
-#define HDE_NAME(x) HDE_name(x)
-
-/***UNIX EXTENSION*****/
-#define HDE_MODE(x) *(HDE_mode(x))
-#define HDE_UID(x) *(HDE_uid(x))
-#define HDE_GID(x) *(HDE_gid(x))
-
-/* mask bits for HDE_FLAGS */
-#define HDE_EXISTENCE 0x01 /* zero if file exists */
-#define HDE_DIRECTORY 0x02 /* zero if file is not a directory */
-#define HDE_ASSOCIATED 0x04 /* zero if file is not Associated */
-#define HDE_RECORD 0x08 /* zero if no record attributes */
-#define HDE_PROTECTION 0x10 /* zero if no protection attributes */
-#define HDE_UNUSED_FLAGS 0x60
-#define HDE_LAST_EXTENT 0x80 /* zero if last extent in file */
-#define HDE_PROHIBITED (HDE_DIRECTORY | HDE_ASSOCIATED | HDE_RECORD | \
- HDE_LAST_EXTENT | HDE_UNUSED_FLAGS)
-
-/* Directory Record date fields */
-#define HDE_DATE_YEAR(x) (((u_char *)x)[0] + 1900)
-#define HDE_DATE_MONTH(x) (((u_char *)x)[1])
-#define HDE_DATE_DAY(x) (((u_char *)x)[2])
-#define HDE_DATE_HOUR(x) (((u_char *)x)[3])
-#define HDE_DATE_MIN(x) (((u_char *)x)[4])
-#define HDE_DATE_SEC(x) (((u_char *)x)[5])
-
-/* tests for Interchange Levels 1 & 2 file types */
-#define HDE_REGULAR_FILE(x) (((x) & HDE_PROHIBITED) == 0)
-#define HDE_REGULAR_DIR(x) (((x) & HDE_PROHIBITED) == HDE_DIRECTORY)
-
-#define HS_DIR_NAMELEN 31 /* max length of a directory name */
-#define HS_FILE_NAMELEN 31 /* max length of a filename */
-
-#endif /*!_HSFS_SPEC_H_*/
--- a/usr/src/cmd/fs.d/hsfs/labelit/iso_impl.h Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,137 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License"). You may not use this file except in compliance
- * with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-/*
- * Copyright 2000 Sun Microsystems, Inc. All rights reserved.
- * Use is subject to license terms.
- */
-/**************************************************************************
- *
- * iso_impl.h internal macros for /usr/etc/fs/HSFS/mkproto
- *
- ***************************************************************************/
-
-#pragma ident "%Z%%M% %I% %E% SMI"
-
-/*
- * Macros for counting and rounding.
- */
-#ifdef howmany
-#undef howmany
-#endif
-
-#if defined(sun386) || defined(i386)
-#define howmany(x, y) ((((u_int)(x))+(((u_int)(y))-1))/((u_int)(y)))
-#define roundup(x, y) ((((u_int)(x)+((u_int)(y)-1))/(u_int)(y))*(u_int)(y))
-#else
-#define howmany(x, y) (((x)+((y)-1))/(y))
-#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
-#endif
-
-extern int cdout;
-extern int set_size;
-extern int set_seq;
-extern int blk_size;
-extern int nlbn_per_sec;
-extern char u[], v[];
-extern long unix_voldesc_sec;
-extern int prototype;
-
-#define PUTSECTOR(buf, secno, nosec) (putdisk(buf, (secno)*ISO_SECTOR_SIZE, \
- (nosec)*ISO_SECTOR_SIZE))
-#define GETSECTOR(buf, secno, nosec) (getdisk(buf, (secno)*ISO_SECTOR_SIZE, \
- (nosec)*ISO_SECTOR_SIZE))
-#define PUTLBN(buf, secno, nosec) (putdisk(buf, (secno)*blk_size, \
- (nosec)*blk_size))
-#define GETLBN(buf, lbn, nolbn) (getdisk(buf, (lbn)*blk_size, \
- (nolbn)*blk_size))
-#define LBN_TO_SEC(lbn) ((lbn)/nlbn_per_sec)
-#define SEC_TO_LBN(sec) ((sec)*nlbn_per_sec)
-#define LBN_TO_BYTE(lbn) ((lbn)*blk_size)
-#define BYTE_TO_SEC(byte) (byte/ISO_SECTOR_SIZE)
-
-#define CD_UNIX 0
-#define CD_ISO 1
-
-#define CD_MSB 0
-#define CD_LSB 1
-
-#define CD_REGULAR 1
-#define CD_FILE 2
-#define CD_DIRECTORY 4
-#define CD_DOT 8
-#define CD_DOTDOT 16
-
-#define UNIX_VOLDESC_SEC ISO_VOLDESC_SEC+1
-
-/* internal data structure */
-/* unix file info - to be copied to a cd-rom image */
-struct ufname {
- int fsize; /* size of file in byte */
- char fname[1]; /* file name, should be longer */
-};
-
-/* dlist - individual element of a directory tree */
-struct dlist {
- struct dlist *dnext; /* point to next */
- struct dlist *pdp; /* point to parent */
- struct dlist *cdp; /* point to child */
- struct dlist *ucdp; /* point to first unix child */
- struct dlist *icdp; /* point to first iso child */
- struct dlist *unext; /* pointer to next in UNIX fname order */
- struct dlist *inext; /* pointer to next in ISO fname order */
- struct dlist *idirnext; /* pointer to next dir in iso, breadth first order */
- struct dlist *udirnext; /* pointer to next dir in unix, breadth first order */
- int idno; /* directory number in iso, in breadth first order */
- int udno; /* directory number in unix, in breadth first order */
- int ipoffset; /* offset in iso path table - directory only */
- int upoffset; /* offset in unix path table - directory only */
- int idlbn; /* lbn of parent in iso directory */
- int idoffset; /* offset of parent in iso directory */
- int udlbn; /* lbn of parent in unix directory */
- int udoffset; /* offset of parent in unix directory */
- int idextlbn; /* lbn of extent in iso */
- int udextlbn; /* lbn of extent in unix */
- int idsize; /* iso directory size */
- int udsize; /* unix directory size */
- int extlbn; /* location of the data */
- int fsize; /* size of the data */
- time_t mtime; /* las modification time */
- long duid; /* owner's user id */
- long dgid; /* owner's group id */
- long dmode; /* mode and type of file */
- long nlink; /* no. of links */
- struct ufname *ufnp; /* pointer to the corresponding UNIX file */
- char isofname[32]; /* iso file name */
- char unixfname[1]; /* unix file name, should be longer */
-};
-
-void update_pvd();
-void update_uvd();
-void update_pvd_ptbl();
-void update_uvd_ptbl();
-
-struct dlist * mkdlist();
-struct dlist * mkdlist_proto();
-struct dlist * mkdlist_path();
-void sortdlist();
-
-
--- a/usr/src/cmd/fs.d/hsfs/labelit/iso_spec.h Sat Jun 30 11:33:30 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,359 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License"). You may not use this file except in compliance
- * with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-/*
- * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
- * Use is subject to license terms.
- */
-#pragma ident "%Z%%M% %I% %E% SMI"
-
-/*
- * ISO 9660 filesystem specification
- */
-
-#ifndef _ISO_SPEC_H_
-#define _ISO_SPEC_H_
-
-#include <sys/isa_defs.h>
-
-/* routines required for date parsing */
-extern struct timeval iso_parse_dirdate(); /* parse date in directory */
-extern struct timeval iso__parse_longdate(); /* parse date in volume id */
-
-/* macros to parse binary integers */
-#define ZERO(x) (u_int) (((u_char *)(x))[0])
-#define ONE(x) (u_int) (((u_char *)(x))[1])
-#define TWO(x) (u_int) (((u_char *)(x))[2])
-#define THREE(x) (u_int) (((u_char *)(x))[3])
-
-#define MSB_INT(x) \
- ((((((ZERO(x) << 8) | ONE(x)) << 8) | TWO(x)) << 8) | THREE(x))
-#define LSB_INT(x) \
- ((((((THREE(x) << 8) | TWO(x)) << 8) | ONE(x)) << 8) | ZERO(x))
-#define MSB_SHORT(x) ((ZERO(x) << 8) | ONE(x))
-#define LSB_SHORT(x) ((ONE(x) << 8) | ZERO(x))
-
-#if defined(sparc)
-/*
- * Sparc machines requires that integer must
- * be in a full word boundary. CD-ROM data aligns
- * to even word boundary only. Because of this mismatch,
- * we have to move integer data from CD-ROM to memory one
- * byte at a time. LSB data starts first. We therefore
- * use this to do byte by byte copying.
- */
-#define BOTH_SHORT(x) LSB_SHORT(x)
-#define BOTH_INT(x) LSB_INT(x)
-
-#elif defined(_LITTLE_ENDIAN)
-#define BOTH_SHORT(x) (short) *((short *)x)
-#define BOTH_INT(x) (int) *((int *)x)
-
-#elif defined(_BIG_ENDIAN)
-#define BOTH_SHORT(x) (short) *((short *)x + 1)
-#define BOTH_INT(x) (int) *((int *)x + 1)
-#else
-#error One of _BIG_ENDIAN and _LITTLE_ENDIAN must be defined
-#endif
-
-/*
- * conversions to/from little endian format
- */
-#if defined(_LITTLE_ENDIAN)
-/* little endian machines */
-#define ltohs(S) (S)
-#define ltohl(L) (L)
-#define htols(S) (S)
-#define htoll(L) (L)
-#else
-/* big endian machines */
-#define ltohs(S) LSB_SHORT((char *) (S))
-#define ltohl(L) LSB_INT((char *) (L))
-#define htols(S) LSB_SHORT((char *) (S))
-#define htoll(L) LSB_INT((char *) (L))
-#endif
-
-/*
- * The following describes actual on-disk structures.
- * To achieve portability, all structures are #defines
- * rather than a structure definition. Macros are provided
- * to get either the data or address of individual fields.
- */
-
-/* Overall High Sierra disk structure */
-#define ISO_SECTOR_SIZE 2048 /* bytes per logical sector */
-#define ISO_SECTOR_SHIFT 11 /* sector<->byte shift count */
-#define ISO_SEC_PER_PAGE (PAGESIZE/HS_SECTOR_SIZE) /* sectors per page */
-#define ISO_SYSAREA_SEC 0 /* 1st sector of system area */
-#define ISO_VOLDESC_SEC 16 /* 1st sector of volume descriptors */
-#define MAXISOOFFSET (ISO_SECTOR_SIZE - 1)
-#define MAXISOMASK (~MAXISOOFFSET)
-
-
-/* Standard File Structure Volume Descriptor */
-
-enum iso_voldesc_type {
- ISO_VD_BOOT=0, ISO_VD_PVD=1, ISO_VD_SVD=2, ISO_VD_VPD=3,
- ISO_VD_UNIX=4, /* UNIX extension */
- ISO_VD_EOV=255
-};
-#define ISO_ID_STRING "CD001" /* ISO_std_id field */
-#define ISO_ID_STRLEN 5 /* ISO_std_id field length */
-#define ISO_ID_VER 1 /* ISO_std_ver field */
-#define ISO_FILE_STRUCT_ID_VER 1 /* ISO_file structure version field */
-#define ISO_DATE_TO_UNIX(x) iso_parse_longdate(x) /* returns a timeval */
-#define ISO_SYS_ID_STRLEN 32
-#define ISO_VOL_ID_STRLEN 32
-#define ISO_VOL_SET_ID_STRLEN 128
-#define ISO_PUB_ID_STRLEN 128
-#define ISO_PREP_ID_STRLEN 128
-#define ISO_APPL_ID_STRLEN 128
-#define ISO_COPYR_ID_STRLEN 37
-#define ISO_ABSTR_ID_STRLEN 37
-#define ISO_DATE_LEN 17
-
-
-
-/* macros to get the address of each field */
-#define ISO_desc_type(x) (&((u_char *)x)[0])
-#define ISO_std_id(x) (&((u_char *)x)[1])
-#define ISO_std_ver(x) (&((u_char *)x)[6])
-#define ISO_sys_id(x) (&((u_char *)x)[8])
-#define ISO_vol_id(x) (&((u_char *)x)[40])
-#define ISO_vol_size(x) (&((u_char *)x)[80])
-#define ISO_set_size(x) (&((u_char *)x)[120])
-#define ISO_set_seq(x) (&((u_char *)x)[124])
-#define ISO_blk_size(x) (&((u_char *)x)[128])
-#define ISO_ptbl_size(x) (&((u_char *)x)[132])
-#define ISO_ptbl_man_ls(x) (&((u_char *)x)[140])
-#define ISO_ptbl_opt_ls1(x) (&((u_char *)x)[144])
-#define ISO_ptbl_man_ms(x) (&((u_char *)x)[148])
-#define ISO_ptbl_opt_ms1(x) (&((u_char *)x)[152])
-#define ISO_root_dir(x) (&((u_char *)x)[156])
-#define ISO_vol_set_id(x) (&((u_char *)x)[190])
-#define ISO_pub_id(x) (&((u_char *)x)[318])
-#define ISO_prep_id(x) (&((u_char *)x)[446])
-#define ISO_appl_id(x) (&((u_char *)x)[574])
-#define ISO_copyr_id(x) (&((u_char *)x)[702])
-#define ISO_abstr_id(x) (&((u_char *)x)[739])
-#define ISO_bibli_id(x) (&((u_char *)x)[776])
-#define ISO_cre_date(x) (&((u_char *)x)[813])
-#define ISO_mod_date(x) (&((u_char *)x)[830])
-#define ISO_exp_date(x) (&((u_char *)x)[847])
-#define ISO_eff_date(x) (&((u_char *)x)[864])
-#define ISO_file_struct_ver(x) (&((u_char *)x)[881])
-
-/* macros to get the values of each field (strings are returned as ptrs) */
-#define ISO_DESC_TYPE(x) ((enum hs_voldesc_type)*(ISO_desc_type(x)))
-#define ISO_STD_ID(x) ISO_std_id(x)
-#define ISO_STD_VER(x) *(ISO_std_ver(x))
-#define ISO_SYS_ID(x) ISO_sys_id(x)
-#define ISO_VOL_ID(x) ISO_vol_id(x)
-#define ISO_VOL_SIZE(x) BOTH_INT(ISO_vol_size(x))
-#define ISO_SET_SIZE(x) BOTH_SHORT(ISO_set_size(x))
-#define ISO_SET_SEQ(x) BOTH_SHORT(ISO_set_seq(x))
-#define ISO_BLK_SIZE(x) BOTH_SHORT(ISO_blk_size(x))
-#define ISO_PTBL_SIZE(x) BOTH_INT(ISO_ptbl_size(x))
-#define ISO_PTBL_MAN_LS(x) LSB_INT(ISO_ptbl_man_ls(x))
-#define ISO_PTBL_OPT_LS1(x) LSB_INT(ISO_ptbl_opt_ls1(x))
-#define ISO_PTBL_MAN_MS(x) MSB_INT(ISO_ptbl_man_ms(x))
-#define ISO_PTBL_OPT_MS1(x) MSB_INT(ISO_ptbl_opt_ms1(x))
-#define ISO_ROOT_DIR(x) ISO_root_dir(x)
-#define ISO_VOL_SET_ID(x) ISO_vol_set_id(x)
-#define ISO_PUB_ID(x) ISO_pub_id(x)
-#define ISO_PREP_ID(x) ISO_prep_id(x)
-#define ISO_APPL_ID(x) ISO_appl_id(x)
-#define ISO_COPYR_ID(x) ISO_copyr_id(x)
-#define ISO_ABSTR_ID(x) ISO_abstr_id(x)
-#define ISO_BIBLI_ID(x) ISO_bibli_id(x)
-#define ISO_CRE_DATE(x) ISO_DATE_TO_UNIX(HSV_cre_date(x))
-#define ISO_MOD_DATE(x) ISO_DATE_TO_UNIX(HSV_mod_date(x))
-#define ISO_EXP_DATE(x) ISO_DATE_TO_UNIX(HSV_exp_date(x))
-#define ISO_EFF_DATE(x) ISO_DATE_TO_UNIX(HSV_eff_date(x))
-#define ISO_FILE_STRUCT_VER(x) *(ISO_file_struct_ver(x))
-
-/* Standard File Structure Volume Descriptor date fields */
-#define ISO_DATE_2DIG(x) ( (((x)[0] - '0') * 10) + \
- ((x)[1] - '0') )
-#define ISO_DATE_4DIG(x) ( (((x)[0] - '0') * 1000) + \
- (((x)[1] - '0') * 100) + \
- (((x)[2] - '0') * 10) + \
- ((x)[3] - '0') )
-#define ISO_DATE_YEAR(x) ISO_DATE_4DIG(&((u_char *)x)[0])
-#define ISO_DATE_MONTH(x) ISO_DATE_2DIG(&((u_char *)x)[4])
-#define ISO_DATE_DAY(x) ISO_DATE_2DIG(&((u_char *)x)[6])
-#define ISO_DATE_HOUR(x) ISO_DATE_2DIG(&((u_char *)x)[8])
-#define ISO_DATE_MIN(x) ISO_DATE_2DIG(&((u_char *)x)[10])
-#define ISO_DATE_SEC(x) ISO_DATE_2DIG(&((u_char *)x)[12])
-#define ISO_DATE_HSEC(x) ISO_DATE_2DIG(&((u_char *)x)[14])
-
-
-
-/* Directory Entry (Directory Record) */
-#define IDE_ROOT_DIR_REC_SIZE 34 /* size of root directory record */
-#define IDE_FDESIZE 33 /* fixed size for hsfs directory area */
- /* max size of a name */
-#define IDE_MAX_NAME_LEN (255 - IDE_FDESIZE)
-
-
-#define IDE_DATE_TO_UNIX(x) iso_parse_dirdate(x) /* returns a timeval */
-
-/* macros to get the address of each field */
-#define IDE_dir_len(x) (&((u_char *)x)[0])
-#define IDE_xar_len(x) (&((u_char *)x)[1])
-#define IDE_ext_lbn(x) (&((u_char *)x)[2])
-#define IDE_ext_size(x) (&((u_char *)x)[10])
-#define IDE_cdate(x) (&((u_char *)x)[18])
-#define IDE_flags(x) (&((u_char *)x)[25])
-#define IDE_intrlv_size(x) (&((u_char *)x)[26])
-#define IDE_intrlv_skip(x) (&((u_char *)x)[27])
-#define IDE_vol_set(x) (&((u_char *)x)[28])
-#define IDE_name_len(x) (&((u_char *)x)[32])
-#define IDE_name(x) (&((u_char *)x)[33])
-
-/* macros to get the values of each field (strings are returned as ptrs) */
-#define IDE_DIR_LEN(x) *(IDE_dir_len(x))
-#define IDE_XAR_LEN(x) *(IDE_xar_len(x))
-#define IDE_EXT_LBN(x) BOTH_INT(IDE_ext_lbn(x))
-#define IDE_EXT_SIZE(x) BOTH_INT(IDE_ext_size(x))
-#define IDE_CDATE(x) IDE_DATE_TO_UNIX(HDE_cdate(x))
-#define IDE_FLAGS(x) *(IDE_flags(x))
-#define IDE_INTRLV_SIZE(x) *(IDE_intrlv_size(x))
-#define IDE_INTRLV_SKIP(x) *(IDE_intrlv_skip(x))
-#define IDE_VOL_SET(x) BOTH_SHORT(IDE_vol_set(x))
-#define IDE_NAME_LEN(x) *(IDE_name_len(x))
-#define IDE_NAME(x) IDE_name(x)
-
-/* mask bits for IDE_FLAGS */
-#define IDE_EXISTENCE 0x01 /* zero if file exists */
-#define IDE_DIRECTORY 0x02 /* zero if file is not a directory */
-#define IDE_ASSOCIATED 0x04 /* zero if file is not Associated */
-#define IDE_RECORD 0x08 /* zero if no record attributes */
-#define IDE_PROTECTION 0x10 /* zero if no protection attributes */
-#define IDE_UNUSED_FLAGS 0x60
-#define IDE_LAST_EXTENT 0x80 /* zero if last extent in file */
-#define IDE_PROHIBITED (IDE_DIRECTORY | HDE_ASSOCIATED | HDE_RECORD | \
- IDE_LAST_EXTENT | IDE_UNUSED_FLAGS)
-
-/* Directory Record date fields */
-#define IDE_DATE_YEAR(x) (((u_char *)x)[0] + 1900)
-#define IDE_DATE_MONTH(x) (((u_char *)x)[1])
-#define IDE_DATE_DAY(x) (((u_char *)x)[2])
-#define IDE_DATE_HOUR(x) (((u_char *)x)[3])
-#define IDE_DATE_MIN(x) (((u_char *)x)[4])
-#define IDE_DATE_SEC(x) (((u_char *)x)[5])
-
-/* tests for Interchange Levels 1 & 2 file types */
-#define IDE_REGULAR_FILE(x) (((x) & IDE_PROHIBITED) == 0)
-#define IDE_REGULAR_DIR(x) (((x) & IDE_PROHIBITED) == IDE_DIRECTORY)
-
-#define ISO_DIR_NAMELEN 31 /* max length of a directory name */
-#define ISO_FILE_NAMELEN 31 /* max length of a filename */
-
-/* Path table enry */
-/* fix size of path table entry */
-#define IPE_FPESIZE 8
-/* macros to get the address of each field */
-#define IPE_name_len(x) (&((u_char *)x)[0])
-#define IPE_xar_len(x) (&((u_char *)x)[1])
-#define IPE_ext_lbn(x) (&((u_char *)x)[2])
-#define IPE_parent_no(x) (&((u_char *)x)[6])
-#define IPE_name(x) (&((u_char *)x)[8])
-
-/* macros to get the values of each field */
-#define IPE_EXT_LBN(x) (MSB_INT(IPE_ext_lbn(x)))
-#define IPE_XAR_LEN(x) *(IPE_xar_len(x))
-#define IPE_NAME_LEN(x) *(IPE_name_len(x))
-#define IPE_PARENT_NO(x) *(short *)(IPE_parent_no(x))
-#define IPE_NAME(x) IPE_name(x)
-
-/* cdrom UNIX extension */
-/* UNIX Volume Descriptor */
-#define ISO_UNIX_ID_STRING "UNIXCD01" /* ISO_UNIX_std_id field */
-#define ISO_UNIX_ID_STRLEN 8 /* ISO_UNIX_std_id length */
-#define ISO_UNIX_FEATURE_SYMLNK 0x01 /* CD-ROM supports symbolic links */
-#define ISO_UNIX_FEATURE_LONGFN 0x02 /* CD-ROM supports long BSD file names */
-
-#define ISO_UNIX_feature(x) (&((u_char *)x)[7])
-#define ISO_UNIX_root_dir(x) (&((u_char *)x)[1395])
-#define ISO_UNIX_signature(x) (&((u_char *)x)[2040])
-
-#define ISO_UNIX_FEATURE(x) *(ISO_UNIX_feature(x))
-#define ISO_UNIX_ROOT_DIR(x) ISO_UNIX_root_dir(x)
-#define ISO_UNIX_SIGNATURE(x) ISO_UNIX_signature(x)
-
-/* UNIX extension to path table entry */
-/* fix size of path table entry */
-#define IPE_UNIX_FPESIZE 20
-
-#define IPE_UNIX_mode(x) (&((u_char *)x)[0])
-#define IPE_UNIX_uid(x) (&((u_char *)x)[4])
-#define IPE_UNIX_gid(x) (&((u_char *)x)[8])
-
-/* macros to get the values of each field */
-#define IPE_UNIX_MODE(x) (MSB_INT(IPE_UNIX_mode(x)))
-#define IPE_UNIX_UID(x) (MSB_INT(IPE_UNIX_uid(x)))
-#define IPE_UNIX_GID(x) (MSB_INT(IPE_UNIX_gid(x)))
-
-/* UNIX extension to directory entry */
-#define IDE_UNIX_SIG_UX "UX" /* UNIX extension signature */
-#define IDE_UNIX_SIG_TI "TI" /* UNIX extension signature for time */
-#define IDE_UNIX_USE_ID_VER 1 /* UNIX extension sys use id */
-#define IDE_UNIX_UX_LEN 36 /* length of UX */
-#define IDE_UNIX_TI_LEN 40 /* length of TI */
-
-#define IDE_UNIX_signature(x) (&((u_char *)x)[0])
-#define IDE_UNIX_ext_len(x) (&((u_char *)x)[2])
-#define IDE_UNIX_use_id(x) (&((u_char *)x)[3])
-#define IDE_UNIX_mode(x) (&((u_char *)x)[4])
-#define IDE_UNIX_nlink(x) (&((u_char *)x)[12])
-#define IDE_UNIX_uid(x) (&((u_char *)x)[20])
-#define IDE_UNIX_gid(x) (&((u_char *)x)[28])
-
-
-#define IDE_UNIX_cre_date(x) (&((u_char *)x)[4])
-#define IDE_UNIX_mod_date(x) (&((u_char *)x)[11])
-#define IDE_UNIX_exp_date(x) (&((u_char *)x)[18])
-#define IDE_UNIX_eff_date(x) (&((u_char *)x)[25])
-#define IDE_UNIX_acc_date(x) (&((u_char *)x)[32])
-#define IDE_UNIX_reserved(x) (&((u_char *)x)[39])
-
-#define IDE_UNIX_SIGNATURE(x) IDE_UNIX_signature(x)
-#define IDE_UNIX_EXT_LEN(x) *(IDE_UNIX_ext_len(x))
-#define IDE_UNIX_USE_ID(x) *(IDE_UNIX_use_id(x))
-#define IDE_UNIX_MODE(x) BOTH_INT(IDE_UNIX_mode(x))
-#define IDE_UNIX_NLINK(x) BOTH_INT(IDE_UNIX_nlink(x))
-#define IDE_UNIX_UID(x) BOTH_INT(IDE_UNIX_uid(x))
-#define IDE_UNIX_GID(x) BOTH_INT(IDE_UNIX_gid(x))
-
-#define IDE_UNIX_CRE_DATE(x) IDE_UNIX_cre_date(x)
-#define IDE_UNIX_MOD_DATE(x) IDE_UNIX_mod_date(x)
-#define IDE_UNIX_EXP_DATE(x) IDE_UNIX_exp_date(x)
-#define IDE_UNIX_EFF_DATE(x) IDE_UNIX_eff_date(x)
-#define IDE_UNIX_ACC_DATE(x) IDE_UNIX_acc_date(x)
-#define IDE_UNIX_RESERVED(x) *(IDE_UNIX_reserved(x))
-
-/* root record */
-/* size of root directory record */
-#define IDE_UNIX_ROOT_DIR_REC_SIZE 34+IDE_UNIX_UX_LEN
-#define IDE_UNIX_MAX_NAME_LEN IDE_MAX_NAME_LEN - IDE_UNIX_UX_LEN
-
-#endif /*!_ISO_SPEC_H_*/
--- a/usr/src/cmd/fs.d/hsfs/labelit/labelit.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/fs.d/hsfs/labelit/labelit.c Sun Aug 12 11:56:48 2012 +0100
@@ -38,9 +38,6 @@
* bibfile: bibliographic file identifier (d-charcters, 37 max)
*/
-#pragma ident "%Z%%M% %I% %E% SMI"
-
-
#include <fcntl.h>
#include <stdio.h>
#include <sys/param.h>
@@ -49,9 +46,9 @@
#include <sys/types.h>
#include <sys/file.h>
#include <dirent.h>
-#include "hsfs_spec.h"
-#include "iso_spec.h"
-#include "iso_impl.h"
+
+#include <sys/fs/hsfs_isospec.h>
+#include <sys/fs/hsfs_spec.h>
#define PUTSECTOR(buf, secno, nosec) (putdisk(buf, (secno)*ISO_SECTOR_SIZE, \
(nosec)*ISO_SECTOR_SIZE))
@@ -157,7 +154,9 @@
if ((cdfd = open(argv[c], openopt)) < 0) {
if (strchr(argv[c], '=') ||
- strchr(argv[c], '-')) usage();
+ strchr(argv[c], '-')) {
+ usage();
+ }
sprintf(errstrng, "%s: main: open(): ", callname);
perror(errstrng);
exit(32);
@@ -185,7 +184,7 @@
usage(void)
{
fprintf(stderr, "usage: %s [-F ufs] [option=value ...] cdimage\n",
- callname);
+ callname);
exit(32);
}
--- a/usr/src/cmd/hal/hald-runner/main.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/hal/hald-runner/main.c Sun Aug 12 11:56:48 2012 +0100
@@ -4,6 +4,7 @@
* main.c - Main dbus interface of the hald runner
*
* Copyright (C) 2006 Sjoerd Simons, <[email protected]>
+ * Copyright (C) 2007 Codethink Ltd. Author Rob Taylor <[email protected]>
*
* Licensed under the Academic Free License version 2.1
*
@@ -31,24 +32,46 @@
#include "utils.h"
#include "runner.h"
+#ifndef __GNUC__
+#define __attribute__(x)
+#endif
+
static gboolean
-parse_first_part(run_request *r, DBusMessage *msg, DBusMessageIter *iter)
+parse_udi (run_request *r, DBusMessage *msg, DBusMessageIter *iter)
{
- DBusMessageIter sub_iter;
char *tmpstr;
- /* First should be the device UDI */
+ /* Should be the device UDI */
if (dbus_message_iter_get_arg_type(iter) != DBUS_TYPE_STRING)
goto malformed;
dbus_message_iter_get_basic(iter, &tmpstr);
r->udi = g_strdup(tmpstr);
- /* Then the environment array */
- if (!dbus_message_iter_next(iter) || dbus_message_iter_get_arg_type(iter) != DBUS_TYPE_ARRAY)
+ if (!dbus_message_iter_next(iter))
+ goto malformed;
+
+ return TRUE;
+
+malformed:
+ return FALSE;
+}
+
+static gboolean
+parse_environment(run_request *r, DBusMessage *msg, DBusMessageIter *iter)
+{
+ DBusMessageIter sub_iter;
+ char *tmpstr;
+
+ /* The environment array */
+ if (dbus_message_iter_get_arg_type(iter) != DBUS_TYPE_ARRAY)
goto malformed;
dbus_message_iter_recurse(iter, &sub_iter);
/* Add default path for the programs we start */
+#if defined(__FreeBSD__)
+ tmpstr = g_strdup_printf("PATH=/sbin:/usr/sbin:/bin:/usr/bin:/usr/local/sbin:/usr/X11R6/sbin:/bin:/usr/bin:/usr/local/bin:/usr/X11R6/bin:%s", getenv("PATH"));
+#else
tmpstr = g_strdup_printf("PATH=/sbin:/usr/sbin:/bin:/usr/bin:%s", getenv("PATH"));
+#endif
r->environment = get_string_array(&sub_iter, tmpstr);
/* Then argv */
@@ -74,7 +97,10 @@
r = new_run_request();
g_assert(dbus_message_iter_init(msg, &iter));
- if (!parse_first_part(r, msg, &iter))
+ if (!parse_udi(r, msg, &iter))
+ goto malformed;
+
+ if (!parse_environment(r, msg, &iter))
goto malformed;
/* Next a string of what should be written to stdin */
@@ -106,25 +132,36 @@
}
static void
-handle_start(DBusConnection *con, DBusMessage *msg)
+handle_start(DBusConnection *con, DBusMessage *msg, gboolean is_singleton)
{
DBusMessage *reply;
DBusMessageIter iter;
run_request *r;
GPid pid;
- dbus_int64_t pid64;
r = new_run_request();
+ r->is_singleton = is_singleton;
+
g_assert(dbus_message_iter_init(msg, &iter));
- if (!dbus_message_iter_init(msg, &iter) || !parse_first_part(r, msg, &iter))
+ if (!dbus_message_iter_init(msg, &iter))
+ goto malformed;
+
+ if (!is_singleton && !parse_udi(r, msg, &iter)) {
+ fprintf(stderr, "error parsing udi");
goto malformed;
+ }
+
+ if (!parse_environment(r, msg, &iter)) {
+ fprintf(stderr, "error parsing environment");
+ goto malformed;
+ }
if (run_request_run(r, con, NULL, &pid)) {
- pid64 = pid;
+ gint64 ppid = pid;
reply = dbus_message_new_method_return(msg);
dbus_message_append_args (reply,
- DBUS_TYPE_INT64, &pid64,
+ DBUS_TYPE_INT64, &ppid,
DBUS_TYPE_INVALID);
} else {
@@ -177,11 +214,18 @@
handle_run(con, msg);
return DBUS_HANDLER_RESULT_HANDLED;
} else if (dbus_message_is_method_call(msg, "org.freedesktop.HalRunner", "Start")) {
- handle_start(con, msg);
+ handle_start(con, msg, FALSE);
+ return DBUS_HANDLER_RESULT_HANDLED;
+ } else if (dbus_message_is_method_call(msg, "org.freedesktop.HalRunner", "StartSingleton")) {
+ handle_start(con, msg, TRUE);
return DBUS_HANDLER_RESULT_HANDLED;
} else if (dbus_message_is_method_call(msg, "org.freedesktop.HalRunner", "Kill")) {
handle_kill(con, msg);
return DBUS_HANDLER_RESULT_HANDLED;
+ } else if (dbus_message_is_method_call(msg, "org.freedesktop.HalRunner", "Shutdown")) {
+ run_kill_all ();
+ exit (0);
+ return DBUS_HANDLER_RESULT_HANDLED;
} else if (dbus_message_is_method_call(msg, "org.freedesktop.HalRunner", "KillAll")) {
run_kill_all();
/* alwasy successfull */
--- a/usr/src/cmd/hal/hald-runner/runner.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/hal/hald-runner/runner.c Sun Aug 12 11:56:48 2012 +0100
@@ -4,6 +4,7 @@
* runner.c - Process running code
*
* Copyright (C) 2006 Sjoerd Simons, <[email protected]>
+ * Copyright (C) 2007 Codethink Ltd. Author Rob Taylor <[email protected]>
*
* Licensed under the Academic Free License version 2.1
*
@@ -48,6 +49,7 @@
#define HALD_RUN_KILLED 0x4
GHashTable *udi_hash = NULL;
+GList *singletons = NULL;
typedef struct {
run_request *r;
@@ -128,15 +130,19 @@
}
static void
-remove_from_hash_table(run_data *rd)
+remove_run_data(run_data *rd)
{
GList *list;
- /* Remove to the hashtable */
- list = (GList *)g_hash_table_lookup(udi_hash, rd->r->udi);
- list = g_list_remove(list, rd);
- /* The hash table will take care to not leak the dupped string */
- g_hash_table_insert(udi_hash, g_strdup(rd->r->udi), list);
+ if (rd->r->is_singleton) {
+ singletons = g_list_remove(singletons, rd);
+ } else {
+ /* Remove to the hashtable */
+ list = (GList *)g_hash_table_lookup(udi_hash, rd->r->udi);
+ list = g_list_remove(list, rd);
+ /* The hash table will take care to not leak the dupped string */
+ g_hash_table_insert(udi_hash, g_strdup(rd->r->udi), list);
+ }
}
static void
@@ -145,7 +151,8 @@
run_data *rd = (run_data *)data;
char **error = NULL;
- printf("%s exited\n", rd->r->argv[0]);
+ printf("pid %d: rc=%d signaled=%d: %s\n",
+ pid, WEXITSTATUS(status), WIFSIGNALED(status), rd->r->argv[0]);
rd->watch = 0;
if (rd->sent_kill == TRUE) {
/* We send it a kill, so ignore */
@@ -170,18 +177,17 @@
free_string_array(error);
out:
- remove_from_hash_table(rd);
+ remove_run_data (rd);
/* emit a signal that this PID exited */
if(rd->con != NULL && rd->emit_pid_exited) {
DBusMessage *signal;
- dbus_int64_t pid64;
+ gint64 ppid = rd->pid;
signal = dbus_message_new_signal ("/org/freedesktop/HalRunner",
"org.freedesktop.HalRunner",
"StartedProcessExited");
- pid64 = rd->pid;
dbus_message_append_args (signal,
- DBUS_TYPE_INT64, &pid64,
+ DBUS_TYPE_INT64, &(ppid),
DBUS_TYPE_INVALID);
dbus_connection_send(rd->con, signal, NULL);
}
@@ -202,7 +208,7 @@
rd->sent_kill = TRUE;
send_reply(rd->con, rd->msg, HALD_RUN_TIMEOUT, 0, NULL);
- remove_from_hash_table(rd);
+ remove_run_data (rd);
return FALSE;
}
@@ -246,7 +252,7 @@
char *program_dir = NULL;
GList *list;
- printf("Run started %s (%d) (%d) \n!", r->argv[0], r->timeout,
+ printf("Run started %s (%u) (%d) \n!", r->argv[0], r->timeout,
r->error_on_stderr);
if (r->input != NULL) {
stdin_p = &stdin_v;
@@ -277,7 +283,7 @@
if (r->input) {
if (write(stdin_v, r->input, strlen(r->input)) != (ssize_t) strlen(r->input))
- printf("Warning: Error while wite r->input (%s) to stdin_v.\n", r->input);
+ printf("Warning: Error while writing r->input (%s) to stdin_v.\n", r->input);
close(stdin_v);
}
@@ -302,12 +308,16 @@
else
rd->timeout = 0;
- /* Add to the hashtable */
- list = (GList *)g_hash_table_lookup(udi_hash, r->udi);
- list = g_list_prepend(list, rd);
+ if (r->is_singleton) {
+ singletons = g_list_prepend(singletons, rd);
+ } else {
+ /* Add to the hashtable */
+ list = (GList *)g_hash_table_lookup(udi_hash, r->udi);
+ list = g_list_prepend(list, rd);
- /* The hash table will take care to not leak the dupped string */
- g_hash_table_insert(udi_hash, g_strdup(r->udi), list);
+ /* The hash table will take care to not leak the dupped string */
+ g_hash_table_insert(udi_hash, g_strdup(r->udi), list);
+ }
/* send back PID if requested.. and only emit StartedProcessExited in this case */
if (out_pid != NULL) {
@@ -365,6 +375,7 @@
run_kill_all()
{
g_hash_table_foreach_remove(udi_hash, hash_kill_udi, NULL);
+ g_list_foreach(singletons, kill_rd, NULL);
}
void
--- a/usr/src/cmd/hal/hald-runner/runner.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/hal/hald-runner/runner.h Sun Aug 12 11:56:48 2012 +0100
@@ -36,6 +36,7 @@
gchar **argv;
gchar *input;
gboolean error_on_stderr;
+ gboolean is_singleton;
guint32 timeout;
} run_request;
@@ -49,9 +50,9 @@
void run_kill_udi(gchar *udi);
/* Kill all running request*/
-void run_kill_all();
+void run_kill_all(void);
/* initialise the actual runner data */
-void run_init();
+void run_init(void);
#endif /* RUNNER_H */
--- a/usr/src/cmd/mdb/common/mdb/mdb_main.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/mdb/common/mdb/mdb_main.c Sun Aug 12 11:56:48 2012 +0100
@@ -21,6 +21,7 @@
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
+ * Copyright 2012, Josef 'Jeff' Sipek <[email protected]>. All rights reserved.
*/
#include <sys/types.h>
@@ -803,6 +804,9 @@
tgt_argc -= c;
}
+ if (fflag)
+ goto tcreate; /* skip re-exec and just create target */
+
/*
* If we just have an object file name, and that file doesn't
* exist, and it's a string of digits, infer it to be a
@@ -866,8 +870,7 @@
* it is not and the target is unknown, use the rawfile tgt.
* Otherwise an ELF-based target is needed, so we must abort.
*/
- if (tgt_ctor != mdb_rawfile_tgt_create &&
- mdb_gelf_check(io, &ehdr, ET_NONE) == -1) {
+ if (mdb_gelf_check(io, &ehdr, ET_NONE) == -1) {
if (tgt_ctor != NULL) {
(void) mdb_gelf_check(io, &ehdr, ET_EXEC);
mdb_io_destroy(io);
@@ -878,8 +881,7 @@
mdb_io_destroy(io);
- if (identify_xvm_file(tgt_argv[0], &longmode) == 1 &&
- !fflag) {
+ if (identify_xvm_file(tgt_argv[0], &longmode) == 1) {
#ifdef _LP64
if (!longmode)
goto reexec;
@@ -891,9 +893,6 @@
goto tcreate;
}
- if (tgt_ctor == mdb_rawfile_tgt_create)
- goto tcreate; /* skip re-exec and just create target */
-
/*
* The object file turned out to be a user core file (ET_CORE),
* and no other arguments were specified, swap 0 and 1. The
--- a/usr/src/cmd/savecore/savecore.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/savecore/savecore.c Sun Aug 12 11:56:48 2012 +0100
@@ -21,6 +21,9 @@
/*
* Copyright (c) 1983, 2010, Oracle and/or its affiliates. All rights reserved.
*/
+/*
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
+ */
#include <stdio.h>
#include <stdlib.h>
@@ -218,6 +221,13 @@
break;
case SC_EXIT_PEND:
+ /*
+ * Raise an ireport saying why we are exiting. Do not
+ * raise if run as savecore -m. If something in the
+ * raise_event codepath calls logprint avoid recursion.
+ */
+ if (!mflag && logprint_raised++ == 0)
+ raise_event(SC_EVENT_SAVECORE_FAILURE, buf);
code = 2;
break;
@@ -227,11 +237,6 @@
case SC_EXIT_ERR:
default:
- /*
- * Raise an ireport saying why we are exiting. Do not
- * raise if run as savecore -m. If something in the
- * raise_event codepath calls logprint avoid recursion.
- */
if (!mflag && logprint_raised++ == 0)
raise_event(SC_EVENT_SAVECORE_FAILURE, buf);
code = 1;
@@ -356,7 +361,7 @@
pagesize = dumphdr.dump_pagesize;
if (dumphdr.dump_magic != DUMP_MAGIC)
- logprint(SC_SL_NONE | SC_EXIT_OK, "bad magic number %x",
+ logprint(SC_SL_NONE | SC_EXIT_PEND, "bad magic number %x",
dumphdr.dump_magic);
if ((dumphdr.dump_flags & DF_VALID) == 0 && !disregard_valid_flag)
@@ -364,18 +369,18 @@
"dump already processed");
if (dumphdr.dump_version != DUMP_VERSION)
- logprint(SC_SL_NONE | SC_IF_VERBOSE | SC_EXIT_OK,
+ logprint(SC_SL_NONE | SC_IF_VERBOSE | SC_EXIT_PEND,
"dump version (%d) != %s version (%d)",
dumphdr.dump_version, progname, DUMP_VERSION);
if (dumphdr.dump_wordsize != DUMP_WORDSIZE)
- logprint(SC_SL_NONE | SC_EXIT_OK,
+ logprint(SC_SL_NONE | SC_EXIT_PEND,
"dump is from %u-bit kernel - cannot save on %u-bit kernel",
dumphdr.dump_wordsize, DUMP_WORDSIZE);
if (datahdr.dump_datahdr_magic == DUMP_DATAHDR_MAGIC) {
if (datahdr.dump_datahdr_version != DUMP_DATAHDR_VERSION)
- logprint(SC_SL_NONE | SC_IF_VERBOSE | SC_EXIT_OK,
+ logprint(SC_SL_NONE | SC_IF_VERBOSE | SC_EXIT_PEND,
"dump data version (%d) != %s data version (%d)",
datahdr.dump_datahdr_version, progname,
DUMP_DATAHDR_VERSION);
--- a/usr/src/cmd/smbsrv/smbd/Makefile Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/smbsrv/smbd/Makefile Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
#
#
# Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
+# Copyright 2012 Nexenta Systems, Inc. All rights reserved.
#
@@ -55,6 +56,8 @@
-lzfs -lbsm -lsocket -lnsl -lscf -lumem -lcmdutils
LDFLAGS += -R/usr/lib/smbsrv
+$(ENABLE_SMB_PRINTING) CPPFLAGS += -DHAVE_CUPS
+
ROOTSMBDDIR = $(ROOTLIB)/smbsrv
ROOTSMBDFILE = $(PROG:%=$(ROOTSMBDDIR)/%)
--- a/usr/src/cmd/smbsrv/smbd/smbd_spool.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/smbsrv/smbd/smbd_spool.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,7 +20,7 @@
*/
/*
* Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
/*
@@ -29,7 +29,6 @@
#include <sys/types.h>
#include <sys/stat.h>
-#include <cups/cups.h>
#include <strings.h>
#include <syslog.h>
#include <signal.h>
@@ -41,6 +40,9 @@
#include <smbsrv/smb_share.h>
#include "smbd.h"
+#ifdef HAVE_CUPS
+#include <cups/cups.h>
+
#define SMB_SPOOL_WAIT 2
#define SMBD_PJOBLEN 256
#define SMBD_PRINTER "Postscript"
@@ -512,3 +514,47 @@
(void) strlcpy(si->shr_cmnt, comment, SMB_SHARE_CMNT_MAX);
}
+
+#else /* HAVE_CUPS */
+
+/*
+ * If not HAVE_CUPS, just provide a few "stubs".
+ */
+
+int
+smbd_cups_init(void)
+{
+ return (ENOENT);
+}
+
+void
+smbd_cups_fini(void)
+{
+}
+
+void
+smbd_load_printers(void)
+{
+}
+
+void
+smbd_spool_init(void)
+{
+}
+
+void
+smbd_spool_fini(void)
+{
+}
+
+void
+smbd_spool_start(void)
+{
+}
+
+void
+smbd_spool_stop(void)
+{
+}
+
+#endif /* HAVE_CUPS */
--- a/usr/src/cmd/truss/codes.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/truss/codes.c Sun Aug 12 11:56:48 2012 +0100
@@ -1251,7 +1251,7 @@
"zfs_cmd_t" },
{ (uint_t)ZFS_IOC_SPACE_WRITTEN, "ZFS_IOC_SPACE_WRITTEN",
"zfs_cmd_t" },
- { (uint_t)ZFS_IOC_DESTROY_SNAPS_NVL, "ZFS_IOC_DESTROY_SNAPS_NVL",
+ { (uint_t)ZFS_IOC_DESTROY_SNAPS, "ZFS_IOC_DESTROY_SNAPS",
"zfs_cmd_t" },
{ (uint_t)ZFS_IOC_POOL_REGUID, "ZFS_IOC_POOL_REGUID",
"zfs_cmd_t" },
@@ -1259,6 +1259,14 @@
"zfs_cmd_t" },
{ (uint_t)ZFS_IOC_SEND_PROGRESS, "ZFS_IOC_SEND_PROGRESS",
"zfs_cmd_t" },
+ { (uint_t)ZFS_IOC_LOG_HISTORY, "ZFS_IOC_LOG_HISTORY",
+ "zfs_cmd_t" },
+ { (uint_t)ZFS_IOC_SEND_NEW, "ZFS_IOC_SEND_NEW",
+ "zfs_cmd_t" },
+ { (uint_t)ZFS_IOC_SEND_SPACE, "ZFS_IOC_SEND_SPACE",
+ "zfs_cmd_t" },
+ { (uint_t)ZFS_IOC_CLONE, "ZFS_IOC_CLONE",
+ "zfs_cmd_t" },
/* kssl ioctls */
{ (uint_t)KSSL_ADD_ENTRY, "KSSL_ADD_ENTRY",
--- a/usr/src/cmd/zdb/zdb.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/zdb/zdb.c Sun Aug 12 11:56:48 2012 +0100
@@ -57,6 +57,7 @@
#include <sys/arc.h>
#include <sys/ddt.h>
#include <sys/zfeature.h>
+#include <zfs_comutil.h>
#undef ZFS_MAXNAMELEN
#undef verify
#include <libzfs.h>
@@ -204,6 +205,27 @@
nvlist_free(nv);
}
+/* ARGSUSED */
+static void
+dump_history_offsets(objset_t *os, uint64_t object, void *data, size_t size)
+{
+ spa_history_phys_t *shp = data;
+
+ if (shp == NULL)
+ return;
+
+ (void) printf("\t\tpool_create_len = %llu\n",
+ (u_longlong_t)shp->sh_pool_create_len);
+ (void) printf("\t\tphys_max_off = %llu\n",
+ (u_longlong_t)shp->sh_phys_max_off);
+ (void) printf("\t\tbof = %llu\n",
+ (u_longlong_t)shp->sh_bof);
+ (void) printf("\t\teof = %llu\n",
+ (u_longlong_t)shp->sh_eof);
+ (void) printf("\t\trecords_lost = %llu\n",
+ (u_longlong_t)shp->sh_records_lost);
+}
+
static void
zdb_nicenum(uint64_t num, char *buf)
{
@@ -853,21 +875,22 @@
for (int i = 0; i < num; i++) {
uint64_t time, txg, ievent;
char *cmd, *intstr;
+ boolean_t printed = B_FALSE;
if (nvlist_lookup_uint64(events[i], ZPOOL_HIST_TIME,
&time) != 0)
- continue;
+ goto next;
if (nvlist_lookup_string(events[i], ZPOOL_HIST_CMD,
&cmd) != 0) {
if (nvlist_lookup_uint64(events[i],
ZPOOL_HIST_INT_EVENT, &ievent) != 0)
- continue;
+ goto next;
verify(nvlist_lookup_uint64(events[i],
ZPOOL_HIST_TXG, &txg) == 0);
verify(nvlist_lookup_string(events[i],
ZPOOL_HIST_INT_STR, &intstr) == 0);
- if (ievent >= LOG_END)
- continue;
+ if (ievent >= ZFS_NUM_LEGACY_HISTORY_EVENTS)
+ goto next;
(void) snprintf(internalstr,
sizeof (internalstr),
@@ -880,6 +903,14 @@
(void) localtime_r(&tsec, &t);
(void) strftime(tbuf, sizeof (tbuf), "%F.%T", &t);
(void) printf("%s %s\n", tbuf, cmd);
+ printed = B_TRUE;
+
+next:
+ if (dump_opt['h'] > 1) {
+ if (!printed)
+ (void) printf("unrecognized record:\n");
+ dump_nvlist(events[i], 2);
+ }
}
}
@@ -1456,7 +1487,7 @@
dump_zap, /* other ZAP */
dump_zap, /* persistent error log */
dump_uint8, /* SPA history */
- dump_uint64, /* SPA history offsets */
+ dump_history_offsets, /* SPA history offsets */
dump_zap, /* Pool properties */
dump_zap, /* DSL permissions */
dump_acl, /* ZFS ACL */
--- a/usr/src/cmd/zfs/Makefile Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/zfs/Makefile Sun Aug 12 11:56:48 2012 +0100
@@ -18,10 +18,11 @@
#
# CDDL HEADER END
#
+# Copyright 2010 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
#
-# Copyright 2010 Sun Microsystems, Inc. All rights reserved.
# Copyright 2010 Nexenta Systems, Inc. All rights reserved.
-# Use is subject to license terms.
+# Copyright (c) 2012 by Delphix. All rights reserved.
#
PROG= zfs
@@ -38,7 +39,7 @@
ROOTETCFSTYPE= $(ROOTETC)/fs/$(FSTYPE)
USRLIBFSTYPE= $(ROOTLIB)/fs/$(FSTYPE)
-LDLIBS += -lzfs -luutil -lumem -lnvpair -lsec -lidmap
+LDLIBS += -lzfs_core -lzfs -luutil -lumem -lnvpair -lsec -lidmap
INCS += -I../../common/zfs
--- a/usr/src/cmd/zfs/zfs_main.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/zfs/zfs_main.c Sun Aug 12 11:56:48 2012 +0100
@@ -56,6 +56,7 @@
#include <time.h>
#include <libzfs.h>
+#include <libzfs_core.h>
#include <zfs_prop.h>
#include <zfs_deleg.h>
#include <libuutil.h>
@@ -70,6 +71,7 @@
static FILE *mnttab_file;
static char history_str[HIS_MAX_RECORD_LEN];
+static boolean_t log_history = B_TRUE;
static int zfs_do_clone(int argc, char **argv);
static int zfs_do_create(int argc, char **argv);
@@ -259,7 +261,7 @@
return (gettext("\tshare <-a | filesystem>\n"));
case HELP_SNAPSHOT:
return (gettext("\tsnapshot [-r] [-o property=value] ... "
- "<filesystem@snapname|volume@snapname>\n"));
+ "<filesystem@snapname|volume@snapname> ...\n"));
case HELP_UNMOUNT:
return (gettext("\tunmount [-f] "
"<-a | filesystem|mountpoint>\n"));
@@ -888,9 +890,9 @@
nvlist_t *cb_nvl;
/* first snap in contiguous run */
- zfs_handle_t *cb_firstsnap;
+ char *cb_firstsnap;
/* previous snap in contiguous run */
- zfs_handle_t *cb_prevsnap;
+ char *cb_prevsnap;
int64_t cb_snapused;
char *cb_snapspec;
} destroy_cbdata_t;
@@ -1004,11 +1006,13 @@
if (nvlist_exists(cb->cb_nvl, name)) {
if (cb->cb_firstsnap == NULL)
- cb->cb_firstsnap = zfs_handle_dup(zhp);
+ cb->cb_firstsnap = strdup(name);
if (cb->cb_prevsnap != NULL)
- zfs_close(cb->cb_prevsnap);
+ free(cb->cb_prevsnap);
/* this snap continues the current range */
- cb->cb_prevsnap = zfs_handle_dup(zhp);
+ cb->cb_prevsnap = strdup(name);
+ if (cb->cb_firstsnap == NULL || cb->cb_prevsnap == NULL)
+ nomem();
if (cb->cb_verbose) {
if (cb->cb_parsable) {
(void) printf("destroy\t%s\n", name);
@@ -1023,12 +1027,12 @@
} else if (cb->cb_firstsnap != NULL) {
/* end of this range */
uint64_t used = 0;
- err = zfs_get_snapused_int(cb->cb_firstsnap,
+ err = lzc_snaprange_space(cb->cb_firstsnap,
cb->cb_prevsnap, &used);
cb->cb_snapused += used;
- zfs_close(cb->cb_firstsnap);
+ free(cb->cb_firstsnap);
cb->cb_firstsnap = NULL;
- zfs_close(cb->cb_prevsnap);
+ free(cb->cb_prevsnap);
cb->cb_prevsnap = NULL;
}
zfs_close(zhp);
@@ -1045,13 +1049,13 @@
if (cb->cb_firstsnap != NULL) {
uint64_t used = 0;
if (err == 0) {
- err = zfs_get_snapused_int(cb->cb_firstsnap,
+ err = lzc_snaprange_space(cb->cb_firstsnap,
cb->cb_prevsnap, &used);
}
cb->cb_snapused += used;
- zfs_close(cb->cb_firstsnap);
+ free(cb->cb_firstsnap);
cb->cb_firstsnap = NULL;
- zfs_close(cb->cb_prevsnap);
+ free(cb->cb_prevsnap);
cb->cb_prevsnap = NULL;
}
return (err);
@@ -1064,7 +1068,7 @@
int err = 0;
/* Check for clones. */
- if (!cb->cb_doclones) {
+ if (!cb->cb_doclones && !cb->cb_defer_destroy) {
cb->cb_target = zhp;
cb->cb_first = B_TRUE;
err = zfs_iter_dependents(zhp, B_TRUE,
@@ -1904,9 +1908,11 @@
/*
* If they did "zfs upgrade -a", then we could
* be doing ioctls to different pools. We need
- * to log this history once to each pool.
+ * to log this history once to each pool, and bypass
+ * the normal history logging that happens in main().
*/
- verify(zpool_stage_history(g_zfs, history_str) == 0);
+ (void) zpool_log_history(g_zfs, history_str);
+ log_history = B_FALSE;
}
if (zfs_prop_set(zhp, "version", verstr) == 0)
cb->cb_numupgraded++;
@@ -3424,6 +3430,32 @@
return (ret);
}
+typedef struct snap_cbdata {
+ nvlist_t *sd_nvl;
+ boolean_t sd_recursive;
+ const char *sd_snapname;
+} snap_cbdata_t;
+
+static int
+zfs_snapshot_cb(zfs_handle_t *zhp, void *arg)
+{
+ snap_cbdata_t *sd = arg;
+ char *name;
+ int rv = 0;
+ int error;
+
+ error = asprintf(&name, "%s@%s", zfs_get_name(zhp), sd->sd_snapname);
+ if (error == -1)
+ nomem();
+ fnvlist_add_boolean(sd->sd_nvl, name);
+ free(name);
+
+ if (sd->sd_recursive)
+ rv = zfs_iter_filesystems(zhp, zfs_snapshot_cb, sd);
+ zfs_close(zhp);
+ return (rv);
+}
+
/*
* zfs snapshot [-r] [-o prop=value] ... <fs@snap>
*
@@ -3433,13 +3465,16 @@
static int
zfs_do_snapshot(int argc, char **argv)
{
- boolean_t recursive = B_FALSE;
int ret = 0;
char c;
nvlist_t *props;
+ snap_cbdata_t sd = { 0 };
+ boolean_t multiple_snaps = B_FALSE;
if (nvlist_alloc(&props, NV_UNIQUE_NAME, 0) != 0)
nomem();
+ if (nvlist_alloc(&sd.sd_nvl, NV_UNIQUE_NAME, 0) != 0)
+ nomem();
/* check options */
while ((c = getopt(argc, argv, "ro:")) != -1) {
@@ -3449,7 +3484,8 @@
return (1);
break;
case 'r':
- recursive = B_TRUE;
+ sd.sd_recursive = B_TRUE;
+ multiple_snaps = B_TRUE;
break;
case '?':
(void) fprintf(stderr, gettext("invalid option '%c'\n"),
@@ -3466,18 +3502,35 @@
(void) fprintf(stderr, gettext("missing snapshot argument\n"));
goto usage;
}
- if (argc > 1) {
- (void) fprintf(stderr, gettext("too many arguments\n"));
- goto usage;
- }
-
- ret = zfs_snapshot(g_zfs, argv[0], recursive, props);
+
+ if (argc > 1)
+ multiple_snaps = B_TRUE;
+ for (; argc > 0; argc--, argv++) {
+ char *atp;
+ zfs_handle_t *zhp;
+
+ atp = strchr(argv[0], '@');
+ if (atp == NULL)
+ goto usage;
+ *atp = '\0';
+ sd.sd_snapname = atp + 1;
+ zhp = zfs_open(g_zfs, argv[0],
+ ZFS_TYPE_FILESYSTEM | ZFS_TYPE_VOLUME);
+ if (zhp == NULL)
+ goto usage;
+ if (zfs_snapshot_cb(zhp, &sd) != 0)
+ goto usage;
+ }
+
+ ret = zfs_snapshot_nvl(g_zfs, sd.sd_nvl, props);
+ nvlist_free(sd.sd_nvl);
nvlist_free(props);
- if (ret && recursive)
+ if (ret != 0 && multiple_snaps)
(void) fprintf(stderr, gettext("no snapshots were created\n"));
return (ret != 0);
usage:
+ nvlist_free(sd.sd_nvl);
nvlist_free(props);
usage(B_FALSE);
return (-1);
@@ -6479,8 +6532,7 @@
return (1);
}
- zpool_set_history_str("zfs", argc, argv, history_str);
- verify(zpool_stage_history(g_zfs, history_str) == 0);
+ zfs_save_arguments(argc, argv, history_str, sizeof (history_str));
libzfs_print_on_error(g_zfs, B_TRUE);
@@ -6549,6 +6601,9 @@
(void) fclose(mnttab_file);
+ if (ret == 0 && log_history)
+ (void) zpool_log_history(g_zfs, history_str);
+
libzfs_fini(g_zfs);
/*
--- a/usr/src/cmd/zhack/zhack.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/zhack/zhack.c Sun Aug 12 11:56:48 2012 +0100
@@ -279,6 +279,9 @@
zfeature_info_t *feature = arg2;
spa_feature_enable(spa, feature, tx);
+ spa_history_log_internal(spa, "zhack enable feature", tx,
+ "guid=%s can_readonly=%u",
+ feature->fi_guid, feature->fi_can_readonly);
}
static void
@@ -356,6 +359,8 @@
zfeature_info_t *feature = arg2;
spa_feature_incr(spa, feature, tx);
+ spa_history_log_internal(spa, "zhack feature incr", tx,
+ "guid=%s", feature->fi_guid);
}
static void
@@ -365,6 +370,8 @@
zfeature_info_t *feature = arg2;
spa_feature_decr(spa, feature, tx);
+ spa_history_log_internal(spa, "zhack feature decr", tx,
+ "guid=%s", feature->fi_guid);
}
static void
--- a/usr/src/cmd/zpool/zpool_main.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/zpool/zpool_main.c Sun Aug 12 11:56:48 2012 +0100
@@ -185,9 +185,9 @@
#define NCOMMAND (sizeof (command_table) / sizeof (command_table[0]))
-zpool_command_t *current_command;
+static zpool_command_t *current_command;
static char history_str[HIS_MAX_RECORD_LEN];
-
+static boolean_t log_history = B_TRUE;
static uint_t timestamp_fmt = NODATE;
static const char *
@@ -381,6 +381,18 @@
}
}
+static boolean_t
+prop_list_contains_feature(nvlist_t *proplist)
+{
+ nvpair_t *nvp;
+ for (nvp = nvlist_next_nvpair(proplist, NULL); NULL != nvp;
+ nvp = nvlist_next_nvpair(proplist, nvp)) {
+ if (zpool_prop_feature(nvpair_name(nvp)))
+ return (B_TRUE);
+ }
+ return (B_FALSE);
+}
+
/*
* Add a property pair (name, string-value) into a property nvlist.
*/
@@ -404,12 +416,30 @@
proplist = *props;
if (poolprop) {
+ const char *vname = zpool_prop_to_name(ZPOOL_PROP_VERSION);
+
if ((prop = zpool_name_to_prop(propname)) == ZPROP_INVAL &&
!zpool_prop_feature(propname)) {
(void) fprintf(stderr, gettext("property '%s' is "
"not a valid pool property\n"), propname);
return (2);
}
+
+ /*
+ * feature@ properties and version should not be specified
+ * at the same time.
+ */
+ if ((prop == ZPROP_INVAL && zpool_prop_feature(propname) &&
+ nvlist_exists(proplist, vname)) ||
+ (prop == ZPOOL_PROP_VERSION &&
+ prop_list_contains_feature(proplist))) {
+ (void) fprintf(stderr, gettext("'feature@' and "
+ "'version' properties cannot be specified "
+ "together\n"));
+ return (2);
+ }
+
+
if (zpool_prop_feature(propname))
normnm = propname;
else
@@ -935,7 +965,10 @@
return (1);
}
- ret = (zpool_destroy(zhp) != 0);
+ /* The history must be logged as part of the export */
+ log_history = B_FALSE;
+
+ ret = (zpool_destroy(zhp, history_str) != 0);
zpool_close(zhp);
@@ -999,10 +1032,13 @@
continue;
}
+ /* The history must be logged as part of the export */
+ log_history = B_FALSE;
+
if (hardforce) {
- if (zpool_export_force(zhp) != 0)
+ if (zpool_export_force(zhp, history_str) != 0)
ret = 1;
- } else if (zpool_export(zhp, force) != 0) {
+ } else if (zpool_export(zhp, force, history_str) != 0) {
ret = 1;
}
@@ -1455,8 +1491,8 @@
break;
case ZPOOL_STATUS_VERSION_OLDER:
- (void) printf(gettext(" status: The pool is formatted using an "
- "older on-disk version.\n"));
+ (void) printf(gettext(" status: The pool is formatted using a "
+ "legacy on-disk version.\n"));
break;
case ZPOOL_STATUS_VERSION_NEWER:
@@ -1464,6 +1500,11 @@
"incompatible version.\n"));
break;
+ case ZPOOL_STATUS_FEAT_DISABLED:
+ (void) printf(gettext(" status: Some supported features are "
+ "not enabled on the pool.\n"));
+ break;
+
case ZPOOL_STATUS_UNSUP_FEAT_READ:
(void) printf(gettext("status: The pool uses the following "
"feature(s) not supported on this sytem:\n"));
@@ -1510,19 +1551,21 @@
* Print out an action according to the overall state of the pool.
*/
if (vs->vs_state == VDEV_STATE_HEALTHY) {
- if (reason == ZPOOL_STATUS_VERSION_OLDER)
+ if (reason == ZPOOL_STATUS_VERSION_OLDER ||
+ reason == ZPOOL_STATUS_FEAT_DISABLED) {
(void) printf(gettext(" action: The pool can be "
"imported using its name or numeric identifier, "
"though\n\tsome features will not be available "
"without an explicit 'zpool upgrade'.\n"));
- else if (reason == ZPOOL_STATUS_HOSTID_MISMATCH)
+ } else if (reason == ZPOOL_STATUS_HOSTID_MISMATCH) {
(void) printf(gettext(" action: The pool can be "
"imported using its name or numeric "
"identifier and\n\tthe '-f' flag.\n"));
- else
+ } else {
(void) printf(gettext(" action: The pool can be "
"imported using its name or numeric "
"identifier.\n"));
+ }
} else if (vs->vs_state == VDEV_STATE_DEGRADED) {
(void) printf(gettext(" action: The pool can be imported "
"despite missing or damaged devices. The\n\tfault "
@@ -3980,12 +4023,13 @@
break;
case ZPOOL_STATUS_VERSION_OLDER:
- (void) printf(gettext("status: The pool is formatted using an "
- "older on-disk format. The pool can\n\tstill be used, but "
- "some features are unavailable.\n"));
+ (void) printf(gettext("status: The pool is formatted using a "
+ "legacy on-disk format. The pool can\n\tstill be used, "
+ "but some features are unavailable.\n"));
(void) printf(gettext("action: Upgrade the pool using 'zpool "
"upgrade'. Once this is done, the\n\tpool will no longer "
- "be accessible on older software versions.\n"));
+ "be accessible on software that does not support feature\n"
+ "\tflags.\n"));
break;
case ZPOOL_STATUS_VERSION_NEWER:
@@ -3997,6 +4041,16 @@
"backup.\n"));
break;
+ case ZPOOL_STATUS_FEAT_DISABLED:
+ (void) printf(gettext("status: Some supported features are not "
+ "enabled on the pool. The pool can\n\tstill be used, but "
+ "some features are unavailable.\n"));
+ (void) printf(gettext("action: Enable all features using "
+ "'zpool upgrade'. Once this is done,\n\tthe pool may no "
+ "longer be accessible by software that does not support\n\t"
+ "the features. See zpool-features(5) for details.\n"));
+ break;
+
case ZPOOL_STATUS_UNSUP_FEAT_READ:
(void) printf(gettext("status: The pool cannot be accessed on "
"this system because it uses the\n\tfollowing feature(s) "
@@ -4226,58 +4280,153 @@
}
typedef struct upgrade_cbdata {
- int cb_all;
int cb_first;
- int cb_newer;
int cb_argc;
uint64_t cb_version;
char **cb_argv;
} upgrade_cbdata_t;
static int
+upgrade_version(zpool_handle_t *zhp, uint64_t version)
+{
+ int ret;
+ nvlist_t *config;
+ uint64_t oldversion;
+
+ config = zpool_get_config(zhp, NULL);
+ verify(nvlist_lookup_uint64(config, ZPOOL_CONFIG_VERSION,
+ &oldversion) == 0);
+
+ assert(SPA_VERSION_IS_SUPPORTED(oldversion));
+ assert(oldversion < version);
+
+ ret = zpool_upgrade(zhp, version);
+ if (ret != 0)
+ return (ret);
+
+ if (version >= SPA_VERSION_FEATURES) {
+ (void) printf(gettext("Successfully upgraded "
+ "'%s' from version %llu to feature flags.\n"),
+ zpool_get_name(zhp), oldversion);
+ } else {
+ (void) printf(gettext("Successfully upgraded "
+ "'%s' from version %llu to version %llu.\n"),
+ zpool_get_name(zhp), oldversion, version);
+ }
+
+ return (0);
+}
+
+static int
+upgrade_enable_all(zpool_handle_t *zhp, int *countp)
+{
+ int i, ret, count;
+ boolean_t firstff = B_TRUE;
+ nvlist_t *enabled = zpool_get_features(zhp);
+
+ count = 0;
+ for (i = 0; i < SPA_FEATURES; i++) {
+ const char *fname = spa_feature_table[i].fi_uname;
+ const char *fguid = spa_feature_table[i].fi_guid;
+ if (!nvlist_exists(enabled, fguid)) {
+ char *propname;
+ verify(-1 != asprintf(&propname, "feature@%s", fname));
+ ret = zpool_set_prop(zhp, propname,
+ ZFS_FEATURE_ENABLED);
+ if (ret != 0) {
+ free(propname);
+ return (ret);
+ }
+ count++;
+
+ if (firstff) {
+ (void) printf(gettext("Enabled the "
+ "following features on '%s':\n"),
+ zpool_get_name(zhp));
+ firstff = B_FALSE;
+ }
+ (void) printf(gettext(" %s\n"), fname);
+ free(propname);
+ }
+ }
+
+ if (countp != NULL)
+ *countp = count;
+ return (0);
+}
+
+static int
upgrade_cb(zpool_handle_t *zhp, void *arg)
{
upgrade_cbdata_t *cbp = arg;
nvlist_t *config;
uint64_t version;
- int ret = 0;
+ boolean_t printnl = B_FALSE;
+ int ret;
config = zpool_get_config(zhp, NULL);
verify(nvlist_lookup_uint64(config, ZPOOL_CONFIG_VERSION,
&version) == 0);
- if (!cbp->cb_newer && SPA_VERSION_IS_SUPPORTED(version) &&
- version != SPA_VERSION) {
- if (!cbp->cb_all) {
- if (cbp->cb_first) {
- (void) printf(gettext("The following pools are "
- "out of date, and can be upgraded. After "
- "being\nupgraded, these pools will no "
- "longer be accessible by older software "
- "versions.\n\n"));
- (void) printf(gettext("VER POOL\n"));
- (void) printf(gettext("--- ------------\n"));
- cbp->cb_first = B_FALSE;
- }
-
- (void) printf("%2llu %s\n", (u_longlong_t)version,
- zpool_get_name(zhp));
- } else {
+ assert(SPA_VERSION_IS_SUPPORTED(version));
+
+ if (version < cbp->cb_version) {
+ cbp->cb_first = B_FALSE;
+ ret = upgrade_version(zhp, cbp->cb_version);
+ if (ret != 0)
+ return (ret);
+ printnl = B_TRUE;
+
+ /*
+ * If they did "zpool upgrade -a", then we could
+ * be doing ioctls to different pools. We need
+ * to log this history once to each pool, and bypass
+ * the normal history logging that happens in main().
+ */
+ (void) zpool_log_history(g_zfs, history_str);
+ log_history = B_FALSE;
+ }
+
+ if (cbp->cb_version >= SPA_VERSION_FEATURES) {
+ int count;
+ ret = upgrade_enable_all(zhp, &count);
+ if (ret != 0)
+ return (ret);
+
+ if (count > 0) {
cbp->cb_first = B_FALSE;
- ret = zpool_upgrade(zhp, cbp->cb_version);
- if (!ret) {
- (void) printf(gettext("Successfully upgraded "
- "'%s'\n\n"), zpool_get_name(zhp));
- }
+ printnl = B_TRUE;
}
- } else if (cbp->cb_newer && !SPA_VERSION_IS_SUPPORTED(version)) {
- assert(!cbp->cb_all);
-
+ }
+
+ if (printnl) {
+ (void) printf(gettext("\n"));
+ }
+
+ return (0);
+}
+
+static int
+upgrade_list_older_cb(zpool_handle_t *zhp, void *arg)
+{
+ upgrade_cbdata_t *cbp = arg;
+ nvlist_t *config;
+ uint64_t version;
+
+ config = zpool_get_config(zhp, NULL);
+ verify(nvlist_lookup_uint64(config, ZPOOL_CONFIG_VERSION,
+ &version) == 0);
+
+ assert(SPA_VERSION_IS_SUPPORTED(version));
+
+ if (version < SPA_VERSION_FEATURES) {
if (cbp->cb_first) {
(void) printf(gettext("The following pools are "
- "formatted using an unsupported software version "
- "and\ncannot be accessed on the current "
- "system.\n\n"));
+ "formatted with legacy version numbers and can\n"
+ "be upgraded to use feature flags. After "
+ "being upgraded, these pools\nwill no "
+ "longer be accessible by software that does not "
+ "support feature\nflags.\n\n"));
(void) printf(gettext("VER POOL\n"));
(void) printf(gettext("--- ------------\n"));
cbp->cb_first = B_FALSE;
@@ -4287,14 +4436,65 @@
zpool_get_name(zhp));
}
- zpool_close(zhp);
- return (ret);
+ return (0);
+}
+
+static int
+upgrade_list_disabled_cb(zpool_handle_t *zhp, void *arg)
+{
+ upgrade_cbdata_t *cbp = arg;
+ nvlist_t *config;
+ uint64_t version;
+
+ config = zpool_get_config(zhp, NULL);
+ verify(nvlist_lookup_uint64(config, ZPOOL_CONFIG_VERSION,
+ &version) == 0);
+
+ if (version >= SPA_VERSION_FEATURES) {
+ int i;
+ boolean_t poolfirst = B_TRUE;
+ nvlist_t *enabled = zpool_get_features(zhp);
+
+ for (i = 0; i < SPA_FEATURES; i++) {
+ const char *fguid = spa_feature_table[i].fi_guid;
+ const char *fname = spa_feature_table[i].fi_uname;
+ if (!nvlist_exists(enabled, fguid)) {
+ if (cbp->cb_first) {
+ (void) printf(gettext("\nSome "
+ "supported features are not "
+ "enabled on the following pools. "
+ "Once a\nfeature is enabled the "
+ "pool may become incompatible with "
+ "software\nthat does not support "
+ "the feature. See "
+ "zpool-features(5) for "
+ "details.\n\n"));
+ (void) printf(gettext("POOL "
+ "FEATURE\n"));
+ (void) printf(gettext("------"
+ "---------\n"));
+ cbp->cb_first = B_FALSE;
+ }
+
+ if (poolfirst) {
+ (void) printf(gettext("%s\n"),
+ zpool_get_name(zhp));
+ poolfirst = B_FALSE;
+ }
+
+ (void) printf(gettext(" %s\n"), fname);
+ }
+ }
+ }
+
+ return (0);
}
/* ARGSUSED */
static int
upgrade_one(zpool_handle_t *zhp, void *data)
{
+ boolean_t printnl = B_FALSE;
upgrade_cbdata_t *cbp = data;
uint64_t cur_version;
int ret;
@@ -4309,26 +4509,45 @@
cur_version = zpool_get_prop_int(zhp, ZPOOL_PROP_VERSION, NULL);
if (cur_version > cbp->cb_version) {
(void) printf(gettext("Pool '%s' is already formatted "
- "using more current version '%llu'.\n"),
+ "using more current version '%llu'.\n\n"),
zpool_get_name(zhp), cur_version);
return (0);
}
- if (cur_version == cbp->cb_version) {
+
+ if (cbp->cb_version != SPA_VERSION && cur_version == cbp->cb_version) {
(void) printf(gettext("Pool '%s' is already formatted "
- "using the current version.\n"), zpool_get_name(zhp));
+ "using version %llu.\n\n"), zpool_get_name(zhp),
+ cbp->cb_version);
return (0);
}
- ret = zpool_upgrade(zhp, cbp->cb_version);
-
- if (!ret) {
- (void) printf(gettext("Successfully upgraded '%s' "
- "from version %llu to version %llu\n\n"),
- zpool_get_name(zhp), (u_longlong_t)cur_version,
- (u_longlong_t)cbp->cb_version);
+ if (cur_version != cbp->cb_version) {
+ printnl = B_TRUE;
+ ret = upgrade_version(zhp, cbp->cb_version);
+ if (ret != 0)
+ return (ret);
}
- return (ret != 0);
+ if (cbp->cb_version >= SPA_VERSION_FEATURES) {
+ int count = 0;
+ ret = upgrade_enable_all(zhp, &count);
+ if (ret != 0)
+ return (ret);
+
+ if (count != 0) {
+ printnl = B_TRUE;
+ } else if (cur_version == SPA_VERSION) {
+ (void) printf(gettext("Pool '%s' already has all "
+ "supported features enabled.\n"),
+ zpool_get_name(zhp));
+ }
+ }
+
+ if (printnl) {
+ (void) printf(gettext("\n"));
+ }
+
+ return (0);
}
/*
@@ -4347,6 +4566,7 @@
upgrade_cbdata_t cb = { 0 };
int ret = 0;
boolean_t showversions = B_FALSE;
+ boolean_t upgradeall = B_FALSE;
char *end;
@@ -4354,7 +4574,7 @@
while ((c = getopt(argc, argv, ":avV:")) != -1) {
switch (c) {
case 'a':
- cb.cb_all = B_TRUE;
+ upgradeall = B_TRUE;
break;
case 'v':
showversions = B_TRUE;
@@ -4387,19 +4607,19 @@
if (cb.cb_version == 0) {
cb.cb_version = SPA_VERSION;
- } else if (!cb.cb_all && argc == 0) {
+ } else if (!upgradeall && argc == 0) {
(void) fprintf(stderr, gettext("-V option is "
"incompatible with other arguments\n"));
usage(B_FALSE);
}
if (showversions) {
- if (cb.cb_all || argc != 0) {
+ if (upgradeall || argc != 0) {
(void) fprintf(stderr, gettext("-v option is "
"incompatible with other arguments\n"));
usage(B_FALSE);
}
- } else if (cb.cb_all) {
+ } else if (upgradeall) {
if (argc != 0) {
(void) fprintf(stderr, gettext("-a option should not "
"be used along with a pool name\n"));
@@ -4409,9 +4629,25 @@
(void) printf(gettext("This system supports ZFS pool feature "
"flags.\n\n"));
- cb.cb_first = B_TRUE;
if (showversions) {
- (void) printf(gettext("The following versions are "
+ int i;
+
+ (void) printf(gettext("The following features are "
+ "supported:\n\n"));
+ (void) printf(gettext("FEAT DESCRIPTION\n"));
+ (void) printf("----------------------------------------------"
+ "---------------\n");
+ for (i = 0; i < SPA_FEATURES; i++) {
+ zfeature_info_t *fi = &spa_feature_table[i];
+ const char *ro = fi->fi_can_readonly ?
+ " (read-only compatible)" : "";
+
+ (void) printf("%-37s%s\n", fi->fi_uname, ro);
+ (void) printf(" %s\n", fi->fi_desc);
+ }
+ (void) printf("\n");
+
+ (void) printf(gettext("The following legacy versions are also "
"supported:\n\n"));
(void) printf(gettext("VER DESCRIPTION\n"));
(void) printf("--- -----------------------------------------"
@@ -4454,32 +4690,44 @@
(void) printf(gettext("\nFor more information on a particular "
"version, including supported releases,\n"));
(void) printf(gettext("see the ZFS Administration Guide.\n\n"));
- } else if (argc == 0) {
- int notfound;
-
+ } else if (argc == 0 && upgradeall) {
+ cb.cb_first = B_TRUE;
ret = zpool_iter(g_zfs, upgrade_cb, &cb);
- notfound = cb.cb_first;
-
- if (!cb.cb_all && ret == 0) {
- if (!cb.cb_first)
- (void) printf("\n");
- cb.cb_first = B_TRUE;
- cb.cb_newer = B_TRUE;
- ret = zpool_iter(g_zfs, upgrade_cb, &cb);
- if (!cb.cb_first) {
- notfound = B_FALSE;
- (void) printf("\n");
+ if (ret == 0 && cb.cb_first) {
+ if (cb.cb_version == SPA_VERSION) {
+ (void) printf(gettext("All pools are already "
+ "formatted using feature flags.\n\n"));
+ (void) printf(gettext("Every feature flags "
+ "pool already has all supported features "
+ "enabled.\n"));
+ } else {
+ (void) printf(gettext("All pools are already "
+ "formatted with version %llu or higher.\n"),
+ cb.cb_version);
}
}
-
- if (ret == 0) {
- if (notfound)
- (void) printf(gettext("All pools are formatted "
- "using this version.\n"));
- else if (!cb.cb_all)
- (void) printf(gettext("Use 'zpool upgrade -v' "
- "for a list of available versions and "
- "their associated\nfeatures.\n"));
+ } else if (argc == 0) {
+ cb.cb_first = B_TRUE;
+ ret = zpool_iter(g_zfs, upgrade_list_older_cb, &cb);
+ assert(ret == 0);
+
+ if (cb.cb_first) {
+ (void) printf(gettext("All pools are formatted "
+ "using feature flags.\n\n"));
+ } else {
+ (void) printf(gettext("\nUse 'zpool upgrade -v' "
+ "for a list of available legacy versions.\n"));
+ }
+
+ cb.cb_first = B_TRUE;
+ ret = zpool_iter(g_zfs, upgrade_list_disabled_cb, &cb);
+ assert(ret == 0);
+
+ if (cb.cb_first) {
+ (void) printf(gettext("Every feature flags pool has "
+ "all supported features enabled.\n"));
+ } else {
+ (void) printf(gettext("\n"));
}
} else {
ret = for_each_pool(argc, argv, B_FALSE, NULL,
@@ -4491,8 +4739,8 @@
typedef struct hist_cbdata {
boolean_t first;
- int longfmt;
- int internal;
+ boolean_t longfmt;
+ boolean_t internal;
} hist_cbdata_t;
/*
@@ -4504,21 +4752,8 @@
nvlist_t *nvhis;
nvlist_t **records;
uint_t numrecords;
- char *cmdstr;
- char *pathstr;
- uint64_t dst_time;
- time_t tsec;
- struct tm t;
- char tbuf[30];
int ret, i;
- uint64_t who;
- struct passwd *pwd;
- char *hostname;
- char *zonename;
- char internalstr[MAXPATHLEN];
hist_cbdata_t *cb = (hist_cbdata_t *)data;
- uint64_t txg;
- uint64_t ievent;
cb->first = B_FALSE;
@@ -4530,64 +4765,94 @@
verify(nvlist_lookup_nvlist_array(nvhis, ZPOOL_HIST_RECORD,
&records, &numrecords) == 0);
for (i = 0; i < numrecords; i++) {
- if (nvlist_lookup_uint64(records[i], ZPOOL_HIST_TIME,
- &dst_time) != 0)
- continue;
-
- /* is it an internal event or a standard event? */
- if (nvlist_lookup_string(records[i], ZPOOL_HIST_CMD,
- &cmdstr) != 0) {
- if (cb->internal == 0)
+ nvlist_t *rec = records[i];
+ char tbuf[30] = "";
+
+ if (nvlist_exists(rec, ZPOOL_HIST_TIME)) {
+ time_t tsec;
+ struct tm t;
+
+ tsec = fnvlist_lookup_uint64(records[i],
+ ZPOOL_HIST_TIME);
+ (void) localtime_r(&tsec, &t);
+ (void) strftime(tbuf, sizeof (tbuf), "%F.%T", &t);
+ }
+
+ if (nvlist_exists(rec, ZPOOL_HIST_CMD)) {
+ (void) printf("%s %s", tbuf,
+ fnvlist_lookup_string(rec, ZPOOL_HIST_CMD));
+ } else if (nvlist_exists(rec, ZPOOL_HIST_INT_EVENT)) {
+ int ievent =
+ fnvlist_lookup_uint64(rec, ZPOOL_HIST_INT_EVENT);
+ if (!cb->internal)
continue;
-
- if (nvlist_lookup_uint64(records[i],
- ZPOOL_HIST_INT_EVENT, &ievent) != 0)
+ if (ievent >= ZFS_NUM_LEGACY_HISTORY_EVENTS) {
+ (void) printf("%s unrecognized record:\n",
+ tbuf);
+ dump_nvlist(rec, 4);
+ continue;
+ }
+ (void) printf("%s [internal %s txg:%lld] %s", tbuf,
+ zfs_history_event_names[ievent],
+ fnvlist_lookup_uint64(rec, ZPOOL_HIST_TXG),
+ fnvlist_lookup_string(rec, ZPOOL_HIST_INT_STR));
+ } else if (nvlist_exists(rec, ZPOOL_HIST_INT_NAME)) {
+ if (!cb->internal)
continue;
- verify(nvlist_lookup_uint64(records[i],
- ZPOOL_HIST_TXG, &txg) == 0);
- verify(nvlist_lookup_string(records[i],
- ZPOOL_HIST_INT_STR, &pathstr) == 0);
- if (ievent >= LOG_END)
+ (void) printf("%s [txg:%lld] %s", tbuf,
+ fnvlist_lookup_uint64(rec, ZPOOL_HIST_TXG),
+ fnvlist_lookup_string(rec, ZPOOL_HIST_INT_NAME));
+ if (nvlist_exists(rec, ZPOOL_HIST_DSNAME)) {
+ (void) printf(" %s (%llu)",
+ fnvlist_lookup_string(rec,
+ ZPOOL_HIST_DSNAME),
+ fnvlist_lookup_uint64(rec,
+ ZPOOL_HIST_DSID));
+ }
+ (void) printf(" %s", fnvlist_lookup_string(rec,
+ ZPOOL_HIST_INT_STR));
+ } else if (nvlist_exists(rec, ZPOOL_HIST_IOCTL)) {
+ if (!cb->internal)
continue;
- (void) snprintf(internalstr,
- sizeof (internalstr),
- "[internal %s txg:%lld] %s",
- zfs_history_event_names[ievent], txg,
- pathstr);
- cmdstr = internalstr;
+ (void) printf("%s ioctl %s\n", tbuf,
+ fnvlist_lookup_string(rec, ZPOOL_HIST_IOCTL));
+ if (nvlist_exists(rec, ZPOOL_HIST_INPUT_NVL)) {
+ (void) printf(" input:\n");
+ dump_nvlist(fnvlist_lookup_nvlist(rec,
+ ZPOOL_HIST_INPUT_NVL), 8);
+ }
+ if (nvlist_exists(rec, ZPOOL_HIST_OUTPUT_NVL)) {
+ (void) printf(" output:\n");
+ dump_nvlist(fnvlist_lookup_nvlist(rec,
+ ZPOOL_HIST_OUTPUT_NVL), 8);
+ }
+ } else {
+ if (!cb->internal)
+ continue;
+ (void) printf("%s unrecognized record:\n", tbuf);
+ dump_nvlist(rec, 4);
}
- tsec = dst_time;
- (void) localtime_r(&tsec, &t);
- (void) strftime(tbuf, sizeof (tbuf), "%F.%T", &t);
- (void) printf("%s %s", tbuf, cmdstr);
if (!cb->longfmt) {
(void) printf("\n");
continue;
}
(void) printf(" [");
- if (nvlist_lookup_uint64(records[i],
- ZPOOL_HIST_WHO, &who) == 0) {
- pwd = getpwuid((uid_t)who);
- if (pwd)
- (void) printf("user %s on",
- pwd->pw_name);
- else
- (void) printf("user %d on",
- (int)who);
- } else {
- (void) printf(gettext("no info]\n"));
- continue;
+ if (nvlist_exists(rec, ZPOOL_HIST_WHO)) {
+ uid_t who = fnvlist_lookup_uint64(rec, ZPOOL_HIST_WHO);
+ struct passwd *pwd = getpwuid(who);
+ (void) printf("user %d ", (int)who);
+ if (pwd != NULL)
+ (void) printf("(%s) ", pwd->pw_name);
}
- if (nvlist_lookup_string(records[i],
- ZPOOL_HIST_HOST, &hostname) == 0) {
- (void) printf(" %s", hostname);
+ if (nvlist_exists(rec, ZPOOL_HIST_HOST)) {
+ (void) printf("on %s",
+ fnvlist_lookup_string(rec, ZPOOL_HIST_HOST));
}
- if (nvlist_lookup_string(records[i],
- ZPOOL_HIST_ZONE, &zonename) == 0) {
- (void) printf(":%s", zonename);
+ if (nvlist_exists(rec, ZPOOL_HIST_ZONE)) {
+ (void) printf(":%s",
+ fnvlist_lookup_string(rec, ZPOOL_HIST_ZONE));
}
-
(void) printf("]");
(void) printf("\n");
}
@@ -4602,8 +4867,6 @@
*
* Displays the history of commands that modified pools.
*/
-
-
int
zpool_do_history(int argc, char **argv)
{
@@ -4616,10 +4879,10 @@
while ((c = getopt(argc, argv, "li")) != -1) {
switch (c) {
case 'l':
- cbdata.longfmt = 1;
+ cbdata.longfmt = B_TRUE;
break;
case 'i':
- cbdata.internal = 1;
+ cbdata.internal = B_TRUE;
break;
case '?':
(void) fprintf(stderr, gettext("invalid option '%c'\n"),
@@ -4844,8 +5107,7 @@
if (strcmp(cmdname, "-?") == 0)
usage(B_TRUE);
- zpool_set_history_str("zpool", argc, argv, history_str);
- verify(zpool_stage_history(g_zfs, history_str) == 0);
+ zfs_save_arguments(argc, argv, history_str, sizeof (history_str));
/*
* Run the appropriate command.
@@ -4872,6 +5134,9 @@
usage(B_FALSE);
}
+ if (ret == 0 && log_history)
+ (void) zpool_log_history(g_zfs, history_str);
+
libzfs_fini(g_zfs);
/*
--- a/usr/src/cmd/ztest/ztest.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/cmd/ztest/ztest.c Sun Aug 12 11:56:48 2012 +0100
@@ -2252,7 +2252,7 @@
*/
nvroot = make_vdev_root("/dev/bogus", NULL, 0, 0, 0, 0, 0, 1);
VERIFY3U(ENOENT, ==,
- spa_create("ztest_bad_file", nvroot, NULL, NULL, NULL));
+ spa_create("ztest_bad_file", nvroot, NULL, NULL));
nvlist_free(nvroot);
/*
@@ -2260,7 +2260,7 @@
*/
nvroot = make_vdev_root("/dev/bogus", NULL, 0, 0, 0, 0, 2, 1);
VERIFY3U(ENOENT, ==,
- spa_create("ztest_bad_mirror", nvroot, NULL, NULL, NULL));
+ spa_create("ztest_bad_mirror", nvroot, NULL, NULL));
nvlist_free(nvroot);
/*
@@ -2269,7 +2269,7 @@
*/
(void) rw_rdlock(&ztest_name_lock);
nvroot = make_vdev_root("/dev/bogus", NULL, 0, 0, 0, 0, 0, 1);
- VERIFY3U(EEXIST, ==, spa_create(zo->zo_pool, nvroot, NULL, NULL, NULL));
+ VERIFY3U(EEXIST, ==, spa_create(zo->zo_pool, nvroot, NULL, NULL));
nvlist_free(nvroot);
VERIFY3U(0, ==, spa_open(zo->zo_pool, &spa, FTAG));
VERIFY3U(EBUSY, ==, spa_destroy(zo->zo_pool));
@@ -3056,8 +3056,7 @@
(void) snprintf(snapname, MAXNAMELEN, "%s@%llu", osname,
(u_longlong_t)id);
- error = dmu_objset_snapshot(osname, strchr(snapname, '@') + 1,
- NULL, NULL, B_FALSE, B_FALSE, -1);
+ error = dmu_objset_snapshot_one(osname, strchr(snapname, '@') + 1);
if (error == ENOSPC) {
ztest_record_enospc(FTAG);
return (B_FALSE);
@@ -3257,8 +3256,7 @@
(void) snprintf(clone2name, MAXNAMELEN, "%s/c2_%llu", osname, id);
(void) snprintf(snap3name, MAXNAMELEN, "%s@s3_%llu", clone1name, id);
- error = dmu_objset_snapshot(osname, strchr(snap1name, '@')+1,
- NULL, NULL, B_FALSE, B_FALSE, -1);
+ error = dmu_objset_snapshot_one(osname, strchr(snap1name, '@') + 1);
if (error && error != EEXIST) {
if (error == ENOSPC) {
ztest_record_enospc(FTAG);
@@ -3281,8 +3279,7 @@
fatal(0, "dmu_objset_create(%s) = %d", clone1name, error);
}
- error = dmu_objset_snapshot(clone1name, strchr(snap2name, '@')+1,
- NULL, NULL, B_FALSE, B_FALSE, -1);
+ error = dmu_objset_snapshot_one(clone1name, strchr(snap2name, '@') + 1);
if (error && error != EEXIST) {
if (error == ENOSPC) {
ztest_record_enospc(FTAG);
@@ -3291,8 +3288,7 @@
fatal(0, "dmu_open_snapshot(%s) = %d", snap2name, error);
}
- error = dmu_objset_snapshot(clone1name, strchr(snap3name, '@')+1,
- NULL, NULL, B_FALSE, B_FALSE, -1);
+ error = dmu_objset_snapshot_one(clone1name, strchr(snap3name, '@') + 1);
if (error && error != EEXIST) {
if (error == ENOSPC) {
ztest_record_enospc(FTAG);
@@ -4480,8 +4476,7 @@
* Create snapshot, clone it, mark snap for deferred destroy,
* destroy clone, verify snap was also destroyed.
*/
- error = dmu_objset_snapshot(osname, snapname, NULL, NULL, FALSE,
- FALSE, -1);
+ error = dmu_objset_snapshot_one(osname, snapname);
if (error) {
if (error == ENOSPC) {
ztest_record_enospc("dmu_objset_snapshot");
@@ -4523,8 +4518,7 @@
* destroy a held snapshot, mark for deferred destroy,
* release hold, verify snapshot was destroyed.
*/
- error = dmu_objset_snapshot(osname, snapname, NULL, NULL, FALSE,
- FALSE, -1);
+ error = dmu_objset_snapshot_one(osname, snapname);
if (error) {
if (error == ENOSPC) {
ztest_record_enospc("dmu_objset_snapshot");
@@ -5612,8 +5606,7 @@
spa_feature_table[i].fi_uname);
VERIFY3U(0, ==, nvlist_add_uint64(props, buf, 0));
}
- VERIFY3U(0, ==, spa_create(ztest_opts.zo_pool, nvroot, props,
- NULL, NULL));
+ VERIFY3U(0, ==, spa_create(ztest_opts.zo_pool, nvroot, props, NULL));
nvlist_free(nvroot);
VERIFY3U(0, ==, spa_open(ztest_opts.zo_pool, &spa, FTAG));
--- a/usr/src/common/zfs/zfs_comutil.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/common/zfs/zfs_comutil.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
/*
@@ -157,7 +158,11 @@
return (version);
}
-const char *zfs_history_event_names[LOG_END] = {
+/*
+ * This is the table of legacy internal event names; it should not be modified.
+ * The internal events are now stored in the history log as strings.
+ */
+const char *zfs_history_event_names[ZFS_NUM_LEGACY_HISTORY_EVENTS] = {
"invalid event",
"pool create",
"vdev add",
--- a/usr/src/common/zfs/zfs_comutil.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/common/zfs/zfs_comutil.h Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#ifndef _ZFS_COMUTIL_H
@@ -37,7 +38,8 @@
extern int zfs_zpl_version_map(int spa_version);
extern int zfs_spa_version_map(int zpl_version);
-extern const char *zfs_history_event_names[LOG_END];
+#define ZFS_NUM_LEGACY_HISTORY_EVENTS 41
+extern const char *zfs_history_event_names[ZFS_NUM_LEGACY_HISTORY_EVENTS];
#ifdef __cplusplus
}
--- a/usr/src/common/zfs/zprop_common.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/common/zfs/zprop_common.c Sun Aug 12 11:56:48 2012 +0100
@@ -22,6 +22,9 @@
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
/*
* Common routines used by zfs and zpool property management.
@@ -129,7 +132,8 @@
zprop_attr_t attr, int objset_types, const char *colname)
{
zprop_register_impl(prop, name, type, 0, NULL, attr,
- objset_types, NULL, colname, B_FALSE, B_FALSE, NULL);
+ objset_types, NULL, colname,
+ type == PROP_TYPE_NUMBER, B_FALSE, NULL);
}
--- a/usr/src/lib/Makefile Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/Makefile Sun Aug 12 11:56:48 2012 +0100
@@ -21,6 +21,7 @@
# Copyright 2011 Nexenta Systems, Inc. All rights reserved.
# Copyright (c) 1989, 2010, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2012 by Delphix. All rights reserved.
include ../Makefile.master
@@ -234,9 +235,10 @@
sasl_plugins \
udapl \
libzpool \
+ libzfs_core \
libzfs \
- libbe \
- pylibbe \
+ libbe \
+ pylibbe \
libzfs_jni \
pyzfs \
pysolaris \
@@ -474,6 +476,7 @@
libwrap \
libxcurses2 \
libzfs \
+ libzfs_core \
libzfs_jni \
libzoneinfo \
libzonestat \
@@ -638,7 +641,8 @@
print: libldap5
udapl/udapl_tavor: udapl/libdat
libzfs: libdevid libgen libnvpair libuutil \
- libadm libavl libefi libidmap libmd
+ libadm libavl libefi libidmap libmd libzfs_core
+libzfs_core: libnvpair
libzfs_jni: libdiskmgt libnvpair libzfs
libzpool: libavl libumem libnvpair libcmdutils
libsec: libavl libidmap
--- a/usr/src/lib/libdtrace/Makefile.com Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/Makefile.com Sun Aug 12 11:56:48 2012 +0100
@@ -20,7 +20,7 @@
#
#
# Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
-# Copyright (c) 2011 by Delphix. All rights reserved.
+# Copyright (c) 2012 by Delphix. All rights reserved.
#
LIBRARY = libdtrace.a
@@ -52,6 +52,7 @@
dt_parser.c \
dt_pcb.c \
dt_pid.c \
+ dt_pq.c \
dt_pragma.c \
dt_print.c \
dt_printf.c \
--- a/usr/src/lib/libdtrace/common/dt_aggregate.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_aggregate.c Sun Aug 12 11:56:48 2012 +0100
@@ -26,6 +26,7 @@
/*
* Copyright (c) 2011, Joyent, Inc. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#include <stdlib.h>
@@ -884,33 +885,14 @@
caddr_t rdata = rh->dtahe_data.dtada_data;
dtrace_recdesc_t *lrec, *rrec;
int64_t *laddr, *raddr;
- int rval, i;
-
- if ((rval = dt_aggregate_hashcmp(lhs, rhs)) != 0)
- return (rval);
+ int rval;
- if (lagg->dtagd_nrecs > ragg->dtagd_nrecs)
- return (DT_GREATERTHAN);
-
- if (lagg->dtagd_nrecs < ragg->dtagd_nrecs)
- return (DT_LESSTHAN);
+ assert(lagg->dtagd_nrecs == ragg->dtagd_nrecs);
- for (i = 0; i < lagg->dtagd_nrecs; i++) {
- lrec = &lagg->dtagd_rec[i];
- rrec = &ragg->dtagd_rec[i];
-
- if (lrec->dtrd_offset < rrec->dtrd_offset)
- return (DT_LESSTHAN);
+ lrec = &lagg->dtagd_rec[lagg->dtagd_nrecs - 1];
+ rrec = &ragg->dtagd_rec[ragg->dtagd_nrecs - 1];
- if (lrec->dtrd_offset > rrec->dtrd_offset)
- return (DT_GREATERTHAN);
-
- if (lrec->dtrd_action < rrec->dtrd_action)
- return (DT_LESSTHAN);
-
- if (lrec->dtrd_action > rrec->dtrd_action)
- return (DT_GREATERTHAN);
- }
+ assert(lrec->dtrd_action == rrec->dtrd_action);
laddr = (int64_t *)(uintptr_t)(ldata + lrec->dtrd_offset);
raddr = (int64_t *)(uintptr_t)(rdata + rrec->dtrd_offset);
--- a/usr/src/lib/libdtrace/common/dt_cc.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_cc.c Sun Aug 12 11:56:48 2012 +0100
@@ -22,7 +22,7 @@
/*
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2011, Joyent Inc. All rights reserved.
- * Copyright (c) 2011 by Delphix. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
/*
@@ -663,63 +663,48 @@
dt_action_trace(dtrace_hdl_t *dtp, dt_node_t *dnp, dtrace_stmtdesc_t *sdp)
{
dtrace_actdesc_t *ap = dt_stmt_action(dtp, sdp);
+ boolean_t istrace = (dnp->dn_ident->di_id == DT_ACT_TRACE);
+ const char *act = istrace ? "trace" : "print";
if (dt_node_is_void(dnp->dn_args)) {
- dnerror(dnp->dn_args, D_TRACE_VOID,
- "trace( ) may not be applied to a void expression\n");
+ dnerror(dnp->dn_args, istrace ? D_TRACE_VOID : D_PRINT_VOID,
+ "%s( ) may not be applied to a void expression\n", act);
}
- if (dt_node_is_dynamic(dnp->dn_args)) {
- dnerror(dnp->dn_args, D_TRACE_DYN,
- "trace( ) may not be applied to a dynamic expression\n");
+ if (dt_node_resolve(dnp->dn_args, DT_IDENT_XLPTR) != NULL) {
+ dnerror(dnp->dn_args, istrace ? D_TRACE_DYN : D_PRINT_DYN,
+ "%s( ) may not be applied to a translated pointer\n", act);
}
dt_cg(yypcb, dnp->dn_args);
- ap->dtad_difo = dt_as(yypcb);
- ap->dtad_kind = DTRACEACT_DIFEXPR;
-}
-
-/*
- * The print() action behaves identically to trace(), except that it stores the
- * CTF type of the argument (if present) within the DOF for the DIFEXPR action.
- * To do this, we set the 'dtsd_strdata' to point to the fully-qualified CTF
- * type ID for the result of the DIF action. We use the ID instead of the name
- * to handles complex types like arrays and function pointers that can't be
- * resolved by ctf_type_lookup(). This is later processed by
- * dtrace_dof_create() and turned into a reference into the string table so
- * that we can get the type information when we process the data after the
- * fact.
- */
-static void
-dt_action_print(dtrace_hdl_t *dtp, dt_node_t *dnp, dtrace_stmtdesc_t *sdp)
-{
- dtrace_actdesc_t *ap = dt_stmt_action(dtp, sdp);
- dt_node_t *dret;
- size_t len;
- dt_module_t *dmp;
-
- if (dt_node_is_void(dnp->dn_args)) {
- dnerror(dnp->dn_args, D_PRINT_VOID,
- "print( ) may not be applied to a void expression\n");
+
+ /*
+ * The print() action behaves identically to trace(), except that it
+ * stores the CTF type of the argument (if present) within the DOF for
+ * the DIFEXPR action. To do this, we set the 'dtsd_strdata' to point
+ * to the fully-qualified CTF type ID for the result of the DIF
+ * action. We use the ID instead of the name to handles complex types
+ * like arrays and function pointers that can't be resolved by
+ * ctf_type_lookup(). This is later processed by dtrace_dof_create()
+ * and turned into a reference into the string table so that we can
+ * get the type information when we process the data after the fact.
+ */
+ if (dnp->dn_ident->di_id == DT_ACT_PRINT) {
+ dt_node_t *dret;
+ size_t n;
+ dt_module_t *dmp;
+
+ dret = yypcb->pcb_dret;
+ dmp = dt_module_lookup_by_ctf(dtp, dret->dn_ctfp);
+
+ n = snprintf(NULL, 0, "%s`%d", dmp->dm_name, dret->dn_type) + 1;
+ sdp->dtsd_strdata = dt_alloc(dtp, n);
+ if (sdp->dtsd_strdata == NULL)
+ longjmp(yypcb->pcb_jmpbuf, EDT_NOMEM);
+ (void) snprintf(sdp->dtsd_strdata, n, "%s`%d", dmp->dm_name,
+ dret->dn_type);
}
- if (dt_node_is_dynamic(dnp->dn_args)) {
- dnerror(dnp->dn_args, D_PRINT_DYN,
- "print( ) may not be applied to a dynamic expression\n");
- }
-
- dt_cg(yypcb, dnp->dn_args);
-
- dret = yypcb->pcb_dret;
- dmp = dt_module_lookup_by_ctf(dtp, dret->dn_ctfp);
-
- len = snprintf(NULL, 0, "%s`%d", dmp->dm_name, dret->dn_type) + 1;
- sdp->dtsd_strdata = dt_alloc(dtp, len);
- if (sdp->dtsd_strdata == NULL)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOMEM);
- (void) snprintf(sdp->dtsd_strdata, len, "%s`%d", dmp->dm_name,
- dret->dn_type);
-
ap->dtad_difo = dt_as(yypcb);
ap->dtad_kind = DTRACEACT_DIFEXPR;
}
@@ -1073,6 +1058,9 @@
case DT_ACT_PANIC:
dt_action_panic(dtp, dnp->dn_expr, sdp);
break;
+ case DT_ACT_PRINT:
+ dt_action_trace(dtp, dnp->dn_expr, sdp);
+ break;
case DT_ACT_PRINTA:
dt_action_printa(dtp, dnp->dn_expr, sdp);
break;
@@ -1103,9 +1091,6 @@
case DT_ACT_TRACE:
dt_action_trace(dtp, dnp->dn_expr, sdp);
break;
- case DT_ACT_PRINT:
- dt_action_print(dtp, dnp->dn_expr, sdp);
- break;
case DT_ACT_TRACEMEM:
dt_action_tracemem(dtp, dnp->dn_expr, sdp);
break;
@@ -2462,7 +2447,8 @@
}
out:
- if (context != DT_CTX_DTYPE && DT_TREEDUMP_PASS(dtp, 3))
+ if (context != DT_CTX_DTYPE && yypcb->pcb_root != NULL &&
+ DT_TREEDUMP_PASS(dtp, 3))
dt_node_printr(yypcb->pcb_root, stderr, 0);
if (dtp->dt_cdefs_fd != -1 && (ftruncate64(dtp->dt_cdefs_fd, 0) == -1 ||
--- a/usr/src/lib/libdtrace/common/dt_cg.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_cg.c Sun Aug 12 11:56:48 2012 +0100
@@ -19,12 +19,15 @@
*
* CDDL HEADER END
*/
+
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
-#pragma ident "%Z%%M% %I% %E% SMI"
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
#include <sys/types.h>
#include <sys/sysmacros.h>
@@ -193,9 +196,6 @@
ssize_t size;
int sreg;
- if ((sreg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
-
type = ctf_type_resolve(ctfp, dnp->dn_type);
kind = ctf_type_kind(ctfp, type);
assert(kind == CTF_K_POINTER || kind == CTF_K_ARRAY);
@@ -212,6 +212,7 @@
if ((size = ctf_type_size(ctfp, type)) == 1)
return; /* multiply or divide by one can be omitted */
+ sreg = dt_regset_alloc(drp);
dt_cg_setx(dlp, sreg, size);
instr = DIF_INSTR_FMT(op, dreg, sreg, dreg);
dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
@@ -251,9 +252,7 @@
assert(dnp->dn_op == DT_TOK_PTR || dnp->dn_op == DT_TOK_DOT);
r1 = dnp->dn_left->dn_reg;
-
- if ((r2 = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ r2 = dt_regset_alloc(drp);
/*
* On little-endian architectures, ctm_offset counts from the right so
@@ -356,10 +355,9 @@
"bits %u\n", m.ctm_offset, m.ctm_type, e.cte_bits);
}
- if ((r1 = dt_regset_alloc(drp)) == -1 ||
- (r2 = dt_regset_alloc(drp)) == -1 ||
- (r3 = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ r1 = dt_regset_alloc(drp);
+ r2 = dt_regset_alloc(drp);
+ r3 = dt_regset_alloc(drp);
/*
* Compute shifts and masks. We need to compute "shift" as the amount
@@ -423,8 +421,7 @@
size = dt_node_type_size(src);
if (src->dn_flags & DT_NF_REF) {
- if ((reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ reg = dt_regset_alloc(drp);
dt_cg_setx(dlp, reg, size);
instr = DIF_INSTR_COPYS(src->dn_reg, reg, dst->dn_reg);
dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
@@ -474,30 +471,58 @@
size_t dstsize = dt_node_type_size(dst);
dif_instr_t instr;
- int reg, n;
+ int rg;
+
+ if (!dt_node_is_scalar(dst))
+ return; /* not a scalar */
+ if (dstsize == srcsize &&
+ ((src->dn_flags ^ dst->dn_flags) & DT_NF_SIGNED) != 0)
+ return; /* not narrowing or changing signed-ness */
+ if (dstsize > srcsize && (src->dn_flags & DT_NF_SIGNED) == 0)
+ return; /* nothing to do in this case */
- if (dt_node_is_scalar(dst) && (dstsize < srcsize ||
- (src->dn_flags & DT_NF_SIGNED) ^ (dst->dn_flags & DT_NF_SIGNED))) {
- if ((reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ rg = dt_regset_alloc(drp);
+
+ if (dstsize > srcsize) {
+ int n = sizeof (uint64_t) * NBBY - srcsize * NBBY;
+ int s = (dstsize - srcsize) * NBBY;
+
+ dt_cg_setx(dlp, rg, n);
+
+ instr = DIF_INSTR_FMT(DIF_OP_SLL, src->dn_reg, rg, dst->dn_reg);
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
- if (dstsize < srcsize)
- n = sizeof (uint64_t) * NBBY - dstsize * NBBY;
- else
- n = sizeof (uint64_t) * NBBY - srcsize * NBBY;
+ if ((dst->dn_flags & DT_NF_SIGNED) || n == s) {
+ instr = DIF_INSTR_FMT(DIF_OP_SRA,
+ dst->dn_reg, rg, dst->dn_reg);
+ dt_irlist_append(dlp,
+ dt_cg_node_alloc(DT_LBL_NONE, instr));
+ } else {
+ dt_cg_setx(dlp, rg, s);
+ instr = DIF_INSTR_FMT(DIF_OP_SRA,
+ dst->dn_reg, rg, dst->dn_reg);
+ dt_irlist_append(dlp,
+ dt_cg_node_alloc(DT_LBL_NONE, instr));
+ dt_cg_setx(dlp, rg, n - s);
+ instr = DIF_INSTR_FMT(DIF_OP_SRL,
+ dst->dn_reg, rg, dst->dn_reg);
+ dt_irlist_append(dlp,
+ dt_cg_node_alloc(DT_LBL_NONE, instr));
+ }
+ } else if (dstsize != sizeof (uint64_t)) {
+ int n = sizeof (uint64_t) * NBBY - dstsize * NBBY;
- dt_cg_setx(dlp, reg, n);
+ dt_cg_setx(dlp, rg, n);
- instr = DIF_INSTR_FMT(DIF_OP_SLL,
- src->dn_reg, reg, dst->dn_reg);
+ instr = DIF_INSTR_FMT(DIF_OP_SLL, src->dn_reg, rg, dst->dn_reg);
dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
instr = DIF_INSTR_FMT((dst->dn_flags & DT_NF_SIGNED) ?
- DIF_OP_SRA : DIF_OP_SRL, dst->dn_reg, reg, dst->dn_reg);
-
+ DIF_OP_SRA : DIF_OP_SRL, dst->dn_reg, rg, dst->dn_reg);
dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
- dt_regset_free(drp, reg);
}
+
+ dt_regset_free(drp, rg);
}
/*
@@ -523,8 +548,7 @@
for (dnp = args; dnp != NULL; dnp = dnp->dn_list)
dt_cg_node(dnp, dlp, drp);
- dt_irlist_append(dlp,
- dt_cg_node_alloc(DT_LBL_NONE, DIF_INSTR_FLUSHTS));
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, DIF_INSTR_FLUSHTS));
for (dnp = args; dnp != NULL; dnp = dnp->dn_list, i++) {
dtrace_diftype_t t;
@@ -538,17 +562,18 @@
dt_cg_typecast(dnp, &isp->dis_args[i], dlp, drp);
isp->dis_args[i].dn_reg = -1;
- if (t.dtdt_flags & DIF_TF_BYREF)
+ if (t.dtdt_flags & DIF_TF_BYREF) {
op = DIF_OP_PUSHTR;
- else
+ if (t.dtdt_size != 0) {
+ reg = dt_regset_alloc(drp);
+ dt_cg_setx(dlp, reg, t.dtdt_size);
+ } else {
+ reg = DIF_REG_R0;
+ }
+ } else {
op = DIF_OP_PUSHTV;
-
- if (t.dtdt_size != 0) {
- if ((reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
- dt_cg_setx(dlp, reg, t.dtdt_size);
- } else
reg = DIF_REG_R0;
+ }
instr = DIF_INSTR_PUSHTS(op, t.dtdt_kind, reg, dnp->dn_reg);
dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
@@ -629,9 +654,7 @@
dt_cg_node(dnp->dn_child, dlp, drp);
dnp->dn_reg = dnp->dn_child->dn_reg;
- if ((reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
-
+ reg = dt_regset_alloc(drp);
dt_cg_setx(dlp, reg, size);
instr = DIF_INSTR_FMT(op, dnp->dn_reg, reg, dnp->dn_reg);
@@ -688,9 +711,7 @@
dt_cg_node(dnp->dn_child, dlp, drp);
dnp->dn_reg = dnp->dn_child->dn_reg;
- if ((nreg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
-
+ nreg = dt_regset_alloc(drp);
dt_cg_setx(dlp, nreg, size);
instr = DIF_INSTR_FMT(op, dnp->dn_reg, nreg, nreg);
dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
@@ -1008,9 +1029,7 @@
* set it to the size of our data structure, and then replace
* it with the result of an allocs of the specified size.
*/
- if ((r1 = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
-
+ r1 = dt_regset_alloc(drp);
dt_cg_setx(dlp, r1,
ctf_type_size(dxp->dx_dst_ctfp, dxp->dx_dst_base));
@@ -1054,8 +1073,7 @@
* and add r1 to it before storing the result.
*/
if (ctm.ctm_offset != 0) {
- if ((r2 = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ r2 = dt_regset_alloc(drp);
/*
* Add the member offset rounded down to the
@@ -1142,8 +1160,7 @@
dt_cg_arglist(dnp->dn_ident, dnp->dn_args, dlp, drp);
- if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ dnp->dn_reg = dt_regset_alloc(drp);
if (dnp->dn_ident->di_flags & DT_IDFLG_TLS)
op = DIF_OP_LDTAA;
@@ -1273,9 +1290,7 @@
if ((size = dt_node_type_size(dnp)) == sizeof (uint64_t))
return;
- if ((reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
-
+ reg = dt_regset_alloc(drp);
assert(size < sizeof (uint64_t));
n = sizeof (uint64_t) * NBBY - size * NBBY;
@@ -1338,6 +1353,162 @@
}
}
+typedef struct dt_xlmemb {
+ dt_ident_t *dtxl_idp; /* translated ident */
+ dt_irlist_t *dtxl_dlp; /* instruction list */
+ dt_regset_t *dtxl_drp; /* register set */
+ int dtxl_sreg; /* location of the translation input */
+ int dtxl_dreg; /* location of our allocated buffer */
+} dt_xlmemb_t;
+
+/*ARGSUSED*/
+static int
+dt_cg_xlate_member(const char *name, ctf_id_t type, ulong_t off, void *arg)
+{
+ dt_xlmemb_t *dx = arg;
+ dt_ident_t *idp = dx->dtxl_idp;
+ dt_irlist_t *dlp = dx->dtxl_dlp;
+ dt_regset_t *drp = dx->dtxl_drp;
+
+ dt_node_t *mnp;
+ dt_xlator_t *dxp;
+
+ int reg, treg;
+ uint32_t instr;
+ size_t size;
+
+ /* Generate code for the translation. */
+ dxp = idp->di_data;
+ mnp = dt_xlator_member(dxp, name);
+
+ /* If there's no translator for the given member, skip it. */
+ if (mnp == NULL)
+ return (0);
+
+ dxp->dx_ident->di_flags |= DT_IDFLG_CGREG;
+ dxp->dx_ident->di_id = dx->dtxl_sreg;
+
+ dt_cg_node(mnp->dn_membexpr, dlp, drp);
+
+ dxp->dx_ident->di_flags &= ~DT_IDFLG_CGREG;
+ dxp->dx_ident->di_id = 0;
+
+ treg = mnp->dn_membexpr->dn_reg;
+
+ /* Compute the offset into our buffer and store the result there. */
+ reg = dt_regset_alloc(drp);
+
+ dt_cg_setx(dlp, reg, off / NBBY);
+ instr = DIF_INSTR_FMT(DIF_OP_ADD, dx->dtxl_dreg, reg, reg);
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
+
+ size = ctf_type_size(mnp->dn_membexpr->dn_ctfp,
+ mnp->dn_membexpr->dn_type);
+ if (dt_node_is_scalar(mnp->dn_membexpr)) {
+ /*
+ * Copying scalars is simple.
+ */
+ switch (size) {
+ case 1:
+ instr = DIF_INSTR_STORE(DIF_OP_STB, treg, reg);
+ break;
+ case 2:
+ instr = DIF_INSTR_STORE(DIF_OP_STH, treg, reg);
+ break;
+ case 4:
+ instr = DIF_INSTR_STORE(DIF_OP_STW, treg, reg);
+ break;
+ case 8:
+ instr = DIF_INSTR_STORE(DIF_OP_STX, treg, reg);
+ break;
+ default:
+ xyerror(D_UNKNOWN, "internal error -- unexpected "
+ "size: %lu\n", (ulong_t)size);
+ }
+
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
+
+ } else if (dt_node_is_string(mnp->dn_membexpr)) {
+ int szreg;
+
+ /*
+ * Use the copys instruction for strings.
+ */
+ szreg = dt_regset_alloc(drp);
+ dt_cg_setx(dlp, szreg, size);
+ instr = DIF_INSTR_COPYS(treg, szreg, reg);
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
+ dt_regset_free(drp, szreg);
+ } else {
+ int szreg;
+
+ /*
+ * If it's anything else then we'll just bcopy it.
+ */
+ szreg = dt_regset_alloc(drp);
+ dt_cg_setx(dlp, szreg, size);
+ dt_irlist_append(dlp,
+ dt_cg_node_alloc(DT_LBL_NONE, DIF_INSTR_FLUSHTS));
+ instr = DIF_INSTR_PUSHTS(DIF_OP_PUSHTV, DIF_TYPE_CTF,
+ DIF_REG_R0, treg);
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
+ instr = DIF_INSTR_PUSHTS(DIF_OP_PUSHTV, DIF_TYPE_CTF,
+ DIF_REG_R0, reg);
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
+ instr = DIF_INSTR_PUSHTS(DIF_OP_PUSHTV, DIF_TYPE_CTF,
+ DIF_REG_R0, szreg);
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
+ instr = DIF_INSTR_CALL(DIF_SUBR_BCOPY, szreg);
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
+ dt_regset_free(drp, szreg);
+ }
+
+ dt_regset_free(drp, reg);
+ dt_regset_free(drp, treg);
+
+ return (0);
+}
+
+/*
+ * If we're expanding a translated type, we create an appropriately sized
+ * buffer with alloca() and then translate each member into it.
+ */
+static int
+dt_cg_xlate_expand(dt_node_t *dnp, dt_ident_t *idp, dt_irlist_t *dlp,
+ dt_regset_t *drp)
+{
+ dt_xlmemb_t dlm;
+ uint32_t instr;
+ int dreg;
+ size_t size;
+
+ dreg = dt_regset_alloc(drp);
+ size = ctf_type_size(dnp->dn_ident->di_ctfp, dnp->dn_ident->di_type);
+
+ /* Call alloca() to create the buffer. */
+ dt_cg_setx(dlp, dreg, size);
+
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, DIF_INSTR_FLUSHTS));
+
+ instr = DIF_INSTR_PUSHTS(DIF_OP_PUSHTV, DIF_TYPE_CTF, DIF_REG_R0, dreg);
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
+
+ instr = DIF_INSTR_CALL(DIF_SUBR_ALLOCA, dreg);
+ dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
+
+ /* Generate the translation for each member. */
+ dlm.dtxl_idp = idp;
+ dlm.dtxl_dlp = dlp;
+ dlm.dtxl_drp = drp;
+ dlm.dtxl_sreg = dnp->dn_reg;
+ dlm.dtxl_dreg = dreg;
+ (void) ctf_member_iter(dnp->dn_ident->di_ctfp,
+ dnp->dn_ident->di_type, dt_cg_xlate_member,
+ &dlm);
+
+ return (dreg);
+}
+
static void
dt_cg_node(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
{
@@ -1350,7 +1521,6 @@
dt_ident_t *idp;
ssize_t stroff;
uint_t op;
- int reg;
switch (dnp->dn_op) {
case DT_TOK_COMMA:
@@ -1552,7 +1722,16 @@
dt_cg_node(dnp->dn_child, dlp, drp);
dnp->dn_reg = dnp->dn_child->dn_reg;
- if (!(dnp->dn_flags & DT_NF_REF)) {
+ if (dt_node_is_dynamic(dnp->dn_child)) {
+ int reg;
+ idp = dt_node_resolve(dnp->dn_child, DT_IDENT_XLPTR);
+ assert(idp != NULL);
+ reg = dt_cg_xlate_expand(dnp, idp, dlp, drp);
+
+ dt_regset_free(drp, dnp->dn_child->dn_reg);
+ dnp->dn_reg = reg;
+
+ } else if (!(dnp->dn_flags & DT_NF_REF)) {
uint_t ubit = dnp->dn_flags & DT_NF_USERLAND;
/*
@@ -1588,10 +1767,7 @@
case DT_TOK_SIZEOF: {
size_t size = dt_node_sizeof(dnp->dn_child);
-
- if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
-
+ dnp->dn_reg = dt_regset_alloc(drp);
assert(size != 0);
dt_cg_setx(dlp, dnp->dn_reg, size);
break;
@@ -1616,8 +1792,7 @@
assert(dxp->dx_ident->di_flags & DT_IDFLG_CGREG);
assert(dxp->dx_ident->di_id != 0);
- if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ dnp->dn_reg = dt_regset_alloc(drp);
if (dxp->dx_arg == -1) {
instr = DIF_INSTR_MOV(
@@ -1701,8 +1876,9 @@
}
if (m.ctm_offset != 0) {
- if ((reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ int reg;
+
+ reg = dt_regset_alloc(drp);
/*
* If the offset is not aligned on a byte boundary, it
@@ -1748,8 +1924,7 @@
break;
case DT_TOK_STRING:
- if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ dnp->dn_reg = dt_regset_alloc(drp);
assert(dnp->dn_kind == DT_NODE_STRING);
stroff = dt_strtab_insert(yypcb->pcb_strtab, dnp->dn_string);
@@ -1772,8 +1947,7 @@
*/
if (dnp->dn_kind == DT_NODE_VAR &&
(dnp->dn_ident->di_flags & DT_IDFLG_CGREG)) {
- if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ dnp->dn_reg = dt_regset_alloc(drp);
instr = DIF_INSTR_MOV(dnp->dn_ident->di_id,
dnp->dn_reg);
dt_irlist_append(dlp,
@@ -1803,11 +1977,9 @@
dt_cg_arglist(dnp->dn_ident, dnp->dn_args, dlp, drp);
- if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
-
- instr = DIF_INSTR_CALL(
- dnp->dn_ident->di_id, dnp->dn_reg);
+ dnp->dn_reg = dt_regset_alloc(drp);
+ instr = DIF_INSTR_CALL(dnp->dn_ident->di_id,
+ dnp->dn_reg);
dt_irlist_append(dlp,
dt_cg_node_alloc(DT_LBL_NONE, instr));
@@ -1834,8 +2006,7 @@
break;
}
- if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
+ dnp->dn_reg = dt_regset_alloc(drp);
if (dnp->dn_ident->di_flags & DT_IDFLG_LOCAL)
op = DIF_OP_LDLS;
@@ -1865,9 +2036,7 @@
dtrace_errmsg(dtp, dtrace_errno(dtp)));
}
- if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
-
+ dnp->dn_reg = dt_regset_alloc(drp);
dt_cg_xsetx(dlp, dnp->dn_ident,
DT_LBL_NONE, dnp->dn_reg, sym.st_value);
@@ -1887,9 +2056,7 @@
break;
case DT_TOK_INT:
- if ((dnp->dn_reg = dt_regset_alloc(drp)) == -1)
- longjmp(yypcb->pcb_jmpbuf, EDT_NOREG);
-
+ dnp->dn_reg = dt_regset_alloc(drp);
dt_cg_setx(dlp, dnp->dn_reg, dnp->dn_value);
break;
@@ -1904,6 +2071,7 @@
{
dif_instr_t instr;
dt_xlator_t *dxp;
+ dt_ident_t *idp;
if (pcb->pcb_regs == NULL && (pcb->pcb_regs =
dt_regset_create(pcb->pcb_hdl->dt_conf.dtc_difintregs)) == NULL)
@@ -1930,9 +2098,9 @@
assert(pcb->pcb_dret == NULL);
pcb->pcb_dret = dnp;
- if (dt_node_is_dynamic(dnp)) {
+ if (dt_node_resolve(dnp, DT_IDENT_XLPTR) != NULL) {
dnerror(dnp, D_CG_DYN, "expression cannot evaluate to result "
- "of dynamic type\n");
+ "of a translated pointer\n");
}
/*
@@ -1948,6 +2116,14 @@
}
dt_cg_node(dnp, &pcb->pcb_ir, pcb->pcb_regs);
+
+ if ((idp = dt_node_resolve(dnp, DT_IDENT_XLSOU)) != NULL) {
+ int reg = dt_cg_xlate_expand(dnp, idp,
+ &pcb->pcb_ir, pcb->pcb_regs);
+ dt_regset_free(pcb->pcb_regs, dnp->dn_reg);
+ dnp->dn_reg = reg;
+ }
+
instr = DIF_INSTR_RET(dnp->dn_reg);
dt_regset_free(pcb->pcb_regs, dnp->dn_reg);
dt_irlist_append(&pcb->pcb_ir, dt_cg_node_alloc(DT_LBL_NONE, instr));
@@ -1957,4 +2133,7 @@
dxp->dx_ident->di_id = 0;
dxp->dx_ident->di_flags &= ~DT_IDFLG_CGREG;
}
+
+ dt_regset_free(pcb->pcb_regs, 0);
+ dt_regset_assert_free(pcb->pcb_regs);
}
--- a/usr/src/lib/libdtrace/common/dt_consume.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_consume.c Sun Aug 12 11:56:48 2012 +0100
@@ -25,7 +25,7 @@
/*
* Copyright (c) 2011, Joyent, Inc. All rights reserved.
- * Copyright (c) 2011 by Delphix. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#include <stdlib.h>
@@ -37,6 +37,7 @@
#include <ctype.h>
#include <alloca.h>
#include <dt_impl.h>
+#include <dt_pq.h>
#define DT_MASK_LO 0x00000000FFFFFFFFULL
@@ -438,17 +439,8 @@
offs += epd->dtepd_size;
do {
- if (offs >= buf->dtbd_size) {
- /*
- * We're at the end -- maybe. If the oldest
- * record is non-zero, we need to wrap.
- */
- if (buf->dtbd_oldest != 0) {
- offs = 0;
- } else {
- goto out;
- }
- }
+ if (offs >= buf->dtbd_size)
+ goto out;
next = *(uint32_t *)((uintptr_t)buf->dtbd_data + offs);
@@ -1700,26 +1692,27 @@
}
static int
-dt_consume_cpu(dtrace_hdl_t *dtp, FILE *fp, int cpu, dtrace_bufdesc_t *buf,
+dt_consume_cpu(dtrace_hdl_t *dtp, FILE *fp, int cpu,
+ dtrace_bufdesc_t *buf, boolean_t just_one,
dtrace_consume_probe_f *efunc, dtrace_consume_rec_f *rfunc, void *arg)
{
dtrace_epid_t id;
- size_t offs, start = buf->dtbd_oldest, end = buf->dtbd_size;
+ size_t offs;
int flow = (dtp->dt_options[DTRACEOPT_FLOWINDENT] != DTRACEOPT_UNSET);
int quiet = (dtp->dt_options[DTRACEOPT_QUIET] != DTRACEOPT_UNSET);
int rval, i, n;
- dtrace_epid_t last = DTRACE_EPIDNONE;
uint64_t tracememsize = 0;
dtrace_probedata_t data;
uint64_t drops;
- caddr_t addr;
bzero(&data, sizeof (data));
data.dtpda_handle = dtp;
data.dtpda_cpu = cpu;
-
-again:
- for (offs = start; offs < end; ) {
+ data.dtpda_flow = dtp->dt_flow;
+ data.dtpda_indent = dtp->dt_indent;
+ data.dtpda_prefix = dtp->dt_prefix;
+
+ for (offs = buf->dtbd_oldest; offs < buf->dtbd_size; ) {
dtrace_eprobedesc_t *epd;
/*
@@ -1754,7 +1747,8 @@
}
if (flow)
- (void) dt_flowindent(dtp, &data, last, buf, offs);
+ (void) dt_flowindent(dtp, &data, dtp->dt_last_epid,
+ buf, offs);
rval = (*efunc)(&data, arg);
@@ -1773,6 +1767,7 @@
return (dt_set_errno(dtp, EDT_BADRVAL));
for (i = 0; i < epd->dtepd_nrecs; i++) {
+ caddr_t addr;
dtrace_recdesc_t *rec = &epd->dtepd_rec[i];
dtrace_actkind_t act = rec->dtrd_action;
@@ -2132,14 +2127,16 @@
rval = (*rfunc)(&data, NULL, arg);
nextepid:
offs += epd->dtepd_size;
- last = id;
+ dtp->dt_last_epid = id;
+ if (just_one) {
+ buf->dtbd_oldest = offs;
+ break;
+ }
}
- if (buf->dtbd_oldest != 0 && start == buf->dtbd_oldest) {
- end = buf->dtbd_oldest;
- start = 0;
- goto again;
- }
+ dtp->dt_flow = data.dtpda_flow;
+ dtp->dt_indent = data.dtpda_indent;
+ dtp->dt_prefix = data.dtpda_prefix;
if ((drops = buf->dtbd_drops) == 0)
return (0);
@@ -2152,6 +2149,126 @@
return (dt_handle_cpudrop(dtp, cpu, DTRACEDROP_PRINCIPAL, drops));
}
+/*
+ * Reduce memory usage by shrinking the buffer if it's no more than half full.
+ * Note, we need to preserve the alignment of the data at dtbd_oldest, which is
+ * only 4-byte aligned.
+ */
+static void
+dt_realloc_buf(dtrace_hdl_t *dtp, dtrace_bufdesc_t *buf, int cursize)
+{
+ uint64_t used = buf->dtbd_size - buf->dtbd_oldest;
+ if (used < cursize / 2) {
+ int misalign = buf->dtbd_oldest & (sizeof (uint64_t) - 1);
+ char *newdata = dt_alloc(dtp, used + misalign);
+ if (newdata == NULL)
+ return;
+ bzero(newdata, misalign);
+ bcopy(buf->dtbd_data + buf->dtbd_oldest,
+ newdata + misalign, used);
+ dt_free(dtp, buf->dtbd_data);
+ buf->dtbd_oldest = misalign;
+ buf->dtbd_size = used + misalign;
+ buf->dtbd_data = newdata;
+ }
+}
+
+/*
+ * If the ring buffer has wrapped, the data is not in order. Rearrange it
+ * so that it is. Note, we need to preserve the alignment of the data at
+ * dtbd_oldest, which is only 4-byte aligned.
+ */
+static int
+dt_unring_buf(dtrace_hdl_t *dtp, dtrace_bufdesc_t *buf)
+{
+ int misalign;
+ char *newdata, *ndp;
+
+ if (buf->dtbd_oldest == 0)
+ return (0);
+
+ misalign = buf->dtbd_oldest & (sizeof (uint64_t) - 1);
+ newdata = ndp = dt_alloc(dtp, buf->dtbd_size + misalign);
+
+ if (newdata == NULL)
+ return (-1);
+
+ assert(0 == (buf->dtbd_size & (sizeof (uint64_t) - 1)));
+
+ bzero(ndp, misalign);
+ ndp += misalign;
+
+ bcopy(buf->dtbd_data + buf->dtbd_oldest, ndp,
+ buf->dtbd_size - buf->dtbd_oldest);
+ ndp += buf->dtbd_size - buf->dtbd_oldest;
+
+ bcopy(buf->dtbd_data, ndp, buf->dtbd_oldest);
+
+ dt_free(dtp, buf->dtbd_data);
+ buf->dtbd_oldest = 0;
+ buf->dtbd_data = newdata;
+ buf->dtbd_size += misalign;
+
+ return (0);
+}
+
+static void
+dt_put_buf(dtrace_hdl_t *dtp, dtrace_bufdesc_t *buf)
+{
+ dt_free(dtp, buf->dtbd_data);
+ dt_free(dtp, buf);
+}
+
+/*
+ * Returns 0 on success, in which case *cbp will be filled in if we retrieved
+ * data, or NULL if there is no data for this CPU.
+ * Returns -1 on failure and sets dt_errno.
+ */
+static int
+dt_get_buf(dtrace_hdl_t *dtp, int cpu, dtrace_bufdesc_t **bufp)
+{
+ dtrace_optval_t size;
+ dtrace_bufdesc_t *buf = dt_zalloc(dtp, sizeof (*buf));
+ int error;
+
+ if (buf == NULL)
+ return (-1);
+
+ (void) dtrace_getopt(dtp, "bufsize", &size);
+ buf->dtbd_data = dt_alloc(dtp, size);
+ if (buf->dtbd_data == NULL) {
+ dt_free(dtp, buf);
+ return (-1);
+ }
+ buf->dtbd_size = size;
+ buf->dtbd_cpu = cpu;
+
+ if (dt_ioctl(dtp, DTRACEIOC_BUFSNAP, buf) == -1) {
+ dt_put_buf(dtp, buf);
+ /*
+ * If we failed with ENOENT, it may be because the
+ * CPU was unconfigured -- this is okay. Any other
+ * error, however, is unexpected.
+ */
+ if (errno == ENOENT) {
+ *bufp = NULL;
+ return (0);
+ }
+
+ return (dt_set_errno(dtp, errno));
+ }
+
+ error = dt_unring_buf(dtp, buf);
+ if (error != 0) {
+ dt_put_buf(dtp, buf);
+ return (error);
+ }
+ dt_realloc_buf(dtp, buf, size);
+
+ *bufp = buf;
+ return (0);
+}
+
typedef struct dt_begin {
dtrace_consume_probe_f *dtbgn_probefunc;
dtrace_consume_rec_f *dtbgn_recfunc;
@@ -2164,7 +2281,7 @@
static int
dt_consume_begin_probe(const dtrace_probedata_t *data, void *arg)
{
- dt_begin_t *begin = (dt_begin_t *)arg;
+ dt_begin_t *begin = arg;
dtrace_probedesc_t *pd = data->dtpda_pdesc;
int r1 = (strcmp(pd->dtpd_provider, "dtrace") == 0);
@@ -2189,7 +2306,7 @@
dt_consume_begin_record(const dtrace_probedata_t *data,
const dtrace_recdesc_t *rec, void *arg)
{
- dt_begin_t *begin = (dt_begin_t *)arg;
+ dt_begin_t *begin = arg;
return (begin->dtbgn_recfunc(data, rec, begin->dtbgn_arg));
}
@@ -2215,7 +2332,7 @@
}
static int
-dt_consume_begin(dtrace_hdl_t *dtp, FILE *fp, dtrace_bufdesc_t *buf,
+dt_consume_begin(dtrace_hdl_t *dtp, FILE *fp,
dtrace_consume_probe_f *pf, dtrace_consume_rec_f *rf, void *arg)
{
/*
@@ -2239,26 +2356,19 @@
* first pass, and that we only process ERROR enablings _not_ induced
* by BEGIN enablings in the second pass.
*/
+
dt_begin_t begin;
processorid_t cpu = dtp->dt_beganon;
- dtrace_bufdesc_t nbuf;
int rval, i;
static int max_ncpus;
- dtrace_optval_t size;
+ dtrace_bufdesc_t *buf;
dtp->dt_beganon = -1;
- if (dt_ioctl(dtp, DTRACEIOC_BUFSNAP, buf) == -1) {
- /*
- * We really don't expect this to fail, but it is at least
- * technically possible for this to fail with ENOENT. In this
- * case, we just drive on...
- */
- if (errno == ENOENT)
- return (0);
-
- return (dt_set_errno(dtp, errno));
- }
+ if (dt_get_buf(dtp, cpu, &buf) != 0)
+ return (-1);
+ if (buf == NULL)
+ return (0);
if (!dtp->dt_stopped || buf->dtbd_cpu != dtp->dt_endedon) {
/*
@@ -2266,7 +2376,10 @@
* we are, we actually processed any END probes on another
* CPU. We can simply consume this buffer and return.
*/
- return (dt_consume_cpu(dtp, fp, cpu, buf, pf, rf, arg));
+ rval = dt_consume_cpu(dtp, fp, cpu, buf, B_FALSE,
+ pf, rf, arg);
+ dt_put_buf(dtp, buf);
+ return (rval);
}
begin.dtbgn_probefunc = pf;
@@ -2283,56 +2396,41 @@
dtp->dt_errhdlr = dt_consume_begin_error;
dtp->dt_errarg = &begin;
- rval = dt_consume_cpu(dtp, fp, cpu, buf, dt_consume_begin_probe,
- dt_consume_begin_record, &begin);
+ rval = dt_consume_cpu(dtp, fp, cpu, buf, B_FALSE,
+ dt_consume_begin_probe, dt_consume_begin_record, &begin);
dtp->dt_errhdlr = begin.dtbgn_errhdlr;
dtp->dt_errarg = begin.dtbgn_errarg;
- if (rval != 0)
+ if (rval != 0) {
+ dt_put_buf(dtp, buf);
return (rval);
-
- /*
- * Now allocate a new buffer. We'll use this to deal with every other
- * CPU.
- */
- bzero(&nbuf, sizeof (dtrace_bufdesc_t));
- (void) dtrace_getopt(dtp, "bufsize", &size);
- if ((nbuf.dtbd_data = malloc(size)) == NULL)
- return (dt_set_errno(dtp, EDT_NOMEM));
+ }
if (max_ncpus == 0)
max_ncpus = dt_sysconf(dtp, _SC_CPUID_MAX) + 1;
for (i = 0; i < max_ncpus; i++) {
- nbuf.dtbd_cpu = i;
-
+ dtrace_bufdesc_t *nbuf;
if (i == cpu)
continue;
- if (dt_ioctl(dtp, DTRACEIOC_BUFSNAP, &nbuf) == -1) {
- /*
- * If we failed with ENOENT, it may be because the
- * CPU was unconfigured -- this is okay. Any other
- * error, however, is unexpected.
- */
- if (errno == ENOENT)
- continue;
-
- free(nbuf.dtbd_data);
-
- return (dt_set_errno(dtp, errno));
+ if (dt_get_buf(dtp, i, &nbuf) != 0) {
+ dt_put_buf(dtp, buf);
+ return (-1);
}
-
- if ((rval = dt_consume_cpu(dtp, fp,
- i, &nbuf, pf, rf, arg)) != 0) {
- free(nbuf.dtbd_data);
+ if (nbuf == NULL)
+ continue;
+
+ rval = dt_consume_cpu(dtp, fp, i, nbuf, B_FALSE,
+ pf, rf, arg);
+ dt_put_buf(dtp, nbuf);
+ if (rval != 0) {
+ dt_put_buf(dtp, buf);
return (rval);
}
}
- free(nbuf.dtbd_data);
-
/*
* Okay -- we're done with the other buffers. Now we want to
* reconsume the first buffer -- but this time we're looking for
@@ -2347,8 +2445,8 @@
dtp->dt_errhdlr = dt_consume_begin_error;
dtp->dt_errarg = &begin;
- rval = dt_consume_cpu(dtp, fp, cpu, buf, dt_consume_begin_probe,
- dt_consume_begin_record, &begin);
+ rval = dt_consume_cpu(dtp, fp, cpu, buf, B_FALSE,
+ dt_consume_begin_probe, dt_consume_begin_record, &begin);
dtp->dt_errhdlr = begin.dtbgn_errhdlr;
dtp->dt_errarg = begin.dtbgn_errarg;
@@ -2356,11 +2454,31 @@
return (rval);
}
+/* ARGSUSED */
+static uint64_t
+dt_buf_oldest(void *elem, void *arg)
+{
+ dtrace_bufdesc_t *buf = elem;
+ size_t offs = buf->dtbd_oldest;
+
+ while (offs < buf->dtbd_size) {
+ dtrace_rechdr_t *dtrh =
+ (dtrace_rechdr_t *)(buf->dtbd_data + offs);
+ if (dtrh->dtrh_epid == DTRACE_EPIDNONE) {
+ offs += sizeof (dtrace_epid_t);
+ } else {
+ return (DTRACE_RECORD_LOAD_TIMESTAMP(dtrh));
+ }
+ }
+
+ /* There are no records left; use the time the buffer was retrieved. */
+ return (buf->dtbd_timestamp);
+}
+
int
dtrace_consume(dtrace_hdl_t *dtp, FILE *fp,
dtrace_consume_probe_f *pf, dtrace_consume_rec_f *rf, void *arg)
{
- dtrace_bufdesc_t *buf = &dtp->dt_buf;
dtrace_optval_t size;
static int max_ncpus;
int i, rval;
@@ -2388,71 +2506,158 @@
if (rf == NULL)
rf = (dtrace_consume_rec_f *)dt_nullrec;
- if (buf->dtbd_data == NULL) {
+ if (dtp->dt_options[DTRACEOPT_TEMPORAL] == DTRACEOPT_UNSET) {
+ /*
+ * The output will not be in the order it was traced. Rather,
+ * we will consume all of the data from each CPU's buffer in
+ * turn. We apply special handling for the records from BEGIN
+ * and END probes so that they are consumed first and last,
+ * respectively.
+ *
+ * If we have just begun, we want to first process the CPU that
+ * executed the BEGIN probe (if any).
+ */
+ if (dtp->dt_active && dtp->dt_beganon != -1 &&
+ (rval = dt_consume_begin(dtp, fp, pf, rf, arg)) != 0)
+ return (rval);
+
+ for (i = 0; i < max_ncpus; i++) {
+ dtrace_bufdesc_t *buf;
+
+ /*
+ * If we have stopped, we want to process the CPU on
+ * which the END probe was processed only _after_ we
+ * have processed everything else.
+ */
+ if (dtp->dt_stopped && (i == dtp->dt_endedon))
+ continue;
+
+ if (dt_get_buf(dtp, i, &buf) != 0)
+ return (-1);
+ if (buf == NULL)
+ continue;
+
+ dtp->dt_flow = 0;
+ dtp->dt_indent = 0;
+ dtp->dt_prefix = NULL;
+ rval = dt_consume_cpu(dtp, fp, i,
+ buf, B_FALSE, pf, rf, arg);
+ dt_put_buf(dtp, buf);
+ if (rval != 0)
+ return (rval);
+ }
+ if (dtp->dt_stopped) {
+ dtrace_bufdesc_t *buf;
+
+ if (dt_get_buf(dtp, dtp->dt_endedon, &buf) != 0)
+ return (-1);
+ if (buf == NULL)
+ return (0);
+
+ rval = dt_consume_cpu(dtp, fp, dtp->dt_endedon,
+ buf, B_FALSE, pf, rf, arg);
+ dt_put_buf(dtp, buf);
+ return (rval);
+ }
+ } else {
+ /*
+ * The output will be in the order it was traced (or for
+ * speculations, when it was committed). We retrieve a buffer
+ * from each CPU and put it into a priority queue, which sorts
+ * based on the first entry in the buffer. This is sufficient
+ * because entries within a buffer are already sorted.
+ *
+ * We then consume records one at a time, always consuming the
+ * oldest record, as determined by the priority queue. When
+ * we reach the end of the time covered by these buffers,
+ * we need to stop and retrieve more records on the next pass.
+ * The kernel tells us the time covered by each buffer, in
+ * dtbd_timestamp. The first buffer's timestamp tells us the
+ * time covered by all buffers, as subsequently retrieved
+ * buffers will cover to a more recent time.
+ */
+
+ uint64_t *drops = alloca(max_ncpus * sizeof (uint64_t));
+ uint64_t first_timestamp = 0;
+ uint_t cookie = 0;
+ dtrace_bufdesc_t *buf;
+
+ bzero(drops, max_ncpus * sizeof (uint64_t));
+
+ if (dtp->dt_bufq == NULL) {
+ dtp->dt_bufq = dt_pq_init(dtp, max_ncpus * 2,
+ dt_buf_oldest, NULL);
+ if (dtp->dt_bufq == NULL) /* ENOMEM */
+ return (-1);
+ }
+
+ /* Retrieve data from each CPU. */
(void) dtrace_getopt(dtp, "bufsize", &size);
- if ((buf->dtbd_data = malloc(size)) == NULL)
- return (dt_set_errno(dtp, EDT_NOMEM));
-
- buf->dtbd_size = size;
- }
-
- /*
- * If we have just begun, we want to first process the CPU that
- * executed the BEGIN probe (if any).
- */
- if (dtp->dt_active && dtp->dt_beganon != -1) {
- buf->dtbd_cpu = dtp->dt_beganon;
- if ((rval = dt_consume_begin(dtp, fp, buf, pf, rf, arg)) != 0)
- return (rval);
- }
-
- for (i = 0; i < max_ncpus; i++) {
- buf->dtbd_cpu = i;
+ for (i = 0; i < max_ncpus; i++) {
+ dtrace_bufdesc_t *buf;
+
+ if (dt_get_buf(dtp, i, &buf) != 0)
+ return (-1);
+ if (buf != NULL) {
+ if (first_timestamp == 0)
+ first_timestamp = buf->dtbd_timestamp;
+ assert(buf->dtbd_timestamp >= first_timestamp);
+
+ dt_pq_insert(dtp->dt_bufq, buf);
+ drops[i] = buf->dtbd_drops;
+ buf->dtbd_drops = 0;
+ }
+ }
+
+ /* Consume records. */
+ for (;;) {
+ dtrace_bufdesc_t *buf = dt_pq_pop(dtp->dt_bufq);
+ uint64_t timestamp;
+
+ if (buf == NULL)
+ break;
+
+ timestamp = dt_buf_oldest(buf, dtp);
+ assert(timestamp >= dtp->dt_last_timestamp);
+ dtp->dt_last_timestamp = timestamp;
+
+ if (timestamp == buf->dtbd_timestamp) {
+ /*
+ * We've reached the end of the time covered
+ * by this buffer. If this is the oldest
+ * buffer, we must do another pass
+ * to retrieve more data.
+ */
+ dt_put_buf(dtp, buf);
+ if (timestamp == first_timestamp &&
+ !dtp->dt_stopped)
+ break;
+ continue;
+ }
+
+ if ((rval = dt_consume_cpu(dtp, fp,
+ buf->dtbd_cpu, buf, B_TRUE, pf, rf, arg)) != 0)
+ return (rval);
+ dt_pq_insert(dtp->dt_bufq, buf);
+ }
+
+ /* Consume drops. */
+ for (i = 0; i < max_ncpus; i++) {
+ if (drops[i] != 0) {
+ int error = dt_handle_cpudrop(dtp, i,
+ DTRACEDROP_PRINCIPAL, drops[i]);
+ if (error != 0)
+ return (error);
+ }
+ }
/*
- * If we have stopped, we want to process the CPU on which the
- * END probe was processed only _after_ we have processed
- * everything else.
+ * Reduce memory usage by re-allocating smaller buffers
+ * for the "remnants".
*/
- if (dtp->dt_stopped && (i == dtp->dt_endedon))
- continue;
-
- if (dt_ioctl(dtp, DTRACEIOC_BUFSNAP, buf) == -1) {
- /*
- * If we failed with ENOENT, it may be because the
- * CPU was unconfigured -- this is okay. Any other
- * error, however, is unexpected.
- */
- if (errno == ENOENT)
- continue;
-
- return (dt_set_errno(dtp, errno));
- }
-
- if ((rval = dt_consume_cpu(dtp, fp, i, buf, pf, rf, arg)) != 0)
- return (rval);
+ while (buf = dt_pq_walk(dtp->dt_bufq, &cookie))
+ dt_realloc_buf(dtp, buf, buf->dtbd_size);
}
- if (!dtp->dt_stopped)
- return (0);
-
- buf->dtbd_cpu = dtp->dt_endedon;
-
- if (dt_ioctl(dtp, DTRACEIOC_BUFSNAP, buf) == -1) {
- /*
- * This _really_ shouldn't fail, but it is strictly speaking
- * possible for this to return ENOENT if the CPU that called
- * the END enabling somehow managed to become unconfigured.
- * It's unclear how the user can possibly expect anything
- * rational to happen in this case -- the state has been thrown
- * out along with the unconfigured CPU -- so we'll just drive
- * on...
- */
- if (errno == ENOENT)
- return (0);
-
- return (dt_set_errno(dtp, errno));
- }
-
- return (dt_consume_cpu(dtp, fp, dtp->dt_endedon, buf, pf, rf, arg));
+ return (0);
}
--- a/usr/src/lib/libdtrace/common/dt_dis.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_dis.c Sun Aug 12 11:56:48 2012 +0100
@@ -19,12 +19,15 @@
*
* CDDL HEADER END
*/
+
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
-#pragma ident "%Z%%M% %I% %E% SMI"
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
#include <strings.h>
#include <stdio.h>
@@ -212,12 +215,22 @@
{
static const char *const tnames[] = { "D type", "string" };
uint_t type = DIF_INSTR_TYPE(in);
+ const char *pad;
- (void) fprintf(fp, "%-4s DT_TYPE(%u), %%r%u, %%r%u",
- name, type, DIF_INSTR_R2(in), DIF_INSTR_RS(in));
+ if (DIF_INSTR_OP(in) == DIF_OP_PUSHTV) {
+ (void) fprintf(fp, "%-4s DT_TYPE(%u), %%r%u",
+ name, type, DIF_INSTR_RS(in));
+ pad = "\t\t";
+ } else {
+ (void) fprintf(fp, "%-4s DT_TYPE(%u), %%r%u, %%r%u",
+ name, type, DIF_INSTR_R2(in), DIF_INSTR_RS(in));
+ pad = "\t";
+ }
- if (type < sizeof (tnames) / sizeof (tnames[0]))
- (void) fprintf(fp, "\t! DT_TYPE(%u) = %s", type, tnames[type]);
+ if (type < sizeof (tnames) / sizeof (tnames[0])) {
+ (void) fprintf(fp, "%s! DT_TYPE(%u) = %s", pad,
+ type, tnames[type]);
+ }
}
static void
--- a/usr/src/lib/libdtrace/common/dt_error.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_error.c Sun Aug 12 11:56:48 2012 +0100
@@ -18,11 +18,16 @@
*
* CDDL HEADER END
*/
+
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
#include <strings.h>
#include <dt_impl.h>
@@ -36,7 +41,6 @@
{ EDT_VERSREDUCED, "Requested version conflicts with earlier setting" },
{ EDT_CTF, "Unexpected libctf error" },
{ EDT_COMPILER, "Error in D program compilation" },
- { EDT_NOREG, "Insufficient registers to generate code" },
{ EDT_NOTUPREG, "Insufficient tuple registers to generate code" },
{ EDT_NOMEM, "Memory allocation failure" },
{ EDT_INT2BIG, "Integer constant table limit exceeded" },
--- a/usr/src/lib/libdtrace/common/dt_errtags.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_errtags.h Sun Aug 12 11:56:48 2012 +0100
@@ -26,7 +26,7 @@
/*
* Copyright (c) 2011, Joyent, Inc. All rights reserved.
- * Copyright (c) 2011 by Delphix. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#ifndef _DT_ERRTAGS_H
@@ -259,7 +259,8 @@
D_LLQUANT_FACTORNSTEPS, /* llquantize() # steps < factor */
D_LLQUANT_FACTOREVEN, /* llquantize() bad # steps/factor */
D_LLQUANT_FACTORSMALL, /* llquantize() magnitude too small */
- D_LLQUANT_MAGTOOBIG /* llquantize() high mag too large */
+ D_LLQUANT_MAGTOOBIG, /* llquantize() high mag too large */
+ D_NOREG /* no available internal registers */
} dt_errtag_t;
extern const char *dt_errtag(dt_errtag_t);
--- a/usr/src/lib/libdtrace/common/dt_impl.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_impl.h Sun Aug 12 11:56:48 2012 +0100
@@ -26,7 +26,7 @@
/*
* Copyright (c) 2011, Joyent, Inc. All rights reserved.
- * Copyright (c) 2011 by Delphix. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#ifndef _DT_IMPL_H
@@ -55,6 +55,7 @@
#include <dt_proc.h>
#include <dt_dof.h>
#include <dt_pcb.h>
+#include <dt_pq.h>
struct dt_module; /* see below */
struct dt_pfdict; /* see <dt_printf.h> */
@@ -226,6 +227,7 @@
uint_t dt_provbuckets; /* number of provider hash buckets */
uint_t dt_nprovs; /* number of providers in hash and list */
dt_proc_hash_t *dt_procs; /* hash table of grabbed process handles */
+ char **dt_proc_env; /* additional environment variables */
dt_intdesc_t dt_ints[6]; /* cached integer type descriptions */
ctf_id_t dt_type_func; /* cached CTF identifier for function type */
ctf_id_t dt_type_fptr; /* cached CTF identifier for function pointer */
@@ -244,7 +246,7 @@
int dt_maxstrdata; /* max strdata ID */
char **dt_strdata; /* pointer to strdata array */
dt_aggregate_t dt_aggregate; /* aggregate */
- dtrace_bufdesc_t dt_buf; /* staging buffer */
+ dt_pq_t *dt_bufq; /* CPU-specific data queue */
struct dt_pfdict *dt_pfdict; /* dictionary of printf conversions */
dt_version_t dt_vmax; /* optional ceiling on program API binding */
dtrace_attribute_t dt_amin; /* optional floor on program attributes */
@@ -305,6 +307,11 @@
struct utsname dt_uts; /* uname(2) information for system */
dt_list_t dt_lib_dep; /* scratch linked-list of lib dependencies */
dt_list_t dt_lib_dep_sorted; /* dependency sorted library list */
+ dtrace_flowkind_t dt_flow; /* flow kind */
+ const char *dt_prefix; /* recommended flow prefix */
+ int dt_indent; /* recommended flow indent */
+ dtrace_epid_t dt_last_epid; /* most recently consumed EPID */
+ uint64_t dt_last_timestamp; /* most recently consumed timestamp */
};
/*
@@ -438,7 +445,6 @@
EDT_VERSREDUCED, /* requested API version has been reduced */
EDT_CTF, /* libctf called failed (dt_ctferr has more) */
EDT_COMPILER, /* error in D program compilation */
- EDT_NOREG, /* register allocation failure */
EDT_NOTUPREG, /* tuple register allocation failure */
EDT_NOMEM, /* memory allocation failure */
EDT_INT2BIG, /* integer limit exceeded */
--- a/usr/src/lib/libdtrace/common/dt_open.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_open.c Sun Aug 12 11:56:48 2012 +0100
@@ -22,7 +22,7 @@
/*
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2011, Joyent, Inc. All rights reserved.
- * Copyright (c) 2011 by Delphix. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#include <sys/types.h>
@@ -81,7 +81,7 @@
/*
* The version number should be increased for every customer visible release
- * of Solaris. The major number should be incremented when a fundamental
+ * of DTrace. The major number should be incremented when a fundamental
* change has been made that would affect all consumers, and would reflect
* sweeping changes to DTrace or the D language. The minor number should be
* incremented when a change is introduced that could break scripts that had
@@ -110,8 +110,9 @@
#define DT_VERS_1_8 DT_VERSION_NUMBER(1, 8, 0)
#define DT_VERS_1_8_1 DT_VERSION_NUMBER(1, 8, 1)
#define DT_VERS_1_9 DT_VERSION_NUMBER(1, 9, 0)
-#define DT_VERS_LATEST DT_VERS_1_9
-#define DT_VERS_STRING "Sun D 1.9"
+#define DT_VERS_1_9_1 DT_VERSION_NUMBER(1, 9, 1)
+#define DT_VERS_LATEST DT_VERS_1_9_1
+#define DT_VERS_STRING "Sun D 1.9.1"
const dt_version_t _dtrace_versions[] = {
DT_VERS_1_0, /* D API 1.0.0 (PSARC 2001/466) Solaris 10 FCS */
@@ -132,6 +133,7 @@
DT_VERS_1_8, /* D API 1.8 */
DT_VERS_1_8_1, /* D API 1.8.1 */
DT_VERS_1_9, /* D API 1.9 */
+ DT_VERS_1_9_1, /* D API 1.9.1 */
0
};
@@ -937,7 +939,7 @@
dtp->dt_mods = calloc(dtp->dt_modbuckets, sizeof (dt_module_t *));
dtp->dt_provbuckets = _dtrace_strbuckets;
dtp->dt_provs = calloc(dtp->dt_provbuckets, sizeof (dt_provider_t *));
- dt_proc_hash_create(dtp);
+ dt_proc_init(dtp);
dtp->dt_vmax = DT_VERS_LATEST;
dtp->dt_cpp_path = strdup(_dtrace_defcpp);
dtp->dt_cpp_argv = malloc(sizeof (char *));
@@ -951,8 +953,9 @@
(void) uname(&dtp->dt_uts);
if (dtp->dt_mods == NULL || dtp->dt_provs == NULL ||
- dtp->dt_procs == NULL || dtp->dt_ld_path == NULL ||
- dtp->dt_cpp_path == NULL || dtp->dt_cpp_argv == NULL)
+ dtp->dt_procs == NULL || dtp->dt_proc_env == NULL ||
+ dtp->dt_ld_path == NULL || dtp->dt_cpp_path == NULL ||
+ dtp->dt_cpp_argv == NULL)
return (set_open_errno(dtp, errp, EDT_NOMEM));
for (i = 0; i < DTRACEOPT_MAX; i++)
@@ -1318,7 +1321,7 @@
int i;
if (dtp->dt_procs != NULL)
- dt_proc_hash_destroy(dtp);
+ dt_proc_fini(dtp);
while ((pgp = dt_list_next(&dtp->dt_programs)) != NULL)
dt_program_destroy(dtp, pgp);
@@ -1365,7 +1368,6 @@
dt_strdata_destroy(dtp);
dt_buffered_destroy(dtp);
dt_aggregate_destroy(dtp);
- free(dtp->dt_buf.dtbd_data);
dt_pfdict_destroy(dtp);
dt_provmod_destroy(&dtp->dt_provmod);
dt_dof_fini(dtp);
--- a/usr/src/lib/libdtrace/common/dt_options.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_options.c Sun Aug 12 11:56:48 2012 +0100
@@ -24,6 +24,10 @@
* Use is subject to license terms.
*/
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
#include <sys/resource.h>
#include <sys/mman.h>
#include <sys/types.h>
@@ -364,6 +368,61 @@
return (0);
}
+static int
+dt_opt_setenv(dtrace_hdl_t *dtp, const char *arg, uintptr_t option)
+{
+ char **p;
+ char *var;
+ int i;
+
+ /*
+ * We can't effectively set environment variables from #pragma lines
+ * since the processes have already been spawned.
+ */
+ if (dtp->dt_pcb != NULL)
+ return (dt_set_errno(dtp, EDT_BADOPTCTX));
+
+ if (arg == NULL)
+ return (dt_set_errno(dtp, EDT_BADOPTVAL));
+
+ if (!option && strchr(arg, '=') != NULL)
+ return (dt_set_errno(dtp, EDT_BADOPTVAL));
+
+ for (i = 1, p = dtp->dt_proc_env; *p != NULL; i++, p++)
+ continue;
+
+ for (p = dtp->dt_proc_env; *p != NULL; p++) {
+ var = strchr(*p, '=');
+ if (var == NULL)
+ var = *p + strlen(*p);
+ if (strncmp(*p, arg, var - *p) == 0) {
+ dt_free(dtp, *p);
+ *p = dtp->dt_proc_env[i - 1];
+ dtp->dt_proc_env[i - 1] = NULL;
+ i--;
+ }
+ }
+
+ if (option) {
+ if ((var = strdup(arg)) == NULL)
+ return (dt_set_errno(dtp, EDT_NOMEM));
+
+ if ((p = dt_alloc(dtp, sizeof (char *) * (i + 1))) == NULL) {
+ dt_free(dtp, var);
+ return (dt_set_errno(dtp, EDT_NOMEM));
+ }
+
+ bcopy(dtp->dt_proc_env, p, sizeof (char *) * i);
+ dt_free(dtp, dtp->dt_proc_env);
+ dtp->dt_proc_env = p;
+
+ dtp->dt_proc_env[i - 1] = var;
+ dtp->dt_proc_env[i] = NULL;
+ }
+
+ return (0);
+}
+
/*ARGSUSED*/
static int
dt_opt_stdc(dtrace_hdl_t *dtp, const char *arg, uintptr_t option)
@@ -407,7 +466,6 @@
return (0);
}
-
/*ARGSUSED*/
static int
dt_opt_tree(dtrace_hdl_t *dtp, const char *arg, uintptr_t option)
@@ -874,6 +932,7 @@
{ "nolibs", dt_opt_cflags, DTRACE_C_NOLIBS },
{ "pgmax", dt_opt_pgmax },
{ "pspec", dt_opt_cflags, DTRACE_C_PSPEC },
+ { "setenv", dt_opt_setenv, 1 },
{ "stdc", dt_opt_stdc },
{ "strip", dt_opt_dflags, DTRACE_D_STRIP },
{ "syslibdir", dt_opt_syslibdir },
@@ -882,6 +941,7 @@
{ "udefs", dt_opt_invcflags, DTRACE_C_UNODEF },
{ "undef", dt_opt_cpp_opts, (uintptr_t)"-U" },
{ "unodefs", dt_opt_cflags, DTRACE_C_UNODEF },
+ { "unsetenv", dt_opt_setenv, 0 },
{ "verbose", dt_opt_cflags, DTRACE_C_DIFV },
{ "version", dt_opt_version },
{ "zdefs", dt_opt_cflags, DTRACE_C_ZDEFS },
@@ -909,6 +969,7 @@
{ "statusrate", dt_opt_rate, DTRACEOPT_STATUSRATE },
{ "strsize", dt_opt_strsize, DTRACEOPT_STRSIZE },
{ "ustackframes", dt_opt_runtime, DTRACEOPT_USTACKFRAMES },
+ { "temporal", dt_opt_runtime, DTRACEOPT_TEMPORAL },
{ NULL }
};
--- a/usr/src/lib/libdtrace/common/dt_parser.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_parser.c Sun Aug 12 11:56:48 2012 +0100
@@ -22,6 +22,7 @@
/*
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2011, Joyent Inc. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
/*
@@ -93,6 +94,7 @@
*/
#include <sys/param.h>
+#include <sys/sysmacros.h>
#include <limits.h>
#include <setjmp.h>
#include <strings.h>
@@ -1856,6 +1858,38 @@
return (dnp);
}
+/*
+ * If an integer constant is being cast to another integer type, we can
+ * perform the cast as part of integer constant folding in this pass. We must
+ * take action when the integer is being cast to a smaller type or if it is
+ * changing signed-ness. If so, we first shift rp's bits bits high (losing
+ * excess bits if narrowing) and then shift them down with either a logical
+ * shift (unsigned) or arithmetic shift (signed).
+ */
+static void
+dt_cast(dt_node_t *lp, dt_node_t *rp)
+{
+ size_t srcsize = dt_node_type_size(rp);
+ size_t dstsize = dt_node_type_size(lp);
+
+ if (dstsize < srcsize) {
+ int n = (sizeof (uint64_t) - dstsize) * NBBY;
+ rp->dn_value <<= n;
+ rp->dn_value >>= n;
+ } else if (dstsize > srcsize) {
+ int n = (sizeof (uint64_t) - srcsize) * NBBY;
+ int s = (dstsize - srcsize) * NBBY;
+
+ rp->dn_value <<= n;
+ if (rp->dn_flags & DT_NF_SIGNED) {
+ rp->dn_value = (intmax_t)rp->dn_value >> s;
+ rp->dn_value >>= n - s;
+ } else {
+ rp->dn_value >>= n;
+ }
+ }
+}
+
dt_node_t *
dt_node_op2(int op, dt_node_t *lp, dt_node_t *rp)
{
@@ -2005,32 +2039,9 @@
}
}
- /*
- * If an integer constant is being cast to another integer type, we can
- * perform the cast as part of integer constant folding in this pass.
- * We must take action when the integer is being cast to a smaller type
- * or if it is changing signed-ness. If so, we first shift rp's bits
- * bits high (losing excess bits if narrowing) and then shift them down
- * with either a logical shift (unsigned) or arithmetic shift (signed).
- */
if (op == DT_TOK_LPAR && rp->dn_kind == DT_NODE_INT &&
dt_node_is_integer(lp)) {
- size_t srcsize = dt_node_type_size(rp);
- size_t dstsize = dt_node_type_size(lp);
-
- if ((dstsize < srcsize) || ((lp->dn_flags & DT_NF_SIGNED) ^
- (rp->dn_flags & DT_NF_SIGNED))) {
- int n = dstsize < srcsize ?
- (sizeof (uint64_t) * NBBY - dstsize * NBBY) :
- (sizeof (uint64_t) * NBBY - srcsize * NBBY);
-
- rp->dn_value <<= n;
- if (lp->dn_flags & DT_NF_SIGNED)
- rp->dn_value = (intmax_t)rp->dn_value >> n;
- else
- rp->dn_value = rp->dn_value >> n;
- }
-
+ dt_cast(lp, rp);
dt_node_type_propagate(lp, rp);
dt_node_attr_assign(rp, dt_attr_min(lp->dn_attr, rp->dn_attr));
dt_node_free(lp);
@@ -2889,14 +2900,14 @@
case DT_TOK_DEREF:
/*
* If the deref operator is applied to a translated pointer,
- * we can just set our output type to the base translation.
+ * we set our output type to the output of the translation.
*/
if ((idp = dt_node_resolve(cp, DT_IDENT_XLPTR)) != NULL) {
dt_xlator_t *dxp = idp->di_data;
dnp->dn_ident = &dxp->dx_souid;
dt_node_type_assign(dnp,
- DT_DYN_CTFP(dtp), DT_DYN_TYPE(dtp));
+ dnp->dn_ident->di_ctfp, dnp->dn_ident->di_type);
break;
}
@@ -3072,6 +3083,31 @@
return (dnp);
}
+static void
+dt_assign_common(dt_node_t *dnp)
+{
+ dt_node_t *lp = dnp->dn_left;
+ dt_node_t *rp = dnp->dn_right;
+ int op = dnp->dn_op;
+
+ if (rp->dn_kind == DT_NODE_INT)
+ dt_cast(lp, rp);
+
+ if (!(lp->dn_flags & DT_NF_LVALUE)) {
+ xyerror(D_OP_LVAL, "operator %s requires modifiable "
+ "lvalue as an operand\n", opstr(op));
+ /* see K&R[A7.17] */
+ }
+
+ if (!(lp->dn_flags & DT_NF_WRITABLE)) {
+ xyerror(D_OP_WRITE, "operator %s can only be applied "
+ "to a writable variable\n", opstr(op));
+ }
+
+ dt_node_type_propagate(lp, dnp); /* see K&R[A7.17] */
+ dt_node_attr_assign(dnp, dt_attr_min(lp->dn_attr, rp->dn_attr));
+}
+
static dt_node_t *
dt_cook_op2(dt_node_t *dnp, uint_t idflags)
{
@@ -3550,19 +3586,7 @@
}
}
asgn_common:
- if (!(lp->dn_flags & DT_NF_LVALUE)) {
- xyerror(D_OP_LVAL, "operator %s requires modifiable "
- "lvalue as an operand\n", opstr(op));
- /* see K&R[A7.17] */
- }
-
- if (!(lp->dn_flags & DT_NF_WRITABLE)) {
- xyerror(D_OP_WRITE, "operator %s can only be applied "
- "to a writable variable\n", opstr(op));
- }
-
- dt_node_type_propagate(lp, dnp); /* see K&R[A7.17] */
- dt_node_attr_assign(dnp, dt_attr_min(lp->dn_attr, rp->dn_attr));
+ dt_assign_common(dnp);
break;
case DT_TOK_PTR:
@@ -3867,6 +3891,14 @@
dt_node_type_propagate(lp, dnp); /* see K&R[A7.5] */
dt_node_attr_assign(dnp, dt_attr_min(lp->dn_attr, rp->dn_attr));
+
+ /*
+ * If it's a pointer then should be able to (attempt to)
+ * assign to it.
+ */
+ if (lkind == CTF_K_POINTER)
+ dnp->dn_flags |= DT_NF_WRITABLE;
+
break;
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libdtrace/common/dt_pq.c Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,157 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+#include <dtrace.h>
+#include <dt_impl.h>
+#include <dt_pq.h>
+#include <assert.h>
+
+/*
+ * Create a new priority queue.
+ *
+ * size is the maximum number of items that will be stored in the priority
+ * queue at one time.
+ */
+dt_pq_t *
+dt_pq_init(dtrace_hdl_t *dtp, uint_t size, dt_pq_value_f value_cb, void *cb_arg)
+{
+ dt_pq_t *p;
+ assert(size > 1);
+
+ if ((p = dt_zalloc(dtp, sizeof (dt_pq_t))) == NULL)
+ return (NULL);
+
+ p->dtpq_items = dt_zalloc(dtp, size * sizeof (p->dtpq_items[0]));
+ if (p->dtpq_items == NULL) {
+ dt_free(dtp, p);
+ return (NULL);
+ }
+
+ p->dtpq_hdl = dtp;
+ p->dtpq_size = size;
+ p->dtpq_last = 1;
+ p->dtpq_value = value_cb;
+ p->dtpq_arg = cb_arg;
+
+ return (p);
+}
+
+void
+dt_pq_fini(dt_pq_t *p)
+{
+ dtrace_hdl_t *dtp = p->dtpq_hdl;
+
+ dt_free(dtp, p->dtpq_items);
+ dt_free(dtp, p);
+}
+
+static uint64_t
+dt_pq_getvalue(dt_pq_t *p, uint_t index)
+{
+ void *item = p->dtpq_items[index];
+ return (p->dtpq_value(item, p->dtpq_arg));
+}
+
+void
+dt_pq_insert(dt_pq_t *p, void *item)
+{
+ uint_t i;
+
+ assert(p->dtpq_last < p->dtpq_size);
+
+ i = p->dtpq_last++;
+ p->dtpq_items[i] = item;
+
+ while (i > 1 && dt_pq_getvalue(p, i) < dt_pq_getvalue(p, i / 2)) {
+ void *tmp = p->dtpq_items[i];
+ p->dtpq_items[i] = p->dtpq_items[i / 2];
+ p->dtpq_items[i / 2] = tmp;
+ i /= 2;
+ }
+}
+
+/*
+ * Return elements from the priority queue. *cookie should be zero when first
+ * called. Returns NULL when there are no more elements.
+ */
+void *
+dt_pq_walk(dt_pq_t *p, uint_t *cookie)
+{
+ (*cookie)++;
+ if (*cookie >= p->dtpq_last)
+ return (NULL);
+
+ return (p->dtpq_items[*cookie]);
+}
+
+void *
+dt_pq_pop(dt_pq_t *p)
+{
+ uint_t i = 1;
+ void *ret;
+
+ assert(p->dtpq_last > 0);
+
+ if (p->dtpq_last == 1)
+ return (NULL);
+
+ ret = p->dtpq_items[1];
+
+ p->dtpq_last--;
+ p->dtpq_items[1] = p->dtpq_items[p->dtpq_last];
+ p->dtpq_items[p->dtpq_last] = NULL;
+
+ for (;;) {
+ uint_t lc = i * 2;
+ uint_t rc = i * 2 + 1;
+ uint_t c;
+ uint64_t v;
+ void *tmp;
+
+ if (lc >= p->dtpq_last)
+ break;
+
+ if (rc >= p->dtpq_last) {
+ c = lc;
+ v = dt_pq_getvalue(p, lc);
+ } else {
+ uint64_t lv = dt_pq_getvalue(p, lc);
+ uint64_t rv = dt_pq_getvalue(p, rc);
+
+ if (lv < rv) {
+ c = lc;
+ v = lv;
+ } else {
+ c = rc;
+ v = rv;
+ }
+ }
+
+ if (v >= dt_pq_getvalue(p, i))
+ break;
+
+ tmp = p->dtpq_items[i];
+ p->dtpq_items[i] = p->dtpq_items[c];
+ p->dtpq_items[c] = tmp;
+
+ i = c;
+ }
+
+ return (ret);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libdtrace/common/dt_pq.h Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,51 @@
+/*
+ * CDDL HEADER START
+ *
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+#ifndef _DT_PQ_H
+#define _DT_PQ_H
+
+#include <dtrace.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint64_t (*dt_pq_value_f)(void *, void *);
+
+typedef struct dt_pq {
+ dtrace_hdl_t *dtpq_hdl; /* dtrace handle */
+ void **dtpq_items; /* array of elements */
+ uint_t dtpq_size; /* count of allocated elements */
+ uint_t dtpq_last; /* next free slot */
+ dt_pq_value_f dtpq_value; /* callback to get the value */
+ void *dtpq_arg; /* callback argument */
+} dt_pq_t;
+
+extern dt_pq_t *dt_pq_init(dtrace_hdl_t *, uint_t size, dt_pq_value_f, void *);
+extern void dt_pq_fini(dt_pq_t *);
+
+extern void dt_pq_insert(dt_pq_t *, void *);
+extern void *dt_pq_pop(dt_pq_t *);
+extern void *dt_pq_walk(dt_pq_t *, uint_t *);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DT_PQ_H */
--- a/usr/src/lib/libdtrace/common/dt_printf.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_printf.c Sun Aug 12 11:56:48 2012 +0100
@@ -22,6 +22,7 @@
/*
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2011, Joyent, Inc. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#include <sys/sysmacros.h>
@@ -154,7 +155,7 @@
pfcheck_dint(dt_pfargv_t *pfv, dt_pfargd_t *pfd, dt_node_t *dnp)
{
if (dnp->dn_flags & DT_NF_SIGNED)
- pfd->pfd_flags |= DT_PFCONV_SIGNED;
+ pfd->pfd_fmt[strlen(pfd->pfd_fmt) - 1] = 'i';
else
pfd->pfd_fmt[strlen(pfd->pfd_fmt) - 1] = 'u';
@@ -642,7 +643,7 @@
{ "hu", "u", "unsigned short", pfcheck_type, pfprint_uint },
{ "hx", "x", "short", pfcheck_xshort, pfprint_uint },
{ "hX", "X", "short", pfcheck_xshort, pfprint_uint },
-{ "i", "i", pfproto_xint, pfcheck_dint, pfprint_dint },
+{ "i", "i", pfproto_xint, pfcheck_xint, pfprint_sint },
{ "I", "s", pfproto_cstr, pfcheck_str, pfprint_inetaddr },
{ "k", "s", "stack", pfcheck_stack, pfprint_stack },
{ "lc", "lc", "int", pfcheck_type, pfprint_sint }, /* a.k.a. wint_t */
--- a/usr/src/lib/libdtrace/common/dt_proc.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_proc.c Sun Aug 12 11:56:48 2012 +0100
@@ -25,6 +25,10 @@
*/
/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+/*
* DTrace Process Control
*
* This file provides a set of routines that permit libdtrace and its clients
@@ -460,7 +464,7 @@
dt_proc_control_data_t *datap = arg;
dtrace_hdl_t *dtp = datap->dpcd_hdl;
dt_proc_t *dpr = datap->dpcd_proc;
- dt_proc_hash_t *dph = dpr->dpr_hdl->dt_procs;
+ dt_proc_hash_t *dph = dtp->dt_procs;
struct ps_prochandle *P = dpr->dpr_proc;
int pfd = Pctlfd(P);
@@ -870,7 +874,8 @@
(void) pthread_mutex_init(&dpr->dpr_lock, NULL);
(void) pthread_cond_init(&dpr->dpr_cv, NULL);
- if ((dpr->dpr_proc = Pcreate(file, argv, &err, NULL, 0)) == NULL) {
+ dpr->dpr_proc = Pxcreate(file, argv, dtp->dt_proc_env, &err, NULL, 0);
+ if (dpr->dpr_proc == NULL) {
return (dt_proc_error(dtp, dpr,
"failed to execute %s: %s\n", file, Pcreate_error(err)));
}
@@ -1034,30 +1039,75 @@
}
void
-dt_proc_hash_create(dtrace_hdl_t *dtp)
+dt_proc_init(dtrace_hdl_t *dtp)
{
+ extern char **environ;
+ static char *envdef[] = {
+ "LD_NOLAZYLOAD=1", /* linker lazy loading hides funcs */
+ NULL
+ };
+ char **p;
+ int i;
+
if ((dtp->dt_procs = dt_zalloc(dtp, sizeof (dt_proc_hash_t) +
- sizeof (dt_proc_t *) * _dtrace_pidbuckets - 1)) != NULL) {
+ sizeof (dt_proc_t *) * _dtrace_pidbuckets - 1)) == NULL)
+ return;
+
+ (void) pthread_mutex_init(&dtp->dt_procs->dph_lock, NULL);
+ (void) pthread_cond_init(&dtp->dt_procs->dph_cv, NULL);
+
+ dtp->dt_procs->dph_hashlen = _dtrace_pidbuckets;
+ dtp->dt_procs->dph_lrulim = _dtrace_pidlrulim;
+
- (void) pthread_mutex_init(&dtp->dt_procs->dph_lock, NULL);
- (void) pthread_cond_init(&dtp->dt_procs->dph_cv, NULL);
+ /*
+ * Count how big our environment needs to be.
+ */
+ for (i = 1, p = environ; *p != NULL; i++, p++)
+ continue;
+ for (p = envdef; *p != NULL; i++, p++)
+ continue;
+
+ if ((dtp->dt_proc_env = dt_zalloc(dtp, sizeof (char *) * i)) == NULL)
+ return;
- dtp->dt_procs->dph_hashlen = _dtrace_pidbuckets;
- dtp->dt_procs->dph_lrulim = _dtrace_pidlrulim;
+ for (i = 0, p = environ; *p != NULL; i++, p++) {
+ if ((dtp->dt_proc_env[i] = strdup(*p)) == NULL)
+ goto err;
+ }
+ for (p = envdef; *p != NULL; i++, p++) {
+ if ((dtp->dt_proc_env[i] = strdup(*p)) == NULL)
+ goto err;
}
+
+ return;
+
+err:
+ while (--i != 0) {
+ dt_free(dtp, dtp->dt_proc_env[i]);
+ }
+ dt_free(dtp, dtp->dt_proc_env);
+ dtp->dt_proc_env = NULL;
}
void
-dt_proc_hash_destroy(dtrace_hdl_t *dtp)
+dt_proc_fini(dtrace_hdl_t *dtp)
{
dt_proc_hash_t *dph = dtp->dt_procs;
dt_proc_t *dpr;
+ char **p;
while ((dpr = dt_list_next(&dph->dph_lrulist)) != NULL)
dt_proc_destroy(dtp, dpr->dpr_proc);
dtp->dt_procs = NULL;
dt_free(dtp, dph);
+
+ for (p = dtp->dt_proc_env; *p != NULL; p++)
+ dt_free(dtp, *p);
+
+ dt_free(dtp, dtp->dt_proc_env);
+ dtp->dt_proc_env = NULL;
}
struct ps_prochandle *
--- a/usr/src/lib/libdtrace/common/dt_proc.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_proc.h Sun Aug 12 11:56:48 2012 +0100
@@ -24,11 +24,13 @@
* Use is subject to license terms.
*/
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
#ifndef _DT_PROC_H
#define _DT_PROC_H
-#pragma ident "%Z%%M% %I% %E% SMI"
-
#include <libproc.h>
#include <dtrace.h>
#include <pthread.h>
@@ -106,8 +108,8 @@
extern void dt_proc_unlock(dtrace_hdl_t *, struct ps_prochandle *);
extern dt_proc_t *dt_proc_lookup(dtrace_hdl_t *, struct ps_prochandle *, int);
-extern void dt_proc_hash_create(dtrace_hdl_t *);
-extern void dt_proc_hash_destroy(dtrace_hdl_t *);
+extern void dt_proc_init(dtrace_hdl_t *);
+extern void dt_proc_fini(dtrace_hdl_t *);
#ifdef __cplusplus
}
--- a/usr/src/lib/libdtrace/common/dt_regset.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_regset.c Sun Aug 12 11:56:48 2012 +0100
@@ -19,12 +19,15 @@
*
* CDDL HEADER END
*/
+
/*
* Copyright 2003 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
-#pragma ident "%Z%%M% %I% %E% SMI"
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
#include <sys/types.h>
#include <sys/bitmap.h>
@@ -33,18 +36,19 @@
#include <stdlib.h>
#include <dt_regset.h>
+#include <dt_impl.h>
dt_regset_t *
-dt_regset_create(ulong_t size)
+dt_regset_create(ulong_t nregs)
{
- ulong_t n = BT_BITOUL(size + 1); /* + 1 for %r0 */
+ ulong_t n = BT_BITOUL(nregs);
dt_regset_t *drp = malloc(sizeof (dt_regset_t));
if (drp == NULL)
return (NULL);
drp->dr_bitmap = malloc(sizeof (ulong_t) * n);
- drp->dr_size = size + 1;
+ drp->dr_size = nregs;
if (drp->dr_bitmap == NULL) {
dt_regset_destroy(drp);
@@ -68,6 +72,25 @@
bzero(drp->dr_bitmap, sizeof (ulong_t) * BT_BITOUL(drp->dr_size));
}
+void
+dt_regset_assert_free(dt_regset_t *drp)
+{
+ int reg;
+ boolean_t fail = B_FALSE;
+ for (reg = 0; reg < drp->dr_size; reg++) {
+ if (BT_TEST(drp->dr_bitmap, reg) != 0) {
+ dt_dprintf("%%r%d was left allocated\n", reg);
+ fail = B_TRUE;
+ }
+ }
+
+ /*
+ * We set this during dtest runs to check for register leaks.
+ */
+ if (fail && getenv("DTRACE_DEBUG_REGSET") != NULL)
+ abort();
+}
+
int
dt_regset_alloc(dt_regset_t *drp)
{
@@ -95,13 +118,15 @@
}
}
- return (-1); /* no available registers */
+ xyerror(D_NOREG, "Insufficient registers to generate code");
+ /*NOTREACHED*/
+ return (-1);
}
void
dt_regset_free(dt_regset_t *drp, int reg)
{
- assert(reg > 0 && reg < drp->dr_size);
+ assert(reg >= 0 && reg < drp->dr_size);
assert(BT_TEST(drp->dr_bitmap, reg) != 0);
BT_CLEAR(drp->dr_bitmap, reg);
}
--- a/usr/src/lib/libdtrace/common/dt_regset.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_regset.h Sun Aug 12 11:56:48 2012 +0100
@@ -19,16 +19,19 @@
*
* CDDL HEADER END
*/
+
/*
* Copyright 2003 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
#ifndef _DT_REGSET_H
#define _DT_REGSET_H
-#pragma ident "%Z%%M% %I% %E% SMI"
-
#include <sys/types.h>
#ifdef __cplusplus
@@ -45,6 +48,7 @@
extern void dt_regset_reset(dt_regset_t *);
extern int dt_regset_alloc(dt_regset_t *);
extern void dt_regset_free(dt_regset_t *, int);
+extern void dt_regset_assert_free(dt_regset_t *);
#ifdef __cplusplus
}
--- a/usr/src/lib/libdtrace/common/dt_subr.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/common/dt_subr.c Sun Aug 12 11:56:48 2012 +0100
@@ -21,6 +21,7 @@
/*
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#include <sys/sysmacros.h>
@@ -577,8 +578,8 @@
size_t avail;
/*
- * It's not legal to use buffered ouput if there is not a
- * handler for buffered output.
+ * Using buffered output is not allowed if a handler has
+ * not been installed.
*/
if (dtp->dt_bufhdlr == NULL) {
va_end(ap);
--- a/usr/src/lib/libdtrace/i386/dt_isadep.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libdtrace/i386/dt_isadep.c Sun Aug 12 11:56:48 2012 +0100
@@ -24,6 +24,10 @@
* Use is subject to license terms.
*/
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
#include <stdlib.h>
#include <assert.h>
#include <errno.h>
@@ -481,7 +485,8 @@
* another debugger attached to this process. The original instruction
* can't be recovered so this must fail.
*/
- if (x86dis.d86_len == 1 && instr[0] == FASTTRAP_INSTR)
+ if (x86dis.d86_len == 1 &&
+ (uchar_t)x86dis.d86_bytes[0] == FASTTRAP_INSTR)
return (-1);
return (x86dis.d86_len);
--- a/usr/src/lib/libshare/smb/Makefile.com Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libshare/smb/Makefile.com Sun Aug 12 11:56:48 2012 +0100
@@ -22,6 +22,8 @@
# Copyright 2010 Sun Microsystems, Inc. All rights reserved.
# Use is subject to license terms.
#
+# Copyright 2012 Nexenta Systems, Inc. All rights reserved.
+#
LIBRARY = libshare_smb.a
VERS = .1
@@ -49,6 +51,7 @@
CFLAGS += $(CCVERBOSE)
CPPFLAGS += -D_REENTRANT -I/usr/include/libxml2 \
-I$(SRCDIR)/../common
+$(ENABLE_SMB_PRINTING) CPPFLAGS += -DHAVE_CUPS
.KEEP_STATE:
--- a/usr/src/lib/libshare/smb/libshare_smb.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libshare/smb/libshare_smb.c Sun Aug 12 11:56:48 2012 +0100
@@ -21,6 +21,7 @@
/*
* Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
/*
@@ -76,6 +77,7 @@
static int range_check_validator(int, char *);
static int range_check_validator_zero_ok(int, char *);
static int string_length_check_validator(int, char *);
+static int print_enable_validator(int, char *);
static int true_false_validator(int, char *);
static int ipv4_validator(int, char *);
static int hostname_validator(int, char *);
@@ -912,7 +914,7 @@
{ SMB_CI_AUTOHOME_MAP, 0, MAX_VALUE_BUFLEN, path_validator, 0 },
{ SMB_CI_IPV6_ENABLE, 0, 0, true_false_validator,
SMB_REFRESH_REFRESH },
- { SMB_CI_PRINT_ENABLE, 0, 0, true_false_validator,
+ { SMB_CI_PRINT_ENABLE, 0, 0, print_enable_validator,
SMB_REFRESH_REFRESH },
{ SMB_CI_MAP, 0, MAX_VALUE_BUFLEN, cmd_validator, SMB_REFRESH_REFRESH },
{ SMB_CI_UNMAP, 0, MAX_VALUE_BUFLEN, cmd_validator,
@@ -999,6 +1001,27 @@
}
/*
+ * If printing support is compiled in, this is the same as:
+ * true_false_validator. Otherwise, only allow false.
+ */
+/*ARGSUSED*/
+static int
+print_enable_validator(int index, char *value)
+{
+ if (value == NULL)
+ return (SA_BAD_VALUE);
+
+#ifdef HAVE_CUPS
+ if (strcasecmp(value, "true") == 0)
+ return (SA_OK);
+#endif
+ if (strcasecmp(value, "false") == 0)
+ return (SA_OK);
+
+ return (SA_BAD_VALUE);
+}
+
+/*
* Check IP v4 address.
*/
/*ARGSUSED*/
--- a/usr/src/lib/libzfs/Makefile.com Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/Makefile.com Sun Aug 12 11:56:48 2012 +0100
@@ -69,7 +69,7 @@
C99MODE= -xc99=%all
C99LMODE= -Xc99=%all
LDLIBS += -lc -lm -ldevid -lgen -lnvpair -luutil -lavl -lefi \
- -ladm -lidmap -ltsol -lmd -lumem
+ -ladm -lidmap -ltsol -lmd -lumem -lzfs_core
CPPFLAGS += $(INCS) -D_LARGEFILE64_SOURCE=1 -D_REENTRANT
SRCS= $(OBJS_COMMON:%.o=$(SRCDIR)/%.c) \
--- a/usr/src/lib/libzfs/common/libzfs.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/libzfs.h Sun Aug 12 11:56:48 2012 +0100
@@ -54,7 +54,8 @@
/*
* libzfs errors
*/
-enum {
+typedef enum zfs_error {
+ EZFS_SUCCESS = 0, /* no error -- success */
EZFS_NOMEM = 2000, /* out of memory */
EZFS_BADPROP, /* invalid property value */
EZFS_PROPREADONLY, /* cannot set readonly property */
@@ -126,7 +127,7 @@
EZFS_DIFFDATA, /* bad zfs diff data */
EZFS_POOLREADONLY, /* pool is in read-only mode */
EZFS_UNKNOWN
-};
+} zfs_error_t;
/*
* The following data structures are all part
@@ -182,6 +183,9 @@
extern void libzfs_print_on_error(libzfs_handle_t *, boolean_t);
+extern void zfs_save_arguments(int argc, char **, char *, int);
+extern int zpool_log_history(libzfs_handle_t *, const char *);
+
extern int libzfs_errno(libzfs_handle_t *);
extern const char *libzfs_error_action(libzfs_handle_t *);
extern const char *libzfs_error_description(libzfs_handle_t *);
@@ -216,7 +220,7 @@
*/
extern int zpool_create(libzfs_handle_t *, const char *, nvlist_t *,
nvlist_t *, nvlist_t *);
-extern int zpool_destroy(zpool_handle_t *);
+extern int zpool_destroy(zpool_handle_t *, const char *);
extern int zpool_add(zpool_handle_t *, nvlist_t *);
typedef struct splitflags {
@@ -312,7 +316,8 @@
* requiring administrative attention. There is no corresponding
* message ID.
*/
- ZPOOL_STATUS_VERSION_OLDER, /* older on-disk version */
+ ZPOOL_STATUS_VERSION_OLDER, /* older legacy on-disk version */
+ ZPOOL_STATUS_FEAT_DISABLED, /* supported features are disabled */
ZPOOL_STATUS_RESILVERING, /* device being resilvered */
ZPOOL_STATUS_OFFLINE_DEV, /* device online */
ZPOOL_STATUS_REMOVED_DEV, /* removed device */
@@ -338,8 +343,8 @@
/*
* Import and export functions
*/
-extern int zpool_export(zpool_handle_t *, boolean_t);
-extern int zpool_export_force(zpool_handle_t *);
+extern int zpool_export(zpool_handle_t *, boolean_t, const char *);
+extern int zpool_export_force(zpool_handle_t *, const char *);
extern int zpool_import(libzfs_handle_t *, nvlist_t *, const char *,
char *altroot);
extern int zpool_import_props(libzfs_handle_t *, nvlist_t *, const char *,
@@ -373,7 +378,7 @@
*/
struct zfs_cmd;
-extern const char *zfs_history_event_names[LOG_END];
+extern const char *zfs_history_event_names[];
extern char *zpool_vdev_name(libzfs_handle_t *, zpool_handle_t *, nvlist_t *,
boolean_t verbose);
@@ -381,9 +386,6 @@
extern int zpool_get_history(zpool_handle_t *, nvlist_t **);
extern int zpool_history_unpack(char *, uint64_t, uint64_t *,
nvlist_t ***, uint_t *);
-extern void zpool_set_history_str(const char *subcommand, int argc,
- char **argv, char *history_str);
-extern int zpool_stage_history(libzfs_handle_t *, const char *);
extern void zpool_obj_to_path(zpool_handle_t *, uint64_t, uint64_t, char *,
size_t len);
extern int zfs_ioctl(libzfs_handle_t *, int, struct zfs_cmd *);
@@ -436,8 +438,6 @@
char *propbuf, int proplen, boolean_t literal);
extern int zfs_prop_get_feature(zfs_handle_t *zhp, const char *propname,
char *buf, size_t len);
-extern int zfs_get_snapused_int(zfs_handle_t *firstsnap, zfs_handle_t *lastsnap,
- uint64_t *usedp);
extern uint64_t zfs_prop_get_int(zfs_handle_t *, zfs_prop_t);
extern int zfs_prop_inherit(zfs_handle_t *, const char *, boolean_t);
extern const char *zfs_prop_values(zfs_prop_t);
@@ -553,6 +553,8 @@
extern int zfs_destroy_snaps_nvl(zfs_handle_t *, nvlist_t *, boolean_t);
extern int zfs_clone(zfs_handle_t *, const char *, nvlist_t *);
extern int zfs_snapshot(libzfs_handle_t *, const char *, boolean_t, nvlist_t *);
+extern int zfs_snapshot_nvl(libzfs_handle_t *hdl, nvlist_t *snaps,
+ nvlist_t *props);
extern int zfs_rollback(zfs_handle_t *, zfs_handle_t *, boolean_t);
extern int zfs_rename(zfs_handle_t *, const char *, boolean_t, boolean_t);
--- a/usr/src/lib/libzfs/common/libzfs_config.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/libzfs_config.c Sun Aug 12 11:56:48 2012 +0100
@@ -337,6 +337,48 @@
}
/*
+ * If the __ZFS_POOL_RESTRICT environment variable is set we only iterate over
+ * pools it lists.
+ *
+ * This is an undocumented feature for use during testing only.
+ *
+ * This function returns B_TRUE if the pool should be skipped
+ * during iteration.
+ */
+static boolean_t
+check_restricted(const char *poolname)
+{
+ static boolean_t initialized = B_FALSE;
+ static char *restricted = NULL;
+
+ const char *cur, *end;
+ int len, namelen;
+
+ if (!initialized) {
+ initialized = B_TRUE;
+ restricted = getenv("__ZFS_POOL_RESTRICT");
+ }
+
+ if (NULL == restricted)
+ return (B_FALSE);
+
+ cur = restricted;
+ namelen = strlen(poolname);
+ do {
+ end = strchr(cur, ' ');
+ len = (NULL == end) ? strlen(cur) : (end - cur);
+
+ if (len == namelen && 0 == strncmp(cur, poolname, len)) {
+ return (B_FALSE);
+ }
+
+ cur += (len + 1);
+ } while (NULL != end);
+
+ return (B_TRUE);
+}
+
+/*
* Iterate over all pools in the system.
*/
int
@@ -359,6 +401,9 @@
for (cn = uu_avl_first(hdl->libzfs_ns_avl); cn != NULL;
cn = uu_avl_next(hdl->libzfs_ns_avl, cn)) {
+ if (check_restricted(cn->cn_name))
+ continue;
+
if (zpool_open_silent(hdl, cn->cn_name, &zhp) != 0) {
hdl->libzfs_pool_iter--;
return (-1);
@@ -394,6 +439,9 @@
for (cn = uu_avl_first(hdl->libzfs_ns_avl); cn != NULL;
cn = uu_avl_next(hdl->libzfs_ns_avl, cn)) {
+ if (check_restricted(cn->cn_name))
+ continue;
+
if ((zhp = make_dataset_handle(hdl, cn->cn_name)) == NULL)
continue;
--- a/usr/src/lib/libzfs/common/libzfs_dataset.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/libzfs_dataset.c Sun Aug 12 11:56:48 2012 +0100
@@ -1407,8 +1407,7 @@
libzfs_handle_t *hdl = zhp->zfs_hdl;
nvlist_t *nvl = NULL, *realprops;
zfs_prop_t prop;
- boolean_t do_prefix;
- uint64_t idx;
+ boolean_t do_prefix = B_TRUE;
int added_resv;
(void) snprintf(errbuf, sizeof (errbuf),
@@ -1447,12 +1446,17 @@
}
/*
- * If the dataset's canmount property is being set to noauto,
- * then we want to prevent unmounting & remounting it.
+ * We don't want to unmount & remount the dataset when changing
+ * its canmount property to 'on' or 'noauto'. We only use
+ * the changelist logic to unmount when setting canmount=off.
*/
- do_prefix = !((prop == ZFS_PROP_CANMOUNT) &&
- (zprop_string_to_index(prop, propval, &idx,
- ZFS_TYPE_DATASET) == 0) && (idx == ZFS_CANMOUNT_NOAUTO));
+ if (prop == ZFS_PROP_CANMOUNT) {
+ uint64_t idx;
+ int err = zprop_string_to_index(prop, propval, &idx,
+ ZFS_TYPE_DATASET);
+ if (err == 0 && idx != ZFS_CANMOUNT_OFF)
+ do_prefix = B_FALSE;
+ }
if (do_prefix && (ret = changelist_prefix(cl)) != 0)
goto error;
@@ -2641,25 +2645,6 @@
return (0);
}
-int
-zfs_get_snapused_int(zfs_handle_t *firstsnap, zfs_handle_t *lastsnap,
- uint64_t *usedp)
-{
- int err;
- zfs_cmd_t zc = { 0 };
-
- (void) strlcpy(zc.zc_name, lastsnap->zfs_name, sizeof (zc.zc_name));
- (void) strlcpy(zc.zc_value, firstsnap->zfs_name, sizeof (zc.zc_value));
-
- err = ioctl(lastsnap->zfs_hdl->libzfs_fd, ZFS_IOC_SPACE_SNAPS, &zc);
- if (err)
- return (err);
-
- *usedp = zc.zc_cookie;
-
- return (0);
-}
-
/*
* Returns the name of the given zfs handle.
*/
@@ -2860,7 +2845,6 @@
*/
for (cp = target + prefixlen + 1;
cp = strchr(cp, '/'); *cp = '/', cp++) {
- char *logstr;
*cp = '\0';
@@ -2871,16 +2855,12 @@
continue;
}
- logstr = hdl->libzfs_log_str;
- hdl->libzfs_log_str = NULL;
if (zfs_create(hdl, target, ZFS_TYPE_FILESYSTEM,
NULL) != 0) {
- hdl->libzfs_log_str = logstr;
opname = dgettext(TEXT_DOMAIN, "create");
goto ancestorerr;
}
- hdl->libzfs_log_str = logstr;
h = zfs_open(hdl, target, ZFS_TYPE_FILESYSTEM);
if (h == NULL) {
opname = dgettext(TEXT_DOMAIN, "open");
@@ -2938,12 +2918,12 @@
zfs_create(libzfs_handle_t *hdl, const char *path, zfs_type_t type,
nvlist_t *props)
{
- zfs_cmd_t zc = { 0 };
int ret;
uint64_t size = 0;
uint64_t blocksize = zfs_prop_default_numeric(ZFS_PROP_VOLBLOCKSIZE);
char errbuf[1024];
uint64_t zoned;
+ dmu_objset_type_t ost;
(void) snprintf(errbuf, sizeof (errbuf), dgettext(TEXT_DOMAIN,
"cannot create '%s'"), path);
@@ -2963,17 +2943,16 @@
* will return ENOENT, not EEXIST. To prevent this from happening, we
* first try to see if the dataset exists.
*/
- (void) strlcpy(zc.zc_name, path, sizeof (zc.zc_name));
- if (zfs_dataset_exists(hdl, zc.zc_name, ZFS_TYPE_DATASET)) {
+ if (zfs_dataset_exists(hdl, path, ZFS_TYPE_DATASET)) {
zfs_error_aux(hdl, dgettext(TEXT_DOMAIN,
"dataset already exists"));
return (zfs_error(hdl, EZFS_EXISTS, errbuf));
}
if (type == ZFS_TYPE_VOLUME)
- zc.zc_objset_type = DMU_OST_ZVOL;
+ ost = DMU_OST_ZVOL;
else
- zc.zc_objset_type = DMU_OST_ZFS;
+ ost = DMU_OST_ZFS;
if (props && (props = zfs_valid_proplist(hdl, type, props,
zoned, NULL, errbuf)) == 0)
@@ -3025,15 +3004,10 @@
}
}
- if (props && zcmd_write_src_nvlist(hdl, &zc, props) != 0)
- return (-1);
+ /* create the dataset */
+ ret = lzc_create(path, ost, props);
nvlist_free(props);
- /* create the dataset */
- ret = zfs_ioctl(hdl, ZFS_IOC_CREATE, &zc);
-
- zcmd_free_nvlists(&zc);
-
/* check for failure */
if (ret != 0) {
char parent[ZFS_MAXNAMELEN];
@@ -3084,7 +3058,8 @@
/*
* Destroys the given dataset. The caller must make sure that the filesystem
- * isn't mounted, and that there are no active dependents.
+ * isn't mounted, and that there are no active dependents. If the file system
+ * does not exist this function does nothing.
*/
int
zfs_destroy(zfs_handle_t *zhp, boolean_t defer)
@@ -3100,7 +3075,8 @@
}
zc.zc_defer_destroy = defer;
- if (zfs_ioctl(zhp->zfs_hdl, ZFS_IOC_DESTROY, &zc) != 0) {
+ if (zfs_ioctl(zhp->zfs_hdl, ZFS_IOC_DESTROY, &zc) != 0 &&
+ errno != ENOENT) {
return (zfs_standard_error_fmt(zhp->zfs_hdl, errno,
dgettext(TEXT_DOMAIN, "cannot destroy '%s'"),
zhp->zfs_name));
@@ -3170,33 +3146,35 @@
zfs_destroy_snaps_nvl(zfs_handle_t *zhp, nvlist_t *snaps, boolean_t defer)
{
int ret;
- zfs_cmd_t zc = { 0 };
-
- (void) strlcpy(zc.zc_name, zhp->zfs_name, sizeof (zc.zc_name));
- if (zcmd_write_src_nvlist(zhp->zfs_hdl, &zc, snaps) != 0)
- return (-1);
- zc.zc_defer_destroy = defer;
-
- ret = zfs_ioctl(zhp->zfs_hdl, ZFS_IOC_DESTROY_SNAPS_NVL, &zc);
+ nvlist_t *errlist;
+
+ ret = lzc_destroy_snaps(snaps, defer, &errlist);
+
if (ret != 0) {
- char errbuf[1024];
-
- (void) snprintf(errbuf, sizeof (errbuf), dgettext(TEXT_DOMAIN,
- "cannot destroy snapshots in %s"), zc.zc_name);
-
- switch (errno) {
- case EEXIST:
- zfs_error_aux(zhp->zfs_hdl, dgettext(TEXT_DOMAIN,
- "snapshot is cloned"));
- return (zfs_error(zhp->zfs_hdl, EZFS_EXISTS, errbuf));
-
- default:
- return (zfs_standard_error(zhp->zfs_hdl, errno,
- errbuf));
+ for (nvpair_t *pair = nvlist_next_nvpair(errlist, NULL);
+ pair != NULL; pair = nvlist_next_nvpair(errlist, pair)) {
+ char errbuf[1024];
+ (void) snprintf(errbuf, sizeof (errbuf),
+ dgettext(TEXT_DOMAIN, "cannot destroy snapshot %s"),
+ nvpair_name(pair));
+
+ switch (fnvpair_value_int32(pair)) {
+ case EEXIST:
+ zfs_error_aux(zhp->zfs_hdl,
+ dgettext(TEXT_DOMAIN,
+ "snapshot is cloned"));
+ ret = zfs_error(zhp->zfs_hdl, EZFS_EXISTS,
+ errbuf);
+ break;
+ default:
+ ret = zfs_standard_error(zhp->zfs_hdl, errno,
+ errbuf);
+ break;
+ }
}
}
- return (0);
+ return (ret);
}
/*
@@ -3205,12 +3183,10 @@
int
zfs_clone(zfs_handle_t *zhp, const char *target, nvlist_t *props)
{
- zfs_cmd_t zc = { 0 };
char parent[ZFS_MAXNAMELEN];
int ret;
char errbuf[1024];
libzfs_handle_t *hdl = zhp->zfs_hdl;
- zfs_type_t type;
uint64_t zoned;
assert(zhp->zfs_type == ZFS_TYPE_SNAPSHOT);
@@ -3229,32 +3205,21 @@
(void) parent_name(target, parent, sizeof (parent));
/* do the clone */
- if (ZFS_IS_VOLUME(zhp)) {
- zc.zc_objset_type = DMU_OST_ZVOL;
- type = ZFS_TYPE_VOLUME;
- } else {
- zc.zc_objset_type = DMU_OST_ZFS;
- type = ZFS_TYPE_FILESYSTEM;
- }
if (props) {
+ zfs_type_t type;
+ if (ZFS_IS_VOLUME(zhp)) {
+ type = ZFS_TYPE_VOLUME;
+ } else {
+ type = ZFS_TYPE_FILESYSTEM;
+ }
if ((props = zfs_valid_proplist(hdl, type, props, zoned,
zhp, errbuf)) == NULL)
return (-1);
-
- if (zcmd_write_src_nvlist(hdl, &zc, props) != 0) {
- nvlist_free(props);
- return (-1);
- }
-
- nvlist_free(props);
}
- (void) strlcpy(zc.zc_name, target, sizeof (zc.zc_name));
- (void) strlcpy(zc.zc_value, zhp->zfs_name, sizeof (zc.zc_value));
- ret = zfs_ioctl(zhp->zfs_hdl, ZFS_IOC_CREATE, &zc);
-
- zcmd_free_nvlists(&zc);
+ ret = lzc_clone(target, zhp->zfs_name, props);
+ nvlist_free(props);
if (ret != 0) {
switch (errno) {
@@ -3339,74 +3304,134 @@
return (ret);
}
+typedef struct snapdata {
+ nvlist_t *sd_nvl;
+ const char *sd_snapname;
+} snapdata_t;
+
+static int
+zfs_snapshot_cb(zfs_handle_t *zhp, void *arg)
+{
+ snapdata_t *sd = arg;
+ char name[ZFS_MAXNAMELEN];
+ int rv = 0;
+
+ (void) snprintf(name, sizeof (name),
+ "%s@%s", zfs_get_name(zhp), sd->sd_snapname);
+
+ fnvlist_add_boolean(sd->sd_nvl, name);
+
+ rv = zfs_iter_filesystems(zhp, zfs_snapshot_cb, sd);
+ zfs_close(zhp);
+ return (rv);
+}
+
/*
- * Takes a snapshot of the given dataset.
+ * Creates snapshots. The keys in the snaps nvlist are the snapshots to be
+ * created.
*/
int
+zfs_snapshot_nvl(libzfs_handle_t *hdl, nvlist_t *snaps, nvlist_t *props)
+{
+ int ret;
+ char errbuf[1024];
+ nvpair_t *elem;
+ nvlist_t *errors;
+
+ (void) snprintf(errbuf, sizeof (errbuf), dgettext(TEXT_DOMAIN,
+ "cannot create snapshots "));
+
+ elem = NULL;
+ while ((elem = nvlist_next_nvpair(snaps, elem)) != NULL) {
+ const char *snapname = nvpair_name(elem);
+
+ /* validate the target name */
+ if (!zfs_validate_name(hdl, snapname, ZFS_TYPE_SNAPSHOT,
+ B_TRUE)) {
+ (void) snprintf(errbuf, sizeof (errbuf),
+ dgettext(TEXT_DOMAIN,
+ "cannot create snapshot '%s'"), snapname);
+ return (zfs_error(hdl, EZFS_INVALIDNAME, errbuf));
+ }
+ }
+
+ if (props != NULL &&
+ (props = zfs_valid_proplist(hdl, ZFS_TYPE_SNAPSHOT,
+ props, B_FALSE, NULL, errbuf)) == NULL) {
+ return (-1);
+ }
+
+ ret = lzc_snapshot(snaps, props, &errors);
+
+ if (ret != 0) {
+ boolean_t printed = B_FALSE;
+ for (elem = nvlist_next_nvpair(errors, NULL);
+ elem != NULL;
+ elem = nvlist_next_nvpair(errors, elem)) {
+ (void) snprintf(errbuf, sizeof (errbuf),
+ dgettext(TEXT_DOMAIN,
+ "cannot create snapshot '%s'"), nvpair_name(elem));
+ (void) zfs_standard_error(hdl,
+ fnvpair_value_int32(elem), errbuf);
+ printed = B_TRUE;
+ }
+ if (!printed) {
+ switch (ret) {
+ case EXDEV:
+ zfs_error_aux(hdl, dgettext(TEXT_DOMAIN,
+ "multiple snapshots of same "
+ "fs not allowed"));
+ (void) zfs_error(hdl, EZFS_EXISTS, errbuf);
+
+ break;
+ default:
+ (void) zfs_standard_error(hdl, ret, errbuf);
+ }
+ }
+ }
+
+ nvlist_free(props);
+ nvlist_free(errors);
+ return (ret);
+}
+
+int
zfs_snapshot(libzfs_handle_t *hdl, const char *path, boolean_t recursive,
nvlist_t *props)
{
- const char *delim;
- char parent[ZFS_MAXNAMELEN];
+ int ret;
+ snapdata_t sd = { 0 };
+ char fsname[ZFS_MAXNAMELEN];
+ char *cp;
zfs_handle_t *zhp;
- zfs_cmd_t zc = { 0 };
- int ret;
char errbuf[1024];
(void) snprintf(errbuf, sizeof (errbuf), dgettext(TEXT_DOMAIN,
- "cannot snapshot '%s'"), path);
-
- /* validate the target name */
+ "cannot snapshot %s"), path);
+
if (!zfs_validate_name(hdl, path, ZFS_TYPE_SNAPSHOT, B_TRUE))
return (zfs_error(hdl, EZFS_INVALIDNAME, errbuf));
- if (props) {
- if ((props = zfs_valid_proplist(hdl, ZFS_TYPE_SNAPSHOT,
- props, B_FALSE, NULL, errbuf)) == NULL)
- return (-1);
-
- if (zcmd_write_src_nvlist(hdl, &zc, props) != 0) {
- nvlist_free(props);
- return (-1);
- }
-
- nvlist_free(props);
- }
-
- /* make sure the parent exists and is of the appropriate type */
- delim = strchr(path, '@');
- (void) strncpy(parent, path, delim - path);
- parent[delim - path] = '\0';
-
- if ((zhp = zfs_open(hdl, parent, ZFS_TYPE_FILESYSTEM |
+ (void) strlcpy(fsname, path, sizeof (fsname));
+ cp = strchr(fsname, '@');
+ *cp = '\0';
+ sd.sd_snapname = cp + 1;
+
+ if ((zhp = zfs_open(hdl, fsname, ZFS_TYPE_FILESYSTEM |
ZFS_TYPE_VOLUME)) == NULL) {
- zcmd_free_nvlists(&zc);
return (-1);
}
- (void) strlcpy(zc.zc_name, zhp->zfs_name, sizeof (zc.zc_name));
- (void) strlcpy(zc.zc_value, delim+1, sizeof (zc.zc_value));
- if (ZFS_IS_VOLUME(zhp))
- zc.zc_objset_type = DMU_OST_ZVOL;
- else
- zc.zc_objset_type = DMU_OST_ZFS;
- zc.zc_cookie = recursive;
- ret = zfs_ioctl(zhp->zfs_hdl, ZFS_IOC_SNAPSHOT, &zc);
-
- zcmd_free_nvlists(&zc);
-
- /*
- * if it was recursive, the one that actually failed will be in
- * zc.zc_name.
- */
- if (ret != 0) {
- (void) snprintf(errbuf, sizeof (errbuf), dgettext(TEXT_DOMAIN,
- "cannot create snapshot '%s@%s'"), zc.zc_name, zc.zc_value);
- (void) zfs_standard_error(hdl, errno, errbuf);
+ verify(nvlist_alloc(&sd.sd_nvl, NV_UNIQUE_NAME, 0) == 0);
+ if (recursive) {
+ (void) zfs_snapshot_cb(zfs_handle_dup(zhp), &sd);
+ } else {
+ fnvlist_add_boolean(sd.sd_nvl, path);
}
+ ret = zfs_snapshot_nvl(hdl, sd.sd_nvl, props);
+ nvlist_free(sd.sd_nvl);
zfs_close(zhp);
-
return (ret);
}
@@ -3434,17 +3459,13 @@
zfs_get_type(zhp) == ZFS_TYPE_SNAPSHOT &&
zfs_prop_get_int(zhp, ZFS_PROP_CREATETXG) >
cbp->cb_create) {
- char *logstr;
cbp->cb_dependent = B_TRUE;
cbp->cb_error |= zfs_iter_dependents(zhp, B_FALSE,
rollback_destroy, cbp);
cbp->cb_dependent = B_FALSE;
- logstr = zhp->zfs_hdl->libzfs_log_str;
- zhp->zfs_hdl->libzfs_log_str = NULL;
cbp->cb_error |= zfs_destroy(zhp, B_FALSE);
- zhp->zfs_hdl->libzfs_log_str = logstr;
}
} else {
/* We must destroy this clone; first unmount it */
--- a/usr/src/lib/libzfs/common/libzfs_impl.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/libzfs_impl.h Sun Aug 12 11:56:48 2012 +0100
@@ -21,11 +21,11 @@
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2011 by Delphix. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
-#ifndef _LIBFS_IMPL_H
-#define _LIBFS_IMPL_H
+#ifndef _LIBZFS_IMPL_H
+#define _LIBZFS_IMPL_H
#include <sys/dmu.h>
#include <sys/fs/zfs.h>
@@ -36,6 +36,7 @@
#include <libuutil.h>
#include <libzfs.h>
#include <libshare.h>
+#include <libzfs_core.h>
#include <fm/libtopo.h>
@@ -67,7 +68,6 @@
int libzfs_desc_active;
char libzfs_action[1024];
char libzfs_desc[1024];
- char *libzfs_log_str;
int libzfs_printerr;
int libzfs_storeerr; /* stuff error messages into buffer */
void *libzfs_sharehdl; /* libshare handle */
@@ -213,4 +213,4 @@
}
#endif
-#endif /* _LIBFS_IMPL_H */
+#endif /* _LIBZFS_IMPL_H */
--- a/usr/src/lib/libzfs/common/libzfs_iter.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/libzfs_iter.c Sun Aug 12 11:56:48 2012 +0100
@@ -22,7 +22,7 @@
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright 2010 Nexenta Systems, Inc. All rights reserved.
- * Copyright (c) 2011 by Delphix. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#include <stdio.h>
@@ -301,12 +301,11 @@
zfs_iter_snapspec(zfs_handle_t *fs_zhp, const char *spec_orig,
zfs_iter_f func, void *arg)
{
- char buf[ZFS_MAXNAMELEN];
- char *comma_separated, *cp;
+ char *buf, *comma_separated, *cp;
int err = 0;
int ret = 0;
- (void) strlcpy(buf, spec_orig, sizeof (buf));
+ buf = zfs_strdup(fs_zhp->zfs_hdl, spec_orig);
cp = buf;
while ((comma_separated = strsep(&cp, ",")) != NULL) {
@@ -364,6 +363,7 @@
}
}
+ free(buf);
return (ret);
}
--- a/usr/src/lib/libzfs/common/libzfs_pool.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/libzfs_pool.c Sun Aug 12 11:56:48 2012 +0100
@@ -34,6 +34,7 @@
#include <stdlib.h>
#include <strings.h>
#include <unistd.h>
+#include <libgen.h>
#include <sys/efi_partition.h>
#include <sys/vtoc.h>
#include <sys/zfs_ioctl.h>
@@ -1205,7 +1206,7 @@
* datasets left in the pool.
*/
int
-zpool_destroy(zpool_handle_t *zhp)
+zpool_destroy(zpool_handle_t *zhp, const char *log_str)
{
zfs_cmd_t zc = { 0 };
zfs_handle_t *zfp = NULL;
@@ -1217,6 +1218,7 @@
return (-1);
(void) strlcpy(zc.zc_name, zhp->zpool_name, sizeof (zc.zc_name));
+ zc.zc_history = (uint64_t)(uintptr_t)log_str;
if (zfs_ioctl(hdl, ZFS_IOC_POOL_DESTROY, &zc) != 0) {
(void) snprintf(msg, sizeof (msg), dgettext(TEXT_DOMAIN,
@@ -1371,8 +1373,9 @@
* Exports the pool from the system. The caller must ensure that there are no
* mounted datasets in the pool.
*/
-int
-zpool_export_common(zpool_handle_t *zhp, boolean_t force, boolean_t hardforce)
+static int
+zpool_export_common(zpool_handle_t *zhp, boolean_t force, boolean_t hardforce,
+ const char *log_str)
{
zfs_cmd_t zc = { 0 };
char msg[1024];
@@ -1383,6 +1386,7 @@
(void) strlcpy(zc.zc_name, zhp->zpool_name, sizeof (zc.zc_name));
zc.zc_cookie = force;
zc.zc_guid = hardforce;
+ zc.zc_history = (uint64_t)(uintptr_t)log_str;
if (zfs_ioctl(zhp->zpool_hdl, ZFS_IOC_POOL_EXPORT, &zc) != 0) {
switch (errno) {
@@ -1404,15 +1408,15 @@
}
int
-zpool_export(zpool_handle_t *zhp, boolean_t force)
+zpool_export(zpool_handle_t *zhp, boolean_t force, const char *log_str)
{
- return (zpool_export_common(zhp, force, B_FALSE));
+ return (zpool_export_common(zhp, force, B_FALSE, log_str));
}
int
-zpool_export_force(zpool_handle_t *zhp)
+zpool_export_force(zpool_handle_t *zhp, const char *log_str)
{
- return (zpool_export_common(zhp, B_TRUE, B_TRUE));
+ return (zpool_export_common(zhp, B_TRUE, B_TRUE, log_str));
}
static void
@@ -3574,40 +3578,30 @@
}
void
-zpool_set_history_str(const char *subcommand, int argc, char **argv,
- char *history_str)
+zfs_save_arguments(int argc, char **argv, char *string, int len)
{
- int i;
-
- (void) strlcpy(history_str, subcommand, HIS_MAX_RECORD_LEN);
- for (i = 1; i < argc; i++) {
- if (strlen(history_str) + 1 + strlen(argv[i]) >
- HIS_MAX_RECORD_LEN)
- break;
- (void) strlcat(history_str, " ", HIS_MAX_RECORD_LEN);
- (void) strlcat(history_str, argv[i], HIS_MAX_RECORD_LEN);
+ (void) strlcpy(string, basename(argv[0]), len);
+ for (int i = 1; i < argc; i++) {
+ (void) strlcat(string, " ", len);
+ (void) strlcat(string, argv[i], len);
}
}
-/*
- * Stage command history for logging.
- */
int
-zpool_stage_history(libzfs_handle_t *hdl, const char *history_str)
+zpool_log_history(libzfs_handle_t *hdl, const char *message)
{
- if (history_str == NULL)
- return (EINVAL);
-
- if (strlen(history_str) > HIS_MAX_RECORD_LEN)
- return (EINVAL);
-
- if (hdl->libzfs_log_str != NULL)
- free(hdl->libzfs_log_str);
-
- if ((hdl->libzfs_log_str = strdup(history_str)) == NULL)
- return (no_memory(hdl));
-
- return (0);
+ zfs_cmd_t zc = { 0 };
+ nvlist_t *args;
+ int err;
+
+ args = fnvlist_alloc();
+ fnvlist_add_string(args, "message", message);
+ err = zcmd_write_src_nvlist(hdl, &zc, args);
+ if (err == 0)
+ err = ioctl(hdl->libzfs_fd, ZFS_IOC_LOG_HISTORY, &zc);
+ nvlist_free(args);
+ zcmd_free_nvlists(&zc);
+ return (err);
}
/*
--- a/usr/src/lib/libzfs/common/libzfs_sendrecv.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/libzfs_sendrecv.c Sun Aug 12 11:56:48 2012 +0100
@@ -21,7 +21,7 @@
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2011 by Delphix. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
* Copyright (c) 2012, Joyent, Inc. All rights reserved.
*/
@@ -1381,7 +1381,6 @@
avl_tree_t *fsavl = NULL;
static uint64_t holdseq;
int spa_version;
- boolean_t holdsnaps = B_FALSE;
pthread_t tid;
int pipefd[2];
dedup_arg_t dda = { 0 };
@@ -1404,11 +1403,6 @@
}
}
- if (!flags->dryrun && zfs_spa_version(zhp, &spa_version) == 0 &&
- spa_version >= SPA_VERSION_USERREFS &&
- (flags->doall || flags->replicate))
- holdsnaps = B_TRUE;
-
if (flags->dedup && !flags->dryrun) {
featureflags |= (DMU_BACKUP_FEATURE_DEDUP |
DMU_BACKUP_FEATURE_DEDUPPROPS);
@@ -1530,7 +1524,18 @@
sdd.filter_cb_arg = cb_arg;
if (debugnvp)
sdd.debugnv = *debugnvp;
- if (holdsnaps || flags->progress) {
+
+ /*
+ * Some flags require that we place user holds on the datasets that are
+ * being sent so they don't get destroyed during the send. We can skip
+ * this step if the pool is imported read-only since the datasets cannot
+ * be destroyed.
+ */
+ if (!flags->dryrun && !zpool_get_prop_int(zfs_get_pool_handle(zhp),
+ ZPOOL_PROP_READONLY, NULL) &&
+ zfs_spa_version(zhp, &spa_version) == 0 &&
+ spa_version >= SPA_VERSION_USERREFS &&
+ (flags->doall || flags->replicate)) {
++holdseq;
(void) snprintf(sdd.holdtag, sizeof (sdd.holdtag),
".send-%d-%llu", getpid(), (u_longlong_t)holdseq);
--- a/usr/src/lib/libzfs/common/libzfs_status.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/libzfs_status.c Sun Aug 12 11:56:48 2012 +0100
@@ -44,6 +44,7 @@
#include <string.h>
#include <unistd.h>
#include "libzfs_impl.h"
+#include "zfeature_common.h"
/*
* Message ID table. This must be kept in sync with the ZPOOL_STATUS_* defines
@@ -319,6 +320,30 @@
if (SPA_VERSION_IS_SUPPORTED(version) && version != SPA_VERSION)
return (ZPOOL_STATUS_VERSION_OLDER);
+ /*
+ * Usable pool with disabled features
+ */
+ if (version >= SPA_VERSION_FEATURES) {
+ int i;
+ nvlist_t *feat;
+
+ if (isimport) {
+ feat = fnvlist_lookup_nvlist(config,
+ ZPOOL_CONFIG_LOAD_INFO);
+ feat = fnvlist_lookup_nvlist(feat,
+ ZPOOL_CONFIG_ENABLED_FEAT);
+ } else {
+ feat = fnvlist_lookup_nvlist(config,
+ ZPOOL_CONFIG_FEATURE_STATS);
+ }
+
+ for (i = 0; i < SPA_FEATURES; i++) {
+ zfeature_info_t *fi = &spa_feature_table[i];
+ if (!nvlist_exists(feat, fi->fi_guid))
+ return (ZPOOL_STATUS_FEAT_DISABLED);
+ }
+ }
+
return (ZPOOL_STATUS_OK);
}
--- a/usr/src/lib/libzfs/common/libzfs_util.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/libzfs_util.c Sun Aug 12 11:56:48 2012 +0100
@@ -43,6 +43,7 @@
#include <sys/types.h>
#include <libzfs.h>
+#include <libzfs_core.h>
#include "libzfs_impl.h"
#include "zfs_prop.h"
@@ -630,6 +631,14 @@
hdl->libzfs_sharetab = fopen("/etc/dfs/sharetab", "r");
+ if (libzfs_core_init() != 0) {
+ (void) close(hdl->libzfs_fd);
+ (void) fclose(hdl->libzfs_mnttab);
+ (void) fclose(hdl->libzfs_sharetab);
+ free(hdl);
+ return (NULL);
+ }
+
zfs_prop_init();
zpool_prop_init();
zpool_feature_init();
@@ -647,12 +656,11 @@
if (hdl->libzfs_sharetab)
(void) fclose(hdl->libzfs_sharetab);
zfs_uninit_libshare(hdl);
- if (hdl->libzfs_log_str)
- (void) free(hdl->libzfs_log_str);
zpool_free_handles(hdl);
libzfs_fru_clear(hdl, B_TRUE);
namespace_clear(hdl);
libzfs_mnttab_fini(hdl);
+ libzfs_core_fini();
free(hdl);
}
@@ -814,17 +822,7 @@
int
zfs_ioctl(libzfs_handle_t *hdl, int request, zfs_cmd_t *zc)
{
- int error;
-
- zc->zc_history = (uint64_t)(uintptr_t)hdl->libzfs_log_str;
- error = ioctl(hdl->libzfs_fd, request, zc);
- if (hdl->libzfs_log_str) {
- free(hdl->libzfs_log_str);
- hdl->libzfs_log_str = NULL;
- }
- zc->zc_history = 0;
-
- return (error);
+ return (ioctl(hdl->libzfs_fd, request, zc));
}
/*
--- a/usr/src/lib/libzfs/common/llib-lzfs Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/llib-lzfs Sun Aug 12 11:56:48 2012 +0100
@@ -32,6 +32,7 @@
/*PROTOLIB1*/
#include <libzfs.h>
+#include <libzfs_core.h>
#include "../../../common/zfs/zfs_comutil.h"
#include "../../../common/zfs/zfs_fletcher.h"
#include "../../../common/zfs/zfs_prop.h"
--- a/usr/src/lib/libzfs/common/mapfile-vers Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzfs/common/mapfile-vers Sun Aug 12 11:56:48 2012 +0100
@@ -76,7 +76,6 @@
zfs_get_holds;
zfs_get_name;
zfs_get_pool_handle;
- zfs_get_snapused_int;
zfs_get_user_props;
zfs_get_type;
zfs_handle_dup;
@@ -133,6 +132,7 @@
zfs_release;
zfs_rename;
zfs_rollback;
+ zfs_save_arguments;
zfs_send;
zfs_share;
zfs_shareall;
@@ -144,6 +144,7 @@
zfs_smb_acl_remove;
zfs_smb_acl_rename;
zfs_snapshot;
+ zfs_snapshot_nvl;
zfs_spa_version;
zfs_spa_version_map;
zfs_type_to_name;
@@ -181,6 +182,7 @@
zpool_fru_set;
zpool_get_config;
zpool_get_errlog;
+ zpool_get_features;
zpool_get_handle;
zpool_get_history;
zpool_get_name;
@@ -197,6 +199,7 @@
zpool_is_bootable;
zpool_iter;
zpool_label_disk;
+ zpool_log_history;
zpool_mount_datasets;
zpool_name_to_prop;
zpool_obj_to_path;
@@ -217,9 +220,7 @@
zpool_reopen;
zpool_scan;
zpool_search_import;
- zpool_set_history_str;
zpool_set_prop;
- zpool_stage_history;
zpool_state_to_name;
zpool_unmount_datasets;
zpool_upgrade;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libzfs_core/Makefile Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,64 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+#
+# Copyright 2007 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+include ../Makefile.lib
+
+HDRS= libzfs_core.h
+
+HDRDIR= common
+
+SUBDIRS= $(MACH)
+$(BUILD64)SUBDIRS += $(MACH64)
+
+all := TARGET= all
+clean := TARGET= clean
+clobber := TARGET= clobber
+install := TARGET= install
+lint := TARGET= lint
+
+MSGFILES = `$(GREP) -l gettext $(HDRDIR)/*.[ch]`
+POFILE = libzfs_core.po
+
+.KEEP_STATE:
+
+all clean clobber install lint: $(SUBDIRS)
+
+$(POFILE): pofile_MSGFILES
+
+install_h: $(ROOTHDRS)
+
+check: $(CHECKHDRS)
+
+_msg: $(MSGDOMAINPOFILE)
+
+$(SUBDIRS): FRC
+ @cd $@; pwd; $(MAKE) $(TARGET)
+
+FRC:
+
+include ../Makefile.targ
+include ../../Makefile.msg.targ
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libzfs_core/Makefile.com Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,69 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+#
+# Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+
+LIBRARY= libzfs_core.a
+VERS= .1
+
+OBJS_SHARED=
+
+OBJS_COMMON= \
+ libzfs_core.o
+
+OBJECTS= $(OBJS_COMMON) $(OBJS_SHARED)
+
+include ../../Makefile.lib
+
+# libzfs_core must be installed in the root filesystem for mount(1M)
+include ../../Makefile.rootfs
+
+LIBS= $(DYNLIB) $(LINTLIB)
+
+SRCDIR = ../common
+
+INCS += -I$(SRCDIR)
+INCS += -I../../../uts/common/fs/zfs
+INCS += -I../../../common/zfs
+INCS += -I../../libc/inc
+
+C99MODE= -xc99=%all
+C99LMODE= -Xc99=%all
+LDLIBS += -lc -lnvpair
+CPPFLAGS += $(INCS) -D_LARGEFILE64_SOURCE=1 -D_REENTRANT
+
+SRCS= $(OBJS_COMMON:%.o=$(SRCDIR)/%.c) \
+ $(OBJS_SHARED:%.o=$(SRC)/common/zfs/%.c)
+$(LINTLIB) := SRCS= $(SRCDIR)/$(LINTSRC)
+
+.KEEP_STATE:
+
+all: $(LIBS)
+
+lint: lintcheck
+
+pics/%.o: ../../../common/zfs/%.c
+ $(COMPILE.c) -o $@ $<
+ $(POST_PROCESS_O)
+
+include ../../Makefile.targ
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libzfs_core/amd64/Makefile Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,30 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License, Version 1.0 only
+# (the "License"). You may not use this file except in compliance
+# with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+#
+# Copyright 2005 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+include ../Makefile.com
+include ../../Makefile.lib.64
+
+install: all $(ROOTLIBS64) $(ROOTLINKS64)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libzfs_core/common/libzfs_core.c Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,477 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+/*
+ * LibZFS_Core (lzc) is intended to replace most functionality in libzfs.
+ * It has the following characteristics:
+ *
+ * - Thread Safe. libzfs_core is accessible concurrently from multiple
+ * threads. This is accomplished primarily by avoiding global data
+ * (e.g. caching). Since it's thread-safe, there is no reason for a
+ * process to have multiple libzfs "instances". Therefore, we store
+ * our few pieces of data (e.g. the file descriptor) in global
+ * variables. The fd is reference-counted so that the libzfs_core
+ * library can be "initialized" multiple times (e.g. by different
+ * consumers within the same process).
+ *
+ * - Committed Interface. The libzfs_core interface will be committed,
+ * therefore consumers can compile against it and be confident that
+ * their code will continue to work on future releases of this code.
+ * Currently, the interface is Evolving (not Committed), but we intend
+ * to commit to it once it is more complete and we determine that it
+ * meets the needs of all consumers.
+ *
+ * - Programatic Error Handling. libzfs_core communicates errors with
+ * defined error numbers, and doesn't print anything to stdout/stderr.
+ *
+ * - Thin Layer. libzfs_core is a thin layer, marshaling arguments
+ * to/from the kernel ioctls. There is generally a 1:1 correspondence
+ * between libzfs_core functions and ioctls to /dev/zfs.
+ *
+ * - Clear Atomicity. Because libzfs_core functions are generally 1:1
+ * with kernel ioctls, and kernel ioctls are general atomic, each
+ * libzfs_core function is atomic. For example, creating multiple
+ * snapshots with a single call to lzc_snapshot() is atomic -- it
+ * can't fail with only some of the requested snapshots created, even
+ * in the event of power loss or system crash.
+ *
+ * - Continued libzfs Support. Some higher-level operations (e.g.
+ * support for "zfs send -R") are too complicated to fit the scope of
+ * libzfs_core. This functionality will continue to live in libzfs.
+ * Where appropriate, libzfs will use the underlying atomic operations
+ * of libzfs_core. For example, libzfs may implement "zfs send -R |
+ * zfs receive" by using individual "send one snapshot", rename,
+ * destroy, and "receive one snapshot" operations in libzfs_core.
+ * /sbin/zfs and /zbin/zpool will link with both libzfs and
+ * libzfs_core. Other consumers should aim to use only libzfs_core,
+ * since that will be the supported, stable interface going forwards.
+ */
+
+#include <libzfs_core.h>
+#include <ctype.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <sys/nvpair.h>
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/zfs_ioctl.h>
+
+static int g_fd;
+static pthread_mutex_t g_lock = PTHREAD_MUTEX_INITIALIZER;
+static int g_refcount;
+
+int
+libzfs_core_init(void)
+{
+ (void) pthread_mutex_lock(&g_lock);
+ if (g_refcount == 0) {
+ g_fd = open("/dev/zfs", O_RDWR);
+ if (g_fd < 0) {
+ (void) pthread_mutex_unlock(&g_lock);
+ return (errno);
+ }
+ }
+ g_refcount++;
+ (void) pthread_mutex_unlock(&g_lock);
+ return (0);
+}
+
+void
+libzfs_core_fini(void)
+{
+ (void) pthread_mutex_lock(&g_lock);
+ ASSERT3S(g_refcount, >, 0);
+ g_refcount--;
+ if (g_refcount == 0)
+ (void) close(g_fd);
+ (void) pthread_mutex_unlock(&g_lock);
+}
+
+static int
+lzc_ioctl(zfs_ioc_t ioc, const char *name,
+ nvlist_t *source, nvlist_t **resultp)
+{
+ zfs_cmd_t zc = { 0 };
+ int error = 0;
+ char *packed;
+ size_t size;
+
+ ASSERT3S(g_refcount, >, 0);
+
+ (void) strlcpy(zc.zc_name, name, sizeof (zc.zc_name));
+
+ packed = fnvlist_pack(source, &size);
+ zc.zc_nvlist_src = (uint64_t)(uintptr_t)packed;
+ zc.zc_nvlist_src_size = size;
+
+ if (resultp != NULL) {
+ zc.zc_nvlist_dst_size = MAX(size * 2, 128 * 1024);
+ zc.zc_nvlist_dst = (uint64_t)(uintptr_t)
+ malloc(zc.zc_nvlist_dst_size);
+ if (zc.zc_nvlist_dst == NULL) {
+ error = ENOMEM;
+ goto out;
+ }
+ }
+
+ while (ioctl(g_fd, ioc, &zc) != 0) {
+ if (errno == ENOMEM && resultp != NULL) {
+ free((void *)(uintptr_t)zc.zc_nvlist_dst);
+ zc.zc_nvlist_dst_size *= 2;
+ zc.zc_nvlist_dst = (uint64_t)(uintptr_t)
+ malloc(zc.zc_nvlist_dst_size);
+ if (zc.zc_nvlist_dst == NULL) {
+ error = ENOMEM;
+ goto out;
+ }
+ } else {
+ error = errno;
+ break;
+ }
+ }
+ if (zc.zc_nvlist_dst_filled) {
+ *resultp = fnvlist_unpack((void *)(uintptr_t)zc.zc_nvlist_dst,
+ zc.zc_nvlist_dst_size);
+ } else if (resultp != NULL) {
+ *resultp = NULL;
+ }
+
+out:
+ fnvlist_pack_free(packed, size);
+ free((void *)(uintptr_t)zc.zc_nvlist_dst);
+ return (error);
+}
+
+int
+lzc_create(const char *fsname, dmu_objset_type_t type, nvlist_t *props)
+{
+ int error;
+ nvlist_t *args = fnvlist_alloc();
+ fnvlist_add_int32(args, "type", type);
+ if (props != NULL)
+ fnvlist_add_nvlist(args, "props", props);
+ error = lzc_ioctl(ZFS_IOC_CREATE, fsname, args, NULL);
+ nvlist_free(args);
+ return (error);
+}
+
+int
+lzc_clone(const char *fsname, const char *origin,
+ nvlist_t *props)
+{
+ int error;
+ nvlist_t *args = fnvlist_alloc();
+ fnvlist_add_string(args, "origin", origin);
+ if (props != NULL)
+ fnvlist_add_nvlist(args, "props", props);
+ error = lzc_ioctl(ZFS_IOC_CLONE, fsname, args, NULL);
+ nvlist_free(args);
+ return (error);
+}
+
+/*
+ * Creates snapshots.
+ *
+ * The keys in the snaps nvlist are the snapshots to be created.
+ * They must all be in the same pool.
+ *
+ * The props nvlist is properties to set. Currently only user properties
+ * are supported. { user:prop_name -> string value }
+ *
+ * The returned results nvlist will have an entry for each snapshot that failed.
+ * The value will be the (int32) error code.
+ *
+ * The return value will be 0 if all snapshots were created, otherwise it will
+ * be the errno of a (undetermined) snapshot that failed.
+ */
+int
+lzc_snapshot(nvlist_t *snaps, nvlist_t *props, nvlist_t **errlist)
+{
+ nvpair_t *elem;
+ nvlist_t *args;
+ int error;
+ char pool[MAXNAMELEN];
+
+ *errlist = NULL;
+
+ /* determine the pool name */
+ elem = nvlist_next_nvpair(snaps, NULL);
+ if (elem == NULL)
+ return (0);
+ (void) strlcpy(pool, nvpair_name(elem), sizeof (pool));
+ pool[strcspn(pool, "/@")] = '\0';
+
+ args = fnvlist_alloc();
+ fnvlist_add_nvlist(args, "snaps", snaps);
+ if (props != NULL)
+ fnvlist_add_nvlist(args, "props", props);
+
+ error = lzc_ioctl(ZFS_IOC_SNAPSHOT, pool, args, errlist);
+ nvlist_free(args);
+
+ return (error);
+}
+
+/*
+ * Destroys snapshots.
+ *
+ * The keys in the snaps nvlist are the snapshots to be destroyed.
+ * They must all be in the same pool.
+ *
+ * Snapshots that do not exist will be silently ignored.
+ *
+ * If 'defer' is not set, and a snapshot has user holds or clones, the
+ * destroy operation will fail and none of the snapshots will be
+ * destroyed.
+ *
+ * If 'defer' is set, and a snapshot has user holds or clones, it will be
+ * marked for deferred destruction, and will be destroyed when the last hold
+ * or clone is removed/destroyed.
+ *
+ * The return value will be 0 if all snapshots were destroyed (or marked for
+ * later destruction if 'defer' is set) or didn't exist to begin with.
+ *
+ * Otherwise the return value will be the errno of a (undetermined) snapshot
+ * that failed, no snapshots will be destroyed, and the errlist will have an
+ * entry for each snapshot that failed. The value in the errlist will be
+ * the (int32) error code.
+ */
+int
+lzc_destroy_snaps(nvlist_t *snaps, boolean_t defer, nvlist_t **errlist)
+{
+ nvpair_t *elem;
+ nvlist_t *args;
+ int error;
+ char pool[MAXNAMELEN];
+
+ /* determine the pool name */
+ elem = nvlist_next_nvpair(snaps, NULL);
+ if (elem == NULL)
+ return (0);
+ (void) strlcpy(pool, nvpair_name(elem), sizeof (pool));
+ pool[strcspn(pool, "/@")] = '\0';
+
+ args = fnvlist_alloc();
+ fnvlist_add_nvlist(args, "snaps", snaps);
+ if (defer)
+ fnvlist_add_boolean(args, "defer");
+
+ error = lzc_ioctl(ZFS_IOC_DESTROY_SNAPS, pool, args, errlist);
+ nvlist_free(args);
+
+ return (error);
+
+}
+
+int
+lzc_snaprange_space(const char *firstsnap, const char *lastsnap,
+ uint64_t *usedp)
+{
+ nvlist_t *args;
+ nvlist_t *result;
+ int err;
+ char fs[MAXNAMELEN];
+ char *atp;
+
+ /* determine the fs name */
+ (void) strlcpy(fs, firstsnap, sizeof (fs));
+ atp = strchr(fs, '@');
+ if (atp == NULL)
+ return (EINVAL);
+ *atp = '\0';
+
+ args = fnvlist_alloc();
+ fnvlist_add_string(args, "firstsnap", firstsnap);
+
+ err = lzc_ioctl(ZFS_IOC_SPACE_SNAPS, lastsnap, args, &result);
+ nvlist_free(args);
+ if (err == 0)
+ *usedp = fnvlist_lookup_uint64(result, "used");
+ fnvlist_free(result);
+
+ return (err);
+}
+
+boolean_t
+lzc_exists(const char *dataset)
+{
+ /*
+ * The objset_stats ioctl is still legacy, so we need to construct our
+ * own zfs_cmd_t rather than using zfsc_ioctl().
+ */
+ zfs_cmd_t zc = { 0 };
+
+ (void) strlcpy(zc.zc_name, dataset, sizeof (zc.zc_name));
+ return (ioctl(g_fd, ZFS_IOC_OBJSET_STATS, &zc) == 0);
+}
+
+/*
+ * If fromsnap is NULL, a full (non-incremental) stream will be sent.
+ */
+int
+lzc_send(const char *snapname, const char *fromsnap, int fd)
+{
+ nvlist_t *args;
+ int err;
+
+ args = fnvlist_alloc();
+ fnvlist_add_int32(args, "fd", fd);
+ if (fromsnap != NULL)
+ fnvlist_add_string(args, "fromsnap", fromsnap);
+ err = lzc_ioctl(ZFS_IOC_SEND_NEW, snapname, args, NULL);
+ nvlist_free(args);
+ return (err);
+}
+
+/*
+ * If fromsnap is NULL, a full (non-incremental) stream will be estimated.
+ */
+int
+lzc_send_space(const char *snapname, const char *fromsnap, uint64_t *spacep)
+{
+ nvlist_t *args;
+ nvlist_t *result;
+ int err;
+
+ args = fnvlist_alloc();
+ if (fromsnap != NULL)
+ fnvlist_add_string(args, "fromsnap", fromsnap);
+ err = lzc_ioctl(ZFS_IOC_SEND_SPACE, snapname, args, &result);
+ nvlist_free(args);
+ if (err == 0)
+ *spacep = fnvlist_lookup_uint64(result, "space");
+ nvlist_free(result);
+ return (err);
+}
+
+static int
+recv_read(int fd, void *buf, int ilen)
+{
+ char *cp = buf;
+ int rv;
+ int len = ilen;
+
+ do {
+ rv = read(fd, cp, len);
+ cp += rv;
+ len -= rv;
+ } while (rv > 0);
+
+ if (rv < 0 || len != 0)
+ return (EIO);
+
+ return (0);
+}
+
+/*
+ * The simplest receive case: receive from the specified fd, creating the
+ * specified snapshot. Apply the specified properties a "received" properties
+ * (which can be overridden by locally-set properties). If the stream is a
+ * clone, its origin snapshot must be specified by 'origin'. The 'force'
+ * flag will cause the target filesystem to be rolled back or destroyed if
+ * necessary to receive.
+ *
+ * Return 0 on success or an errno on failure.
+ *
+ * Note: this interface does not work on dedup'd streams
+ * (those with DMU_BACKUP_FEATURE_DEDUP).
+ */
+int
+lzc_receive(const char *snapname, nvlist_t *props, const char *origin,
+ boolean_t force, int fd)
+{
+ /*
+ * The receive ioctl is still legacy, so we need to construct our own
+ * zfs_cmd_t rather than using zfsc_ioctl().
+ */
+ zfs_cmd_t zc = { 0 };
+ char *atp;
+ char *packed = NULL;
+ size_t size;
+ dmu_replay_record_t drr;
+ int error;
+
+ ASSERT3S(g_refcount, >, 0);
+
+ /* zc_name is name of containing filesystem */
+ (void) strlcpy(zc.zc_name, snapname, sizeof (zc.zc_name));
+ atp = strchr(zc.zc_name, '@');
+ if (atp == NULL)
+ return (EINVAL);
+ *atp = '\0';
+
+ /* if the fs does not exist, try its parent. */
+ if (!lzc_exists(zc.zc_name)) {
+ char *slashp = strrchr(zc.zc_name, '/');
+ if (slashp == NULL)
+ return (ENOENT);
+ *slashp = '\0';
+
+ }
+
+ /* zc_value is full name of the snapshot to create */
+ (void) strlcpy(zc.zc_value, snapname, sizeof (zc.zc_value));
+
+ if (props != NULL) {
+ /* zc_nvlist_src is props to set */
+ packed = fnvlist_pack(props, &size);
+ zc.zc_nvlist_src = (uint64_t)(uintptr_t)packed;
+ zc.zc_nvlist_src_size = size;
+ }
+
+ /* zc_string is name of clone origin (if DRR_FLAG_CLONE) */
+ if (origin != NULL)
+ (void) strlcpy(zc.zc_string, origin, sizeof (zc.zc_string));
+
+ /* zc_begin_record is non-byteswapped BEGIN record */
+ error = recv_read(fd, &drr, sizeof (drr));
+ if (error != 0)
+ goto out;
+ zc.zc_begin_record = drr.drr_u.drr_begin;
+
+ /* zc_cookie is fd to read from */
+ zc.zc_cookie = fd;
+
+ /* zc guid is force flag */
+ zc.zc_guid = force;
+
+ /* zc_cleanup_fd is unused */
+ zc.zc_cleanup_fd = -1;
+
+ error = ioctl(g_fd, ZFS_IOC_RECV, &zc);
+ if (error != 0)
+ error = errno;
+
+out:
+ if (packed != NULL)
+ fnvlist_pack_free(packed, size);
+ free((void*)(uintptr_t)zc.zc_nvlist_dst);
+ return (error);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libzfs_core/common/libzfs_core.h Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,62 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+#ifndef _LIBZFS_CORE_H
+#define _LIBZFS_CORE_H
+
+#include <libnvpair.h>
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/fs/zfs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int libzfs_core_init(void);
+void libzfs_core_fini(void);
+
+int lzc_snapshot(nvlist_t *snaps, nvlist_t *props, nvlist_t **errlist);
+int lzc_create(const char *fsname, dmu_objset_type_t type, nvlist_t *props);
+int lzc_clone(const char *fsname, const char *origin, nvlist_t *props);
+int lzc_destroy_snaps(nvlist_t *snaps, boolean_t defer, nvlist_t **errlist);
+
+int lzc_snaprange_space(const char *firstsnap, const char *lastsnap,
+ uint64_t *usedp);
+
+int lzc_send(const char *snapname, const char *fromsnap, int fd);
+int lzc_receive(const char *snapname, nvlist_t *props, const char *origin,
+ boolean_t force, int fd);
+int lzc_send_space(const char *snapname, const char *fromsnap,
+ uint64_t *result);
+
+boolean_t lzc_exists(const char *dataset);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LIBZFS_CORE_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libzfs_core/common/llib-lzfs_core Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,28 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
+
+/*LINTLIBRARY*/
+/*PROTOLIB1*/
+
+#include <libzfs_core.h>
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libzfs_core/common/mapfile-vers Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,56 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+# Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2012 by Delphix. All rights reserved.
+#
+# MAPFILE HEADER START
+#
+# WARNING: STOP NOW. DO NOT MODIFY THIS FILE.
+# Object versioning must comply with the rules detailed in
+#
+# usr/src/lib/README.mapfiles
+#
+# You should not be making modifications here until you've read the most current
+# copy of that file. If you need help, contact a gatekeeper for guidance.
+#
+# MAPFILE HEADER END
+#
+
+$mapfile_version 2
+
+SYMBOL_VERSION ILLUMOS_0.1 {
+ global:
+
+ libzfs_core_fini;
+ libzfs_core_init;
+ lzc_clone;
+ lzc_create;
+ lzc_destroy_snaps;
+ lzc_exists;
+ lzc_receive;
+ lzc_send;
+ lzc_send_space;
+ lzc_snaprange_space;
+ lzc_snapshot;
+
+ local:
+ *;
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libzfs_core/i386/Makefile Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,29 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License, Version 1.0 only
+# (the "License"). You may not use this file except in compliance
+# with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+#
+# Copyright 2005 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+include ../Makefile.com
+
+install: all $(ROOTLIBS) $(ROOTLINKS) $(ROOTLINT)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libzfs_core/sparc/Makefile Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,29 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License, Version 1.0 only
+# (the "License"). You may not use this file except in compliance
+# with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+#
+# Copyright 2005 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+include ../Makefile.com
+
+install: all $(ROOTLIBS) $(ROOTLINKS) $(ROOTLINT)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/lib/libzfs_core/sparcv9/Makefile Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,32 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License, Version 1.0 only
+# (the "License"). You may not use this file except in compliance
+# with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+#
+# Copyright 2006 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+include ../Makefile.com
+include ../../Makefile.lib.64
+
+sparcv9_C_PICFLAGS= -K PIC
+
+install: all $(ROOTLIBS64) $(ROOTLINKS64)
--- a/usr/src/lib/libzpool/common/kernel.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzpool/common/kernel.c Sun Aug 12 11:56:48 2012 +0100
@@ -871,6 +871,12 @@
return (0);
}
+uid_t
+crgetruid(cred_t *cr)
+{
+ return (0);
+}
+
gid_t
crgetgid(cred_t *cr)
{
--- a/usr/src/lib/libzpool/common/sys/zfs_context.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/libzpool/common/sys/zfs_context.h Sun Aug 12 11:56:48 2012 +0100
@@ -286,6 +286,7 @@
#define rw_downgrade(rwlp) do { } while (0)
extern uid_t crgetuid(cred_t *cr);
+extern uid_t crgetruid(cred_t *cr);
extern gid_t crgetgid(cred_t *cr);
extern int crgetngroups(cred_t *cr);
extern gid_t *crgetgroups(cred_t *cr);
--- a/usr/src/lib/smbsrv/libmlsvc/Makefile.com Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/smbsrv/libmlsvc/Makefile.com Sun Aug 12 11:56:48 2012 +0100
@@ -19,7 +19,7 @@
# CDDL HEADER END
#
#
-# Copyright 2011 Nexenta Systems, Inc. All rights reserved.
+# Copyright 2012 Nexenta Systems, Inc. All rights reserved.
# Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
#
@@ -87,6 +87,7 @@
-lscf -lcmdutils -lsec -lavl -lnvpair -luutil -luuid -lgen -lzfs -lc
CPPFLAGS += $(INCS) -D_REENTRANT
+$(ENABLE_SMB_PRINTING) CPPFLAGS += -DHAVE_CUPS
SRCS= $(OBJS_COMMON:%.o=$(SRCDIR)/%.c)
--- a/usr/src/lib/smbsrv/libmlsvc/common/spoolss_svc.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/lib/smbsrv/libmlsvc/common/spoolss_svc.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
/*
@@ -44,6 +45,8 @@
#include <smbsrv/nmpipes.h>
#include <mlsvc.h>
+#ifdef HAVE_CUPS
+
#define SPOOLSS_PRINTER "Postscript"
typedef struct smb_spool {
@@ -1194,3 +1197,27 @@
FIXUP_PDU_SIZE(spoolss_GetPrinter_result, size2);
FIXUP_PDU_SIZE(spoolss_GetPrinter, size3);
}
+
+#else /* HAVE_CUPS */
+
+/*
+ * If not HAVE_CUPS, just provide a few "stubs".
+ */
+
+void
+spoolss_initialize(void)
+{
+}
+
+void
+spoolss_finalize(void)
+{
+}
+
+/*ARGSUSED*/
+void
+spoolss_register_copyfile(spoolss_copyfile_t copyfile)
+{
+}
+
+#endif /* HAVE_CUPS */
--- a/usr/src/man/man1/cpio.1 Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/man/man1/cpio.1 Sun Aug 12 11:56:48 2012 +0100
@@ -1,6 +1,7 @@
'\" te
.\" Copyright 1989 AT&T
.\" Copyright (c) 2009, Sun Microsystems, Inc. All Rights Reserved
+.\" Copyright (c) 2012 Gary Mills
.\" Portions Copyright (c) 1992, X/Open Company Limited All Rights Reserved
.\" Sun Microsystems, Inc. gratefully acknowledges The Open Group for permission to reproduce portions of its copyrighted documentation. Original documentation from The Open Group can be obtained online at http://www.opengroup.org/bookstore/.
.\" The Institute of Electrical and Electronics Engineers and The Open Group, have given us permission to reprint portions of their documentation. In the following statement, the phrase "this text" refers to portions of the system documentation. Portions of this text
@@ -16,19 +17,19 @@
.SH SYNOPSIS
.LP
.nf
-\fBcpio\fR \fB-i\fR [\fB-bBcdfkmPrsStuvV6@/\fR] [\fB-C\fR \fIbufsize\fR] [\fB-E\fR \fIfile\fR]
+\fBcpio\fR \fB-i\fR [\fB-bBcdfkmPqrsStuvV6@/\fR] [\fB-C\fR \fIbufsize\fR] [\fB-E\fR \fIfile\fR]
[\fB-H\fR \fIheader\fR] [\fB-I\fR \fI\fR [\fB-M\fR \fImessage\fR]] [\fB-R\fR \fIid\fR] [\fIpattern\fR]...
.fi
.LP
.nf
-\fBcpio\fR \fB-o\fR [\fB-aABcLPvV@/\fR] [\fB-C\fR \fIbufsize\fR] [\fB-H\fR \fIheader\fR]
+\fBcpio\fR \fB-o\fR [\fB-aABcLPqvV@/\fR] [\fB-C\fR \fIbufsize\fR] [\fB-H\fR \fIheader\fR]
[\fB-O\fR \fIfile\fR [\fB-M\fR \fImessage\fR]]
.fi
.LP
.nf
-\fBcpio\fR \fB-p\fR [\fB-adlLmPuvV@/\fR] [\fB-R\fR \fIid\fR] \fIdirectory\fR
+\fBcpio\fR \fB-p\fR [\fB-adlLmPquvV@/\fR] [\fB-R\fR \fIid\fR] \fIdirectory\fR
.fi
.SH DESCRIPTION
@@ -425,6 +426,16 @@
.sp
.ne 2
.na
+\fB\fB-q\fR\fR
+.ad
+.RS 14n
+Quiet. Suppresses the number of blocks message that normally is printed
+after the copy is completed.
+.RE
+
+.sp
+.ne 2
+.na
\fB\fB-r\fR\fR
.ad
.RS 14n
--- a/usr/src/man/man1m/beadm.1m Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/man/man1m/beadm.1m Sun Aug 12 11:56:48 2012 +0100
@@ -6,54 +6,55 @@
.SH SYNOPSIS
.LP
.nf
-\fBbeadm\fR create [\fB-a\fR] [\fB-d\fR \fIdescription\fR]
+\fBbeadm\fR \fBcreate\fR [\fB-a\fR] [\fB-d\fR \fIdescription\fR]
[\fB-e\fR \fInon-activeBeName\fR | \fIbeName@snapshot\fR]
- [\fB-o\fR \fIproperty=value\fR] ... [\fB-p\fR \fIzpool\FI] \fIbeName\fR
+ [\fB-o\fR \fIproperty=value\fR] ... [\fB-p\fR \fIzpool\fR]
+ [\fB-v\fR] \fIbeName\fR
.fi
.LP
.nf
-\fBbeadm\fR \fBcreate\fR \fIbeName@snapshot\fR
+\fBbeadm\fR \fBcreate\fR [\fB-v\fR] \fIbeName@snapshot\fR
.fi
.LP
.nf
-\fBbeadm\fR \fBdestroy\fR [\fB-fFs\fR] \fIbeName\fR | \fIbeName@snapshot\fR
+\fBbeadm\fR \fBdestroy\fR [\fB-fFsv\fR] \fIbeName\fR | \fIbeName@snapshot\fR
.fi
.LP
.nf
-\fBbeadm\fR \fBlist\fR [\fB-a\fR | \fB-ds\fR] [\fB-H\fR] [\fIbeName\fR]
+\fBbeadm\fR \fBlist\fR [\fB-a\fR | \fB-ds\fR] [\fB-H\fR] [\fB-v\fR] [\fIbeName\fR]
.fi
.LP
.nf
-\fBbeadm\fR \fBmount\fR \fIbeName\fR \fImountpoint\fR
+\fBbeadm\fR \fBmount\fR [\fB-v\fR] \fIbeName\fR \fImountpoint\fR
.fi
.LP
.nf
-\fBbeadm\fR \fBunmount\fR [\fB-f\fR] \fIbeName\fR | \fImountpoint\fR
+\fBbeadm\fR \fBunmount\fR [\fB-fv\fR] \fIbeName\fR | \fImountpoint\fR
.fi
.LP
.nf
-\fBbeadm\fR \fBrename\fR \fIbeName\fR \fInewBeName\fR
+\fBbeadm\fR \fBrename\fR [\fB-v\fR] \fIbeName\fR \fInewBeName\fR
.fi
.LP
.nf
-\fBbeadm\fR \fBactivate\fR \fIbeName\fR
+\fBbeadm\fR \fBactivate\fR [\fB-v\fR] \fIbeName\fR
.fi
.LP
.nf
-\fBbeadm\fR \fBrollback\fR \fIbeName\fR \fIsnapshot\fR
+\fBbeadm\fR \fBrollback\fR [\fB-v\fR] \fIbeName\fR \fIsnapshot\fR
.fi
.LP
.nf
-\fBbeadm\fR \fBrollback\fR \fIbeName@snapshot\fR
+\fBbeadm\fR \fBrollback\fR [\fB-v\fR] \fIbeName@snapshot\fR
.fi
.SH DESCRIPTION
@@ -160,9 +161,9 @@
.ne 2
.na
\fBbeadm\fR \fBcreate\fR [\fB-a\fR] [\fB-d\fR \fIdescription\fR]
-[\fB-e\fR \fInon-activeBeName\fR | \fIbeName@snapshot\fR]
- [\fB-o\fR
-\fIproperty=value\fR] ... [\fB-p\fR \fIzpool\fR] \fIbeName\fR
+ [\fB-e\fR \fInon-activeBeName\fR | \fIbeName@snapshot\fR]
+ [\fB-o\fR \fIproperty=value\fR] ... [\fB-p\fR \fIzpool\fR]
+ [\fB-v\fR] \fIbeName\fR
.ad
.sp .6
@@ -239,22 +240,40 @@
default
behavior is to create the new BE in the same pool as as the origin BE.
.RE
+.sp
+.ne 2
+.na
+\fB-v\fR
+.ad
+.sp .6
+.RS 4n
+Verbose mode. Displays verbose error messages from \fBbeadm\fR.
+.RE
.RE
.sp
.ne 2
.na
-\fBbeadm\fR \fBcreate\fR \fIbeName@snapshot\fR
+\fBbeadm\fR \fBcreate\fR [\fB-v\fR] \fIbeName@snapshot\fR
.ad
.sp .6
.RS 4n
Creates a snapshot of the existing BE named beName.
+.sp
+.ne 2
+.na
+\fB-v\fR
+.ad
+.sp .6
+.RS 4n
+Verbose mode. Displays verbose error messages from \fBbeadm\fR.
+.RE
.RE
.sp
.ne 2
.na
-\fBbeadm\fR \fBdestroy\fR [\fB-fFs\fR] \fIbeName\fR | \fIbeName@snapshot\fR
+\fBbeadm\fR \fBdestroy\fR [\fB-fFsv\fR] \fIbeName\fR | \fIbeName@snapshot\fR
.ad
.sp .6
.RS 4n
@@ -294,12 +313,21 @@
Destroy all snapshots of the boot
environment.
.RE
+.sp
+.ne 2
+.na
+\fB-v\fR
+.ad
+.sp .6
+.RS 4n
+Verbose mode. Displays verbose error messages from \fBbeadm\fR.
+.RE
.RE
.sp
.ne 2
.na
-\fBbeadm\fR \fBlist\fR [\fB-a\fR | \fB-ds\fR] [\fB-H\fR] [\fIbeName\fR]
+\fBbeadm\fR \fBlist\fR [\fB-a\fR | \fB-ds\fR] [\fB-H\fR] [\fB-v\fR] [\fIbeName\fR]
.ad
.sp .6
.RS 4n
@@ -358,23 +386,41 @@
Do not list header information. Each field in the list information is
separated by a semicolon.
.RE
+.sp
+.ne 2
+.na
+\fB-v\fR
+.ad
+.sp .6
+.RS 4n
+Verbose mode. Displays verbose error messages from \fBbeadm\fR.
+.RE
.RE
.sp
.ne 2
.na
-\fBbeadm\fR \fBmount\fR \fIbeName\fR \fImountpoint\fR
+\fBbeadm\fR \fBmount\fR [\fB-v\fR] \fIbeName\fR \fImountpoint\fR
.ad
.sp .6
.RS 4n
Mounts a boot environment named beName at mountpoint. mountpoint must be an
already existing empty directory.
+.sp
+.ne 2
+.na
+\fB-v\fR
+.ad
+.sp .6
+.RS 4n
+Verbose mode. Displays verbose error messages from \fBbeadm\fR.
+.RE
.RE
.sp
.ne 2
.na
-\fBbeadm\fR \fBunmount\fR [\fB-f\fR] \fIbeName\fR | \fImountpoint\fR
+\fBbeadm\fR \fBunmount\fR [\fB-fv\fR] \fIbeName\fR | \fImountpoint\fR
.ad
.sp .6
.RS 4n
@@ -389,37 +435,73 @@
.RS 4n
Forcefully unmount the boot environment even if its currently busy.
.RE
+.sp
+.ne 2
+.na
+\fB-v\fR
+.ad
+.sp .6
+.RS 4n
+Verbose mode. Displays verbose error messages from \fBbeadm\fR.
+.RE
.RE
.sp
.ne 2
.na
-\fBbeadm\fR \fBrename\fR \fIbeName\fR \fInewBeName\fR
+\fBbeadm\fR \fBrename\fR [\fB-v\fR] \fIbeName\fR \fInewBeName\fR
.ad
.sp .6
.RS 4n
Renames the boot environment named \fIbeName\fR to \fInewBeName\fR.
+.sp
+.ne 2
+.na
+\fB-v\fR
+.ad
+.sp .6
+.RS 4n
+Verbose mode. Displays verbose error messages from \fBbeadm\fR.
+.RE
.RE
.sp
.ne 2
.na
-\fBbeadm\fR \fBrollback\fR \fIbeName\fR \fIsnapshot\fR | \fIbeName@snapshot\fR
+\fBbeadm\fR \fBrollback\fR [\fB-v\fR] \fIbeName\fR \fIsnapshot\fR | \fIbeName@snapshot\fR
.ad
.sp .6
.RS 4n
Roll back the boot environment named \fIbeName\fR to existing snapshot
of the boot environment named \fIbeName@snapshot\fR.
+.sp
+.ne 2
+.na
+\fB-v\fR
+.ad
+.sp .6
+.RS 4n
+Verbose mode. Displays verbose error messages from \fBbeadm\fR.
+.RE
.RE
.sp
.ne 2
.na
-\fBbeadm\fR \fBactivate\fR \fIbeName\fR
+\fBbeadm\fR \fBactivate\fR [\fB-v\fR] \fIbeName\fR
.ad
.sp .6
.RS 4n
Makes beName the active BE on next reboot.
+.sp
+.ne 2
+.na
+\fB-v\fR
+.ad
+.sp .6
+.RS 4n
+Verbose mode. Displays verbose error messages from \fBbeadm\fR.
+.RE
.RE
.SH ALTERNATE BE LOCATION
--- a/usr/src/man/man1m/ifconfig.1m Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/man/man1m/ifconfig.1m Sun Aug 12 11:56:48 2012 +0100
@@ -1,8 +1,9 @@
'\" te
+.\" Copyright (C) 2012, Darren Reed. All rights reserved
.\" Copyright (C) 2009, Sun Microsystems, Inc. All Rights Reserved
.\" Copyright 1989 AT&T
.\" Copyright (c) 1983 Regents of the University of California. All rights reserved. The Berkeley software License Agreement specifies the terms and conditions for redistribution.
-.TH IFCONFIG 1M "Aug 13, 2009"
+.TH IFCONFIG 1M "July 23, 2012"
.SH NAME
ifconfig \- configure network interface parameters
.SH SYNOPSIS
@@ -48,7 +49,17 @@
specific to that address family. Only privileged users may modify the
configuration of a network interface. Options appearing within braces
(\fB{\|}\fR) indicate that one of the options must be specified.
-.SS "DHCP Configuration"
+.SS Network Interface Observability
+.sp
+.LP
+Network interface observability with \fBifconfig\fR is limited to those
+network interfaces that have been prepared for use with the IP
+protocol suite. The preferred method for configuring a network
+interface for use with TCP/IP is with \fBipadm\fR and alternatively
+with the use of the \fBplumb\fR option as documented below. Network
+interfaces that have not been configured for use with the IP
+protocol suite can only be observed by using the \fBdladm\fR command.
+.SS DHCP Configuration
.sp
.LP
The forms of \fBifconfig\fR that use the \fBauto-dhcp\fR or \fBdhcp\fR
@@ -63,6 +74,10 @@
.SH OPTIONS
.sp
.LP
+When the \fBifconfig\fR command is executed without any options
+its behavior is the same as when the \fB\-a\fR option is supplied
+with no other options or arguments.
+.LP
The following options are supported:
.sp
.ne 2
--- a/usr/src/man/man1m/zfs.1m Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/man/man1m/zfs.1m Sun Aug 12 11:56:48 2012 +0100
@@ -39,7 +39,7 @@
.LP
.nf
\fBzfs\fR \fBsnapshot\fR [\fB-r\fR] [\fB-o\fR \fIproperty\fR=\fIvalue\fR]...
- \fIfilesystem@snapname\fR|\fIvolume@snapname\fR
+ \fIfilesystem@snapname\fR|\fIvolume@snapname\fR...
.fi
.LP
@@ -1837,13 +1837,14 @@
.ne 2
.na
\fB\fBzfs snapshot\fR [\fB-r\fR] [\fB-o\fR \fIproperty\fR=\fIvalue\fR] ...
-\fIfilesystem@snapname\fR|\fIvolume@snapname\fR\fR
+\fIfilesystem@snapname\fR|\fIvolume@snapname\fR\fR...
.ad
.sp .6
.RS 4n
-Creates a snapshot with the given name. All previous modifications by
-successful system calls to the file system are part of the snapshot. See the
-"Snapshots" section for details.
+Creates snapshots with the given names. All previous modifications by
+successful system calls to the file system are part of the snapshots.
+Snapshots are taken atomically, so that all snapshots correspond to the same
+moment in time. See the "Snapshots" section for details.
.sp
.ne 2
.na
@@ -1851,9 +1852,7 @@
.ad
.sp .6
.RS 4n
-Recursively create snapshots of all descendent datasets. Snapshots are taken
-atomically, so that all recursive snapshots correspond to the same moment in
-time.
+Recursively create snapshots of all descendent datasets
.RE
.sp
--- a/usr/src/man/man1m/zpool.1m Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/man/man1m/zpool.1m Sun Aug 12 11:56:48 2012 +0100
@@ -1692,11 +1692,10 @@
.ad
.sp .6
.RS 4n
-Displays all pools formatted using a different \fBZFS\fR on-disk version. Older
-versions can continue to be used, but some features may not be available. These
-pools can be upgraded using "\fBzpool upgrade -a\fR". Pools that are formatted
-with a more recent version are also displayed, although these pools will be
-inaccessible on the system.
+Displays pools which do not have all supported features enabled and pools
+formatted using a legacy ZFS version number. These pools can continue to be
+used, but some features may not be available. Use "\fBzpool upgrade -a\fR"
+to enable all features on all pools.
.RE
.sp
@@ -1706,9 +1705,9 @@
.ad
.sp .6
.RS 4n
-Displays \fBZFS\fR versions supported by the current software. The current
-\fBZFS\fR versions and all previous supported versions are displayed, along
-with an explanation of the features provided with each version.
+Displays legacy \fBZFS\fR versions supported by the current software. See
+\fBzfs-features\fR(5) for a description of feature flags features supported
+by the current software.
.RE
.sp
@@ -1718,16 +1717,18 @@
.ad
.sp .6
.RS 4n
-Upgrades the given pool to the latest on-disk version. Once this is done, the
-pool will no longer be accessible on systems running older versions of the
-software.
+Enables all supported features on the given pool. Once this is done, the
+pool will no longer be accessible on systems that do not support feature
+flags. See \fBzfs-features\fR(5) for details on compatability with systems
+that support feature flags, but do not support all features enabled on the
+pool.
.sp
.ne 2
.na
\fB\fB-a\fR\fR
.ad
.RS 14n
-Upgrades all pools.
+Enables all supported features on all pools.
.RE
.sp
@@ -1736,10 +1737,9 @@
\fB\fB-V\fR \fIversion\fR\fR
.ad
.RS 14n
-Upgrade to the specified version. If the \fB-V\fR flag is not specified, the
-pool is upgraded to the most recent version. This option can only be used to
-increase the version number, and only up to the most recent version supported
-by this software.
+Upgrade to the specified legacy version. If the \fB-V\fR flag is specified, no
+features will be enabled on the pool. This option can only be used to increase
+the version number up to the last supported legacy version number.
.RE
.RE
--- a/usr/src/man/man5/zpool-features.5 Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/man/man5/zpool-features.5 Sun Aug 12 11:56:48 2012 +0100
@@ -20,8 +20,9 @@
.LP
ZFS pool on\-disk format versions are specified via "features" which replace
the old on\-disk format numbers (the last supported on\-disk format number is
-28). To enable a feature on a pool use the \fBzpool\fR(1M) command to set
-the \fBfeature@\fR\fIfeature_name\fR property to \fBenabled\fR.
+28). To enable a feature on a pool use the \fBupgrade\fR subcommand of the
+\fBzpool\fR(1M) command, or set the \fBfeature@\fR\fIfeature_name\fR property
+to \fBenabled\fR.
.sp
.LP
The pool format does not affect file system version compatibility or the ability
--- a/usr/src/man/man7d/atge.7d Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/man/man7d/atge.7d Sun Aug 12 11:56:48 2012 +0100
@@ -1,4 +1,5 @@
'\" te
+.\" Copyright (c) 2012 Gary Mills
.\" Copyright (c) 2009, Sun Microsystems, Inc. All Rights Reserved
.\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing.
.\" See the License for the specific language governing permissions and limitations under the License. When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the
@@ -9,12 +10,20 @@
.SH DESCRIPTION
.sp
.LP
-The \fBatge\fR ethernet driver is GLD based supporting the Atheros/Attansic L1E
-Gigabit Ethernet 10/100/1000 Base (AR8121/AR8113) chipsets:
+The \fBatge\fR ethernet driver supports the
+Atheros/Attansic L1, L1E, and L1C Ethernet
+(AR8121/AR8113/8114, AR8131/AR8132, and AR8151/AR8152) chipsets:
.sp
.in +2
.nf
-pciex1969,1026 Atheros/Attansic GigabitE 10/100/1000 Base (AR8121/AR8113)
+pciex1969,1026 Atheros AR8121/8113/8114
+pciex1969,1048 Attansic L1
+pciex1969,1062 Atheros AR8132 Fast Ethernet
+pciex1969,1063 Atheros AR8131 Gigabit Ethernet
+pciex1969,1073 Atheros AR8151 v1.0 Gigabit Ethernet
+pciex1969,1083 Atheros AR8151 v2.0 Gigabit Ethernet
+pciex1969,2060 Atheros AR8152 v1.1 Fast Ethernet
+pciex1969,2062 Atheros AR8152 v2.0 Fast Ethernet
.fi
.in -2
.sp
--- a/usr/src/man/man7d/ixgbe.7d Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/man/man7d/ixgbe.7d Sun Aug 12 11:56:48 2012 +0100
@@ -1,5 +1,6 @@
'\" te
.\" Copyright (c) 2009, Sun Microsystems, Inc. All Rights Reserved
+.\" Copyright 2012, Nexenta Systems, Inc. All rights reserved.
.\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing.
.\" See the License for the specific language governing permissions and limitations under the License. When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with
.\" the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner]
@@ -95,7 +96,7 @@
.sp
.LP
By default, the \fBixgbe\fR driver performs auto-negotiation to select the link
-speed and mode. Link speed and mode can only be 10000 Mbps full-duplex. See the
+speed and mode. Link speed and mode can only be 10000 Mbps full-duplex for fiber, and only 10000, 1000, or 100 Mbps full-duplex for copper. See the
\fIIEEE802.3\fR standard for more information.
.SH FILES
.sp
--- a/usr/src/pkg/manifests/driver-network-atge.mf Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/pkg/manifests/driver-network-atge.mf Sun Aug 12 11:56:48 2012 +0100
@@ -21,6 +21,7 @@
#
# Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2012 Gary Mills
#
#
@@ -43,7 +44,13 @@
dir path=usr/share/man/man7d
driver name=atge \
alias=pciex1969,1026 \
- alias=pciex1969,1048
+ alias=pciex1969,1048 \
+ alias=pciex1969,1062 \
+ alias=pciex1969,1063 \
+ alias=pciex1969,1073 \
+ alias=pciex1969,1083 \
+ alias=pciex1969,2060 \
+ alias=pciex1969,2062
file path=kernel/drv/$(ARCH64)/atge group=sys
file path=kernel/drv/atge group=sys
file path=usr/share/man/man7d/atge.7d
--- a/usr/src/pkg/manifests/driver-network-ixgbe.mf Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/pkg/manifests/driver-network-ixgbe.mf Sun Aug 12 11:56:48 2012 +0100
@@ -21,6 +21,8 @@
#
# Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2012, Joyent, Inc. All rights reserved.
+# Copyright 2012 Nexenta Systems, Inc. All rights reserved.
#
#
@@ -60,6 +62,7 @@
alias=pciex8086,1514 \
alias=pciex8086,1517 \
alias=pciex8086,151c \
+ alias=pciex8086,1528 \
alias=pciex8086,154d \
alias=pciex8086,1557
file path=kernel/drv/$(ARCH64)/ixgbe group=sys
--- a/usr/src/pkg/manifests/system-dtrace-tests.mf Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/pkg/manifests/system-dtrace-tests.mf Sun Aug 12 11:56:48 2012 +0100
@@ -21,7 +21,7 @@
#
# Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
-# Copyright (c) 2011 by Delphix. All rights reserved.
+# Copyright (c) 2012 by Delphix. All rights reserved.
#
set name=pkg.fmri value=pkg:/system/dtrace/tests@$(PKGVERS)
@@ -52,6 +52,7 @@
dir path=opt/SUNWdtrt/tst/common/bitfields
dir path=opt/SUNWdtrt/tst/common/buffering
dir path=opt/SUNWdtrt/tst/common/builtinvar
+dir path=opt/SUNWdtrt/tst/common/cg
dir path=opt/SUNWdtrt/tst/common/clauses
dir path=opt/SUNWdtrt/tst/common/cpc
dir path=opt/SUNWdtrt/tst/common/decls
@@ -59,6 +60,7 @@
dir path=opt/SUNWdtrt/tst/common/dtraceUtil
dir path=opt/SUNWdtrt/tst/common/end
dir path=opt/SUNWdtrt/tst/common/enum
+dir path=opt/SUNWdtrt/tst/common/env
dir path=opt/SUNWdtrt/tst/common/error
dir path=opt/SUNWdtrt/tst/common/exit
dir path=opt/SUNWdtrt/tst/common/fbtprovider
@@ -333,6 +335,8 @@
file path=opt/SUNWdtrt/tst/common/aggs/tst.signedkeys.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/aggs/tst.signedkeyspos.d mode=0444
file path=opt/SUNWdtrt/tst/common/aggs/tst.signedkeyspos.d.out mode=0444
+file path=opt/SUNWdtrt/tst/common/aggs/tst.sizedkeys.d mode=0444
+file path=opt/SUNWdtrt/tst/common/aggs/tst.sizedkeys.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/aggs/tst.stddev.d mode=0444
file path=opt/SUNWdtrt/tst/common/aggs/tst.stddev.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/aggs/tst.subr.d mode=0444
@@ -357,7 +361,14 @@
file path=opt/SUNWdtrt/tst/common/arithmetic/err.D_SYNTAX.muladd.d mode=0444
file path=opt/SUNWdtrt/tst/common/arithmetic/err.D_SYNTAX.muldiv.d mode=0444
file path=opt/SUNWdtrt/tst/common/arithmetic/tst.basics.d mode=0444
-file path=opt/SUNWdtrt/tst/common/arithmetic/tst.complex.d mode=0444
+file path=opt/SUNWdtrt/tst/common/arithmetic/tst.basics.d.out mode=0444
+file path=opt/SUNWdtrt/tst/common/arithmetic/tst.compcast.d mode=0444
+file path=opt/SUNWdtrt/tst/common/arithmetic/tst.compcast.d.out mode=0444
+file path=opt/SUNWdtrt/tst/common/arithmetic/tst.compnarrowassign.d mode=0444
+file path=opt/SUNWdtrt/tst/common/arithmetic/tst.compnarrowassign.d.out \
+ mode=0444
+file path=opt/SUNWdtrt/tst/common/arithmetic/tst.execcast.d mode=0444
+file path=opt/SUNWdtrt/tst/common/arithmetic/tst.execcast.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/arrays/err.D_ARR_BADREF.bad.d mode=0444
file path=opt/SUNWdtrt/tst/common/arrays/err.D_DECL_ARRBIG.toobig.d mode=0444
file path=opt/SUNWdtrt/tst/common/arrays/err.D_DECL_ARRNULL.bad.d mode=0444
@@ -474,6 +485,8 @@
file path=opt/SUNWdtrt/tst/common/builtinvar/tst.tid1.d mode=0444
file path=opt/SUNWdtrt/tst/common/builtinvar/tst.timestamp.d mode=0444
file path=opt/SUNWdtrt/tst/common/builtinvar/tst.vtimestamp.d mode=0444
+file path=opt/SUNWdtrt/tst/common/cg/err.D_NOREG.noreg.d mode=0444
+file path=opt/SUNWdtrt/tst/common/cg/err.baddif.d mode=0444
file path=opt/SUNWdtrt/tst/common/clauses/err.D_IDENT_UNDEF.aggfun.d mode=0444
file path=opt/SUNWdtrt/tst/common/clauses/err.D_IDENT_UNDEF.aggtup.d mode=0444
file path=opt/SUNWdtrt/tst/common/clauses/err.D_IDENT_UNDEF.arrtup.d mode=0444
@@ -720,6 +733,20 @@
file path=opt/SUNWdtrt/tst/common/enum/tst.EnumEquality.d mode=0444
file path=opt/SUNWdtrt/tst/common/enum/tst.EnumSameValue.d mode=0444
file path=opt/SUNWdtrt/tst/common/enum/tst.EnumValAssign.d mode=0444
+file path=opt/SUNWdtrt/tst/common/env/err.D_PRAGMA_OPTSET.setfromscript.d \
+ mode=0444
+file path=opt/SUNWdtrt/tst/common/env/err.D_PRAGMA_OPTSET.unsetfromscript.d \
+ mode=0444
+file path=opt/SUNWdtrt/tst/common/env/tst.ld_nolazyload.ksh mode=0444
+file path=opt/SUNWdtrt/tst/common/env/tst.ld_nolazyload.ksh.out mode=0444
+file path=opt/SUNWdtrt/tst/common/env/tst.setenv1.ksh mode=0444
+file path=opt/SUNWdtrt/tst/common/env/tst.setenv1.ksh.out mode=0444
+file path=opt/SUNWdtrt/tst/common/env/tst.setenv2.ksh mode=0444
+file path=opt/SUNWdtrt/tst/common/env/tst.setenv2.ksh.out mode=0444
+file path=opt/SUNWdtrt/tst/common/env/tst.unsetenv1.ksh mode=0444
+file path=opt/SUNWdtrt/tst/common/env/tst.unsetenv1.ksh.out mode=0444
+file path=opt/SUNWdtrt/tst/common/env/tst.unsetenv2.ksh mode=0444
+file path=opt/SUNWdtrt/tst/common/env/tst.unsetenv2.ksh.out mode=0444
file path=opt/SUNWdtrt/tst/common/error/tst.DTRACEFLT_BADADDR.d mode=0444
file path=opt/SUNWdtrt/tst/common/error/tst.DTRACEFLT_DIVZERO.d mode=0444
file path=opt/SUNWdtrt/tst/common/error/tst.DTRACEFLT_UNKNOWN.d mode=0444
@@ -1153,6 +1180,8 @@
file path=opt/SUNWdtrt/tst/common/pointers/tst.ValidPointer1.d mode=0444
file path=opt/SUNWdtrt/tst/common/pointers/tst.ValidPointer2.d mode=0444
file path=opt/SUNWdtrt/tst/common/pointers/tst.VoidCast.d mode=0444
+file path=opt/SUNWdtrt/tst/common/pointers/tst.assigncast1.d mode=0444
+file path=opt/SUNWdtrt/tst/common/pointers/tst.assigncast2.d mode=0444
file path=opt/SUNWdtrt/tst/common/pointers/tst.basic1.d mode=0444
file path=opt/SUNWdtrt/tst/common/pointers/tst.basic2.d mode=0444
file path=opt/SUNWdtrt/tst/common/pragma/err.D_PRAGERR.d mode=0444
@@ -1168,6 +1197,9 @@
file path=opt/SUNWdtrt/tst/common/pragma/tst.libdepfullyconnected.ksh \
mode=0444
file path=opt/SUNWdtrt/tst/common/pragma/tst.libdepsepdir.ksh mode=0444
+file path=opt/SUNWdtrt/tst/common/pragma/tst.temporal.ksh mode=0444
+file path=opt/SUNWdtrt/tst/common/pragma/tst.temporal2.ksh mode=0444
+file path=opt/SUNWdtrt/tst/common/pragma/tst.temporal3.d mode=0444
file path=opt/SUNWdtrt/tst/common/predicates/err.D_PRED_SCALAR.NonScalarPred.d \
mode=0444
file path=opt/SUNWdtrt/tst/common/predicates/err.D_SYNTAX.invalid.d mode=0444
@@ -1177,7 +1209,6 @@
file path=opt/SUNWdtrt/tst/common/predicates/tst.basics.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/predicates/tst.complex.d mode=0444
file path=opt/SUNWdtrt/tst/common/predicates/tst.complex.d.out mode=0444
-file path=opt/SUNWdtrt/tst/common/predicates/tst.predcache.ksh mode=0444
file path=opt/SUNWdtrt/tst/common/preprocessor/err.D_IDENT_UNDEF.afterprobe.d \
mode=0444
file path=opt/SUNWdtrt/tst/common/preprocessor/err.D_PRAGCTL_INVAL.tabdefine.d \
@@ -1222,17 +1253,19 @@
file path=opt/SUNWdtrt/tst/common/preprocessor/tst.preexpifelse.d.out \
mode=0444
file path=opt/SUNWdtrt/tst/common/preprocessor/tst.withinprobe.d mode=0444
-file path=opt/SUNWdtrt/tst/common/print/err.D_PRINT_DYN.bad.d mode=0444
file path=opt/SUNWdtrt/tst/common/print/err.D_PRINT_VOID.bad.d mode=0444
file path=opt/SUNWdtrt/tst/common/print/err.D_PROTO_LEN.bad.d mode=0444
file path=opt/SUNWdtrt/tst/common/print/tst.array.d mode=0444
file path=opt/SUNWdtrt/tst/common/print/tst.array.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/print/tst.bitfield.d mode=0444
file path=opt/SUNWdtrt/tst/common/print/tst.bitfield.d.out mode=0444
+file path=opt/SUNWdtrt/tst/common/print/tst.dyn.d mode=0444
file path=opt/SUNWdtrt/tst/common/print/tst.primitive.d mode=0444
file path=opt/SUNWdtrt/tst/common/print/tst.primitive.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/print/tst.struct.d mode=0444
file path=opt/SUNWdtrt/tst/common/print/tst.struct.d.out mode=0444
+file path=opt/SUNWdtrt/tst/common/print/tst.xlate.d mode=0444
+file path=opt/SUNWdtrt/tst/common/print/tst.xlate.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/printa/err.D_PRINTA_AGGARG.badagg.d \
mode=0444
file path=opt/SUNWdtrt/tst/common/printa/err.D_PRINTA_AGGARG.badfmt.d \
@@ -1313,6 +1346,8 @@
file path=opt/SUNWdtrt/tst/common/printf/tst.printgG.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/printf/tst.rawfmt.d mode=0444
file path=opt/SUNWdtrt/tst/common/printf/tst.rawfmt.d.out mode=0444
+file path=opt/SUNWdtrt/tst/common/printf/tst.signs.d mode=0444
+file path=opt/SUNWdtrt/tst/common/printf/tst.signs.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/printf/tst.str.d mode=0444
file path=opt/SUNWdtrt/tst/common/printf/tst.str.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/printf/tst.sym.d mode=0444
@@ -1766,8 +1801,8 @@
file path=opt/SUNWdtrt/tst/common/tick-n/tst.tickusec.d mode=0444
file path=opt/SUNWdtrt/tst/common/tick-n/tst.tickusec.d.out mode=0444
file path=opt/SUNWdtrt/tst/common/trace/err.D_PROTO_LEN.bad.d mode=0444
-file path=opt/SUNWdtrt/tst/common/trace/err.D_TRACE_DYN.bad.d mode=0444
file path=opt/SUNWdtrt/tst/common/trace/err.D_TRACE_VOID.bad.d mode=0444
+file path=opt/SUNWdtrt/tst/common/trace/tst.dyn.d mode=0444
file path=opt/SUNWdtrt/tst/common/trace/tst.misc.d mode=0444
file path=opt/SUNWdtrt/tst/common/trace/tst.qstring.d mode=0444
file path=opt/SUNWdtrt/tst/common/trace/tst.qstring.d.out mode=0444
@@ -1838,6 +1873,14 @@
mode=0444
file path=opt/SUNWdtrt/tst/common/translators/tst.StructureAssignment.d \
mode=0444
+file path=opt/SUNWdtrt/tst/common/translators/tst.TestTransStability1.ksh \
+ mode=0444
+file path=opt/SUNWdtrt/tst/common/translators/tst.TestTransStability1.ksh.out \
+ mode=0444
+file path=opt/SUNWdtrt/tst/common/translators/tst.TestTransStability2.ksh \
+ mode=0444
+file path=opt/SUNWdtrt/tst/common/translators/tst.TestTransStability2.ksh.out \
+ mode=0444
file path=opt/SUNWdtrt/tst/common/translators/tst.TransNonPointer.d mode=0444
file path=opt/SUNWdtrt/tst/common/translators/tst.TransOutputPointer.d \
mode=0444
--- a/usr/src/pkg/manifests/system-file-system-zfs.mf Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/pkg/manifests/system-file-system-zfs.mf Sun Aug 12 11:56:48 2012 +0100
@@ -85,10 +85,15 @@
file path=kernel/kmdb/$(ARCH64)/zfs group=sys mode=0555
$(i386_ONLY)file path=kernel/kmdb/zfs group=sys mode=0555
file path=lib/$(ARCH64)/libzfs.so.1
+file path=lib/$(ARCH64)/libzfs_core.so.1
file path=lib/$(ARCH64)/llib-lzfs.ln
+file path=lib/$(ARCH64)/llib-lzfs_core.ln
file path=lib/libzfs.so.1
+file path=lib/libzfs_core.so.1
file path=lib/llib-lzfs
file path=lib/llib-lzfs.ln
+file path=lib/llib-lzfs_core
+file path=lib/llib-lzfs_core.ln
file path=sbin/zfs mode=0555
file path=sbin/zpool mode=0555
file path=usr/lib/$(ARCH64)/libzfs_jni.so.1
@@ -146,23 +151,35 @@
link path=etc/fs/zfs/mount target=../../../sbin/zfs
link path=etc/fs/zfs/umount target=../../../sbin/zfs
link path=lib/$(ARCH64)/libzfs.so target=libzfs.so.1
+link path=lib/$(ARCH64)/libzfs_core.so target=libzfs_core.so.1
link path=lib/libzfs.so target=libzfs.so.1
+link path=lib/libzfs_core.so target=libzfs_core.so.1
link path=usr/lib/$(ARCH64)/libzfs.so \
target=../../../lib/$(ARCH64)/libzfs.so.1
link path=usr/lib/$(ARCH64)/libzfs.so.1 \
target=../../../lib/$(ARCH64)/libzfs.so.1
+link path=usr/lib/$(ARCH64)/libzfs_core.so \
+ target=../../../lib/$(ARCH64)/libzfs_core.so.1
+link path=usr/lib/$(ARCH64)/libzfs_core.so.1 \
+ target=../../../lib/$(ARCH64)/libzfs_core.so.1
link path=usr/lib/$(ARCH64)/libzfs_jni.so target=libzfs_jni.so.1
link path=usr/lib/$(ARCH64)/libzpool.so target=libzpool.so.1
link path=usr/lib/$(ARCH64)/llib-lzfs.ln \
target=../../../lib/$(ARCH64)/llib-lzfs.ln
+link path=usr/lib/$(ARCH64)/llib-lzfs_core.ln \
+ target=../../../lib/$(ARCH64)/llib-lzfs_core.ln
link path=usr/lib/fs/zfs/mount target=../../../../sbin/zfs
link path=usr/lib/fs/zfs/umount target=../../../../sbin/zfs
link path=usr/lib/libzfs.so target=../../lib/libzfs.so.1
link path=usr/lib/libzfs.so.1 target=../../lib/libzfs.so.1
+link path=usr/lib/libzfs_core.so target=../../lib/libzfs_core.so.1
+link path=usr/lib/libzfs_core.so.1 target=../../lib/libzfs_core.so.1
link path=usr/lib/libzfs_jni.so target=libzfs_jni.so.1
$(i386_ONLY)link path=usr/lib/libzpool.so target=libzpool.so.1
link path=usr/lib/llib-lzfs target=../../lib/llib-lzfs
link path=usr/lib/llib-lzfs.ln target=../../lib/llib-lzfs.ln
+link path=usr/lib/llib-lzfs_core target=../../lib/llib-lzfs_core
+link path=usr/lib/llib-lzfs_core.ln target=../../lib/llib-lzfs_core.ln
link path=usr/sbin/zfs target=../../sbin/zfs
link path=usr/sbin/zpool target=../../sbin/zpool
depend fmri=runtime/python-26 type=require
--- a/usr/src/pkg/manifests/system-header.mf Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/pkg/manifests/system-header.mf Sun Aug 12 11:56:48 2012 +0100
@@ -22,6 +22,7 @@
#
# Copyright 2011 Nexenta Systems, Inc. All rights reserved.
# Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2012 by Delphix. All rights reserved.
#
set name=pkg.fmri value=pkg:/system/header@$(PKGVERS)
@@ -505,6 +506,7 @@
$(sparc_ONLY)file path=usr/include/libv12n.h
file path=usr/include/libw.h
file path=usr/include/libzfs.h
+file path=usr/include/libzfs_core.h
file path=usr/include/libzoneinfo.h
file path=usr/include/limits.h
file path=usr/include/linenum.h
--- a/usr/src/tools/ctf/cvt/dwarf.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/tools/ctf/cvt/dwarf.c Sun Aug 12 11:56:48 2012 +0100
@@ -22,6 +22,10 @@
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
+/*
+ * Copyright 2012 Jason King. All rights reserved.
+ * Use is subject to license terms.
+ */
/*
* DWARF to tdata conversion
@@ -360,6 +364,37 @@
return (0);
}
+/*
+ * the following functions lookup the value of an attribute in a DIE:
+ *
+ * die_signed
+ * die_unsigned
+ * die_bool
+ * die_string
+ *
+ * They all take the same parameters (with the exception of valp which is
+ * a pointer to the type of the attribute we are looking up):
+ *
+ * dw - the dwarf object to look in
+ * die - the DIE we're interested in
+ * name - the name of the attribute to lookup
+ * valp - pointer to where the value of the attribute is placed
+ * req - if the value is required (0 / non-zero)
+ *
+ * If the attribute is not found, one of the following happens:
+ * - program terminates (req is non-zero)
+ * - function returns 0
+ *
+ * If the value is found, and in a form (class) we can handle, the function
+ * returns 1.
+ *
+ * Currently, we can only handle attribute values that are stored as
+ * constants (immediate value). If an attribute has a form we cannot
+ * handle (for example VLAs may store the dimensions of the array
+ * as a DWARF expression that can compute it at runtime by reading
+ * values off the stack or other locations in memory), it is treated
+ * the same as if the attribute does not exist.
+ */
static int
die_signed(dwarf_t *dw, Dwarf_Die die, Dwarf_Half name, Dwarf_Signed *valp,
int req)
@@ -371,6 +406,9 @@
return (0); /* die_attr will terminate for us if necessary */
if (dwarf_formsdata(attr, &val, &dw->dw_err) != DW_DLV_OK) {
+ if (req == 0)
+ return (0);
+
terminate("die %llu: failed to get signed (form 0x%x)\n",
die_off(dw, die), die_attr_form(dw, attr));
}
@@ -392,6 +430,9 @@
return (0); /* die_attr will terminate for us if necessary */
if (dwarf_formudata(attr, &val, &dw->dw_err) != DW_DLV_OK) {
+ if (req == 0)
+ return (0);
+
terminate("die %llu: failed to get unsigned (form 0x%x)\n",
die_off(dw, die), die_attr_form(dw, attr));
}
@@ -412,6 +453,9 @@
return (0); /* die_attr will terminate for us if necessary */
if (dwarf_formflag(attr, &val, &dw->dw_err) != DW_DLV_OK) {
+ if (req == 0)
+ return (0);
+
terminate("die %llu: failed to get bool (form 0x%x)\n",
die_off(dw, die), die_attr_form(dw, attr));
}
@@ -432,6 +476,9 @@
return (0); /* die_attr will terminate for us if necessary */
if (dwarf_formstring(attr, &str, &dw->dw_err) != DW_DLV_OK) {
+ if (req == 0)
+ return (0);
+
terminate("die %llu: failed to get string (form 0x%x)\n",
die_off(dw, die), die_attr_form(dw, attr));
}
@@ -1791,6 +1838,59 @@
} while (dw->dw_nunres != 0);
}
+/*
+ * Any object containing a function or object symbol at any scope should also
+ * contain DWARF data.
+ */
+static boolean_t
+should_have_dwarf(Elf *elf)
+{
+ Elf_Scn *scn = NULL;
+ Elf_Data *data = NULL;
+ GElf_Shdr shdr;
+ GElf_Sym sym;
+ uint32_t symdx = 0;
+ size_t nsyms = 0;
+ boolean_t found = B_FALSE;
+
+ while ((scn = elf_nextscn(elf, scn)) != NULL) {
+ gelf_getshdr(scn, &shdr);
+
+ if (shdr.sh_type == SHT_SYMTAB) {
+ found = B_TRUE;
+ break;
+ }
+ }
+
+ if (!found)
+ terminate("cannot convert stripped objects\n");
+
+ data = elf_getdata(scn, NULL);
+ nsyms = shdr.sh_size / shdr.sh_entsize;
+
+ for (symdx = 0; symdx < nsyms; symdx++) {
+ gelf_getsym(data, symdx, &sym);
+
+ if ((GELF_ST_TYPE(sym.st_info) == STT_FUNC) ||
+ (GELF_ST_TYPE(sym.st_info) == STT_TLS) ||
+ (GELF_ST_TYPE(sym.st_info) == STT_OBJECT)) {
+ char *name;
+
+ name = elf_strptr(elf, shdr.sh_link, sym.st_name);
+
+ /* Studio emits these local symbols regardless */
+ if ((strcmp(name, "Bbss.bss") != 0) &&
+ (strcmp(name, "Ttbss.bss") != 0) &&
+ (strcmp(name, "Ddata.data") != 0) &&
+ (strcmp(name, "Ttdata.data") != 0) &&
+ (strcmp(name, "Drodata.rodata") != 0))
+ return (B_TRUE);
+ }
+ }
+
+ return (B_FALSE);
+}
+
/*ARGSUSED*/
int
dw_read(tdata_t *td, Elf *elf, const char *filename)
@@ -1814,8 +1914,12 @@
if ((rc = dwarf_elf_init(elf, DW_DLC_READ, NULL, NULL, &dw.dw_dw,
&dw.dw_err)) == DW_DLV_NO_ENTRY) {
- errno = ENOENT;
- return (-1);
+ if (should_have_dwarf(elf)) {
+ errno = ENOENT;
+ return (-1);
+ } else {
+ return (0);
+ }
} else if (rc != DW_DLV_OK) {
if (dwarf_errno(dw.dw_err) == DW_DLE_DEBUG_INFO_NULL) {
/*
@@ -1834,10 +1938,18 @@
terminate("file does not contain valid DWARF data: %s\n",
dwarf_errmsg(dw.dw_err));
+ /*
+ * Some compilers emit no DWARF for empty files, others emit an empty
+ * compilation unit.
+ */
if ((cu = die_sibling(&dw, NULL)) == NULL ||
- (child = die_child(&dw, cu)) == NULL)
+ ((child = die_child(&dw, cu)) == NULL) &&
+ should_have_dwarf(elf)) {
terminate("file does not contain dwarf type data "
"(try compiling with -g)\n");
+ } else if (child == NULL) {
+ return (0);
+ }
dw.dw_maxoff = nxthdr - 1;
--- a/usr/src/tools/env/illumos.sh Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/tools/env/illumos.sh Sun Aug 12 11:56:48 2012 +0100
@@ -226,3 +226,6 @@
# POST_NIGHTLY can be any command to be run at the end of nightly. See
# nightly(1) for interactions between environment variables and this command.
#POST_NIGHTLY=
+
+# Uncomment this to disable support for SMB printing.
+# export ENABLE_SMB_PRINTING='#'
--- a/usr/src/tools/scripts/git-pbchk.py Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/tools/scripts/git-pbchk.py Sun Aug 12 11:56:48 2012 +0100
@@ -24,6 +24,7 @@
import re
import subprocess
import sys
+import tempfile
from cStringIO import StringIO
@@ -62,15 +63,24 @@
command = ["git"] + command
- p = subprocess.Popen(command,
- stdout=subprocess.PIPE,
- stderr=subprocess.STDOUT)
+ try:
+ tmpfile = tempfile.TemporaryFile(prefix="git-nits")
+ except EnvironmentError, e:
+ raise GitError("Could not create temporary file: %s\n" % e)
+
+ try:
+ p = subprocess.Popen(command,
+ stdout=tmpfile,
+ stderr=subprocess.STDOUT)
+ except OSError, e:
+ raise GitError("could not execute %s: %s\n" (command, e))
err = p.wait()
if err != 0:
raise GitError(p.stdout.read())
- return p.stdout
+ tmpfile.seek(0)
+ return tmpfile
def git_root():
--- a/usr/src/uts/common/Makefile.files Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/Makefile.files Sun Aug 12 11:56:48 2012 +0100
@@ -1846,7 +1846,7 @@
VR_OBJS += vr.o
-ATGE_OBJS += atge_main.o atge_l1e.o atge_mii.o atge_l1.o
+ATGE_OBJS += atge_main.o atge_l1e.o atge_mii.o atge_l1.o atge_l1c.o
YGE_OBJS = yge.o
@@ -1921,7 +1921,7 @@
ixgbe_buf.o ixgbe_debug.o ixgbe_gld.o \
ixgbe_log.o ixgbe_main.o \
ixgbe_osdep.o ixgbe_rx.o ixgbe_stat.o \
- ixgbe_tx.o
+ ixgbe_tx.o ixgbe_x540.o ixgbe_mbx.o
#
# NIU 10G/1G driver module
--- a/usr/src/uts/common/dtrace/dtrace.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/dtrace/dtrace.c Sun Aug 12 11:56:48 2012 +0100
@@ -22,6 +22,7 @@
/*
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2011, Joyent, Inc. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
/*
@@ -2401,9 +2402,10 @@
{
dtrace_speculation_t *spec;
dtrace_buffer_t *src, *dest;
- uintptr_t daddr, saddr, dlimit;
+ uintptr_t daddr, saddr, dlimit, slimit;
dtrace_speculation_state_t current, new;
intptr_t offs;
+ uint64_t timestamp;
if (which == 0)
return;
@@ -2479,7 +2481,37 @@
}
/*
- * We have the space; copy the buffer across. (Note that this is a
+ * We have sufficient space to copy the speculative buffer into the
+ * primary buffer. First, modify the speculative buffer, filling
+ * in the timestamp of all entries with the current time. The data
+ * must have the commit() time rather than the time it was traced,
+ * so that all entries in the primary buffer are in timestamp order.
+ */
+ timestamp = dtrace_gethrtime();
+ saddr = (uintptr_t)src->dtb_tomax;
+ slimit = saddr + src->dtb_offset;
+ while (saddr < slimit) {
+ size_t size;
+ dtrace_rechdr_t *dtrh = (dtrace_rechdr_t *)saddr;
+
+ if (dtrh->dtrh_epid == DTRACE_EPIDNONE) {
+ saddr += sizeof (dtrace_epid_t);
+ continue;
+ }
+ ASSERT3U(dtrh->dtrh_epid, <=, state->dts_necbs);
+ size = state->dts_ecbs[dtrh->dtrh_epid - 1]->dte_size;
+
+ ASSERT3U(saddr + size, <=, slimit);
+ ASSERT3U(size, >=, sizeof (dtrace_rechdr_t));
+ ASSERT3U(DTRACE_RECORD_LOAD_TIMESTAMP(dtrh), ==, UINT64_MAX);
+
+ DTRACE_RECORD_STORE_TIMESTAMP(dtrh, timestamp);
+
+ saddr += size;
+ }
+
+ /*
+ * Copy the buffer across. (Note that this is a
* highly subobtimal bcopy(); in the unlikely event that this becomes
* a serious performance issue, a high-performance DTrace-specific
* bcopy() should obviously be invented.)
@@ -5951,7 +5983,7 @@
if (now - state->dts_alive > dtrace_deadman_timeout) {
/*
* We seem to be dead. Unless we (a) have kernel
- * destructive permissions (b) have expicitly enabled
+ * destructive permissions (b) have explicitly enabled
* destructive actions and (c) destructive actions have
* not been disabled, we're going to transition into
* the KILLED state, from which no further processing
@@ -5979,8 +6011,18 @@
tomax = buf->dtb_tomax;
ASSERT(tomax != NULL);
- if (ecb->dte_size != 0)
- DTRACE_STORE(uint32_t, tomax, offs, ecb->dte_epid);
+ if (ecb->dte_size != 0) {
+ dtrace_rechdr_t dtrh;
+ if (!(mstate.dtms_present & DTRACE_MSTATE_TIMESTAMP)) {
+ mstate.dtms_timestamp = dtrace_gethrtime();
+ mstate.dtms_present |= DTRACE_MSTATE_TIMESTAMP;
+ }
+ ASSERT3U(ecb->dte_size, >=, sizeof (dtrace_rechdr_t));
+ dtrh.dtrh_epid = ecb->dte_epid;
+ DTRACE_RECORD_STORE_TIMESTAMP(&dtrh,
+ mstate.dtms_timestamp);
+ *((dtrace_rechdr_t *)(tomax + offs)) = dtrh;
+ }
mstate.dtms_epid = ecb->dte_epid;
mstate.dtms_present |= DTRACE_MSTATE_EPID;
@@ -6144,7 +6186,9 @@
continue;
switch (act->dta_kind) {
- case DTRACEACT_SPECULATE:
+ case DTRACEACT_SPECULATE: {
+ dtrace_rechdr_t *dtrh;
+
ASSERT(buf == &state->dts_buffer[cpuid]);
buf = dtrace_speculation_buffer(state,
cpuid, val);
@@ -6166,10 +6210,23 @@
tomax = buf->dtb_tomax;
ASSERT(tomax != NULL);
- if (ecb->dte_size != 0)
- DTRACE_STORE(uint32_t, tomax, offs,
- ecb->dte_epid);
+ if (ecb->dte_size == 0)
+ continue;
+
+ ASSERT3U(ecb->dte_size, >=,
+ sizeof (dtrace_rechdr_t));
+ dtrh = ((void *)(tomax + offs));
+ dtrh->dtrh_epid = ecb->dte_epid;
+ /*
+ * When the speculation is committed, all of
+ * the records in the speculative buffer will
+ * have their timestamps set to the commit
+ * time. Until then, it is set to a sentinel
+ * value, for debugability.
+ */
+ DTRACE_RECORD_STORE_TIMESTAMP(dtrh, UINT64_MAX);
continue;
+ }
case DTRACEACT_CHILL:
if (dtrace_priv_kernel_destructive(state))
@@ -9369,9 +9426,9 @@
/*
* The default size is the size of the default action: recording
- * the epid.
- */
- ecb->dte_size = ecb->dte_needed = sizeof (dtrace_epid_t);
+ * the header.
+ */
+ ecb->dte_size = ecb->dte_needed = sizeof (dtrace_rechdr_t);
ecb->dte_alignment = sizeof (dtrace_epid_t);
epid = state->dts_epid++;
@@ -9470,122 +9527,89 @@
static void
dtrace_ecb_resize(dtrace_ecb_t *ecb)
{
- uint32_t maxalign = sizeof (dtrace_epid_t);
- uint32_t align = sizeof (uint8_t), offs, diff;
dtrace_action_t *act;
- int wastuple = 0;
+ uint32_t curneeded = UINT32_MAX;
uint32_t aggbase = UINT32_MAX;
- dtrace_state_t *state = ecb->dte_state;
-
- /*
- * If we record anything, we always record the epid. (And we always
- * record it first.)
- */
- offs = sizeof (dtrace_epid_t);
- ecb->dte_size = ecb->dte_needed = sizeof (dtrace_epid_t);
+
+ /*
+ * If we record anything, we always record the dtrace_rechdr_t. (And
+ * we always record it first.)
+ */
+ ecb->dte_size = sizeof (dtrace_rechdr_t);
+ ecb->dte_alignment = sizeof (dtrace_epid_t);
for (act = ecb->dte_action; act != NULL; act = act->dta_next) {
dtrace_recdesc_t *rec = &act->dta_rec;
-
- if ((align = rec->dtrd_alignment) > maxalign)
- maxalign = align;
-
- if (!wastuple && act->dta_intuple) {
- /*
- * This is the first record in a tuple. Align the
- * offset to be at offset 4 in an 8-byte aligned
- * block.
- */
- diff = offs + sizeof (dtrace_aggid_t);
-
- if (diff = (diff & (sizeof (uint64_t) - 1)))
- offs += sizeof (uint64_t) - diff;
-
- aggbase = offs - sizeof (dtrace_aggid_t);
- ASSERT(!(aggbase & (sizeof (uint64_t) - 1)));
- }
-
- /*LINTED*/
- if (rec->dtrd_size != 0 && (diff = (offs & (align - 1)))) {
- /*
- * The current offset is not properly aligned; align it.
- */
- offs += align - diff;
- }
-
- rec->dtrd_offset = offs;
-
- if (offs + rec->dtrd_size > ecb->dte_needed) {
- ecb->dte_needed = offs + rec->dtrd_size;
-
- if (ecb->dte_needed > state->dts_needed)
- state->dts_needed = ecb->dte_needed;
- }
+ ASSERT(rec->dtrd_size > 0 || rec->dtrd_alignment == 1);
+
+ ecb->dte_alignment = MAX(ecb->dte_alignment,
+ rec->dtrd_alignment);
if (DTRACEACT_ISAGG(act->dta_kind)) {
dtrace_aggregation_t *agg = (dtrace_aggregation_t *)act;
- dtrace_action_t *first = agg->dtag_first, *prev;
-
- ASSERT(rec->dtrd_size != 0 && first != NULL);
- ASSERT(wastuple);
+
+ ASSERT(rec->dtrd_size != 0);
+ ASSERT(agg->dtag_first != NULL);
+ ASSERT(act->dta_prev->dta_intuple);
ASSERT(aggbase != UINT32_MAX);
+ ASSERT(curneeded != UINT32_MAX);
agg->dtag_base = aggbase;
- while ((prev = first->dta_prev) != NULL &&
- DTRACEACT_ISAGG(prev->dta_kind)) {
- agg = (dtrace_aggregation_t *)prev;
- first = agg->dtag_first;
- }
-
- if (prev != NULL) {
- offs = prev->dta_rec.dtrd_offset +
- prev->dta_rec.dtrd_size;
- } else {
- offs = sizeof (dtrace_epid_t);
- }
- wastuple = 0;
+ curneeded = P2ROUNDUP(curneeded, rec->dtrd_alignment);
+ rec->dtrd_offset = curneeded;
+ curneeded += rec->dtrd_size;
+ ecb->dte_needed = MAX(ecb->dte_needed, curneeded);
+
+ aggbase = UINT32_MAX;
+ curneeded = UINT32_MAX;
+ } else if (act->dta_intuple) {
+ if (curneeded == UINT32_MAX) {
+ /*
+ * This is the first record in a tuple. Align
+ * curneeded to be at offset 4 in an 8-byte
+ * aligned block.
+ */
+ ASSERT(act->dta_prev == NULL ||
+ !act->dta_prev->dta_intuple);
+ ASSERT3U(aggbase, ==, UINT32_MAX);
+ curneeded = P2PHASEUP(ecb->dte_size,
+ sizeof (uint64_t), sizeof (dtrace_aggid_t));
+
+ aggbase = curneeded - sizeof (dtrace_aggid_t);
+ ASSERT(IS_P2ALIGNED(aggbase,
+ sizeof (uint64_t)));
+ }
+ curneeded = P2ROUNDUP(curneeded, rec->dtrd_alignment);
+ rec->dtrd_offset = curneeded;
+ curneeded += rec->dtrd_size;
} else {
- if (!act->dta_intuple)
- ecb->dte_size = offs + rec->dtrd_size;
-
- offs += rec->dtrd_size;
- }
-
- wastuple = act->dta_intuple;
+ /* tuples must be followed by an aggregation */
+ ASSERT(act->dta_prev == NULL ||
+ !act->dta_prev->dta_intuple);
+
+ ecb->dte_size = P2ROUNDUP(ecb->dte_size,
+ rec->dtrd_alignment);
+ rec->dtrd_offset = ecb->dte_size;
+ ecb->dte_size += rec->dtrd_size;
+ ecb->dte_needed = MAX(ecb->dte_needed, ecb->dte_size);
+ }
}
if ((act = ecb->dte_action) != NULL &&
!(act->dta_kind == DTRACEACT_SPECULATE && act->dta_next == NULL) &&
- ecb->dte_size == sizeof (dtrace_epid_t)) {
- /*
- * If the size is still sizeof (dtrace_epid_t), then all
+ ecb->dte_size == sizeof (dtrace_rechdr_t)) {
+ /*
+ * If the size is still sizeof (dtrace_rechdr_t), then all
* actions store no data; set the size to 0.
*/
- ecb->dte_alignment = maxalign;
ecb->dte_size = 0;
-
- /*
- * If the needed space is still sizeof (dtrace_epid_t), then
- * all actions need no additional space; set the needed
- * size to 0.
- */
- if (ecb->dte_needed == sizeof (dtrace_epid_t))
- ecb->dte_needed = 0;
-
- return;
- }
-
- /*
- * Set our alignment, and make sure that the dte_size and dte_needed
- * are aligned to the size of an EPID.
- */
- ecb->dte_alignment = maxalign;
- ecb->dte_size = (ecb->dte_size + (sizeof (dtrace_epid_t) - 1)) &
- ~(sizeof (dtrace_epid_t) - 1);
- ecb->dte_needed = (ecb->dte_needed + (sizeof (dtrace_epid_t) - 1)) &
- ~(sizeof (dtrace_epid_t) - 1);
- ASSERT(ecb->dte_size <= ecb->dte_needed);
+ }
+
+ ecb->dte_size = P2ROUNDUP(ecb->dte_size, sizeof (dtrace_epid_t));
+ ecb->dte_needed = P2ROUNDUP(ecb->dte_needed, (sizeof (dtrace_epid_t)));
+ ecb->dte_state->dts_needed = MAX(ecb->dte_state->dts_needed,
+ ecb->dte_needed);
}
static dtrace_action_t *
@@ -9955,7 +9979,7 @@
break;
case DTRACEACT_SPECULATE:
- if (ecb->dte_size > sizeof (dtrace_epid_t))
+ if (ecb->dte_size > sizeof (dtrace_rechdr_t))
return (EINVAL);
if (dp == NULL)
@@ -10068,7 +10092,7 @@
ecb->dte_action = NULL;
ecb->dte_action_last = NULL;
- ecb->dte_size = sizeof (dtrace_epid_t);
+ ecb->dte_size = 0;
}
static void
@@ -10339,12 +10363,13 @@
caddr_t tomax = buf->dtb_tomax;
caddr_t xamot = buf->dtb_xamot;
dtrace_icookie_t cookie;
- hrtime_t now = dtrace_gethrtime();
+ hrtime_t now;
ASSERT(!(buf->dtb_flags & DTRACEBUF_NOSWITCH));
ASSERT(!(buf->dtb_flags & DTRACEBUF_RING));
cookie = dtrace_interrupt_disable();
+ now = dtrace_gethrtime();
buf->dtb_tomax = xamot;
buf->dtb_xamot = tomax;
buf->dtb_xamot_drops = buf->dtb_drops;
@@ -10639,7 +10664,7 @@
if (epid == DTRACE_EPIDNONE) {
size = sizeof (uint32_t);
} else {
- ASSERT(epid <= state->dts_necbs);
+ ASSERT3U(epid, <=, state->dts_necbs);
ASSERT(state->dts_ecbs[epid - 1] != NULL);
size = state->dts_ecbs[epid - 1]->dte_size;
@@ -15623,6 +15648,7 @@
desc.dtbd_drops = buf->dtb_drops;
desc.dtbd_errors = buf->dtb_errors;
desc.dtbd_oldest = buf->dtb_xamot_offset;
+ desc.dtbd_timestamp = dtrace_gethrtime();
mutex_exit(&dtrace_lock);
@@ -15675,6 +15701,7 @@
desc.dtbd_drops = buf->dtb_xamot_drops;
desc.dtbd_errors = buf->dtb_xamot_errors;
desc.dtbd_oldest = 0;
+ desc.dtbd_timestamp = buf->dtb_switched;
mutex_exit(&dtrace_lock);
--- a/usr/src/uts/common/fs/hsfs/hsfs_vfsops.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/hsfs/hsfs_vfsops.c Sun Aug 12 11:56:48 2012 +0100
@@ -1156,8 +1156,7 @@
* To avoid that we read the whole medium in case that someone prepares
* a malicious "fs image", we read at most 32 blocks.
*/
- for (n = 0; n < 32 &&
- (enum iso_voldesc_type) ISO_DESC_TYPE(volp) != ISO_VD_EOV; n++) {
+ for (n = 0; n < 32 && ISO_DESC_TYPE(volp) != ISO_VD_EOV; n++) {
for (i = 0; i < ISO_ID_STRLEN; i++)
if (ISO_STD_ID(volp)[i] != ISO_ID_STRING[i])
goto cantfind;
--- a/usr/src/uts/common/fs/nfs/nfs4_state.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/nfs/nfs4_state.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
#include <sys/systm.h>
@@ -2021,15 +2022,12 @@
return (&oo->ro_owner);
}
+/* ARGSUSED */
static bool_t
rfs4_openowner_expiry(rfs4_entry_t u_entry)
{
- rfs4_openowner_t *oo = (rfs4_openowner_t *)u_entry;
-
- if (rfs4_dbe_is_invalid(oo->ro_dbe))
- return (TRUE);
- return ((gethrestime_sec() - oo->ro_client->rc_last_access
- > rfs4_lease_time));
+ /* openstateid held us and did all needed delay */
+ return (TRUE);
}
static void
--- a/usr/src/uts/common/fs/smbsrv/smb_print.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/smbsrv/smb_print.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,7 +20,7 @@
*/
/*
* Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
/*
@@ -183,8 +183,12 @@
{
smb_sdrc_t rc;
- if (sr->sr_server->sv_cfg.skc_print_enable == 0 ||
- !STYPE_ISPRN(sr->tid_tree->t_res_type)) {
+ /*
+ * If sv_cfg.skc_print_enable somehow went false while
+ * we have a print FID open, close the FID. In this
+ * situation, smb_spool_add_fid() will do nothing.
+ */
+ if (!STYPE_ISPRN(sr->tid_tree->t_res_type)) {
smbsr_error(sr, NT_STATUS_BAD_DEVICE_TYPE,
ERRDOS, ERROR_BAD_DEV_TYPE);
cmn_err(CE_WARN, "smb_com_close_print_file: SDRC_ERROR");
@@ -192,8 +196,7 @@
}
rc = smb_com_close(sr);
- (void) smb_spool_add_fid(sr->smb_fid);
- cv_broadcast(&sr->sr_server->sp_info.sp_cv);
+ smb_spool_add_fid(sr->sr_server, sr->smb_fid);
return (rc);
}
--- a/usr/src/uts/common/fs/smbsrv/smb_server.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/smbsrv/smb_server.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,7 +20,7 @@
*/
/*
* Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
/*
@@ -2156,17 +2156,14 @@
*
*/
-int
-smb_spool_add_fid(uint16_t fid)
+void
+smb_spool_add_fid(smb_server_t *sv, uint16_t fid)
{
smb_llist_t *fidlist;
- smb_server_t *sv;
smb_spoolfid_t *sf;
- int rc = 0;
- rc = smb_server_lookup(&sv);
- if (rc)
- return (rc);
+ if (sv->sv_cfg.skc_print_enable == 0)
+ return;
sf = kmem_zalloc(sizeof (smb_spoolfid_t), KM_SLEEP);
fidlist = &sv->sp_info.sp_fidlist;
@@ -2174,8 +2171,7 @@
sf->sf_fid = fid;
smb_llist_insert_tail(fidlist, sf);
smb_llist_exit(fidlist);
- smb_server_release(sv);
- return (rc);
+ cv_broadcast(&sv->sp_info.sp_cv);
}
/*
--- a/usr/src/uts/common/fs/zfs/dmu_objset.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/dmu_objset.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
/* Portions Copyright 2010 Robert Milkowski */
@@ -699,30 +700,33 @@
spa_t *spa = dd->dd_pool->dp_spa;
struct oscarg *oa = arg2;
uint64_t obj;
+ dsl_dataset_t *ds;
+ blkptr_t *bp;
ASSERT(dmu_tx_is_syncing(tx));
obj = dsl_dataset_create_sync(dd, oa->lastname,
oa->clone_origin, oa->flags, oa->cr, tx);
- if (oa->clone_origin == NULL) {
- dsl_pool_t *dp = dd->dd_pool;
- dsl_dataset_t *ds;
- blkptr_t *bp;
- objset_t *os;
-
- VERIFY3U(0, ==, dsl_dataset_hold_obj(dp, obj, FTAG, &ds));
- bp = dsl_dataset_get_blkptr(ds);
- ASSERT(BP_IS_HOLE(bp));
-
- os = dmu_objset_create_impl(spa, ds, bp, oa->type, tx);
+ VERIFY3U(0, ==, dsl_dataset_hold_obj(dd->dd_pool, obj, FTAG, &ds));
+ bp = dsl_dataset_get_blkptr(ds);
+ if (BP_IS_HOLE(bp)) {
+ objset_t *os =
+ dmu_objset_create_impl(spa, ds, bp, oa->type, tx);
if (oa->userfunc)
oa->userfunc(os, oa->userarg, oa->cr, tx);
- dsl_dataset_rele(ds, FTAG);
}
- spa_history_log_internal(LOG_DS_CREATE, spa, tx, "dataset = %llu", obj);
+ if (oa->clone_origin == NULL) {
+ spa_history_log_internal_ds(ds, "create", tx, "");
+ } else {
+ char namebuf[MAXNAMELEN];
+ dsl_dataset_name(oa->clone_origin, namebuf);
+ spa_history_log_internal_ds(ds, "clone", tx,
+ "origin=%s (%llu)", namebuf, oa->clone_origin->ds_object);
+ }
+ dsl_dataset_rele(ds, FTAG);
}
int
@@ -799,34 +803,40 @@
return (error);
}
-struct snaparg {
- dsl_sync_task_group_t *dstg;
- char *snapname;
- char *htag;
- char failed[MAXPATHLEN];
- boolean_t recursive;
- boolean_t needsuspend;
- boolean_t temporary;
- nvlist_t *props;
- struct dsl_ds_holdarg *ha; /* only needed in the temporary case */
- dsl_dataset_t *newds;
-};
+typedef struct snapallarg {
+ dsl_sync_task_group_t *saa_dstg;
+ boolean_t saa_needsuspend;
+ nvlist_t *saa_props;
+
+ /* the following are used only if 'temporary' is set: */
+ boolean_t saa_temporary;
+ const char *saa_htag;
+ struct dsl_ds_holdarg *saa_ha;
+ dsl_dataset_t *saa_newds;
+} snapallarg_t;
+
+typedef struct snaponearg {
+ const char *soa_longname; /* long snap name */
+ const char *soa_snapname; /* short snap name */
+ snapallarg_t *soa_saa;
+} snaponearg_t;
static int
snapshot_check(void *arg1, void *arg2, dmu_tx_t *tx)
{
objset_t *os = arg1;
- struct snaparg *sn = arg2;
+ snaponearg_t *soa = arg2;
+ snapallarg_t *saa = soa->soa_saa;
int error;
/* The props have already been checked by zfs_check_userprops(). */
error = dsl_dataset_snapshot_check(os->os_dsl_dataset,
- sn->snapname, tx);
+ soa->soa_snapname, tx);
if (error)
return (error);
- if (sn->temporary) {
+ if (saa->saa_temporary) {
/*
* Ideally we would just call
* dsl_dataset_user_hold_check() and
@@ -844,12 +854,13 @@
* Not checking number of tags because the tag will be
* unique, as it will be the only tag.
*/
- if (strlen(sn->htag) + MAX_TAG_PREFIX_LEN >= MAXNAMELEN)
+ if (strlen(saa->saa_htag) + MAX_TAG_PREFIX_LEN >= MAXNAMELEN)
return (E2BIG);
- sn->ha = kmem_alloc(sizeof (struct dsl_ds_holdarg), KM_SLEEP);
- sn->ha->temphold = B_TRUE;
- sn->ha->htag = sn->htag;
+ saa->saa_ha = kmem_alloc(sizeof (struct dsl_ds_holdarg),
+ KM_SLEEP);
+ saa->saa_ha->temphold = B_TRUE;
+ saa->saa_ha->htag = saa->saa_htag;
}
return (error);
}
@@ -859,24 +870,25 @@
{
objset_t *os = arg1;
dsl_dataset_t *ds = os->os_dsl_dataset;
- struct snaparg *sn = arg2;
-
- dsl_dataset_snapshot_sync(ds, sn->snapname, tx);
+ snaponearg_t *soa = arg2;
+ snapallarg_t *saa = soa->soa_saa;
- if (sn->props) {
+ dsl_dataset_snapshot_sync(ds, soa->soa_snapname, tx);
+
+ if (saa->saa_props != NULL) {
dsl_props_arg_t pa;
- pa.pa_props = sn->props;
+ pa.pa_props = saa->saa_props;
pa.pa_source = ZPROP_SRC_LOCAL;
dsl_props_set_sync(ds->ds_prev, &pa, tx);
}
- if (sn->temporary) {
+ if (saa->saa_temporary) {
struct dsl_ds_destroyarg da;
- dsl_dataset_user_hold_sync(ds->ds_prev, sn->ha, tx);
- kmem_free(sn->ha, sizeof (struct dsl_ds_holdarg));
- sn->ha = NULL;
- sn->newds = ds->ds_prev;
+ dsl_dataset_user_hold_sync(ds->ds_prev, saa->saa_ha, tx);
+ kmem_free(saa->saa_ha, sizeof (struct dsl_ds_holdarg));
+ saa->saa_ha = NULL;
+ saa->saa_newds = ds->ds_prev;
da.ds = ds->ds_prev;
da.defer = B_TRUE;
@@ -885,131 +897,180 @@
}
static int
-dmu_objset_snapshot_one(const char *name, void *arg)
+snapshot_one_impl(const char *snapname, void *arg)
{
- struct snaparg *sn = arg;
+ char fsname[MAXPATHLEN];
+ snapallarg_t *saa = arg;
+ snaponearg_t *soa;
objset_t *os;
int err;
- char *cp;
-
- /*
- * If the objset starts with a '%', then ignore it unless it was
- * explicitly named (ie, not recursive). These hidden datasets
- * are always inconsistent, and by not opening them here, we can
- * avoid a race with dsl_dir_destroy_check().
- */
- cp = strrchr(name, '/');
- if (cp && cp[1] == '%' && sn->recursive)
- return (0);
- (void) strcpy(sn->failed, name);
+ (void) strlcpy(fsname, snapname, sizeof (fsname));
+ strchr(fsname, '@')[0] = '\0';
- /*
- * Check permissions if we are doing a recursive snapshot. The
- * permission checks for the starting dataset have already been
- * performed in zfs_secpolicy_snapshot()
- */
- if (sn->recursive && (err = zfs_secpolicy_snapshot_perms(name, CRED())))
- return (err);
-
- err = dmu_objset_hold(name, sn, &os);
+ err = dmu_objset_hold(fsname, saa, &os);
if (err != 0)
return (err);
/*
* If the objset is in an inconsistent state (eg, in the process
- * of being destroyed), don't snapshot it. As with %hidden
- * datasets, we return EBUSY if this name was explicitly
- * requested (ie, not recursive), and otherwise ignore it.
+ * of being destroyed), don't snapshot it.
*/
if (os->os_dsl_dataset->ds_phys->ds_flags & DS_FLAG_INCONSISTENT) {
- dmu_objset_rele(os, sn);
- return (sn->recursive ? 0 : EBUSY);
+ dmu_objset_rele(os, saa);
+ return (EBUSY);
}
- if (sn->needsuspend) {
+ if (saa->saa_needsuspend) {
err = zil_suspend(dmu_objset_zil(os));
if (err) {
- dmu_objset_rele(os, sn);
+ dmu_objset_rele(os, saa);
return (err);
}
}
- dsl_sync_task_create(sn->dstg, snapshot_check, snapshot_sync,
- os, sn, 3);
+
+ soa = kmem_zalloc(sizeof (*soa), KM_SLEEP);
+ soa->soa_saa = saa;
+ soa->soa_longname = snapname;
+ soa->soa_snapname = strchr(snapname, '@') + 1;
+
+ dsl_sync_task_create(saa->saa_dstg, snapshot_check, snapshot_sync,
+ os, soa, 3);
return (0);
}
+/*
+ * The snapshots must all be in the same pool.
+ */
int
-dmu_objset_snapshot(char *fsname, char *snapname, char *tag,
- nvlist_t *props, boolean_t recursive, boolean_t temporary, int cleanup_fd)
+dmu_objset_snapshot(nvlist_t *snaps, nvlist_t *props, nvlist_t *errors)
{
dsl_sync_task_t *dst;
- struct snaparg sn;
+ snapallarg_t saa = { 0 };
+ spa_t *spa;
+ int rv = 0;
+ int err;
+ nvpair_t *pair;
+
+ pair = nvlist_next_nvpair(snaps, NULL);
+ if (pair == NULL)
+ return (0);
+
+ err = spa_open(nvpair_name(pair), &spa, FTAG);
+ if (err)
+ return (err);
+ saa.saa_dstg = dsl_sync_task_group_create(spa_get_dsl(spa));
+ saa.saa_props = props;
+ saa.saa_needsuspend = (spa_version(spa) < SPA_VERSION_FAST_SNAP);
+
+ for (pair = nvlist_next_nvpair(snaps, NULL); pair != NULL;
+ pair = nvlist_next_nvpair(snaps, pair)) {
+ err = snapshot_one_impl(nvpair_name(pair), &saa);
+ if (err != 0) {
+ if (errors != NULL) {
+ fnvlist_add_int32(errors,
+ nvpair_name(pair), err);
+ }
+ rv = err;
+ }
+ }
+
+ /*
+ * If any call to snapshot_one_impl() failed, don't execute the
+ * sync task. The error handling code below will clean up the
+ * snaponearg_t from any successful calls to
+ * snapshot_one_impl().
+ */
+ if (rv == 0)
+ err = dsl_sync_task_group_wait(saa.saa_dstg);
+ if (err != 0)
+ rv = err;
+
+ for (dst = list_head(&saa.saa_dstg->dstg_tasks); dst;
+ dst = list_next(&saa.saa_dstg->dstg_tasks, dst)) {
+ objset_t *os = dst->dst_arg1;
+ snaponearg_t *soa = dst->dst_arg2;
+ if (dst->dst_err != 0) {
+ if (errors != NULL) {
+ fnvlist_add_int32(errors,
+ soa->soa_longname, dst->dst_err);
+ }
+ rv = dst->dst_err;
+ }
+
+ if (saa.saa_needsuspend)
+ zil_resume(dmu_objset_zil(os));
+ dmu_objset_rele(os, &saa);
+ kmem_free(soa, sizeof (*soa));
+ }
+
+ dsl_sync_task_group_destroy(saa.saa_dstg);
+ spa_close(spa, FTAG);
+ return (rv);
+}
+
+int
+dmu_objset_snapshot_one(const char *fsname, const char *snapname)
+{
+ int err;
+ char *longsnap = kmem_asprintf("%s@%s", fsname, snapname);
+ nvlist_t *snaps = fnvlist_alloc();
+
+ fnvlist_add_boolean(snaps, longsnap);
+ err = dmu_objset_snapshot(snaps, NULL, NULL);
+ fnvlist_free(snaps);
+ strfree(longsnap);
+ return (err);
+}
+
+int
+dmu_objset_snapshot_tmp(const char *snapname, const char *tag, int cleanup_fd)
+{
+ dsl_sync_task_t *dst;
+ snapallarg_t saa = { 0 };
spa_t *spa;
minor_t minor;
int err;
- (void) strcpy(sn.failed, fsname);
-
- err = spa_open(fsname, &spa, FTAG);
+ err = spa_open(snapname, &spa, FTAG);
if (err)
return (err);
+ saa.saa_dstg = dsl_sync_task_group_create(spa_get_dsl(spa));
+ saa.saa_htag = tag;
+ saa.saa_needsuspend = (spa_version(spa) < SPA_VERSION_FAST_SNAP);
+ saa.saa_temporary = B_TRUE;
- if (temporary) {
- if (cleanup_fd < 0) {
- spa_close(spa, FTAG);
- return (EINVAL);
- }
- if ((err = zfs_onexit_fd_hold(cleanup_fd, &minor)) != 0) {
- spa_close(spa, FTAG);
- return (err);
- }
+ if (cleanup_fd < 0) {
+ spa_close(spa, FTAG);
+ return (EINVAL);
+ }
+ if ((err = zfs_onexit_fd_hold(cleanup_fd, &minor)) != 0) {
+ spa_close(spa, FTAG);
+ return (err);
}
- sn.dstg = dsl_sync_task_group_create(spa_get_dsl(spa));
- sn.snapname = snapname;
- sn.htag = tag;
- sn.props = props;
- sn.recursive = recursive;
- sn.needsuspend = (spa_version(spa) < SPA_VERSION_FAST_SNAP);
- sn.temporary = temporary;
- sn.ha = NULL;
- sn.newds = NULL;
-
- if (recursive) {
- err = dmu_objset_find(fsname,
- dmu_objset_snapshot_one, &sn, DS_FIND_CHILDREN);
- } else {
- err = dmu_objset_snapshot_one(fsname, &sn);
- }
+ err = snapshot_one_impl(snapname, &saa);
if (err == 0)
- err = dsl_sync_task_group_wait(sn.dstg);
+ err = dsl_sync_task_group_wait(saa.saa_dstg);
- for (dst = list_head(&sn.dstg->dstg_tasks); dst;
- dst = list_next(&sn.dstg->dstg_tasks, dst)) {
+ for (dst = list_head(&saa.saa_dstg->dstg_tasks); dst;
+ dst = list_next(&saa.saa_dstg->dstg_tasks, dst)) {
objset_t *os = dst->dst_arg1;
- dsl_dataset_t *ds = os->os_dsl_dataset;
- if (dst->dst_err) {
- dsl_dataset_name(ds, sn.failed);
- } else if (temporary) {
- dsl_register_onexit_hold_cleanup(sn.newds, tag, minor);
- }
- if (sn.needsuspend)
+ dsl_register_onexit_hold_cleanup(saa.saa_newds, tag, minor);
+ if (saa.saa_needsuspend)
zil_resume(dmu_objset_zil(os));
- dmu_objset_rele(os, &sn);
+ dmu_objset_rele(os, &saa);
}
- if (err)
- (void) strcpy(fsname, sn.failed);
- if (temporary)
- zfs_onexit_fd_rele(cleanup_fd);
- dsl_sync_task_group_destroy(sn.dstg);
+ zfs_onexit_fd_rele(cleanup_fd);
+ dsl_sync_task_group_destroy(saa.saa_dstg);
spa_close(spa, FTAG);
return (err);
}
+
static void
dmu_objset_sync_dnodes(list_t *list, list_t *newlist, dmu_tx_t *tx)
{
--- a/usr/src/uts/common/fs/zfs/dmu_send.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/dmu_send.c Sun Aug 12 11:56:48 2012 +0100
@@ -387,9 +387,48 @@
return (err);
}
+/*
+ * Return TRUE if 'earlier' is an earlier snapshot in 'later's timeline.
+ * For example, they could both be snapshots of the same filesystem, and
+ * 'earlier' is before 'later'. Or 'earlier' could be the origin of
+ * 'later's filesystem. Or 'earlier' could be an older snapshot in the origin's
+ * filesystem. Or 'earlier' could be the origin's origin.
+ */
+static boolean_t
+is_before(dsl_dataset_t *later, dsl_dataset_t *earlier)
+{
+ dsl_pool_t *dp = later->ds_dir->dd_pool;
+ int error;
+ boolean_t ret;
+ dsl_dataset_t *origin;
+
+ if (earlier->ds_phys->ds_creation_txg >=
+ later->ds_phys->ds_creation_txg)
+ return (B_FALSE);
+
+ if (later->ds_dir == earlier->ds_dir)
+ return (B_TRUE);
+ if (!dsl_dir_is_clone(later->ds_dir))
+ return (B_FALSE);
+
+ rw_enter(&dp->dp_config_rwlock, RW_READER);
+ if (later->ds_dir->dd_phys->dd_origin_obj == earlier->ds_object) {
+ rw_exit(&dp->dp_config_rwlock);
+ return (B_TRUE);
+ }
+ error = dsl_dataset_hold_obj(dp,
+ later->ds_dir->dd_phys->dd_origin_obj, FTAG, &origin);
+ rw_exit(&dp->dp_config_rwlock);
+ if (error != 0)
+ return (B_FALSE);
+ ret = is_before(origin, earlier);
+ dsl_dataset_rele(origin, FTAG);
+ return (ret);
+}
+
int
-dmu_send(objset_t *tosnap, objset_t *fromsnap, boolean_t fromorigin,
- int outfd, vnode_t *vp, offset_t *off)
+dmu_send(objset_t *tosnap, objset_t *fromsnap, int outfd, vnode_t *vp,
+ offset_t *off)
{
dsl_dataset_t *ds = tosnap->os_dsl_dataset;
dsl_dataset_t *fromds = fromsnap ? fromsnap->os_dsl_dataset : NULL;
@@ -402,30 +441,13 @@
if (ds->ds_phys->ds_next_snap_obj == 0)
return (EINVAL);
- /* fromsnap must be an earlier snapshot from the same fs as tosnap */
- if (fromds && (ds->ds_dir != fromds->ds_dir ||
- fromds->ds_phys->ds_creation_txg >= ds->ds_phys->ds_creation_txg))
+ /*
+ * fromsnap must be an earlier snapshot from the same fs as tosnap,
+ * or the origin's fs.
+ */
+ if (fromds != NULL && !is_before(ds, fromds))
return (EXDEV);
- if (fromorigin) {
- dsl_pool_t *dp = ds->ds_dir->dd_pool;
-
- if (fromsnap)
- return (EINVAL);
-
- if (dsl_dir_is_clone(ds->ds_dir)) {
- rw_enter(&dp->dp_config_rwlock, RW_READER);
- err = dsl_dataset_hold_obj(dp,
- ds->ds_dir->dd_phys->dd_origin_obj, FTAG, &fromds);
- rw_exit(&dp->dp_config_rwlock);
- if (err)
- return (err);
- } else {
- fromorigin = B_FALSE;
- }
- }
-
-
drr = kmem_zalloc(sizeof (dmu_replay_record_t), KM_SLEEP);
drr->drr_type = DRR_BEGIN;
drr->drr_u.drr_begin.drr_magic = DMU_BACKUP_MAGIC;
@@ -450,7 +472,7 @@
drr->drr_u.drr_begin.drr_creation_time =
ds->ds_phys->ds_creation_time;
drr->drr_u.drr_begin.drr_type = tosnap->os_phys->os_type;
- if (fromorigin)
+ if (fromds != NULL && ds->ds_dir != fromds->ds_dir)
drr->drr_u.drr_begin.drr_flags |= DRR_FLAG_CLONE;
drr->drr_u.drr_begin.drr_toguid = ds->ds_phys->ds_guid;
if (ds->ds_phys->ds_flags & DS_FLAG_CI_DATASET)
@@ -462,8 +484,6 @@
if (fromds)
fromtxg = fromds->ds_phys->ds_creation_txg;
- if (fromorigin)
- dsl_dataset_rele(fromds, FTAG);
dsp = kmem_zalloc(sizeof (dmu_sendarg_t), KM_SLEEP);
@@ -521,8 +541,7 @@
}
int
-dmu_send_estimate(objset_t *tosnap, objset_t *fromsnap, boolean_t fromorigin,
- uint64_t *sizep)
+dmu_send_estimate(objset_t *tosnap, objset_t *fromsnap, uint64_t *sizep)
{
dsl_dataset_t *ds = tosnap->os_dsl_dataset;
dsl_dataset_t *fromds = fromsnap ? fromsnap->os_dsl_dataset : NULL;
@@ -534,27 +553,13 @@
if (ds->ds_phys->ds_next_snap_obj == 0)
return (EINVAL);
- /* fromsnap must be an earlier snapshot from the same fs as tosnap */
- if (fromds && (ds->ds_dir != fromds->ds_dir ||
- fromds->ds_phys->ds_creation_txg >= ds->ds_phys->ds_creation_txg))
+ /*
+ * fromsnap must be an earlier snapshot from the same fs as tosnap,
+ * or the origin's fs.
+ */
+ if (fromds != NULL && !is_before(ds, fromds))
return (EXDEV);
- if (fromorigin) {
- if (fromsnap)
- return (EINVAL);
-
- if (dsl_dir_is_clone(ds->ds_dir)) {
- rw_enter(&dp->dp_config_rwlock, RW_READER);
- err = dsl_dataset_hold_obj(dp,
- ds->ds_dir->dd_phys->dd_origin_obj, FTAG, &fromds);
- rw_exit(&dp->dp_config_rwlock);
- if (err)
- return (err);
- } else {
- fromorigin = B_FALSE;
- }
- }
-
/* Get uncompressed size estimate of changed data. */
if (fromds == NULL) {
size = ds->ds_phys->ds_uncompressed_bytes;
@@ -562,8 +567,6 @@
uint64_t used, comp;
err = dsl_dataset_space_written(fromds, ds,
&used, &comp, &size);
- if (fromorigin)
- dsl_dataset_rele(fromds, FTAG);
if (err)
return (err);
}
@@ -662,8 +665,7 @@
rbsa->ds, &rbsa->ds->ds_phys->ds_bp, rbsa->type, tx);
}
- spa_history_log_internal(LOG_DS_REPLAY_FULL_SYNC,
- dd->dd_pool->dp_spa, tx, "dataset = %lld", dsobj);
+ spa_history_log_internal_ds(rbsa->ds, "receive new", tx, "");
}
/* ARGSUSED */
@@ -764,8 +766,7 @@
rbsa->ds = cds;
- spa_history_log_internal(LOG_DS_REPLAY_INC_SYNC,
- dp->dp_spa, tx, "dataset = %lld", dsobj);
+ spa_history_log_internal_ds(cds, "receive over existing", tx, "");
}
static boolean_t
@@ -1573,6 +1574,7 @@
dmu_buf_will_dirty(ds->ds_dbuf, tx);
ds->ds_phys->ds_flags &= ~DS_FLAG_INCONSISTENT;
+ spa_history_log_internal_ds(ds, "finished receiving", tx, "");
}
static int
--- a/usr/src/uts/common/fs/zfs/dmu_tx.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/dmu_tx.c Sun Aug 12 11:56:48 2012 +0100
@@ -48,7 +48,7 @@
{
dmu_tx_t *tx = kmem_zalloc(sizeof (dmu_tx_t), KM_SLEEP);
tx->tx_dir = dd;
- if (dd)
+ if (dd != NULL)
tx->tx_pool = dd->dd_pool;
list_create(&tx->tx_holds, sizeof (dmu_tx_hold_t),
offsetof(dmu_tx_hold_t, txh_node));
--- a/usr/src/uts/common/fs/zfs/dsl_dataset.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/dsl_dataset.c Sun Aug 12 11:56:48 2012 +0100
@@ -914,7 +914,8 @@
* The snapshots must all be in the same pool.
*/
int
-dmu_snapshots_destroy_nvl(nvlist_t *snaps, boolean_t defer, char *failed)
+dmu_snapshots_destroy_nvl(nvlist_t *snaps, boolean_t defer,
+ nvlist_t *errlist)
{
int err;
dsl_sync_task_t *dst;
@@ -949,7 +950,7 @@
} else if (err == ENOENT) {
err = 0;
} else {
- (void) strcpy(failed, nvpair_name(pair));
+ fnvlist_add_int32(errlist, nvpair_name(pair), err);
break;
}
}
@@ -963,10 +964,12 @@
dsl_dataset_t *ds = dsda->ds;
/*
- * Return the file system name that triggered the error
+ * Return the snapshots that triggered the error.
*/
- if (dst->dst_err) {
- dsl_dataset_name(ds, failed);
+ if (dst->dst_err != 0) {
+ char name[ZFS_MAXNAMELEN];
+ dsl_dataset_name(ds, name);
+ fnvlist_add_int32(errlist, name, dst->dst_err);
}
ASSERT3P(dsda->rm_origin, ==, NULL);
dsl_dataset_disown(ds, dstg);
@@ -1045,7 +1048,6 @@
dsl_dir_t *dd;
uint64_t obj;
struct dsl_ds_destroyarg dsda = { 0 };
- dsl_dataset_t dummy_ds = { 0 };
dsda.ds = ds;
@@ -1065,8 +1067,6 @@
}
dd = ds->ds_dir;
- dummy_ds.ds_dir = dd;
- dummy_ds.ds_object = ds->ds_object;
/*
* Check for errors and mark this ds as inconsistent, in
@@ -1153,7 +1153,7 @@
dsl_sync_task_create(dstg, dsl_dataset_destroy_check,
dsl_dataset_destroy_sync, &dsda, tag, 0);
dsl_sync_task_create(dstg, dsl_dir_destroy_check,
- dsl_dir_destroy_sync, &dummy_ds, FTAG, 0);
+ dsl_dir_destroy_sync, dd, FTAG, 0);
err = dsl_sync_task_group_wait(dstg);
dsl_sync_task_group_destroy(dstg);
@@ -1328,14 +1328,12 @@
dsl_dataset_destroy_begin_sync(void *arg1, void *arg2, dmu_tx_t *tx)
{
dsl_dataset_t *ds = arg1;
- dsl_pool_t *dp = ds->ds_dir->dd_pool;
/* Mark it as inconsistent on-disk, in case we crash */
dmu_buf_will_dirty(ds->ds_dbuf, tx);
ds->ds_phys->ds_flags |= DS_FLAG_INCONSISTENT;
- spa_history_log_internal(LOG_DS_DESTROY_BEGIN, dp->dp_spa, tx,
- "dataset = %llu", ds->ds_object);
+ spa_history_log_internal_ds(ds, "destroy begin", tx, "");
}
static int
@@ -1660,9 +1658,13 @@
ASSERT(spa_version(dp->dp_spa) >= SPA_VERSION_USERREFS);
dmu_buf_will_dirty(ds->ds_dbuf, tx);
ds->ds_phys->ds_flags |= DS_FLAG_DEFER_DESTROY;
+ spa_history_log_internal_ds(ds, "defer_destroy", tx, "");
return;
}
+ /* We need to log before removing it from the namespace. */
+ spa_history_log_internal_ds(ds, "destroy", tx, "");
+
/* signal any waiters that this dataset is going away */
mutex_enter(&ds->ds_lock);
ds->ds_owner = dsl_reaper;
@@ -1957,8 +1959,6 @@
dsl_dataset_rele(ds_prev, FTAG);
spa_prop_clear_bootfs(dp->dp_spa, ds->ds_object, tx);
- spa_history_log_internal(LOG_DS_DESTROY, dp->dp_spa, tx,
- "dataset = %llu", ds->ds_object);
if (ds->ds_phys->ds_next_clones_obj != 0) {
uint64_t count;
@@ -2006,7 +2006,7 @@
return (ENOSPC);
/*
- * Propogate any reserved space for this snapshot to other
+ * Propagate any reserved space for this snapshot to other
* snapshot checks in this sync group.
*/
if (asize > 0)
@@ -2016,10 +2016,9 @@
}
int
-dsl_dataset_snapshot_check(void *arg1, void *arg2, dmu_tx_t *tx)
+dsl_dataset_snapshot_check(dsl_dataset_t *ds, const char *snapname,
+ dmu_tx_t *tx)
{
- dsl_dataset_t *ds = arg1;
- const char *snapname = arg2;
int err;
uint64_t value;
@@ -2031,7 +2030,7 @@
return (EAGAIN);
/*
- * Check for conflicting name snapshot name.
+ * Check for conflicting snapshot name.
*/
err = dsl_dataset_snap_lookup(ds, snapname, &value);
if (err == 0)
@@ -2055,10 +2054,9 @@
}
void
-dsl_dataset_snapshot_sync(void *arg1, void *arg2, dmu_tx_t *tx)
+dsl_dataset_snapshot_sync(dsl_dataset_t *ds, const char *snapname,
+ dmu_tx_t *tx)
{
- dsl_dataset_t *ds = arg1;
- const char *snapname = arg2;
dsl_pool_t *dp = ds->ds_dir->dd_pool;
dmu_buf_t *dbuf;
dsl_dataset_phys_t *dsphys;
@@ -2164,8 +2162,7 @@
dsl_dir_snap_cmtime_update(ds->ds_dir);
- spa_history_log_internal(LOG_DS_SNAPSHOT, dp->dp_spa, tx,
- "dataset = %llu", dsobj);
+ spa_history_log_internal_ds(ds->ds_prev, "snapshot", tx, "");
}
void
@@ -2252,7 +2249,20 @@
{
uint64_t refd, avail, uobjs, aobjs, ratio;
- dsl_dir_stats(ds->ds_dir, nv);
+ ratio = ds->ds_phys->ds_compressed_bytes == 0 ? 100 :
+ (ds->ds_phys->ds_uncompressed_bytes * 100 /
+ ds->ds_phys->ds_compressed_bytes);
+
+ dsl_prop_nvlist_add_uint64(nv, ZFS_PROP_REFRATIO, ratio);
+
+ if (dsl_dataset_is_snapshot(ds)) {
+ dsl_prop_nvlist_add_uint64(nv, ZFS_PROP_COMPRESSRATIO, ratio);
+ dsl_prop_nvlist_add_uint64(nv, ZFS_PROP_USED,
+ ds->ds_phys->ds_unique_bytes);
+ get_clones_stat(ds, nv);
+ } else {
+ dsl_dir_stats(ds->ds_dir, nv);
+ }
dsl_dataset_space(ds, &refd, &avail, &uobjs, &aobjs);
dsl_prop_nvlist_add_uint64(nv, ZFS_PROP_AVAILABLE, avail);
@@ -2297,22 +2307,6 @@
}
}
- ratio = ds->ds_phys->ds_compressed_bytes == 0 ? 100 :
- (ds->ds_phys->ds_uncompressed_bytes * 100 /
- ds->ds_phys->ds_compressed_bytes);
- dsl_prop_nvlist_add_uint64(nv, ZFS_PROP_REFRATIO, ratio);
-
- if (ds->ds_phys->ds_next_snap_obj) {
- /*
- * This is a snapshot; override the dd's space used with
- * our unique space and compression ratio.
- */
- dsl_prop_nvlist_add_uint64(nv, ZFS_PROP_USED,
- ds->ds_phys->ds_unique_bytes);
- dsl_prop_nvlist_add_uint64(nv, ZFS_PROP_COMPRESSRATIO, ratio);
-
- get_clones_stat(ds, nv);
- }
}
void
@@ -2321,27 +2315,25 @@
stat->dds_creation_txg = ds->ds_phys->ds_creation_txg;
stat->dds_inconsistent = ds->ds_phys->ds_flags & DS_FLAG_INCONSISTENT;
stat->dds_guid = ds->ds_phys->ds_guid;
- if (ds->ds_phys->ds_next_snap_obj) {
+ stat->dds_origin[0] = '\0';
+ if (dsl_dataset_is_snapshot(ds)) {
stat->dds_is_snapshot = B_TRUE;
stat->dds_num_clones = ds->ds_phys->ds_num_children - 1;
} else {
stat->dds_is_snapshot = B_FALSE;
stat->dds_num_clones = 0;
+
+ rw_enter(&ds->ds_dir->dd_pool->dp_config_rwlock, RW_READER);
+ if (dsl_dir_is_clone(ds->ds_dir)) {
+ dsl_dataset_t *ods;
+
+ VERIFY(0 == dsl_dataset_get_ref(ds->ds_dir->dd_pool,
+ ds->ds_dir->dd_phys->dd_origin_obj, FTAG, &ods));
+ dsl_dataset_name(ods, stat->dds_origin);
+ dsl_dataset_drop_ref(ods, FTAG);
+ }
+ rw_exit(&ds->ds_dir->dd_pool->dp_config_rwlock);
}
-
- /* clone origin is really a dsl_dir thing... */
- rw_enter(&ds->ds_dir->dd_pool->dp_config_rwlock, RW_READER);
- if (dsl_dir_is_clone(ds->ds_dir)) {
- dsl_dataset_t *ods;
-
- VERIFY(0 == dsl_dataset_get_ref(ds->ds_dir->dd_pool,
- ds->ds_dir->dd_phys->dd_origin_obj, FTAG, &ods));
- dsl_dataset_name(ods, stat->dds_origin);
- dsl_dataset_drop_ref(ods, FTAG);
- } else {
- stat->dds_origin[0] = '\0';
- }
- rw_exit(&ds->ds_dir->dd_pool->dp_config_rwlock);
}
uint64_t
@@ -2458,8 +2450,8 @@
ds->ds_snapname, 8, 1, &ds->ds_object, tx);
ASSERT3U(err, ==, 0);
- spa_history_log_internal(LOG_DS_RENAME, dd->dd_pool->dp_spa, tx,
- "dataset = %llu", ds->ds_object);
+ spa_history_log_internal_ds(ds, "rename", tx,
+ "-> @%s", newsnapname);
dsl_dataset_rele(hds, FTAG);
}
@@ -2939,8 +2931,7 @@
origin_ds->ds_phys->ds_unique_bytes = pa->unique;
/* log history record */
- spa_history_log_internal(LOG_DS_PROMOTE, dd->dd_pool->dp_spa, tx,
- "dataset = %llu", hds->ds_object);
+ spa_history_log_internal_ds(hds, "promote", tx, "");
dsl_dir_close(odd, FTAG);
}
@@ -3298,6 +3289,9 @@
csa->ohds->ds_phys->ds_deadlist_obj);
dsl_scan_ds_clone_swapped(csa->ohds, csa->cds, tx);
+
+ spa_history_log_internal_ds(csa->cds, "clone swap", tx,
+ "parent=%s", csa->ohds->ds_dir->dd_myname);
}
/*
@@ -3454,9 +3448,8 @@
dmu_buf_will_dirty(ds->ds_dbuf, tx);
ds->ds_quota = effective_value;
- spa_history_log_internal(LOG_DS_REFQUOTA,
- ds->ds_dir->dd_pool->dp_spa, tx, "%lld dataset = %llu ",
- (longlong_t)ds->ds_quota, ds->ds_object);
+ spa_history_log_internal_ds(ds, "set refquota", tx,
+ "refquota=%lld", (longlong_t)ds->ds_quota);
}
}
@@ -3561,9 +3554,8 @@
dsl_dir_diduse_space(ds->ds_dir, DD_USED_REFRSRV, delta, 0, 0, tx);
mutex_exit(&ds->ds_dir->dd_lock);
- spa_history_log_internal(LOG_DS_REFRESERV,
- ds->ds_dir->dd_pool->dp_spa, tx, "%lld dataset = %llu",
- (longlong_t)effective_value, ds->ds_object);
+ spa_history_log_internal_ds(ds, "set refreservation", tx,
+ "refreservation=%lld", (longlong_t)effective_value);
}
int
@@ -3629,7 +3621,7 @@
{
dsl_dataset_t *ds = arg1;
struct dsl_ds_holdarg *ha = arg2;
- char *htag = ha->htag;
+ const char *htag = ha->htag;
objset_t *mos = ds->ds_dir->dd_pool->dp_meta_objset;
int error = 0;
@@ -3663,7 +3655,7 @@
{
dsl_dataset_t *ds = arg1;
struct dsl_ds_holdarg *ha = arg2;
- char *htag = ha->htag;
+ const char *htag = ha->htag;
dsl_pool_t *dp = ds->ds_dir->dd_pool;
objset_t *mos = dp->dp_meta_objset;
uint64_t now = gethrestime_sec();
@@ -3691,9 +3683,9 @@
htag, &now, tx));
}
- spa_history_log_internal(LOG_DS_USER_HOLD,
- dp->dp_spa, tx, "<%s> temp = %d dataset = %llu", htag,
- (int)ha->temphold, ds->ds_object);
+ spa_history_log_internal_ds(ds, "hold", tx,
+ "tag = %s temp = %d holds now = %llu",
+ htag, (int)ha->temphold, ds->ds_userrefs);
}
static int
@@ -3900,7 +3892,6 @@
dsl_pool_t *dp = ds->ds_dir->dd_pool;
objset_t *mos = dp->dp_meta_objset;
uint64_t zapobj;
- uint64_t dsobj = ds->ds_object;
uint64_t refs;
int error;
@@ -3923,9 +3914,8 @@
dsl_dataset_destroy_sync(&dsda, tag, tx);
}
- spa_history_log_internal(LOG_DS_USER_RELEASE,
- dp->dp_spa, tx, "<%s> %lld dataset = %llu",
- ra->htag, (longlong_t)refs, dsobj);
+ spa_history_log_internal_ds(ds, "release", tx,
+ "tag = %s refs now = %lld", ra->htag, (longlong_t)refs);
}
static int
--- a/usr/src/uts/common/fs/zfs/dsl_deleg.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/dsl_deleg.c Sun Aug 12 11:56:48 2012 +0100
@@ -181,10 +181,8 @@
VERIFY(zap_update(mos, jumpobj,
perm, 8, 1, &n, tx) == 0);
- spa_history_log_internal(LOG_DS_PERM_UPDATE,
- dd->dd_pool->dp_spa, tx,
- "%s %s dataset = %llu", whokey, perm,
- dd->dd_phys->dd_head_dataset_obj);
+ spa_history_log_internal_dd(dd, "permission update", tx,
+ "%s %s", whokey, perm);
}
}
}
@@ -213,10 +211,8 @@
(void) zap_remove(mos, zapobj, whokey, tx);
VERIFY(0 == zap_destroy(mos, jumpobj, tx));
}
- spa_history_log_internal(LOG_DS_PERM_WHO_REMOVE,
- dd->dd_pool->dp_spa, tx,
- "%s dataset = %llu", whokey,
- dd->dd_phys->dd_head_dataset_obj);
+ spa_history_log_internal_dd(dd, "permission who remove",
+ tx, "%s", whokey);
continue;
}
@@ -234,10 +230,8 @@
VERIFY(0 == zap_destroy(mos,
jumpobj, tx));
}
- spa_history_log_internal(LOG_DS_PERM_REMOVE,
- dd->dd_pool->dp_spa, tx,
- "%s %s dataset = %llu", whokey, perm,
- dd->dd_phys->dd_head_dataset_obj);
+ spa_history_log_internal_dd(dd, "permission remove", tx,
+ "%s %s", whokey, perm);
}
}
}
@@ -524,12 +518,10 @@
}
/*
- * Check if user has requested permission. If descendent is set, must have
- * descendent perms.
+ * Check if user has requested permission.
*/
int
-dsl_deleg_access_impl(dsl_dataset_t *ds, boolean_t descendent, const char *perm,
- cred_t *cr)
+dsl_deleg_access_impl(dsl_dataset_t *ds, const char *perm, cred_t *cr)
{
dsl_dir_t *dd;
dsl_pool_t *dp;
@@ -550,7 +542,7 @@
SPA_VERSION_DELEGATED_PERMS)
return (EPERM);
- if (dsl_dataset_is_snapshot(ds) || descendent) {
+ if (dsl_dataset_is_snapshot(ds)) {
/*
* Snapshots are treated as descendents only,
* local permissions do not apply.
@@ -643,7 +635,7 @@
if (error)
return (error);
- error = dsl_deleg_access_impl(ds, B_FALSE, perm, cr);
+ error = dsl_deleg_access_impl(ds, perm, cr);
dsl_dataset_rele(ds, FTAG);
return (error);
--- a/usr/src/uts/common/fs/zfs/dsl_dir.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/dsl_dir.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#include <sys/dmu.h>
@@ -39,8 +40,8 @@
#include "zfs_namecheck.h"
static uint64_t dsl_dir_space_towrite(dsl_dir_t *dd);
-static void dsl_dir_set_reservation_sync(void *arg1, void *arg2, dmu_tx_t *tx);
-
+static void dsl_dir_set_reservation_sync_impl(dsl_dir_t *dd,
+ uint64_t value, dmu_tx_t *tx);
/* ARGSUSED */
static void
@@ -447,8 +448,7 @@
int
dsl_dir_destroy_check(void *arg1, void *arg2, dmu_tx_t *tx)
{
- dsl_dataset_t *ds = arg1;
- dsl_dir_t *dd = ds->ds_dir;
+ dsl_dir_t *dd = arg1;
dsl_pool_t *dp = dd->dd_pool;
objset_t *mos = dp->dp_meta_objset;
int err;
@@ -477,24 +477,19 @@
void
dsl_dir_destroy_sync(void *arg1, void *tag, dmu_tx_t *tx)
{
- dsl_dataset_t *ds = arg1;
- dsl_dir_t *dd = ds->ds_dir;
+ dsl_dir_t *dd = arg1;
objset_t *mos = dd->dd_pool->dp_meta_objset;
- dsl_prop_setarg_t psa;
- uint64_t value = 0;
uint64_t obj;
dd_used_t t;
ASSERT(RW_WRITE_HELD(&dd->dd_pool->dp_config_rwlock));
ASSERT(dd->dd_phys->dd_head_dataset_obj == 0);
- /* Remove our reservation. */
- dsl_prop_setarg_init_uint64(&psa, "reservation",
- (ZPROP_SRC_NONE | ZPROP_SRC_LOCAL | ZPROP_SRC_RECEIVED),
- &value);
- psa.psa_effective_value = 0; /* predict default value */
-
- dsl_dir_set_reservation_sync(ds, &psa, tx);
+ /*
+ * Remove our reservation. The impl() routine avoids setting the
+ * actual property, which would require the (already destroyed) ds.
+ */
+ dsl_dir_set_reservation_sync_impl(dd, 0, tx);
ASSERT3U(dd->dd_phys->dd_used_bytes, ==, 0);
ASSERT3U(dd->dd_phys->dd_reserved, ==, 0);
@@ -1060,9 +1055,8 @@
dd->dd_phys->dd_quota = effective_value;
mutex_exit(&dd->dd_lock);
- spa_history_log_internal(LOG_DS_QUOTA, dd->dd_pool->dp_spa,
- tx, "%lld dataset = %llu ",
- (longlong_t)effective_value, dd->dd_phys->dd_head_dataset_obj);
+ spa_history_log_internal_dd(dd, "set quota", tx,
+ "quota=%lld", (longlong_t)effective_value);
}
int
@@ -1149,25 +1143,17 @@
}
static void
-dsl_dir_set_reservation_sync(void *arg1, void *arg2, dmu_tx_t *tx)
+dsl_dir_set_reservation_sync_impl(dsl_dir_t *dd, uint64_t value, dmu_tx_t *tx)
{
- dsl_dataset_t *ds = arg1;
- dsl_dir_t *dd = ds->ds_dir;
- dsl_prop_setarg_t *psa = arg2;
- uint64_t effective_value = psa->psa_effective_value;
uint64_t used;
int64_t delta;
- dsl_prop_set_sync(ds, psa, tx);
- DSL_PROP_CHECK_PREDICTION(dd, psa);
-
dmu_buf_will_dirty(dd->dd_dbuf, tx);
mutex_enter(&dd->dd_lock);
used = dd->dd_phys->dd_used_bytes;
- delta = MAX(used, effective_value) -
- MAX(used, dd->dd_phys->dd_reserved);
- dd->dd_phys->dd_reserved = effective_value;
+ delta = MAX(used, value) - MAX(used, dd->dd_phys->dd_reserved);
+ dd->dd_phys->dd_reserved = value;
if (dd->dd_parent != NULL) {
/* Roll up this additional usage into our ancestors */
@@ -1175,10 +1161,24 @@
delta, 0, 0, tx);
}
mutex_exit(&dd->dd_lock);
+}
- spa_history_log_internal(LOG_DS_RESERVATION, dd->dd_pool->dp_spa,
- tx, "%lld dataset = %llu",
- (longlong_t)effective_value, dd->dd_phys->dd_head_dataset_obj);
+
+static void
+dsl_dir_set_reservation_sync(void *arg1, void *arg2, dmu_tx_t *tx)
+{
+ dsl_dataset_t *ds = arg1;
+ dsl_dir_t *dd = ds->ds_dir;
+ dsl_prop_setarg_t *psa = arg2;
+ uint64_t value = psa->psa_effective_value;
+
+ dsl_prop_set_sync(ds, psa, tx);
+ DSL_PROP_CHECK_PREDICTION(dd, psa);
+
+ dsl_dir_set_reservation_sync_impl(dd, value, tx);
+
+ spa_history_log_internal_dd(dd, "set reservation", tx,
+ "reservation=%lld", (longlong_t)value);
}
int
@@ -1299,9 +1299,15 @@
dsl_pool_t *dp = dd->dd_pool;
objset_t *mos = dp->dp_meta_objset;
int err;
+ char namebuf[MAXNAMELEN];
ASSERT(dmu_buf_refcount(dd->dd_dbuf) <= 2);
+ /* Log this before we change the name. */
+ dsl_dir_name(ra->newparent, namebuf);
+ spa_history_log_internal_dd(dd, "rename", tx,
+ "-> %s/%s", namebuf, ra->mynewname);
+
if (ra->newparent != dd->dd_parent) {
dsl_dir_diduse_space(dd->dd_parent, DD_USED_CHILD,
-dd->dd_phys->dd_used_bytes,
@@ -1341,8 +1347,6 @@
dd->dd_myname, 8, 1, &dd->dd_object, tx);
ASSERT3U(err, ==, 0);
- spa_history_log_internal(LOG_DS_RENAME, dd->dd_pool->dp_spa,
- tx, "dataset = %llu", dd->dd_phys->dd_head_dataset_obj);
}
int
--- a/usr/src/uts/common/fs/zfs/dsl_prop.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/dsl_prop.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#include <sys/zfs_context.h>
@@ -702,11 +703,9 @@
}
}
- spa_history_log_internal((source == ZPROP_SRC_NONE ||
- source == ZPROP_SRC_INHERITED) ? LOG_DS_INHERIT :
- LOG_DS_PROPSET, ds->ds_dir->dd_pool->dp_spa, tx,
- "%s=%s dataset = %llu", propname,
- (valstr == NULL ? "" : valstr), ds->ds_object);
+ spa_history_log_internal_ds(ds, (source == ZPROP_SRC_NONE ||
+ source == ZPROP_SRC_INHERITED) ? "inherit" : "set", tx,
+ "%s=%s", propname, (valstr == NULL ? "" : valstr));
if (tbuf != NULL)
kmem_free(tbuf, ZAP_MAXVALUELEN);
@@ -755,24 +754,6 @@
}
}
-void
-dsl_dir_prop_set_uint64_sync(dsl_dir_t *dd, const char *name, uint64_t val,
- dmu_tx_t *tx)
-{
- objset_t *mos = dd->dd_pool->dp_meta_objset;
- uint64_t zapobj = dd->dd_phys->dd_props_zapobj;
-
- ASSERT(dmu_tx_is_syncing(tx));
-
- VERIFY(0 == zap_update(mos, zapobj, name, sizeof (val), 1, &val, tx));
-
- dsl_prop_changed_notify(dd->dd_pool, dd->dd_object, name, val, TRUE);
-
- spa_history_log_internal(LOG_DS_PROPSET, dd->dd_pool->dp_spa, tx,
- "%s=%llu dataset = %llu", name, (u_longlong_t)val,
- dd->dd_phys->dd_head_dataset_obj);
-}
-
int
dsl_prop_set(const char *dsname, const char *propname, zprop_source_t source,
int intsz, int numints, const void *buf)
--- a/usr/src/uts/common/fs/zfs/dsl_scan.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/dsl_scan.c Sun Aug 12 11:56:48 2012 +0100
@@ -228,7 +228,7 @@
dsl_scan_sync_state(scn, tx);
- spa_history_log_internal(LOG_POOL_SCAN, spa, tx,
+ spa_history_log_internal(spa, "scan setup", tx,
"func=%u mintxg=%llu maxtxg=%llu",
*funcp, scn->scn_phys.scn_min_txg, scn->scn_phys.scn_max_txg);
}
@@ -277,7 +277,7 @@
else
scn->scn_phys.scn_state = DSS_CANCELED;
- spa_history_log_internal(LOG_POOL_SCAN_DONE, spa, tx,
+ spa_history_log_internal(spa, "scan done", tx,
"complete=%u", complete);
if (DSL_SCAN_IS_SCRUB_RESILVER(scn)) {
--- a/usr/src/uts/common/fs/zfs/dsl_synctask.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/dsl_synctask.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#include <sys/dmu.h>
@@ -85,17 +86,17 @@
/* Do a preliminary error check. */
dstg->dstg_err = 0;
+#ifdef ZFS_DEBUG
+ /*
+ * Only check half the time, otherwise, the sync-context
+ * check will almost never fail.
+ */
+ if (spa_get_random(2) == 0)
+ goto skip;
+#endif
rw_enter(&dstg->dstg_pool->dp_config_rwlock, RW_READER);
for (dst = list_head(&dstg->dstg_tasks); dst;
dst = list_next(&dstg->dstg_tasks, dst)) {
-#ifdef ZFS_DEBUG
- /*
- * Only check half the time, otherwise, the sync-context
- * check will almost never fail.
- */
- if (spa_get_random(2) == 0)
- continue;
-#endif
dst->dst_err =
dst->dst_checkfunc(dst->dst_arg1, dst->dst_arg2, tx);
if (dst->dst_err)
@@ -107,6 +108,7 @@
dmu_tx_commit(tx);
return (dstg->dstg_err);
}
+skip:
/*
* We don't generally have many sync tasks, so pay the price of
--- a/usr/src/uts/common/fs/zfs/rrwlock.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/rrwlock.c Sun Aug 12 11:56:48 2012 +0100
@@ -22,6 +22,9 @@
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
#include <sys/refcount.h>
#include <sys/rrwlock.h>
@@ -262,3 +265,13 @@
return (held);
}
+
+void
+rrw_tsd_destroy(void *arg)
+{
+ rrw_node_t *rn = arg;
+ if (rn != NULL) {
+ panic("thread %p terminating with rrw lock %p held",
+ (void *)curthread, (void *)rn->rn_rrl);
+ }
+}
--- a/usr/src/uts/common/fs/zfs/spa.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/spa.c Sun Aug 12 11:56:48 2012 +0100
@@ -2149,7 +2149,7 @@
if (spa_version(spa) >= SPA_VERSION_FEATURES) {
boolean_t missing_feat_read = B_FALSE;
- nvlist_t *unsup_feat;
+ nvlist_t *unsup_feat, *enabled_feat;
if (spa_dir_prop(spa, DMU_POOL_FEATURES_FOR_READ,
&spa->spa_feat_for_read_obj) != 0) {
@@ -2166,27 +2166,32 @@
return (spa_vdev_err(rvd, VDEV_AUX_CORRUPT_DATA, EIO));
}
- VERIFY(nvlist_alloc(&unsup_feat, NV_UNIQUE_NAME, KM_SLEEP) ==
- 0);
+ enabled_feat = fnvlist_alloc();
+ unsup_feat = fnvlist_alloc();
if (!feature_is_supported(spa->spa_meta_objset,
spa->spa_feat_for_read_obj, spa->spa_feat_desc_obj,
- unsup_feat))
+ unsup_feat, enabled_feat))
missing_feat_read = B_TRUE;
if (spa_writeable(spa) || state == SPA_LOAD_TRYIMPORT) {
if (!feature_is_supported(spa->spa_meta_objset,
spa->spa_feat_for_write_obj, spa->spa_feat_desc_obj,
- unsup_feat))
+ unsup_feat, enabled_feat)) {
missing_feat_write = B_TRUE;
+ }
}
+ fnvlist_add_nvlist(spa->spa_load_info,
+ ZPOOL_CONFIG_ENABLED_FEAT, enabled_feat);
+
if (!nvlist_empty(unsup_feat)) {
- VERIFY(nvlist_add_nvlist(spa->spa_load_info,
- ZPOOL_CONFIG_UNSUP_FEAT, unsup_feat) == 0);
+ fnvlist_add_nvlist(spa->spa_load_info,
+ ZPOOL_CONFIG_UNSUP_FEAT, unsup_feat);
}
- nvlist_free(unsup_feat);
+ fnvlist_free(enabled_feat);
+ fnvlist_free(unsup_feat);
if (!missing_feat_read) {
fnvlist_add_boolean(spa->spa_load_info,
@@ -2545,6 +2550,12 @@
spa_async_request(spa, SPA_ASYNC_RESILVER);
/*
+ * Log the fact that we booted up (so that we can detect if
+ * we rebooted in the middle of an operation).
+ */
+ spa_history_log_version(spa, "open");
+
+ /*
* Delete any inconsistent datasets.
*/
(void) dmu_objset_find(spa_name(spa),
@@ -3220,7 +3231,7 @@
*/
int
spa_create(const char *pool, nvlist_t *nvroot, nvlist_t *props,
- const char *history_str, nvlist_t *zplprops)
+ nvlist_t *zplprops)
{
spa_t *spa;
char *altroot = NULL;
@@ -3439,9 +3450,7 @@
spa_config_sync(spa, B_FALSE, B_TRUE);
- if (version >= SPA_VERSION_ZPOOL_HISTORY && history_str != NULL)
- (void) spa_history_log(spa, history_str, LOG_CMD_POOL_CREATE);
- spa_history_log_version(spa, LOG_POOL_CREATE);
+ spa_history_log_version(spa, "create");
spa->spa_minref = refcount_count(&spa->spa_refcount);
@@ -3641,7 +3650,6 @@
}
error = 0;
- spa_history_log_version(spa, LOG_POOL_IMPORT);
out:
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
vdev_free(rvd);
@@ -3703,7 +3711,7 @@
spa_config_sync(spa, B_FALSE, B_TRUE);
mutex_exit(&spa_namespace_lock);
- spa_history_log_version(spa, LOG_POOL_IMPORT);
+ spa_history_log_version(spa, "import");
return (0);
}
@@ -3834,7 +3842,7 @@
spa_async_request(spa, SPA_ASYNC_AUTOEXPAND);
mutex_exit(&spa_namespace_lock);
- spa_history_log_version(spa, LOG_POOL_IMPORT);
+ spa_history_log_version(spa, "import");
return (0);
}
@@ -4372,7 +4380,7 @@
*/
(void) spa_vdev_exit(spa, newrootvd, dtl_max_txg, 0);
- spa_history_log_internal(LOG_POOL_VDEV_ATTACH, spa, NULL,
+ spa_history_log_internal(spa, "vdev attach", NULL,
"%s vdev=%s %s vdev=%s",
replacing && newvd_isspare ? "spare in" :
replacing ? "replace" : "attach", newvdpath,
@@ -4589,7 +4597,7 @@
error = spa_vdev_exit(spa, vd, txg, 0);
- spa_history_log_internal(LOG_POOL_VDEV_DETACH, spa, NULL,
+ spa_history_log_internal(spa, "detach", NULL,
"vdev=%s", vdpath);
spa_strfree(vdpath);
@@ -4858,9 +4866,8 @@
if (vml[c] != NULL) {
vdev_split(vml[c]);
if (error == 0)
- spa_history_log_internal(LOG_POOL_VDEV_DETACH,
- spa, tx, "vdev=%s",
- vml[c]->vdev_path);
+ spa_history_log_internal(spa, "detach", tx,
+ "vdev=%s", vml[c]->vdev_path);
vdev_free(vml[c]);
}
}
@@ -4875,8 +4882,8 @@
zio_handle_panic_injection(spa, FTAG, 3);
/* split is complete; log a history record */
- spa_history_log_internal(LOG_POOL_SPLIT, newspa, NULL,
- "split new pool %s from pool %s", newname, spa_name(spa));
+ spa_history_log_internal(newspa, "split", NULL,
+ "from pool %s", spa_name(spa));
kmem_free(vml, children * sizeof (vdev_t *));
@@ -5462,8 +5469,7 @@
* then log an internal history event.
*/
if (new_space != old_space) {
- spa_history_log_internal(LOG_POOL_VDEV_ONLINE,
- spa, NULL,
+ spa_history_log_internal(spa, "vdev online", NULL,
"pool '%s' size: %llu(+%llu)",
spa_name(spa), new_space, new_space - old_space);
}
@@ -5699,6 +5705,7 @@
spa->spa_uberblock.ub_version = version;
vdev_config_dirty(spa->spa_root_vdev);
+ spa_history_log_internal(spa, "set", tx, "version=%lld", version);
}
/*
@@ -5733,6 +5740,8 @@
VERIFY3U(0, ==, zfeature_lookup_name(fname, &feature));
spa_feature_enable(spa, feature, tx);
+ spa_history_log_internal(spa, "set", tx,
+ "%s=enabled", nvpair_name(elem));
break;
case ZPOOL_PROP_VERSION:
@@ -5772,6 +5781,8 @@
*/
if (tx->tx_txg != TXG_INITIAL)
vdev_config_dirty(spa->spa_root_vdev);
+ spa_history_log_internal(spa, "set", tx,
+ "%s=%s", nvpair_name(elem), strval);
break;
default:
/*
@@ -5794,7 +5805,8 @@
VERIFY(zap_update(mos,
spa->spa_pool_props_object, propname,
1, strlen(strval) + 1, strval, tx) == 0);
-
+ spa_history_log_internal(spa, "set", tx,
+ "%s=%s", nvpair_name(elem), strval);
} else if (nvpair_type(elem) == DATA_TYPE_UINT64) {
VERIFY(nvpair_value_uint64(elem, &intval) == 0);
@@ -5806,6 +5818,8 @@
VERIFY(zap_update(mos,
spa->spa_pool_props_object, propname,
8, 1, &intval, tx) == 0);
+ spa_history_log_internal(spa, "set", tx,
+ "%s=%lld", nvpair_name(elem), intval);
} else {
ASSERT(0); /* not allowed */
}
@@ -5834,13 +5848,6 @@
}
}
- /* log internal history if this is not a zpool create */
- if (spa_version(spa) >= SPA_VERSION_ZPOOL_HISTORY &&
- tx->tx_txg != TXG_INITIAL) {
- spa_history_log_internal(LOG_POOL_PROPSET,
- spa, tx, "%s %lld %s",
- nvpair_name(elem), intval, spa_name(spa));
- }
}
mutex_exit(&spa->spa_props_lock);
--- a/usr/src/uts/common/fs/zfs/spa_history.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/spa_history.c Sun Aug 12 11:56:48 2012 +0100
@@ -21,7 +21,7 @@
/*
* Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2011 by Delphix. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#include <sys/spa.h>
@@ -30,9 +30,12 @@
#include <sys/dsl_synctask.h>
#include <sys/dmu_tx.h>
#include <sys/dmu_objset.h>
+#include <sys/dsl_dataset.h>
+#include <sys/dsl_dir.h>
#include <sys/utsname.h>
#include <sys/cmn_err.h>
#include <sys/sunddi.h>
+#include <sys/cred.h>
#include "zfs_comutil.h"
#ifdef _KERNEL
#include <sys/zone.h>
@@ -176,12 +179,14 @@
}
static char *
-spa_history_zone()
+spa_history_zone(void)
{
#ifdef _KERNEL
+ if (INGLOBALZONE(curproc))
+ return (NULL);
return (curproc->p_zone->zone_name);
#else
- return ("global");
+ return (NULL);
#endif
}
@@ -193,14 +198,12 @@
spa_history_log_sync(void *arg1, void *arg2, dmu_tx_t *tx)
{
spa_t *spa = arg1;
- history_arg_t *hap = arg2;
- const char *history_str = hap->ha_history_str;
+ nvlist_t *nvl = arg2;
objset_t *mos = spa->spa_meta_objset;
dmu_buf_t *dbp;
spa_history_phys_t *shpp;
size_t reclen;
uint64_t le_len;
- nvlist_t *nvrecord;
char *record_packed = NULL;
int ret;
@@ -230,46 +233,35 @@
}
#endif
- VERIFY(nvlist_alloc(&nvrecord, NV_UNIQUE_NAME, KM_SLEEP) == 0);
- VERIFY(nvlist_add_uint64(nvrecord, ZPOOL_HIST_TIME,
- gethrestime_sec()) == 0);
- VERIFY(nvlist_add_uint64(nvrecord, ZPOOL_HIST_WHO, hap->ha_uid) == 0);
- if (hap->ha_zone != NULL)
- VERIFY(nvlist_add_string(nvrecord, ZPOOL_HIST_ZONE,
- hap->ha_zone) == 0);
+ fnvlist_add_uint64(nvl, ZPOOL_HIST_TIME, gethrestime_sec());
#ifdef _KERNEL
- VERIFY(nvlist_add_string(nvrecord, ZPOOL_HIST_HOST,
- utsname.nodename) == 0);
+ fnvlist_add_string(nvl, ZPOOL_HIST_HOST, utsname.nodename);
#endif
- if (hap->ha_log_type == LOG_CMD_POOL_CREATE ||
- hap->ha_log_type == LOG_CMD_NORMAL) {
- VERIFY(nvlist_add_string(nvrecord, ZPOOL_HIST_CMD,
- history_str) == 0);
-
- zfs_dbgmsg("command: %s", history_str);
- } else {
- VERIFY(nvlist_add_uint64(nvrecord, ZPOOL_HIST_INT_EVENT,
- hap->ha_event) == 0);
- VERIFY(nvlist_add_uint64(nvrecord, ZPOOL_HIST_TXG,
- tx->tx_txg) == 0);
- VERIFY(nvlist_add_string(nvrecord, ZPOOL_HIST_INT_STR,
- history_str) == 0);
-
- zfs_dbgmsg("internal %s pool:%s txg:%llu %s",
- zfs_history_event_names[hap->ha_event], spa_name(spa),
- (longlong_t)tx->tx_txg, history_str);
-
+ if (nvlist_exists(nvl, ZPOOL_HIST_CMD)) {
+ zfs_dbgmsg("command: %s",
+ fnvlist_lookup_string(nvl, ZPOOL_HIST_CMD));
+ } else if (nvlist_exists(nvl, ZPOOL_HIST_INT_NAME)) {
+ if (nvlist_exists(nvl, ZPOOL_HIST_DSNAME)) {
+ zfs_dbgmsg("txg %lld %s %s (id %llu) %s",
+ fnvlist_lookup_uint64(nvl, ZPOOL_HIST_TXG),
+ fnvlist_lookup_string(nvl, ZPOOL_HIST_INT_NAME),
+ fnvlist_lookup_string(nvl, ZPOOL_HIST_DSNAME),
+ fnvlist_lookup_uint64(nvl, ZPOOL_HIST_DSID),
+ fnvlist_lookup_string(nvl, ZPOOL_HIST_INT_STR));
+ } else {
+ zfs_dbgmsg("txg %lld %s %s",
+ fnvlist_lookup_uint64(nvl, ZPOOL_HIST_TXG),
+ fnvlist_lookup_string(nvl, ZPOOL_HIST_INT_NAME),
+ fnvlist_lookup_string(nvl, ZPOOL_HIST_INT_STR));
+ }
+ } else if (nvlist_exists(nvl, ZPOOL_HIST_IOCTL)) {
+ zfs_dbgmsg("ioctl %s",
+ fnvlist_lookup_string(nvl, ZPOOL_HIST_IOCTL));
}
- VERIFY(nvlist_size(nvrecord, &reclen, NV_ENCODE_XDR) == 0);
- record_packed = kmem_alloc(reclen, KM_SLEEP);
-
- VERIFY(nvlist_pack(nvrecord, &record_packed, &reclen,
- NV_ENCODE_XDR, KM_SLEEP) == 0);
+ record_packed = fnvlist_pack(nvl, &reclen);
mutex_enter(&spa->spa_history_lock);
- if (hap->ha_log_type == LOG_CMD_POOL_CREATE)
- VERIFY(shpp->sh_eof == shpp->sh_pool_create_len);
/* write out the packed length as little endian */
le_len = LE_64((uint64_t)reclen);
@@ -277,33 +269,42 @@
if (!ret)
ret = spa_history_write(spa, record_packed, reclen, shpp, tx);
- if (!ret && hap->ha_log_type == LOG_CMD_POOL_CREATE) {
- shpp->sh_pool_create_len += sizeof (le_len) + reclen;
- shpp->sh_bof = shpp->sh_pool_create_len;
+ /* The first command is the create, which we keep forever */
+ if (ret == 0 && shpp->sh_pool_create_len == 0 &&
+ nvlist_exists(nvl, ZPOOL_HIST_CMD)) {
+ shpp->sh_pool_create_len = shpp->sh_bof = shpp->sh_eof;
}
mutex_exit(&spa->spa_history_lock);
- nvlist_free(nvrecord);
- kmem_free(record_packed, reclen);
+ fnvlist_pack_free(record_packed, reclen);
dmu_buf_rele(dbp, FTAG);
-
- strfree(hap->ha_history_str);
- if (hap->ha_zone != NULL)
- strfree(hap->ha_zone);
- kmem_free(hap, sizeof (history_arg_t));
+ fnvlist_free(nvl);
}
/*
* Write out a history event.
*/
int
-spa_history_log(spa_t *spa, const char *history_str, history_log_type_t what)
+spa_history_log(spa_t *spa, const char *msg)
{
- history_arg_t *ha;
+ int err;
+ nvlist_t *nvl = fnvlist_alloc();
+
+ fnvlist_add_string(nvl, ZPOOL_HIST_CMD, msg);
+ err = spa_history_log_nvl(spa, nvl);
+ fnvlist_free(nvl);
+ return (err);
+}
+
+int
+spa_history_log_nvl(spa_t *spa, nvlist_t *nvl)
+{
int err = 0;
dmu_tx_t *tx;
+ nvlist_t *nvarg;
- ASSERT(what != LOG_INTERNAL);
+ if (spa_version(spa) < SPA_VERSION_ZPOOL_HISTORY)
+ return (EINVAL);
tx = dmu_tx_create_dd(spa_get_dsl(spa)->dp_mos_dir);
err = dmu_tx_assign(tx, TXG_WAIT);
@@ -312,19 +313,21 @@
return (err);
}
- ha = kmem_alloc(sizeof (history_arg_t), KM_SLEEP);
- ha->ha_history_str = strdup(history_str);
- ha->ha_zone = strdup(spa_history_zone());
- ha->ha_log_type = what;
- ha->ha_uid = crgetuid(CRED());
+ nvarg = fnvlist_dup(nvl);
+ if (spa_history_zone() != NULL) {
+ fnvlist_add_string(nvarg, ZPOOL_HIST_ZONE,
+ spa_history_zone());
+ }
+ fnvlist_add_uint64(nvarg, ZPOOL_HIST_WHO, crgetruid(CRED()));
/* Kick this off asynchronously; errors are ignored. */
dsl_sync_task_do_nowait(spa_get_dsl(spa), NULL,
- spa_history_log_sync, spa, ha, 0, tx);
+ spa_history_log_sync, spa, nvarg, 0, tx);
dmu_tx_commit(tx);
- /* spa_history_log_sync will free ha and strings */
+ /* spa_history_log_sync will free nvl */
return (err);
+
}
/*
@@ -341,7 +344,7 @@
int err;
/*
- * If the command history doesn't exist (older pool),
+ * If the command history doesn't exist (older pool),
* that's ok, just return ENOENT.
*/
if (!spa->spa_history)
@@ -424,11 +427,14 @@
return (err);
}
+/*
+ * The nvlist will be consumed by this call.
+ */
static void
-log_internal(history_internal_events_t event, spa_t *spa,
+log_internal(nvlist_t *nvl, const char *operation, spa_t *spa,
dmu_tx_t *tx, const char *fmt, va_list adx)
{
- history_arg_t *ha;
+ char *msg;
/*
* If this is part of creating a pool, not everything is
@@ -437,28 +443,25 @@
if (tx->tx_txg == TXG_INITIAL)
return;
- ha = kmem_alloc(sizeof (history_arg_t), KM_SLEEP);
- ha->ha_history_str = kmem_alloc(vsnprintf(NULL, 0, fmt, adx) + 1,
- KM_SLEEP);
+ msg = kmem_alloc(vsnprintf(NULL, 0, fmt, adx) + 1, KM_SLEEP);
+ (void) vsprintf(msg, fmt, adx);
+ fnvlist_add_string(nvl, ZPOOL_HIST_INT_STR, msg);
+ strfree(msg);
- (void) vsprintf(ha->ha_history_str, fmt, adx);
-
- ha->ha_log_type = LOG_INTERNAL;
- ha->ha_event = event;
- ha->ha_zone = NULL;
- ha->ha_uid = 0;
+ fnvlist_add_string(nvl, ZPOOL_HIST_INT_NAME, operation);
+ fnvlist_add_uint64(nvl, ZPOOL_HIST_TXG, tx->tx_txg);
if (dmu_tx_is_syncing(tx)) {
- spa_history_log_sync(spa, ha, tx);
+ spa_history_log_sync(spa, nvl, tx);
} else {
dsl_sync_task_do_nowait(spa_get_dsl(spa), NULL,
- spa_history_log_sync, spa, ha, 0, tx);
+ spa_history_log_sync, spa, nvl, 0, tx);
}
- /* spa_history_log_sync() will free ha and strings */
+ /* spa_history_log_sync() will free nvl */
}
void
-spa_history_log_internal(history_internal_events_t event, spa_t *spa,
+spa_history_log_internal(spa_t *spa, const char *operation,
dmu_tx_t *tx, const char *fmt, ...)
{
dmu_tx_t *htx = tx;
@@ -474,7 +477,7 @@
}
va_start(adx, fmt);
- log_internal(event, spa, htx, fmt, adx);
+ log_internal(fnvlist_alloc(), operation, spa, htx, fmt, adx);
va_end(adx);
/* if we didn't get a tx from the caller, commit the one we made */
@@ -483,21 +486,56 @@
}
void
-spa_history_log_version(spa_t *spa, history_internal_events_t event)
+spa_history_log_internal_ds(dsl_dataset_t *ds, const char *operation,
+ dmu_tx_t *tx, const char *fmt, ...)
+{
+ va_list adx;
+ char namebuf[MAXNAMELEN];
+ nvlist_t *nvl = fnvlist_alloc();
+
+ ASSERT(tx != NULL);
+
+ dsl_dataset_name(ds, namebuf);
+ fnvlist_add_string(nvl, ZPOOL_HIST_DSNAME, namebuf);
+ fnvlist_add_uint64(nvl, ZPOOL_HIST_DSID, ds->ds_object);
+
+ va_start(adx, fmt);
+ log_internal(nvl, operation, dsl_dataset_get_spa(ds), tx, fmt, adx);
+ va_end(adx);
+}
+
+void
+spa_history_log_internal_dd(dsl_dir_t *dd, const char *operation,
+ dmu_tx_t *tx, const char *fmt, ...)
+{
+ va_list adx;
+ char namebuf[MAXNAMELEN];
+ nvlist_t *nvl = fnvlist_alloc();
+
+ ASSERT(tx != NULL);
+
+ dsl_dir_name(dd, namebuf);
+ fnvlist_add_string(nvl, ZPOOL_HIST_DSNAME, namebuf);
+ fnvlist_add_uint64(nvl, ZPOOL_HIST_DSID,
+ dd->dd_phys->dd_head_dataset_obj);
+
+ va_start(adx, fmt);
+ log_internal(nvl, operation, dd->dd_pool->dp_spa, tx, fmt, adx);
+ va_end(adx);
+}
+
+void
+spa_history_log_version(spa_t *spa, const char *operation)
{
#ifdef _KERNEL
uint64_t current_vers = spa_version(spa);
- if (current_vers >= SPA_VERSION_ZPOOL_HISTORY) {
- spa_history_log_internal(event, spa, NULL,
- "pool spa %llu; zfs spa %llu; zpl %d; uts %s %s %s %s",
- (u_longlong_t)current_vers, SPA_VERSION, ZPL_VERSION,
- utsname.nodename, utsname.release, utsname.version,
- utsname.machine);
- }
- cmn_err(CE_CONT, "!%s version %llu pool %s using %llu",
- event == LOG_POOL_IMPORT ? "imported" :
- event == LOG_POOL_CREATE ? "created" : "accessed",
+ spa_history_log_internal(spa, operation, NULL,
+ "pool version %llu; software version %llu/%d; uts %s %s %s %s",
+ (u_longlong_t)current_vers, SPA_VERSION, ZPL_VERSION,
+ utsname.nodename, utsname.release, utsname.version,
+ utsname.machine);
+ cmn_err(CE_CONT, "!%s version %llu pool %s using %llu", operation,
(u_longlong_t)current_vers, spa_name(spa), SPA_VERSION);
#endif
}
--- a/usr/src/uts/common/fs/zfs/sys/dmu.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/sys/dmu.h Sun Aug 12 11:56:48 2012 +0100
@@ -44,6 +44,7 @@
#include <sys/param.h>
#include <sys/cred.h>
#include <sys/time.h>
+#include <sys/fs/zfs.h>
#ifdef __cplusplus
extern "C" {
@@ -216,16 +217,6 @@
DMU_OTN_ZAP_METADATA = DMU_OT(DMU_BSWAP_ZAP, B_TRUE),
} dmu_object_type_t;
-typedef enum dmu_objset_type {
- DMU_OST_NONE,
- DMU_OST_META,
- DMU_OST_ZFS,
- DMU_OST_ZVOL,
- DMU_OST_OTHER, /* For testing only! */
- DMU_OST_ANY, /* Be careful! */
- DMU_OST_NUMTYPES
-} dmu_objset_type_t;
-
void byteswap_uint64_array(void *buf, size_t size);
void byteswap_uint32_array(void *buf, size_t size);
void byteswap_uint16_array(void *buf, size_t size);
@@ -270,9 +261,11 @@
int dmu_objset_clone(const char *name, struct dsl_dataset *clone_origin,
uint64_t flags);
int dmu_objset_destroy(const char *name, boolean_t defer);
-int dmu_snapshots_destroy_nvl(struct nvlist *snaps, boolean_t defer, char *);
-int dmu_objset_snapshot(char *fsname, char *snapname, char *tag,
- struct nvlist *props, boolean_t recursive, boolean_t temporary, int fd);
+int dmu_snapshots_destroy_nvl(struct nvlist *snaps, boolean_t defer,
+ struct nvlist *errlist);
+int dmu_objset_snapshot(struct nvlist *snaps, struct nvlist *, struct nvlist *);
+int dmu_objset_snapshot_one(const char *fsname, const char *snapname);
+int dmu_objset_snapshot_tmp(const char *, const char *, int);
int dmu_objset_rename(const char *name, const char *newname,
boolean_t recursive);
int dmu_objset_find(char *name, int func(const char *, void *), void *arg,
@@ -789,10 +782,9 @@
void dmu_traverse_objset(objset_t *os, uint64_t txg_start,
dmu_traverse_cb_t cb, void *arg);
-int dmu_send(objset_t *tosnap, objset_t *fromsnap, boolean_t fromorigin,
+int dmu_send(objset_t *tosnap, objset_t *fromsnap,
int outfd, struct vnode *vp, offset_t *off);
-int dmu_send_estimate(objset_t *tosnap, objset_t *fromsnap, boolean_t fromorign,
- uint64_t *sizep);
+int dmu_send_estimate(objset_t *tosnap, objset_t *fromsnap, uint64_t *sizep);
typedef struct dmu_recv_cookie {
/*
--- a/usr/src/uts/common/fs/zfs/sys/dmu_objset.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/sys/dmu_objset.h Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
/* Portions Copyright 2010 Robert Milkowski */
@@ -137,24 +138,14 @@
void dmu_objset_disown(objset_t *os, void *tag);
int dmu_objset_from_ds(struct dsl_dataset *ds, objset_t **osp);
-int dmu_objset_create(const char *name, dmu_objset_type_t type, uint64_t flags,
- void (*func)(objset_t *os, void *arg, cred_t *cr, dmu_tx_t *tx), void *arg);
-int dmu_objset_clone(const char *name, struct dsl_dataset *clone_origin,
- uint64_t flags);
-int dmu_objset_destroy(const char *name, boolean_t defer);
-int dmu_objset_snapshot(char *fsname, char *snapname, char *tag,
- struct nvlist *props, boolean_t recursive, boolean_t temporary, int fd);
void dmu_objset_stats(objset_t *os, nvlist_t *nv);
void dmu_objset_fast_stat(objset_t *os, dmu_objset_stats_t *stat);
void dmu_objset_space(objset_t *os, uint64_t *refdbytesp, uint64_t *availbytesp,
uint64_t *usedobjsp, uint64_t *availobjsp);
uint64_t dmu_objset_fsid_guid(objset_t *os);
-int dmu_objset_find(char *name, int func(const char *, void *), void *arg,
- int flags);
int dmu_objset_find_spa(spa_t *spa, const char *name,
int func(spa_t *, uint64_t, const char *, void *), void *arg, int flags);
int dmu_objset_prefetch(const char *name, void *arg);
-void dmu_objset_byteswap(void *buf, size_t size);
int dmu_objset_evict_dbufs(objset_t *os);
timestruc_t dmu_objset_snap_cmtime(objset_t *os);
--- a/usr/src/uts/common/fs/zfs/sys/dsl_dataset.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/sys/dsl_dataset.h Sun Aug 12 11:56:48 2012 +0100
@@ -180,7 +180,7 @@
struct dsl_ds_holdarg {
dsl_sync_task_group_t *dstg;
- char *htag;
+ const char *htag;
char *snapname;
boolean_t recursive;
boolean_t gotone;
@@ -215,12 +215,11 @@
uint64_t dsl_dataset_create_sync_dd(dsl_dir_t *dd, dsl_dataset_t *origin,
uint64_t flags, dmu_tx_t *tx);
int dsl_dataset_destroy(dsl_dataset_t *ds, void *tag, boolean_t defer);
-int dsl_snapshots_destroy(char *fsname, char *snapname, boolean_t defer);
dsl_checkfunc_t dsl_dataset_destroy_check;
dsl_syncfunc_t dsl_dataset_destroy_sync;
-dsl_checkfunc_t dsl_dataset_snapshot_check;
-dsl_syncfunc_t dsl_dataset_snapshot_sync;
dsl_syncfunc_t dsl_dataset_user_hold_sync;
+int dsl_dataset_snapshot_check(dsl_dataset_t *ds, const char *, dmu_tx_t *tx);
+void dsl_dataset_snapshot_sync(dsl_dataset_t *ds, const char *, dmu_tx_t *tx);
int dsl_dataset_rename(char *name, const char *newname, boolean_t recursive);
int dsl_dataset_promote(const char *name, char *conflsnap);
int dsl_dataset_clone_swap(dsl_dataset_t *clone, dsl_dataset_t *origin_head,
--- a/usr/src/uts/common/fs/zfs/sys/dsl_deleg.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/sys/dsl_deleg.h Sun Aug 12 11:56:48 2012 +0100
@@ -20,7 +20,7 @@
*/
/*
* Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2011 by Delphix. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#ifndef _SYS_DSL_DELEG_H
@@ -65,8 +65,7 @@
int dsl_deleg_get(const char *ddname, nvlist_t **nvp);
int dsl_deleg_set(const char *ddname, nvlist_t *nvp, boolean_t unset);
int dsl_deleg_access(const char *ddname, const char *perm, cred_t *cr);
-int dsl_deleg_access_impl(struct dsl_dataset *ds, boolean_t descendent,
- const char *perm, cred_t *cr);
+int dsl_deleg_access_impl(struct dsl_dataset *ds, const char *perm, cred_t *cr);
void dsl_deleg_set_create_perms(dsl_dir_t *dd, dmu_tx_t *tx, cred_t *cr);
int dsl_deleg_can_allow(char *ddname, nvlist_t *nvp, cred_t *cr);
int dsl_deleg_can_unallow(char *ddname, nvlist_t *nvp, cred_t *cr);
--- a/usr/src/uts/common/fs/zfs/sys/dsl_prop.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/sys/dsl_prop.h Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#ifndef _SYS_DSL_PROP_H
@@ -89,8 +90,6 @@
int dsl_prop_set(const char *ddname, const char *propname,
zprop_source_t source, int intsz, int numints, const void *buf);
int dsl_props_set(const char *dsname, zprop_source_t source, nvlist_t *nvl);
-void dsl_dir_prop_set_uint64_sync(dsl_dir_t *dd, const char *name, uint64_t val,
- dmu_tx_t *tx);
void dsl_prop_setarg_init_uint64(dsl_prop_setarg_t *psa, const char *propname,
zprop_source_t source, uint64_t *value);
--- a/usr/src/uts/common/fs/zfs/sys/rrwlock.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/sys/rrwlock.h Sun Aug 12 11:56:48 2012 +0100
@@ -22,12 +22,13 @@
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
+/*
+ * Copyright (c) 2012 by Delphix. All rights reserved.
+ */
#ifndef _SYS_RR_RW_LOCK_H
#define _SYS_RR_RW_LOCK_H
-#pragma ident "%Z%%M% %I% %E% SMI"
-
#ifdef __cplusplus
extern "C" {
#endif
@@ -69,6 +70,7 @@
void rrw_enter(rrwlock_t *rrl, krw_t rw, void *tag);
void rrw_exit(rrwlock_t *rrl, void *tag);
boolean_t rrw_held(rrwlock_t *rrl, krw_t rw);
+void rrw_tsd_destroy(void *arg);
#define RRW_READ_HELD(x) rrw_held(x, RW_READER)
#define RRW_WRITE_HELD(x) rrw_held(x, RW_WRITER)
--- a/usr/src/uts/common/fs/zfs/sys/spa.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/sys/spa.h Sun Aug 12 11:56:48 2012 +0100
@@ -52,6 +52,7 @@
typedef struct ddt ddt_t;
typedef struct ddt_entry ddt_entry_t;
struct dsl_pool;
+struct dsl_dataset;
/*
* General-purpose 32-bit and 64-bit bitfield encodings.
@@ -418,7 +419,7 @@
extern int spa_get_stats(const char *pool, nvlist_t **config, char *altroot,
size_t buflen);
extern int spa_create(const char *pool, nvlist_t *config, nvlist_t *props,
- const char *history_str, nvlist_t *zplprops);
+ nvlist_t *zplprops);
extern int spa_import_rootpool(char *devpath, char *devid);
extern int spa_import(const char *pool, nvlist_t *config, nvlist_t *props,
uint64_t flags);
@@ -632,31 +633,20 @@
extern int spa_mode(spa_t *spa);
extern uint64_t strtonum(const char *str, char **nptr);
-/* history logging */
-typedef enum history_log_type {
- LOG_CMD_POOL_CREATE,
- LOG_CMD_NORMAL,
- LOG_INTERNAL
-} history_log_type_t;
-
-typedef struct history_arg {
- char *ha_history_str;
- history_log_type_t ha_log_type;
- history_internal_events_t ha_event;
- char *ha_zone;
- uid_t ha_uid;
-} history_arg_t;
-
extern char *spa_his_ievent_table[];
extern void spa_history_create_obj(spa_t *spa, dmu_tx_t *tx);
extern int spa_history_get(spa_t *spa, uint64_t *offset, uint64_t *len_read,
char *his_buf);
-extern int spa_history_log(spa_t *spa, const char *his_buf,
- history_log_type_t what);
-extern void spa_history_log_internal(history_internal_events_t event,
- spa_t *spa, dmu_tx_t *tx, const char *fmt, ...);
-extern void spa_history_log_version(spa_t *spa, history_internal_events_t evt);
+extern int spa_history_log(spa_t *spa, const char *his_buf);
+extern int spa_history_log_nvl(spa_t *spa, nvlist_t *nvl);
+extern void spa_history_log_version(spa_t *spa, const char *operation);
+extern void spa_history_log_internal(spa_t *spa, const char *operation,
+ dmu_tx_t *tx, const char *fmt, ...);
+extern void spa_history_log_internal_ds(struct dsl_dataset *ds, const char *op,
+ dmu_tx_t *tx, const char *fmt, ...);
+extern void spa_history_log_internal_dd(dsl_dir_t *dd, const char *operation,
+ dmu_tx_t *tx, const char *fmt, ...);
/* error handling */
struct zbookmark;
--- a/usr/src/uts/common/fs/zfs/sys/zfeature.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/sys/zfeature.h Sun Aug 12 11:56:48 2012 +0100
@@ -35,7 +35,7 @@
#endif
extern boolean_t feature_is_supported(objset_t *os, uint64_t obj,
- uint64_t desc_obj, nvlist_t *unsup_feat);
+ uint64_t desc_obj, nvlist_t *unsup_feat, nvlist_t *enabled_feat);
struct spa;
extern void spa_feature_create_zap_objects(struct spa *, dmu_tx_t *);
--- a/usr/src/uts/common/fs/zfs/sys/zfs_ioctl.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/sys/zfs_ioctl.h Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#ifndef _SYS_ZFS_IOCTL_H
@@ -41,6 +42,15 @@
#endif
/*
+ * The structures in this file are passed between userland and the
+ * kernel. Userland may be running a 32-bit process, while the kernel
+ * is 64-bit. Therefore, these structures need to compile the same in
+ * 32-bit and 64-bit. This means not using type "long", and adding
+ * explicit padding so that the 32-bit structure will not be packed more
+ * tightly than the 64-bit structure (which requires 64-bit alignment).
+ */
+
+/*
* Property values for snapdir
*/
#define ZFS_SNAPDIR_HIDDEN 0
@@ -256,22 +266,29 @@
} zfs_case_t;
typedef struct zfs_cmd {
- char zc_name[MAXPATHLEN];
+ char zc_name[MAXPATHLEN]; /* name of pool or dataset */
+ uint64_t zc_nvlist_src; /* really (char *) */
+ uint64_t zc_nvlist_src_size;
+ uint64_t zc_nvlist_dst; /* really (char *) */
+ uint64_t zc_nvlist_dst_size;
+ boolean_t zc_nvlist_dst_filled; /* put an nvlist in dst? */
+ int zc_pad2;
+
+ /*
+ * The following members are for legacy ioctls which haven't been
+ * converted to the new method.
+ */
+ uint64_t zc_history; /* really (char *) */
char zc_value[MAXPATHLEN * 2];
char zc_string[MAXNAMELEN];
char zc_top_ds[MAXPATHLEN];
uint64_t zc_guid;
uint64_t zc_nvlist_conf; /* really (char *) */
uint64_t zc_nvlist_conf_size;
- uint64_t zc_nvlist_src; /* really (char *) */
- uint64_t zc_nvlist_src_size;
- uint64_t zc_nvlist_dst; /* really (char *) */
- uint64_t zc_nvlist_dst_size;
uint64_t zc_cookie;
uint64_t zc_objset_type;
uint64_t zc_perm_action;
- uint64_t zc_history; /* really (char *) */
- uint64_t zc_history_len;
+ uint64_t zc_history_len;
uint64_t zc_history_offset;
uint64_t zc_obj;
uint64_t zc_iflags; /* internal to zfs(7fs) */
--- a/usr/src/uts/common/fs/zfs/zfeature.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/zfeature.c Sun Aug 12 11:56:48 2012 +0100
@@ -173,7 +173,7 @@
*/
boolean_t
feature_is_supported(objset_t *os, uint64_t obj, uint64_t desc_obj,
- nvlist_t *unsup_feat)
+ nvlist_t *unsup_feat, nvlist_t *enabled_feat)
{
boolean_t supported;
zap_cursor_t zc;
@@ -186,11 +186,16 @@
ASSERT(za.za_integer_length == sizeof (uint64_t) &&
za.za_num_integers == 1);
+ if (NULL != enabled_feat) {
+ fnvlist_add_uint64(enabled_feat, za.za_name,
+ za.za_first_integer);
+ }
+
if (za.za_first_integer != 0 &&
!zfeature_is_supported(za.za_name)) {
supported = B_FALSE;
- if (unsup_feat != NULL) {
+ if (NULL != unsup_feat) {
char *desc = "";
char buf[MAXPATHLEN];
--- a/usr/src/uts/common/fs/zfs/zfs_ctldir.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/zfs_ctldir.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
/*
@@ -749,8 +750,7 @@
return (err);
if (err == 0) {
- err = dmu_objset_snapshot(name, dirname, NULL, NULL,
- B_FALSE, B_FALSE, -1);
+ err = dmu_objset_snapshot_one(name, dirname);
if (err)
return (err);
err = lookupnameat(dirname, seg, follow, NULL, vpp, dvp);
--- a/usr/src/uts/common/fs/zfs/zfs_ioctl.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/zfs_ioctl.c Sun Aug 12 11:56:48 2012 +0100
@@ -23,8 +23,109 @@
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
* Portions Copyright 2011 Martin Matuska
* Copyright 2011 Nexenta Systems, Inc. All rights reserved.
+ * Copyright (c) 2012, Joyent, Inc. All rights reserved.
* Copyright (c) 2012 by Delphix. All rights reserved.
- * Copyright (c) 2012, Joyent, Inc. All rights reserved.
+ */
+
+/*
+ * ZFS ioctls.
+ *
+ * This file handles the ioctls to /dev/zfs, used for configuring ZFS storage
+ * pools and filesystems, e.g. with /sbin/zfs and /sbin/zpool.
+ *
+ * There are two ways that we handle ioctls: the legacy way where almost
+ * all of the logic is in the ioctl callback, and the new way where most
+ * of the marshalling is handled in the common entry point, zfsdev_ioctl().
+ *
+ * Non-legacy ioctls should be registered by calling
+ * zfs_ioctl_register() from zfs_ioctl_init(). The ioctl is invoked
+ * from userland by lzc_ioctl().
+ *
+ * The registration arguments are as follows:
+ *
+ * const char *name
+ * The name of the ioctl. This is used for history logging. If the
+ * ioctl returns successfully (the callback returns 0), and allow_log
+ * is true, then a history log entry will be recorded with the input &
+ * output nvlists. The log entry can be printed with "zpool history -i".
+ *
+ * zfs_ioc_t ioc
+ * The ioctl request number, which userland will pass to ioctl(2).
+ * The ioctl numbers can change from release to release, because
+ * the caller (libzfs) must be matched to the kernel.
+ *
+ * zfs_secpolicy_func_t *secpolicy
+ * This function will be called before the zfs_ioc_func_t, to
+ * determine if this operation is permitted. It should return EPERM
+ * on failure, and 0 on success. Checks include determining if the
+ * dataset is visible in this zone, and if the user has either all
+ * zfs privileges in the zone (SYS_MOUNT), or has been granted permission
+ * to do this operation on this dataset with "zfs allow".
+ *
+ * zfs_ioc_namecheck_t namecheck
+ * This specifies what to expect in the zfs_cmd_t:zc_name -- a pool
+ * name, a dataset name, or nothing. If the name is not well-formed,
+ * the ioctl will fail and the callback will not be called.
+ * Therefore, the callback can assume that the name is well-formed
+ * (e.g. is null-terminated, doesn't have more than one '@' character,
+ * doesn't have invalid characters).
+ *
+ * zfs_ioc_poolcheck_t pool_check
+ * This specifies requirements on the pool state. If the pool does
+ * not meet them (is suspended or is readonly), the ioctl will fail
+ * and the callback will not be called. If any checks are specified
+ * (i.e. it is not POOL_CHECK_NONE), namecheck must not be NO_NAME.
+ * Multiple checks can be or-ed together (e.g. POOL_CHECK_SUSPENDED |
+ * POOL_CHECK_READONLY).
+ *
+ * boolean_t smush_outnvlist
+ * If smush_outnvlist is true, then the output is presumed to be a
+ * list of errors, and it will be "smushed" down to fit into the
+ * caller's buffer, by removing some entries and replacing them with a
+ * single "N_MORE_ERRORS" entry indicating how many were removed. See
+ * nvlist_smush() for details. If smush_outnvlist is false, and the
+ * outnvlist does not fit into the userland-provided buffer, then the
+ * ioctl will fail with ENOMEM.
+ *
+ * zfs_ioc_func_t *func
+ * The callback function that will perform the operation.
+ *
+ * The callback should return 0 on success, or an error number on
+ * failure. If the function fails, the userland ioctl will return -1,
+ * and errno will be set to the callback's return value. The callback
+ * will be called with the following arguments:
+ *
+ * const char *name
+ * The name of the pool or dataset to operate on, from
+ * zfs_cmd_t:zc_name. The 'namecheck' argument specifies the
+ * expected type (pool, dataset, or none).
+ *
+ * nvlist_t *innvl
+ * The input nvlist, deserialized from zfs_cmd_t:zc_nvlist_src. Or
+ * NULL if no input nvlist was provided. Changes to this nvlist are
+ * ignored. If the input nvlist could not be deserialized, the
+ * ioctl will fail and the callback will not be called.
+ *
+ * nvlist_t *outnvl
+ * The output nvlist, initially empty. The callback can fill it in,
+ * and it will be returned to userland by serializing it into
+ * zfs_cmd_t:zc_nvlist_dst. If it is non-empty, and serialization
+ * fails (e.g. because the caller didn't supply a large enough
+ * buffer), then the overall ioctl will fail. See the
+ * 'smush_nvlist' argument above for additional behaviors.
+ *
+ * There are two typical uses of the output nvlist:
+ * - To return state, e.g. property values. In this case,
+ * smush_outnvlist should be false. If the buffer was not large
+ * enough, the caller will reallocate a larger buffer and try
+ * the ioctl again.
+ *
+ * - To return multiple errors from an ioctl which makes on-disk
+ * changes. In this case, smush_outnvlist should be true.
+ * Ioctls which make on-disk modifications should generally not
+ * use the outnvl if they succeed, because the caller can not
+ * distinguish between the operation failing, and
+ * deserialization failing.
*/
#include <sys/types.h>
@@ -85,8 +186,13 @@
ldi_ident_t zfs_li = NULL;
dev_info_t *zfs_dip;
-typedef int zfs_ioc_func_t(zfs_cmd_t *);
-typedef int zfs_secpolicy_func_t(zfs_cmd_t *, cred_t *);
+uint_t zfs_fsyncer_key;
+extern uint_t rrw_tsd_key;
+static uint_t zfs_allow_log_key;
+
+typedef int zfs_ioc_legacy_func_t(zfs_cmd_t *);
+typedef int zfs_ioc_func_t(const char *, nvlist_t *, nvlist_t *);
+typedef int zfs_secpolicy_func_t(zfs_cmd_t *, nvlist_t *, cred_t *);
typedef enum {
NO_NAME,
@@ -97,15 +203,18 @@
typedef enum {
POOL_CHECK_NONE = 1 << 0,
POOL_CHECK_SUSPENDED = 1 << 1,
- POOL_CHECK_READONLY = 1 << 2
+ POOL_CHECK_READONLY = 1 << 2,
} zfs_ioc_poolcheck_t;
typedef struct zfs_ioc_vec {
+ zfs_ioc_legacy_func_t *zvec_legacy_func;
zfs_ioc_func_t *zvec_func;
zfs_secpolicy_func_t *zvec_secpolicy;
zfs_ioc_namecheck_t zvec_namecheck;
- boolean_t zvec_his_log;
+ boolean_t zvec_allow_log;
zfs_ioc_poolcheck_t zvec_pool_check;
+ boolean_t zvec_smush_outnvlist;
+ const char *zvec_name;
} zfs_ioc_vec_t;
/* This array is indexed by zfs_userquota_prop_t */
@@ -123,7 +232,8 @@
nvlist_t **errors);
static int zfs_fill_zplprops_root(uint64_t, nvlist_t *, nvlist_t *,
boolean_t *);
-int zfs_set_prop_nvlist(const char *, zprop_source_t, nvlist_t *, nvlist_t **);
+int zfs_set_prop_nvlist(const char *, zprop_source_t, nvlist_t *, nvlist_t *);
+static int get_nvlist(uint64_t nvl, uint64_t size, int iflag, nvlist_t **nvp);
/* _NOTE(PRINTFLIKE(4)) - this is printf-like, but lint is too whiney */
void
@@ -261,7 +371,7 @@
if (spa_open(zc->zc_name, &spa, FTAG) == 0) {
if (spa_version(spa) >= SPA_VERSION_ZPOOL_HISTORY)
- (void) spa_history_log(spa, buf, LOG_CMD_NORMAL);
+ (void) spa_history_log(spa, buf);
spa_close(spa, FTAG);
}
history_str_free(buf);
@@ -273,7 +383,7 @@
*/
/* ARGSUSED */
static int
-zfs_secpolicy_none(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_none(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
return (0);
}
@@ -284,7 +394,7 @@
*/
/* ARGSUSED */
static int
-zfs_secpolicy_read(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_read(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
if (INGLOBALZONE(curproc) ||
zone_dataset_visible(zc->zc_name, NULL))
@@ -353,26 +463,13 @@
return (zfs_dozonecheck_impl(dataset, zoned, cr));
}
-/*
- * If name ends in a '@', then require recursive permissions.
- */
-int
+static int
zfs_secpolicy_write_perms(const char *name, const char *perm, cred_t *cr)
{
int error;
- boolean_t descendent = B_FALSE;
dsl_dataset_t *ds;
- char *at;
-
- at = strchr(name, '@');
- if (at != NULL && at[1] == '\0') {
- *at = '\0';
- descendent = B_TRUE;
- }
error = dsl_dataset_hold(name, FTAG, &ds);
- if (at != NULL)
- *at = '@';
if (error != 0)
return (error);
@@ -380,14 +477,14 @@
if (error == 0) {
error = secpolicy_zfs(cr);
if (error)
- error = dsl_deleg_access_impl(ds, descendent, perm, cr);
+ error = dsl_deleg_access_impl(ds, perm, cr);
}
dsl_dataset_rele(ds, FTAG);
return (error);
}
-int
+static int
zfs_secpolicy_write_perms_ds(const char *name, dsl_dataset_t *ds,
const char *perm, cred_t *cr)
{
@@ -397,7 +494,7 @@
if (error == 0) {
error = secpolicy_zfs(cr);
if (error)
- error = dsl_deleg_access_impl(ds, B_FALSE, perm, cr);
+ error = dsl_deleg_access_impl(ds, perm, cr);
}
return (error);
}
@@ -551,8 +648,9 @@
return (zfs_secpolicy_write_perms(dsname, zfs_prop_to_name(prop), cr));
}
-int
-zfs_secpolicy_fsacl(zfs_cmd_t *zc, cred_t *cr)
+/* ARGSUSED */
+static int
+zfs_secpolicy_set_fsacl(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
int error;
@@ -567,15 +665,17 @@
return (0);
}
-int
-zfs_secpolicy_rollback(zfs_cmd_t *zc, cred_t *cr)
+/* ARGSUSED */
+static int
+zfs_secpolicy_rollback(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
return (zfs_secpolicy_write_perms(zc->zc_name,
ZFS_DELEG_PERM_ROLLBACK, cr));
}
-int
-zfs_secpolicy_send(zfs_cmd_t *zc, cred_t *cr)
+/* ARGSUSED */
+static int
+zfs_secpolicy_send(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
spa_t *spa;
dsl_pool_t *dp;
@@ -611,8 +711,17 @@
return (error);
}
+/* ARGSUSED */
static int
-zfs_secpolicy_deleg_share(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_send_new(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
+{
+ return (zfs_secpolicy_write_perms(zc->zc_name,
+ ZFS_DELEG_PERM_SEND, cr));
+}
+
+/* ARGSUSED */
+static int
+zfs_secpolicy_deleg_share(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
vnode_t *vp;
int error;
@@ -636,7 +745,7 @@
}
int
-zfs_secpolicy_share(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_share(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
if (!INGLOBALZONE(curproc))
return (EPERM);
@@ -644,12 +753,12 @@
if (secpolicy_nfs(cr) == 0) {
return (0);
} else {
- return (zfs_secpolicy_deleg_share(zc, cr));
+ return (zfs_secpolicy_deleg_share(zc, innvl, cr));
}
}
int
-zfs_secpolicy_smb_acl(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_smb_acl(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
if (!INGLOBALZONE(curproc))
return (EPERM);
@@ -657,7 +766,7 @@
if (secpolicy_smb(cr) == 0) {
return (0);
} else {
- return (zfs_secpolicy_deleg_share(zc, cr));
+ return (zfs_secpolicy_deleg_share(zc, innvl, cr));
}
}
@@ -695,27 +804,55 @@
return (zfs_secpolicy_write_perms(name, ZFS_DELEG_PERM_DESTROY, cr));
}
+/* ARGSUSED */
static int
-zfs_secpolicy_destroy(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_destroy(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
return (zfs_secpolicy_destroy_perms(zc->zc_name, cr));
}
/*
* Destroying snapshots with delegated permissions requires
- * descendent mount and destroy permissions.
+ * descendant mount and destroy permissions.
*/
+/* ARGSUSED */
static int
-zfs_secpolicy_destroy_recursive(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_destroy_snaps(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
- int error;
- char *dsname;
-
- dsname = kmem_asprintf("%s@", zc->zc_name);
-
- error = zfs_secpolicy_destroy_perms(dsname, cr);
-
- strfree(dsname);
+ nvlist_t *snaps;
+ nvpair_t *pair, *nextpair;
+ int error = 0;
+
+ if (nvlist_lookup_nvlist(innvl, "snaps", &snaps) != 0)
+ return (EINVAL);
+ for (pair = nvlist_next_nvpair(snaps, NULL); pair != NULL;
+ pair = nextpair) {
+ dsl_dataset_t *ds;
+
+ nextpair = nvlist_next_nvpair(snaps, pair);
+ error = dsl_dataset_hold(nvpair_name(pair), FTAG, &ds);
+ if (error == 0) {
+ dsl_dataset_rele(ds, FTAG);
+ } else if (error == ENOENT) {
+ /*
+ * Ignore any snapshots that don't exist (we consider
+ * them "already destroyed"). Remove the name from the
+ * nvl here in case the snapshot is created between
+ * now and when we try to destroy it (in which case
+ * we don't want to destroy it since we haven't
+ * checked for permission).
+ */
+ fnvlist_remove_nvpair(snaps, pair);
+ error = 0;
+ continue;
+ } else {
+ break;
+ }
+ error = zfs_secpolicy_destroy_perms(nvpair_name(pair), cr);
+ if (error != 0)
+ break;
+ }
+
return (error);
}
@@ -748,14 +885,16 @@
return (error);
}
+/* ARGSUSED */
static int
-zfs_secpolicy_rename(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_rename(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
return (zfs_secpolicy_rename_perms(zc->zc_name, zc->zc_value, cr));
}
+/* ARGSUSED */
static int
-zfs_secpolicy_promote(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_promote(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
char parentname[MAXNAMELEN];
objset_t *clone;
@@ -795,8 +934,9 @@
return (error);
}
+/* ARGSUSED */
static int
-zfs_secpolicy_receive(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_recv(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
int error;
@@ -819,49 +959,72 @@
ZFS_DELEG_PERM_SNAPSHOT, cr));
}
+/*
+ * Check for permission to create each snapshot in the nvlist.
+ */
+/* ARGSUSED */
static int
-zfs_secpolicy_snapshot(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_snapshot(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
-
- return (zfs_secpolicy_snapshot_perms(zc->zc_name, cr));
+ nvlist_t *snaps;
+ int error;
+ nvpair_t *pair;
+
+ if (nvlist_lookup_nvlist(innvl, "snaps", &snaps) != 0)
+ return (EINVAL);
+ for (pair = nvlist_next_nvpair(snaps, NULL); pair != NULL;
+ pair = nvlist_next_nvpair(snaps, pair)) {
+ char *name = nvpair_name(pair);
+ char *atp = strchr(name, '@');
+
+ if (atp == NULL) {
+ error = EINVAL;
+ break;
+ }
+ *atp = '\0';
+ error = zfs_secpolicy_snapshot_perms(name, cr);
+ *atp = '@';
+ if (error != 0)
+ break;
+ }
+ return (error);
+}
+
+/* ARGSUSED */
+static int
+zfs_secpolicy_log_history(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
+{
+ /*
+ * Even root must have a proper TSD so that we know what pool
+ * to log to.
+ */
+ if (tsd_get(zfs_allow_log_key) == NULL)
+ return (EPERM);
+ return (0);
}
static int
-zfs_secpolicy_create(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_create_clone(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
char parentname[MAXNAMELEN];
int error;
+ char *origin;
if ((error = zfs_get_parent(zc->zc_name, parentname,
sizeof (parentname))) != 0)
return (error);
- if (zc->zc_value[0] != '\0') {
- if ((error = zfs_secpolicy_write_perms(zc->zc_value,
- ZFS_DELEG_PERM_CLONE, cr)) != 0)
- return (error);
- }
+ if (nvlist_lookup_string(innvl, "origin", &origin) == 0 &&
+ (error = zfs_secpolicy_write_perms(origin,
+ ZFS_DELEG_PERM_CLONE, cr)) != 0)
+ return (error);
if ((error = zfs_secpolicy_write_perms(parentname,
ZFS_DELEG_PERM_CREATE, cr)) != 0)
return (error);
- error = zfs_secpolicy_write_perms(parentname,
- ZFS_DELEG_PERM_MOUNT, cr);
-
- return (error);
-}
-
-static int
-zfs_secpolicy_umount(zfs_cmd_t *zc, cred_t *cr)
-{
- int error;
-
- error = secpolicy_fs_unmount(cr, NULL);
- if (error) {
- error = dsl_deleg_access(zc->zc_name, ZFS_DELEG_PERM_MOUNT, cr);
- }
- return (error);
+ return (zfs_secpolicy_write_perms(parentname,
+ ZFS_DELEG_PERM_MOUNT, cr));
}
/*
@@ -870,7 +1033,7 @@
*/
/* ARGSUSED */
static int
-zfs_secpolicy_config(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_config(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
if (secpolicy_sys_config(cr, B_FALSE) != 0)
return (EPERM);
@@ -883,7 +1046,7 @@
*/
/* ARGSUSED */
static int
-zfs_secpolicy_diff(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_diff(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
int error;
@@ -899,13 +1062,14 @@
*/
/* ARGSUSED */
static int
-zfs_secpolicy_inject(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_inject(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
return (secpolicy_zinject(cr));
}
+/* ARGSUSED */
static int
-zfs_secpolicy_inherit(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_inherit_prop(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
zfs_prop_t prop = zfs_name_to_prop(zc->zc_value);
@@ -921,9 +1085,9 @@
}
static int
-zfs_secpolicy_userspace_one(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_userspace_one(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
- int err = zfs_secpolicy_read(zc, cr);
+ int err = zfs_secpolicy_read(zc, innvl, cr);
if (err)
return (err);
@@ -950,9 +1114,9 @@
}
static int
-zfs_secpolicy_userspace_many(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_userspace_many(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
- int err = zfs_secpolicy_read(zc, cr);
+ int err = zfs_secpolicy_read(zc, innvl, cr);
if (err)
return (err);
@@ -963,22 +1127,25 @@
userquota_perms[zc->zc_objset_type], cr));
}
+/* ARGSUSED */
static int
-zfs_secpolicy_userspace_upgrade(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_userspace_upgrade(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
return (zfs_secpolicy_setprop(zc->zc_name, ZFS_PROP_VERSION,
NULL, cr));
}
+/* ARGSUSED */
static int
-zfs_secpolicy_hold(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_hold(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
return (zfs_secpolicy_write_perms(zc->zc_name,
ZFS_DELEG_PERM_HOLD, cr));
}
+/* ARGSUSED */
static int
-zfs_secpolicy_release(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_release(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
return (zfs_secpolicy_write_perms(zc->zc_name,
ZFS_DELEG_PERM_RELEASE, cr));
@@ -988,7 +1155,7 @@
* Policy for allowing temporary snapshots to be taken or released
*/
static int
-zfs_secpolicy_tmp_snapshot(zfs_cmd_t *zc, cred_t *cr)
+zfs_secpolicy_tmp_snapshot(zfs_cmd_t *zc, nvlist_t *innvl, cred_t *cr)
{
/*
* A temporary snapshot is the same as a snapshot,
@@ -1001,13 +1168,13 @@
ZFS_DELEG_PERM_DIFF, cr)) == 0)
return (0);
- error = zfs_secpolicy_snapshot(zc, cr);
+ error = zfs_secpolicy_snapshot_perms(zc->zc_name, cr);
if (!error)
- error = zfs_secpolicy_hold(zc, cr);
+ error = zfs_secpolicy_hold(zc, innvl, cr);
if (!error)
- error = zfs_secpolicy_release(zc, cr);
+ error = zfs_secpolicy_release(zc, innvl, cr);
if (!error)
- error = zfs_secpolicy_destroy(zc, cr);
+ error = zfs_secpolicy_destroy(zc, innvl, cr);
return (error);
}
@@ -1046,36 +1213,40 @@
return (0);
}
+/*
+ * Reduce the size of this nvlist until it can be serialized in 'max' bytes.
+ * Entries will be removed from the end of the nvlist, and one int32 entry
+ * named "N_MORE_ERRORS" will be added indicating how many entries were
+ * removed.
+ */
static int
-fit_error_list(zfs_cmd_t *zc, nvlist_t **errors)
+nvlist_smush(nvlist_t *errors, size_t max)
{
size_t size;
- VERIFY(nvlist_size(*errors, &size, NV_ENCODE_NATIVE) == 0);
-
- if (size > zc->zc_nvlist_dst_size) {
+ size = fnvlist_size(errors);
+
+ if (size > max) {
nvpair_t *more_errors;
int n = 0;
- if (zc->zc_nvlist_dst_size < 1024)
+ if (max < 1024)
return (ENOMEM);
- VERIFY(nvlist_add_int32(*errors, ZPROP_N_MORE_ERRORS, 0) == 0);
- more_errors = nvlist_prev_nvpair(*errors, NULL);
+ fnvlist_add_int32(errors, ZPROP_N_MORE_ERRORS, 0);
+ more_errors = nvlist_prev_nvpair(errors, NULL);
do {
- nvpair_t *pair = nvlist_prev_nvpair(*errors,
+ nvpair_t *pair = nvlist_prev_nvpair(errors,
more_errors);
- VERIFY(nvlist_remove_nvpair(*errors, pair) == 0);
+ fnvlist_remove_nvpair(errors, pair);
n++;
- VERIFY(nvlist_size(*errors, &size,
- NV_ENCODE_NATIVE) == 0);
- } while (size > zc->zc_nvlist_dst_size);
-
- VERIFY(nvlist_remove_nvpair(*errors, more_errors) == 0);
- VERIFY(nvlist_add_int32(*errors, ZPROP_N_MORE_ERRORS, n) == 0);
- ASSERT(nvlist_size(*errors, &size, NV_ENCODE_NATIVE) == 0);
- ASSERT(size <= zc->zc_nvlist_dst_size);
+ size = fnvlist_size(errors);
+ } while (size > max);
+
+ fnvlist_remove_nvpair(errors, more_errors);
+ fnvlist_add_int32(errors, ZPROP_N_MORE_ERRORS, n);
+ ASSERT3U(fnvlist_size(errors), <=, max);
}
return (0);
@@ -1088,21 +1259,20 @@
int error = 0;
size_t size;
- VERIFY(nvlist_size(nvl, &size, NV_ENCODE_NATIVE) == 0);
+ size = fnvlist_size(nvl);
if (size > zc->zc_nvlist_dst_size) {
error = ENOMEM;
} else {
- packed = kmem_alloc(size, KM_SLEEP);
- VERIFY(nvlist_pack(nvl, &packed, &size, NV_ENCODE_NATIVE,
- KM_SLEEP) == 0);
+ packed = fnvlist_pack(nvl, &size);
if (ddi_copyout(packed, (void *)(uintptr_t)zc->zc_nvlist_dst,
size, zc->zc_iflags) != 0)
error = EFAULT;
- kmem_free(packed, size);
+ fnvlist_pack_free(packed, size);
}
zc->zc_nvlist_dst_size = size;
+ zc->zc_nvlist_dst_filled = B_TRUE;
return (error);
}
@@ -1181,7 +1351,6 @@
nvlist_t *config, *props = NULL;
nvlist_t *rootprops = NULL;
nvlist_t *zplprops = NULL;
- char *buf;
if (error = get_nvlist(zc->zc_nvlist_conf, zc->zc_nvlist_conf_size,
zc->zc_iflags, &config))
@@ -1221,9 +1390,7 @@
goto pool_props_bad;
}
- buf = history_str_get(zc);
-
- error = spa_create(zc->zc_name, config, props, buf, zplprops);
+ error = spa_create(zc->zc_name, config, props, zplprops);
/*
* Set the remaining root properties
@@ -1232,9 +1399,6 @@
ZPROP_SRC_LOCAL, rootprops, NULL)) != 0)
(void) spa_destroy(zc->zc_name);
- if (buf != NULL)
- history_str_free(buf);
-
pool_props_bad:
nvlist_free(rootprops);
nvlist_free(zplprops);
@@ -2229,31 +2393,25 @@
/*
* This function is best effort. If it fails to set any of the given properties,
- * it continues to set as many as it can and returns the first error
- * encountered. If the caller provides a non-NULL errlist, it also gives the
- * complete list of names of all the properties it failed to set along with the
- * corresponding error numbers. The caller is responsible for freeing the
- * returned errlist.
+ * it continues to set as many as it can and returns the last error
+ * encountered. If the caller provides a non-NULL errlist, it will be filled in
+ * with the list of names of all the properties that failed along with the
+ * corresponding error numbers.
*
- * If every property is set successfully, zero is returned and the list pointed
- * at by errlist is NULL.
+ * If every property is set successfully, zero is returned and errlist is not
+ * modified.
*/
int
zfs_set_prop_nvlist(const char *dsname, zprop_source_t source, nvlist_t *nvl,
- nvlist_t **errlist)
+ nvlist_t *errlist)
{
nvpair_t *pair;
nvpair_t *propval;
int rv = 0;
uint64_t intval;
char *strval;
- nvlist_t *genericnvl;
- nvlist_t *errors;
- nvlist_t *retrynvl;
-
- VERIFY(nvlist_alloc(&genericnvl, NV_UNIQUE_NAME, KM_SLEEP) == 0);
- VERIFY(nvlist_alloc(&errors, NV_UNIQUE_NAME, KM_SLEEP) == 0);
- VERIFY(nvlist_alloc(&retrynvl, NV_UNIQUE_NAME, KM_SLEEP) == 0);
+ nvlist_t *genericnvl = fnvlist_alloc();
+ nvlist_t *retrynvl = fnvlist_alloc();
retry:
pair = NULL;
@@ -2266,7 +2424,7 @@
propval = pair;
if (nvpair_type(pair) == DATA_TYPE_NVLIST) {
nvlist_t *attrs;
- VERIFY(nvpair_value_nvlist(pair, &attrs) == 0);
+ attrs = fnvpair_value_nvlist(pair);
if (nvlist_lookup_nvpair(attrs, ZPROP_VALUE,
&propval) != 0)
err = EINVAL;
@@ -2291,8 +2449,7 @@
} else if (nvpair_type(propval) == DATA_TYPE_UINT64) {
const char *unused;
- VERIFY(nvpair_value_uint64(propval,
- &intval) == 0);
+ intval = fnvpair_value_uint64(propval);
switch (zfs_prop_get_type(prop)) {
case PROP_TYPE_NUMBER:
@@ -2336,8 +2493,11 @@
}
}
- if (err != 0)
- VERIFY(nvlist_add_int32(errors, propname, err) == 0);
+ if (err != 0) {
+ if (errlist != NULL)
+ fnvlist_add_int32(errlist, propname, err);
+ rv = err;
+ }
}
if (nvl != retrynvl && !nvlist_empty(retrynvl)) {
@@ -2359,44 +2519,33 @@
propval = pair;
if (nvpair_type(pair) == DATA_TYPE_NVLIST) {
nvlist_t *attrs;
- VERIFY(nvpair_value_nvlist(pair, &attrs) == 0);
- VERIFY(nvlist_lookup_nvpair(attrs, ZPROP_VALUE,
- &propval) == 0);
+ attrs = fnvpair_value_nvlist(pair);
+ propval = fnvlist_lookup_nvpair(attrs,
+ ZPROP_VALUE);
}
if (nvpair_type(propval) == DATA_TYPE_STRING) {
- VERIFY(nvpair_value_string(propval,
- &strval) == 0);
+ strval = fnvpair_value_string(propval);
err = dsl_prop_set(dsname, propname, source, 1,
strlen(strval) + 1, strval);
} else {
- VERIFY(nvpair_value_uint64(propval,
- &intval) == 0);
+ intval = fnvpair_value_uint64(propval);
err = dsl_prop_set(dsname, propname, source, 8,
1, &intval);
}
if (err != 0) {
- VERIFY(nvlist_add_int32(errors, propname,
- err) == 0);
+ if (errlist != NULL) {
+ fnvlist_add_int32(errlist, propname,
+ err);
+ }
+ rv = err;
}
}
}
nvlist_free(genericnvl);
nvlist_free(retrynvl);
- if ((pair = nvlist_next_nvpair(errors, NULL)) == NULL) {
- nvlist_free(errors);
- errors = NULL;
- } else {
- VERIFY(nvpair_value_int32(pair, &rv) == 0);
- }
-
- if (errlist == NULL)
- nvlist_free(errors);
- else
- *errlist = errors;
-
return (rv);
}
@@ -2404,7 +2553,7 @@
* Check that all the properties are valid user properties.
*/
static int
-zfs_check_userprops(char *fsname, nvlist_t *nvl)
+zfs_check_userprops(const char *fsname, nvlist_t *nvl)
{
nvpair_t *pair = NULL;
int error = 0;
@@ -2484,7 +2633,7 @@
boolean_t received = zc->zc_cookie;
zprop_source_t source = (received ? ZPROP_SRC_RECEIVED :
ZPROP_SRC_LOCAL);
- nvlist_t *errors = NULL;
+ nvlist_t *errors;
int error;
if ((error = get_nvlist(zc->zc_nvlist_src, zc->zc_nvlist_src_size,
@@ -2507,7 +2656,8 @@
}
}
- error = zfs_set_prop_nvlist(zc->zc_name, source, nvl, &errors);
+ errors = fnvlist_alloc();
+ error = zfs_set_prop_nvlist(zc->zc_name, source, nvl, errors);
if (zc->zc_nvlist_dst != NULL && errors != NULL) {
(void) put_nvlist(zc, errors);
@@ -2589,7 +2739,7 @@
return (EINVAL);
}
- /* the property name has been validated by zfs_secpolicy_inherit() */
+ /* property name has been validated by zfs_secpolicy_inherit_prop() */
return (dsl_prop_set(zc->zc_name, zc->zc_value, source, 0, 0, NULL));
}
@@ -2932,26 +3082,30 @@
}
/*
- * inputs:
- * zc_objset_type type of objset to create (fs vs zvol)
- * zc_name name of new objset
- * zc_value name of snapshot to clone from (may be empty)
- * zc_nvlist_src{_size} nvlist of properties to apply
+ * innvl: {
+ * "type" -> dmu_objset_type_t (int32)
+ * (optional) "props" -> { prop -> value }
+ * }
*
- * outputs: none
+ * outnvl: propname -> error code (int32)
*/
static int
-zfs_ioc_create(zfs_cmd_t *zc)
+zfs_ioc_create(const char *fsname, nvlist_t *innvl, nvlist_t *outnvl)
{
- objset_t *clone;
int error = 0;
- zfs_creat_t zct;
+ zfs_creat_t zct = { 0 };
nvlist_t *nvprops = NULL;
void (*cbfunc)(objset_t *os, void *arg, cred_t *cr, dmu_tx_t *tx);
- dmu_objset_type_t type = zc->zc_objset_type;
+ int32_t type32;
+ dmu_objset_type_t type;
+ boolean_t is_insensitive = B_FALSE;
+
+ if (nvlist_lookup_int32(innvl, "type", &type32) != 0)
+ return (EINVAL);
+ type = type32;
+ (void) nvlist_lookup_nvlist(innvl, "props", &nvprops);
switch (type) {
-
case DMU_OST_ZFS:
cbfunc = zfs_create_cb;
break;
@@ -2964,230 +3118,290 @@
cbfunc = NULL;
break;
}
- if (strchr(zc->zc_name, '@') ||
- strchr(zc->zc_name, '%'))
+ if (strchr(fsname, '@') ||
+ strchr(fsname, '%'))
+ return (EINVAL);
+
+ zct.zct_props = nvprops;
+
+ if (cbfunc == NULL)
return (EINVAL);
- if (zc->zc_nvlist_src != NULL &&
- (error = get_nvlist(zc->zc_nvlist_src, zc->zc_nvlist_src_size,
- zc->zc_iflags, &nvprops)) != 0)
- return (error);
-
- zct.zct_zplprops = NULL;
- zct.zct_props = nvprops;
-
- if (zc->zc_value[0] != '\0') {
+ if (type == DMU_OST_ZVOL) {
+ uint64_t volsize, volblocksize;
+
+ if (nvprops == NULL)
+ return (EINVAL);
+ if (nvlist_lookup_uint64(nvprops,
+ zfs_prop_to_name(ZFS_PROP_VOLSIZE), &volsize) != 0)
+ return (EINVAL);
+
+ if ((error = nvlist_lookup_uint64(nvprops,
+ zfs_prop_to_name(ZFS_PROP_VOLBLOCKSIZE),
+ &volblocksize)) != 0 && error != ENOENT)
+ return (EINVAL);
+
+ if (error != 0)
+ volblocksize = zfs_prop_default_numeric(
+ ZFS_PROP_VOLBLOCKSIZE);
+
+ if ((error = zvol_check_volblocksize(
+ volblocksize)) != 0 ||
+ (error = zvol_check_volsize(volsize,
+ volblocksize)) != 0)
+ return (error);
+ } else if (type == DMU_OST_ZFS) {
+ int error;
+
/*
- * We're creating a clone of an existing snapshot.
+ * We have to have normalization and
+ * case-folding flags correct when we do the
+ * file system creation, so go figure them out
+ * now.
*/
- zc->zc_value[sizeof (zc->zc_value) - 1] = '\0';
- if (dataset_namecheck(zc->zc_value, NULL, NULL) != 0) {
- nvlist_free(nvprops);
- return (EINVAL);
- }
-
- error = dmu_objset_hold(zc->zc_value, FTAG, &clone);
- if (error) {
- nvlist_free(nvprops);
- return (error);
- }
-
- error = dmu_objset_clone(zc->zc_name, dmu_objset_ds(clone), 0);
- dmu_objset_rele(clone, FTAG);
- if (error) {
- nvlist_free(nvprops);
+ VERIFY(nvlist_alloc(&zct.zct_zplprops,
+ NV_UNIQUE_NAME, KM_SLEEP) == 0);
+ error = zfs_fill_zplprops(fsname, nvprops,
+ zct.zct_zplprops, &is_insensitive);
+ if (error != 0) {
+ nvlist_free(zct.zct_zplprops);
return (error);
}
- } else {
- boolean_t is_insensitive = B_FALSE;
-
- if (cbfunc == NULL) {
- nvlist_free(nvprops);
- return (EINVAL);
- }
-
- if (type == DMU_OST_ZVOL) {
- uint64_t volsize, volblocksize;
-
- if (nvprops == NULL ||
- nvlist_lookup_uint64(nvprops,
- zfs_prop_to_name(ZFS_PROP_VOLSIZE),
- &volsize) != 0) {
- nvlist_free(nvprops);
- return (EINVAL);
- }
-
- if ((error = nvlist_lookup_uint64(nvprops,
- zfs_prop_to_name(ZFS_PROP_VOLBLOCKSIZE),
- &volblocksize)) != 0 && error != ENOENT) {
- nvlist_free(nvprops);
- return (EINVAL);
- }
-
- if (error != 0)
- volblocksize = zfs_prop_default_numeric(
- ZFS_PROP_VOLBLOCKSIZE);
-
- if ((error = zvol_check_volblocksize(
- volblocksize)) != 0 ||
- (error = zvol_check_volsize(volsize,
- volblocksize)) != 0) {
- nvlist_free(nvprops);
- return (error);
- }
- } else if (type == DMU_OST_ZFS) {
- int error;
-
- /*
- * We have to have normalization and
- * case-folding flags correct when we do the
- * file system creation, so go figure them out
- * now.
- */
- VERIFY(nvlist_alloc(&zct.zct_zplprops,
- NV_UNIQUE_NAME, KM_SLEEP) == 0);
- error = zfs_fill_zplprops(zc->zc_name, nvprops,
- zct.zct_zplprops, &is_insensitive);
- if (error != 0) {
- nvlist_free(nvprops);
- nvlist_free(zct.zct_zplprops);
- return (error);
- }
- }
- error = dmu_objset_create(zc->zc_name, type,
- is_insensitive ? DS_FLAG_CI_DATASET : 0, cbfunc, &zct);
- nvlist_free(zct.zct_zplprops);
+ }
+
+ error = dmu_objset_create(fsname, type,
+ is_insensitive ? DS_FLAG_CI_DATASET : 0, cbfunc, &zct);
+ nvlist_free(zct.zct_zplprops);
+
+ /*
+ * It would be nice to do this atomically.
+ */
+ if (error == 0) {
+ error = zfs_set_prop_nvlist(fsname, ZPROP_SRC_LOCAL,
+ nvprops, outnvl);
+ if (error != 0)
+ (void) dmu_objset_destroy(fsname, B_FALSE);
}
+ return (error);
+}
+
+/*
+ * innvl: {
+ * "origin" -> name of origin snapshot
+ * (optional) "props" -> { prop -> value }
+ * }
+ *
+ * outnvl: propname -> error code (int32)
+ */
+static int
+zfs_ioc_clone(const char *fsname, nvlist_t *innvl, nvlist_t *outnvl)
+{
+ int error = 0;
+ nvlist_t *nvprops = NULL;
+ char *origin_name;
+ dsl_dataset_t *origin;
+
+ if (nvlist_lookup_string(innvl, "origin", &origin_name) != 0)
+ return (EINVAL);
+ (void) nvlist_lookup_nvlist(innvl, "props", &nvprops);
+
+ if (strchr(fsname, '@') ||
+ strchr(fsname, '%'))
+ return (EINVAL);
+
+ if (dataset_namecheck(origin_name, NULL, NULL) != 0)
+ return (EINVAL);
+
+ error = dsl_dataset_hold(origin_name, FTAG, &origin);
+ if (error)
+ return (error);
+
+ error = dmu_objset_clone(fsname, origin, 0);
+ dsl_dataset_rele(origin, FTAG);
+ if (error)
+ return (error);
/*
* It would be nice to do this atomically.
*/
if (error == 0) {
- error = zfs_set_prop_nvlist(zc->zc_name, ZPROP_SRC_LOCAL,
- nvprops, NULL);
+ error = zfs_set_prop_nvlist(fsname, ZPROP_SRC_LOCAL,
+ nvprops, outnvl);
if (error != 0)
- (void) dmu_objset_destroy(zc->zc_name, B_FALSE);
+ (void) dmu_objset_destroy(fsname, B_FALSE);
}
- nvlist_free(nvprops);
+ return (error);
+}
+
+/*
+ * innvl: {
+ * "snaps" -> { snapshot1, snapshot2 }
+ * (optional) "props" -> { prop -> value (string) }
+ * }
+ *
+ * outnvl: snapshot -> error code (int32)
+ *
+ */
+static int
+zfs_ioc_snapshot(const char *poolname, nvlist_t *innvl, nvlist_t *outnvl)
+{
+ nvlist_t *snaps;
+ nvlist_t *props = NULL;
+ int error, poollen;
+ nvpair_t *pair;
+
+ (void) nvlist_lookup_nvlist(innvl, "props", &props);
+ if ((error = zfs_check_userprops(poolname, props)) != 0)
+ return (error);
+
+ if (!nvlist_empty(props) &&
+ zfs_earlier_version(poolname, SPA_VERSION_SNAP_PROPS))
+ return (ENOTSUP);
+
+ if (nvlist_lookup_nvlist(innvl, "snaps", &snaps) != 0)
+ return (EINVAL);
+ poollen = strlen(poolname);
+ for (pair = nvlist_next_nvpair(snaps, NULL); pair != NULL;
+ pair = nvlist_next_nvpair(snaps, pair)) {
+ const char *name = nvpair_name(pair);
+ const char *cp = strchr(name, '@');
+
+ /*
+ * The snap name must contain an @, and the part after it must
+ * contain only valid characters.
+ */
+ if (cp == NULL || snapshot_namecheck(cp + 1, NULL, NULL) != 0)
+ return (EINVAL);
+
+ /*
+ * The snap must be in the specified pool.
+ */
+ if (strncmp(name, poolname, poollen) != 0 ||
+ (name[poollen] != '/' && name[poollen] != '@'))
+ return (EXDEV);
+
+ /* This must be the only snap of this fs. */
+ for (nvpair_t *pair2 = nvlist_next_nvpair(snaps, pair);
+ pair2 != NULL; pair2 = nvlist_next_nvpair(snaps, pair2)) {
+ if (strncmp(name, nvpair_name(pair2), cp - name + 1)
+ == 0) {
+ return (EXDEV);
+ }
+ }
+ }
+
+ error = dmu_objset_snapshot(snaps, props, outnvl);
return (error);
}
/*
- * inputs:
- * zc_name name of filesystem
- * zc_value short name of snapshot
- * zc_cookie recursive flag
- * zc_nvlist_src[_size] property list
- *
- * outputs:
- * zc_value short snapname (i.e. part after the '@')
+ * innvl: "message" -> string
*/
+/* ARGSUSED */
static int
-zfs_ioc_snapshot(zfs_cmd_t *zc)
+zfs_ioc_log_history(const char *unused, nvlist_t *innvl, nvlist_t *outnvl)
{
- nvlist_t *nvprops = NULL;
+ char *message;
+ spa_t *spa;
int error;
- boolean_t recursive = zc->zc_cookie;
-
- if (snapshot_namecheck(zc->zc_value, NULL, NULL) != 0)
+ char *poolname;
+
+ /*
+ * The poolname in the ioctl is not set, we get it from the TSD,
+ * which was set at the end of the last successful ioctl that allows
+ * logging. The secpolicy func already checked that it is set.
+ * Only one log ioctl is allowed after each successful ioctl, so
+ * we clear the TSD here.
+ */
+ poolname = tsd_get(zfs_allow_log_key);
+ (void) tsd_set(zfs_allow_log_key, NULL);
+ error = spa_open(poolname, &spa, FTAG);
+ strfree(poolname);
+ if (error != 0)
+ return (error);
+
+ if (nvlist_lookup_string(innvl, "message", &message) != 0) {
+ spa_close(spa, FTAG);
return (EINVAL);
-
- if (zc->zc_nvlist_src != NULL &&
- (error = get_nvlist(zc->zc_nvlist_src, zc->zc_nvlist_src_size,
- zc->zc_iflags, &nvprops)) != 0)
- return (error);
-
- error = zfs_check_userprops(zc->zc_name, nvprops);
- if (error)
- goto out;
-
- if (!nvlist_empty(nvprops) &&
- zfs_earlier_version(zc->zc_name, SPA_VERSION_SNAP_PROPS)) {
- error = ENOTSUP;
- goto out;
}
- error = dmu_objset_snapshot(zc->zc_name, zc->zc_value, NULL,
- nvprops, recursive, B_FALSE, -1);
-
-out:
- nvlist_free(nvprops);
+ if (spa_version(spa) < SPA_VERSION_ZPOOL_HISTORY) {
+ spa_close(spa, FTAG);
+ return (ENOTSUP);
+ }
+
+ error = spa_history_log(spa, message);
+ spa_close(spa, FTAG);
return (error);
}
+/* ARGSUSED */
int
zfs_unmount_snap(const char *name, void *arg)
{
- vfs_t *vfsp = NULL;
-
- if (arg) {
- char *snapname = arg;
- char *fullname = kmem_asprintf("%s@%s", name, snapname);
- vfsp = zfs_get_vfs(fullname);
- strfree(fullname);
- } else if (strchr(name, '@')) {
- vfsp = zfs_get_vfs(name);
+ vfs_t *vfsp;
+ int err;
+
+ if (strchr(name, '@') == NULL)
+ return (0);
+
+ vfsp = zfs_get_vfs(name);
+ if (vfsp == NULL)
+ return (0);
+
+ if ((err = vn_vfswlock(vfsp->vfs_vnodecovered)) != 0) {
+ VFS_RELE(vfsp);
+ return (err);
}
-
- if (vfsp) {
- /*
- * Always force the unmount for snapshots.
- */
- int flag = MS_FORCE;
- int err;
-
- if ((err = vn_vfswlock(vfsp->vfs_vnodecovered)) != 0) {
- VFS_RELE(vfsp);
- return (err);
- }
- VFS_RELE(vfsp);
- if ((err = dounmount(vfsp, flag, kcred)) != 0)
- return (err);
- }
- return (0);
+ VFS_RELE(vfsp);
+
+ /*
+ * Always force the unmount for snapshots.
+ */
+ return (dounmount(vfsp, MS_FORCE, kcred));
}
/*
- * inputs:
- * zc_name name of filesystem, snaps must be under it
- * zc_nvlist_src[_size] full names of snapshots to destroy
- * zc_defer_destroy mark for deferred destroy
+ * innvl: {
+ * "snaps" -> { snapshot1, snapshot2 }
+ * (optional boolean) "defer"
+ * }
*
- * outputs:
- * zc_name on failure, name of failed snapshot
+ * outnvl: snapshot -> error code (int32)
+ *
*/
static int
-zfs_ioc_destroy_snaps_nvl(zfs_cmd_t *zc)
+zfs_ioc_destroy_snaps(const char *poolname, nvlist_t *innvl, nvlist_t *outnvl)
{
- int err, len;
- nvlist_t *nvl;
+ int poollen;
+ nvlist_t *snaps;
nvpair_t *pair;
-
- if ((err = get_nvlist(zc->zc_nvlist_src, zc->zc_nvlist_src_size,
- zc->zc_iflags, &nvl)) != 0)
- return (err);
-
- len = strlen(zc->zc_name);
- for (pair = nvlist_next_nvpair(nvl, NULL); pair != NULL;
- pair = nvlist_next_nvpair(nvl, pair)) {
+ boolean_t defer;
+
+ if (nvlist_lookup_nvlist(innvl, "snaps", &snaps) != 0)
+ return (EINVAL);
+ defer = nvlist_exists(innvl, "defer");
+
+ poollen = strlen(poolname);
+ for (pair = nvlist_next_nvpair(snaps, NULL); pair != NULL;
+ pair = nvlist_next_nvpair(snaps, pair)) {
const char *name = nvpair_name(pair);
+
/*
- * The snap name must be underneath the zc_name. This ensures
- * that our permission checks were legitimate.
+ * The snap must be in the specified pool.
*/
- if (strncmp(zc->zc_name, name, len) != 0 ||
- (name[len] != '@' && name[len] != '/')) {
- nvlist_free(nvl);
- return (EINVAL);
- }
-
+ if (strncmp(name, poolname, poollen) != 0 ||
+ (name[poollen] != '/' && name[poollen] != '@'))
+ return (EXDEV);
+
+ /*
+ * Ignore failures to unmount; dmu_snapshots_destroy_nvl()
+ * will deal with this gracefully (by filling in outnvl).
+ */
(void) zfs_unmount_snap(name, NULL);
}
- err = dmu_snapshots_destroy_nvl(nvl, zc->zc_defer_destroy,
- zc->zc_name);
- nvlist_free(nvl);
- return (err);
+ return (dmu_snapshots_destroy_nvl(snaps, defer, outnvl));
}
/*
@@ -3491,7 +3705,7 @@
(void) strcpy(zc->zc_value, nvpair_name(pair));
if ((err = zfs_check_settable(dataset, pair, CRED())) != 0 ||
- (err = zfs_secpolicy_inherit(zc, CRED())) != 0) {
+ (err = zfs_secpolicy_inherit_prop(zc, NULL, CRED())) != 0) {
VERIFY(nvlist_remove_nvpair(props, pair) == 0);
VERIFY(nvlist_add_int32(errors,
zc->zc_value, err) == 0);
@@ -3699,8 +3913,6 @@
* dmu_recv_begin() succeeds.
*/
if (props) {
- nvlist_t *errlist;
-
if (dmu_objset_from_ds(drc.drc_logical_ds, &os) == 0) {
if (drc.drc_newfs) {
if (spa_version(os->os_spa) >=
@@ -3719,12 +3931,12 @@
}
(void) zfs_set_prop_nvlist(tofs, ZPROP_SRC_RECEIVED,
- props, &errlist);
- (void) nvlist_merge(errors, errlist, 0);
- nvlist_free(errlist);
+ props, errors);
}
- if (fit_error_list(zc, &errors) != 0 || put_nvlist(zc, errors) != 0) {
+ if (zc->zc_nvlist_dst_size != 0 &&
+ (nvlist_smush(errors, zc->zc_nvlist_dst_size) != 0 ||
+ put_nvlist(zc, errors) != 0)) {
/*
* Caller made zc->zc_nvlist_dst less than the minimum expected
* size or supplied an invalid address.
@@ -3856,15 +4068,13 @@
rw_enter(&dp->dp_config_rwlock, RW_READER);
error = dsl_dataset_hold_obj(dp, zc->zc_sendobj, FTAG, &ds);
rw_exit(&dp->dp_config_rwlock);
- if (error) {
- spa_close(spa, FTAG);
+ spa_close(spa, FTAG);
+ if (error)
return (error);
- }
error = dmu_objset_from_ds(ds, &tosnap);
if (error) {
dsl_dataset_rele(ds, FTAG);
- spa_close(spa, FTAG);
return (error);
}
@@ -3872,7 +4082,6 @@
rw_enter(&dp->dp_config_rwlock, RW_READER);
error = dsl_dataset_hold_obj(dp, zc->zc_fromobj, FTAG, &dsfrom);
rw_exit(&dp->dp_config_rwlock);
- spa_close(spa, FTAG);
if (error) {
dsl_dataset_rele(ds, FTAG);
return (error);
@@ -3883,12 +4092,37 @@
dsl_dataset_rele(ds, FTAG);
return (error);
}
- } else {
- spa_close(spa, FTAG);
+ }
+
+ if (zc->zc_obj) {
+ dsl_pool_t *dp = ds->ds_dir->dd_pool;
+
+ if (fromsnap != NULL) {
+ dsl_dataset_rele(dsfrom, FTAG);
+ dsl_dataset_rele(ds, FTAG);
+ return (EINVAL);
+ }
+
+ if (dsl_dir_is_clone(ds->ds_dir)) {
+ rw_enter(&dp->dp_config_rwlock, RW_READER);
+ error = dsl_dataset_hold_obj(dp,
+ ds->ds_dir->dd_phys->dd_origin_obj, FTAG, &dsfrom);
+ rw_exit(&dp->dp_config_rwlock);
+ if (error) {
+ dsl_dataset_rele(ds, FTAG);
+ return (error);
+ }
+ error = dmu_objset_from_ds(dsfrom, &fromsnap);
+ if (error) {
+ dsl_dataset_rele(dsfrom, FTAG);
+ dsl_dataset_rele(ds, FTAG);
+ return (error);
+ }
+ }
}
if (estimate) {
- error = dmu_send_estimate(tosnap, fromsnap, zc->zc_obj,
+ error = dmu_send_estimate(tosnap, fromsnap,
&zc->zc_objset_type);
} else {
file_t *fp = getf(zc->zc_cookie);
@@ -3900,7 +4134,7 @@
}
off = fp->f_offset;
- error = dmu_send(tosnap, fromsnap, zc->zc_obj,
+ error = dmu_send(tosnap, fromsnap,
zc->zc_cookie, fp->f_vnode, &off);
if (VOP_SEEK(fp->f_vnode, fp->f_offset, &off, NULL) == 0)
@@ -4414,6 +4648,7 @@
* zc_cleanup_fd cleanup-on-exit file descriptor for calling process
*
* outputs:
+ * zc_value short name of new snapshot
*/
static int
zfs_ioc_tmp_snapshot(zfs_cmd_t *zc)
@@ -4421,22 +4656,21 @@
char *snap_name;
int error;
- snap_name = kmem_asprintf("%s-%016llx", zc->zc_value,
+ snap_name = kmem_asprintf("%s@%s-%016llx", zc->zc_name, zc->zc_value,
(u_longlong_t)ddi_get_lbolt64());
- if (strlen(snap_name) >= MAXNAMELEN) {
+ if (strlen(snap_name) >= MAXPATHLEN) {
strfree(snap_name);
return (E2BIG);
}
- error = dmu_objset_snapshot(zc->zc_name, snap_name, snap_name,
- NULL, B_FALSE, B_TRUE, zc->zc_cleanup_fd);
+ error = dmu_objset_snapshot_tmp(snap_name, "%temp", zc->zc_cleanup_fd);
if (error != 0) {
strfree(snap_name);
return (error);
}
- (void) strcpy(zc->zc_value, snap_name);
+ (void) strcpy(zc->zc_value, strchr(snap_name, '@') + 1);
strfree(snap_name);
return (0);
}
@@ -4790,172 +5024,427 @@
dsl_dataset_rele(new, FTAG);
return (error);
}
-
/*
- * inputs:
- * zc_name full name of last snapshot
- * zc_value full name of first snapshot
+ * innvl: {
+ * "firstsnap" -> snapshot name
+ * }
*
- * outputs:
- * zc_cookie space in bytes
- * zc_objset_type compressed space in bytes
- * zc_perm_action uncompressed space in bytes
+ * outnvl: {
+ * "used" -> space in bytes
+ * "compressed" -> compressed space in bytes
+ * "uncompressed" -> uncompressed space in bytes
+ * }
*/
static int
-zfs_ioc_space_snaps(zfs_cmd_t *zc)
+zfs_ioc_space_snaps(const char *lastsnap, nvlist_t *innvl, nvlist_t *outnvl)
{
int error;
dsl_dataset_t *new, *old;
-
- error = dsl_dataset_hold(zc->zc_name, FTAG, &new);
+ char *firstsnap;
+ uint64_t used, comp, uncomp;
+
+ if (nvlist_lookup_string(innvl, "firstsnap", &firstsnap) != 0)
+ return (EINVAL);
+
+ error = dsl_dataset_hold(lastsnap, FTAG, &new);
if (error != 0)
return (error);
- error = dsl_dataset_hold(zc->zc_value, FTAG, &old);
+ error = dsl_dataset_hold(firstsnap, FTAG, &old);
if (error != 0) {
dsl_dataset_rele(new, FTAG);
return (error);
}
- error = dsl_dataset_space_wouldfree(old, new, &zc->zc_cookie,
- &zc->zc_objset_type, &zc->zc_perm_action);
+ error = dsl_dataset_space_wouldfree(old, new, &used, &comp, &uncomp);
dsl_dataset_rele(old, FTAG);
dsl_dataset_rele(new, FTAG);
+ fnvlist_add_uint64(outnvl, "used", used);
+ fnvlist_add_uint64(outnvl, "compressed", comp);
+ fnvlist_add_uint64(outnvl, "uncompressed", uncomp);
+ return (error);
+}
+
+/*
+ * innvl: {
+ * "fd" -> file descriptor to write stream to (int32)
+ * (optional) "fromsnap" -> full snap name to send an incremental from
+ * }
+ *
+ * outnvl is unused
+ */
+/* ARGSUSED */
+static int
+zfs_ioc_send_new(const char *snapname, nvlist_t *innvl, nvlist_t *outnvl)
+{
+ objset_t *fromsnap = NULL;
+ objset_t *tosnap;
+ int error;
+ offset_t off;
+ char *fromname;
+ int fd;
+
+ error = nvlist_lookup_int32(innvl, "fd", &fd);
+ if (error != 0)
+ return (EINVAL);
+
+ error = dmu_objset_hold(snapname, FTAG, &tosnap);
+ if (error)
+ return (error);
+
+ error = nvlist_lookup_string(innvl, "fromsnap", &fromname);
+ if (error == 0) {
+ error = dmu_objset_hold(fromname, FTAG, &fromsnap);
+ if (error) {
+ dmu_objset_rele(tosnap, FTAG);
+ return (error);
+ }
+ }
+
+ file_t *fp = getf(fd);
+ if (fp == NULL) {
+ dmu_objset_rele(tosnap, FTAG);
+ if (fromsnap != NULL)
+ dmu_objset_rele(fromsnap, FTAG);
+ return (EBADF);
+ }
+
+ off = fp->f_offset;
+ error = dmu_send(tosnap, fromsnap, fd, fp->f_vnode, &off);
+
+ if (VOP_SEEK(fp->f_vnode, fp->f_offset, &off, NULL) == 0)
+ fp->f_offset = off;
+ releasef(fd);
+ if (fromsnap != NULL)
+ dmu_objset_rele(fromsnap, FTAG);
+ dmu_objset_rele(tosnap, FTAG);
return (error);
}
/*
- * pool create, destroy, and export don't log the history as part of
- * zfsdev_ioctl, but rather zfs_ioc_pool_create, and zfs_ioc_pool_export
- * do the logging of those commands.
+ * Determine approximately how large a zfs send stream will be -- the number
+ * of bytes that will be written to the fd supplied to zfs_ioc_send_new().
+ *
+ * innvl: {
+ * (optional) "fromsnap" -> full snap name to send an incremental from
+ * }
+ *
+ * outnvl: {
+ * "space" -> bytes of space (uint64)
+ * }
+ */
+static int
+zfs_ioc_send_space(const char *snapname, nvlist_t *innvl, nvlist_t *outnvl)
+{
+ objset_t *fromsnap = NULL;
+ objset_t *tosnap;
+ int error;
+ char *fromname;
+ uint64_t space;
+
+ error = dmu_objset_hold(snapname, FTAG, &tosnap);
+ if (error)
+ return (error);
+
+ error = nvlist_lookup_string(innvl, "fromsnap", &fromname);
+ if (error == 0) {
+ error = dmu_objset_hold(fromname, FTAG, &fromsnap);
+ if (error) {
+ dmu_objset_rele(tosnap, FTAG);
+ return (error);
+ }
+ }
+
+ error = dmu_send_estimate(tosnap, fromsnap, &space);
+ fnvlist_add_uint64(outnvl, "space", space);
+
+ if (fromsnap != NULL)
+ dmu_objset_rele(fromsnap, FTAG);
+ dmu_objset_rele(tosnap, FTAG);
+ return (error);
+}
+
+
+static zfs_ioc_vec_t zfs_ioc_vec[ZFS_IOC_LAST - ZFS_IOC_FIRST];
+
+static void
+zfs_ioctl_register_legacy(zfs_ioc_t ioc, zfs_ioc_legacy_func_t *func,
+ zfs_secpolicy_func_t *secpolicy, zfs_ioc_namecheck_t namecheck,
+ boolean_t log_history, zfs_ioc_poolcheck_t pool_check)
+{
+ zfs_ioc_vec_t *vec = &zfs_ioc_vec[ioc - ZFS_IOC_FIRST];
+
+ ASSERT3U(ioc, >=, ZFS_IOC_FIRST);
+ ASSERT3U(ioc, <, ZFS_IOC_LAST);
+ ASSERT3P(vec->zvec_legacy_func, ==, NULL);
+ ASSERT3P(vec->zvec_func, ==, NULL);
+
+ vec->zvec_legacy_func = func;
+ vec->zvec_secpolicy = secpolicy;
+ vec->zvec_namecheck = namecheck;
+ vec->zvec_allow_log = log_history;
+ vec->zvec_pool_check = pool_check;
+}
+
+/*
+ * See the block comment at the beginning of this file for details on
+ * each argument to this function.
*/
-static zfs_ioc_vec_t zfs_ioc_vec[] = {
- { zfs_ioc_pool_create, zfs_secpolicy_config, POOL_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_pool_destroy, zfs_secpolicy_config, POOL_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_pool_import, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_NONE },
- { zfs_ioc_pool_export, zfs_secpolicy_config, POOL_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_pool_configs, zfs_secpolicy_none, NO_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_pool_stats, zfs_secpolicy_read, POOL_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_pool_tryimport, zfs_secpolicy_config, NO_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_pool_scan, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_pool_freeze, zfs_secpolicy_config, NO_NAME, B_FALSE,
- POOL_CHECK_READONLY },
- { zfs_ioc_pool_upgrade, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_pool_get_history, zfs_secpolicy_config, POOL_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_vdev_add, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_vdev_remove, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_vdev_set_state, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_vdev_attach, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_vdev_detach, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_vdev_setpath, zfs_secpolicy_config, POOL_NAME, B_FALSE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_vdev_setfru, zfs_secpolicy_config, POOL_NAME, B_FALSE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_objset_stats, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_SUSPENDED },
- { zfs_ioc_objset_zplprops, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_dataset_list_next, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_SUSPENDED },
- { zfs_ioc_snapshot_list_next, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_SUSPENDED },
- { zfs_ioc_set_prop, zfs_secpolicy_none, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_create, zfs_secpolicy_create, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_destroy, zfs_secpolicy_destroy, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_rollback, zfs_secpolicy_rollback, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_rename, zfs_secpolicy_rename, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_recv, zfs_secpolicy_receive, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_send, zfs_secpolicy_send, DATASET_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_inject_fault, zfs_secpolicy_inject, NO_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_clear_fault, zfs_secpolicy_inject, NO_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_inject_list_next, zfs_secpolicy_inject, NO_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_error_log, zfs_secpolicy_inject, POOL_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_clear, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_NONE },
- { zfs_ioc_promote, zfs_secpolicy_promote, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_snapshot, zfs_secpolicy_snapshot, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_dsobj_to_dsname, zfs_secpolicy_diff, POOL_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_obj_to_path, zfs_secpolicy_diff, DATASET_NAME, B_FALSE,
- POOL_CHECK_SUSPENDED },
- { zfs_ioc_pool_set_props, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_pool_get_props, zfs_secpolicy_read, POOL_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_set_fsacl, zfs_secpolicy_fsacl, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_get_fsacl, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_share, zfs_secpolicy_share, DATASET_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_inherit_prop, zfs_secpolicy_inherit, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_smb_acl, zfs_secpolicy_smb_acl, DATASET_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_userspace_one, zfs_secpolicy_userspace_one, DATASET_NAME,
- B_FALSE, POOL_CHECK_NONE },
- { zfs_ioc_userspace_many, zfs_secpolicy_userspace_many, DATASET_NAME,
- B_FALSE, POOL_CHECK_NONE },
- { zfs_ioc_userspace_upgrade, zfs_secpolicy_userspace_upgrade,
- DATASET_NAME, B_FALSE, POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_hold, zfs_secpolicy_hold, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_release, zfs_secpolicy_release, DATASET_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_get_holds, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_SUSPENDED },
- { zfs_ioc_objset_recvd_props, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_vdev_split, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_next_obj, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_diff, zfs_secpolicy_diff, DATASET_NAME, B_FALSE,
- POOL_CHECK_NONE },
- { zfs_ioc_tmp_snapshot, zfs_secpolicy_tmp_snapshot, DATASET_NAME,
- B_FALSE, POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_obj_to_stats, zfs_secpolicy_diff, DATASET_NAME, B_FALSE,
- POOL_CHECK_SUSPENDED },
- { zfs_ioc_space_written, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_SUSPENDED },
- { zfs_ioc_space_snaps, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_SUSPENDED },
- { zfs_ioc_destroy_snaps_nvl, zfs_secpolicy_destroy_recursive,
- DATASET_NAME, B_TRUE, POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_pool_reguid, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY },
- { zfs_ioc_pool_reopen, zfs_secpolicy_config, POOL_NAME, B_TRUE,
- POOL_CHECK_SUSPENDED },
- { zfs_ioc_send_progress, zfs_secpolicy_read, DATASET_NAME, B_FALSE,
- POOL_CHECK_NONE }
-};
+static void
+zfs_ioctl_register(const char *name, zfs_ioc_t ioc, zfs_ioc_func_t *func,
+ zfs_secpolicy_func_t *secpolicy, zfs_ioc_namecheck_t namecheck,
+ zfs_ioc_poolcheck_t pool_check, boolean_t smush_outnvlist,
+ boolean_t allow_log)
+{
+ zfs_ioc_vec_t *vec = &zfs_ioc_vec[ioc - ZFS_IOC_FIRST];
+
+ ASSERT3U(ioc, >=, ZFS_IOC_FIRST);
+ ASSERT3U(ioc, <, ZFS_IOC_LAST);
+ ASSERT3P(vec->zvec_legacy_func, ==, NULL);
+ ASSERT3P(vec->zvec_func, ==, NULL);
+
+ /* if we are logging, the name must be valid */
+ ASSERT(!allow_log || namecheck != NO_NAME);
+
+ vec->zvec_name = name;
+ vec->zvec_func = func;
+ vec->zvec_secpolicy = secpolicy;
+ vec->zvec_namecheck = namecheck;
+ vec->zvec_pool_check = pool_check;
+ vec->zvec_smush_outnvlist = smush_outnvlist;
+ vec->zvec_allow_log = allow_log;
+}
+
+static void
+zfs_ioctl_register_pool(zfs_ioc_t ioc, zfs_ioc_legacy_func_t *func,
+ zfs_secpolicy_func_t *secpolicy, boolean_t log_history,
+ zfs_ioc_poolcheck_t pool_check)
+{
+ zfs_ioctl_register_legacy(ioc, func, secpolicy,
+ POOL_NAME, log_history, pool_check);
+}
+
+static void
+zfs_ioctl_register_dataset_nolog(zfs_ioc_t ioc, zfs_ioc_legacy_func_t *func,
+ zfs_secpolicy_func_t *secpolicy, zfs_ioc_poolcheck_t pool_check)
+{
+ zfs_ioctl_register_legacy(ioc, func, secpolicy,
+ DATASET_NAME, B_FALSE, pool_check);
+}
+
+static void
+zfs_ioctl_register_pool_modify(zfs_ioc_t ioc, zfs_ioc_legacy_func_t *func)
+{
+ zfs_ioctl_register_legacy(ioc, func, zfs_secpolicy_config,
+ POOL_NAME, B_TRUE, POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY);
+}
+
+static void
+zfs_ioctl_register_pool_meta(zfs_ioc_t ioc, zfs_ioc_legacy_func_t *func,
+ zfs_secpolicy_func_t *secpolicy)
+{
+ zfs_ioctl_register_legacy(ioc, func, secpolicy,
+ NO_NAME, B_FALSE, POOL_CHECK_NONE);
+}
+
+static void
+zfs_ioctl_register_dataset_read_secpolicy(zfs_ioc_t ioc,
+ zfs_ioc_legacy_func_t *func, zfs_secpolicy_func_t *secpolicy)
+{
+ zfs_ioctl_register_legacy(ioc, func, secpolicy,
+ DATASET_NAME, B_FALSE, POOL_CHECK_SUSPENDED);
+}
+
+static void
+zfs_ioctl_register_dataset_read(zfs_ioc_t ioc, zfs_ioc_legacy_func_t *func)
+{
+ zfs_ioctl_register_dataset_read_secpolicy(ioc, func,
+ zfs_secpolicy_read);
+}
+
+static void
+zfs_ioctl_register_dataset_modify(zfs_ioc_t ioc, zfs_ioc_legacy_func_t *func,
+ zfs_secpolicy_func_t *secpolicy)
+{
+ zfs_ioctl_register_legacy(ioc, func, secpolicy,
+ DATASET_NAME, B_TRUE, POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY);
+}
+
+static void
+zfs_ioctl_init(void)
+{
+ zfs_ioctl_register("snapshot", ZFS_IOC_SNAPSHOT,
+ zfs_ioc_snapshot, zfs_secpolicy_snapshot, POOL_NAME,
+ POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY, B_TRUE, B_TRUE);
+
+ zfs_ioctl_register("log_history", ZFS_IOC_LOG_HISTORY,
+ zfs_ioc_log_history, zfs_secpolicy_log_history, NO_NAME,
+ POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY, B_FALSE, B_FALSE);
+
+ zfs_ioctl_register("space_snaps", ZFS_IOC_SPACE_SNAPS,
+ zfs_ioc_space_snaps, zfs_secpolicy_read, DATASET_NAME,
+ POOL_CHECK_SUSPENDED, B_FALSE, B_FALSE);
+
+ zfs_ioctl_register("send", ZFS_IOC_SEND_NEW,
+ zfs_ioc_send_new, zfs_secpolicy_send_new, DATASET_NAME,
+ POOL_CHECK_SUSPENDED, B_FALSE, B_FALSE);
+
+ zfs_ioctl_register("send_space", ZFS_IOC_SEND_SPACE,
+ zfs_ioc_send_space, zfs_secpolicy_read, DATASET_NAME,
+ POOL_CHECK_SUSPENDED, B_FALSE, B_FALSE);
+
+ zfs_ioctl_register("create", ZFS_IOC_CREATE,
+ zfs_ioc_create, zfs_secpolicy_create_clone, DATASET_NAME,
+ POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY, B_TRUE, B_TRUE);
+
+ zfs_ioctl_register("clone", ZFS_IOC_CLONE,
+ zfs_ioc_clone, zfs_secpolicy_create_clone, DATASET_NAME,
+ POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY, B_TRUE, B_TRUE);
+
+ zfs_ioctl_register("destroy_snaps", ZFS_IOC_DESTROY_SNAPS,
+ zfs_ioc_destroy_snaps, zfs_secpolicy_destroy_snaps, POOL_NAME,
+ POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY, B_TRUE, B_TRUE);
+
+ /* IOCTLS that use the legacy function signature */
+
+ zfs_ioctl_register_legacy(ZFS_IOC_POOL_FREEZE, zfs_ioc_pool_freeze,
+ zfs_secpolicy_config, NO_NAME, B_FALSE, POOL_CHECK_READONLY);
+
+ zfs_ioctl_register_pool(ZFS_IOC_POOL_CREATE, zfs_ioc_pool_create,
+ zfs_secpolicy_config, B_TRUE, POOL_CHECK_NONE);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_POOL_SCAN,
+ zfs_ioc_pool_scan);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_POOL_UPGRADE,
+ zfs_ioc_pool_upgrade);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_VDEV_ADD,
+ zfs_ioc_vdev_add);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_VDEV_REMOVE,
+ zfs_ioc_vdev_remove);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_VDEV_SET_STATE,
+ zfs_ioc_vdev_set_state);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_VDEV_ATTACH,
+ zfs_ioc_vdev_attach);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_VDEV_DETACH,
+ zfs_ioc_vdev_detach);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_VDEV_SETPATH,
+ zfs_ioc_vdev_setpath);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_VDEV_SETFRU,
+ zfs_ioc_vdev_setfru);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_POOL_SET_PROPS,
+ zfs_ioc_pool_set_props);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_VDEV_SPLIT,
+ zfs_ioc_vdev_split);
+ zfs_ioctl_register_pool_modify(ZFS_IOC_POOL_REGUID,
+ zfs_ioc_pool_reguid);
+
+ zfs_ioctl_register_pool_meta(ZFS_IOC_POOL_CONFIGS,
+ zfs_ioc_pool_configs, zfs_secpolicy_none);
+ zfs_ioctl_register_pool_meta(ZFS_IOC_POOL_TRYIMPORT,
+ zfs_ioc_pool_tryimport, zfs_secpolicy_config);
+ zfs_ioctl_register_pool_meta(ZFS_IOC_INJECT_FAULT,
+ zfs_ioc_inject_fault, zfs_secpolicy_inject);
+ zfs_ioctl_register_pool_meta(ZFS_IOC_CLEAR_FAULT,
+ zfs_ioc_clear_fault, zfs_secpolicy_inject);
+ zfs_ioctl_register_pool_meta(ZFS_IOC_INJECT_LIST_NEXT,
+ zfs_ioc_inject_list_next, zfs_secpolicy_inject);
+
+ /*
+ * pool destroy, and export don't log the history as part of
+ * zfsdev_ioctl, but rather zfs_ioc_pool_export
+ * does the logging of those commands.
+ */
+ zfs_ioctl_register_pool(ZFS_IOC_POOL_DESTROY, zfs_ioc_pool_destroy,
+ zfs_secpolicy_config, B_FALSE, POOL_CHECK_NONE);
+ zfs_ioctl_register_pool(ZFS_IOC_POOL_EXPORT, zfs_ioc_pool_export,
+ zfs_secpolicy_config, B_FALSE, POOL_CHECK_NONE);
+
+ zfs_ioctl_register_pool(ZFS_IOC_POOL_STATS, zfs_ioc_pool_stats,
+ zfs_secpolicy_read, B_FALSE, POOL_CHECK_NONE);
+ zfs_ioctl_register_pool(ZFS_IOC_POOL_GET_PROPS, zfs_ioc_pool_get_props,
+ zfs_secpolicy_read, B_FALSE, POOL_CHECK_NONE);
+
+ zfs_ioctl_register_pool(ZFS_IOC_ERROR_LOG, zfs_ioc_error_log,
+ zfs_secpolicy_inject, B_FALSE, POOL_CHECK_SUSPENDED);
+ zfs_ioctl_register_pool(ZFS_IOC_DSOBJ_TO_DSNAME,
+ zfs_ioc_dsobj_to_dsname,
+ zfs_secpolicy_diff, B_FALSE, POOL_CHECK_SUSPENDED);
+ zfs_ioctl_register_pool(ZFS_IOC_POOL_GET_HISTORY,
+ zfs_ioc_pool_get_history,
+ zfs_secpolicy_config, B_FALSE, POOL_CHECK_SUSPENDED);
+
+ zfs_ioctl_register_pool(ZFS_IOC_POOL_IMPORT, zfs_ioc_pool_import,
+ zfs_secpolicy_config, B_TRUE, POOL_CHECK_NONE);
+
+ zfs_ioctl_register_pool(ZFS_IOC_CLEAR, zfs_ioc_clear,
+ zfs_secpolicy_config, B_TRUE, POOL_CHECK_SUSPENDED);
+ zfs_ioctl_register_pool(ZFS_IOC_POOL_REOPEN, zfs_ioc_pool_reopen,
+ zfs_secpolicy_config, B_TRUE, POOL_CHECK_SUSPENDED);
+
+ zfs_ioctl_register_dataset_read(ZFS_IOC_SPACE_WRITTEN,
+ zfs_ioc_space_written);
+ zfs_ioctl_register_dataset_read(ZFS_IOC_GET_HOLDS,
+ zfs_ioc_get_holds);
+ zfs_ioctl_register_dataset_read(ZFS_IOC_OBJSET_RECVD_PROPS,
+ zfs_ioc_objset_recvd_props);
+ zfs_ioctl_register_dataset_read(ZFS_IOC_NEXT_OBJ,
+ zfs_ioc_next_obj);
+ zfs_ioctl_register_dataset_read(ZFS_IOC_GET_FSACL,
+ zfs_ioc_get_fsacl);
+ zfs_ioctl_register_dataset_read(ZFS_IOC_OBJSET_STATS,
+ zfs_ioc_objset_stats);
+ zfs_ioctl_register_dataset_read(ZFS_IOC_OBJSET_ZPLPROPS,
+ zfs_ioc_objset_zplprops);
+ zfs_ioctl_register_dataset_read(ZFS_IOC_DATASET_LIST_NEXT,
+ zfs_ioc_dataset_list_next);
+ zfs_ioctl_register_dataset_read(ZFS_IOC_SNAPSHOT_LIST_NEXT,
+ zfs_ioc_snapshot_list_next);
+ zfs_ioctl_register_dataset_read(ZFS_IOC_SEND_PROGRESS,
+ zfs_ioc_send_progress);
+
+ zfs_ioctl_register_dataset_read_secpolicy(ZFS_IOC_DIFF,
+ zfs_ioc_diff, zfs_secpolicy_diff);
+ zfs_ioctl_register_dataset_read_secpolicy(ZFS_IOC_OBJ_TO_STATS,
+ zfs_ioc_obj_to_stats, zfs_secpolicy_diff);
+ zfs_ioctl_register_dataset_read_secpolicy(ZFS_IOC_OBJ_TO_PATH,
+ zfs_ioc_obj_to_path, zfs_secpolicy_diff);
+ zfs_ioctl_register_dataset_read_secpolicy(ZFS_IOC_USERSPACE_ONE,
+ zfs_ioc_userspace_one, zfs_secpolicy_userspace_one);
+ zfs_ioctl_register_dataset_read_secpolicy(ZFS_IOC_USERSPACE_MANY,
+ zfs_ioc_userspace_many, zfs_secpolicy_userspace_many);
+ zfs_ioctl_register_dataset_read_secpolicy(ZFS_IOC_SEND,
+ zfs_ioc_send, zfs_secpolicy_send);
+
+ zfs_ioctl_register_dataset_modify(ZFS_IOC_SET_PROP, zfs_ioc_set_prop,
+ zfs_secpolicy_none);
+ zfs_ioctl_register_dataset_modify(ZFS_IOC_DESTROY, zfs_ioc_destroy,
+ zfs_secpolicy_destroy);
+ zfs_ioctl_register_dataset_modify(ZFS_IOC_ROLLBACK, zfs_ioc_rollback,
+ zfs_secpolicy_rollback);
+ zfs_ioctl_register_dataset_modify(ZFS_IOC_RENAME, zfs_ioc_rename,
+ zfs_secpolicy_rename);
+ zfs_ioctl_register_dataset_modify(ZFS_IOC_RECV, zfs_ioc_recv,
+ zfs_secpolicy_recv);
+ zfs_ioctl_register_dataset_modify(ZFS_IOC_PROMOTE, zfs_ioc_promote,
+ zfs_secpolicy_promote);
+ zfs_ioctl_register_dataset_modify(ZFS_IOC_HOLD, zfs_ioc_hold,
+ zfs_secpolicy_hold);
+ zfs_ioctl_register_dataset_modify(ZFS_IOC_RELEASE, zfs_ioc_release,
+ zfs_secpolicy_release);
+ zfs_ioctl_register_dataset_modify(ZFS_IOC_INHERIT_PROP,
+ zfs_ioc_inherit_prop, zfs_secpolicy_inherit_prop);
+ zfs_ioctl_register_dataset_modify(ZFS_IOC_SET_FSACL, zfs_ioc_set_fsacl,
+ zfs_secpolicy_set_fsacl);
+
+ zfs_ioctl_register_dataset_nolog(ZFS_IOC_SHARE, zfs_ioc_share,
+ zfs_secpolicy_share, POOL_CHECK_NONE);
+ zfs_ioctl_register_dataset_nolog(ZFS_IOC_SMB_ACL, zfs_ioc_smb_acl,
+ zfs_secpolicy_smb_acl, POOL_CHECK_NONE);
+ zfs_ioctl_register_dataset_nolog(ZFS_IOC_USERSPACE_UPGRADE,
+ zfs_ioc_userspace_upgrade, zfs_secpolicy_userspace_upgrade,
+ POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY);
+ zfs_ioctl_register_dataset_nolog(ZFS_IOC_TMP_SNAPSHOT,
+ zfs_ioc_tmp_snapshot, zfs_secpolicy_tmp_snapshot,
+ POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY);
+}
int
pool_status_check(const char *name, zfs_ioc_namecheck_t type,
@@ -5092,67 +5581,145 @@
zfsdev_ioctl(dev_t dev, int cmd, intptr_t arg, int flag, cred_t *cr, int *rvalp)
{
zfs_cmd_t *zc;
- uint_t vec;
- int error, rc;
+ uint_t vecnum;
+ int error, rc, len;
minor_t minor = getminor(dev);
+ const zfs_ioc_vec_t *vec;
+ char *saved_poolname = NULL;
+ nvlist_t *innvl = NULL;
if (minor != 0 &&
zfsdev_get_soft_state(minor, ZSST_CTLDEV) == NULL)
return (zvol_ioctl(dev, cmd, arg, flag, cr, rvalp));
- vec = cmd - ZFS_IOC;
+ vecnum = cmd - ZFS_IOC_FIRST;
ASSERT3U(getmajor(dev), ==, ddi_driver_major(zfs_dip));
- if (vec >= sizeof (zfs_ioc_vec) / sizeof (zfs_ioc_vec[0]))
+ if (vecnum >= sizeof (zfs_ioc_vec) / sizeof (zfs_ioc_vec[0]))
return (EINVAL);
+ vec = &zfs_ioc_vec[vecnum];
zc = kmem_zalloc(sizeof (zfs_cmd_t), KM_SLEEP);
error = ddi_copyin((void *)arg, zc, sizeof (zfs_cmd_t), flag);
- if (error != 0)
+ if (error != 0) {
error = EFAULT;
-
- if ((error == 0) && !(flag & FKIOCTL))
- error = zfs_ioc_vec[vec].zvec_secpolicy(zc, cr);
+ goto out;
+ }
+
+ zc->zc_iflags = flag & FKIOCTL;
+ if (zc->zc_nvlist_src_size != 0) {
+ error = get_nvlist(zc->zc_nvlist_src, zc->zc_nvlist_src_size,
+ zc->zc_iflags, &innvl);
+ if (error != 0)
+ goto out;
+ }
/*
* Ensure that all pool/dataset names are valid before we pass down to
* the lower layers.
*/
- if (error == 0) {
- zc->zc_name[sizeof (zc->zc_name) - 1] = '\0';
- zc->zc_iflags = flag & FKIOCTL;
- switch (zfs_ioc_vec[vec].zvec_namecheck) {
- case POOL_NAME:
- if (pool_namecheck(zc->zc_name, NULL, NULL) != 0)
- error = EINVAL;
+ zc->zc_name[sizeof (zc->zc_name) - 1] = '\0';
+ switch (vec->zvec_namecheck) {
+ case POOL_NAME:
+ if (pool_namecheck(zc->zc_name, NULL, NULL) != 0)
+ error = EINVAL;
+ else
error = pool_status_check(zc->zc_name,
- zfs_ioc_vec[vec].zvec_namecheck,
- zfs_ioc_vec[vec].zvec_pool_check);
- break;
-
- case DATASET_NAME:
- if (dataset_namecheck(zc->zc_name, NULL, NULL) != 0)
- error = EINVAL;
+ vec->zvec_namecheck, vec->zvec_pool_check);
+ break;
+
+ case DATASET_NAME:
+ if (dataset_namecheck(zc->zc_name, NULL, NULL) != 0)
+ error = EINVAL;
+ else
error = pool_status_check(zc->zc_name,
- zfs_ioc_vec[vec].zvec_namecheck,
- zfs_ioc_vec[vec].zvec_pool_check);
- break;
-
- case NO_NAME:
- break;
- }
+ vec->zvec_namecheck, vec->zvec_pool_check);
+ break;
+
+ case NO_NAME:
+ break;
}
- if (error == 0)
- error = zfs_ioc_vec[vec].zvec_func(zc);
-
+
+ if (error == 0 && !(flag & FKIOCTL))
+ error = vec->zvec_secpolicy(zc, innvl, cr);
+
+ if (error != 0)
+ goto out;
+
+ /* legacy ioctls can modify zc_name */
+ len = strcspn(zc->zc_name, "/@") + 1;
+ saved_poolname = kmem_alloc(len, KM_SLEEP);
+ (void) strlcpy(saved_poolname, zc->zc_name, len);
+
+ if (vec->zvec_func != NULL) {
+ nvlist_t *outnvl;
+ int puterror = 0;
+ spa_t *spa;
+ nvlist_t *lognv = NULL;
+
+ ASSERT(vec->zvec_legacy_func == NULL);
+
+ /*
+ * Add the innvl to the lognv before calling the func,
+ * in case the func changes the innvl.
+ */
+ if (vec->zvec_allow_log) {
+ lognv = fnvlist_alloc();
+ fnvlist_add_string(lognv, ZPOOL_HIST_IOCTL,
+ vec->zvec_name);
+ if (!nvlist_empty(innvl)) {
+ fnvlist_add_nvlist(lognv, ZPOOL_HIST_INPUT_NVL,
+ innvl);
+ }
+ }
+
+ outnvl = fnvlist_alloc();
+ error = vec->zvec_func(zc->zc_name, innvl, outnvl);
+
+ if (error == 0 && vec->zvec_allow_log &&
+ spa_open(zc->zc_name, &spa, FTAG) == 0) {
+ if (!nvlist_empty(outnvl)) {
+ fnvlist_add_nvlist(lognv, ZPOOL_HIST_OUTPUT_NVL,
+ outnvl);
+ }
+ (void) spa_history_log_nvl(spa, lognv);
+ spa_close(spa, FTAG);
+ }
+ fnvlist_free(lognv);
+
+ if (!nvlist_empty(outnvl) || zc->zc_nvlist_dst_size != 0) {
+ int smusherror = 0;
+ if (vec->zvec_smush_outnvlist) {
+ smusherror = nvlist_smush(outnvl,
+ zc->zc_nvlist_dst_size);
+ }
+ if (smusherror == 0)
+ puterror = put_nvlist(zc, outnvl);
+ }
+
+ if (puterror != 0)
+ error = puterror;
+
+ nvlist_free(outnvl);
+ } else {
+ error = vec->zvec_legacy_func(zc);
+ }
+
+out:
+ nvlist_free(innvl);
rc = ddi_copyout(zc, (void *)arg, sizeof (zfs_cmd_t), flag);
- if (error == 0) {
- if (rc != 0)
- error = EFAULT;
- if (zfs_ioc_vec[vec].zvec_his_log)
- zfs_log_history(zc);
+ if (error == 0 && rc != 0)
+ error = EFAULT;
+ if (error == 0 && vec->zvec_allow_log) {
+ char *s = tsd_get(zfs_allow_log_key);
+ if (s != NULL)
+ strfree(s);
+ (void) tsd_set(zfs_allow_log_key, saved_poolname);
+ } else {
+ if (saved_poolname != NULL)
+ strfree(saved_poolname);
}
kmem_free(zc, sizeof (zfs_cmd_t));
@@ -5268,9 +5835,12 @@
NULL
};
-
-uint_t zfs_fsyncer_key;
-extern uint_t rrw_tsd_key;
+static void
+zfs_allow_log_destroy(void *arg)
+{
+ char *poolname = arg;
+ strfree(poolname);
+}
int
_init(void)
@@ -5280,6 +5850,7 @@
spa_init(FREAD | FWRITE);
zfs_init();
zvol_init();
+ zfs_ioctl_init();
if ((error = mod_install(&modlinkage)) != 0) {
zvol_fini();
@@ -5289,7 +5860,8 @@
}
tsd_create(&zfs_fsyncer_key, NULL);
- tsd_create(&rrw_tsd_key, NULL);
+ tsd_create(&rrw_tsd_key, rrw_tsd_destroy);
+ tsd_create(&zfs_allow_log_key, zfs_allow_log_destroy);
error = ldi_ident_from_mod(&modlinkage, &zfs_li);
ASSERT(error == 0);
--- a/usr/src/uts/common/fs/zfs/zfs_vfsops.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/zfs_vfsops.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,7 @@
*/
/*
* Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
/* Portions Copyright 2010 Robert Milkowski */
@@ -2248,9 +2249,8 @@
sa_register_update_callback(os, zfs_sa_upgrade);
}
- spa_history_log_internal(LOG_DS_UPGRADE,
- dmu_objset_spa(os), tx, "oldver=%llu newver=%llu dataset = %llu",
- zfsvfs->z_version, newvers, dmu_objset_id(os));
+ spa_history_log_internal_ds(dmu_objset_ds(os), "upgrade", tx,
+ "from %llu to %llu", zfsvfs->z_version, newvers);
dmu_tx_commit(tx);
--- a/usr/src/uts/common/fs/zfs/zvol.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/fs/zfs/zvol.c Sun Aug 12 11:56:48 2012 +0100
@@ -24,6 +24,7 @@
* Portions Copyright 2010 Robert Milkowski
*
* Copyright 2011 Nexenta Systems, Inc. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
/*
@@ -135,7 +136,7 @@
int zvol_maxphys = DMU_MAX_ACCESS/2;
extern int zfs_set_prop_nvlist(const char *, zprop_source_t,
- nvlist_t *, nvlist_t **);
+ nvlist_t *, nvlist_t *);
static int zvol_remove_zv(zvol_state_t *);
static int zvol_get_data(void *arg, lr_write_t *lr, char *buf, zio_t *zio);
static int zvol_dumpify(zvol_state_t *zv);
@@ -1885,7 +1886,7 @@
if (zap_lookup(zv->zv_objset, ZVOL_ZAP_OBJ, ZVOL_DUMPSIZE,
8, 1, &dumpsize) != 0 || dumpsize != zv->zv_volsize) {
- boolean_t resize = (dumpsize > 0) ? B_TRUE : B_FALSE;
+ boolean_t resize = (dumpsize > 0);
if ((error = zvol_dump_init(zv, resize)) != 0) {
(void) zvol_dump_fini(zv);
--- a/usr/src/uts/common/io/atge/atge.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/atge/atge.h Sun Aug 12 11:56:48 2012 +0100
@@ -19,6 +19,8 @@
* CDDL HEADER END
*/
/*
+ * Copyright (c) 2012 Gary Mills
+ *
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
@@ -33,6 +35,7 @@
#include <sys/ethernet.h>
#include <sys/mac_provider.h>
#include "atge_l1e_reg.h"
+#include "atge_l1c_reg.h"
#define ATGE_PCI_REG_NUMBER 1
@@ -48,10 +51,20 @@
#define ATGE_FLAG_FASTETHER 0x0010
#define ATGE_FLAG_JUMBO 0x0020
#define ATGE_MII_CHECK 0x0040
+#define ATGE_FLAG_ASPM_MON 0x0080
+#define ATGE_FLAG_CMB_BUG 0x0100
+#define ATGE_FLAG_SMB_BUG 0x0200
+#define ATGE_FLAG_APS 0x1000
#define ATGE_CHIP_L1_DEV_ID 0x1048
#define ATGE_CHIP_L2_DEV_ID 0x2048
#define ATGE_CHIP_L1E_DEV_ID 0x1026
+#define ATGE_CHIP_L1CG_DEV_ID 0x1063
+#define ATGE_CHIP_L1CF_DEV_ID 0x1062
+#define ATGE_CHIP_AR8151V1_DEV_ID 0x1073
+#define ATGE_CHIP_AR8151V2_DEV_ID 0x1083
+#define ATGE_CHIP_AR8152V1_DEV_ID 0x2060
+#define ATGE_CHIP_AR8152V2_DEV_ID 0x2062
#define ATGE_PROMISC 0x001
#define ATGE_ALL_MULTICST 0x002
@@ -142,6 +155,8 @@
* General purpose macros.
*/
#define ATGE_MODEL(atgep) atgep->atge_model
+#define ATGE_VID(atgep) atgep->atge_vid
+#define ATGE_DID(atgep) atgep->atge_did
/*
* Different type of chip models.
@@ -150,6 +165,7 @@
ATGE_CHIP_L1 = 1,
ATGE_CHIP_L2,
ATGE_CHIP_L1E,
+ ATGE_CHIP_L1C,
} atge_model_t;
typedef struct atge_cards {
@@ -221,6 +237,20 @@
} atge_l1_data_t;
/*
+ * L1C specific private data.
+ */
+typedef struct atge_l1c_data {
+ atge_ring_t *atge_rx_ring;
+ atge_dma_t *atge_l1c_cmb;
+ atge_dma_t *atge_l1c_rr;
+ atge_dma_t *atge_l1c_smb;
+ int atge_l1c_rr_consumers;
+ uint32_t atge_l1c_intr_status;
+ uint32_t atge_l1c_rx_prod_cons;
+ uint32_t atge_l1c_tx_prod_cons;
+} atge_l1c_data_t;
+
+/*
* TX descriptor table is same with L1, L1E and L2E chips.
*/
#pragma pack(1)
@@ -257,6 +287,8 @@
dev_info_t *atge_dip;
char atge_name[8];
atge_model_t atge_model;
+ uint16_t atge_vid;
+ uint16_t atge_did;
int atge_chip_rev;
uint8_t atge_revid;
@@ -300,6 +332,8 @@
int atge_tx_resched;
int atge_mtu;
int atge_int_mod;
+ int atge_int_rx_mod; /* L1C */
+ int atge_int_tx_mod; /* L1C */
int atge_max_frame_size;
--- a/usr/src/uts/common/io/atge/atge_cmn_reg.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/atge/atge_cmn_reg.h Sun Aug 12 11:56:48 2012 +0100
@@ -19,9 +19,37 @@
* CDDL HEADER END
*/
/*
+ * Copyright (c) 2012 Gary Mills
+ *
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
+/*
+ * Copyright (c) 2009, Pyun YongHyeon <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
#ifndef _ATGE_CMN_REG_H
#define _ATGE_CMN_REG_H
@@ -43,15 +71,23 @@
#define ATGE_MASTER_CFG 0x1400
#define MASTER_RESET 0x00000001
-#define MASTER_MTIMER_ENB 0x00000002
#define MASTER_ITIMER_ENB 0x00000004 /* L1 */
-#define MASTER_IM_TX_TIMER_ENB 0x00000004 /* L1E */
#define MASTER_MANUAL_INT_ENB 0x00000008
-#define MASTER_IM_RX_TIMER_ENB 0x00000020
#define MASTER_INT_RDCLR 0x00000040
+#define MASTER_SA_TIMER_ENB 0x00000080
+#define MASTER_MTIMER_ENB 0x00000100
#define MASTER_LED_MODE 0x00000200
+#define MASTER_MANUAL_INTR_ENB 0x00000200
+#define MASTER_IM_TX_TIMER_ENB 0x00000400
+#define MASTER_IM_RX_TIMER_ENB 0x00000800
+#define MASTER_CLK_SEL_DIS 0x00001000
+#define MASTER_CLK_SWH_MODE 0x00002000
+#define MASTER_INTR_RD_CLR 0x00004000
#define MASTER_CHIP_REV_MASK 0x00FF0000
#define MASTER_CHIP_ID_MASK 0xFF000000
+#define MASTER_CHIP_ID_MASKXXX 0x7F000000 /* XXX */
+#define MASTER_OTP_SEL 0x80000000
+#define MASTER_TEST_MODE_SHIFT 2
#define MASTER_CHIP_REV_SHIFT 16
#define MASTER_CHIP_ID_SHIFT 24
@@ -67,6 +103,12 @@
#define IDLE_STATUS_SMB 0x00000040
#define IDLE_STATUS_CMB 0x00000080
+#define ATGE_SERDES_LOCK 0x1424
+#define SERDES_LOCK_DET 0x00000001
+#define SERDES_LOCK_DET_ENB 0x00000002
+#define SERDES_MAC_CLK_SLOWDOWN 0x00020000
+#define SERDES_PHY_CLK_SLOWDOWN 0x00040000
+
#define ATGE_MAC_CFG 0x1480
#define ATGE_CFG_TX_ENB 0x00000001
#define ATGE_CFG_RX_ENB 0x00000002
@@ -93,6 +135,9 @@
#define ATGE_CFG_ALLMULTI 0x02000000
#define ATGE_CFG_BCAST 0x04000000
#define ATGE_CFG_DBG 0x08000000
+#define ATGE_CFG_SINGLE_PAUSE_ENB 0x10000000
+#define ATGE_CFG_HASH_ALG_CRC32 0x20000000
+#define ATGE_CFG_SPEED_MODE_SW 0x40000000
#define ATGE_CFG_PREAMBLE_SHIFT 10
#define ATGE_CFG_PREAMBLE_DEFAULT 7
@@ -116,7 +161,7 @@
#define INTR_GPHY 0x00001000
#define INTR_RX_PKT 0x00010000
#define INTR_TX_PKT 0x00020000
-#define INTR_TX_DMA 0x00040000
+#define INTR_TX_DMA 0x00040000 /* L1 intr status */
#define INTR_MAC_RX 0x00400000
#define INTR_MAC_TX 0x00800000
#define INTR_UNDERRUN 0x01000000
@@ -133,9 +178,6 @@
#define INTR_RX_PKT2 0x00100000
#define INTR_RX_PKT3 0x00200000
-/* L1 intr status */
-#define INTR_TX_DMA 0x00040000
-
/*
* L1E specific errors. We keep it here since some errors are common for
* both L1 and L1E chip.
@@ -158,11 +200,6 @@
#define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256
/*
- * RXQ CFG register.
- */
-#define ATGE_RXQ_CFG 0x15A0
-
-/*
* Common registers for DMA CFG.
*/
#define ATGE_DMA_CFG 0x15C0
@@ -237,6 +274,113 @@
#define ATGE_DMA_BLOCK 0x1534
#define DMA_BLOCK_LOAD 0x00000001
+/* From Freebsd if_alcreg.h */
+/* 0x0000 - 0x02FF : PCIe configuration space */
+
+#define ATGE_PEX_UNC_ERR_SEV 0x10C
+#define PEX_UNC_ERR_SEV_TRN 0x00000001
+#define PEX_UNC_ERR_SEV_DLP 0x00000010
+#define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000
+#define PEX_UNC_ERR_SEV_FCP 0x00002000
+#define PEX_UNC_ERR_SEV_CPL_TO 0x00004000
+#define PEX_UNC_ERR_SEV_CA 0x00008000
+#define PEX_UNC_ERR_SEV_UC 0x00010000
+#define PEX_UNC_ERR_SEV_ROV 0x00020000
+#define PEX_UNC_ERR_SEV_MLFP 0x00040000
+#define PEX_UNC_ERR_SEV_ECRC 0x00080000
+#define PEX_UNC_ERR_SEV_UR 0x00100000
+
+#define ATGE_PCIE_PHYMISC 0x1000
+#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
+
+#define ATGE_PCIE_PHYMISC2 0x1004
+#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
+#define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
+#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
+#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
+
+#define ATGE_LTSSM_ID_CFG 0x12FC
+#define LTSSM_ID_WRO_ENB 0x00001000
+
+#define ATGE_SMB_STAT_TIMER 0x15C4
+#define SMB_STAT_TIMER_MASK 0x00FFFFFF
+#define SMB_STAT_TIMER_SHIFT 0
+
+#define ATGE_CMB_TD_THRESH 0x15C8
+#define CMB_TD_THRESH_MASK 0x0000FFFF
+#define CMB_TD_THRESH_SHIFT 0
+
+#define ATGE_CMB_TX_TIMER 0x15CC
+#define CMB_TX_TIMER_MASK 0x0000FFFF
+#define CMB_TX_TIMER_SHIFT 0
+
+#define ATGE_MBOX_RD0_PROD_IDX 0x15E0
+
+#define ATGE_MBOX_RD1_PROD_IDX 0x15E4
+
+#define ATGE_MBOX_RD2_PROD_IDX 0x15E8
+
+#define ATGE_MBOX_RD3_PROD_IDX 0x15EC
+
+#define ATGE_MBOX_RD_PROD_MASK 0x0000FFFF
+#define MBOX_RD_PROD_SHIFT 0
+
+#define ATGE_MBOX_TD_PROD_IDX 0x15F0
+#define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF
+#define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000
+#define MBOX_TD_PROD_HI_IDX_SHIFT 0
+#define MBOX_TD_PROD_LO_IDX_SHIFT 16
+
+#define ATGE_MBOX_TD_CONS_IDX 0x15F4
+#define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
+#define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
+#define MBOX_TD_CONS_HI_IDX_SHIFT 0
+#define MBOX_TD_CONS_LO_IDX_SHIFT 16
+
+#define ATGE_MBOX_RD01_CONS_IDX 0x15F8
+#define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
+#define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
+#define MBOX_RD0_CONS_IDX_SHIFT 0
+#define MBOX_RD1_CONS_IDX_SHIFT 16
+
+#define ATGE_MBOX_RD23_CONS_IDX 0x15FC
+#define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF
+#define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000
+#define MBOX_RD2_CONS_IDX_SHIFT 0
+#define MBOX_RD3_CONS_IDX_SHIFT 16
+
+#define ATGE_INTR_RETRIG_TIMER 0x1608
+#define INTR_RETRIG_TIMER_MASK 0x0000FFFF
+#define INTR_RETRIG_TIMER_SHIFT 0
+
+#define ATGE_HDS_CFG 0x160C
+#define HDS_CFG_ENB 0x00000001
+#define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00
+#define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000
+#define HDS_CFG_BACKFILLSIZE_SHIFT 8
+#define HDS_CFG_MAX_HDRSIZE_SHIFT 20
+
+/* AR813x/AR815x registers for MAC statistics */
+#define ATGE_RX_MIB_BASE 0x1700
+
+#define ATGE_TX_MIB_BASE 0x1760
+
+#define ATGE_CLK_GATING_CFG 0x1814
+#define CLK_GATING_DMAW_ENB 0x0001
+#define CLK_GATING_DMAR_ENB 0x0002
+#define CLK_GATING_TXQ_ENB 0x0004
+#define CLK_GATING_RXQ_ENB 0x0008
+#define CLK_GATING_TXMAC_ENB 0x0010
+#define CLK_GATING_RXMAC_ENB 0x0020
+
+#define ATGE_DEBUG_DATA0 0x1900
+
+#define ATGE_DEBUG_DATA1 0x1904
+
+#define ATGE_MII_DBG_ADDR 0x1D
+#define ATGE_MII_DBG_DATA 0x1E
+/* End Freebsd if_alcreg.h */
+
#define ATGE_MBOX 0x15F0
#define MBOX_RD_PROD_IDX_MASK 0x000007FF
#define MBOX_RRD_CONS_IDX_MASK 0x003FF800
@@ -349,8 +493,10 @@
#define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0
#define RXQ_FIFO_PAUSE_THRESH_HI_SHIFT 16
+/*
+ * RXQ CFG register.
+ */
#define ATGE_RXQ_CFG 0x15A0
-#define ATGE_TXQ_CFG 0x1580
#define RXQ_CFG_ALIGN_32 0x00000000
#define RXQ_CFG_ALIGN_64 0x00000001
#define RXQ_CFG_ALIGN_128 0x00000002
@@ -381,6 +527,81 @@
#define ATPHY_DBG_ADDR 0x1D
#define ATPHY_DBG_DATA 0x1E
+/* From Freebsd if_alcreg.h */
+#define MII_ANA_CFG0 0x00
+#define ANA_RESTART_CAL 0x0001
+#define ANA_MANUL_SWICH_ON_MASK 0x001E
+#define ANA_MAN_ENABLE 0x0020
+#define ANA_SEL_HSP 0x0040
+#define ANA_EN_HB 0x0080
+#define ANA_EN_HBIAS 0x0100
+#define ANA_OEN_125M 0x0200
+#define ANA_EN_LCKDT 0x0400
+#define ANA_LCKDT_PHY 0x0800
+#define ANA_AFE_MODE 0x1000
+#define ANA_VCO_SLOW 0x2000
+#define ANA_VCO_FAST 0x4000
+#define ANA_SEL_CLK125M_DSP 0x8000
+#define ANA_MANUL_SWICH_ON_SHIFT 1
+
+#define MII_ANA_CFG4 0x04
+#define ANA_IECHO_ADJ_MASK 0x0F
+#define ANA_IECHO_ADJ_3_MASK 0x000F
+#define ANA_IECHO_ADJ_2_MASK 0x00F0
+#define ANA_IECHO_ADJ_1_MASK 0x0F00
+#define ANA_IECHO_ADJ_0_MASK 0xF000
+#define ANA_IECHO_ADJ_3_SHIFT 0
+#define ANA_IECHO_ADJ_2_SHIFT 4
+#define ANA_IECHO_ADJ_1_SHIFT 8
+#define ANA_IECHO_ADJ_0_SHIFT 12
+
+#define MII_ANA_CFG5 0x05
+#define ANA_SERDES_CDR_BW_MASK 0x0003
+#define ANA_MS_PAD_DBG 0x0004
+#define ANA_SPEEDUP_DBG 0x0008
+#define ANA_SERDES_TH_LOS_MASK 0x0030
+#define ANA_SERDES_EN_DEEM 0x0040
+#define ANA_SERDES_TXELECIDLE 0x0080
+#define ANA_SERDES_BEACON 0x0100
+#define ANA_SERDES_HALFTXDR 0x0200
+#define ANA_SERDES_SEL_HSP 0x0400
+#define ANA_SERDES_EN_PLL 0x0800
+#define ANA_SERDES_EN 0x1000
+#define ANA_SERDES_EN_LCKDT 0x2000
+#define ANA_SERDES_CDR_BW_SHIFT 0
+#define ANA_SERDES_TH_LOS_SHIFT 4
+
+#define MII_ANA_CFG11 0x0B
+#define ANA_PS_HIB_EN 0x8000
+
+#define MII_ANA_CFG18 0x12
+#define ANA_TEST_MODE_10BT_01MASK 0x0003
+#define ANA_LOOP_SEL_10BT 0x0004
+#define ANA_RGMII_MODE_SW 0x0008
+#define ANA_EN_LONGECABLE 0x0010
+#define ANA_TEST_MODE_10BT_2 0x0020
+#define ANA_EN_10BT_IDLE 0x0400
+#define ANA_EN_MASK_TB 0x0800
+#define ANA_TRIGGER_SEL_TIMER_MASK 0x3000
+#define ANA_INTERVAL_SEL_TIMER_MASK 0xC000
+#define ANA_TEST_MODE_10BT_01SHIFT 0
+#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
+#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
+
+#define MII_ANA_CFG41 0x29
+#define ANA_TOP_PS_EN 0x8000
+
+#define MII_ANA_CFG54 0x36
+#define ANA_LONG_CABLE_TH_100_MASK 0x003F
+#define ANA_DESERVED 0x0040
+#define ANA_EN_LIT_CH 0x0080
+#define ANA_SHORT_CABLE_TH_100_MASK 0x3F00
+#define ANA_BP_BAD_LINK_ACCUM 0x4000
+#define ANA_BP_SMALL_BW 0x8000
+#define ANA_LONG_CABLE_TH_100_SHIFT 0
+#define ANA_SHORT_CABLE_TH_100_SHIFT 8
+/* End Freebsd if_alcreg.h */
+
#define ATGE_TD_EOP 0x00000001
#define ATGE_TD_BUFLEN_MASK 0x00003FFF
#define ATGE_TD_BUFLEN_SHIFT 0
--- a/usr/src/uts/common/io/atge/atge_l1_reg.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/atge/atge_l1_reg.h Sun Aug 12 11:56:48 2012 +0100
@@ -21,6 +21,7 @@
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
+ * Copyright (c) 2012 Gary Mills
*/
#ifndef _ATGE_L1_REG_H
@@ -181,7 +182,6 @@
/*
* PHY registers.
*/
-#define L1_CSMB_CTRL 0x15D0
#define PHY_CDTS_STAT_OK 0x0000
#define PHY_CDTS_STAT_SHORT 0x0100
#define PHY_CDTS_STAT_OPEN 0x0200
@@ -198,8 +198,6 @@
#define DMA_CFG_WR_BURST_MASK 0x07
#define DMA_CFG_WR_BURST_SHIFT 7
-#define RXQ_CFG_ENB 0x80000000
-
#define L1_RD_LEN_MASK 0x0000FFFF
#define L1_RD_LEN_SHIFT 0
@@ -219,8 +217,6 @@
#define RXQ_CFG_RD_BURST_MASK 0x000000FF
#define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00
#define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000
-#define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
-#define RXQ_CFG_ENB 0x80000000
#define RXQ_CFG_RD_BURST_SHIFT 0
#define RXQ_CFG_RD_BURST_DEFAULT 8
#define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8
@@ -228,16 +224,9 @@
#define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16
#define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1
-#define TXQ_CFG_ENB 0x00000020
-#define TXQ_CFG_ENHANCED_MODE 0x00000040
#define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00
-#define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
-#define TXQ_CFG_TPD_BURST_SHIFT 0
-#define TXQ_CFG_TPD_BURST_DEFAULT 4
#define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8
#define TXQ_CFG_TPD_FETCH_DEFAULT 16
-#define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
-#define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256
#define L1_TX_JUMBO_TPD_TH_IPG 0x1584
#define TX_JUMBO_TPD_TH_MASK 0x000007FF
@@ -264,22 +253,10 @@
#define CSMB_CTRL_CMB_ENB 0x00000004
#define CSMB_CTRL_SMB_ENB 0x00000008
-#define INTR_TX_FIFO_UNDERRUN 0x00000040
-#define INTR_RX_FIFO_OFLOW 0x00000008
-#define INTR_TX_DMA 0x00040000
#define INTR_RX_DMA 0x00080000
#define INTR_CMB_RX 0x00100000
#define INTR_CMB_TX 0x00200000
-#define INTR_MAC_RX 0x00400000
-#define INTR_MAC_TX 0x00800000
-#define INTR_UNDERRUN 0x01000000
-#define INTR_FRAME_ERROR 0x02000000
-#define INTR_FRAME_OK 0x04000000
-#define INTR_CSUM_ERROR 0x08000000
-#define INTR_PHY_LINK_DOWN 0x10000000
#define INTR_DIS_SMB 0x20000000
-#define INTR_DIS_DMA 0x40000000
-#define INTR_DIS_INT 0x80000000
#define L1_INTRS \
(INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/uts/common/io/atge/atge_l1c.c Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,1034 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 Gary Mills
+ *
+ * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
+/*
+ * Copyright (c) 2009, Pyun YongHyeon <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/stream.h>
+#include <sys/strsun.h>
+#include <sys/stat.h>
+#include <sys/modctl.h>
+#include <sys/ethernet.h>
+#include <sys/debug.h>
+#include <sys/conf.h>
+#include <sys/mii.h>
+#include <sys/miiregs.h>
+#include <sys/sysmacros.h>
+#include <sys/dditypes.h>
+#include <sys/ddi.h>
+#include <sys/sunddi.h>
+#include <sys/byteorder.h>
+#include <sys/note.h>
+#include <sys/vlan.h>
+#include <sys/stream.h>
+
+#include "atge.h"
+#include "atge_l1c_reg.h"
+#include "atge_cmn_reg.h"
+
+static ddi_dma_attr_t atge_l1c_dma_attr_tx_desc = {
+ DMA_ATTR_V0, /* dma_attr_version */
+ 0, /* dma_attr_addr_lo */
+ 0x0000ffffffffull, /* dma_attr_addr_hi */
+ 0x0000ffffffffull, /* dma_attr_count_max */
+ L1C_TX_RING_ALIGN, /* dma_attr_align */
+ 0x0000fffc, /* dma_attr_burstsizes */
+ 1, /* dma_attr_minxfer */
+ 0x0000ffffffffull, /* dma_attr_maxxfer */
+ 0x0000ffffffffull, /* dma_attr_seg */
+ 1, /* dma_attr_sgllen */
+ 1, /* dma_attr_granular */
+ 0 /* dma_attr_flags */
+};
+
+static ddi_dma_attr_t atge_l1c_dma_attr_rx_desc = {
+ DMA_ATTR_V0, /* dma_attr_version */
+ 0, /* dma_attr_addr_lo */
+ 0x0000ffffffffull, /* dma_attr_addr_hi */
+ 0x0000ffffffffull, /* dma_attr_count_max */
+ L1C_RX_RING_ALIGN, /* dma_attr_align */
+ 0x0000fffc, /* dma_attr_burstsizes */
+ 1, /* dma_attr_minxfer */
+ 0x0000ffffffffull, /* dma_attr_maxxfer */
+ 0x0000ffffffffull, /* dma_attr_seg */
+ 1, /* dma_attr_sgllen */
+ 1, /* dma_attr_granular */
+ 0 /* dma_attr_flags */
+};
+
+static ddi_dma_attr_t atge_l1c_dma_attr_cmb = {
+ DMA_ATTR_V0, /* dma_attr_version */
+ 0, /* dma_attr_addr_lo */
+ 0x0000ffffffffull, /* dma_attr_addr_hi */
+ 0x0000ffffffffull, /* dma_attr_count_max */
+ L1C_CMB_ALIGN, /* dma_attr_align */
+ 0x0000fffc, /* dma_attr_burstsizes */
+ 1, /* dma_attr_minxfer */
+ 0x0000ffffffffull, /* dma_attr_maxxfer */
+ 0x0000ffffffffull, /* dma_attr_seg */
+ 1, /* dma_attr_sgllen */
+ 1, /* dma_attr_granular */
+ 0 /* dma_attr_flags */
+};
+
+static ddi_dma_attr_t atge_l1c_dma_attr_smb = {
+ DMA_ATTR_V0, /* dma_attr_version */
+ 0, /* dma_attr_addr_lo */
+ 0x0000ffffffffull, /* dma_attr_addr_hi */
+ 0x0000ffffffffull, /* dma_attr_count_max */
+ L1C_SMB_ALIGN, /* dma_attr_align */
+ 0x0000fffc, /* dma_attr_burstsizes */
+ 1, /* dma_attr_minxfer */
+ 0x0000ffffffffull, /* dma_attr_maxxfer */
+ 0x0000ffffffffull, /* dma_attr_seg */
+ 1, /* dma_attr_sgllen */
+ 1, /* dma_attr_granular */
+ 0 /* dma_attr_flags */
+};
+
+static ddi_dma_attr_t atge_l1c_dma_attr_rr = {
+ DMA_ATTR_V0, /* dma_attr_version */
+ 0, /* dma_attr_addr_lo */
+ 0x0000ffffffffull, /* dma_attr_addr_hi */
+ 0x0000ffffffffull, /* dma_attr_count_max */
+ L1C_RR_RING_ALIGN, /* dma_attr_align */
+ 0x0000fffc, /* dma_attr_burstsizes */
+ 1, /* dma_attr_minxfer */
+ 0x0000ffffffffull, /* dma_attr_maxxfer */
+ 0x0000ffffffffull, /* dma_attr_seg */
+ 1, /* dma_attr_sgllen */
+ 1, /* dma_attr_granular */
+ 0 /* dma_attr_flags */
+};
+
+int
+atge_l1c_alloc_dma(atge_t *atgep)
+{
+ atge_l1c_data_t *l1c;
+ atge_dma_t *dma;
+ int err;
+
+ l1c = kmem_zalloc(sizeof (atge_l1c_data_t), KM_SLEEP);
+ atgep->atge_private_data = l1c;
+
+ /*
+ * Allocate TX ring descriptor.
+ */
+ atgep->atge_tx_buf_len = atgep->atge_mtu +
+ sizeof (struct ether_header) + VLAN_TAGSZ + ETHERFCSL;
+ atgep->atge_tx_ring = kmem_alloc(sizeof (atge_ring_t), KM_SLEEP);
+ atgep->atge_tx_ring->r_atge = atgep;
+ atgep->atge_tx_ring->r_desc_ring = NULL;
+ dma = atge_alloc_a_dma_blk(atgep, &atge_l1c_dma_attr_tx_desc,
+ ATGE_TX_RING_SZ, DDI_DMA_RDWR);
+ if (dma == NULL) {
+ atge_error(atgep->atge_dip, "DMA allocation failed for TX"
+ " desc ring");
+ return (DDI_FAILURE);
+ }
+ atgep->atge_tx_ring->r_desc_ring = dma;
+
+ /*
+ * Allocate DMA buffers for TX ring.
+ */
+ err = atge_alloc_buffers(atgep->atge_tx_ring, ATGE_TX_RING_CNT,
+ atgep->atge_tx_buf_len, DDI_DMA_WRITE);
+ if (err != DDI_SUCCESS) {
+ atge_error(atgep->atge_dip, "DMA allocation failed for"
+ " TX Ring");
+ return (err);
+ }
+
+ /*
+ * Allocate RX ring.
+ */
+ atgep->atge_rx_buf_len = atgep->atge_mtu +
+ sizeof (struct ether_header) + VLAN_TAGSZ + ETHERFCSL;
+ l1c->atge_rx_ring = kmem_alloc(sizeof (atge_ring_t), KM_SLEEP);
+ l1c->atge_rx_ring->r_atge = atgep;
+ l1c->atge_rx_ring->r_desc_ring = NULL;
+ dma = atge_alloc_a_dma_blk(atgep, &atge_l1c_dma_attr_rx_desc,
+ L1C_RX_RING_SZ, DDI_DMA_RDWR);
+ if (dma == NULL) {
+ atge_error(atgep->atge_dip, "DMA allocation failed"
+ " for RX Ring");
+ return (DDI_FAILURE);
+ }
+ l1c->atge_rx_ring->r_desc_ring = dma;
+
+ /*
+ * Allocate DMA buffers for RX ring.
+ */
+ err = atge_alloc_buffers(l1c->atge_rx_ring, L1C_RX_RING_CNT,
+ atgep->atge_rx_buf_len, DDI_DMA_READ);
+ if (err != DDI_SUCCESS) {
+ atge_error(atgep->atge_dip, "DMA allocation failed for"
+ " RX buffers");
+ return (err);
+ }
+
+ /*
+ * Allocate CMB used for fetching interrupt status data.
+ */
+ ATGE_DB(("%s: %s() L1C_CMB_BLOCK_SZ : 0x%x", atgep->atge_name,
+ __func__, L1C_CMB_BLOCK_SZ));
+
+ dma = atge_alloc_a_dma_blk(atgep, &atge_l1c_dma_attr_cmb,
+ L1C_CMB_BLOCK_SZ, DDI_DMA_RDWR);
+ l1c->atge_l1c_cmb = dma;
+ if (dma == NULL) {
+ atge_error(atgep->atge_dip, "DMA allocation failed for CMB");
+ return (DDI_FAILURE);
+ }
+
+ /*
+ * RR ring (Return Ring for RX and TX).
+ */
+ ATGE_DB(("%s: %s() L1C_RR_RING_SZ : 0x%x", atgep->atge_name,
+ __func__, L1C_RR_RING_SZ));
+
+ dma = atge_alloc_a_dma_blk(atgep, &atge_l1c_dma_attr_rr,
+ L1C_RR_RING_SZ, DDI_DMA_RDWR);
+ l1c->atge_l1c_rr = dma;
+ if (dma == NULL) {
+ atge_error(atgep->atge_dip, "DMA allocation failed"
+ " for RX RR ring");
+ return (DDI_FAILURE);
+ }
+
+ /*
+ * SMB for statistics.
+ */
+ ATGE_DB(("%s: %s() L1C_SMB_BLOCK_SZ : 0x%x", atgep->atge_name,
+ __func__, L1C_SMB_BLOCK_SZ));
+
+ dma = atge_alloc_a_dma_blk(atgep, &atge_l1c_dma_attr_smb,
+ L1C_SMB_BLOCK_SZ, DDI_DMA_RDWR);
+ l1c->atge_l1c_smb = dma;
+ if (dma == NULL) {
+ atge_error(atgep->atge_dip, "DMA allocation failed for SMB");
+ return (DDI_FAILURE);
+ }
+
+ atgep->atge_hw_stats = kmem_zalloc(sizeof (atge_l1c_smb_t), KM_SLEEP);
+
+ return (DDI_SUCCESS);
+}
+
+void
+atge_l1c_free_dma(atge_t *atgep)
+{
+ atge_l1c_data_t *l1c;
+
+ l1c = atgep->atge_private_data;
+
+ /*
+ * Free TX ring.
+ */
+ if (atgep->atge_tx_ring != NULL) {
+ atge_free_buffers(atgep->atge_tx_ring, ATGE_TX_RING_CNT);
+
+ if (atgep->atge_tx_ring->r_desc_ring != NULL) {
+ atge_free_a_dma_blk(atgep->atge_tx_ring->r_desc_ring);
+ }
+
+ kmem_free(atgep->atge_tx_ring, sizeof (atge_ring_t));
+ atgep->atge_tx_ring = NULL;
+ }
+
+ if (l1c && l1c->atge_l1c_cmb != NULL) {
+ atge_free_a_dma_blk(l1c->atge_l1c_cmb);
+ l1c->atge_l1c_cmb = NULL;
+ }
+
+ if (l1c && l1c->atge_l1c_rr != NULL) {
+ atge_free_a_dma_blk(l1c->atge_l1c_rr);
+ l1c->atge_l1c_rr = NULL;
+ }
+
+ if (l1c && l1c->atge_l1c_smb != NULL) {
+ atge_free_a_dma_blk(l1c->atge_l1c_smb);
+ l1c->atge_l1c_smb = NULL;
+ }
+
+ /*
+ * Free RX ring.
+ */
+ if (l1c && l1c->atge_rx_ring != NULL) {
+ atge_free_buffers(l1c->atge_rx_ring, L1C_RX_RING_CNT);
+
+ if (l1c->atge_rx_ring->r_desc_ring != NULL) {
+ atge_free_a_dma_blk(l1c->atge_rx_ring->r_desc_ring);
+ }
+
+ kmem_free(l1c->atge_rx_ring, sizeof (atge_ring_t));
+ l1c->atge_rx_ring = NULL;
+ }
+
+ /*
+ * Free the memory allocated for gathering hw stats.
+ */
+ if (atgep->atge_hw_stats != NULL) {
+ kmem_free(atgep->atge_hw_stats, sizeof (atge_l1c_smb_t));
+ atgep->atge_hw_stats = NULL;
+ }
+
+ /*
+ * Free the private area.
+ */
+ if (l1c != NULL) {
+ kmem_free(l1c, sizeof (atge_l1c_data_t));
+ atgep->atge_private_data = NULL;
+ }
+}
+
+void
+atge_l1c_init_rx_ring(atge_t *atgep)
+{
+ atge_l1c_data_t *l1c;
+ atge_dma_t *dma;
+ l1c_rx_desc_t *rx;
+ int i;
+
+ l1c = atgep->atge_private_data;
+ l1c->atge_rx_ring->r_consumer = L1C_RX_RING_CNT - 1;
+ dma = l1c->atge_rx_ring->r_desc_ring;
+ bzero(dma->addr, L1C_RX_RING_SZ);
+
+ for (i = 0; i < L1C_RX_RING_CNT; i++) {
+ rx = (l1c_rx_desc_t *)(dma->addr +
+ (i * sizeof (l1c_rx_desc_t)));
+
+ ATGE_PUT64(dma, &rx->addr,
+ l1c->atge_rx_ring->r_buf_tbl[i]->cookie.dmac_laddress);
+ /* No length field. */
+ }
+
+ DMA_SYNC(dma, 0, 0, DDI_DMA_SYNC_FORDEV);
+ /* Let controller know availability of new Rx buffers. */
+ OUTL(atgep, ATGE_MBOX_RD0_PROD_IDX, l1c->atge_rx_ring->r_consumer);
+}
+
+void
+atge_l1c_init_tx_ring(atge_t *atgep)
+{
+ atgep->atge_tx_ring->r_producer = 0;
+ atgep->atge_tx_ring->r_consumer = 0;
+ atgep->atge_tx_ring->r_avail_desc = ATGE_TX_RING_CNT;
+
+ bzero(atgep->atge_tx_ring->r_desc_ring->addr, ATGE_TX_RING_SZ);
+ DMA_SYNC(atgep->atge_tx_ring->r_desc_ring, 0, 0, DDI_DMA_SYNC_FORDEV);
+}
+
+void
+atge_l1c_init_rr_ring(atge_t *atgep)
+{
+ atge_l1c_data_t *l1c;
+ atge_dma_t *dma;
+
+ l1c = atgep->atge_private_data;
+ l1c->atge_l1c_rr_consumers = 0;
+
+ dma = l1c->atge_l1c_rr;
+ bzero(dma->addr, L1C_RR_RING_SZ);
+ DMA_SYNC(dma, 0, 0, DDI_DMA_SYNC_FORDEV);
+}
+
+void
+atge_l1c_init_smb(atge_t *atgep)
+{
+ atge_l1c_data_t *l1c;
+ atge_dma_t *dma;
+
+ l1c = atgep->atge_private_data;
+ dma = l1c->atge_l1c_smb;
+ bzero(dma->addr, L1C_SMB_BLOCK_SZ);
+ DMA_SYNC(dma, 0, 0, DDI_DMA_SYNC_FORDEV);
+}
+
+void
+atge_l1c_init_cmb(atge_t *atgep)
+{
+ atge_l1c_data_t *l1c;
+ atge_dma_t *dma;
+
+ l1c = atgep->atge_private_data;
+ dma = l1c->atge_l1c_cmb;
+ bzero(dma->addr, L1C_CMB_BLOCK_SZ);
+ DMA_SYNC(dma, 0, 0, DDI_DMA_SYNC_FORDEV);
+}
+
+void
+atge_l1c_program_dma(atge_t *atgep)
+{
+ atge_l1c_data_t *l1c;
+ atge_ring_t *r;
+ uint32_t reg;
+
+ l1c = atgep->atge_private_data;
+
+ /*
+ * Clear WOL status and disable all WOL feature as WOL
+ * would interfere Rx operation under normal environments.
+ */
+ (void) INL(atgep, ATGE_WOL_CFG);
+ OUTL(atgep, ATGE_WOL_CFG, 0);
+
+ /* TX */
+ r = atgep->atge_tx_ring;
+ OUTL(atgep, L1C_TX_BASE_ADDR_HI,
+ ATGE_ADDR_HI(r->r_desc_ring->cookie.dmac_laddress));
+ OUTL(atgep, L1C_TDL_HEAD_ADDR_LO,
+ ATGE_ADDR_LO(r->r_desc_ring->cookie.dmac_laddress));
+ /* We don't use high priority ring. */
+ OUTL(atgep, L1C_TDH_HEAD_ADDR_LO, 0);
+
+ /* RX */
+ r = l1c->atge_rx_ring;
+ OUTL(atgep, L1C_RX_BASE_ADDR_HI,
+ ATGE_ADDR_HI(r->r_desc_ring->cookie.dmac_laddress));
+ OUTL(atgep, L1C_RD0_HEAD_ADDR_LO,
+ ATGE_ADDR_LO(r->r_desc_ring->cookie.dmac_laddress));
+ /* We use one Rx ring. */
+ OUTL(atgep, L1C_RD1_HEAD_ADDR_LO, 0);
+ OUTL(atgep, L1C_RD2_HEAD_ADDR_LO, 0);
+ OUTL(atgep, L1C_RD3_HEAD_ADDR_LO, 0);
+
+ /* RR Ring */
+ /*
+ * Let hardware split jumbo frames into alc_max_buf_sized chunks.
+ * if it do not fit the buffer size. Rx return descriptor holds
+ * a counter that indicates how many fragments were made by the
+ * hardware. The buffer size should be multiple of 8 bytes.
+ * Since hardware has limit on the size of buffer size, always
+ * use the maximum value.
+ * For strict-alignment architectures make sure to reduce buffer
+ * size by 8 bytes to make room for alignment fixup.
+ */
+ OUTL(atgep, L1C_RX_BUF_SIZE, RX_BUF_SIZE_MAX); /* XXX */
+
+ /* Set Rx return descriptor base addresses. */
+ OUTL(atgep, L1C_RRD0_HEAD_ADDR_LO,
+ ATGE_ADDR_LO(l1c->atge_l1c_rr->cookie.dmac_laddress));
+ /* We use one Rx return ring. */
+ OUTL(atgep, L1C_RRD1_HEAD_ADDR_LO, 0);
+ OUTL(atgep, L1C_RRD2_HEAD_ADDR_LO, 0);
+ OUTL(atgep, L1C_RRD3_HEAD_ADDR_LO, 0);
+
+ /* CMB */
+ OUTL(atgep, L1C_CMB_BASE_ADDR_LO,
+ ATGE_ADDR_LO(l1c->atge_l1c_cmb->cookie.dmac_laddress));
+
+ /* SMB */
+ OUTL(atgep, L1C_SMB_BASE_ADDR_HI,
+ ATGE_ADDR_HI(l1c->atge_l1c_smb->cookie.dmac_laddress));
+ OUTL(atgep, L1C_SMB_BASE_ADDR_LO,
+ ATGE_ADDR_LO(l1c->atge_l1c_smb->cookie.dmac_laddress));
+
+ /*
+ * Set RX return ring (RR) counter.
+ */
+ /* Set Rx descriptor counter. */
+ OUTL(atgep, L1C_RD_RING_CNT,
+ (L1C_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
+ /* Set Rx return descriptor counter. */
+ OUTL(atgep, L1C_RRD_RING_CNT,
+ (L1C_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
+
+ /*
+ * Set TX descriptor counter.
+ */
+ OUTL(atgep, L1C_TD_RING_CNT,
+ (ATGE_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
+
+ switch (ATGE_DID(atgep)) {
+ case ATGE_CHIP_AR8152V1_DEV_ID:
+ /* Reconfigure SRAM - Vendor magic. */
+ OUTL(atgep, L1C_SRAM_RX_FIFO_LEN, 0x000002A0);
+ OUTL(atgep, L1C_SRAM_TX_FIFO_LEN, 0x00000100);
+ OUTL(atgep, L1C_SRAM_RX_FIFO_ADDR, 0x029F0000);
+ OUTL(atgep, L1C_SRAM_RD_ADDR, 0x02BF02A0);
+ OUTL(atgep, L1C_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
+ OUTL(atgep, L1C_SRAM_TRD_ADDR, 0x03DF03C0);
+ OUTL(atgep, L1C_TXF_WATER_MARK, 0x00000000);
+ OUTL(atgep, L1C_RD_DMA_CFG, 0x00000000);
+ break;
+ }
+
+ /*
+ * Inform hardware that we have loaded DMA registers.
+ */
+ OUTL(atgep, ATGE_DMA_BLOCK, DMA_BLOCK_LOAD);
+
+ /* Configure interrupt moderation timer. */
+ reg = ATGE_USECS(atgep->atge_int_rx_mod) << IM_TIMER_RX_SHIFT;
+ reg |= ATGE_USECS(atgep->atge_int_tx_mod) << IM_TIMER_TX_SHIFT;
+ OUTL(atgep, ATGE_IM_TIMER, reg);
+ /*
+ * We don't want to automatic interrupt clear as task queue
+ * for the interrupt should know interrupt status.
+ */
+ reg = 0;
+ if (ATGE_USECS(atgep->atge_int_rx_mod) != 0)
+ reg |= MASTER_IM_RX_TIMER_ENB;
+ if (ATGE_USECS(atgep->atge_int_tx_mod) != 0)
+ reg |= MASTER_IM_TX_TIMER_ENB;
+ OUTL(atgep, ATGE_MASTER_CFG, reg);
+}
+
+void
+atge_l1c_clear_stats(atge_t *atgep)
+{
+ atge_l1c_smb_t smb;
+ uint32_t *reg;
+ int i;
+
+ /*
+ * Clear RX stats first.
+ */
+ i = 0;
+ reg = &smb.rx_frames;
+ while (reg++ <= &smb.rx_pkts_filtered) {
+ (void) INL(atgep, ATGE_RX_MIB_BASE + i);
+ i += sizeof (uint32_t);
+ }
+
+ /*
+ * Clear TX stats.
+ */
+ i = 0;
+ reg = &smb.tx_frames;
+ while (reg++ <= &smb.tx_mcast_bytes) {
+ (void) INL(atgep, ATGE_TX_MIB_BASE + i);
+ i += sizeof (uint32_t);
+ }
+}
+
+void
+atge_l1c_gather_stats(atge_t *atgep)
+{
+ atge_l1c_data_t *l1c;
+ atge_dma_t *dma;
+ atge_l1c_smb_t *stat;
+ atge_l1c_smb_t *smb;
+
+ ASSERT(atgep != NULL);
+
+ l1c = atgep->atge_private_data;
+ dma = l1c->atge_l1c_smb;
+ DMA_SYNC(dma, 0, 0, DDI_DMA_SYNC_FORKERNEL);
+ stat = (atge_l1c_smb_t *)atgep->atge_hw_stats;
+ smb = (atge_l1c_smb_t *)dma->addr;
+
+ /* Rx stats. */
+ stat->rx_frames += smb->rx_frames;
+ stat->rx_bcast_frames += smb->rx_bcast_frames;
+ stat->rx_mcast_frames += smb->rx_mcast_frames;
+ stat->rx_pause_frames += smb->rx_pause_frames;
+ stat->rx_control_frames += smb->rx_control_frames;
+ stat->rx_crcerrs += smb->rx_crcerrs;
+ stat->rx_lenerrs += smb->rx_lenerrs;
+ stat->rx_bytes += smb->rx_bytes;
+ stat->rx_runts += smb->rx_runts;
+ stat->rx_fragments += smb->rx_fragments;
+ stat->rx_pkts_64 += smb->rx_pkts_64;
+ stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
+ stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
+ stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
+ stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
+ stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
+ stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
+ stat->rx_pkts_truncated += smb->rx_pkts_truncated;
+ stat->rx_fifo_oflows += smb->rx_fifo_oflows;
+ stat->rx_alignerrs += smb->rx_alignerrs;
+ stat->rx_bcast_bytes += smb->rx_bcast_bytes;
+ stat->rx_mcast_bytes += smb->rx_mcast_bytes;
+ stat->rx_pkts_filtered += smb->rx_pkts_filtered;
+
+ /* Tx stats. */
+ stat->tx_frames += smb->tx_frames;
+ stat->tx_bcast_frames += smb->tx_bcast_frames;
+ stat->tx_mcast_frames += smb->tx_mcast_frames;
+ stat->tx_pause_frames += smb->tx_pause_frames;
+ stat->tx_excess_defer += smb->tx_excess_defer;
+ stat->tx_control_frames += smb->tx_control_frames;
+ stat->tx_deferred += smb->tx_deferred;
+ stat->tx_bytes += smb->tx_bytes;
+ stat->tx_pkts_64 += smb->tx_pkts_64;
+ stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
+ stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
+ stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
+ stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
+ stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
+ stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
+ stat->tx_single_colls += smb->tx_single_colls;
+ stat->tx_multi_colls += smb->tx_multi_colls;
+ stat->tx_late_colls += smb->tx_late_colls;
+ stat->tx_excess_colls += smb->tx_excess_colls;
+ stat->tx_underrun += smb->tx_underrun;
+ stat->tx_desc_underrun += smb->tx_desc_underrun;
+ stat->tx_lenerrs += smb->tx_lenerrs;
+ stat->tx_pkts_truncated += smb->tx_pkts_truncated;
+ stat->tx_bcast_bytes += smb->tx_bcast_bytes;
+ stat->tx_mcast_bytes += smb->tx_mcast_bytes;
+
+ /*
+ * Update global counters in atge_t.
+ */
+ atgep->atge_brdcstrcv += smb->rx_bcast_frames;
+ atgep->atge_multircv += smb->rx_mcast_frames;
+ atgep->atge_multixmt += smb->tx_mcast_frames;
+ atgep->atge_brdcstxmt += smb->tx_bcast_frames;
+
+ atgep->atge_align_errors += smb->rx_alignerrs;
+ atgep->atge_fcs_errors += smb->rx_crcerrs;
+ atgep->atge_defer_xmts += smb->tx_deferred;
+ atgep->atge_first_collisions += smb->tx_single_colls;
+ atgep->atge_multi_collisions += smb->tx_multi_colls * 2;
+ atgep->atge_tx_late_collisions += smb->tx_late_colls;
+ atgep->atge_ex_collisions += smb->tx_excess_colls;
+ atgep->atge_toolong_errors += smb->rx_lenerrs;
+ atgep->atge_overflow += smb->rx_fifo_oflows;
+ atgep->atge_underflow += (smb->tx_underrun + smb->tx_desc_underrun);
+ atgep->atge_runt += smb->rx_runts;
+
+
+ atgep->atge_collisions += smb->tx_single_colls +
+ smb->tx_multi_colls * 2 + smb->tx_late_colls;
+
+ /*
+ * tx_pkts_truncated counter looks suspicious. It constantly
+ * increments with no sign of Tx errors. Hence we don't factor it.
+ */
+ atgep->atge_macxmt_errors += smb->tx_late_colls + smb->tx_underrun;
+
+ atgep->atge_macrcv_errors += smb->rx_crcerrs + smb->rx_lenerrs +
+ smb->rx_runts + smb->rx_pkts_truncated +
+ smb->rx_alignerrs;
+
+ smb->updated = 0;
+ DMA_SYNC(dma, 0, 0, DDI_DMA_SYNC_FORDEV);
+}
+
+void
+atge_l1c_stop_tx_mac(atge_t *atgep)
+{
+ uint32_t reg;
+ int t;
+
+ ATGE_DB(("%s: %s() called", atgep->atge_name, __func__));
+
+ reg = INL(atgep, ATGE_MAC_CFG);
+ if ((reg & ATGE_CFG_TX_ENB) != 0) {
+ reg &= ~ATGE_CFG_TX_ENB;
+ OUTL(atgep, ATGE_MAC_CFG, reg);
+ }
+
+ /* Stop TX DMA engine. */
+ reg = INL(atgep, ATGE_DMA_CFG);
+ if ((reg & DMA_CFG_RD_ENB) != 0) {
+ reg &= ~DMA_CFG_RD_ENB;
+ OUTL(atgep, ATGE_DMA_CFG, reg);
+ }
+
+ for (t = ATGE_RESET_TIMEOUT; t > 0; t--) {
+ if ((INL(atgep, ATGE_IDLE_STATUS) &
+ (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
+ break;
+
+ drv_usecwait(10);
+ }
+
+ if (t == 0) {
+ /* This should be an FMA event. */
+ atge_error(atgep->atge_dip, "stopping TX DMA Engine timeout");
+ }
+}
+
+void
+atge_l1c_stop_rx_mac(atge_t *atgep)
+{
+ uint32_t reg;
+ int t;
+
+ ATGE_DB(("%s: %s() called", atgep->atge_name, __func__));
+
+ reg = INL(atgep, ATGE_MAC_CFG);
+ if ((reg & ATGE_CFG_RX_ENB) != 0) {
+ reg &= ~ATGE_CFG_RX_ENB;
+ OUTL(atgep, ATGE_MAC_CFG, reg);
+ }
+
+ /* Stop RX DMA engine. */
+ reg = INL(atgep, ATGE_DMA_CFG);
+ if ((reg & DMA_CFG_WR_ENB) != 0) {
+ reg &= ~DMA_CFG_WR_ENB;
+ OUTL(atgep, ATGE_DMA_CFG, reg);
+ }
+
+ for (t = ATGE_RESET_TIMEOUT; t > 0; t--) {
+ if ((INL(atgep, ATGE_IDLE_STATUS) &
+ (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
+ break;
+ drv_usecwait(10);
+ }
+
+ if (t == 0) {
+ /* This should be an FMA event. */
+ atge_error(atgep->atge_dip, " stopping RX DMA Engine timeout");
+ }
+}
+
+/*
+ * Receives (consumes) packets.
+ */
+static mblk_t *
+atge_l1c_rx(atge_t *atgep)
+{
+ atge_l1c_data_t *l1c;
+ mblk_t *mp = NULL, *rx_head = NULL, *rx_tail = NULL;
+ l1c_rx_rdesc_t *rx_rr;
+ uint32_t rdinfo, status, totlen, pktlen, slotlen;
+ int nsegs, rx_cons = 0, cnt;
+ atge_dma_t *buf;
+ uchar_t *bufp;
+ int sync = 0;
+
+ l1c = atgep->atge_private_data;
+ ASSERT(l1c != NULL);
+
+ DMA_SYNC(l1c->atge_l1c_rr, 0, 0, DDI_DMA_SYNC_FORKERNEL);
+ for (;;) {
+ rx_rr = (l1c_rx_rdesc_t *)(l1c->atge_l1c_rr->addr +
+ (l1c->atge_l1c_rr_consumers * sizeof (l1c_rx_rdesc_t)));
+
+ rdinfo = ATGE_GET32(l1c->atge_l1c_rr, &rx_rr->rdinfo);
+ status = ATGE_GET32(l1c->atge_l1c_rr, &rx_rr->status);
+
+ rx_cons = L1C_RRD_RD_IDX(rdinfo);
+ nsegs = L1C_RRD_RD_CNT(rdinfo);
+ totlen = L1C_RRD_BYTES(status);
+
+ ATGE_DB(("%s: %s() PKT -- rdinfo : 0x%x,"
+ "status : 0x%x, totlen : %d,"
+ " rx_cons : %d, nsegs : %d", atgep->atge_name, __func__,
+ rdinfo, status, totlen, rx_cons, nsegs));
+
+ if ((status & L1C_RRD_VALID) == 0) {
+ break;
+ }
+
+ if ((status & (L1C_RRD_ERR_CRC | L1C_RRD_ERR_ALIGN |
+ L1C_RRD_ERR_TRUNC | L1C_RRD_ERR_RUNT |
+ L1C_RRD_ERR_ICMP | L1C_RRD_ERR_LENGTH)) != 0) {
+ atge_error(atgep->atge_dip, "errored pkt");
+
+ l1c->atge_rx_ring->r_consumer += nsegs;
+ l1c->atge_rx_ring->r_consumer %= L1C_RX_RING_CNT;
+ break;
+ }
+
+ ASSERT(rx_cons >= 0 && rx_cons <= L1C_RX_RING_CNT);
+
+ mp = allocb(totlen + L1C_HEADROOM, BPRI_MED);
+ if (mp != NULL) {
+ mp->b_rptr += L1C_HEADROOM;
+ bufp = mp->b_rptr;
+ mp->b_wptr = bufp + totlen;
+ mp->b_next = NULL;
+
+ atgep->atge_ipackets++;
+ atgep->atge_rbytes += totlen;
+
+ /*
+ * If there are more than one segments, then the first
+ * segment should be of size MTU. We couldn't verify
+ * this as our driver does not support changing MTU
+ * or Jumbo Frames.
+ */
+ if (nsegs > 1) {
+ slotlen = atgep->atge_mtu;
+ } else {
+ slotlen = totlen;
+ }
+ } else {
+ ATGE_DB(("%s: %s() PKT mp == NULL totlen : %d",
+ atgep->atge_name, __func__, totlen));
+
+ if (slotlen > atgep->atge_rx_buf_len) {
+ atgep->atge_toolong_errors++;
+ } else if (mp == NULL) {
+ atgep->atge_norcvbuf++;
+ }
+
+ rx_rr->status = 0;
+ break;
+ }
+
+ for (cnt = 0, pktlen = 0; cnt < nsegs; cnt++) {
+ buf = l1c->atge_rx_ring->r_buf_tbl[rx_cons];
+
+ slotlen = min(atgep->atge_max_frame_size, totlen);
+
+ bcopy(buf->addr, (bufp + pktlen), slotlen);
+ pktlen += slotlen;
+ totlen -= slotlen;
+
+ ATGE_DB(("%s: %s() len : %d, rxcons : %d, pktlen : %d",
+ atgep->atge_name, __func__, slotlen, rx_cons,
+ pktlen));
+
+ ATGE_INC_SLOT(rx_cons, L1C_RX_RING_CNT);
+ }
+
+ if (rx_tail == NULL) {
+ rx_head = rx_tail = mp;
+ } else {
+ rx_tail->b_next = mp;
+ rx_tail = mp;
+ }
+
+ if (cnt != nsegs) {
+ l1c->atge_rx_ring->r_consumer += nsegs;
+ l1c->atge_rx_ring->r_consumer %= L1C_RX_RING_CNT;
+ } else {
+ l1c->atge_rx_ring->r_consumer = rx_cons;
+ }
+
+ /*
+ * Tell the chip that this RR can be reused.
+ */
+ rx_rr->status = 0;
+
+ ATGE_INC_SLOT(l1c->atge_l1c_rr_consumers, L1C_RR_RING_CNT);
+ sync++;
+ }
+
+ if (sync) {
+ DMA_SYNC(l1c->atge_rx_ring->r_desc_ring, 0, 0,
+ DDI_DMA_SYNC_FORDEV);
+
+ DMA_SYNC(l1c->atge_l1c_rr, 0, 0, DDI_DMA_SYNC_FORDEV);
+ /*
+ * Let controller know availability of new Rx buffers.
+ */
+ OUTL(atgep, ATGE_MBOX_RD0_PROD_IDX,
+ l1c->atge_rx_ring->r_consumer);
+
+ ATGE_DB(("%s: %s() PKT Recved -> r_consumer : %d, rx_cons : %d"
+ " atge_l1c_rr_consumers : %d",
+ atgep->atge_name, __func__, l1c->atge_rx_ring->r_consumer,
+ rx_cons, l1c->atge_l1c_rr_consumers));
+ }
+
+
+ return (rx_head);
+}
+
+/*
+ * The interrupt handler for L1C chip.
+ */
+/*ARGSUSED*/
+uint_t
+atge_l1c_interrupt(caddr_t arg1, caddr_t arg2)
+{
+ atge_t *atgep = (void *)arg1;
+ mblk_t *rx_head = NULL;
+ uint32_t status;
+ int resched = 0;
+
+ ASSERT(atgep != NULL);
+
+ mutex_enter(&atgep->atge_intr_lock);
+
+ if (atgep->atge_chip_state & ATGE_CHIP_SUSPENDED) {
+ mutex_exit(&atgep->atge_intr_lock);
+ return (DDI_INTR_UNCLAIMED);
+ }
+
+ status = INL(atgep, ATGE_INTR_STATUS);
+ if (status == 0 || (status & atgep->atge_intrs) == 0) {
+ mutex_exit(&atgep->atge_intr_lock);
+
+ if (atgep->atge_flags & ATGE_FIXED_TYPE)
+ return (DDI_INTR_UNCLAIMED);
+
+ return (DDI_INTR_CLAIMED);
+ }
+
+ ATGE_DB(("%s: %s() entry status : %x",
+ atgep->atge_name, __func__, status));
+
+ /*
+ * Disable interrupts.
+ */
+ if (status & L1C_INTR_GPHY) {
+ /* clear PHY interrupt source before we ack interrupts */
+ (void) atge_mii_read(atgep,
+ atgep->atge_phyaddr, ATGE_ISR_ACK_GPHY);
+ }
+
+ OUTL(atgep, ATGE_INTR_STATUS, status | L1C_INTR_DIS_INT);
+ FLUSH(atgep, ATGE_INTR_STATUS);
+
+ /*
+ * Check if chip is running, only then do the work.
+ */
+ if (atgep->atge_chip_state & ATGE_CHIP_RUNNING) {
+ atge_l1c_data_t *l1c;
+
+ l1c = atgep->atge_private_data;
+
+ ATGE_DB(("%s: %s() atge_l1c_intr_status : %x, "
+ "atge_l1c_rx_prod_cons : %d, atge_l1c_tx_prod_cons : %d"
+ " atge_l1c_rr_consumers : %d",
+ atgep->atge_name, __func__, l1c->atge_l1c_intr_status,
+ l1c->atge_l1c_rx_prod_cons, l1c->atge_l1c_tx_prod_cons,
+ l1c->atge_l1c_rr_consumers));
+
+ if (status & L1C_INTR_SMB)
+ atge_l1c_gather_stats(atgep);
+
+ /*
+ * Check for errors.
+ */
+ if (status & (L1C_INTR_DMA_RD_TO_RST |
+ L1C_INTR_DMA_WR_TO_RST | L1C_INTR_TXQ_TO_RST)) {
+ /* This should be an FMA event. */
+ atge_error(atgep->atge_dip,
+ "L1C chip detected a fatal error, "
+ "interrupt status: %x", status);
+
+ if (status & L1C_INTR_DMA_RD_TO_RST) {
+ atge_error(atgep->atge_dip,
+ "DMA read error");
+ }
+ if (status & L1C_INTR_DMA_WR_TO_RST) {
+ atge_error(atgep->atge_dip,
+ "DMA write error");
+ }
+ if (status & L1C_INTR_TXQ_TO_RST) {
+ atge_error(atgep->atge_dip,
+ "Transmit queue error");
+ }
+
+ /* This should be an FMA event. */
+ atge_device_stop(atgep);
+ /*
+ * Device has failed fatally.
+ * It will not be restarted by the driver.
+ */
+ goto done;
+
+ }
+
+ rx_head = atge_l1c_rx(atgep);
+ if (status & L1C_INTR_TX_PKT) {
+ int cons;
+
+ mutex_enter(&atgep->atge_tx_lock);
+ cons = INL(atgep, ATGE_MBOX_TD_CONS_IDX) >> 16;
+ atge_tx_reclaim(atgep, cons);
+ if (atgep->atge_tx_resched) {
+ atgep->atge_tx_resched = 0;
+ resched = 1;
+ }
+
+ mutex_exit(&atgep->atge_tx_lock);
+ }
+ }
+
+ /* Re-enable interrupts. */
+ OUTL(atgep, ATGE_INTR_STATUS, 0);
+
+done:
+ mutex_exit(&atgep->atge_intr_lock);
+
+ if (status & L1C_INTR_GPHY) {
+ /* link down */
+ ATGE_DB(("%s: %s() MII_CHECK Performed",
+ atgep->atge_name, __func__));
+ mii_check(atgep->atge_mii);
+ }
+
+ /*
+ * Pass the list of packets received from chip to MAC layer.
+ */
+ if (rx_head) {
+ mac_rx(atgep->atge_mh, 0, rx_head);
+ }
+
+ /*
+ * Let MAC start sending pkts if the downstream was asked to pause.
+ */
+ if (resched)
+ mac_tx_update(atgep->atge_mh);
+
+ return (DDI_INTR_CLAIMED);
+}
+
+void
+atge_l1c_send_packet(atge_ring_t *r)
+{
+ atge_t *atgep;
+
+ atgep = r->r_atge;
+
+ mutex_enter(&atgep->atge_mbox_lock);
+ /* Sync descriptors. */
+ DMA_SYNC(atgep->atge_tx_ring->r_desc_ring, 0, 0, DDI_DMA_SYNC_FORDEV);
+ /* Kick. Assume we're using normal Tx priority queue. */
+ OUTL(atgep, ATGE_MBOX_TD_PROD_IDX,
+ (atgep->atge_tx_ring->r_producer << MBOX_TD_PROD_LO_IDX_SHIFT) &
+ MBOX_TD_PROD_LO_IDX_MASK);
+ mutex_exit(&atgep->atge_mbox_lock);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/uts/common/io/atge/atge_l1c_reg.h Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,492 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2012 Gary Mills
+ *
+ * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
+/*
+ * Copyright (c) 2009, Pyun YongHyeon <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ATGE_L1C_REG_H
+#define _ATGE_L1C_REG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#pragma pack(1)
+typedef struct l1c_cmb {
+ uint32_t intr_status;
+ uint32_t rx_prod_cons;
+ uint32_t tx_prod_cons;
+} l1c_cmb_t;
+
+typedef struct l1c_rx_desc {
+ uint64_t addr;
+ /* No length field. */
+} l1c_rx_desc_t;
+
+typedef struct l1c_rx_rdesc {
+ uint32_t rdinfo; /* word 0 */
+ uint32_t rss; /* word 1 */
+ uint32_t vtag; /* word 2 */
+ uint32_t status; /* word 3 */
+} l1c_rx_rdesc_t;
+
+/*
+ * Statistics counters collected by the MAC
+ */
+typedef struct l1c_smb {
+ /* Rx stats. */
+ uint32_t rx_frames;
+ uint32_t rx_bcast_frames;
+ uint32_t rx_mcast_frames;
+ uint32_t rx_pause_frames;
+ uint32_t rx_control_frames;
+ uint32_t rx_crcerrs;
+ uint32_t rx_lenerrs;
+ uint32_t rx_bytes;
+ uint32_t rx_runts;
+ uint32_t rx_fragments;
+ uint32_t rx_pkts_64;
+ uint32_t rx_pkts_65_127;
+ uint32_t rx_pkts_128_255;
+ uint32_t rx_pkts_256_511;
+ uint32_t rx_pkts_512_1023;
+ uint32_t rx_pkts_1024_1518;
+ uint32_t rx_pkts_1519_max;
+ uint32_t rx_pkts_truncated;
+ uint32_t rx_fifo_oflows;
+ uint32_t rx_desc_oflows;
+ uint32_t rx_alignerrs;
+ uint32_t rx_bcast_bytes;
+ uint32_t rx_mcast_bytes;
+ uint32_t rx_pkts_filtered;
+ /* Tx stats. */
+ uint32_t tx_frames;
+ uint32_t tx_bcast_frames;
+ uint32_t tx_mcast_frames;
+ uint32_t tx_pause_frames;
+ uint32_t tx_excess_defer;
+ uint32_t tx_control_frames;
+ uint32_t tx_deferred;
+ uint32_t tx_bytes;
+ uint32_t tx_pkts_64;
+ uint32_t tx_pkts_65_127;
+ uint32_t tx_pkts_128_255;
+ uint32_t tx_pkts_256_511;
+ uint32_t tx_pkts_512_1023;
+ uint32_t tx_pkts_1024_1518;
+ uint32_t tx_pkts_1519_max;
+ uint32_t tx_single_colls;
+ uint32_t tx_multi_colls;
+ uint32_t tx_late_colls;
+ uint32_t tx_excess_colls;
+ uint32_t tx_underrun;
+ uint32_t tx_desc_underrun;
+ uint32_t tx_lenerrs;
+ uint32_t tx_pkts_truncated;
+ uint32_t tx_bcast_bytes;
+ uint32_t tx_mcast_bytes;
+ uint32_t updated;
+} atge_l1c_smb_t;
+#pragma pack()
+
+#define L1C_RX_RING_CNT 256
+#define L1C_RR_RING_CNT L1C_RX_RING_CNT
+#define L1C_HEADROOM 6 /* Must be divisible by 2, but not 4. */
+
+#define L1C_RING_ALIGN 16
+#define L1C_TX_RING_ALIGN 16
+#define L1C_RX_RING_ALIGN 16
+#define L1C_RR_RING_ALIGN 16
+#define L1C_CMB_ALIGN 16
+#define L1C_SMB_ALIGN 16
+
+#define L1C_CMB_BLOCK_SZ sizeof (struct l1c_cmb)
+#define L1C_SMB_BLOCK_SZ sizeof (struct l1c_smb)
+
+#define L1C_RX_RING_SZ \
+ (sizeof (struct l1c_rx_desc) * L1C_RX_RING_CNT)
+
+#define L1C_RR_RING_SZ \
+ (sizeof (struct l1c_rx_rdesc) * L1C_RR_RING_CNT)
+
+/*
+ * For RX
+ */
+/* word 0 */
+#define L1C_RRD_CSUM_MASK 0x0000FFFF
+#define L1C_RRD_RD_CNT_MASK 0x000F0000
+#define L1C_RRD_RD_IDX_MASK 0xFFF00000
+#define L1C_RRD_CSUM_SHIFT 0
+#define L1C_RRD_RD_CNT_SHIFT 16
+#define L1C_RRD_RD_IDX_SHIFT 20
+#define L1C_RRD_CSUM(x) \
+ (((x) & L1C_RRD_CSUM_MASK) >> L1C_RRD_CSUM_SHIFT)
+#define L1C_RRD_RD_CNT(x) \
+ (((x) & L1C_RRD_RD_CNT_MASK) >> L1C_RRD_RD_CNT_SHIFT)
+#define L1C_RRD_RD_IDX(x) \
+ (((x) & L1C_RRD_RD_IDX_MASK) >> L1C_RRD_RD_IDX_SHIFT)
+
+/* word 2 */
+#define L1C_RRD_VLAN_MASK 0x0000FFFF
+#define L1C_RRD_HEAD_LEN_MASK 0x00FF0000
+#define L1C_RRD_HDS_MASK 0x03000000
+#define L1C_RRD_HDS_NONE 0x00000000
+#define L1C_RRD_HDS_HEAD 0x01000000
+#define L1C_RRD_HDS_DATA 0x02000000
+#define L1C_RRD_CPU_MASK 0x0C000000
+#define L1C_RRD_HASH_FLAG_MASK 0xF0000000
+#define L1C_RRD_VLAN_SHIFT 0
+#define L1C_RRD_HEAD_LEN_SHIFT 16
+#define L1C_RRD_HDS_SHIFT 24
+#define L1C_RRD_CPU_SHIFT 26
+#define L1C_RRD_HASH_FLAG_SHIFT 28
+#define L1C_RRD_VLAN(x) \
+ (((x) & L1C_RRD_VLAN_MASK) >> L1C_RRD_VLAN_SHIFT)
+#define L1C_RRD_HEAD_LEN(x) \
+ (((x) & L1C_RRD_HEAD_LEN_MASK) >> L1C_RRD_HEAD_LEN_SHIFT)
+#define L1C_RRD_CPU(x) \
+ (((x) & L1C_RRD_CPU_MASK) >> L1C_RRD_CPU_SHIFT)
+
+ /* word3 */
+#define L1C_RRD_LEN_MASK 0x00003FFF
+#define L1C_RRD_LEN_SHIFT 0
+#define L1C_RRD_TCP_UDPCSUM_NOK 0x00004000
+#define L1C_RRD_IPCSUM_NOK 0x00008000
+#define L1C_RRD_VLAN_TAG 0x00010000
+#define L1C_RRD_PROTO_MASK 0x000E0000
+#define L1C_RRD_PROTO_IPV4 0x00020000
+#define L1C_RRD_PROTO_IPV6 0x000C0000
+#define L1C_RRD_ERR_SUM 0x00100000
+#define L1C_RRD_ERR_CRC 0x00200000
+#define L1C_RRD_ERR_ALIGN 0x00400000
+#define L1C_RRD_ERR_TRUNC 0x00800000
+#define L1C_RRD_ERR_RUNT 0x01000000
+#define L1C_RRD_ERR_ICMP 0x02000000
+#define L1C_RRD_BCAST 0x04000000
+#define L1C_RRD_MCAST 0x08000000
+#define L1C_RRD_SNAP_LLC 0x10000000
+#define L1C_RRD_ETHER 0x00000000
+#define L1C_RRD_FIFO_FULL 0x20000000
+#define L1C_RRD_ERR_LENGTH 0x40000000
+#define L1C_RRD_VALID 0x80000000
+#define L1C_RRD_BYTES(x) \
+ (((x) & L1C_RRD_LEN_MASK) >> L1C_RRD_LEN_SHIFT)
+#define L1C_RRD_IPV4(x) \
+ (((x) & L1C_RRD_PROTO_MASK) == L1C_RRD_PROTO_IPV4)
+
+#define RRD_PROD_MASK 0x0000FFFF
+#define TPD_CONS_MASK 0xFFFF0000
+#define TPD_CONS_SHIFT 16
+#define CMB_UPDATED 0x00000001
+#define RRD_PROD_SHIFT 0
+
+#pragma pack(1)
+typedef struct l1c_tx_desc {
+ uint32_t len;
+#define L1C_TD_BUFLEN_MASK 0x00003FFF
+#define L1C_TD_VLAN_MASK 0xFFFF0000
+#define L1C_TD_BUFLEN_SHIFT 0
+#define L1C_TX_BYTES(x) \
+ (((x) << L1C_TD_BUFLEN_SHIFT) & L1C_TD_BUFLEN_MASK)
+#define L1C_TD_VLAN_SHIFT 16
+
+ uint32_t flags;
+#define L1C_TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */
+#define L1C_TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */
+#define L1C_TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */
+#define L1C_TD_CUSTOM_CSUM 0x00000100
+#define L1C_TD_IPCSUM 0x00000200
+#define L1C_TD_TCPCSUM 0x00000400
+#define L1C_TD_UDPCSUM 0x00000800
+#define L1C_TD_TSO 0x00001000
+#define L1C_TD_TSO_DESCV1 0x00000000
+#define L1C_TD_TSO_DESCV2 0x00002000
+#define L1C_TD_CON_VLAN_TAG 0x00004000
+#define L1C_TD_INS_VLAN_TAG 0x00008000
+#define L1C_TD_IPV4_DESCV2 0x00010000
+#define L1C_TD_LLC_SNAP 0x00020000
+#define L1C_TD_ETHERNET 0x00000000
+#define L1C_TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */
+#define L1C_TD_CUSTOM_CSUM_EVEN_PAD 0x40000000
+#define L1C_TD_MSS_MASK 0x7FFC0000
+#define L1C_TD_EOP 0x80000000
+#define L1C_TD_L4HDR_OFFSET_SHIFT 0
+#define L1C_TD_TCPHDR_OFFSET_SHIFT 0
+#define L1C_TD_PLOAD_OFFSET_SHIFT 0
+#define L1C_TD_CUSTOM_CSUM_OFFSET_SHIFT 18
+#define L1C_TD_MSS_SHIFT 18
+
+ uint64_t addr;
+} l1c_tx_desc_t;
+#pragma pack()
+
+/*
+ * All descriptors and CMB/SMB share the same high address.
+ */
+
+/* From Freebsd if_alcreg.h */
+#define L1C_RSS_IDT_TABLE0 0x14E0
+
+#define L1C_RX_BASE_ADDR_HI 0x1540
+
+#define L1C_TX_BASE_ADDR_HI 0x1544
+
+#define L1C_SMB_BASE_ADDR_HI 0x1548
+
+#define L1C_SMB_BASE_ADDR_LO 0x154C
+
+#define L1C_RD0_HEAD_ADDR_LO 0x1550
+
+#define L1C_RD1_HEAD_ADDR_LO 0x1554
+
+#define L1C_RD2_HEAD_ADDR_LO 0x1558
+
+#define L1C_RD3_HEAD_ADDR_LO 0x155C
+
+#define L1C_RD_RING_CNT 0x1560
+#define RD_RING_CNT_MASK 0x00000FFF
+#define RD_RING_CNT_SHIFT 0
+
+#define L1C_RX_BUF_SIZE 0x1564
+#define RX_BUF_SIZE_MASK 0x0000FFFF
+/*
+ * If larger buffer size than 1536 is specified the controller
+ * will be locked up. This is hardware limitation.
+ */
+#define RX_BUF_SIZE_MAX 1536
+
+#define L1C_RRD0_HEAD_ADDR_LO 0x1568
+
+#define L1C_RRD1_HEAD_ADDR_LO 0x156C
+
+#define L1C_RRD2_HEAD_ADDR_LO 0x1570
+
+#define L1C_RRD3_HEAD_ADDR_LO 0x1574
+
+#define L1C_RRD_RING_CNT 0x1578
+#define RRD_RING_CNT_MASK 0x00000FFF
+#define RRD_RING_CNT_SHIFT 0
+
+#define L1C_TDH_HEAD_ADDR_LO 0x157C
+
+#define L1C_TDL_HEAD_ADDR_LO 0x1580
+
+#define L1C_TD_RING_CNT 0x1584
+#define TD_RING_CNT_MASK 0x0000FFFF
+#define TD_RING_CNT_SHIFT 0
+
+#define L1C_CMB_BASE_ADDR_LO 0x1588
+
+#define L1C_RXQ_CFG 0x15A0
+#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003
+#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000
+#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001
+#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002
+#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003
+
+#define L1C_RSS_CPU 0x15B8
+
+/* End of Freebsd if_alcreg.h */
+
+/*
+ * PHY registers.
+ */
+#define PHY_CDTS_STAT_OK 0x0000
+#define PHY_CDTS_STAT_SHORT 0x0100
+#define PHY_CDTS_STAT_OPEN 0x0200
+#define PHY_CDTS_STAT_INVAL 0x0300
+#define PHY_CDTS_STAT_MASK 0x0300
+
+/*
+ * MAC CFG registers (L1C specific)
+ */
+#define L1C_CFG_SINGLE_PAUSE_ENB 0x10000000
+
+/*
+ * DMA CFG registers (L1C specific)
+ */
+#define DMA_CFG_RD_ENB 0x00000400
+#define DMA_CFG_WR_ENB 0x00000800
+#define DMA_CFG_RD_BURST_MASK 0x07
+#define DMA_CFG_RD_BURST_SHIFT 4
+#define DMA_CFG_WR_BURST_MASK 0x07
+#define DMA_CFG_WR_BURST_SHIFT 7
+#define DMA_CFG_SMB_DIS 0x01000000
+
+#define L1C_RD_LEN_MASK 0x0000FFFF
+#define L1C_RD_LEN_SHIFT 0
+
+#define L1C_SRAM_RD_ADDR 0x1500
+#define L1C_SRAM_RD_LEN 0x1504
+#define L1C_SRAM_RRD_ADDR 0x1508
+#define L1C_SRAM_RRD_LEN 0x150C
+#define L1C_SRAM_TPD_ADDR 0x1510
+#define L1C_SRAM_TPD_LEN 0x1514
+#define L1C_SRAM_TRD_ADDR 0x1518
+#define L1C_SRAM_TRD_LEN 0x151C
+#define L1C_SRAM_RX_FIFO_ADDR 0x1520
+#define L1C_SRAM_RX_FIFO_LEN 0x1524
+#define L1C_SRAM_TX_FIFO_ADDR 0x1528
+#define L1C_SRAM_TX_FIFO_LEN 0x152C
+
+#define L1C_RXQ_CFG_RD_BURST_MASK 0x03f00000
+#define L1C_RXQ_CFG_RD_BURST_SHIFT 20
+
+#define L1C_TXQ_CFG 0x1590
+#define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00
+#define L1C_TXQ_CFG_TPD_BURST_DEFAULT 5
+#define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8
+#define TXQ_CFG_TPD_FETCH_DEFAULT 16
+
+#define L1C_TXF_WATER_MARK 0x1598 /* 8 bytes unit */
+#define TXF_WATER_MARK_HI_MASK 0x00000FFF
+#define TXF_WATER_MARK_LO_MASK 0x0FFF0000
+#define TXF_WATER_MARK_BURST_ENB 0x80000000
+#define TXF_WATER_MARK_LO_SHIFT 0
+#define TXF_WATER_MARK_HI_SHIFT 16
+
+#define L1C_RD_DMA_CFG 0x15AC
+#define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */
+#define RD_DMA_CFG_TIMER_MASK 0xFFFF0000
+#define RD_DMA_CFG_THRESH_SHIFT 0
+#define RD_DMA_CFG_TIMER_SHIFT 16
+#define RD_DMA_CFG_THRESH_DEFAULT 0x100
+#define RD_DMA_CFG_TIMER_DEFAULT 0
+#define RD_DMA_CFG_TICK_USECS 8
+#define L1C_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS)
+
+/* CMB DMA Write Threshold Register */
+#define L1C_CMB_WR_THRESH 0x15D4
+#define CMB_WR_THRESH_RRD_MASK 0x000007FF
+#define CMB_WR_THRESH_TPD_MASK 0x07FF0000
+#define CMB_WR_THRESH_RRD_SHIFT 0
+#define CMB_WR_THRESH_RRD_DEFAULT 4
+#define CMB_WR_THRESH_TPD_SHIFT 16
+#define CMB_WR_THRESH_TPD_DEFAULT 4
+
+/* SMB auto DMA timer register */
+#define L1C_SMB_TIMER 0x15E4
+
+#define L1C_CSMB_CTRL 0x15D0
+#define CSMB_CTRL_CMB_KICK 0x00000001
+#define CSMB_CTRL_SMB_KICK 0x00000002
+#define CSMB_CTRL_CMB_ENB 0x00000004
+#define CSMB_CTRL_SMB_ENB 0x00000008
+
+/* From Freebsd if_alcreg.h */
+#define L1C_INTR_SMB 0x00000001
+#define L1C_INTR_TIMER 0x00000002
+#define L1C_INTR_MANUAL_TIMER 0x00000004
+#define L1C_INTR_RX_FIFO_OFLOW 0x00000008
+#define L1C_INTR_RD0_UNDERRUN 0x00000010
+#define L1C_INTR_RD1_UNDERRUN 0x00000020
+#define L1C_INTR_RD2_UNDERRUN 0x00000040
+#define L1C_INTR_RD3_UNDERRUN 0x00000080
+#define L1C_INTR_TX_FIFO_UNDERRUN 0x00000100
+#define L1C_INTR_DMA_RD_TO_RST 0x00000200
+#define L1C_INTR_DMA_WR_TO_RST 0x00000400
+#define L1C_INTR_TX_CREDIT 0x00000800
+#define L1C_INTR_GPHY 0x00001000
+#define L1C_INTR_GPHY_LOW_PW 0x00002000
+#define L1C_INTR_TXQ_TO_RST 0x00004000
+#define L1C_INTR_TX_PKT 0x00008000
+#define L1C_INTR_RX_PKT0 0x00010000
+#define L1C_INTR_RX_PKT1 0x00020000
+#define L1C_INTR_RX_PKT2 0x00040000
+#define L1C_INTR_RX_PKT3 0x00080000
+#define L1C_INTR_MAC_RX 0x00100000
+#define L1C_INTR_MAC_TX 0x00200000
+#define L1C_INTR_UNDERRUN 0x00400000
+#define L1C_INTR_FRAME_ERROR 0x00800000
+#define L1C_INTR_FRAME_OK 0x01000000
+#define L1C_INTR_CSUM_ERROR 0x02000000
+#define L1C_INTR_PHY_LINK_DOWN 0x04000000
+#define L1C_INTR_DIS_INT 0x80000000
+
+#define L1C_INTR_RX_PKT L1C_INTR_RX_PKT0
+#define L1C_INTR_RD_UNDERRUN L1C_INTR_RD0_UNDERRUN
+
+#define L1C_INTRS \
+ (L1C_INTR_DMA_RD_TO_RST | L1C_INTR_DMA_WR_TO_RST | \
+ L1C_INTR_TXQ_TO_RST| L1C_INTR_RX_PKT | L1C_INTR_TX_PKT | \
+ L1C_INTR_RX_FIFO_OFLOW | L1C_INTR_RD_UNDERRUN | \
+ L1C_INTR_TX_FIFO_UNDERRUN)
+
+#define L1C_RXQ_RRD_PAUSE_THRESH 0x15AC
+#define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF
+#define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000
+#define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0
+#define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16
+
+/* RX/TX count-down timer to trigger CMB-write. */
+#define L1C_CMB_WR_TIMER 0x15D8
+#define CMB_WR_TIMER_RX_MASK 0x0000FFFF
+#define CMB_WR_TIMER_TX_MASK 0xFFFF0000
+#define CMB_WR_TIMER_RX_SHIFT 0
+#define CMB_WR_TIMER_TX_SHIFT 16
+
+/*
+ * Useful macros.
+ */
+#define L1C_RX_NSEGS(x) \
+ (((x) & L1C_RRD_NSEGS_MASK) >> L1C_RRD_NSEGS_SHIFT)
+#define L1C_RX_CONS(x) \
+ (((x) & L1C_RRD_CONS_MASK) >> L1C_RRD_CONS_SHIFT)
+#define L1C_RX_CSUM(x) \
+ (((x) & L1C_RRD_CSUM_MASK) >> L1C_RRD_CSUM_SHIFT)
+#define L1C_RX_BYTES(x) \
+ (((x) & L1C_RRD_LEN_MASK) >> L1C_RRD_LEN_SHIFT)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ATGE_L1C_REG_H */
--- a/usr/src/uts/common/io/atge/atge_l1e.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/atge/atge_l1e.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,6 +20,8 @@
*/
/*
+ * Copyright (c) 2012 Gary Mills
+ *
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
@@ -401,10 +403,10 @@
OUTL(atgep, ATGE_IM_TIMER, reg);
reg = INL(atgep, ATGE_MASTER_CFG);
- reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
- reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
- reg |= MASTER_IM_RX_TIMER_ENB;
- reg |= MASTER_IM_TX_TIMER_ENB;
+ reg &= ~(L1E_MASTER_CHIP_REV_MASK | L1E_MASTER_CHIP_ID_MASK);
+ reg &= ~(L1E_MASTER_IM_RX_TIMER_ENB | L1E_MASTER_IM_TX_TIMER_ENB);
+ reg |= L1E_MASTER_IM_RX_TIMER_ENB;
+ reg |= L1E_MASTER_IM_TX_TIMER_ENB;
OUTL(atgep, ATGE_MASTER_CFG, reg);
OUTW(atgep, RX_COALSC_PKT_1e, 0);
--- a/usr/src/uts/common/io/atge/atge_l1e_reg.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/atge/atge_l1e_reg.h Sun Aug 12 11:56:48 2012 +0100
@@ -19,6 +19,8 @@
* CDDL HEADER END
*/
/*
+ * Copyright (c) 2012 Gary Mills
+ *
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
@@ -48,22 +50,28 @@
} rx_cmb_t;
#pragma pack()
+/* Master configuration */
+#define L1E_MASTER_CFG 0x1400
+#define L1E_MASTER_RESET 0x00000001
+#define L1E_MASTER_MTIMER_ENB 0x00000002
+#define L1E_MASTER_IM_TX_TIMER_ENB 0x00000004
+#define L1E_MASTER_MANUAL_INT_ENB 0x00000008
+#define L1E_MASTER_IM_RX_TIMER_ENB 0x00000020
+#define L1E_MASTER_CHIP_REV_MASK 0x00FF0000
+#define L1E_MASTER_CHIP_ID_MASK 0xFF000000
+#define L1E_MASTER_CHIP_REV_SHIFT 16
+#define L1E_MASTER_CHIP_ID_SHIFT 24
+
+
/*
* DMA CFG registers (L1E specific).
*/
#define DMA_CFG_RD_REQ_PRI 0x00000400
-#define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800
-#define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000
#define DMA_CFG_TXCMB_ENB 0x00100000
-#define DMA_CFG_RXCMB_ENB 0x00200000
#define DMA_CFG_RD_BURST_MASK 0x07
#define DMA_CFG_RD_BURST_SHIFT 4
#define DMA_CFG_WR_BURST_MASK 0x07
#define DMA_CFG_WR_BURST_SHIFT 7
-#define DMA_CFG_RD_DELAY_CNT_SHIFT 11
-#define DMA_CFG_WR_DELAY_CNT_SHIFT 16
-#define DMA_CFG_RD_DELAY_CNT_DEFAULT 15
-#define DMA_CFG_WR_DELAY_CNT_DEFAULT 4
#define L1E_TX_RING_CNT_MIN 32
#define L1E_TX_RING_CNT_MAX 1020
--- a/usr/src/uts/common/io/atge/atge_main.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/atge/atge_main.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,8 +20,36 @@
*/
/*
+ * Copyright (c) 2012 Gary Mills
+ *
* Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
*/
+/*
+ * Copyright (c) 2009, Pyun YongHyeon <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
#include <sys/types.h>
#include <sys/stream.h>
@@ -53,15 +81,16 @@
#include "atge.h"
#include "atge_cmn_reg.h"
+#include "atge_l1c_reg.h"
#include "atge_l1e_reg.h"
#include "atge_l1_reg.h"
/*
- * Atheros/Attansic Ethernet chips are of three types - L1, L2 and L1E.
- * This driver is for L1E/L1 but can be extended to support other chips.
+ * Atheros/Attansic Ethernet chips are of four types - L1, L2, L1E and L1C.
+ * This driver is for L1E/L1/L1C but can be extended to support other chips.
* L1E comes in 1Gigabit and Fast Ethernet flavors. L1 comes in 1Gigabit
- * flavors only.
+ * flavors only. L1C comes in both flavours.
*
* Atheros/Attansic Ethernet controllers have descriptor based TX and RX
* with an exception of L1E. L1E's RX side is not descriptor based ring.
@@ -152,6 +181,7 @@
* L1 specific functions.
*/
int atge_l1_alloc_dma(atge_t *);
+void atge_l1_free_dma(atge_t *);
void atge_l1_init_tx_ring(atge_t *);
void atge_l1_init_rx_ring(atge_t *);
void atge_l1_init_rr_ring(atge_t *);
@@ -163,14 +193,34 @@
uint_t atge_l1_interrupt(caddr_t, caddr_t);
void atge_l1_send_packet(atge_ring_t *);
+/*
+ * L1C specific functions.
+ */
+int atge_l1c_alloc_dma(atge_t *);
+void atge_l1c_free_dma(atge_t *);
+void atge_l1c_init_tx_ring(atge_t *);
+void atge_l1c_init_rx_ring(atge_t *);
+void atge_l1c_init_rr_ring(atge_t *);
+void atge_l1c_init_cmb(atge_t *);
+void atge_l1c_init_smb(atge_t *);
+void atge_l1c_program_dma(atge_t *);
+void atge_l1c_stop_tx_mac(atge_t *);
+void atge_l1c_stop_rx_mac(atge_t *);
+uint_t atge_l1c_interrupt(caddr_t, caddr_t);
+void atge_l1c_send_packet(atge_ring_t *);
+void atge_l1c_gather_stats(atge_t *);
+void atge_l1c_clear_stats(atge_t *);
/*
* Function prototyps for MII operations.
*/
uint16_t atge_mii_read(void *, uint8_t, uint8_t);
void atge_mii_write(void *, uint8_t, uint8_t, uint16_t);
+uint16_t atge_l1c_mii_read(void *, uint8_t, uint8_t);
+void atge_l1c_mii_write(void *, uint8_t, uint8_t, uint16_t);
void atge_l1e_mii_reset(void *);
void atge_l1_mii_reset(void *);
+void atge_l1c_mii_reset(void *);
static void atge_mii_notify(void *, link_state_t);
void atge_tx_reclaim(atge_t *atgep, int cons);
@@ -197,6 +247,17 @@
};
/*
+ * L1C chip.
+ */
+static mii_ops_t atge_l1c_mii_ops = {
+ MII_OPS_VERSION,
+ atge_l1c_mii_read,
+ atge_l1c_mii_write,
+ atge_mii_notify,
+ NULL
+};
+
+/*
* Function Prototypes for MAC callbacks.
*/
static int atge_m_stat(void *, uint_t, uint64_t *);
@@ -272,11 +333,28 @@
* Table of supported devices.
*/
#define ATGE_VENDOR_ID 0x1969
+#define ATGE_L1_STR "Attansic L1"
+#define ATGE_L1CG_STR "Atheros AR8131 Gigabit Ethernet"
+#define ATGE_L1CF_STR "Atheros AR8132 Fast Ethernet"
#define ATGE_L1E_STR "Atheros AR8121/8113/8114"
+#define ATGE_AR8151V1_STR "Atheros AR8151 v1.0 Gigabit Ethernet"
+#define ATGE_AR8151V2_STR "Atheros AR8151 v2.0 Gigabit Ethernet"
+#define ATGE_AR8152V1_STR "Atheros AR8152 v1.1 Fast Ethernet"
+#define ATGE_AR8152V2_STR "Atheros AR8152 v2.0 Fast Ethernet"
static atge_cards_t atge_cards[] = {
+ {ATGE_VENDOR_ID, ATGE_CHIP_AR8151V2_DEV_ID, ATGE_AR8151V2_STR,
+ ATGE_CHIP_L1C},
+ {ATGE_VENDOR_ID, ATGE_CHIP_AR8151V1_DEV_ID, ATGE_AR8151V1_STR,
+ ATGE_CHIP_L1C},
+ {ATGE_VENDOR_ID, ATGE_CHIP_AR8152V2_DEV_ID, ATGE_AR8152V2_STR,
+ ATGE_CHIP_L1C},
+ {ATGE_VENDOR_ID, ATGE_CHIP_AR8152V1_DEV_ID, ATGE_AR8152V1_STR,
+ ATGE_CHIP_L1C},
+ {ATGE_VENDOR_ID, ATGE_CHIP_L1CG_DEV_ID, ATGE_L1CG_STR, ATGE_CHIP_L1C},
+ {ATGE_VENDOR_ID, ATGE_CHIP_L1CF_DEV_ID, ATGE_L1CF_STR, ATGE_CHIP_L1C},
{ATGE_VENDOR_ID, ATGE_CHIP_L1E_DEV_ID, ATGE_L1E_STR, ATGE_CHIP_L1E},
- {ATGE_VENDOR_ID, ATGE_CHIP_L1_DEV_ID, "Attansic L1", ATGE_CHIP_L1},
+ {ATGE_VENDOR_ID, ATGE_CHIP_L1_DEV_ID, ATGE_L1_STR, ATGE_CHIP_L1},
};
/*
@@ -300,22 +378,47 @@
DTRACE_PROBE1(atge__debug, char *, buf);
}
+static
+void
+atge_message(dev_info_t *dip, int level, char *fmt, va_list ap)
+{
+ char buf[256];
+ char *p = "!%s%d: %s";
+ char *q = "!atge: %s";
+
+ (void) vsnprintf(buf, sizeof (buf), fmt, ap);
+
+ if (level != CE_NOTE) {
+ p++;
+ q++;
+ }
+
+ if (dip) {
+ cmn_err(level, p,
+ ddi_driver_name(dip), ddi_get_instance(dip), buf);
+ } else {
+ cmn_err(level, q, buf);
+ }
+}
+
+void
+atge_notice(dev_info_t *dip, char *fmt, ...)
+{
+ va_list ap;
+
+ va_start(ap, fmt);
+ (void) atge_message(dip, CE_NOTE, fmt, ap);
+ va_end(ap);
+}
+
void
atge_error(dev_info_t *dip, char *fmt, ...)
{
va_list ap;
- char buf[256];
va_start(ap, fmt);
- (void) vsnprintf(buf, sizeof (buf), fmt, ap);
+ (void) atge_message(dip, CE_WARN, fmt, ap);
va_end(ap);
-
- if (dip) {
- cmn_err(CE_WARN, "%s%d: %s",
- ddi_driver_name(dip), ddi_get_instance(dip), buf);
- } else {
- cmn_err(CE_WARN, "atge: %s", buf);
- }
}
void
@@ -325,10 +428,23 @@
int speed;
link_duplex_t ld;
+ /* Re-enable TX/RX MACs */
reg = INL(atgep, ATGE_MAC_CFG);
reg &= ~(ATGE_CFG_FULL_DUPLEX | ATGE_CFG_TX_FC | ATGE_CFG_RX_FC |
ATGE_CFG_SPEED_MASK);
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1C:
+ switch (ATGE_DID(atgep)) {
+ case ATGE_CHIP_AR8151V2_DEV_ID:
+ case ATGE_CHIP_AR8151V1_DEV_ID:
+ case ATGE_CHIP_AR8152V2_DEV_ID:
+ reg |= ATGE_CFG_HASH_ALG_CRC32 | ATGE_CFG_SPEED_MODE_SW;
+ break;
+ }
+ break;
+ }
+
speed = mii_get_speed(atgep->atge_mii);
switch (speed) {
case 10:
@@ -345,19 +461,43 @@
reg |= ATGE_CFG_FULL_DUPLEX;
/* Re-enable TX/RX MACs */
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
reg |= ATGE_CFG_TX_ENB | ATGE_CFG_RX_ENB | ATGE_CFG_RX_FC;
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ break;
+ case ATGE_CHIP_L1:
+ case ATGE_CHIP_L1C:
reg |= ATGE_CFG_TX_ENB | ATGE_CFG_RX_ENB;
+ break;
}
OUTL(atgep, ATGE_MAC_CFG, reg);
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
reg = ATGE_USECS(ATGE_IM_RX_TIMER_DEFAULT) << IM_TIMER_RX_SHIFT;
reg |= ATGE_USECS(ATGE_IM_TX_TIMER_DEFAULT) <<
IM_TIMER_TX_SHIFT;
OUTL(atgep, ATGE_IM_TIMER, reg);
+ break;
+ case ATGE_CHIP_L1:
+ break;
+ case ATGE_CHIP_L1C:
+ /* Configure interrupt moderation timer. */
+ reg = ATGE_USECS(atgep->atge_int_rx_mod) << IM_TIMER_RX_SHIFT;
+ reg |= ATGE_USECS(atgep->atge_int_tx_mod) << IM_TIMER_TX_SHIFT;
+ OUTL(atgep, ATGE_IM_TIMER, reg);
+ /*
+ * We don't want to automatic interrupt clear as task queue
+ * for the interrupt should know interrupt status.
+ */
+ reg = 0;
+ if (ATGE_USECS(atgep->atge_int_rx_mod) != 0)
+ reg |= MASTER_IM_RX_TIMER_ENB;
+ if (ATGE_USECS(atgep->atge_int_tx_mod) != 0)
+ reg |= MASTER_IM_TX_TIMER_ENB;
+ OUTL(atgep, ATGE_MASTER_CFG, reg);
+ break;
}
ATGE_DB(("%s: %s() mac_cfg is : %x",
@@ -523,12 +663,19 @@
* Add interrupt handler now.
*/
for (i = 0; i < atgep->atge_intr_cnt; i++) {
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
err = ddi_intr_add_handler(atgep->atge_intr_handle[i],
atge_l1e_interrupt, atgep, (caddr_t)(uintptr_t)i);
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ break;
+ case ATGE_CHIP_L1:
err = ddi_intr_add_handler(atgep->atge_intr_handle[i],
atge_l1_interrupt, atgep, (caddr_t)(uintptr_t)i);
+ break;
+ case ATGE_CHIP_L1C:
+ err = ddi_intr_add_handler(atgep->atge_intr_handle[i],
+ atge_l1c_interrupt, atgep, (caddr_t)(uintptr_t)i);
+ break;
}
if (err != DDI_SUCCESS) {
@@ -709,9 +856,14 @@
if (atge_cards[i].vendor_id == vid &&
atge_cards[i].device_id == did) {
atgep->atge_model = atge_cards[i].model;
+ atgep->atge_vid = vid;
+ atgep->atge_did = did;
atgep->atge_revid =
pci_config_get8(atgep->atge_conf_handle,
PCI_CONF_REVID);
+ atge_notice(atgep->atge_dip, "PCI-ID pci%x,%x,%x: %s",
+ vid, did, atgep->atge_revid,
+ atge_cards[i].cardname);
ATGE_DB(("%s: %s : PCI-ID pci%x,%x and model : %d",
atgep->atge_name, __func__, vid, did,
atgep->atge_model));
@@ -721,12 +873,14 @@
}
atge_error(atgep->atge_dip, "atge driver is attaching to unknown"
- " pci%d,%d vendor/device-id card", vid, did);
+ " pci%x,%x vendor/device-id card", vid, did);
/*
- * Assume it's L1 chip.
+ * Assume it's L1C chip.
*/
- atgep->atge_model = ATGE_CHIP_L1;
+ atgep->atge_model = ATGE_CHIP_L1C;
+ atgep->atge_vid = vid;
+ atgep->atge_did = did;
atgep->atge_revid = pci_config_get8(atgep->atge_conf_handle,
PCI_CONF_REVID);
@@ -774,14 +928,18 @@
}
/*
- * Reset functionality for L1 and L1E. It's same.
+ * Reset functionality for L1, L1E, and L1C. It's same.
*/
static void
atge_device_reset(atge_t *atgep)
{
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E ||
- ATGE_MODEL(atgep) == ATGE_CHIP_L1)
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
+ case ATGE_CHIP_L1:
+ case ATGE_CHIP_L1C:
atge_device_reset_l1_l1e(atgep);
+ break;
+ }
}
void
@@ -789,8 +947,14 @@
{
uint32_t reg;
int t;
-
- OUTL(atgep, ATGE_MASTER_CFG, MASTER_RESET);
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1C:
+ OUTL(atgep, ATGE_MASTER_CFG, MASTER_RESET | 0x40);
+ break;
+ default:
+ OUTL(atgep, ATGE_MASTER_CFG, MASTER_RESET);
+ break;
+ }
reg = INL(atgep, ATGE_MASTER_CFG);
for (t = ATGE_RESET_TIMEOUT; t > 0; t--) {
drv_usecwait(10);
@@ -816,13 +980,20 @@
reg);
}
- /*
- * Initialize PCIe module. These values came from FreeBSD and
- * we don't know the meaning of it.
- */
- OUTL(atgep, 0x12FC, 0x6500);
- reg = INL(atgep, 0x1008) | 0x8000;
- OUTL(atgep, 0x1008, reg);
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
+ case ATGE_CHIP_L1:
+ /*
+ * Initialize PCIe module. These values came from FreeBSD and
+ * we don't know the meaning of it.
+ */
+ OUTL(atgep, ATGE_LTSSM_ID_CFG, 0x6500);
+ reg = INL(atgep, 0x1008) | 0x8000;
+ OUTL(atgep, 0x1008, reg);
+ break;
+ case ATGE_CHIP_L1C:
+ break;
+ }
/*
* Get chip revision.
@@ -843,10 +1014,16 @@
{
int err = DDI_FAILURE;
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
err = atge_l1e_alloc_dma(atgep);
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ break;
+ case ATGE_CHIP_L1:
err = atge_l1_alloc_dma(atgep);
+ break;
+ case ATGE_CHIP_L1C:
+ err = atge_l1c_alloc_dma(atgep);
+ break;
}
return (err);
@@ -855,8 +1032,16 @@
static void
atge_free_dma(atge_t *atgep)
{
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
atge_l1e_free_dma(atgep);
+ break;
+ case ATGE_CHIP_L1:
+ atge_l1_free_dma(atgep);
+ break;
+ case ATGE_CHIP_L1C:
+ atge_l1c_free_dma(atgep);
+ break;
}
}
@@ -877,15 +1062,15 @@
instance = ddi_get_instance(devinfo);
switch (cmd) {
- default:
- return (DDI_FAILURE);
-
case DDI_RESUME:
return (atge_resume(devinfo));
case DDI_ATTACH:
ddi_set_driver_private(devinfo, NULL);
break;
+ default:
+ return (DDI_FAILURE);
+
}
atgep = kmem_zalloc(sizeof (atge_t), KM_SLEEP);
@@ -951,7 +1136,8 @@
atgep->atge_link_state = LINK_STATE_DOWN;
atgep->atge_mtu = ETHERMTU;
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
if (atgep->atge_revid > 0xF0) {
/* L2E Rev. B. AR8114 */
atgep->atge_flags |= ATGE_FLAG_FASTETHER;
@@ -965,6 +1151,45 @@
atgep->atge_flags |= ATGE_FLAG_FASTETHER;
}
}
+ break;
+ case ATGE_CHIP_L1:
+ break;
+ case ATGE_CHIP_L1C:
+ /*
+ * One odd thing is AR8132 uses the same PHY hardware(F1
+ * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
+ * the PHY supports 1000Mbps but that's not true. The PHY
+ * used in AR8132 can't establish gigabit link even if it
+ * shows the same PHY model/revision number of AR8131.
+ *
+ * It seems that AR813x/AR815x has silicon bug for SMB. In
+ * addition, Atheros said that enabling SMB wouldn't improve
+ * performance. However I think it's bad to access lots of
+ * registers to extract MAC statistics.
+ *
+ * Don't use Tx CMB. It is known to have silicon bug.
+ */
+ switch (ATGE_DID(atgep)) {
+ case ATGE_CHIP_AR8152V2_DEV_ID:
+ case ATGE_CHIP_AR8152V1_DEV_ID:
+ atgep->atge_flags |= ATGE_FLAG_APS |
+ ATGE_FLAG_FASTETHER |
+ ATGE_FLAG_ASPM_MON | ATGE_FLAG_JUMBO |
+ ATGE_FLAG_SMB_BUG | ATGE_FLAG_CMB_BUG;
+ break;
+ case ATGE_CHIP_AR8151V2_DEV_ID:
+ case ATGE_CHIP_AR8151V1_DEV_ID:
+ atgep->atge_flags |= ATGE_FLAG_APS |
+ ATGE_FLAG_ASPM_MON | ATGE_FLAG_JUMBO |
+ ATGE_FLAG_SMB_BUG | ATGE_FLAG_CMB_BUG;
+ break;
+ case ATGE_CHIP_L1CF_DEV_ID:
+ atgep->atge_flags |= ATGE_FLAG_FASTETHER;
+ break;
+ case ATGE_CHIP_L1CG_DEV_ID:
+ break;
+ }
+ break;
}
/*
@@ -999,6 +1224,20 @@
(128 << ((burst >> 5) & 0x07))));
}
+ /* Clear data link and flow-control protocol error. */
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
+ break;
+ case ATGE_CHIP_L1:
+ break;
+ case ATGE_CHIP_L1C:
+ OUTL_AND(atgep, ATGE_PEX_UNC_ERR_SEV,
+ ~(PEX_UNC_ERR_SEV_UC | PEX_UNC_ERR_SEV_FCP));
+ OUTL_AND(atgep, ATGE_LTSSM_ID_CFG, ~LTSSM_ID_WRO_ENB);
+ OUTL_OR(atgep, ATGE_PCIE_PHYMISC, PCIE_PHYMISC_FORCE_RCV_DET);
+ break;
+ }
+
/*
* Allocate DMA resources.
*/
@@ -1016,10 +1255,16 @@
/*
* Setup MII.
*/
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
mii_ops = &atge_l1e_mii_ops;
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ break;
+ case ATGE_CHIP_L1:
mii_ops = &atge_l1_mii_ops;
+ break;
+ case ATGE_CHIP_L1C:
+ mii_ops = &atge_l1c_mii_ops;
+ break;
}
if ((atgep->atge_mii = mii_alloc(atgep, devinfo,
@@ -1072,10 +1317,16 @@
/*
* Reset the PHY before starting.
*/
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
atge_l1e_mii_reset(atgep);
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ break;
+ case ATGE_CHIP_L1:
atge_l1_mii_reset(atgep);
+ break;
+ case ATGE_CHIP_L1C:
+ atge_l1c_mii_reset(atgep);
+ break;
}
/*
@@ -1362,8 +1613,14 @@
/*
* Reset the PHY before resuming MII.
*/
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
atge_l1e_mii_reset(atgep);
+ break;
+ case ATGE_CHIP_L1:
+ break;
+ case ATGE_CHIP_L1C:
+ break;
}
mii_resume(atgep->atge_mii);
@@ -1797,16 +2054,45 @@
*/
atge_program_ether(atgep);
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
atge_l1e_program_dma(atgep);
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ break;
+ case ATGE_CHIP_L1:
atge_l1_program_dma(atgep);
+ break;
+ case ATGE_CHIP_L1C:
+ atge_l1c_program_dma(atgep);
+ break;
}
ATGE_DB(("%s: %s() dma, counters programmed ", atgep->atge_name,
__func__));
- OUTW(atgep, ATGE_INTR_CLR_TIMER, 1*1000/2);
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
+ case ATGE_CHIP_L1:
+ OUTW(atgep, ATGE_INTR_CLR_TIMER, 1*1000/2);
+ break;
+ case ATGE_CHIP_L1C:
+ /*
+ * Disable interrupt re-trigger timer. We don't want automatic
+ * re-triggering of un-ACKed interrupts.
+ */
+ OUTL(atgep, ATGE_INTR_RETRIG_TIMER, ATGE_USECS(0));
+ /* Configure CMB. */
+ OUTL(atgep, ATGE_CMB_TX_TIMER, ATGE_USECS(0));
+ /*
+ * Hardware can be configured to issue SMB interrupt based
+ * on programmed interval. Since there is a callout that is
+ * invoked for every hz in driver we use that instead of
+ * relying on periodic SMB interrupt.
+ */
+ OUTL(atgep, ATGE_SMB_STAT_TIMER, ATGE_USECS(0));
+ /* Clear MAC statistics. */
+ atge_l1c_clear_stats(atgep);
+ break;
+ }
/*
* Set Maximum frame size but don't let MTU be less than ETHER_MTU.
@@ -1820,6 +2106,16 @@
VLAN_TAGSZ + ETHERFCSL;
OUTL(atgep, ATGE_FRAME_SIZE, atgep->atge_max_frame_size);
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
+ break;
+ case ATGE_CHIP_L1:
+ break;
+ case ATGE_CHIP_L1C:
+ /* Disable header split(?) */
+ OUTL(atgep, ATGE_HDS_CFG, 0);
+ break;
+ }
/*
* Configure IPG/IFG parameters.
@@ -1846,7 +2142,23 @@
/*
* Configure jumbo frame.
*/
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
+ if (atgep->atge_flags & ATGE_FLAG_JUMBO) {
+
+ if (atgep->atge_mtu < ETHERMTU)
+ reg = atgep->atge_max_frame_size;
+ else if (atgep->atge_mtu < 6 * 1024)
+ reg = (atgep->atge_max_frame_size * 2) / 3;
+ else
+ reg = atgep->atge_max_frame_size / 2;
+
+ OUTL(atgep, L1E_TX_JUMBO_THRESH,
+ ROUNDUP(reg, TX_JUMBO_THRESH_UNIT) >>
+ TX_JUMBO_THRESH_UNIT_SHIFT);
+ }
+ break;
+ case ATGE_CHIP_L1:
fsize = ROUNDUP(atgep->atge_max_frame_size, sizeof (uint64_t));
OUTL(atgep, ATGE_RXQ_JUMBO_CFG,
(((fsize / sizeof (uint64_t)) <<
@@ -1856,37 +2168,46 @@
RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
((ATGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
RXQ_JUMBO_CFG_RRD_TIMER_MASK));
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E &&
- atgep->atge_flags & ATGE_FLAG_JUMBO) {
-
- if (atgep->atge_mtu < ETHERMTU)
- reg = atgep->atge_max_frame_size;
- else if (atgep->atge_mtu < 6 * 1024)
- reg = (atgep->atge_max_frame_size * 2) / 3;
- else
- reg = atgep->atge_max_frame_size / 2;
-
- OUTL(atgep, L1E_TX_JUMBO_THRESH,
- ROUNDUP(reg, TX_JUMBO_THRESH_UNIT) >>
- TX_JUMBO_THRESH_UNIT_SHIFT);
+ break;
+ case ATGE_CHIP_L1C:
+ break;
}
/*
* Configure flow-control parameters.
*/
- if ((atgep->atge_flags & ATGE_FLAG_PCIE) != 0) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
+ case ATGE_CHIP_L1:
+ if ((atgep->atge_flags & ATGE_FLAG_PCIE) != 0) {
/*
* Some hardware version require this magic.
*/
- OUTL(atgep, 0x12FC, 0x6500);
+ OUTL(atgep, ATGE_LTSSM_ID_CFG, 0x6500);
reg = INL(atgep, 0x1008);
OUTL(atgep, 0x1008, reg | 0x8000);
+ }
+ break;
+ case ATGE_CHIP_L1C:
+ break;
}
/*
* These are all magic parameters which came from FreeBSD.
*/
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
+ reg = INL(atgep, L1E_SRAM_RX_FIFO_LEN);
+ rxf_hi = (reg * 4) / 5;
+ rxf_lo = reg/ 5;
+
+ OUTL(atgep, ATGE_RXQ_FIFO_PAUSE_THRESH,
+ ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
+ RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
+ ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
+ RXQ_FIFO_PAUSE_THRESH_HI_MASK));
+ break;
+ case ATGE_CHIP_L1:
switch (atgep->atge_chip_rev) {
case 0x8001:
case 0x9001:
@@ -1926,54 +2247,46 @@
RXQ_RRD_PAUSE_THRESH_LO_MASK) |
((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
RXQ_RRD_PAUSE_THRESH_HI_MASK));
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
- reg = INL(atgep, L1E_SRAM_RX_FIFO_LEN);
- rxf_hi = (reg * 4) / 5;
- rxf_lo = reg/ 5;
-
- OUTL(atgep, ATGE_RXQ_FIFO_PAUSE_THRESH,
- ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
- RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
- ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
- RXQ_FIFO_PAUSE_THRESH_HI_MASK));
+ break;
+ case ATGE_CHIP_L1C:
+ switch (ATGE_DID(atgep)) {
+ case ATGE_CHIP_AR8151V2_DEV_ID:
+ case ATGE_CHIP_AR8152V1_DEV_ID:
+ OUTL(atgep, ATGE_SERDES_LOCK,
+ INL(atgep, ATGE_SERDES_LOCK) |
+ SERDES_MAC_CLK_SLOWDOWN |
+ SERDES_PHY_CLK_SLOWDOWN);
+ break;
+ case ATGE_CHIP_L1CG_DEV_ID:
+ case ATGE_CHIP_L1CF_DEV_ID:
+ /*
+ * Configure flow control parameters.
+ * XON : 80% of Rx FIFO
+ * XOFF : 30% of Rx FIFO
+ */
+ reg = INL(atgep, L1C_SRAM_RX_FIFO_LEN);
+ rxf_hi = (reg * 8) / 10;
+ rxf_lo = (reg * 3) / 10;
+
+ OUTL(atgep, ATGE_RXQ_FIFO_PAUSE_THRESH,
+ ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
+ RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
+ ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
+ RXQ_FIFO_PAUSE_THRESH_HI_MASK));
+ break;
+ }
+ break;
}
- /* Configure RxQ. */
- reg = 0;
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
- reg =
- ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
- RXQ_CFG_RD_BURST_MASK) |
- ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
- RXQ_CFG_RRD_BURST_THRESH_SHIFT) &
- RXQ_CFG_RRD_BURST_THRESH_MASK) |
- ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
- RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) &
- RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
- RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB;
- OUTL(atgep, ATGE_RXQ_CFG, reg);
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
+ /* Configure RxQ. */
reg = RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB |
RXQ_CFG_IPV6_CSUM_VERIFY | RXQ_CFG_ENB;
OUTL(atgep, ATGE_RXQ_CFG, reg);
- }
-
- /*
- * Configure TxQ.
- */
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
- reg =
- (((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
- TXQ_CFG_TPD_BURST_MASK) |
- ((TXQ_CFG_TX_FIFO_BURST_DEFAULT <<
- TXQ_CFG_TX_FIFO_BURST_SHIFT) &
- TXQ_CFG_TX_FIFO_BURST_MASK) |
- ((TXQ_CFG_TPD_FETCH_DEFAULT <<
- TXQ_CFG_TPD_FETCH_THRESH_SHIFT) &
- TXQ_CFG_TPD_FETCH_THRESH_MASK) |
- TXQ_CFG_ENB);
- OUTL(atgep, ATGE_TXQ_CFG, reg);
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ /*
+ * Configure TxQ.
+ */
reg = (128 <<
(atgep->atge_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) <<
TXQ_CFG_TX_FIFO_BURST_SHIFT;
@@ -1984,38 +2297,12 @@
reg |= TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB;
OUTL(atgep, ATGE_TXQ_CFG, reg);
- }
-
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
- OUTL(atgep, L1_TX_JUMBO_TPD_TH_IPG,
- (((fsize / sizeof (uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
- TX_JUMBO_TPD_TH_MASK) |
- ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
- TX_JUMBO_TPD_IPG_MASK));
- }
-
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
/* Disable RSS. */
OUTL(atgep, L1E_RSS_IDT_TABLE0, 0);
OUTL(atgep, L1E_RSS_CPU, 0);
- }
-
- /*
- * Configure DMA parameters.
- */
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
- OUTL(atgep, ATGE_DMA_CFG,
- DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
- atgep->atge_dma_rd_burst | DMA_CFG_RD_ENB |
- atgep->atge_dma_wr_burst | DMA_CFG_WR_ENB);
-
- /* Configure CMB DMA write threshold. */
- OUTL(atgep, L1_CMB_WR_THRESH,
- ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
- CMB_WR_THRESH_RRD_MASK) |
- ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
- CMB_WR_THRESH_TPD_MASK));
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ /*
+ * Configure DMA parameters.
+ */
/*
* Don't use Tx CMB. It is known to cause RRS update failure
* under certain circumstances. Typical phenomenon of the
@@ -2030,12 +2317,62 @@
DMA_CFG_RD_DELAY_CNT_SHIFT) & DMA_CFG_RD_DELAY_CNT_MASK) |
((DMA_CFG_WR_DELAY_CNT_DEFAULT <<
DMA_CFG_WR_DELAY_CNT_SHIFT) & DMA_CFG_WR_DELAY_CNT_MASK));
- }
-
- /*
- * Enable CMB/SMB timer.
- */
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ /*
+ * Enable CMB/SMB timer.
+ */
+ OUTL(atgep, L1E_SMB_STAT_TIMER, 100000);
+ atge_l1e_clear_stats(atgep);
+ break;
+ case ATGE_CHIP_L1:
+ /* Configure RxQ. */
+ reg =
+ ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
+ RXQ_CFG_RD_BURST_MASK) |
+ ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
+ RXQ_CFG_RRD_BURST_THRESH_SHIFT) &
+ RXQ_CFG_RRD_BURST_THRESH_MASK) |
+ ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
+ RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) &
+ RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
+ RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB;
+ OUTL(atgep, ATGE_RXQ_CFG, reg);
+ /*
+ * Configure TxQ.
+ */
+ reg =
+ (((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
+ TXQ_CFG_TPD_BURST_MASK) |
+ ((TXQ_CFG_TX_FIFO_BURST_DEFAULT <<
+ TXQ_CFG_TX_FIFO_BURST_SHIFT) &
+ TXQ_CFG_TX_FIFO_BURST_MASK) |
+ ((TXQ_CFG_TPD_FETCH_DEFAULT <<
+ TXQ_CFG_TPD_FETCH_THRESH_SHIFT) &
+ TXQ_CFG_TPD_FETCH_THRESH_MASK) |
+ TXQ_CFG_ENB);
+ OUTL(atgep, ATGE_TXQ_CFG, reg);
+ /* Jumbo frames */
+ OUTL(atgep, L1_TX_JUMBO_TPD_TH_IPG,
+ (((fsize / sizeof (uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
+ TX_JUMBO_TPD_TH_MASK) |
+ ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
+ TX_JUMBO_TPD_IPG_MASK));
+ /*
+ * Configure DMA parameters.
+ */
+ OUTL(atgep, ATGE_DMA_CFG,
+ DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
+ atgep->atge_dma_rd_burst | DMA_CFG_RD_ENB |
+ atgep->atge_dma_wr_burst | DMA_CFG_WR_ENB);
+
+ /* Configure CMB DMA write threshold. */
+ OUTL(atgep, L1_CMB_WR_THRESH,
+ ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
+ CMB_WR_THRESH_RRD_MASK) |
+ ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
+ CMB_WR_THRESH_TPD_MASK));
+ /*
+ * Enable CMB/SMB timer.
+ */
/* Set CMB/SMB timer and enable them. */
OUTL(atgep, L1_CMB_WR_TIMER,
((ATGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) &
@@ -2047,12 +2384,54 @@
OUTL(atgep, L1_SMB_TIMER, ATGE_USECS(1000 * 1000));
OUTL(atgep, L1_CSMB_CTRL,
CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
- OUTL(atgep, L1E_SMB_STAT_TIMER, 100000);
- atge_l1e_clear_stats(atgep);
+ break;
+ case ATGE_CHIP_L1C:
+ /* Configure RxQ. */
+ reg =
+ RXQ_CFG_RD_BURST_DEFAULT << L1C_RXQ_CFG_RD_BURST_SHIFT |
+ RXQ_CFG_IPV6_CSUM_VERIFY | RXQ_CFG_ENB;
+ if ((atgep->atge_flags & ATGE_FLAG_ASPM_MON) != 0)
+ reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
+ OUTL(atgep, ATGE_RXQ_CFG, reg);
+ /*
+ * Configure TxQ.
+ */
+ reg = (128 <<
+ (atgep->atge_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) <<
+ TXQ_CFG_TX_FIFO_BURST_SHIFT;
+
+ switch (ATGE_DID(atgep)) {
+ case ATGE_CHIP_AR8152V2_DEV_ID:
+ case ATGE_CHIP_AR8152V1_DEV_ID:
+ reg >>= 1;
+ break;
+ }
+
+ reg |= (L1C_TXQ_CFG_TPD_BURST_DEFAULT <<
+ TXQ_CFG_TPD_BURST_SHIFT) & TXQ_CFG_TPD_BURST_MASK;
+
+ reg |= TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB;
+
+ OUTL(atgep, L1C_TXQ_CFG, reg);
+ /* Disable RSS until I understand L1C/L2C's RSS logic. */
+ OUTL(atgep, L1C_RSS_IDT_TABLE0, 0xe4e4e4e4);
+ OUTL(atgep, L1C_RSS_CPU, 0);
+ /*
+ * Configure DMA parameters.
+ */
+ OUTL(atgep, ATGE_DMA_CFG,
+ DMA_CFG_SMB_DIS |
+ DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
+ DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT |
+ DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT |
+
+ atgep->atge_dma_rd_burst | DMA_CFG_RD_ENB |
+ atgep->atge_dma_wr_burst | DMA_CFG_WR_ENB);
+ /* Configure CMB DMA write threshold not required. */
+ /* Set CMB/SMB timer and enable them not required. */
+ break;
}
-
/*
* Disable all WOL bits as WOL can interfere normal Rx
* operation.
@@ -2072,6 +2451,22 @@
((ATGE_CFG_PREAMBLE_DEFAULT << ATGE_CFG_PREAMBLE_SHIFT) &
ATGE_CFG_PREAMBLE_MASK));
+ /*
+ * AR813x/AR815x always does checksum computation regardless
+ * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
+ * have bug in protocol field in Rx return structure so
+ * these controllers can't handle fragmented frames. Disable
+ * Rx checksum offloading until there is a newer controller
+ * that has sane implementation.
+ */
+ switch (ATGE_DID(atgep)) {
+ case ATGE_CHIP_AR8151V2_DEV_ID:
+ case ATGE_CHIP_AR8151V1_DEV_ID:
+ case ATGE_CHIP_AR8152V2_DEV_ID:
+ reg |= ATGE_CFG_HASH_ALG_CRC32 | ATGE_CFG_SPEED_MODE_SW;
+ break;
+ }
+
if ((atgep->atge_flags & ATGE_FLAG_FASTETHER) != 0) {
reg |= ATGE_CFG_SPEED_10_100;
ATGE_DB(("%s: %s() Fast Ethernet", atgep->atge_name, __func__));
@@ -2079,6 +2474,11 @@
reg |= ATGE_CFG_SPEED_1000;
ATGE_DB(("%s: %s() 1G speed", atgep->atge_name, __func__));
}
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1C:
+ reg |= L1C_CFG_SINGLE_PAUSE_ENB;
+ break;
+ }
OUTL(atgep, ATGE_MAC_CFG, reg);
@@ -2092,13 +2492,17 @@
/*
* Acknowledge all pending interrupts and clear it.
*/
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
- OUTL(atgep, ATGE_INTR_STATUS, 0);
- OUTL(atgep, ATGE_INTR_MASK, atgep->atge_intrs);
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
OUTL(atgep, ATGE_INTR_MASK, L1E_INTRS);
OUTL(atgep, ATGE_INTR_STATUS, 0xFFFFFFFF);
OUTL(atgep, ATGE_INTR_STATUS, 0);
+ break;
+ case ATGE_CHIP_L1:
+ case ATGE_CHIP_L1C:
+ OUTL(atgep, ATGE_INTR_STATUS, 0);
+ OUTL(atgep, ATGE_INTR_MASK, atgep->atge_intrs);
+ break;
}
atge_mac_config(atgep);
@@ -2194,8 +2598,13 @@
/*
* Collect stats for L1E. L1 chip's stats are collected by interrupt.
*/
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
atge_l1e_gather_stats(atgep);
+ break;
+ case ATGE_CHIP_L1:
+ case ATGE_CHIP_L1C:
+ break;
}
/*
@@ -2203,40 +2612,70 @@
*/
atge_disable_intrs(atgep);
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1)
- OUTL(atgep, L1_CSMB_CTRL, 0);
-
- /* Stop DMA Engine */
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
- atge_l1_stop_tx_mac(atgep);
- atge_l1_stop_rx_mac(atgep);
-
- reg = INL(atgep, ATGE_DMA_CFG);
- reg &= ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
- OUTL(atgep, ATGE_DMA_CFG, reg);
-
- }
-
- /*
- * Disable queue processing.
- */
- /* Stop TxQ */
- reg = INL(atgep, ATGE_TXQ_CFG);
- reg = reg & ~TXQ_CFG_ENB;
- OUTL(atgep, ATGE_TXQ_CFG, reg);
-
- /* Stop RxQ */
- reg = INL(atgep, ATGE_RXQ_CFG);
- reg = reg & ~RXQ_CFG_ENB;
- OUTL(atgep, ATGE_RXQ_CFG, reg);
-
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
+ /* Clear CTRL not required. */
+ /* Stop DMA Engine not required. */
+ /*
+ * Disable queue processing.
+ */
+ /* Stop TxQ */
+ reg = INL(atgep, ATGE_TXQ_CFG);
+ reg = reg & ~TXQ_CFG_ENB;
+ OUTL(atgep, ATGE_TXQ_CFG, reg);
+ /* Stop RxQ */
+ reg = INL(atgep, ATGE_RXQ_CFG);
+ reg = reg & ~RXQ_CFG_ENB;
+ OUTL(atgep, ATGE_RXQ_CFG, reg);
+ /* Stop DMA */
reg = INL(atgep, ATGE_DMA_CFG);
reg = reg & ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
OUTL(atgep, ATGE_DMA_CFG, reg);
drv_usecwait(1000);
atge_l1e_stop_mac(atgep);
OUTL(atgep, ATGE_INTR_STATUS, 0xFFFFFFFF);
+ break;
+ case ATGE_CHIP_L1:
+ /* Clear CTRL. */
+ OUTL(atgep, L1_CSMB_CTRL, 0);
+ /* Stop DMA Engine */
+ atge_l1_stop_tx_mac(atgep);
+ atge_l1_stop_rx_mac(atgep);
+ reg = INL(atgep, ATGE_DMA_CFG);
+ reg &= ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
+ OUTL(atgep, ATGE_DMA_CFG, reg);
+ /*
+ * Disable queue processing.
+ */
+ /* Stop TxQ */
+ reg = INL(atgep, ATGE_TXQ_CFG);
+ reg = reg & ~TXQ_CFG_ENB;
+ OUTL(atgep, ATGE_TXQ_CFG, reg);
+ /* Stop RxQ */
+ reg = INL(atgep, ATGE_RXQ_CFG);
+ reg = reg & ~RXQ_CFG_ENB;
+ OUTL(atgep, ATGE_RXQ_CFG, reg);
+ break;
+ case ATGE_CHIP_L1C:
+ /* Clear CTRL not required. */
+ /* Stop DMA Engine */
+ atge_l1c_stop_tx_mac(atgep);
+ atge_l1c_stop_rx_mac(atgep);
+ reg = INL(atgep, ATGE_DMA_CFG);
+ reg &= ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
+ OUTL(atgep, ATGE_DMA_CFG, reg);
+ /*
+ * Disable queue processing.
+ */
+ /* Stop TxQ */
+ reg = INL(atgep, L1C_TXQ_CFG);
+ reg = reg & ~TXQ_CFG_ENB;
+ OUTL(atgep, L1C_TXQ_CFG, reg);
+ /* Stop RxQ */
+ reg = INL(atgep, ATGE_RXQ_CFG);
+ reg = reg & ~RXQ_CFG_ENB;
+ OUTL(atgep, ATGE_RXQ_CFG, reg);
+ break;
}
for (t = ATGE_RESET_TIMEOUT; t > 0; t--) {
@@ -2261,13 +2700,15 @@
void
atge_device_init(atge_t *atgep)
{
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
atgep->atge_intrs = L1E_INTRS;
atgep->atge_int_mod = ATGE_IM_TIMER_DEFAULT;
atge_l1e_init_tx_ring(atgep);
atge_l1e_init_rx_pages(atgep);
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ break;
+ case ATGE_CHIP_L1:
atgep->atge_intrs = L1_INTRS | INTR_GPHY | INTR_PHY_LINK_DOWN |
INTR_LINK_CHG;
atgep->atge_int_mod = ATGE_IM_TIMER_DEFAULT;
@@ -2277,6 +2718,22 @@
atge_l1_init_rr_ring(atgep);
atge_l1_init_cmb(atgep);
atge_l1_init_smb(atgep);
+ break;
+ case ATGE_CHIP_L1C:
+ atgep->atge_intrs = L1C_INTRS | L1C_INTR_GPHY |
+ L1C_INTR_PHY_LINK_DOWN;
+ atgep->atge_int_rx_mod = 400/2;
+ atgep->atge_int_tx_mod = 2000/1;
+
+ atge_l1c_init_tx_ring(atgep);
+ atge_l1c_init_rx_ring(atgep);
+ atge_l1c_init_rr_ring(atgep);
+ atge_l1c_init_cmb(atgep);
+ atge_l1c_init_smb(atgep);
+
+ /* Enable all clocks. */
+ OUTL(atgep, ATGE_CLK_GATING_CFG, 0);
+ break;
}
}
@@ -2311,7 +2768,6 @@
static int
atge_send_a_packet(atge_t *atgep, mblk_t *mp)
{
- atge_tx_desc_t *txd;
uchar_t *c;
uint32_t cflags = 0;
atge_ring_t *r;
@@ -2361,17 +2817,40 @@
r->r_avail_desc--;
c = (uchar_t *)r->r_desc_ring->addr;
- c += (sizeof (atge_tx_desc_t) * start);
- txd = (atge_tx_desc_t *)c;
-
- ATGE_PUT64(r->r_desc_ring, &txd->addr,
- r->r_buf_tbl[start]->cookie.dmac_laddress);
-
- ATGE_PUT32(r->r_desc_ring, &txd->len, ATGE_TX_BYTES(pktlen));
-
- cflags |= ATGE_TD_EOP;
- ATGE_PUT32(r->r_desc_ring, &txd->flags, cflags);
-
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1C:
+ {
+ l1c_tx_desc_t *txd;
+
+ c += (sizeof (l1c_tx_desc_t) * start);
+ txd = (l1c_tx_desc_t *)c;
+
+ ATGE_PUT64(r->r_desc_ring, &txd->addr,
+ r->r_buf_tbl[start]->cookie.dmac_laddress);
+
+ ATGE_PUT32(r->r_desc_ring, &txd->len, L1C_TX_BYTES(pktlen));
+
+ cflags |= L1C_TD_EOP;
+ ATGE_PUT32(r->r_desc_ring, &txd->flags, cflags);
+ break;
+ }
+ default:
+ {
+ atge_tx_desc_t *txd;
+
+ c += (sizeof (atge_tx_desc_t) * start);
+ txd = (atge_tx_desc_t *)c;
+
+ ATGE_PUT64(r->r_desc_ring, &txd->addr,
+ r->r_buf_tbl[start]->cookie.dmac_laddress);
+
+ ATGE_PUT32(r->r_desc_ring, &txd->len, ATGE_TX_BYTES(pktlen));
+
+ cflags |= ATGE_TD_EOP;
+ ATGE_PUT32(r->r_desc_ring, &txd->flags, cflags);
+ break;
+ }
+ }
/*
* Sync buffer first.
*/
@@ -2390,10 +2869,16 @@
/*
* Program TX descriptor to send a packet.
*/
- if (ATGE_MODEL(atgep) == ATGE_CHIP_L1E) {
+ switch (ATGE_MODEL(atgep)) {
+ case ATGE_CHIP_L1E:
atge_l1e_send_packet(r);
- } else if (ATGE_MODEL(atgep) == ATGE_CHIP_L1) {
+ break;
+ case ATGE_CHIP_L1:
atge_l1_send_packet(r);
+ break;
+ case ATGE_CHIP_L1C:
+ atge_l1c_send_packet(r);
+ break;
}
r->r_atge->atge_opackets++;
--- a/usr/src/uts/common/io/atge/atge_mii.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/atge/atge_mii.c Sun Aug 12 11:56:48 2012 +0100
@@ -1,3 +1,29 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2012 Gary Mills
+ *
+ * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
+ */
/*
* Copyright (c) 2008, Pyun YongHyeon <[email protected]>
* All rights reserved.
@@ -30,6 +56,7 @@
#include "atge.h"
#include "atge_cmn_reg.h"
+#include "atge_l1c_reg.h"
#include "atge_l1e_reg.h"
#include "atge_l1_reg.h"
@@ -90,7 +117,7 @@
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
for (i = PHY_TIMEOUT; i > 0; i--) {
- drv_usecwait(1);
+ drv_usecwait(5);
v = INL(atgep, ATGE_MDIO);
if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
break;
@@ -210,3 +237,147 @@
atge_mii_write(atgep, phyaddr, ATPHY_DBG_DATA, 0x024E);
}
}
+
+void
+atge_l1c_mii_reset(void *arg)
+{
+ atge_t *atgep = arg;
+ uint16_t data;
+ int phyaddr;
+
+ phyaddr = mii_get_addr(atgep->atge_mii);
+
+ /* Reset magic from Linux, via Freebsd */
+ OUTW(atgep, ATGE_GPHY_CTRL,
+ GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET);
+ (void) INW(atgep, ATGE_GPHY_CTRL);
+ drv_usecwait(10 * 1000);
+
+ OUTW(atgep, ATGE_GPHY_CTRL,
+ GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
+ GPHY_CTRL_SEL_ANA_RESET);
+ (void) INW(atgep, ATGE_GPHY_CTRL);
+ drv_usecwait(10 * 1000);
+
+ /*
+ * Some fast ethernet chips may not be able to auto-nego with
+ * switches even though they have 1000T based PHY. Hence we need
+ * to write 0 to MII_MSCONTROL control register.
+ */
+ if (atgep->atge_flags & ATGE_FLAG_FASTETHER)
+ atge_mii_write(atgep, phyaddr, MII_MSCONTROL, 0x0);
+
+ /* DSP fixup, Vendor magic. */
+ switch (ATGE_DID(atgep)) {
+ uint16_t reg;
+
+ case ATGE_CHIP_AR8152V1_DEV_ID:
+ atge_mii_write(atgep, phyaddr, ATPHY_DBG_ADDR, 0x000A);
+ reg = atge_mii_read(atgep, phyaddr, ATPHY_DBG_DATA);
+ atge_mii_write(atgep, phyaddr, ATPHY_DBG_DATA, reg & 0xDFFF);
+ /* FALLTHROUGH */
+ case ATGE_CHIP_AR8151V2_DEV_ID:
+ case ATGE_CHIP_AR8151V1_DEV_ID:
+ case ATGE_CHIP_AR8152V2_DEV_ID:
+ atge_mii_write(atgep, phyaddr, ATPHY_DBG_ADDR, 0x003B);
+ reg = atge_mii_read(atgep, phyaddr, ATPHY_DBG_DATA);
+ atge_mii_write(atgep, phyaddr, ATPHY_DBG_DATA, reg & 0xFFF7);
+ drv_usecwait(20 * 1000);
+ break;
+ }
+
+ switch (ATGE_DID(atgep)) {
+ case ATGE_CHIP_AR8151V1_DEV_ID:
+ atge_mii_write(atgep, phyaddr, ATPHY_DBG_ADDR, 0x0029);
+ atge_mii_write(atgep, phyaddr, ATPHY_DBG_DATA, 0x929D);
+ break;
+ case ATGE_CHIP_AR8151V2_DEV_ID:
+ case ATGE_CHIP_AR8152V2_DEV_ID:
+ case ATGE_CHIP_L1CG_DEV_ID:
+ case ATGE_CHIP_L1CF_DEV_ID:
+ atge_mii_write(atgep, phyaddr, ATPHY_DBG_ADDR, 0x0029);
+ atge_mii_write(atgep, phyaddr, ATPHY_DBG_DATA, 0xB6DD);
+ break;
+ }
+
+ /* Load DSP codes, vendor magic. */
+ data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
+ ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) &
+ ANA_INTERVAL_SEL_TIMER_MASK);
+ atge_mii_write(atgep, phyaddr,
+ ATPHY_DBG_ADDR, MII_ANA_CFG18);
+ atge_mii_write(atgep, phyaddr,
+ ATPHY_DBG_DATA, data);
+
+ data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) |
+ ANA_MS_PAD_DBG | ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP |
+ ANA_SERDES_EN_PLL | ANA_SERDES_EN_LCKDT;
+ atge_mii_write(atgep, phyaddr,
+ ATPHY_DBG_ADDR, MII_ANA_CFG5);
+ atge_mii_write(atgep, phyaddr,
+ ATPHY_DBG_DATA, data);
+
+ data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) &
+ ANA_LONG_CABLE_TH_100_MASK) |
+ ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) &
+ ANA_SHORT_CABLE_TH_100_SHIFT) |
+ ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW;
+ atge_mii_write(atgep, phyaddr,
+ ATPHY_DBG_ADDR, MII_ANA_CFG54);
+ atge_mii_write(atgep, phyaddr,
+ ATPHY_DBG_DATA, data);
+
+ data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) |
+ ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) |
+ ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) |
+ ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK);
+ atge_mii_write(atgep, phyaddr,
+ ATPHY_DBG_ADDR, MII_ANA_CFG4);
+ atge_mii_write(atgep, phyaddr,
+ ATPHY_DBG_DATA, data);
+
+ data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) |
+ ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB |
+ ANA_OEN_125M;
+ atge_mii_write(atgep, phyaddr,
+ ATPHY_DBG_ADDR, MII_ANA_CFG0);
+ atge_mii_write(atgep, phyaddr,
+ ATPHY_DBG_DATA, data);
+ drv_usecwait(1000);
+}
+
+uint16_t
+atge_l1c_mii_read(void *arg, uint8_t phy, uint8_t reg)
+{
+
+ if (phy != 0) {
+ /* avoid PHY address alias */
+ return (0xffffU);
+ }
+
+ return (atge_mii_read(arg, phy, reg));
+}
+
+void
+atge_l1c_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val)
+{
+
+ if (phy != 0) {
+ /* avoid PHY address alias */
+ return;
+ }
+
+ if (reg == MII_CONTROL) {
+ /*
+ * Don't issue a reset if MII_CONTROL_RESET is set.
+ * Otherwise it occasionally
+ * advertises incorrect capability.
+ */
+ if ((val & MII_CONTROL_RESET) == 0) {
+ /* RESET bit is required to set mode */
+ atge_mii_write(arg, phy, reg, val | MII_CONTROL_RESET);
+ }
+ } else {
+ atge_mii_write(arg, phy, reg, val);
+ }
+}
--- a/usr/src/uts/common/io/comstar/port/iscsit/iscsit.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/comstar/port/iscsit/iscsit.c Sun Aug 12 11:56:48 2012 +0100
@@ -20,9 +20,8 @@
*/
/*
* Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- */
-/*
- * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
+ *
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
#include <sys/cpuvar.h>
@@ -3161,9 +3160,21 @@
mutex_exit(&ict->ict_mutex);
index = ntohl(cmdsn) % ISCSIT_RXPDU_QUEUE_LEN;
- ASSERT(cbuf->cb_buffer[index] == NULL);
- cbuf->cb_buffer[index] = rx_pdu;
- cbuf->cb_num_elems++;
+ /*
+ * In the normal case, assuming that the Initiator is not
+ * buggy and that we don't have packet duplication occuring,
+ * the entry in the array will be NULL. However, we may have
+ * received a duplicate PDU with cmdsn > expsn , and in that
+ * case we just ignore this PDU -- the previously received one
+ * remains queued for processing. We need to be careful not
+ * to leak this one however.
+ */
+ if (cbuf->cb_buffer[index] != NULL) {
+ idm_pdu_complete(rx_pdu, IDM_STATUS_FAIL);
+ } else {
+ cbuf->cb_buffer[index] = rx_pdu;
+ cbuf->cb_num_elems++;
+ }
}
static idm_pdu_t *
--- a/usr/src/uts/common/io/ixgbe/ixgbe_82598.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_82598.c Sun Aug 12 11:56:48 2012 +0100
@@ -1,6 +1,6 @@
/******************************************************************************
- Copyright (c) 2001-2010, Intel Corporation
+ Copyright (c) 2001-2012, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,49 +30,36 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
#include "ixgbe_type.h"
+#include "ixgbe_82598.h"
#include "ixgbe_api.h"
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
-u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
-s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *autoneg);
+ ixgbe_link_speed *speed,
+ bool *autoneg);
static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
-s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
- bool autoneg_wait_to_complete);
+ bool autoneg_wait_to_complete);
static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed, bool *link_up,
- bool link_up_wait_to_complete);
+ ixgbe_link_speed *speed, bool *link_up,
+ bool link_up_wait_to_complete);
static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
+ ixgbe_link_speed speed,
+ bool autoneg,
+ bool autoneg_wait_to_complete);
static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
+ ixgbe_link_speed speed,
+ bool autoneg,
+ bool autoneg_wait_to_complete);
static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
-s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);
-void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw);
-s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
-s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
- u32 vind, bool vlan_on);
static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
-s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
-s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
-s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
- u8 *eeprom_data);
-u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
-s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
-void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
-void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
+static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
+ u32 headroom, int strategy);
/**
* ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
@@ -117,31 +104,6 @@
}
/**
- * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
- * @hw: pointer to hardware structure
- *
- * Read PCIe configuration space, and get the MSI-X vector count from
- * the capabilities table.
- **/
-u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
-{
- u32 msix_count = 18;
-
- DEBUGFUNC("ixgbe_get_pcie_msix_count_82598");
-
- if (hw->mac.msix_vectors_from_pcie) {
- msix_count = IXGBE_READ_PCIE_WORD(hw,
- IXGBE_PCIE_MSIX_82598_CAPS);
- msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
-
- /* MSI-X count is zero-based in HW, so increment to give
- * proper value */
- msix_count++;
- }
- return msix_count;
-}
-
-/**
* ixgbe_init_ops_82598 - Inits func ptrs and MAC type
* @hw: pointer to hardware structure
*
@@ -168,7 +130,7 @@
mac->ops.reset_hw = &ixgbe_reset_hw_82598;
mac->ops.get_media_type = &ixgbe_get_media_type_82598;
mac->ops.get_supported_physical_layer =
- &ixgbe_get_supported_physical_layer_82598;
+ &ixgbe_get_supported_physical_layer_82598;
mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
@@ -177,18 +139,19 @@
mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
mac->ops.set_vfta = &ixgbe_set_vfta_82598;
+ mac->ops.set_vlvf = NULL;
mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
/* Flow Control */
mac->ops.fc_enable = &ixgbe_fc_enable_82598;
- mac->mcft_size = 128;
- mac->vft_size = 128;
- mac->num_rar_entries = 16;
- mac->rx_pb_size = 512;
- mac->max_tx_queues = 32;
- mac->max_rx_queues = 64;
- mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
+ mac->mcft_size = 128;
+ mac->vft_size = 128;
+ mac->num_rar_entries = 16;
+ mac->rx_pb_size = 512;
+ mac->max_tx_queues = 32;
+ mac->max_rx_queues = 64;
+ mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
/* SFP+ Module */
phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
@@ -197,8 +160,11 @@
mac->ops.check_link = &ixgbe_check_mac_link_82598;
mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
mac->ops.flap_tx_laser = NULL;
- mac->ops.get_link_capabilities =
- &ixgbe_get_link_capabilities_82598;
+ mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
+ mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
+
+ /* Manageability interface */
+ mac->ops.set_fw_drv_ver = NULL;
return ret_val;
}
@@ -228,7 +194,7 @@
if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
mac->ops.get_link_capabilities =
- &ixgbe_get_copper_link_capabilities_generic;
+ &ixgbe_get_copper_link_capabilities_generic;
}
switch (hw->phy.type) {
@@ -236,11 +202,7 @@
phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
phy->ops.check_link = &ixgbe_check_phy_link_tnx;
phy->ops.get_firmware_version =
- &ixgbe_get_phy_firmware_version_tnx;
- break;
- case ixgbe_phy_aq:
- phy->ops.get_firmware_version =
- &ixgbe_get_phy_firmware_version_generic;
+ &ixgbe_get_phy_firmware_version_tnx;
break;
case ixgbe_phy_nl:
phy->ops.reset = &ixgbe_reset_phy_nl;
@@ -256,8 +218,8 @@
/* Check to see if SFP+ module is supported */
ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
- &list_offset,
- &data_offset);
+ &list_offset,
+ &data_offset);
if (ret_val != IXGBE_SUCCESS) {
ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
goto out;
@@ -293,15 +255,15 @@
for (i = 0; ((i < hw->mac.max_tx_queues) &&
(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
- regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+ regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
}
for (i = 0; ((i < hw->mac.max_rx_queues) &&
(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
- regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
- IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+ regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
+ IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
}
@@ -321,8 +283,8 @@
* Determines the link capabilities by reading the AUTOC register.
**/
static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *autoneg)
+ ixgbe_link_speed *speed,
+ bool *autoneg)
{
s32 status = IXGBE_SUCCESS;
u32 autoc = 0;
@@ -389,7 +351,6 @@
switch (hw->phy.type) {
case ixgbe_phy_cu_unknown:
case ixgbe_phy_tn:
- case ixgbe_phy_aq:
media_type = ixgbe_media_type_copper;
goto out;
default:
@@ -430,22 +391,41 @@
/**
* ixgbe_fc_enable_82598 - Enable flow control
* @hw: pointer to hardware structure
- * @packetbuf_num: packet buffer number (0-7)
*
* Enable flow control according to the current settings.
**/
-s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
+s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
{
s32 ret_val = IXGBE_SUCCESS;
u32 fctrl_reg;
u32 rmcs_reg;
u32 reg;
- u32 rx_pba_size;
+ u32 fcrtl, fcrth;
u32 link_speed = 0;
+ int i;
bool link_up;
DEBUGFUNC("ixgbe_fc_enable_82598");
+ /* Validate the water mark configuration */
+ if (!hw->fc.pause_time) {
+ ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+ goto out;
+ }
+
+ /* Low water mark of zero causes XOFF floods */
+ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
+ if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
+ hw->fc.high_water[i]) {
+ if (!hw->fc.low_water[i] ||
+ hw->fc.low_water[i] >= hw->fc.high_water[i]) {
+ DEBUGOUT("Invalid water mark configuration\n");
+ ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+ goto out;
+ }
+ }
+ }
+
/*
* On 82598 having Rx FC on causes resets while doing 1G
* so if it's on turn it off once we know link_speed. For
@@ -467,9 +447,7 @@
}
/* Negotiate the fc mode to use */
- ret_val = ixgbe_fc_autoneg(hw);
- if (ret_val == IXGBE_ERR_FLOW_CONTROL)
- goto out;
+ ixgbe_fc_autoneg(hw);
/* Disable any previous flow control settings */
fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
@@ -530,31 +508,27 @@
IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
/* Set up and enable Rx high/low water mark thresholds, enable XON. */
- if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
- rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
- rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
+ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
+ if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
+ hw->fc.high_water[i]) {
+ fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
+ fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
+ IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
+ IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
+ } else {
+ IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
+ IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
+ }
- reg = (rx_pba_size - hw->fc.low_water) << 6;
- if (hw->fc.send_xon)
- reg |= IXGBE_FCRTL_XONE;
-
- IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
-
- reg = (rx_pba_size - hw->fc.high_water) << 6;
- reg |= IXGBE_FCRTH_FCEN;
-
- IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
}
/* Configure pause time (2 TCs per register) */
- reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
- if ((packetbuf_num & 1) == 0)
- reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
- else
- reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
- IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
+ reg = hw->fc.pause_time * 0x00010001;
+ for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
+ IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
- IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
+ /* Configure flow control refresh threshold value */
+ IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
out:
return ret_val;
@@ -568,7 +542,7 @@
* Restarts the link. Performs autonegotiation if needed.
**/
static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
- bool autoneg_wait_to_complete)
+ bool autoneg_wait_to_complete)
{
u32 autoc_reg;
u32 links_reg;
@@ -626,7 +600,7 @@
for (timeout = 0;
timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
(an_reg & IXGBE_MII_AUTONEG_LINK_UP))
@@ -653,8 +627,8 @@
* Reads the links register to determine if link is up and the current speed
**/
static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed, bool *link_up,
- bool link_up_wait_to_complete)
+ ixgbe_link_speed *speed, bool *link_up,
+ bool link_up_wait_to_complete)
{
u32 links_reg;
u32 i;
@@ -672,7 +646,7 @@
hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
- &adapt_comp_reg);
+ &adapt_comp_reg);
if (link_up_wait_to_complete) {
for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
if ((link_reg & 1) &&
@@ -684,11 +658,11 @@
}
msec_delay(100);
hw->phy.ops.read_reg(hw, 0xC79F,
- IXGBE_TWINAX_DEV,
- &link_reg);
+ IXGBE_TWINAX_DEV,
+ &link_reg);
hw->phy.ops.read_reg(hw, 0xC00C,
- IXGBE_TWINAX_DEV,
- &adapt_comp_reg);
+ IXGBE_TWINAX_DEV,
+ &adapt_comp_reg);
}
} else {
if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
@@ -729,11 +703,6 @@
(ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
*link_up = FALSE;
- /* if link is down, zero out the current_mode */
- if (*link_up == FALSE) {
- hw->fc.current_mode = ixgbe_fc_none;
- hw->fc.fc_was_autonegged = FALSE;
- }
out:
return IXGBE_SUCCESS;
}
@@ -748,19 +717,21 @@
* Set the link speed in the AUTOC register and restarts link.
**/
static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete)
+ ixgbe_link_speed speed, bool autoneg,
+ bool autoneg_wait_to_complete)
{
- s32 status = IXGBE_SUCCESS;
+ s32 status;
ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
- u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- u32 autoc = curr_autoc;
- u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
+ u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+ u32 autoc = curr_autoc;
+ u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
DEBUGFUNC("ixgbe_setup_mac_link_82598");
/* Check to see if speed passed in is supported. */
- (void) ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
+ status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
+ if (status != IXGBE_SUCCESS)
+ return (status);
speed &= link_capabilities;
if (speed == IXGBE_LINK_SPEED_UNKNOWN)
@@ -768,7 +739,7 @@
/* Set KX4/KX support according to speed requested */
else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
- link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
+ link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
if (speed & IXGBE_LINK_SPEED_10GB_FULL)
autoc |= IXGBE_AUTOC_KX4_SUPP;
@@ -785,7 +756,7 @@
* stored values
*/
status = ixgbe_start_mac_link_82598(hw,
- autoneg_wait_to_complete);
+ autoneg_wait_to_complete);
}
return status;
@@ -802,9 +773,9 @@
* Sets the link speed in the AUTOC register in the MAC and restarts link.
**/
static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete)
+ ixgbe_link_speed speed,
+ bool autoneg,
+ bool autoneg_wait_to_complete)
{
s32 status;
@@ -812,9 +783,12 @@
/* Setup the PHY according to input speed */
status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
- autoneg_wait_to_complete);
- /* Set up MAC */
- (void) ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
+ autoneg_wait_to_complete);
+ if (status == IXGBE_SUCCESS) {
+ /* Set up MAC */
+ status =
+ ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
+ }
return status;
}
@@ -840,7 +814,9 @@
DEBUGFUNC("ixgbe_reset_hw_82598");
/* Call adapter stop to disable tx/rx and clear interrupts */
- hw->mac.ops.stop_adapter(hw);
+ status = hw->mac.ops.stop_adapter(hw);
+ if (status != IXGBE_SUCCESS)
+ goto reset_hw_out;
/*
* Power up the Atlas Tx lanes if they are currently powered down.
@@ -851,28 +827,28 @@
if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
/* Enable Tx Atlas so packets can be transmitted again */
hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
- &analog_val);
+ &analog_val);
analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
- analog_val);
+ analog_val);
hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
- &analog_val);
+ &analog_val);
analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
- analog_val);
+ analog_val);
hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
- &analog_val);
+ &analog_val);
analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
- analog_val);
+ analog_val);
hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
- &analog_val);
+ &analog_val);
analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
- analog_val);
+ analog_val);
}
/* Reset PHY */
@@ -883,26 +859,19 @@
phy_status = hw->phy.ops.init(hw);
if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
goto reset_hw_out;
- else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
- goto no_phy_reset;
+ if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
+ goto mac_reset_top;
hw->phy.ops.reset(hw);
}
-no_phy_reset:
- /*
- * Prevent the PCI-E bus from from hanging by disabling PCI-E master
- * access and verify no pending requests before reset
- */
- (void) ixgbe_disable_pcie_master(hw);
-
mac_reset_top:
/*
* Issue global reset to the MAC. This needs to be a SW reset.
* If link reset is used, it might reset the MAC when mng is using it
*/
- ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
- IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
+ ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
+ IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
IXGBE_WRITE_FLUSH(hw);
/* Poll for reset bit to self-clear indicating reset is complete */
@@ -917,21 +886,18 @@
DEBUGOUT("Reset polling failed to complete.\n");
}
+ msec_delay(50);
+
/*
* Double resets are required for recovery from certain error
* conditions. Between resets, it is necessary to stall to allow time
- * for any pending HW events to complete. We use 1usec since that is
- * what is needed for ixgbe_disable_pcie_master(). The second reset
- * then clears out any effects of those events.
+ * for any pending HW events to complete.
*/
if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
- usec_delay(1);
goto mac_reset_top;
}
- msec_delay(50);
-
gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
@@ -1002,7 +968,7 @@
u32 rar_high;
u32 rar_entries = hw->mac.num_rar_entries;
- UNREFERENCED_PARAMETER(vmdq);
+ UNREFERENCED_1PARAMETER(vmdq);
/* Make sure we are using a valid rar index range */
if (rar >= rar_entries) {
@@ -1029,7 +995,7 @@
* Turn on/off specified VLAN in the VLAN filter table.
**/
s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
- bool vlan_on)
+ bool vlan_on)
{
u32 regindex;
u32 bitindex;
@@ -1088,7 +1054,7 @@
for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
for (offset = 0; offset < hw->mac.vft_size; offset++)
IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
- 0);
+ 0);
return IXGBE_SUCCESS;
}
@@ -1108,7 +1074,7 @@
DEBUGFUNC("ixgbe_read_analog_reg8_82598");
IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
- IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
+ IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
IXGBE_WRITE_FLUSH(hw);
usec_delay(10);
atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
@@ -1148,7 +1114,7 @@
* Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
**/
s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
- u8 *eeprom_data)
+ u8 *eeprom_data)
{
s32 status = IXGBE_SUCCESS;
u16 sfp_addr = 0;
@@ -1167,16 +1133,16 @@
sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
hw->phy.ops.write_reg(hw,
- IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- sfp_addr);
+ IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
+ IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+ sfp_addr);
/* Poll status */
for (i = 0; i < 100; i++) {
hw->phy.ops.read_reg(hw,
- IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- &sfp_stat);
+ IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
+ IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+ &sfp_stat);
sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
break;
@@ -1191,7 +1157,7 @@
/* Read data */
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
+ IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
*eeprom_data = (u8)(sfp_data >> 8);
} else {
@@ -1225,7 +1191,6 @@
* physical layer because 10GBase-T PHYs use LMS = KX4/KX */
switch (hw->phy.type) {
case ixgbe_phy_tn:
- case ixgbe_phy_aq:
case ixgbe_phy_cu_unknown:
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
@@ -1356,16 +1321,57 @@
for (i = 0; ((i < hw->mac.max_tx_queues) &&
(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
- regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+ regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
}
for (i = 0; ((i < hw->mac.max_rx_queues) &&
(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
- regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
- IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+ regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
+ IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
}
}
+
+/**
+ * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
+ * @hw: pointer to hardware structure
+ * @num_pb: number of packet buffers to allocate
+ * @headroom: reserve n KB of headroom
+ * @strategy: packet buffer allocation strategy
+ **/
+static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
+ u32 headroom, int strategy)
+{
+ u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
+ u8 i = 0;
+ UNREFERENCED_1PARAMETER(headroom);
+
+ if (!num_pb)
+ return;
+
+ /* Setup Rx packet buffer sizes */
+ switch (strategy) {
+ case PBA_STRATEGY_WEIGHTED:
+ /* Setup the first four at 80KB */
+ rxpktsize = IXGBE_RXPBSIZE_80KB;
+ for (; i < 4; i++)
+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
+ /* Setup the last four at 48KB...don't re-init i */
+ rxpktsize = IXGBE_RXPBSIZE_48KB;
+ /* Fall Through */
+ /* FALLTHRU */
+ case PBA_STRATEGY_EQUAL:
+ default:
+ /* Divide the remaining Rx packet buffer evenly among the TCs */
+ for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
+ break;
+ }
+
+ /* Setup Tx packet buffer sizes */
+ for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
+ IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_82598.h Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,52 @@
+/******************************************************************************
+
+ Copyright (c) 2001-2012, Intel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+******************************************************************************/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.h,v 1.2 2012/07/05 20:51:44 jfv Exp $*/
+
+#ifndef _IXGBE_82598_H_
+#define _IXGBE_82598_H_
+
+u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
+s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw);
+s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);
+void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw);
+s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
+s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on);
+s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
+s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
+s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
+ u8 *eeprom_data);
+u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
+s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
+void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
+void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
+#endif /* _IXGBE_82598_H_ */
--- a/usr/src/uts/common/io/ixgbe/ixgbe_82599.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_82599.c Sun Aug 12 11:56:48 2012 +0100
@@ -30,50 +30,23 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.8 2012/07/05 20:51:44 jfv Exp $*/
#include "ixgbe_type.h"
+#include "ixgbe_82599.h"
#include "ixgbe_api.h"
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
-s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
-s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *autoneg);
-enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
-void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
-void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
-void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
-s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete);
-s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete);
-s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
- bool autoneg_wait_to_complete);
-s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
-s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);
-void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);
-s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
-s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
-s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
-s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw);
-s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
-s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
-u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
-s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
+ ixgbe_link_speed speed,
+ bool autoneg,
+ bool autoneg_wait_to_complete);
static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
-bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
-
+static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
+ u16 offset, u16 *data);
+static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data);
void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
{
@@ -84,9 +57,9 @@
/* enable the laser control functions for SFP+ fiber */
if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
mac->ops.disable_tx_laser =
- &ixgbe_disable_tx_laser_multispeed_fiber;
+ &ixgbe_disable_tx_laser_multispeed_fiber;
mac->ops.enable_tx_laser =
- &ixgbe_enable_tx_laser_multispeed_fiber;
+ &ixgbe_enable_tx_laser_multispeed_fiber;
mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
} else {
@@ -141,7 +114,7 @@
if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
mac->ops.get_link_capabilities =
- &ixgbe_get_copper_link_capabilities_generic;
+ &ixgbe_get_copper_link_capabilities_generic;
}
/* Set necessary function pointers based on phy type */
@@ -150,11 +123,7 @@
phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
phy->ops.check_link = &ixgbe_check_phy_link_tnx;
phy->ops.get_firmware_version =
- &ixgbe_get_phy_firmware_version_tnx;
- break;
- case ixgbe_phy_aq:
- phy->ops.get_firmware_version =
- &ixgbe_get_phy_firmware_version_generic;
+ &ixgbe_get_phy_firmware_version_tnx;
break;
default:
break;
@@ -178,12 +147,13 @@
hw->phy.ops.reset = NULL;
ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
- &data_offset);
+ &data_offset);
if (ret_val != IXGBE_SUCCESS)
goto setup_sfp_out;
/* PHY config will finish before releasing the semaphore */
- ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
+ ret_val = hw->mac.ops.acquire_swfw_sync(hw,
+ IXGBE_GSSR_MAC_CSR_SM);
if (ret_val != IXGBE_SUCCESS) {
ret_val = IXGBE_ERR_SWFW_SYNC;
goto setup_sfp_out;
@@ -197,14 +167,14 @@
}
/* Release the semaphore */
- ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
/* Delay obtaining semaphore again to allow FW access */
msec_delay(hw->eeprom.semaphore_delay);
/* Now restart DSP by setting Restart_AN and clearing LMS */
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
- IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
- IXGBE_AUTOC_AN_RESTART));
+ IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
+ IXGBE_AUTOC_AN_RESTART));
/* Wait for AN to leave state 0 */
for (i = 0; i < 10; i++) {
@@ -221,8 +191,8 @@
/* Restart DSP by setting Restart_AN and return to SFI mode */
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
- IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
- IXGBE_AUTOC_AN_RESTART));
+ IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
+ IXGBE_AUTOC_AN_RESTART));
}
setup_sfp_out:
@@ -241,6 +211,7 @@
{
struct ixgbe_mac_info *mac = &hw->mac;
struct ixgbe_phy_info *phy = &hw->phy;
+ struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
s32 ret_val;
DEBUGFUNC("ixgbe_init_ops_82599");
@@ -257,11 +228,13 @@
mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
mac->ops.get_media_type = &ixgbe_get_media_type_82599;
mac->ops.get_supported_physical_layer =
- &ixgbe_get_supported_physical_layer_82599;
+ &ixgbe_get_supported_physical_layer_82599;
+ mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
+ mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
- mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599;
+ mac->ops.start_hw = &ixgbe_start_hw_82599;
mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
@@ -270,10 +243,12 @@
/* RAR, Multicast, VLAN */
mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
+ mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
mac->rar_highwater = 1;
mac->ops.set_vfta = &ixgbe_set_vfta_generic;
+ mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
@@ -282,16 +257,30 @@
/* Link */
mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
- mac->ops.check_link = &ixgbe_check_mac_link_generic;
+ mac->ops.check_link = &ixgbe_check_mac_link_generic;
+ mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
ixgbe_init_mac_link_ops_82599(hw);
- mac->mcft_size = 128;
- mac->vft_size = 128;
- mac->num_rar_entries = 128;
- mac->rx_pb_size = 512;
- mac->max_tx_queues = 128;
- mac->max_rx_queues = 128;
- mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
+ mac->mcft_size = 128;
+ mac->vft_size = 128;
+ mac->num_rar_entries = 128;
+ mac->rx_pb_size = 512;
+ mac->max_tx_queues = 128;
+ mac->max_rx_queues = 128;
+ mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
+
+ mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
+ IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
+
+ hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
+
+ /* EEPROM */
+ eeprom->ops.read = &ixgbe_read_eeprom_82599;
+ eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
+
+ /* Manageability interface */
+ mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
+
return ret_val;
}
@@ -305,8 +294,8 @@
* Determines the link capabilities by reading the AUTOC register.
**/
s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *negotiation)
+ ixgbe_link_speed *speed,
+ bool *negotiation)
{
s32 status = IXGBE_SUCCESS;
u32 autoc = 0;
@@ -316,7 +305,9 @@
/* Check if 1G SFP module. */
if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
*speed = IXGBE_LINK_SPEED_1GB_FULL;
*negotiation = TRUE;
goto out;
@@ -388,7 +379,7 @@
if (hw->phy.multispeed_fiber) {
*speed |= IXGBE_LINK_SPEED_10GB_FULL |
- IXGBE_LINK_SPEED_1GB_FULL;
+ IXGBE_LINK_SPEED_1GB_FULL;
*negotiation = TRUE;
}
@@ -412,7 +403,6 @@
switch (hw->phy.type) {
case ixgbe_phy_cu_unknown:
case ixgbe_phy_tn:
- case ixgbe_phy_aq:
media_type = ixgbe_media_type_copper;
goto out;
default:
@@ -459,7 +449,7 @@
* Restarts the link. Performs autonegotiation if needed.
**/
s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
- bool autoneg_wait_to_complete)
+ bool autoneg_wait_to_complete)
{
u32 autoc_reg;
u32 links_reg;
@@ -573,8 +563,8 @@
* Set the link speed in the AUTOC register and restarts link.
**/
s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete)
+ ixgbe_link_speed speed, bool autoneg,
+ bool autoneg_wait_to_complete)
{
s32 status = IXGBE_SUCCESS;
ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
@@ -619,9 +609,9 @@
msec_delay(40);
status = ixgbe_setup_mac_link_82599(hw,
- IXGBE_LINK_SPEED_10GB_FULL,
- autoneg,
- autoneg_wait_to_complete);
+ IXGBE_LINK_SPEED_10GB_FULL,
+ autoneg,
+ autoneg_wait_to_complete);
if (status != IXGBE_SUCCESS)
return status;
@@ -639,7 +629,7 @@
/* If we have link, just jump out */
status = ixgbe_check_link(hw, &link_speed,
- &link_up, FALSE);
+ &link_up, FALSE);
if (status != IXGBE_SUCCESS)
return status;
@@ -699,7 +689,7 @@
*/
if (speedcnt > 1)
status = ixgbe_setup_mac_link_multispeed_fiber(hw,
- highest_link_speed, autoneg, autoneg_wait_to_complete);
+ highest_link_speed, autoneg, autoneg_wait_to_complete);
out:
/* Set autoneg_advertised value based on input link speed */
@@ -724,8 +714,8 @@
* Implements the Intel SmartSpeed algorithm.
**/
s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete)
+ ixgbe_link_speed speed, bool autoneg,
+ bool autoneg_wait_to_complete)
{
s32 status = IXGBE_SUCCESS;
ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
@@ -837,8 +827,8 @@
* Set the link speed in the AUTOC register and restarts link.
**/
s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete)
+ ixgbe_link_speed speed, bool autoneg,
+ bool autoneg_wait_to_complete)
{
s32 status = IXGBE_SUCCESS;
u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
@@ -886,8 +876,8 @@
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
autoc |= IXGBE_AUTOC_KX_SUPP;
} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
- (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
- link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
+ (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
+ link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
/* Switch from 1G SFI to 10G SFI if requested */
if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
(pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
@@ -895,7 +885,7 @@
autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
}
} else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
- (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
+ (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
/* Switch from 10G SFI to 1G SFI if requested */
if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
(pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
@@ -951,9 +941,9 @@
* Restarts link on PHY and MAC based on settings passed in.
**/
static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete)
+ ixgbe_link_speed speed,
+ bool autoneg,
+ bool autoneg_wait_to_complete)
{
s32 status;
@@ -961,9 +951,12 @@
/* Setup the PHY according to input speed */
status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
- autoneg_wait_to_complete);
- /* Set up MAC */
- (void) ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
+ autoneg_wait_to_complete);
+ if (status == IXGBE_SUCCESS) {
+ /* Set up MAC */
+ status =
+ ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
+ }
return status;
}
@@ -978,16 +971,20 @@
**/
s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
{
- s32 status = IXGBE_SUCCESS;
- u32 ctrl;
- u32 i;
- u32 autoc;
- u32 autoc2;
+ ixgbe_link_speed link_speed;
+ s32 status;
+ u32 ctrl, i, autoc, autoc2;
+ bool link_up = FALSE;
DEBUGFUNC("ixgbe_reset_hw_82599");
/* Call adapter stop to disable tx/rx and clear interrupts */
- hw->mac.ops.stop_adapter(hw);
+ status = hw->mac.ops.stop_adapter(hw);
+ if (status != IXGBE_SUCCESS)
+ goto reset_hw_out;
+
+ /* flush pending Tx transactions */
+ ixgbe_clear_tx_pending(hw);
/* PHY ops must be identified and initialized prior to reset */
@@ -1010,48 +1007,49 @@
if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
hw->phy.ops.reset(hw);
- /*
- * Prevent the PCI-E bus from from hanging by disabling PCI-E master
- * access and verify no pending requests before reset
- */
- (void) ixgbe_disable_pcie_master(hw);
-
mac_reset_top:
/*
- * Issue global reset to the MAC. This needs to be a SW reset.
- * If link reset is used, it might reset the MAC when mng is using it
+ * Issue global reset to the MAC. Needs to be SW reset if link is up.
+ * If link reset is used when link is up, it might reset the PHY when
+ * mng is using it. If link is down or the flag to force full link
+ * reset is set, then perform link reset.
*/
- ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
- IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
+ ctrl = IXGBE_CTRL_LNK_RST;
+ if (!hw->force_full_reset) {
+ hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
+ if (link_up)
+ ctrl = IXGBE_CTRL_RST;
+ }
+
+ ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
+ IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
IXGBE_WRITE_FLUSH(hw);
/* Poll for reset bit to self-clear indicating reset is complete */
for (i = 0; i < 10; i++) {
usec_delay(1);
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
- if (!(ctrl & IXGBE_CTRL_RST))
+ if (!(ctrl & IXGBE_CTRL_RST_MASK))
break;
}
- if (ctrl & IXGBE_CTRL_RST) {
+
+ if (ctrl & IXGBE_CTRL_RST_MASK) {
status = IXGBE_ERR_RESET_FAILED;
DEBUGOUT("Reset polling failed to complete.\n");
}
+ msec_delay(50);
+
/*
* Double resets are required for recovery from certain error
* conditions. Between resets, it is necessary to stall to allow time
- * for any pending HW events to complete. We use 1usec since that is
- * what is needed for ixgbe_disable_pcie_master(). The second reset
- * then clears out any effects of those events.
+ * for any pending HW events to complete.
*/
if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
- usec_delay(1);
goto mac_reset_top;
}
- msec_delay(50);
-
/*
* Store the original AUTOC/AUTOC2 values if they have not been
* stored off yet. Otherwise restore the stored original
@@ -1072,7 +1070,7 @@
(hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
autoc2 |= (hw->mac.orig_autoc2 &
- IXGBE_AUTOC2_UPPER_MASK);
+ IXGBE_AUTOC2_UPPER_MASK);
IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
}
}
@@ -1094,7 +1092,10 @@
/* Add the SAN MAC address to the RAR only if it's a valid address */
if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
- hw->mac.san_addr, 0, IXGBE_RAH_AV);
+ hw->mac.san_addr, 0, IXGBE_RAH_AV);
+
+ /* Save the SAN MAC RAR index */
+ hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
/* Reserve the last RAR for the SAN MAC address */
hw->mac.num_rar_entries--;
@@ -1102,7 +1103,7 @@
/* Store the alternative WWNN/WWPN prefix */
hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
- &hw->mac.wwpn_prefix);
+ &hw->mac.wwpn_prefix);
reset_hw_out:
return status;
@@ -1132,7 +1133,7 @@
}
if (i >= IXGBE_FDIRCMD_CMD_POLL) {
DEBUGOUT("Flow Director previous command isn't complete, "
- "aborting table re-initialization. \n");
+ "aborting table re-initialization.\n");
return IXGBE_ERR_FDIR_REINIT_FAILED;
}
@@ -1146,12 +1147,12 @@
* - write 0 to bit 8 of FDIRCMD register
*/
IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
- (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
- IXGBE_FDIRCMD_CLEARHT));
+ (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
+ IXGBE_FDIRCMD_CLEARHT));
IXGBE_WRITE_FLUSH(hw);
IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
- (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
- ~IXGBE_FDIRCMD_CLEARHT));
+ (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
+ ~IXGBE_FDIRCMD_CLEARHT));
IXGBE_WRITE_FLUSH(hw);
/*
* Clear FDIR Hash register to clear any leftover hashes
@@ -1166,7 +1167,7 @@
/* Poll init-done after we write FDIRCTRL register */
for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
- IXGBE_FDIRCTRL_INIT_DONE)
+ IXGBE_FDIRCTRL_INIT_DONE)
break;
usec_delay(10);
}
@@ -1186,63 +1187,15 @@
}
/**
- * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
+ * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
* @hw: pointer to hardware structure
- * @pballoc: which mode to allocate filters with
+ * @fdirctrl: value to write to flow director control register
**/
-s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
+static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
{
- u32 fdirctrl = 0;
- u32 pbsize;
int i;
- DEBUGFUNC("ixgbe_init_fdir_signature_82599");
-
- /*
- * Before enabling Flow Director, the Rx Packet Buffer size
- * must be reduced. The new value is the current size minus
- * flow director memory usage size.
- */
- pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
- (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
-
- /*
- * The defaults in the HW for RX PB 1-7 are not zero and so should be
- * intialized to zero for non DCB mode otherwise actual total RX PB
- * would be bigger than programmed and filter space would run into
- * the PB 0 region.
- */
- for (i = 1; i < 8; i++)
- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
-
- /* Send interrupt when 64 filters are left */
- fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
-
- /* Set the maximum length per hash bucket to 0xA filters */
- fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
-
- switch (pballoc) {
- case IXGBE_FDIR_PBALLOC_64K:
- /* 8k - 1 signature filters */
- fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
- break;
- case IXGBE_FDIR_PBALLOC_128K:
- /* 16k - 1 signature filters */
- fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
- break;
- case IXGBE_FDIR_PBALLOC_256K:
- /* 32k - 1 signature filters */
- fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
- break;
- default:
- /* bad value */
- return IXGBE_ERR_CONFIG;
- };
-
- /* Move the flexible bytes to use the ethertype - shift 6 words */
- fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
-
+ DEBUGFUNC("ixgbe_fdir_enable_82599");
/* Prime the keys for hashing */
IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
@@ -1265,12 +1218,37 @@
IXGBE_WRITE_FLUSH(hw);
for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
- IXGBE_FDIRCTRL_INIT_DONE)
+ IXGBE_FDIRCTRL_INIT_DONE)
break;
msec_delay(1);
}
+
if (i >= IXGBE_FDIR_INIT_DONE_POLL)
- DEBUGOUT("Flow Director Signature poll time exceeded!\n");
+ DEBUGOUT("Flow Director poll time exceeded!\n");
+}
+
+/**
+ * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
+ * @hw: pointer to hardware structure
+ * @fdirctrl: value to write to flow director control register, initially
+ * contains just the value of the Rx packet buffer allocation
+ **/
+s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
+{
+ DEBUGFUNC("ixgbe_init_fdir_signature_82599");
+
+ /*
+ * Continue setup of fdirctrl register bits:
+ * Move the flexible bytes to use the ethertype - shift 6 words
+ * Set the maximum length per hash bucket to 0xA filters
+ * Send interrupt when 64 filters are left
+ */
+ fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
+ (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
+ (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
+
+ /* write hashes and fdirctrl register, poll for completion */
+ ixgbe_fdir_enable_82599(hw, fdirctrl);
return IXGBE_SUCCESS;
}
@@ -1278,190 +1256,35 @@
/**
* ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
* @hw: pointer to hardware structure
- * @pballoc: which mode to allocate filters with
+ * @fdirctrl: value to write to flow director control register, initially
+ * contains just the value of the Rx packet buffer allocation
**/
-s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
+s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
{
- u32 fdirctrl = 0;
- u32 pbsize;
- int i;
-
DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
/*
- * Before enabling Flow Director, the Rx Packet Buffer size
- * must be reduced. The new value is the current size minus
- * flow director memory usage size.
+ * Continue setup of fdirctrl register bits:
+ * Turn perfect match filtering on
+ * Report hash in RSS field of Rx wb descriptor
+ * Initialize the drop queue
+ * Move the flexible bytes to use the ethertype - shift 6 words
+ * Set the maximum length per hash bucket to 0xA filters
+ * Send interrupt when 64 (0x4 * 16) filters are left
*/
- pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
- (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
-
- /*
- * The defaults in the HW for RX PB 1-7 are not zero and so should be
- * intialized to zero for non DCB mode otherwise actual total RX PB
- * would be bigger than programmed and filter space would run into
- * the PB 0 region.
- */
- for (i = 1; i < 8; i++)
- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
-
- /* Send interrupt when 64 filters are left */
- fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
-
- /* Initialize the drop queue to Rx queue 127 */
- fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
+ fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
+ IXGBE_FDIRCTRL_REPORT_STATUS |
+ (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
+ (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
+ (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
+ (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
- switch (pballoc) {
- case IXGBE_FDIR_PBALLOC_64K:
- /* 2k - 1 perfect filters */
- fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
- break;
- case IXGBE_FDIR_PBALLOC_128K:
- /* 4k - 1 perfect filters */
- fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
- break;
- case IXGBE_FDIR_PBALLOC_256K:
- /* 8k - 1 perfect filters */
- fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
- break;
- default:
- /* bad value */
- return IXGBE_ERR_CONFIG;
- };
-
- /* Turn perfect match filtering on */
- fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
- fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
-
- /* Move the flexible bytes to use the ethertype - shift 6 words */
- fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
-
- /* Prime the keys for hashing */
- IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
- IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,IXGBE_ATR_SIGNATURE_HASH_KEY);
-
- /*
- * Poll init-done after we write the register. Estimated times:
- * 10G: PBALLOC = 11b, timing is 60us
- * 1G: PBALLOC = 11b, timing is 600us
- * 100M: PBALLOC = 11b, timing is 6ms
- *
- * Multiple these timings by 4 if under full Rx load
- *
- * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
- * 1 msec per poll time. If we're at line rate and drop to 100M, then
- * this might not finish in our poll time, but we can live with that
- * for now.
- */
-
- /* Set the maximum length per hash bucket to 0xA filters */
- fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
-
- IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
- IXGBE_WRITE_FLUSH(hw);
- for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
- if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
- IXGBE_FDIRCTRL_INIT_DONE)
- break;
- msec_delay(1);
- }
- if (i >= IXGBE_FDIR_INIT_DONE_POLL)
- DEBUGOUT("Flow Director Perfect poll time exceeded!\n");
+ /* write hashes and fdirctrl register, poll for completion */
+ ixgbe_fdir_enable_82599(hw, fdirctrl);
return IXGBE_SUCCESS;
}
-/**
- * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
- * @stream: input bitstream to compute the hash on
- * @key: 32-bit hash key
- **/
-u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
- u32 key)
-{
- /*
- * The algorithm is as follows:
- * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
- * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
- * and A[n] x B[n] is bitwise AND between same length strings
- *
- * K[n] is 16 bits, defined as:
- * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
- * for n modulo 32 < 15, K[n] =
- * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
- *
- * S[n] is 16 bits, defined as:
- * for n >= 15, S[n] = S[n:n - 15]
- * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
- *
- * To simplify for programming, the algorithm is implemented
- * in software this way:
- *
- * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
- *
- * for (i = 0; i < 352; i+=32)
- * hi_hash_dword[31:0] ^= Stream[(i+31):i];
- *
- * lo_hash_dword[15:0] ^= Stream[15:0];
- * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
- * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
- *
- * hi_hash_dword[31:0] ^= Stream[351:320];
- *
- * if(key[0])
- * hash[15:0] ^= Stream[15:0];
- *
- * for (i = 0; i < 16; i++) {
- * if (key[i])
- * hash[15:0] ^= lo_hash_dword[(i+15):i];
- * if (key[i + 16])
- * hash[15:0] ^= hi_hash_dword[(i+15):i];
- * }
- *
- */
- __be32 common_hash_dword = 0;
- u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
- u32 hash_result = 0;
- u8 i;
-
- /* record the flow_vm_vlan bits as they are a key part to the hash */
- flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
-
- /* generate common hash dword */
- for (i = 10; i; i -= 2)
- common_hash_dword ^= atr_input->dword_stream[i] ^
- atr_input->dword_stream[i - 1];
-
- hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
-
- /* low dword is word swapped version of common */
- lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
-
- /* apply flow ID/VM pool/VLAN ID bits to hash words */
- hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
-
- /* Process bits 0 and 16 */
- if (key & 0x0001) hash_result ^= lo_hash_dword;
- if (key & 0x00010000) hash_result ^= hi_hash_dword;
-
- /*
- * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
- * delay this because bit 0 of the stream should not be processed
- * so we do not add the vlan until after bit 0 was processed
- */
- lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
-
-
- /* process the remaining 30 bits in the key 2 bits at a time */
- for (i = 15; i; i-- ) {
- if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
- if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
- }
-
- return hash_result & IXGBE_ATR_HASH_MASK;
-}
-
/*
* These defines allow us to quickly generate all of the necessary instructions
* in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
@@ -1469,8 +1292,11 @@
*/
#define IXGBE_ATR_COMMON_HASH_KEY \
(IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
+#ifdef lint
+#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n)
+#else
#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
-{ \
+do { \
u32 n = (_n); \
if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
common_hash ^= lo_hash_dword >> n; \
@@ -1484,7 +1310,8 @@
bucket_hash ^= hi_hash_dword >> n; \
else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
sig_hash ^= hi_hash_dword << (16 - n); \
-}
+} while (0);
+#endif
/**
* ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
@@ -1496,8 +1323,8 @@
* defines, and computing two keys at once since the hashed dword stream
* will be the same for both keys.
**/
-static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
- union ixgbe_atr_hash_dword common)
+u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
+ union ixgbe_atr_hash_dword common)
{
u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
@@ -1555,13 +1382,14 @@
/**
* ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
* @hw: pointer to hardware structure
- * @stream: input bitstream
+ * @input: unique input dword
+ * @common: compressed common input dword
* @queue: queue index to direct traffic to
**/
s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_hash_dword input,
- union ixgbe_atr_hash_dword common,
- u8 queue)
+ union ixgbe_atr_hash_dword input,
+ union ixgbe_atr_hash_dword common,
+ u8 queue)
{
u64 fdirhashcmd;
u32 fdircmd;
@@ -1587,7 +1415,7 @@
/* configure FDIRCMD register */
fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
- IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
+ IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
@@ -1604,6 +1432,104 @@
return IXGBE_SUCCESS;
}
+#ifdef lint
+#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n)
+#else
+#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
+do { \
+ u32 n = (_n); \
+ if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
+ bucket_hash ^= lo_hash_dword >> n; \
+ if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
+ bucket_hash ^= hi_hash_dword >> n; \
+} while (0);
+#endif
+/**
+ * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
+ * @atr_input: input bitstream to compute the hash on
+ * @input_mask: mask for the input bitstream
+ *
+ * This function serves two main purposes. First it applys the input_mask
+ * to the atr_input resulting in a cleaned up atr_input data stream.
+ * Secondly it computes the hash and stores it in the bkt_hash field at
+ * the end of the input byte stream. This way it will be available for
+ * future use without needing to recompute the hash.
+ **/
+void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
+ union ixgbe_atr_input *input_mask)
+{
+
+ u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
+ u32 bucket_hash = 0;
+
+ /* Apply masks to input data */
+ input->dword_stream[0] &= input_mask->dword_stream[0];
+ input->dword_stream[1] &= input_mask->dword_stream[1];
+ input->dword_stream[2] &= input_mask->dword_stream[2];
+ input->dword_stream[3] &= input_mask->dword_stream[3];
+ input->dword_stream[4] &= input_mask->dword_stream[4];
+ input->dword_stream[5] &= input_mask->dword_stream[5];
+ input->dword_stream[6] &= input_mask->dword_stream[6];
+ input->dword_stream[7] &= input_mask->dword_stream[7];
+ input->dword_stream[8] &= input_mask->dword_stream[8];
+ input->dword_stream[9] &= input_mask->dword_stream[9];
+ input->dword_stream[10] &= input_mask->dword_stream[10];
+
+ /* record the flow_vm_vlan bits as they are a key part to the hash */
+ flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
+
+ /* generate common hash dword */
+ hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
+ input->dword_stream[2] ^
+ input->dword_stream[3] ^
+ input->dword_stream[4] ^
+ input->dword_stream[5] ^
+ input->dword_stream[6] ^
+ input->dword_stream[7] ^
+ input->dword_stream[8] ^
+ input->dword_stream[9] ^
+ input->dword_stream[10]);
+
+ /* low dword is word swapped version of common */
+ lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
+
+ /* apply flow ID/VM pool/VLAN ID bits to hash words */
+ hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
+
+ /* Process bits 0 and 16 */
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
+
+ /*
+ * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
+ * delay this because bit 0 of the stream should not be processed
+ * so we do not add the vlan until after bit 0 was processed
+ */
+ lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
+
+ /* Process remaining 30 bit of the key */
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
+ IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
+
+ /*
+ * Limit hash to 13 bits since max bucket count is 8K.
+ * Store result at the end of the input stream.
+ */
+ input->formatted.bkt_hash = bucket_hash & 0x1FFF;
+}
+
/**
* ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
* @input_mask: mask to be bit swapped
@@ -1613,11 +1539,11 @@
* generate a correctly swapped value we need to bit swap the mask and that
* is what is accomplished by this function.
**/
-static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
+static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
{
- u32 mask = IXGBE_NTOHS(input_masks->dst_port_mask);
+ u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
- mask |= IXGBE_NTOHS(input_masks->src_port_mask);
+ mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
@@ -1639,58 +1565,16 @@
IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
#define IXGBE_STORE_AS_BE16(_value) \
- (((u16)(_value) >> 8) | ((u16)(_value) << 8))
-
+ IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
-/**
- * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
- * @hw: pointer to hardware structure
- * @input: input bitstream
- * @input_masks: masks for the input bitstream
- * @soft_id: software index for the filters
- * @queue: queue index to direct traffic to
- *
- * Note that the caller to this function must lock before calling, since the
- * hardware writes must be protected from one another.
- **/
-s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_input *input,
- struct ixgbe_atr_input_masks *input_masks,
- u16 soft_id, u8 queue)
+s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
+ union ixgbe_atr_input *input_mask)
{
- u32 fdirhash;
- u32 fdircmd;
- u32 fdirport, fdirtcpm;
- u32 fdirvlan;
- /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
- u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
- IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
-
- DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
+ /* mask IPv6 since it is currently not supported */
+ u32 fdirm = IXGBE_FDIRM_DIPv6;
+ u32 fdirtcpm;
- /*
- * Check flow_type formatting, and bail out before we touch the hardware
- * if there's a configuration issue
- */
- switch (input->formatted.flow_type) {
- case IXGBE_ATR_FLOW_TYPE_IPV4:
- /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
- fdirm |= IXGBE_FDIRM_L4P;
- /* FALLTHRU */
- case IXGBE_ATR_FLOW_TYPE_SCTPV4:
- if (input_masks->dst_port_mask || input_masks->src_port_mask) {
- DEBUGOUT(" Error on src/dst port mask\n");
- return IXGBE_ERR_CONFIG;
- }
- break;
- case IXGBE_ATR_FLOW_TYPE_TCPV4:
- break;
- case IXGBE_ATR_FLOW_TYPE_UDPV4:
- break;
- default:
- DEBUGOUT(" Error on flow type input\n");
- return IXGBE_ERR_CONFIG;
- }
+ DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
/*
* Program the relevant mask registers. If src/dst_port or src/dst_addr
@@ -1702,42 +1586,76 @@
* point in time.
*/
- /* Program FDIRM */
- switch (IXGBE_NTOHS(input_masks->vlan_id_mask) & 0xEFFF) {
- case 0xEFFF:
- /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
- fdirm &= ~IXGBE_FDIRM_VLANID;
+ /* verify bucket hash is cleared on hash generation */
+ if (input_mask->formatted.bkt_hash)
+ DEBUGOUT(" bucket hash should always be 0 in mask\n");
+
+ /* Program FDIRM and verify partial masks */
+ switch (input_mask->formatted.vm_pool & 0x7F) {
+ case 0x0:
+ fdirm |= IXGBE_FDIRM_POOL;
/* FALLTHRU */
+ case 0x7F:
+ break;
+ default:
+ DEBUGOUT(" Error on vm pool mask\n");
+ return IXGBE_ERR_CONFIG;
+ }
+
+ switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
+ case 0x0:
+ fdirm |= IXGBE_FDIRM_L4P;
+ if (input_mask->formatted.dst_port ||
+ input_mask->formatted.src_port) {
+ DEBUGOUT(" Error on src/dst port mask\n");
+ return IXGBE_ERR_CONFIG;
+ }
+ /* FALLTHRU */
+ case IXGBE_ATR_L4TYPE_MASK:
+ break;
+ default:
+ DEBUGOUT(" Error on flow type mask\n");
+ return IXGBE_ERR_CONFIG;
+ }
+
+ switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
+ case 0x0000:
+ /* mask VLAN ID, fall through to mask VLAN priority */
+ fdirm |= IXGBE_FDIRM_VLANID;
+ /* FALLTHRU */
+ case 0x0FFF:
+ /* mask VLAN priority */
+ fdirm |= IXGBE_FDIRM_VLANP;
+ break;
case 0xE000:
- /* Unmask VLAN prio - bit 1 */
- fdirm &= ~IXGBE_FDIRM_VLANP;
- break;
- case 0x0FFF:
- /* Unmask VLAN ID - bit 0 */
- fdirm &= ~IXGBE_FDIRM_VLANID;
- break;
- case 0x0000:
- /* do nothing, vlans already masked */
+ /* mask VLAN ID only, fall through */
+ fdirm |= IXGBE_FDIRM_VLANID;
+ /* FALLTHRU */
+ case 0xEFFF:
+ /* no VLAN fields masked */
break;
default:
DEBUGOUT(" Error on VLAN mask\n");
return IXGBE_ERR_CONFIG;
}
- if (input_masks->flex_mask & 0xFFFF) {
- if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
- DEBUGOUT(" Error on flexible byte mask\n");
- return IXGBE_ERR_CONFIG;
- }
- /* Unmask Flex Bytes - bit 4 */
- fdirm &= ~IXGBE_FDIRM_FLEX;
+ switch (input_mask->formatted.flex_bytes & 0xFFFF) {
+ case 0x0000:
+ /* Mask Flex Bytes, fall through */
+ fdirm |= IXGBE_FDIRM_FLEX;
+ /* FALLTHRU */
+ case 0xFFFF:
+ break;
+ default:
+ DEBUGOUT(" Error on flexible byte mask\n");
+ return IXGBE_ERR_CONFIG;
}
/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
/* store the TCP/UDP port masks, bit reversed from port layout */
- fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
+ fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
/* write both the same so that UDP and TCP use the same mask */
IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
@@ -1745,24 +1663,34 @@
/* store source and destination IP masks (big-enian) */
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
- ~input_masks->src_ip_mask[0]);
+ ~input_mask->formatted.src_ip[0]);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
- ~input_masks->dst_ip_mask[0]);
+ ~input_mask->formatted.dst_ip[0]);
+
+ return IXGBE_SUCCESS;
+}
+
+s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
+ union ixgbe_atr_input *input,
+ u16 soft_id, u8 queue)
+{
+ u32 fdirport, fdirvlan, fdirhash, fdircmd;
- /* Apply masks to input data */
- input->formatted.vlan_id &= input_masks->vlan_id_mask;
- input->formatted.flex_bytes &= input_masks->flex_mask;
- input->formatted.src_port &= input_masks->src_port_mask;
- input->formatted.dst_port &= input_masks->dst_port_mask;
- input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
- input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
+ DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
- /* record vlan (little-endian) and flex_bytes(big-endian) */
- fdirvlan =
- IXGBE_STORE_AS_BE16(IXGBE_NTOHS(input->formatted.flex_bytes));
- fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
- fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
- IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
+ /* currently IPv6 is not supported, must be programmed with 0 */
+ IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
+ input->formatted.src_ip[0]);
+ IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
+ input->formatted.src_ip[1]);
+ IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
+ input->formatted.src_ip[2]);
+
+ /* record the source address (big-endian) */
+ IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
+
+ /* record the first 32 bits of the destination address (big-endian) */
+ IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
/* record source and destination port (little-endian)*/
fdirport = IXGBE_NTOHS(input->formatted.dst_port);
@@ -1770,29 +1698,141 @@
fdirport |= IXGBE_NTOHS(input->formatted.src_port);
IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
- /* record the first 32 bits of the destination address (big-endian) */
- IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
+ /* record vlan (little-endian) and flex_bytes(big-endian) */
+ fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
+ fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
+ fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
+ IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
- /* record the source address (big-endian) */
- IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
+ /* configure FDIRHASH register */
+ fdirhash = input->formatted.bkt_hash;
+ fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
+ IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
+
+ /*
+ * flush all previous writes to make certain registers are
+ * programmed prior to issuing the command
+ */
+ IXGBE_WRITE_FLUSH(hw);
/* configure FDIRCMD register */
fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
+ if (queue == IXGBE_FDIR_DROP_QUEUE)
+ fdircmd |= IXGBE_FDIRCMD_DROP;
fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
+ fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
- /* we only want the bucket hash so drop the upper 16 bits */
- fdirhash = ixgbe_atr_compute_hash_82599(input,
- IXGBE_ATR_BUCKET_HASH_KEY);
- fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
-
- IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
return IXGBE_SUCCESS;
}
+s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
+ union ixgbe_atr_input *input,
+ u16 soft_id)
+{
+ u32 fdirhash;
+ u32 fdircmd = 0;
+ u32 retry_count;
+ s32 err = IXGBE_SUCCESS;
+
+ /* configure FDIRHASH register */
+ fdirhash = input->formatted.bkt_hash;
+ fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
+ IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
+
+ /* flush hash to HW */
+ IXGBE_WRITE_FLUSH(hw);
+
+ /* Query if filter is present */
+ IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
+
+ for (retry_count = 10; retry_count; retry_count--) {
+ /* allow 10us for query to process */
+ usec_delay(10);
+ /* verify query completed successfully */
+ fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
+ if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
+ break;
+ }
+
+ if (!retry_count)
+ err = IXGBE_ERR_FDIR_REINIT_FAILED;
+
+ /* if filter exists in hardware then remove it */
+ if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
+ IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
+ IXGBE_WRITE_FLUSH(hw);
+ IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
+ IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
+ }
+
+ return err;
+}
+
+/**
+ * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
+ * @hw: pointer to hardware structure
+ * @input: input bitstream
+ * @input_mask: mask for the input bitstream
+ * @soft_id: software index for the filters
+ * @queue: queue index to direct traffic to
+ *
+ * Note that the caller to this function must lock before calling, since the
+ * hardware writes must be protected from one another.
+ **/
+s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
+ union ixgbe_atr_input *input,
+ union ixgbe_atr_input *input_mask,
+ u16 soft_id, u8 queue)
+{
+ s32 err = IXGBE_ERR_CONFIG;
+
+ DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
+
+ /*
+ * Check flow_type formatting, and bail out before we touch the hardware
+ * if there's a configuration issue
+ */
+ switch (input->formatted.flow_type) {
+ case IXGBE_ATR_FLOW_TYPE_IPV4:
+ input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
+ if (input->formatted.dst_port || input->formatted.src_port) {
+ DEBUGOUT(" Error on src/dst port\n");
+ return IXGBE_ERR_CONFIG;
+ }
+ break;
+ case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+ if (input->formatted.dst_port || input->formatted.src_port) {
+ DEBUGOUT(" Error on src/dst port\n");
+ return IXGBE_ERR_CONFIG;
+ }
+ /* FALLTHRU */
+ case IXGBE_ATR_FLOW_TYPE_TCPV4:
+ case IXGBE_ATR_FLOW_TYPE_UDPV4:
+ input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
+ IXGBE_ATR_L4TYPE_MASK;
+ break;
+ default:
+ DEBUGOUT(" Error on flow type input\n");
+ return err;
+ }
+
+ /* program input mask into the HW */
+ err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
+ if (err)
+ return err;
+
+ /* apply mask and compute/store hash */
+ ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
+
+ /* program filters to filter memory */
+ return ixgbe_fdir_write_perfect_filter_82599(hw, input,
+ soft_id, queue);
+}
+
/**
* ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
* @hw: pointer to hardware structure
@@ -1808,7 +1848,7 @@
DEBUGFUNC("ixgbe_read_analog_reg8_82599");
IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
- (reg << 8));
+ (reg << 8));
IXGBE_WRITE_FLUSH(hw);
usec_delay(10);
core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
@@ -1840,18 +1880,18 @@
}
/**
- * ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx
+ * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
* @hw: pointer to hardware structure
*
* Starts the hardware using the generic start_hw function
* and the generation start_hw function.
* Then performs revision-specific operations, if any.
**/
-s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw)
+s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
{
s32 ret_val = IXGBE_SUCCESS;
- DEBUGFUNC("ixgbe_start_hw_rev_1__82599");
+ DEBUGFUNC("ixgbe_start_hw_82599");
ret_val = ixgbe_start_hw_generic(hw);
if (ret_val != IXGBE_SUCCESS)
@@ -1891,7 +1931,7 @@
if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
goto out;
else
- status = ixgbe_identify_sfp_module_generic(hw);
+ status = ixgbe_identify_module_generic(hw);
}
/* Set PHY type none if no PHY detected */
@@ -1932,7 +1972,6 @@
switch (hw->phy.type) {
case ixgbe_phy_tn:
- case ixgbe_phy_aq:
case ixgbe_phy_cu_unknown:
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
@@ -2016,6 +2055,8 @@
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
+ else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
+ physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
break;
default:
break;
@@ -2034,9 +2075,6 @@
**/
s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
{
-#define IXGBE_MAX_SECRX_POLL 30
- int i;
- int secrxreg;
DEBUGFUNC("ixgbe_enable_rx_dma_82599");
@@ -2046,28 +2084,12 @@
* the Rx DMA unit. Therefore, make sure the security engine is
* completely disabled prior to enabling the Rx unit.
*/
- secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
- secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
- for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
- secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
- if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
- break;
- else
- /* Use interrupt-safe sleep just in case */
- usec_delay(10);
- }
- /* For informational purposes only */
- if (i >= IXGBE_MAX_SECRX_POLL)
- DEBUGOUT("Rx unit being enabled before security "
- "path fully disabled. Continuing with init.\n");
+ hw->mac.ops.disable_sec_rx_path(hw);
IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
- secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
- secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
- IXGBE_WRITE_FLUSH(hw);
+
+ hw->mac.ops.enable_sec_rx_path(hw);
return IXGBE_SUCCESS;
}
@@ -2104,16 +2126,15 @@
/* get the offset to the Pass Through Patch Configuration block */
hw->eeprom.ops.read(hw, (fw_offset +
- IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
- &fw_ptp_cfg_offset);
+ IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
+ &fw_ptp_cfg_offset);
if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
goto fw_version_out;
/* get the firmware version */
hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
- IXGBE_FW_PATCH_VERSION_4),
- &fw_version);
+ IXGBE_FW_PATCH_VERSION_4), &fw_version);
if (fw_version > 0x5)
status = IXGBE_SUCCESS;
@@ -2146,8 +2167,8 @@
/* get the offset to the LESM Parameters block */
status = hw->eeprom.ops.read(hw, (fw_offset +
- IXGBE_FW_LESM_PARAMETERS_PTR),
- &fw_lesm_param_offset);
+ IXGBE_FW_LESM_PARAMETERS_PTR),
+ &fw_lesm_param_offset);
if ((status != IXGBE_SUCCESS) ||
(fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
@@ -2155,8 +2176,8 @@
/* get the lesm state word */
status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
- IXGBE_FW_LESM_STATE_1),
- &fw_lesm_state);
+ IXGBE_FW_LESM_STATE_1),
+ &fw_lesm_state);
if ((status == IXGBE_SUCCESS) &&
(fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
@@ -2166,4 +2187,70 @@
return lesm_enabled;
}
+/**
+ * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
+ * fastest available method
+ *
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in EEPROM to read
+ * @words: number of words
+ * @data: word(s) read from the EEPROM
+ *
+ * Retrieves 16 bit word(s) read from EEPROM
+ **/
+static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data)
+{
+ struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
+ s32 ret_val = IXGBE_ERR_CONFIG;
+ DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
+
+ /*
+ * If EEPROM is detected and can be addressed using 14 bits,
+ * use EERD otherwise use bit bang
+ */
+ if ((eeprom->type == ixgbe_eeprom_spi) &&
+ (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
+ ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
+ data);
+ else
+ ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
+ words,
+ data);
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_read_eeprom_82599 - Read EEPROM word using
+ * fastest available method
+ *
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in the EEPROM to read
+ * @data: word read from the EEPROM
+ *
+ * Reads a 16 bit word from the EEPROM
+ **/
+static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
+ u16 offset, u16 *data)
+{
+ struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
+ s32 ret_val = IXGBE_ERR_CONFIG;
+
+ DEBUGFUNC("ixgbe_read_eeprom_82599");
+
+ /*
+ * If EEPROM is detected and can be addressed using 14 bits,
+ * use EERD otherwise use bit bang
+ */
+ if ((eeprom->type == ixgbe_eeprom_spi) &&
+ (offset <= IXGBE_EERD_MAX_ADDR))
+ ret_val = ixgbe_read_eerd_generic(hw, offset, data);
+ else
+ ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
+
+ return ret_val;
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_82599.h Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,65 @@
+/******************************************************************************
+
+ Copyright (c) 2001-2012, Intel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+******************************************************************************/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.h,v 1.1 2012/01/30 16:42:02 jfv Exp $*/
+
+#ifndef _IXGBE_82599_H_
+#define _IXGBE_82599_H_
+
+s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
+ ixgbe_link_speed *speed, bool *autoneg);
+enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
+void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
+void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
+void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
+s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
+ ixgbe_link_speed speed, bool autoneg,
+ bool autoneg_wait_to_complete);
+s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
+ ixgbe_link_speed speed, bool autoneg,
+ bool autoneg_wait_to_complete);
+s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
+ bool autoneg_wait_to_complete);
+s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed,
+ bool autoneg, bool autoneg_wait_to_complete);
+s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);
+void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);
+s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
+s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
+s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
+s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
+s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
+s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
+u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
+s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
+bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
+#endif /* _IXGBE_82599_H_ */
--- a/usr/src/uts/common/io/ixgbe/ixgbe_api.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_api.c Sun Aug 12 11:56:48 2012 +0100
@@ -30,14 +30,11 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
#include "ixgbe_api.h"
#include "ixgbe_common.h"
-extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
-extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
-
/**
* ixgbe_init_shared_code - Initialize the shared code
* @hw: pointer to hardware structure
@@ -59,7 +56,9 @@
/*
* Set the mac type
*/
- (void) ixgbe_set_mac_type(hw);
+ status = ixgbe_set_mac_type(hw);
+ if (status != IXGBE_SUCCESS)
+ return (status);
switch (hw->mac.type) {
case ixgbe_mac_82598EB:
@@ -68,6 +67,9 @@
case ixgbe_mac_82599EB:
status = ixgbe_init_ops_82599(hw);
break;
+ case ixgbe_mac_X540:
+ status = ixgbe_init_ops_X540(hw);
+ break;
default:
status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
break;
@@ -120,6 +122,16 @@
case IXGBE_DEV_ID_82599_T3_LOM:
hw->mac.type = ixgbe_mac_82599EB;
break;
+ case IXGBE_DEV_ID_82599_VF:
+ hw->mac.type = ixgbe_mac_82599_vf;
+ break;
+ case IXGBE_DEV_ID_X540_VF:
+ hw->mac.type = ixgbe_mac_X540_vf;
+ break;
+ case IXGBE_DEV_ID_X540T:
+ case IXGBE_DEV_ID_X540T1:
+ hw->mac.type = ixgbe_mac_X540;
+ break;
default:
ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
break;
@@ -129,7 +141,7 @@
}
DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
- hw->mac.type, ret_val);
+ hw->mac.type, ret_val);
return ret_val;
}
@@ -142,7 +154,7 @@
s32 ixgbe_init_hw(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -155,7 +167,7 @@
s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -171,7 +183,7 @@
s32 ixgbe_start_hw(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -198,7 +210,7 @@
s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -210,7 +222,7 @@
enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
- ixgbe_media_type_unknown);
+ ixgbe_media_type_unknown);
}
/**
@@ -226,7 +238,7 @@
s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
{
return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
- (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
+ (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -240,7 +252,7 @@
s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
{
return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,
- (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
+ (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -253,7 +265,7 @@
s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
{
return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,
- (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
+ (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -266,7 +278,7 @@
s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
{
return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
- (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
+ (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -279,11 +291,11 @@
* block to check the support for the alternative WWNN/WWPN prefix support.
**/
s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
- u16 *wwpn_prefix)
+ u16 *wwpn_prefix)
{
return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
- (hw, wwnn_prefix, wwpn_prefix),
- IXGBE_NOT_IMPLEMENTED);
+ (hw, wwnn_prefix, wwpn_prefix),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -296,8 +308,8 @@
s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
{
return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,
- (hw, bs),
- IXGBE_NOT_IMPLEMENTED);
+ (hw, bs),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -309,7 +321,7 @@
s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -346,7 +358,7 @@
s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -363,19 +375,6 @@
}
/**
- * ixgbe_read_pba_length - Reads part number string length from EEPROM
- * @hw: pointer to hardware structure
- * @pba_num_size: part number string buffer length
- *
- * Reads the part number length from the EEPROM.
- * Returns expected buffer size in pba_num_size.
- **/
-s32 ixgbe_read_pba_length(struct ixgbe_hw *hw, u32 *pba_num_size)
-{
- return ixgbe_read_pba_length_generic(hw, pba_num_size);
-}
-
-/**
* ixgbe_read_pba_num - Reads part number from EEPROM
* @hw: pointer to hardware structure
* @pba_num: stores the part number from the EEPROM
@@ -399,7 +398,7 @@
if (hw->phy.type == ixgbe_phy_unknown) {
status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
return status;
@@ -420,7 +419,7 @@
if (status == IXGBE_SUCCESS) {
status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
return status;
}
@@ -435,8 +434,8 @@
s32 status = IXGBE_SUCCESS;
status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
- (hw, firmware_version),
- IXGBE_NOT_IMPLEMENTED);
+ (hw, firmware_version),
+ IXGBE_NOT_IMPLEMENTED);
return status;
}
@@ -449,13 +448,21 @@
* Reads a value from a specified PHY register
**/
s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
- u16 *phy_data)
+ u16 *phy_data)
{
+ s32 status;
+
if (hw->phy.id == 0)
- (void) ixgbe_identify_phy(hw);
+ status = ixgbe_identify_phy(hw);
+ else
+ status = IXGBE_SUCCESS;
- return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
- device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
+ if (status == IXGBE_SUCCESS) {
+ status = ixgbe_call_func(hw, hw->phy.ops.read_reg,
+ (hw, reg_addr, device_type, phy_data),
+ IXGBE_NOT_IMPLEMENTED);
+ }
+ return (status);
}
/**
@@ -467,13 +474,22 @@
* Writes a value to specified PHY register
**/
s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
- u16 phy_data)
+ u16 phy_data)
{
+ s32 status;
+
if (hw->phy.id == 0)
- (void) ixgbe_identify_phy(hw);
+ status = ixgbe_identify_phy(hw);
+ else
+ status = IXGBE_SUCCESS;
- return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
- device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
+ if (status == IXGBE_SUCCESS) {
+ status = ixgbe_call_func(hw, hw->phy.ops.write_reg,
+ (hw, reg_addr, device_type, phy_data),
+ IXGBE_NOT_IMPLEMENTED);
+ }
+
+ return status;
}
/**
@@ -485,7 +501,7 @@
s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -496,10 +512,10 @@
* the PHY.
**/
s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *link_up)
+ bool *link_up)
{
return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
- link_up), IXGBE_NOT_IMPLEMENTED);
+ link_up), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -511,12 +527,12 @@
* Sets the auto advertised capabilities
**/
s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete)
+ bool autoneg,
+ bool autoneg_wait_to_complete)
{
return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
- autoneg, autoneg_wait_to_complete),
- IXGBE_NOT_IMPLEMENTED);
+ autoneg, autoneg_wait_to_complete),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -526,11 +542,11 @@
* Reads the links register to determine if link is up and the current speed
**/
s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *link_up, bool link_up_wait_to_complete)
+ bool *link_up, bool link_up_wait_to_complete)
{
return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
- link_up, link_up_wait_to_complete),
- IXGBE_NOT_IMPLEMENTED);
+ link_up, link_up_wait_to_complete),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -581,12 +597,12 @@
* Performs autonegotiation if needed.
**/
s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete)
+ bool autoneg,
+ bool autoneg_wait_to_complete)
{
return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
- autoneg, autoneg_wait_to_complete),
- IXGBE_NOT_IMPLEMENTED);
+ autoneg, autoneg_wait_to_complete),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -596,10 +612,10 @@
* Determines the link capabilities of the current configuration.
**/
s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *autoneg)
+ bool *autoneg)
{
return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
- speed, autoneg), IXGBE_NOT_IMPLEMENTED);
+ speed, autoneg), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -612,7 +628,7 @@
s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
{
return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -625,7 +641,7 @@
s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
{
return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -638,7 +654,7 @@
s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
{
return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -650,7 +666,7 @@
s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
{
return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -663,7 +679,7 @@
s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
@@ -680,7 +696,26 @@
s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
{
return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
+ * @hw: pointer to hardware structure
+ * @offset: offset within the EEPROM to be written to
+ * @data: 16 bit word(s) to be written to the EEPROM
+ * @words: number of words
+ *
+ * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
+ * called after this function, the EEPROM will most likely contain an
+ * invalid checksum.
+ **/
+s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,
+ u16 *data)
+{
+ return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,
+ (hw, offset, words, data),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -694,7 +729,24 @@
s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
{
return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
+ * @hw: pointer to hardware structure
+ * @offset: offset within the EEPROM to be read
+ * @data: read 16 bit word(s) from EEPROM
+ * @words: number of words
+ *
+ * Reads 16 bit word(s) from EEPROM
+ **/
+s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data)
+{
+ return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,
+ (hw, offset, words, data),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -707,7 +759,7 @@
s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
{
return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
- (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
+ (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -717,7 +769,7 @@
s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -732,7 +784,7 @@
s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
{
return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,
- (hw, addr, vmdq),
+ (hw, addr, vmdq),
IXGBE_NOT_IMPLEMENTED);
}
@@ -747,10 +799,10 @@
* Puts an ethernet address into a receive address register.
**/
s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
- u32 enable_addr)
+ u32 enable_addr)
{
return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
- enable_addr), IXGBE_NOT_IMPLEMENTED);
+ enable_addr), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -763,7 +815,7 @@
s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
{
return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -775,7 +827,19 @@
s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
{
return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
+
+}
+
+/**
+ * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
+ * @hw: pointer to hardware structure
+ * @vmdq: VMDq default pool index
+ **/
+s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
+{
+ return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
+ (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -787,7 +851,7 @@
s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
{
return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -801,7 +865,7 @@
s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -825,11 +889,11 @@
* first secondary addresses, and falls back to promiscuous mode as needed.
**/
s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
- u32 addr_count, ixgbe_mc_addr_itr func)
+ u32 addr_count, ixgbe_mc_addr_itr func)
{
return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
- addr_list, addr_count, func),
- IXGBE_NOT_IMPLEMENTED);
+ addr_list, addr_count, func),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -845,11 +909,12 @@
* multicast table.
**/
s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
- u32 mc_addr_count, ixgbe_mc_addr_itr func)
+ u32 mc_addr_count, ixgbe_mc_addr_itr func,
+ bool clear)
{
return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
- mc_addr_list, mc_addr_count, func),
- IXGBE_NOT_IMPLEMENTED);
+ mc_addr_list, mc_addr_count, func, clear),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -861,7 +926,7 @@
s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -873,7 +938,7 @@
s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -885,7 +950,7 @@
s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -900,23 +965,56 @@
s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
{
return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
- vlan_on), IXGBE_NOT_IMPLEMENTED);
+ vlan_on), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ * ixgbe_set_vlvf - Set VLAN Pool Filter
+ * @hw: pointer to hardware structure
+ * @vlan: VLAN id to write to VLAN filter
+ * @vind: VMDq output index that maps queue to VLAN id in VFVFB
+ * @vlan_on: boolean flag to turn on/off VLAN in VFVF
+ * @vfta_changed: pointer to boolean flag which indicates whether VFTA
+ * should be changed
+ *
+ * Turn on/off specified bit in VLVF table.
+ **/
+s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
+ bool *vfta_changed)
+{
+ return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
+ vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_fc_enable - Enable flow control
* @hw: pointer to hardware structure
- * @packetbuf_num: packet buffer number (0-7)
*
* Configures the flow control settings based on SW configuration.
**/
-s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
+s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
{
- return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num),
- IXGBE_NOT_IMPLEMENTED);
+ return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
+ * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
+ * @hw: pointer to hardware structure
+ * @maj: driver major number to be sent to firmware
+ * @min: driver minor number to be sent to firmware
+ * @build: driver build number to be sent to firmware
+ * @ver: driver version number to be sent to firmware
+ **/
+s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
+ u8 ver)
+{
+ return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
+ build, ver), IXGBE_NOT_IMPLEMENTED);
+}
+
+
+/**
* ixgbe_read_analog_reg8 - Reads 8 bit analog register
* @hw: pointer to hardware structure
* @reg: analog register to read
@@ -927,7 +1025,7 @@
s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
{
return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
- val), IXGBE_NOT_IMPLEMENTED);
+ val), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -941,7 +1039,7 @@
s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
{
return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
- val), IXGBE_NOT_IMPLEMENTED);
+ val), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -954,7 +1052,7 @@
s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
- IXGBE_NOT_IMPLEMENTED);
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -966,10 +1064,10 @@
* Performs byte read operation to SFP module's EEPROM over I2C interface.
**/
s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
- u8 *data)
+ u8 *data)
{
return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
- dev_addr, data), IXGBE_NOT_IMPLEMENTED);
+ dev_addr, data), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -982,10 +1080,10 @@
* at a specified device address.
**/
s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
- u8 data)
+ u8 data)
{
return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
- dev_addr, data), IXGBE_NOT_IMPLEMENTED);
+ dev_addr, data), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -997,11 +1095,11 @@
* Performs byte write operation to SFP module's EEPROM over I2C interface.
**/
s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
- u8 byte_offset, u8 eeprom_data)
+ u8 byte_offset, u8 eeprom_data)
{
return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
- (hw, byte_offset, eeprom_data),
- IXGBE_NOT_IMPLEMENTED);
+ (hw, byte_offset, eeprom_data),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -1015,8 +1113,8 @@
s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
{
return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
- (hw, byte_offset, eeprom_data),
- IXGBE_NOT_IMPLEMENTED);
+ (hw, byte_offset, eeprom_data),
+ IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -1028,11 +1126,11 @@
u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
- (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
+ (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
}
/**
- * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics
+ * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
* @hw: pointer to hardware structure
* @regval: bitfield to write to the Rx DMA register
*
@@ -1041,7 +1139,31 @@
s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
{
return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
- (hw, regval), IXGBE_NOT_IMPLEMENTED);
+ (hw, regval), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ * ixgbe_disable_sec_rx_path - Stops the receive data path
+ * @hw: pointer to hardware structure
+ *
+ * Stops the receive data path.
+ **/
+s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)
+{
+ return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,
+ (hw), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ * ixgbe_enable_sec_rx_path - Enables the receive data path
+ * @hw: pointer to hardware structure
+ *
+ * Enables the receive data path.
+ **/
+s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
+{
+ return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
+ (hw), IXGBE_NOT_IMPLEMENTED);
}
/**
@@ -1055,7 +1177,7 @@
s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
{
return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
- (hw, mask), IXGBE_NOT_IMPLEMENTED);
+ (hw, mask), IXGBE_NOT_IMPLEMENTED);
}
/**
--- a/usr/src/uts/common/io/ixgbe/ixgbe_api.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_api.h Sun Aug 12 11:56:48 2012 +0100
@@ -1,6 +1,6 @@
/******************************************************************************
- Copyright (c) 2001-2010, Intel Corporation
+ Copyright (c) 2001-2012, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,6 +30,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.h,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
#ifndef _IXGBE_API_H_
#define _IXGBE_API_H_
@@ -38,6 +39,11 @@
s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
+extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
+extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
+extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
+extern s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw);
+
s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
s32 ixgbe_init_hw(struct ixgbe_hw *hw);
s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
@@ -52,32 +58,31 @@
s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);
s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
-s32 ixgbe_read_pba_length(struct ixgbe_hw *hw, u32 *pba_num_size);
s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
- u16 *phy_data);
+ u16 *phy_data);
s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
- u16 phy_data);
+ u16 phy_data);
s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *link_up);
+ ixgbe_link_speed *speed,
+ bool *link_up);
s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
+ ixgbe_link_speed speed,
+ bool autoneg,
+ bool autoneg_wait_to_complete);
void ixgbe_disable_tx_laser(struct ixgbe_hw *hw);
void ixgbe_enable_tx_laser(struct ixgbe_hw *hw);
void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
- bool autoneg, bool autoneg_wait_to_complete);
+ bool autoneg, bool autoneg_wait_to_complete);
s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *link_up, bool link_up_wait_to_complete);
+ bool *link_up, bool link_up_wait_to_complete);
s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *autoneg);
+ bool *autoneg);
s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
@@ -85,57 +90,79 @@
s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
+s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data);
s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
+s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data);
+
s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
- u32 enable_addr);
+ u32 enable_addr);
s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
+s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);
s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
- u32 addr_count, ixgbe_mc_addr_itr func);
+ u32 addr_count, ixgbe_mc_addr_itr func);
s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
- u32 mc_addr_count, ixgbe_mc_addr_itr func);
+ u32 mc_addr_count, ixgbe_mc_addr_itr func,
+ bool clear);
void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);
s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
- u32 vind, bool vlan_on);
-
-s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num);
-
+ u32 vind, bool vlan_on);
+s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
+ bool vlan_on, bool *vfta_changed);
+s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
+s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
+ u8 ver);
void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,
- u16 *firmware_version);
+ u16 *firmware_version);
s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);
u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
+s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);
+s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
-s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
-s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
+s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
+s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_hash_dword input,
+ union ixgbe_atr_hash_dword input,
union ixgbe_atr_hash_dword common,
- u8 queue);
+ u8 queue);
+s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
+ union ixgbe_atr_input *input_mask);
+s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
+ union ixgbe_atr_input *input,
+ u16 soft_id, u8 queue);
+s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
+ union ixgbe_atr_input *input,
+ u16 soft_id);
s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_input *input,
- struct ixgbe_atr_input_masks *masks,
- u16 soft_id,
- u8 queue);
-u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *input, u32 key);
+ union ixgbe_atr_input *input,
+ union ixgbe_atr_input *mask,
+ u16 soft_id,
+ u8 queue);
+void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
+ union ixgbe_atr_input *mask);
+u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
+ union ixgbe_atr_hash_dword common);
s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
- u8 *data);
+ u8 *data);
s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
- u8 data);
+ u8 data);
s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
@@ -143,8 +170,7 @@
s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
- u16 *wwpn_prefix);
+ u16 *wwpn_prefix);
s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
-
#endif /* _IXGBE_API_H_ */
--- a/usr/src/uts/common/io/ixgbe/ixgbe_common.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_common.c Sun Aug 12 11:56:48 2012 +0100
@@ -1,6 +1,6 @@
/******************************************************************************
- Copyright (c) 2001-2010, Intel Corporation
+ Copyright (c) 2001-2012, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +30,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.c,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
@@ -42,7 +42,7 @@
static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
- u16 count);
+ u16 count);
static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
@@ -50,15 +50,13 @@
static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
- u16 *san_mac_offset);
-static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
-static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
-static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
-static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
-static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
- u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
-
-s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan);
+ u16 *san_mac_offset);
+static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data);
+static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data);
+static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
+ u16 offset);
/**
* ixgbe_init_ops_generic - Inits function ptrs
@@ -77,13 +75,18 @@
/* EEPROM */
eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
/* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
- if (eec & (1 << 8))
+ if (eec & IXGBE_EEC_PRES) {
eeprom->ops.read = &ixgbe_read_eerd_generic;
- else
+ eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
+ } else {
eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
+ eeprom->ops.read_buffer =
+ &ixgbe_read_eeprom_buffer_bit_bang_generic;
+ }
eeprom->ops.write = &ixgbe_write_eeprom_generic;
+ eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
eeprom->ops.validate_checksum =
- &ixgbe_validate_eeprom_checksum_generic;
+ &ixgbe_validate_eeprom_checksum_generic;
eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
@@ -121,6 +124,7 @@
mac->ops.disable_mc = &ixgbe_disable_mc_generic;
mac->ops.clear_vfta = NULL;
mac->ops.set_vfta = NULL;
+ mac->ops.set_vlvf = NULL;
mac->ops.init_uta_tables = NULL;
/* Flow Control */
@@ -135,6 +139,176 @@
}
/**
+ * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
+ * control
+ * @hw: pointer to hardware structure
+ *
+ * There are several phys that do not support autoneg flow control. This
+ * function check the device id to see if the associated phy supports
+ * autoneg flow control.
+ **/
+static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
+{
+
+ DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
+
+ switch (hw->device_id) {
+ case IXGBE_DEV_ID_X540T:
+ case IXGBE_DEV_ID_X540T1:
+ return IXGBE_SUCCESS;
+ case IXGBE_DEV_ID_82599_T3_LOM:
+ return IXGBE_SUCCESS;
+ default:
+ return IXGBE_ERR_FC_NOT_SUPPORTED;
+ }
+}
+
+/**
+ * ixgbe_setup_fc - Set up flow control
+ * @hw: pointer to hardware structure
+ *
+ * Called at init time to set up flow control.
+ **/
+static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
+{
+ s32 ret_val = IXGBE_SUCCESS;
+ u32 reg = 0, reg_bp = 0;
+ u16 reg_cu = 0;
+
+ DEBUGFUNC("ixgbe_setup_fc");
+
+ /*
+ * Validate the requested mode. Strict IEEE mode does not allow
+ * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
+ */
+ if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
+ DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
+ ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+ goto out;
+ }
+
+ /*
+ * 10gig parts do not have a word in the EEPROM to determine the
+ * default flow control setting, so we explicitly set it to full.
+ */
+ if (hw->fc.requested_mode == ixgbe_fc_default)
+ hw->fc.requested_mode = ixgbe_fc_full;
+
+ /*
+ * Set up the 1G and 10G flow control advertisement registers so the
+ * HW will be able to do fc autoneg once the cable is plugged in. If
+ * we link at 10G, the 1G advertisement is harmless and vice versa.
+ */
+ switch (hw->phy.media_type) {
+ case ixgbe_media_type_fiber:
+ case ixgbe_media_type_backplane:
+ reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
+ reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+ break;
+ case ixgbe_media_type_copper:
+ hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
+ break;
+ default:
+ break;
+ }
+
+ /*
+ * The possible values of fc.requested_mode are:
+ * 0: Flow control is completely disabled
+ * 1: Rx flow control is enabled (we can receive pause frames,
+ * but not send pause frames).
+ * 2: Tx flow control is enabled (we can send pause frames but
+ * we do not support receiving pause frames).
+ * 3: Both Rx and Tx flow control (symmetric) are enabled.
+ * other: Invalid.
+ */
+ switch (hw->fc.requested_mode) {
+ case ixgbe_fc_none:
+ /* Flow control completely disabled by software override. */
+ reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
+ if (hw->phy.media_type == ixgbe_media_type_backplane)
+ reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
+ IXGBE_AUTOC_ASM_PAUSE);
+ else if (hw->phy.media_type == ixgbe_media_type_copper)
+ reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
+ break;
+ case ixgbe_fc_tx_pause:
+ /*
+ * Tx Flow control is enabled, and Rx Flow control is
+ * disabled by software override.
+ */
+ reg |= IXGBE_PCS1GANA_ASM_PAUSE;
+ reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
+ if (hw->phy.media_type == ixgbe_media_type_backplane) {
+ reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
+ reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
+ } else if (hw->phy.media_type == ixgbe_media_type_copper) {
+ reg_cu |= IXGBE_TAF_ASM_PAUSE;
+ reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
+ }
+ break;
+ case ixgbe_fc_rx_pause:
+ /*
+ * Rx Flow control is enabled and Tx Flow control is
+ * disabled by software override. Since there really
+ * isn't a way to advertise that we are capable of RX
+ * Pause ONLY, we will advertise that we support both
+ * symmetric and asymmetric Rx PAUSE, as such we fall
+ * through to the fc_full statement. Later, we will
+ * disable the adapter's ability to send PAUSE frames.
+ */
+ case ixgbe_fc_full:
+ /* Flow control (both Rx and Tx) is enabled by SW override. */
+ reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
+ if (hw->phy.media_type == ixgbe_media_type_backplane)
+ reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
+ IXGBE_AUTOC_ASM_PAUSE;
+ else if (hw->phy.media_type == ixgbe_media_type_copper)
+ reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
+ break;
+ default:
+ DEBUGOUT("Flow control param set incorrectly\n");
+ ret_val = IXGBE_ERR_CONFIG;
+ goto out;
+ }
+
+ if (hw->mac.type != ixgbe_mac_X540) {
+ /*
+ * Enable auto-negotiation between the MAC & PHY;
+ * the MAC will advertise clause 37 flow control.
+ */
+ IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
+ reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
+
+ /* Disable AN timeout */
+ if (hw->fc.strict_ieee)
+ reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
+
+ IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
+ DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
+ }
+
+ /*
+ * AUTOC restart handles negotiation of 1G and 10G on backplane
+ * and copper. There is no need to set the PCS1GCTL register.
+ *
+ */
+ if (hw->phy.media_type == ixgbe_media_type_backplane) {
+ reg_bp |= IXGBE_AUTOC_AN_RESTART;
+ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
+ } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
+ (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
+ hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
+ }
+
+ DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
+out:
+ return ret_val;
+}
+
+/**
* ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
* @hw: pointer to hardware structure
*
@@ -145,6 +319,7 @@
**/
s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
{
+ s32 ret_val;
u32 ctrl_ext;
DEBUGFUNC("ixgbe_start_hw_generic");
@@ -167,12 +342,15 @@
IXGBE_WRITE_FLUSH(hw);
/* Setup flow control */
- (void) ixgbe_setup_fc(hw, 0);
+ ret_val = ixgbe_setup_fc(hw);
+ if (ret_val != IXGBE_SUCCESS)
+ goto out;
/* Clear adapter stopped flag */
hw->adapter_stopped = FALSE;
- return IXGBE_SUCCESS;
+out:
+ return ret_val;
}
/**
@@ -200,14 +378,14 @@
/* Disable relaxed ordering */
for (i = 0; i < hw->mac.max_tx_queues; i++) {
regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
- regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+ regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
}
for (i = 0; i < hw->mac.max_rx_queues; i++) {
regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
- regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
- IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+ regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
+ IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
}
@@ -302,8 +480,9 @@
(void) IXGBE_READ_REG(hw, IXGBE_GORCH);
(void) IXGBE_READ_REG(hw, IXGBE_GOTCL);
(void) IXGBE_READ_REG(hw, IXGBE_GOTCH);
- for (i = 0; i < 8; i++)
- (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i));
+ if (hw->mac.type == ixgbe_mac_82598EB)
+ for (i = 0; i < 8; i++)
+ (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i));
(void) IXGBE_READ_REG(hw, IXGBE_RUC);
(void) IXGBE_READ_REG(hw, IXGBE_RFC);
(void) IXGBE_READ_REG(hw, IXGBE_ROC);
@@ -338,6 +517,19 @@
}
}
+ if (hw->mac.type == ixgbe_mac_X540) {
+ if (hw->phy.id == 0)
+ (void) ixgbe_identify_phy(hw);
+ hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
+ IXGBE_MDIO_PCS_DEV_TYPE, &i);
+ hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
+ IXGBE_MDIO_PCS_DEV_TYPE, &i);
+ hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
+ IXGBE_MDIO_PCS_DEV_TYPE, &i);
+ hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
+ IXGBE_MDIO_PCS_DEV_TYPE, &i);
+ }
+
return IXGBE_SUCCESS;
}
@@ -350,7 +542,7 @@
* Reads the part number string from the EEPROM.
**/
s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
- u32 pba_num_size)
+ u32 pba_num_size)
{
s32 ret_val;
u16 data;
@@ -453,66 +645,6 @@
}
/**
- * ixgbe_read_pba_length_generic - Reads part number length from EEPROM
- * @hw: pointer to hardware structure
- * @pba_num_size: part number string buffer length
- *
- * Reads the part number length from the EEPROM.
- * Returns expected buffer size in pba_num_size
- **/
-s32 ixgbe_read_pba_length_generic(struct ixgbe_hw *hw, u32 *pba_num_size)
-{
- s32 ret_val;
- u16 data;
- u16 pba_ptr;
- u16 length;
-
- DEBUGFUNC("ixgbe_read_pba_length_generic");
-
- if (pba_num_size == NULL) {
- DEBUGOUT("PBA buffer size was null\n");
- return IXGBE_ERR_INVALID_ARGUMENT;
- }
-
- ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
- if (ret_val) {
- DEBUGOUT("NVM Read Error\n");
- return ret_val;
- }
-
- ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
- if (ret_val) {
- DEBUGOUT("NVM Read Error\n");
- return ret_val;
- }
-
- /* if data is not ptr guard the PBA must be in legacy format */
- if (data != IXGBE_PBANUM_PTR_GUARD) {
- *pba_num_size = 11;
- return IXGBE_SUCCESS;
- }
-
- ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
- if (ret_val) {
- DEBUGOUT("NVM Read Error\n");
- return ret_val;
- }
-
- if (length == 0xFFFF || length == 0) {
- DEBUGOUT("NVM PBA number section invalid length\n");
- return IXGBE_ERR_PBA_SECTION;
- }
-
- /*
- * Convert from length in u16 values to u8 chars, add 1 for NULL,
- * and subtract 2 because length field is included in length.
- */
- *pba_num_size = ((u32)length * 2) - 1;
-
- return IXGBE_SUCCESS;
-}
-
-/**
* ixgbe_read_pba_num_generic - Reads part number from EEPROM
* @hw: pointer to hardware structure
* @pba_num: stores the part number from the EEPROM
@@ -618,6 +750,9 @@
case IXGBE_PCI_LINK_SPEED_5000:
hw->bus.speed = ixgbe_bus_speed_5000;
break;
+ case IXGBE_PCI_LINK_SPEED_8000:
+ hw->bus.speed = ixgbe_bus_speed_8000;
+ break;
default:
hw->bus.speed = ixgbe_bus_speed_unknown;
break;
@@ -663,7 +798,6 @@
**/
s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
{
- u32 number_of_queues;
u32 reg_val;
u16 i;
@@ -676,35 +810,35 @@
hw->adapter_stopped = TRUE;
/* Disable the receive unit */
- reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
- reg_val &= ~(IXGBE_RXCTRL_RXEN);
- IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
- IXGBE_WRITE_FLUSH(hw);
- msec_delay(2);
-
- /* Clear interrupt mask to stop from interrupts being generated */
+ IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
+
+ /* Clear interrupt mask to stop interrupts from being generated */
IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
- /* Clear any pending interrupts */
+ /* Clear any pending interrupts, flush previous writes */
(void) IXGBE_READ_REG(hw, IXGBE_EICR);
/* Disable the transmit unit. Each queue must be disabled. */
- number_of_queues = hw->mac.max_tx_queues;
- for (i = 0; i < number_of_queues; i++) {
- reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
- if (reg_val & IXGBE_TXDCTL_ENABLE) {
- reg_val &= ~IXGBE_TXDCTL_ENABLE;
- IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
- }
+ for (i = 0; i < hw->mac.max_tx_queues; i++)
+ IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
+
+ /* Disable the receive unit by stopping each queue */
+ for (i = 0; i < hw->mac.max_rx_queues; i++) {
+ reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
+ reg_val &= ~IXGBE_RXDCTL_ENABLE;
+ reg_val |= IXGBE_RXDCTL_SWFLSH;
+ IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
}
+ /* flush all queues disables */
+ IXGBE_WRITE_FLUSH(hw);
+ msec_delay(2);
+
/*
* Prevent the PCI-E bus from from hanging by disabling PCI-E master
* access and verify no pending requests
*/
- (void) ixgbe_disable_pcie_master(hw);
-
- return IXGBE_SUCCESS;
+ return ixgbe_disable_pcie_master(hw);
}
/**
@@ -767,6 +901,8 @@
/* Set default semaphore delay to 10ms which is a well
* tested value */
eeprom->semaphore_delay = 10;
+ /* Clear EEPROM page size, it will be initialized as needed */
+ eeprom->word_page_size = 0;
/*
* Check for EEPROM present first.
@@ -781,9 +917,9 @@
* change if a future EEPROM is not SPI.
*/
eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
- IXGBE_EEC_SIZE_SHIFT);
+ IXGBE_EEC_SIZE_SHIFT);
eeprom->word_size = 1 << (eeprom_size +
- IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT);
+ IXGBE_EEPROM_WORD_SIZE_SHIFT);
}
if (eec & IXGBE_EEC_ADDR_SIZE)
@@ -791,14 +927,155 @@
else
eeprom->address_bits = 8;
DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
- "%d\n", eeprom->type, eeprom->word_size,
- eeprom->address_bits);
+ "%d\n", eeprom->type, eeprom->word_size,
+ eeprom->address_bits);
}
return IXGBE_SUCCESS;
}
/**
+ * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
+ * @hw: pointer to hardware structure
+ * @offset: offset within the EEPROM to write
+ * @words: number of word(s)
+ * @data: 16 bit word(s) to write to EEPROM
+ *
+ * Reads 16 bit word(s) from EEPROM through bit-bang method
+ **/
+s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data)
+{
+ s32 status = IXGBE_SUCCESS;
+ u16 i, count;
+
+ DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
+
+ hw->eeprom.ops.init_params(hw);
+
+ if (words == 0) {
+ status = IXGBE_ERR_INVALID_ARGUMENT;
+ goto out;
+ }
+
+ if (offset + words > hw->eeprom.word_size) {
+ status = IXGBE_ERR_EEPROM;
+ goto out;
+ }
+
+ /*
+ * The EEPROM page size cannot be queried from the chip. We do lazy
+ * initialization. It is worth to do that when we write large buffer.
+ */
+ if ((hw->eeprom.word_page_size == 0) &&
+ (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
+ status = ixgbe_detect_eeprom_page_size_generic(hw, offset);
+ if (status != IXGBE_SUCCESS)
+ goto out;
+
+ /*
+ * We cannot hold synchronization semaphores for too long
+ * to avoid other entity starvation. However it is more efficient
+ * to read in bursts than synchronizing access for each word.
+ */
+ for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
+ count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
+ IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
+ status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
+ count, &data[i]);
+
+ if (status != IXGBE_SUCCESS)
+ break;
+ }
+
+out:
+ return status;
+}
+
+/**
+ * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
+ * @hw: pointer to hardware structure
+ * @offset: offset within the EEPROM to be written to
+ * @words: number of word(s)
+ * @data: 16 bit word(s) to be written to the EEPROM
+ *
+ * If ixgbe_eeprom_update_checksum is not called after this function, the
+ * EEPROM will most likely contain an invalid checksum.
+ **/
+static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data)
+{
+ s32 status;
+ u16 word;
+ u16 page_size;
+ u16 i;
+ u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
+
+ DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
+
+ /* Prepare the EEPROM for writing */
+ status = ixgbe_acquire_eeprom(hw);
+
+ if (status == IXGBE_SUCCESS) {
+ if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
+ ixgbe_release_eeprom(hw);
+ status = IXGBE_ERR_EEPROM;
+ }
+ }
+
+ if (status == IXGBE_SUCCESS) {
+ for (i = 0; i < words; i++) {
+ ixgbe_standby_eeprom(hw);
+
+ /* Send the WRITE ENABLE command (8 bit opcode ) */
+ ixgbe_shift_out_eeprom_bits(hw,
+ IXGBE_EEPROM_WREN_OPCODE_SPI,
+ IXGBE_EEPROM_OPCODE_BITS);
+
+ ixgbe_standby_eeprom(hw);
+
+ /*
+ * Some SPI eeproms use the 8th address bit embedded
+ * in the opcode
+ */
+ if ((hw->eeprom.address_bits == 8) &&
+ ((offset + i) >= 128))
+ write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
+
+ /* Send the Write command (8-bit opcode + addr) */
+ ixgbe_shift_out_eeprom_bits(hw, write_opcode,
+ IXGBE_EEPROM_OPCODE_BITS);
+ ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
+ hw->eeprom.address_bits);
+
+ page_size = hw->eeprom.word_page_size;
+
+ /* Send the data in burst via SPI*/
+ do {
+ word = data[i];
+ word = (word >> 8) | (word << 8);
+ ixgbe_shift_out_eeprom_bits(hw, word, 16);
+
+ if (page_size == 0)
+ break;
+
+ /* do not wrap around page */
+ if (((offset + i) & (page_size - 1)) ==
+ (page_size - 1))
+ break;
+ } while (++i < words);
+
+ ixgbe_standby_eeprom(hw);
+ msec_delay(10);
+ }
+ /* Done with writing - release the EEPROM */
+ ixgbe_release_eeprom(hw);
+ }
+
+ return status;
+}
+
+/**
* ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be written to
@@ -810,7 +1087,6 @@
s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
{
s32 status;
- u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
DEBUGFUNC("ixgbe_write_eeprom_generic");
@@ -821,7 +1097,81 @@
goto out;
}
- /* Prepare the EEPROM for writing */
+ status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
+
+out:
+ return status;
+}
+
+/**
+ * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
+ * @hw: pointer to hardware structure
+ * @offset: offset within the EEPROM to be read
+ * @data: read 16 bit words(s) from EEPROM
+ * @words: number of word(s)
+ *
+ * Reads 16 bit word(s) from EEPROM through bit-bang method
+ **/
+s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data)
+{
+ s32 status = IXGBE_SUCCESS;
+ u16 i, count;
+
+ DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
+
+ hw->eeprom.ops.init_params(hw);
+
+ if (words == 0) {
+ status = IXGBE_ERR_INVALID_ARGUMENT;
+ goto out;
+ }
+
+ if (offset + words > hw->eeprom.word_size) {
+ status = IXGBE_ERR_EEPROM;
+ goto out;
+ }
+
+ /*
+ * We cannot hold synchronization semaphores for too long
+ * to avoid other entity starvation. However it is more efficient
+ * to read in bursts than synchronizing access for each word.
+ */
+ for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
+ count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
+ IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
+
+ status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
+ count, &data[i]);
+
+ if (status != IXGBE_SUCCESS)
+ break;
+ }
+
+out:
+ return status;
+}
+
+/**
+ * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
+ * @hw: pointer to hardware structure
+ * @offset: offset within the EEPROM to be read
+ * @words: number of word(s)
+ * @data: read 16 bit word(s) from EEPROM
+ *
+ * Reads 16 bit word(s) from EEPROM through bit-bang method
+ **/
+static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data)
+{
+ s32 status;
+ u16 word_in;
+ u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
+ u16 i;
+
+ DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
+
+ /* Prepare the EEPROM for reading */
status = ixgbe_acquire_eeprom(hw);
if (status == IXGBE_SUCCESS) {
@@ -832,37 +1182,31 @@
}
if (status == IXGBE_SUCCESS) {
- ixgbe_standby_eeprom(hw);
-
- /* Send the WRITE ENABLE command (8 bit opcode ) */
- ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
- IXGBE_EEPROM_OPCODE_BITS);
-
- ixgbe_standby_eeprom(hw);
-
- /*
- * Some SPI eeproms use the 8th address bit embedded in the
- * opcode
- */
- if ((hw->eeprom.address_bits == 8) && (offset >= 128))
- write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
-
- /* Send the Write command (8-bit opcode + addr) */
- ixgbe_shift_out_eeprom_bits(hw, write_opcode,
- IXGBE_EEPROM_OPCODE_BITS);
- ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
- hw->eeprom.address_bits);
-
- /* Send the data */
- data = (data >> 8) | (data << 8);
- ixgbe_shift_out_eeprom_bits(hw, data, 16);
- ixgbe_standby_eeprom(hw);
-
- /* Done with writing - release the EEPROM */
+ for (i = 0; i < words; i++) {
+ ixgbe_standby_eeprom(hw);
+ /*
+ * Some SPI eeproms use the 8th address bit embedded
+ * in the opcode
+ */
+ if ((hw->eeprom.address_bits == 8) &&
+ ((offset + i) >= 128))
+ read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
+
+ /* Send the READ command (opcode + addr) */
+ ixgbe_shift_out_eeprom_bits(hw, read_opcode,
+ IXGBE_EEPROM_OPCODE_BITS);
+ ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
+ hw->eeprom.address_bits);
+
+ /* Read the data. */
+ word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
+ data[i] = (word_in >> 8) | (word_in << 8);
+ }
+
+ /* End this read operation */
ixgbe_release_eeprom(hw);
}
-out:
return status;
}
@@ -875,11 +1219,9 @@
* Reads 16 bit value from EEPROM through bit-bang method
**/
s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
- u16 *data)
+ u16 *data)
{
s32 status;
- u16 word_in;
- u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
@@ -890,40 +1232,101 @@
goto out;
}
- /* Prepare the EEPROM for reading */
- status = ixgbe_acquire_eeprom(hw);
-
- if (status == IXGBE_SUCCESS) {
- if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
- ixgbe_release_eeprom(hw);
- status = IXGBE_ERR_EEPROM;
+ status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
+
+out:
+ return status;
+}
+
+/**
+ * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in the EEPROM to read
+ * @words: number of word(s)
+ * @data: 16 bit word(s) from the EEPROM
+ *
+ * Reads a 16 bit word(s) from the EEPROM using the EERD register.
+ **/
+s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data)
+{
+ u32 eerd;
+ s32 status = IXGBE_SUCCESS;
+ u32 i;
+
+ DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
+
+ hw->eeprom.ops.init_params(hw);
+
+ if (words == 0) {
+ status = IXGBE_ERR_INVALID_ARGUMENT;
+ goto out;
+ }
+
+ if (offset >= hw->eeprom.word_size) {
+ status = IXGBE_ERR_EEPROM;
+ goto out;
+ }
+
+ for (i = 0; i < words; i++) {
+ eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
+ IXGBE_EEPROM_RW_REG_START;
+
+ IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
+ status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
+
+ if (status == IXGBE_SUCCESS) {
+ data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
+ IXGBE_EEPROM_RW_REG_DATA);
+ } else {
+ DEBUGOUT("Eeprom read timed out\n");
+ goto out;
}
}
-
- if (status == IXGBE_SUCCESS) {
- ixgbe_standby_eeprom(hw);
-
- /*
- * Some SPI eeproms use the 8th address bit embedded in the
- * opcode
- */
- if ((hw->eeprom.address_bits == 8) && (offset >= 128))
- read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
-
- /* Send the READ command (opcode + addr) */
- ixgbe_shift_out_eeprom_bits(hw, read_opcode,
- IXGBE_EEPROM_OPCODE_BITS);
- ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
- hw->eeprom.address_bits);
-
- /* Read the data. */
- word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
- *data = (word_in >> 8) | (word_in << 8);
-
- /* End this read operation */
- ixgbe_release_eeprom(hw);
- }
-
+out:
+ return status;
+}
+
+/**
+ * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
+ * @hw: pointer to hardware structure
+ * @offset: offset within the EEPROM to be used as a scratch pad
+ *
+ * Discover EEPROM page size by writing marching data at given offset.
+ * This function is called only when we are writing a new large buffer
+ * at given offset so the data would be overwritten anyway.
+ **/
+static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
+ u16 offset)
+{
+ u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
+ s32 status = IXGBE_SUCCESS;
+ u16 i;
+
+ DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
+
+ for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
+ data[i] = i;
+
+ hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
+ status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
+ IXGBE_EEPROM_PAGE_SIZE_MAX, data);
+ hw->eeprom.word_page_size = 0;
+ if (status != IXGBE_SUCCESS)
+ goto out;
+
+ status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
+ if (status != IXGBE_SUCCESS)
+ goto out;
+
+ /*
+ * When writing in burst more than the actual page size
+ * EEPROM address wraps around current page.
+ */
+ hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
+
+ DEBUGOUT1("Detected EEPROM page size = %d words.",
+ hw->eeprom.word_page_size);
out:
return status;
}
@@ -938,29 +1341,58 @@
**/
s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
{
- u32 eerd;
- s32 status;
-
- DEBUGFUNC("ixgbe_read_eerd_generic");
+ return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
+}
+
+/**
+ * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in the EEPROM to write
+ * @words: number of word(s)
+ * @data: word(s) write to the EEPROM
+ *
+ * Write a 16 bit word(s) to the EEPROM using the EEWR register.
+ **/
+s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data)
+{
+ u32 eewr;
+ s32 status = IXGBE_SUCCESS;
+ u16 i;
+
+ DEBUGFUNC("ixgbe_write_eewr_generic");
hw->eeprom.ops.init_params(hw);
+ if (words == 0) {
+ status = IXGBE_ERR_INVALID_ARGUMENT;
+ goto out;
+ }
+
if (offset >= hw->eeprom.word_size) {
status = IXGBE_ERR_EEPROM;
goto out;
}
- eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
- IXGBE_EEPROM_RW_REG_START;
-
- IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
- status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
-
- if (status == IXGBE_SUCCESS)
- *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
- IXGBE_EEPROM_RW_REG_DATA);
- else
- DEBUGOUT("Eeprom read timed out\n");
+ for (i = 0; i < words; i++) {
+ eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
+ (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
+ IXGBE_EEPROM_RW_REG_START;
+
+ status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
+ if (status != IXGBE_SUCCESS) {
+ DEBUGOUT("Eeprom write EEWR timed out\n");
+ goto out;
+ }
+
+ IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
+
+ status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
+ if (status != IXGBE_SUCCESS) {
+ DEBUGOUT("Eeprom write EEWR timed out\n");
+ goto out;
+ }
+ }
out:
return status;
@@ -976,37 +1408,7 @@
**/
s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
{
- u32 eewr;
- s32 status;
-
- DEBUGFUNC("ixgbe_write_eewr_generic");
-
- hw->eeprom.ops.init_params(hw);
-
- if (offset >= hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
-
- eewr = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) |
- (data << IXGBE_EEPROM_RW_REG_DATA) | IXGBE_EEPROM_RW_REG_START;
-
- status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
- if (status != IXGBE_SUCCESS) {
- DEBUGOUT("Eeprom write EEWR timed out\n");
- goto out;
- }
-
- IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
-
- status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
- if (status != IXGBE_SUCCESS) {
- DEBUGOUT("Eeprom write EEWR timed out\n");
- goto out;
- }
-
-out:
- return status;
+ return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
}
/**
@@ -1055,7 +1457,8 @@
DEBUGFUNC("ixgbe_acquire_eeprom");
- if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS)
+ if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
+ != IXGBE_SUCCESS)
status = IXGBE_ERR_SWFW_SYNC;
if (status == IXGBE_SUCCESS) {
@@ -1078,7 +1481,7 @@
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
DEBUGOUT("Could not acquire EEPROM grant\n");
- ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
status = IXGBE_ERR_EEPROM;
}
@@ -1124,6 +1527,28 @@
usec_delay(50);
}
+ if (i == timeout) {
+ DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
+ "not granted.\n");
+ /*
+ * this release is particularly important because our attempts
+ * above to get the semaphore may have succeeded, and if there
+ * was a timeout, we should unconditionally clear the semaphore
+ * bits to free the driver to make progress
+ */
+ ixgbe_release_eeprom_semaphore(hw);
+
+ usec_delay(50);
+ /*
+ * one last try
+ * If the SMBI bit is 0 when we read it, then the bit will be
+ * set and we have the semaphore
+ */
+ swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+ if (!(swsm & IXGBE_SWSM_SMBI))
+ status = IXGBE_SUCCESS;
+ }
+
/* Now get the semaphore between SW/FW through the SWESMBI bit */
if (status == IXGBE_SUCCESS) {
for (i = 0; i < timeout; i++) {
@@ -1150,13 +1575,13 @@
*/
if (i >= timeout) {
DEBUGOUT("SWESMBI Software EEPROM semaphore "
- "not granted.\n");
+ "not granted.\n");
ixgbe_release_eeprom_semaphore(hw);
status = IXGBE_ERR_EEPROM;
}
} else {
DEBUGOUT("Software semaphore SMBI between device drivers "
- "not granted.\n");
+ "not granted.\n");
}
return status;
@@ -1202,7 +1627,7 @@
*/
for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
- IXGBE_EEPROM_OPCODE_BITS);
+ IXGBE_EEPROM_OPCODE_BITS);
spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
break;
@@ -1253,7 +1678,7 @@
* @count: number of bits to shift out
**/
static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
- u16 count)
+ u16 count)
{
u32 eec;
u32 mask;
@@ -1404,7 +1829,7 @@
eec &= ~IXGBE_EEC_REQ;
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
/* Delay before attempt to obtain semaphore again to allow FW access */
msec_delay(hw->eeprom.semaphore_delay);
@@ -1465,7 +1890,7 @@
* caller does not need checksum_val, the value can be NULL.
**/
s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
- u16 *checksum_val)
+ u16 *checksum_val)
{
s32 status;
u16 checksum;
@@ -1523,7 +1948,7 @@
if (status == IXGBE_SUCCESS) {
checksum = hw->eeprom.ops.calc_checksum(hw);
status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
- checksum);
+ checksum);
} else {
DEBUGOUT("EEPROM read failed\n");
}
@@ -1553,7 +1978,7 @@
status = IXGBE_ERR_INVALID_MAC_ADDR;
/* Reject the zero address */
} else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
- mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
+ mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
DEBUGOUT("MAC address is all zeros\n");
status = IXGBE_ERR_INVALID_MAC_ADDR;
}
@@ -1571,7 +1996,7 @@
* Puts an ethernet address into a receive address register.
**/
s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
- u32 enable_addr)
+ u32 enable_addr)
{
u32 rar_low, rar_high;
u32 rar_entries = hw->mac.num_rar_entries;
@@ -1592,9 +2017,9 @@
* order from network order (big endian) to little endian
*/
rar_low = ((u32)addr[0] |
- ((u32)addr[1] << 8) |
- ((u32)addr[2] << 16) |
- ((u32)addr[3] << 24));
+ ((u32)addr[1] << 8) |
+ ((u32)addr[2] << 16) |
+ ((u32)addr[3] << 24));
/*
* Some parts put the VMDq setting in the extra RAH bits,
* so save everything except the lower 16 bits that hold part
@@ -1676,18 +2101,18 @@
hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
- hw->mac.addr[0], hw->mac.addr[1],
- hw->mac.addr[2]);
+ hw->mac.addr[0], hw->mac.addr[1],
+ hw->mac.addr[2]);
DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
- hw->mac.addr[4], hw->mac.addr[5]);
+ hw->mac.addr[4], hw->mac.addr[5]);
} else {
/* Setup the receive address. */
DEBUGOUT("Overriding MAC Address in RAR[0]\n");
DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
- hw->mac.addr[0], hw->mac.addr[1],
- hw->mac.addr[2]);
+ hw->mac.addr[0], hw->mac.addr[1],
+ hw->mac.addr[2]);
DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
- hw->mac.addr[4], hw->mac.addr[5]);
+ hw->mac.addr[4], hw->mac.addr[5]);
hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
@@ -1713,9 +2138,8 @@
for (i = 0; i < hw->mac.mcft_size; i++)
IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
- (void) ixgbe_init_uta_tables(hw);
-
- return IXGBE_SUCCESS;
+ /* Should always be IXGBE_SUCCESS. */
+ return ixgbe_init_uta_tables(hw);
}
/**
@@ -1733,7 +2157,7 @@
DEBUGFUNC("ixgbe_add_uc_addr");
DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
- addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
/*
* Place this address in the RAR if there is room,
@@ -1766,7 +2190,7 @@
* manually putting the device into promiscuous mode.
**/
s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
- u32 addr_count, ixgbe_mc_addr_itr next)
+ u32 addr_count, ixgbe_mc_addr_itr next)
{
u8 *addr;
u32 i;
@@ -1903,14 +2327,14 @@
* @mc_addr_list: the list of new multicast addresses
* @mc_addr_count: number of addresses
* @next: iterator function to walk the multicast address list
+ * @clear: flag, when set clears the table beforehand
*
- * The given list replaces any existing list. Clears the MC addrs from receive
- * address registers and the multicast table. Uses unused receive address
- * registers for the first multicast addresses, and hashes the rest into the
- * multicast table.
+ * When the clear flag is set, the given list replaces any existing list.
+ * Hashes the given addresses into the multicast table.
**/
s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
- u32 mc_addr_count, ixgbe_mc_addr_itr next)
+ u32 mc_addr_count, ixgbe_mc_addr_itr next,
+ bool clear)
{
u32 i;
u32 vmdq;
@@ -1925,8 +2349,11 @@
hw->addr_ctrl.mta_in_use = 0;
/* Clear mta_shadow */
- DEBUGOUT(" Clearing MTA\n");
- (void) memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
+ if (clear) {
+ DEBUGOUT(" Clearing MTA\n");
+ (void) memset(&hw->mac.mta_shadow, 0,
+ sizeof(hw->mac.mta_shadow));
+ }
/* Update mta_shadow */
for (i = 0; i < mc_addr_count; i++) {
@@ -1941,7 +2368,7 @@
if (hw->addr_ctrl.mta_in_use > 0)
IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
- IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
+ IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
return IXGBE_SUCCESS;
@@ -1961,7 +2388,7 @@
if (a->mta_in_use > 0)
IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
- hw->mac.mc_filter_type);
+ hw->mac.mc_filter_type);
return IXGBE_SUCCESS;
}
@@ -1987,28 +2414,44 @@
/**
* ixgbe_fc_enable_generic - Enable flow control
* @hw: pointer to hardware structure
- * @packetbuf_num: packet buffer number (0-7)
*
* Enable flow control according to the current settings.
**/
-s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
+s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
{
s32 ret_val = IXGBE_SUCCESS;
u32 mflcn_reg, fccfg_reg;
u32 reg;
- u32 rx_pba_size;
u32 fcrtl, fcrth;
+ int i;
DEBUGFUNC("ixgbe_fc_enable_generic");
+ /* Validate the water mark configuration */
+ if (!hw->fc.pause_time) {
+ ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+ goto out;
+ }
+
+ /* Low water mark of zero causes XOFF floods */
+ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
+ if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
+ hw->fc.high_water[i]) {
+ if (!hw->fc.low_water[i] ||
+ hw->fc.low_water[i] >= hw->fc.high_water[i]) {
+ DEBUGOUT("Invalid water mark configuration\n");
+ ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+ goto out;
+ }
+ }
+ }
+
/* Negotiate the fc mode to use */
- ret_val = ixgbe_fc_autoneg(hw);
- if (ret_val == IXGBE_ERR_FLOW_CONTROL)
- goto out;
+ ixgbe_fc_autoneg(hw);
/* Disable any previous flow control settings */
mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
- mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
+ mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
@@ -2064,212 +2507,41 @@
IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
- rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
- rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
-
- fcrth = (rx_pba_size - hw->fc.high_water) << 10;
- fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
-
- if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
- fcrth |= IXGBE_FCRTH_FCEN;
- if (hw->fc.send_xon)
- fcrtl |= IXGBE_FCRTL_XONE;
+
+ /* Set up and enable Rx high/low water mark thresholds, enable XON. */
+ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
+ if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
+ hw->fc.high_water[i]) {
+ fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
+ IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
+ fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
+ } else {
+ IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
+ /*
+ * In order to prevent Tx hangs when the internal Tx
+ * switch is enabled we must set the high water mark
+ * to the maximum FCRTH value. This allows the Tx
+ * switch to function even under heavy Rx workloads.
+ */
+ fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
+ }
+
+ IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
}
- IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
- IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
-
/* Configure pause time (2 TCs per register) */
- reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
- if ((packetbuf_num & 1) == 0)
- reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
- else
- reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
- IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
-
- IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
+ reg = hw->fc.pause_time * 0x00010001;
+ for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
+ IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
+
+ /* Configure flow control refresh threshold value */
+ IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
out:
return ret_val;
}
/**
- * ixgbe_fc_autoneg - Configure flow control
- * @hw: pointer to hardware structure
- *
- * Compares our advertised flow control capabilities to those advertised by
- * our link partner, and determines the proper flow control mode to use.
- **/
-s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
-{
- s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
- ixgbe_link_speed speed;
- bool link_up;
-
- DEBUGFUNC("ixgbe_fc_autoneg");
-
- if (hw->fc.disable_fc_autoneg)
- goto out;
-
- /*
- * AN should have completed when the cable was plugged in.
- * Look for reasons to bail out. Bail out if:
- * - FC autoneg is disabled, or if
- * - link is not up.
- *
- * Since we're being called from an LSC, link is already known to be up.
- * So use link_up_wait_to_complete=FALSE.
- */
- hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
- if (!link_up) {
- ret_val = IXGBE_ERR_FLOW_CONTROL;
- goto out;
- }
-
- switch (hw->phy.media_type) {
- /* Autoneg flow control on fiber adapters */
- case ixgbe_media_type_fiber:
- if (speed == IXGBE_LINK_SPEED_1GB_FULL)
- ret_val = ixgbe_fc_autoneg_fiber(hw);
- break;
-
- /* Autoneg flow control on backplane adapters */
- case ixgbe_media_type_backplane:
- ret_val = ixgbe_fc_autoneg_backplane(hw);
- break;
-
- /* Autoneg flow control on copper adapters */
- case ixgbe_media_type_copper:
- if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
- ret_val = ixgbe_fc_autoneg_copper(hw);
- break;
-
- default:
- break;
- }
-
-out:
- if (ret_val == IXGBE_SUCCESS) {
- hw->fc.fc_was_autonegged = TRUE;
- } else {
- hw->fc.fc_was_autonegged = FALSE;
- hw->fc.current_mode = hw->fc.requested_mode;
- }
- return ret_val;
-}
-
-/**
- * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
- * @hw: pointer to hardware structure
- * @speed:
- * @link_up
- *
- * Enable flow control according on 1 gig fiber.
- **/
-static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
-{
- u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
- s32 ret_val;
-
- /*
- * On multispeed fiber at 1g, bail out if
- * - link is up but AN did not complete, or if
- * - link is up and AN completed but timed out
- */
-
- linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
- if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
- ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
- ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
- goto out;
- }
-
- pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
- pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
-
- ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
- pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
- IXGBE_PCS1GANA_ASM_PAUSE,
- IXGBE_PCS1GANA_SYM_PAUSE,
- IXGBE_PCS1GANA_ASM_PAUSE);
-
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
- * @hw: pointer to hardware structure
- *
- * Enable flow control according to IEEE clause 37.
- **/
-static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
-{
- u32 links2, anlp1_reg, autoc_reg, links;
- s32 ret_val;
-
- /*
- * On backplane, bail out if
- * - backplane autoneg was not completed, or if
- * - we are 82599 and link partner is not AN enabled
- */
- links = IXGBE_READ_REG(hw, IXGBE_LINKS);
- if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
- hw->fc.fc_was_autonegged = FALSE;
- hw->fc.current_mode = hw->fc.requested_mode;
- ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
- goto out;
- }
-
- if (hw->mac.type == ixgbe_mac_82599EB) {
- links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
- if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
- hw->fc.fc_was_autonegged = FALSE;
- hw->fc.current_mode = hw->fc.requested_mode;
- ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
- goto out;
- }
- }
- /*
- * Read the 10g AN autoc and LP ability registers and resolve
- * local flow control settings accordingly
- */
- autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
-
- ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
- anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
- IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
-
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
- * @hw: pointer to hardware structure
- *
- * Enable flow control according to IEEE clause 37.
- **/
-static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
-{
- u16 technology_ability_reg = 0;
- u16 lp_technology_ability_reg = 0;
-
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &technology_ability_reg);
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &lp_technology_ability_reg);
-
- return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
- (u32)lp_technology_ability_reg,
- IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
- IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
-}
-
-/**
* ixgbe_negotiate_fc - Negotiate flow control
* @hw: pointer to hardware structure
* @adv_reg: flow control advertised settings
@@ -2319,173 +2591,161 @@
}
/**
- * ixgbe_setup_fc - Set up flow control
+ * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
* @hw: pointer to hardware structure
*
- * Called at init time to set up flow control.
+ * Enable flow control according on 1 gig fiber.
**/
-s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
+static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
{
- s32 ret_val = IXGBE_SUCCESS;
- u32 reg = 0, reg_bp = 0;
- u16 reg_cu = 0;
-
- DEBUGFUNC("ixgbe_setup_fc");
-
- /* Validate the packetbuf configuration */
- if (packetbuf_num < 0 || packetbuf_num > 7) {
- DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
- " 0-7\n", packetbuf_num);
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
- }
+ u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
+ s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
/*
- * Validate the water mark configuration. Zero water marks are invalid
- * because it causes the controller to just blast out fc packets.
+ * On multispeed fiber at 1g, bail out if
+ * - link is up but AN did not complete, or if
+ * - link is up and AN completed but timed out
*/
- if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
- DEBUGOUT("Invalid water mark configuration\n");
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+
+ linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
+ if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
+ (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
goto out;
- }
+
+ pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
+ pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
+
+ ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
+ pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
+ IXGBE_PCS1GANA_ASM_PAUSE,
+ IXGBE_PCS1GANA_SYM_PAUSE,
+ IXGBE_PCS1GANA_ASM_PAUSE);
+
+out:
+ return ret_val;
+}
+
+/**
+ * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
+ * @hw: pointer to hardware structure
+ *
+ * Enable flow control according to IEEE clause 37.
+ **/
+static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
+{
+ u32 links2, anlp1_reg, autoc_reg, links;
+ s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
/*
- * Validate the requested mode. Strict IEEE mode does not allow
- * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
+ * On backplane, bail out if
+ * - backplane autoneg was not completed, or if
+ * - we are 82599 and link partner is not AN enabled
+ */
+ links = IXGBE_READ_REG(hw, IXGBE_LINKS);
+ if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
+ goto out;
+
+ if (hw->mac.type == ixgbe_mac_82599EB) {
+ links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
+ if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
+ goto out;
+ }
+ /*
+ * Read the 10g AN autoc and LP ability registers and resolve
+ * local flow control settings accordingly
*/
- if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
- DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
- }
+ autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+ anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
+
+ ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
+ anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
+ IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
+
+out:
+ return ret_val;
+}
+
+/**
+ * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
+ * @hw: pointer to hardware structure
+ *
+ * Enable flow control according to IEEE clause 37.
+ **/
+static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
+{
+ u16 technology_ability_reg = 0;
+ u16 lp_technology_ability_reg = 0;
+
+ hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ &technology_ability_reg);
+ hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ &lp_technology_ability_reg);
+
+ return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
+ (u32)lp_technology_ability_reg,
+ IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
+ IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
+}
+
+/**
+ * ixgbe_fc_autoneg - Configure flow control
+ * @hw: pointer to hardware structure
+ *
+ * Compares our advertised flow control capabilities to those advertised by
+ * our link partner, and determines the proper flow control mode to use.
+ **/
+void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
+{
+ s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
+ ixgbe_link_speed speed;
+ bool link_up;
+
+ DEBUGFUNC("ixgbe_fc_autoneg");
/*
- * 10gig parts do not have a word in the EEPROM to determine the
- * default flow control setting, so we explicitly set it to full.
+ * AN should have completed when the cable was plugged in.
+ * Look for reasons to bail out. Bail out if:
+ * - FC autoneg is disabled, or if
+ * - link is not up.
*/
- if (hw->fc.requested_mode == ixgbe_fc_default)
- hw->fc.requested_mode = ixgbe_fc_full;
-
- /*
- * Set up the 1G and 10G flow control advertisement registers so the
- * HW will be able to do fc autoneg once the cable is plugged in. If
- * we link at 10G, the 1G advertisement is harmless and vice versa.
- */
+ if (hw->fc.disable_fc_autoneg)
+ goto out;
+
+ hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
+ if (!link_up)
+ goto out;
switch (hw->phy.media_type) {
+ /* Autoneg flow control on fiber adapters */
case ixgbe_media_type_fiber:
- case ixgbe_media_type_backplane:
- reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
- reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+ if (speed == IXGBE_LINK_SPEED_1GB_FULL)
+ ret_val = ixgbe_fc_autoneg_fiber(hw);
break;
+ /* Autoneg flow control on backplane adapters */
+ case ixgbe_media_type_backplane:
+ ret_val = ixgbe_fc_autoneg_backplane(hw);
+ break;
+
+ /* Autoneg flow control on copper adapters */
case ixgbe_media_type_copper:
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
+ if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
+ ret_val = ixgbe_fc_autoneg_copper(hw);
break;
default:
- ;
+ break;
}
- /*
- * The possible values of fc.requested_mode are:
- * 0: Flow control is completely disabled
- * 1: Rx flow control is enabled (we can receive pause frames,
- * but not send pause frames).
- * 2: Tx flow control is enabled (we can send pause frames but
- * we do not support receiving pause frames).
- * 3: Both Rx and Tx flow control (symmetric) are enabled.
- * other: Invalid.
- */
- switch (hw->fc.requested_mode) {
- case ixgbe_fc_none:
- /* Flow control completely disabled by software override. */
- reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
- if (hw->phy.media_type == ixgbe_media_type_backplane)
- reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
- IXGBE_AUTOC_ASM_PAUSE);
- else if (hw->phy.media_type == ixgbe_media_type_copper)
- reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
- break;
- case ixgbe_fc_rx_pause:
- /*
- * Rx Flow control is enabled and Tx Flow control is
- * disabled by software override. Since there really
- * isn't a way to advertise that we are capable of RX
- * Pause ONLY, we will advertise that we support both
- * symmetric and asymmetric Rx PAUSE. Later, we will
- * disable the adapter's ability to send PAUSE frames.
- */
- reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
- if (hw->phy.media_type == ixgbe_media_type_backplane)
- reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
- IXGBE_AUTOC_ASM_PAUSE);
- else if (hw->phy.media_type == ixgbe_media_type_copper)
- reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
- break;
- case ixgbe_fc_tx_pause:
- /*
- * Tx Flow control is enabled, and Rx Flow control is
- * disabled by software override.
- */
- reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
- reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
- if (hw->phy.media_type == ixgbe_media_type_backplane) {
- reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
- reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
- } else if (hw->phy.media_type == ixgbe_media_type_copper) {
- reg_cu |= (IXGBE_TAF_ASM_PAUSE);
- reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
- }
- break;
- case ixgbe_fc_full:
- /* Flow control (both Rx and Tx) is enabled by SW override. */
- reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
- if (hw->phy.media_type == ixgbe_media_type_backplane)
- reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
- IXGBE_AUTOC_ASM_PAUSE);
- else if (hw->phy.media_type == ixgbe_media_type_copper)
- reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
- break;
- default:
- DEBUGOUT("Flow control param set incorrectly\n");
- ret_val = IXGBE_ERR_CONFIG;
- goto out;
+out:
+ if (ret_val == IXGBE_SUCCESS) {
+ hw->fc.fc_was_autonegged = TRUE;
+ } else {
+ hw->fc.fc_was_autonegged = FALSE;
+ hw->fc.current_mode = hw->fc.requested_mode;
}
-
- /*
- * Enable auto-negotiation between the MAC & PHY;
- * the MAC will advertise clause 37 flow control.
- */
- IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
- reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
-
- /* Disable AN timeout */
- if (hw->fc.strict_ieee)
- reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
-
- IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
- DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
-
- /*
- * AUTOC restart handles negotiation of 1G and 10G on backplane
- * and copper. There is no need to set the PCS1GCTL register.
- *
- */
- if (hw->phy.media_type == ixgbe_media_type_backplane) {
- reg_bp |= IXGBE_AUTOC_AN_RESTART;
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
- } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
- (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
- hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
- }
-
- DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
-out:
- return ret_val;
}
/**
@@ -2499,78 +2759,60 @@
**/
s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
{
+ s32 status = IXGBE_SUCCESS;
u32 i;
- u32 reg_val;
- u32 number_of_queues;
- s32 status = IXGBE_SUCCESS;
DEBUGFUNC("ixgbe_disable_pcie_master");
- /* Just jump out if bus mastering is already disabled */
+ /* Always set this bit to ensure any future transactions are blocked */
+ IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
+
+ /* Exit if master requets are blocked */
if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
goto out;
- /* Disable the receive unit by stopping each queue */
- number_of_queues = hw->mac.max_rx_queues;
- for (i = 0; i < number_of_queues; i++) {
- reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
- if (reg_val & IXGBE_RXDCTL_ENABLE) {
- reg_val &= ~IXGBE_RXDCTL_ENABLE;
- IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
- }
+ /* Poll for master request bit to clear */
+ for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
+ usec_delay(100);
+ if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
+ goto out;
}
- reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
- reg_val |= IXGBE_CTRL_GIO_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
-
- for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
- if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
- goto check_device_status;
- usec_delay(100);
- }
-
+ /*
+ * Two consecutive resets are required via CTRL.RST per datasheet
+ * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
+ * of this need. The first reset prevents new master requests from
+ * being issued by our device. We then must wait 1usec or more for any
+ * remaining completions from the PCIe bus to trickle in, and then reset
+ * again to clear out any effects they may have had on our device.
+ */
DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
- status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
+ hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
/*
* Before proceeding, make sure that the PCIe block does not have
* transactions pending.
*/
-check_device_status:
for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
+ usec_delay(100);
if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
- IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
- break;
- usec_delay(100);
+ IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
+ goto out;
}
- if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
- DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
- else
- goto out;
-
- /*
- * Two consecutive resets are required via CTRL.RST per datasheet
- * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
- * of this need. The first reset prevents new master requests from
- * being issued by our device. We then must wait 1usec for any
- * remaining completions from the PCIe bus to trickle in, and then reset
- * again to clear out any effects they may have had on our device.
- */
- hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
+ DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
+ status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
out:
return status;
}
-
/**
* ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
* @hw: pointer to hardware structure
* @mask: Mask to specify which semaphore to acquire
*
- * Acquires the SWFW semaphore thought the GSSR register for the specified
+ * Acquires the SWFW semaphore through the GSSR register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash)
**/
s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
@@ -2620,7 +2862,7 @@
* @hw: pointer to hardware structure
* @mask: Mask to specify which semaphore to release
*
- * Releases the SWFW semaphore thought the GSSR register for the specified
+ * Releases the SWFW semaphore through the GSSR register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash)
**/
void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
@@ -2640,6 +2882,63 @@
}
/**
+ * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
+ * @hw: pointer to hardware structure
+ *
+ * Stops the receive data path and waits for the HW to internally empty
+ * the Rx security block
+ **/
+s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
+{
+#define IXGBE_MAX_SECRX_POLL 40
+
+ int i;
+ int secrxreg;
+
+ DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
+
+
+ secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
+ secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
+ IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
+ for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
+ secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
+ if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
+ break;
+ else
+ /* Use interrupt-safe sleep just in case */
+ usec_delay(1000);
+ }
+
+ /* For informational purposes only */
+ if (i >= IXGBE_MAX_SECRX_POLL)
+ DEBUGOUT("Rx unit being enabled before security "
+ "path fully disabled. Continuing with init.\n");
+
+ return IXGBE_SUCCESS;
+}
+
+/**
+ * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
+ * @hw: pointer to hardware structure
+ *
+ * Enables the receive data path.
+ **/
+s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
+{
+ int secrxreg;
+
+ DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
+
+ secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
+ secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
+ IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
+ IXGBE_WRITE_FLUSH(hw);
+
+ return IXGBE_SUCCESS;
+}
+
+/**
* ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
* @hw: pointer to hardware structure
* @regval: register value to write to RXCTRL
@@ -2679,6 +2978,7 @@
autoc_reg |= IXGBE_AUTOC_AN_RESTART;
autoc_reg |= IXGBE_AUTOC_FLU;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
+ IXGBE_WRITE_FLUSH(hw);
msec_delay(10);
}
@@ -2726,7 +3026,7 @@
* get and set mac_addr routines.
**/
static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
- u16 *san_mac_offset)
+ u16 *san_mac_offset)
{
DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
@@ -2777,7 +3077,7 @@
hw->mac.ops.set_lan_id(hw);
/* apply the port offset to the address offset */
(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
- (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
+ (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
for (i = 0; i < 3; i++) {
hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
san_mac_addr[i * 2] = (u8)(san_mac_data);
@@ -2816,7 +3116,7 @@
hw->mac.ops.set_lan_id(hw);
/* Apply the port offset to the address offset */
(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
- (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
+ (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
for (i = 0; i < 3; i++) {
san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
@@ -2836,20 +3136,35 @@
* Read PCIe configuration space, and get the MSI-X vector count from
* the capabilities table.
**/
-u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
+u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
{
- u32 msix_count = 64;
+ u16 msix_count = 1;
+ u16 max_msix_count;
+ u16 pcie_offset;
+
+ switch (hw->mac.type) {
+ case ixgbe_mac_82598EB:
+ pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
+ max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
+ break;
+ case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
+ pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
+ max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
+ break;
+ default:
+ return msix_count;
+ }
DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
- if (hw->mac.msix_vectors_from_pcie) {
- msix_count = IXGBE_READ_PCIE_WORD(hw,
- IXGBE_PCIE_MSIX_82599_CAPS);
- msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
-
- /* MSI-X count is zero-based in HW, so increment to give
- * proper value */
- msix_count++;
- }
+ msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
+ msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
+
+ /* MSI-X count is zero-based in HW */
+ msix_count++;
+
+ if (msix_count > max_msix_count)
+ msix_count = max_msix_count;
return msix_count;
}
@@ -3004,6 +3319,33 @@
}
/**
+ * This function should only be involved in the IOV mode.
+ * In IOV mode, Default pool is next pool after the number of
+ * VFs advertized and not 0.
+ * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
+ *
+ * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
+ * @hw: pointer to hardware struct
+ * @vmdq: VMDq pool index
+ **/
+s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
+{
+ u32 rar = hw->mac.san_mac_rar_index;
+
+ DEBUGFUNC("ixgbe_set_vmdq_san_mac");
+
+ if (vmdq < 32) {
+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
+ } else {
+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
+ }
+
+ return IXGBE_SUCCESS;
+}
+
+/**
* ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
* @hw: pointer to hardware structure
**/
@@ -3077,14 +3419,13 @@
* Turn on/off specified VLAN in the VLAN filter table.
**/
s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
- bool vlan_on)
+ bool vlan_on)
{
s32 regindex;
u32 bitindex;
u32 vfta;
- u32 bits;
- u32 vt;
u32 targetbit;
+ s32 ret_val = IXGBE_SUCCESS;
bool vfta_changed = FALSE;
DEBUGFUNC("ixgbe_set_vfta_generic");
@@ -3122,7 +3463,41 @@
}
/* Part 2
- * If VT Mode is set
+ * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
+ */
+ ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
+ &vfta_changed);
+ if (ret_val != IXGBE_SUCCESS)
+ return ret_val;
+
+ if (vfta_changed)
+ IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
+
+ return IXGBE_SUCCESS;
+}
+
+/**
+ * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
+ * @hw: pointer to hardware structure
+ * @vlan: VLAN id to write to VLAN filter
+ * @vind: VMDq output index that maps queue to VLAN id in VFVFB
+ * @vlan_on: boolean flag to turn on/off VLAN in VFVF
+ * @vfta_changed: pointer to boolean flag which indicates whether VFTA
+ * should be changed
+ *
+ * Turn on/off specified bit in VLVF table.
+ **/
+s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
+ bool vlan_on, bool *vfta_changed)
+{
+ u32 vt;
+
+ DEBUGFUNC("ixgbe_set_vlvf_generic");
+
+ if (vlan > 4095)
+ return IXGBE_ERR_PARAM;
+
+ /* If VT Mode is set
* Either vlan_on
* make sure the vlan is in VLVF
* set the vind bit in the matching VLVFB
@@ -3132,6 +3507,7 @@
vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
if (vt & IXGBE_VT_CTL_VT_ENABLE) {
s32 vlvf_index;
+ u32 bits;
vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
if (vlvf_index < 0)
@@ -3141,39 +3517,39 @@
/* set the pool bit */
if (vind < 32) {
bits = IXGBE_READ_REG(hw,
- IXGBE_VLVFB(vlvf_index*2));
+ IXGBE_VLVFB(vlvf_index * 2));
bits |= (1 << vind);
IXGBE_WRITE_REG(hw,
- IXGBE_VLVFB(vlvf_index*2),
+ IXGBE_VLVFB(vlvf_index * 2),
bits);
} else {
bits = IXGBE_READ_REG(hw,
- IXGBE_VLVFB((vlvf_index*2)+1));
- bits |= (1 << (vind-32));
+ IXGBE_VLVFB((vlvf_index * 2) + 1));
+ bits |= (1 << (vind - 32));
IXGBE_WRITE_REG(hw,
- IXGBE_VLVFB((vlvf_index*2)+1),
- bits);
+ IXGBE_VLVFB((vlvf_index * 2) + 1),
+ bits);
}
} else {
/* clear the pool bit */
if (vind < 32) {
bits = IXGBE_READ_REG(hw,
- IXGBE_VLVFB(vlvf_index*2));
+ IXGBE_VLVFB(vlvf_index * 2));
bits &= ~(1 << vind);
IXGBE_WRITE_REG(hw,
- IXGBE_VLVFB(vlvf_index*2),
+ IXGBE_VLVFB(vlvf_index * 2),
bits);
bits |= IXGBE_READ_REG(hw,
- IXGBE_VLVFB((vlvf_index*2)+1));
+ IXGBE_VLVFB((vlvf_index * 2) + 1));
} else {
bits = IXGBE_READ_REG(hw,
- IXGBE_VLVFB((vlvf_index*2)+1));
- bits &= ~(1 << (vind-32));
+ IXGBE_VLVFB((vlvf_index * 2) + 1));
+ bits &= ~(1 << (vind - 32));
IXGBE_WRITE_REG(hw,
- IXGBE_VLVFB((vlvf_index*2)+1),
- bits);
+ IXGBE_VLVFB((vlvf_index * 2) + 1),
+ bits);
bits |= IXGBE_READ_REG(hw,
- IXGBE_VLVFB(vlvf_index*2));
+ IXGBE_VLVFB(vlvf_index * 2));
}
}
@@ -3195,20 +3571,16 @@
if (bits) {
IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
(IXGBE_VLVF_VIEN | vlan));
- if (!vlan_on) {
+ if ((!vlan_on) && (vfta_changed != NULL)) {
/* someone wants to clear the vfta entry
* but some pools/VFs are still using it.
* Ignore it. */
- vfta_changed = FALSE;
+ *vfta_changed = FALSE;
}
- }
- else
+ } else
IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
}
- if (vfta_changed)
- IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
-
return IXGBE_SUCCESS;
}
@@ -3229,8 +3601,8 @@
for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
- IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
- IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
+ IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
+ IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
}
return IXGBE_SUCCESS;
@@ -3246,7 +3618,7 @@
* Reads the links register to determine if link is up and the current speed
**/
s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *link_up, bool link_up_wait_to_complete)
+ bool *link_up, bool link_up_wait_to_complete)
{
u32 links_reg, links_orig;
u32 i;
@@ -3260,7 +3632,7 @@
if (links_orig != links_reg) {
DEBUGOUT2("LINKS changed from %08X to %08X\n",
- links_orig, links_reg);
+ links_orig, links_reg);
}
if (link_up_wait_to_complete) {
@@ -3285,20 +3657,14 @@
IXGBE_LINKS_SPEED_10G_82599)
*speed = IXGBE_LINK_SPEED_10GB_FULL;
else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
- IXGBE_LINKS_SPEED_1G_82599)
+ IXGBE_LINKS_SPEED_1G_82599)
*speed = IXGBE_LINK_SPEED_1GB_FULL;
else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
- IXGBE_LINKS_SPEED_100_82599)
+ IXGBE_LINKS_SPEED_100_82599)
*speed = IXGBE_LINK_SPEED_100_FULL;
else
*speed = IXGBE_LINK_SPEED_UNKNOWN;
- /* if link is down, zero out the current_mode */
- if (*link_up == FALSE) {
- hw->fc.current_mode = ixgbe_fc_none;
- hw->fc.fc_was_autonegged = FALSE;
- }
-
return IXGBE_SUCCESS;
}
@@ -3313,7 +3679,7 @@
* block to check the support for the alternative WWNN/WWPN prefix support.
**/
s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
- u16 *wwpn_prefix)
+ u16 *wwpn_prefix)
{
u16 offset, caps;
u16 alt_san_mac_blk_offset;
@@ -3326,7 +3692,7 @@
/* check if alternative SAN MAC is supported */
hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
- &alt_san_mac_blk_offset);
+ &alt_san_mac_blk_offset);
if ((alt_san_mac_blk_offset == 0) ||
(alt_san_mac_blk_offset == 0xFFFF))
@@ -3399,28 +3765,6 @@
}
/**
- * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
- * control
- * @hw: pointer to hardware structure
- *
- * There are several phys that do not support autoneg flow control. This
- * function check the device id to see if the associated phy supports
- * autoneg flow control.
- **/
-static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
-{
-
- DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
-
- switch (hw->device_id) {
- case IXGBE_DEV_ID_82599_T3_LOM:
- return IXGBE_SUCCESS;
- default:
- return IXGBE_ERR_FC_NOT_SUPPORTED;
- }
-}
-
-/**
* ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
* @hw: pointer to hardware structure
* @enable: enable or disable switch for anti-spoofing
@@ -3444,20 +3788,22 @@
* PFVFSPOOF register array is size 8 with 8 bits assigned to
* MAC anti-spoof enables in each register array element.
*/
- for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
+ for (j = 0; j < pf_target_reg; j++)
IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
- /* If not enabling anti-spoofing then done */
- if (!enable)
- return;
-
/*
* The PF should be allowed to spoof so that it can support
- * emulation mode NICs. Reset the bit assigned to the PF
+ * emulation mode NICs. Do not set the bits assigned to the PF
*/
- pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
- pfvfspoof ^= (1 << pf_target_shift);
- IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
+ pfvfspoof &= (1 << pf_target_shift) - 1;
+ IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
+
+ /*
+ * Remaining pools belong to the PF so they do not need to have
+ * anti-spoofing enabled.
+ */
+ for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
+ IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
}
/**
@@ -3516,15 +3862,301 @@
/* Enable relaxed ordering */
for (i = 0; i < hw->mac.max_tx_queues; i++) {
regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
- regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+ regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
}
for (i = 0; i < hw->mac.max_rx_queues; i++) {
regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
- regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
- IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+ regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
+ IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
}
}
+
+/**
+ * ixgbe_calculate_checksum - Calculate checksum for buffer
+ * @buffer: pointer to EEPROM
+ * @length: size of EEPROM to calculate a checksum for
+ * Calculates the checksum for some buffer on a specified length. The
+ * checksum calculated is returned.
+ **/
+static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
+{
+ u32 i;
+ u8 sum = 0;
+
+ DEBUGFUNC("ixgbe_calculate_checksum");
+
+ if (!buffer)
+ return 0;
+
+ for (i = 0; i < length; i++)
+ sum += buffer[i];
+
+ return (u8) (0 - sum);
+}
+
+/**
+ * ixgbe_host_interface_command - Issue command to manageability block
+ * @hw: pointer to the HW structure
+ * @buffer: contains the command to write and where the return status will
+ * be placed
+ * @length: length of buffer, must be multiple of 4 bytes
+ *
+ * Communicates with the manageability block. On success return IXGBE_SUCCESS
+ * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
+ **/
+static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
+ u32 length)
+{
+ u32 hicr, i, bi;
+ u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
+ u8 buf_len, dword_len;
+
+ s32 ret_val = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_host_interface_command");
+
+ if (length == 0 || length & 0x3 ||
+ length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
+ DEBUGOUT("Buffer length failure.\n");
+ ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
+ goto out;
+ }
+
+ /* Check that the host interface is enabled. */
+ hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
+ if ((hicr & IXGBE_HICR_EN) == 0) {
+ DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
+ ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
+ goto out;
+ }
+
+ /* Calculate length in DWORDs */
+ dword_len = length >> 2;
+
+ /*
+ * The device driver writes the relevant command block
+ * into the ram area.
+ */
+ for (i = 0; i < dword_len; i++)
+ IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
+ i, IXGBE_CPU_TO_LE32(buffer[i]));
+
+ /* Setting this bit tells the ARC that a new command is pending. */
+ IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
+
+ for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
+ hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
+ if (!(hicr & IXGBE_HICR_C))
+ break;
+ msec_delay(1);
+ }
+
+ /* Check command successful completion. */
+ if (i == IXGBE_HI_COMMAND_TIMEOUT ||
+ (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
+ DEBUGOUT("Command has failed with no status valid.\n");
+ ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
+ goto out;
+ }
+
+ /* Calculate length in DWORDs */
+ dword_len = hdr_size >> 2;
+
+ /* first pull in the header so we know the buffer length */
+ for (bi = 0; bi < dword_len; bi++) {
+ buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
+ buffer[bi] = IXGBE_LE32_TO_CPUS(buffer[bi]);
+ }
+
+ /* If there is any thing in data position pull it in */
+ buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
+ if (buf_len == 0)
+ goto out;
+
+ if (length < (buf_len + hdr_size)) {
+ DEBUGOUT("Buffer not large enough for reply message.\n");
+ ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
+ goto out;
+ }
+
+ /* Calculate length in DWORDs, add 3 for odd lengths */
+ dword_len = (buf_len + 3) >> 2;
+
+ /* Pull in the rest of the buffer (bi is where we left off)*/
+ for (; bi <= dword_len; bi++) {
+ buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
+ buffer[bi] = IXGBE_LE32_TO_CPUS(buffer[bi]);
+ }
+
+out:
+ return ret_val;
+}
+
+/**
+ * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
+ * @hw: pointer to the HW structure
+ * @maj: driver version major number
+ * @min: driver version minor number
+ * @build: driver version build number
+ * @sub: driver version sub build number
+ *
+ * Sends driver version number to firmware through the manageability
+ * block. On success return IXGBE_SUCCESS
+ * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
+ * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
+ **/
+s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
+ u8 build, u8 sub)
+{
+ struct ixgbe_hic_drv_info fw_cmd;
+ int i;
+ s32 ret_val = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
+
+ if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
+ != IXGBE_SUCCESS) {
+ ret_val = IXGBE_ERR_SWFW_SYNC;
+ goto out;
+ }
+
+ fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
+ fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
+ fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
+ fw_cmd.port_num = (u8)hw->bus.func;
+ fw_cmd.ver_maj = maj;
+ fw_cmd.ver_min = min;
+ fw_cmd.ver_build = build;
+ fw_cmd.ver_sub = sub;
+ fw_cmd.hdr.checksum = 0;
+ fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
+ (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
+ fw_cmd.pad = 0;
+ fw_cmd.pad2 = 0;
+
+ for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
+ /* LINTED */
+ ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
+ sizeof(fw_cmd));
+ if (ret_val != IXGBE_SUCCESS)
+ continue;
+
+ if (fw_cmd.hdr.cmd_or_resp.ret_status ==
+ FW_CEM_RESP_STATUS_SUCCESS)
+ ret_val = IXGBE_SUCCESS;
+ else
+ ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
+
+ break;
+ }
+
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
+out:
+ return ret_val;
+}
+
+/**
+ * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
+ * @hw: pointer to hardware structure
+ * @num_pb: number of packet buffers to allocate
+ * @headroom: reserve n KB of headroom
+ * @strategy: packet buffer allocation strategy
+ **/
+void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
+ int strategy)
+{
+ u32 pbsize = hw->mac.rx_pb_size;
+ int i = 0;
+ u32 rxpktsize, txpktsize, txpbthresh;
+
+ /* Reserve headroom */
+ pbsize -= headroom;
+
+ if (!num_pb)
+ num_pb = 1;
+
+ /* Divide remaining packet buffer space amongst the number of packet
+ * buffers requested using supplied strategy.
+ */
+ switch (strategy) {
+ case PBA_STRATEGY_WEIGHTED:
+ /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
+ * buffer with 5/8 of the packet buffer space.
+ */
+ rxpktsize = (pbsize * 5) / (num_pb * 4);
+ pbsize -= rxpktsize * (num_pb / 2);
+ rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
+ for (; i < (num_pb / 2); i++)
+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
+ /* Fall through to configure remaining packet buffers */
+ /* FALLTHRU */
+ case PBA_STRATEGY_EQUAL:
+ rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
+ for (; i < num_pb; i++)
+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
+ break;
+ default:
+ break;
+ }
+
+ /* Only support an equally distributed Tx packet buffer strategy. */
+ txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
+ txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
+ for (i = 0; i < num_pb; i++) {
+ IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
+ IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
+ }
+
+ /* Clear unused TCs, if any, to zero buffer size*/
+ for (; i < IXGBE_MAX_PB; i++) {
+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
+ IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
+ IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
+ }
+}
+
+/**
+ * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
+ * @hw: pointer to the hardware structure
+ *
+ * The 82599 and x540 MACs can experience issues if TX work is still pending
+ * when a reset occurs. This function prevents this by flushing the PCIe
+ * buffers on the system.
+ **/
+void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
+{
+ u32 gcr_ext, hlreg0;
+
+ /*
+ * If double reset is not requested then all transactions should
+ * already be clear and as such there is no work to do
+ */
+ if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
+ return;
+
+ /*
+ * Set loopback enable to prevent any transmits from being sent
+ * should the link come up. This assumes that the RXCTRL.RXEN bit
+ * has already been cleared.
+ */
+ hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
+ IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
+
+ /* initiate cleaning flow for buffers in the PCIe transaction layer */
+ gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
+ IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
+ gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
+
+ /* Flush all writes and allow 20usec for all transactions to clear */
+ IXGBE_WRITE_FLUSH(hw);
+ usec_delay(20);
+
+ /* restore previous register values */
+ IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
+ IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
+}
+
--- a/usr/src/uts/common/io/ixgbe/ixgbe_common.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_common.h Sun Aug 12 11:56:48 2012 +0100
@@ -1,6 +1,6 @@
/******************************************************************************
- Copyright (c) 2001-2010, Intel Corporation
+ Copyright (c) 2001-2012, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,19 +30,24 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.h,v 1.12 2012/07/05 20:51:44 jfv Exp $*/
#ifndef _IXGBE_COMMON_H_
#define _IXGBE_COMMON_H_
#include "ixgbe_type.h"
+#ifdef lint
+/* Use "hw" somehow... */
+#define IXGBE_WRITE_REG64(hw, reg, value) hw = hw
+#else
#define IXGBE_WRITE_REG64(hw, reg, value) \
- { \
+ do { \
IXGBE_WRITE_REG(hw, reg, (u32) value); \
IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
- }
+ } while (0)
+#endif
-u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
+u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
@@ -51,8 +56,7 @@
s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
- u32 pba_num_size);
-s32 ixgbe_read_pba_length_generic(struct ixgbe_hw *hw, u32 *pba_num_size);
+ u32 pba_num_size);
s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
@@ -63,32 +67,41 @@
s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
+s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data);
s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
+s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data);
s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
+s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data);
s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
- u16 *data);
+ u16 *data);
+s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data);
u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
- u16 *checksum_val);
+ u16 *checksum_val);
s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
- u32 enable_addr);
+ u32 enable_addr);
s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
- u32 mc_addr_count,
- ixgbe_mc_addr_itr func);
+ u32 mc_addr_count,
+ ixgbe_mc_addr_itr func, bool clear);
s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
- u32 addr_count, ixgbe_mc_addr_itr func);
+ u32 addr_count, ixgbe_mc_addr_itr func);
s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
+s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw);
+s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw);
-s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
-s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packtetbuf_num);
-s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
+s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);
+void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
s32 ixgbe_validate_mac_addr(u8 *mac_addr);
s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
@@ -102,23 +115,32 @@
s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
+s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);
s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
- u32 vind, bool vlan_on);
+ u32 vind, bool vlan_on);
+s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
+ bool vlan_on, bool *vfta_changed);
s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
+s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan);
s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *link_up, bool link_up_wait_to_complete);
+ ixgbe_link_speed *speed,
+ bool *link_up, bool link_up_wait_to_complete);
s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
- u16 *wwpn_prefix);
+ u16 *wwpn_prefix);
s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs);
void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);
void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
+void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
+ int strategy);
void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw);
+s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
+ u8 build, u8 ver);
+void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
#endif /* IXGBE_COMMON */
--- a/usr/src/uts/common/io/ixgbe/ixgbe_gld.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_gld.c Sun Aug 12 11:56:48 2012 +0100
@@ -25,6 +25,7 @@
/*
* Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
#include "ixgbe_sw.h"
@@ -710,13 +711,15 @@
ixgbe->intr_throttling[0] = (uint32_t)result;
/*
- * 82599 requires the interupt throttling rate is
- * a multiple of 8. This is enforced by the register
- * definiton.
+ * 82599 and X540 require the interrupt throttling
+ * rate is a multiple of 8. This is enforced by the
+ * register definiton.
*/
- if (hw->mac.type == ixgbe_mac_82599EB)
+ if (hw->mac.type == ixgbe_mac_82599EB ||
+ hw->mac.type == ixgbe_mac_X540) {
ixgbe->intr_throttling[0] =
ixgbe->intr_throttling[0] & 0xFF8;
+ }
for (i = 0; i < MAX_INTR_VECTOR; i++)
ixgbe->intr_throttling[i] =
--- a/usr/src/uts/common/io/ixgbe/ixgbe_main.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_main.c Sun Aug 12 11:56:48 2012 +0100
@@ -25,6 +25,8 @@
/*
* Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, Joyent, Inc. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
#include "ixgbe_sw.h"
@@ -291,6 +293,36 @@
| IXGBE_FLAG_SFP_PLUG_CAPABLE) /* capability flags */
};
+static adapter_info_t ixgbe_X540_cap = {
+ 128, /* maximum number of rx queues */
+ 1, /* minimum number of rx queues */
+ 128, /* default number of rx queues */
+ 64, /* maximum number of rx groups */
+ 1, /* minimum number of rx groups */
+ 1, /* default number of rx groups */
+ 128, /* maximum number of tx queues */
+ 1, /* minimum number of tx queues */
+ 8, /* default number of tx queues */
+ 15500, /* maximum MTU size */
+ 0xFF8, /* maximum interrupt throttle rate */
+ 0, /* minimum interrupt throttle rate */
+ 200, /* default interrupt throttle rate */
+ 64, /* maximum total msix vectors */
+ 16, /* maximum number of ring vectors */
+ 2, /* maximum number of other vectors */
+ (IXGBE_EICR_LSC
+ | IXGBE_EICR_GPI_SDP1
+ | IXGBE_EICR_GPI_SDP2), /* "other" interrupt types handled */
+
+ (IXGBE_SDP1_GPIEN
+ | IXGBE_SDP2_GPIEN), /* "other" interrupt types enable mask */
+
+ (IXGBE_FLAG_DCA_CAPABLE
+ | IXGBE_FLAG_RSS_CAPABLE
+ | IXGBE_FLAG_VMDQ_CAPABLE
+ | IXGBE_FLAG_RSC_CAPABLE) /* capability flags */
+};
+
/*
* Module Initialization Functions.
*/
@@ -867,6 +899,15 @@
}
break;
+ case ixgbe_mac_X540:
+ IXGBE_DEBUGLOG_0(ixgbe, "identify X540 adapter\n");
+ ixgbe->capab = &ixgbe_X540_cap;
+ /*
+ * For now, X540 is all set in its capab structure.
+ * As other X540 variants show up, things can change here.
+ */
+ break;
+
default:
IXGBE_DEBUGLOG_1(ixgbe,
"adapter not supported in ixgbe_identify_hardware(): %d\n",
@@ -1200,8 +1241,8 @@
* Setup default flow control thresholds - enable/disable
* & flow control type is controlled by ixgbe.conf
*/
- hw->fc.high_water = DEFAULT_FCRTH;
- hw->fc.low_water = DEFAULT_FCRTL;
+ hw->fc.high_water[0] = DEFAULT_FCRTH;
+ hw->fc.low_water[0] = DEFAULT_FCRTL;
hw->fc.pause_time = DEFAULT_FCPAUSE;
hw->fc.send_xon = B_TRUE;
@@ -2090,13 +2131,14 @@
reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index));
reg_val |= IXGBE_RXDCTL_ENABLE; /* enable queue */
- /* Not a valid value for 82599 */
- if (hw->mac.type < ixgbe_mac_82599EB) {
+ /* Not a valid value for 82599 or X540 */
+ if (hw->mac.type == ixgbe_mac_82598EB) {
reg_val |= 0x0020; /* pthresh */
}
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index), reg_val);
- if (hw->mac.type == ixgbe_mac_82599EB) {
+ if (hw->mac.type == ixgbe_mac_82599EB ||
+ hw->mac.type == ixgbe_mac_X540) {
reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
reg_val |= (IXGBE_RDRXCTL_CRCSTRIP | IXGBE_RDRXCTL_AGGDIS);
IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg_val);
@@ -2333,11 +2375,18 @@
* Turn off relaxed ordering for head write back or it will
* cause problems with the tx recycling
*/
- reg_val = IXGBE_READ_REG(hw,
- IXGBE_DCA_TXCTRL(tx_ring->index));
- reg_val &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
- IXGBE_WRITE_REG(hw,
- IXGBE_DCA_TXCTRL(tx_ring->index), reg_val);
+
+ reg_val = (hw->mac.type == ixgbe_mac_82598EB) ?
+ IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(tx_ring->index)) :
+ IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(tx_ring->index));
+ reg_val &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
+ if (hw->mac.type == ixgbe_mac_82598EB) {
+ IXGBE_WRITE_REG(hw,
+ IXGBE_DCA_TXCTRL(tx_ring->index), reg_val);
+ } else {
+ IXGBE_WRITE_REG(hw,
+ IXGBE_DCA_TXCTRL_82599(tx_ring->index), reg_val);
+ }
} else {
tx_ring->tbd_head_wb = NULL;
}
@@ -2386,6 +2435,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
IXGBE_WRITE_REG(hw, IXGBE_TQSM(i >> 2),
ring_mapping);
break;
@@ -2404,6 +2454,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
IXGBE_WRITE_REG(hw, IXGBE_TQSM(i >> 2), ring_mapping);
break;
@@ -2420,13 +2471,22 @@
IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_val);
/*
- * enable DMA for 82599 parts
- */
- if (hw->mac.type == ixgbe_mac_82599EB) {
- /* DMATXCTL.TE must be set after all Tx config is complete */
+ * enable DMA for 82599 and X540 parts
+ */
+ if (hw->mac.type == ixgbe_mac_82599EB ||
+ hw->mac.type == ixgbe_mac_X540) {
+ /* DMATXCTL.TE must be set after all Tx config is complete */
reg_val = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
reg_val |= IXGBE_DMATXCTL_TE;
IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_val);
+
+ /* Disable arbiter to set MTQC */
+ reg_val = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
+ reg_val |= IXGBE_RTTDCS_ARBDIS;
+ IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg_val);
+ IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
+ reg_val &= ~IXGBE_RTTDCS_ARBDIS;
+ IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg_val);
}
/*
@@ -2526,6 +2586,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
/*
* Enable VMDq-only.
*/
@@ -2619,6 +2680,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
/*
* Enable RSS & Setup RSS Hash functions
*/
@@ -2664,7 +2726,8 @@
rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
- if (hw->mac.type == ixgbe_mac_82599EB) {
+ if (hw->mac.type == ixgbe_mac_82599EB ||
+ hw->mac.type == ixgbe_mac_X540) {
/*
* Enable Virtualization and Replication.
*/
@@ -2839,7 +2902,7 @@
* Update the multicast addresses to the MTA registers
*/
(void) ixgbe_update_mc_addr_list(hw, mc_addr_list, mc_addr_count,
- ixgbe_mc_table_itr);
+ ixgbe_mc_table_itr, TRUE);
}
/*
@@ -2875,6 +2938,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
/*
* 82599 supports the following combination:
* vmdq no. x rss no.
@@ -2883,6 +2947,8 @@
* 1 x [1..16]
* However 8 rss queue per pool (vmdq) is sufficient for
* most cases.
+ *
+ * For now, treat X540 like the 82599.
*/
ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
if (ixgbe->num_rx_groups == 1) {
@@ -3045,8 +3111,9 @@
ixgbe->relax_order_enable = ixgbe_get_prop(ixgbe,
PROP_RELAX_ORDER_ENABLE, 0, 1, DEFAULT_RELAX_ORDER_ENABLE);
- /* Head Write Back not recommended for 82599 */
- if (hw->mac.type >= ixgbe_mac_82599EB) {
+ /* Head Write Back not recommended for 82599 and X540 */
+ if (hw->mac.type == ixgbe_mac_82599EB ||
+ hw->mac.type == ixgbe_mac_X540) {
ixgbe->tx_head_wb_enable = B_FALSE;
}
@@ -3069,9 +3136,9 @@
}
/*
- * ixgbe LRO only been supported by 82599 now
- */
- if (hw->mac.type != ixgbe_mac_82599EB) {
+ * ixgbe LRO only been supported by 82599 and X540 now
+ */
+ if (hw->mac.type == ixgbe_mac_82598EB) {
ixgbe->lro_enable = B_FALSE;
}
ixgbe->tx_copy_thresh = ixgbe_get_prop(ixgbe, PROP_TX_COPY_THRESHOLD,
@@ -3099,11 +3166,11 @@
ixgbe->capab->max_intr_throttle,
ixgbe->capab->def_intr_throttle);
/*
- * 82599 requires the interupt throttling rate is
+ * 82599 and X540 require the interrupt throttling rate is
* a multiple of 8. This is enforced by the register
* definiton.
*/
- if (hw->mac.type == ixgbe_mac_82599EB)
+ if (hw->mac.type == ixgbe_mac_82599EB || hw->mac.type == ixgbe_mac_X540)
ixgbe->intr_throttling[0] = ixgbe->intr_throttling[0] & 0xFF8;
}
@@ -3229,7 +3296,7 @@
ixgbe->link_check_complete = B_TRUE;
/* Link is up, enable flow control settings */
- (void) ixgbe_fc_enable(hw, 0);
+ (void) ixgbe_fc_enable(hw);
/*
* The Link is up, check whether it was marked as down earlier
@@ -3732,10 +3799,10 @@
/*
* General purpose interrupt enable.
- * For 82599, extended interrupt automask enable
+ * For 82599 or X540, extended interrupt automask enable
* only in MSI or MSI-X mode
*/
- if ((hw->mac.type < ixgbe_mac_82599EB) ||
+ if ((hw->mac.type == ixgbe_mac_82598EB) ||
(ixgbe->intr_type == DDI_INTR_TYPE_MSI)) {
gpie |= IXGBE_GPIE_EIAME;
}
@@ -3748,6 +3815,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
gpie |= ixgbe->capab->other_gpie;
/* Enable RSC Delay 8us when LRO enabled */
@@ -3941,6 +4009,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_AUTOC);
reg |= (IXGBE_AUTOC_FLU |
IXGBE_AUTOC_10G_KX4);
@@ -4159,6 +4228,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
ixgbe->eimc = IXGBE_82599_OTHER_INTR;
IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
break;
@@ -4252,6 +4322,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
ixgbe->eimc = IXGBE_82599_OTHER_INTR;
IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
break;
@@ -4331,6 +4402,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
ixgbe->eims |= IXGBE_EICR_RTX_QUEUE;
ixgbe_intr_other_work(ixgbe, eicr);
break;
@@ -4731,6 +4803,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
if (cause == -1) {
/* other causes */
msix_vector |= IXGBE_IVAR_ALLOC_VAL;
@@ -4784,6 +4857,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
if (cause == -1) {
/* other causes */
index = (intr_alloc_entry & 1) * 8;
@@ -4833,6 +4907,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
if (cause == -1) {
/* other causes */
index = (intr_alloc_entry & 1) * 8;
@@ -4875,6 +4950,7 @@
return (sw_rx_index);
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
return (sw_rx_index * 2);
default:
@@ -4890,6 +4966,7 @@
return (hw_rx_index);
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
if (ixgbe->num_rx_groups > 32) {
hw_rx_index = (sw_rx_index /
rx_ring_per_group) * 2 +
@@ -4994,6 +5071,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
for (v_idx = 0; v_idx < 64; v_idx++)
IXGBE_WRITE_REG(hw, IXGBE_IVAR(v_idx), 0);
IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, 0);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_mbx.c Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,759 @@
+/******************************************************************************
+
+ Copyright (c) 2001-2012, Intel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+******************************************************************************/
+/*$FreeBSD$*/
+
+#include "ixgbe_type.h"
+#include "ixgbe_mbx.h"
+
+/**
+ * ixgbe_read_mbx - Reads a message from the mailbox
+ * @hw: pointer to the HW structure
+ * @msg: The message buffer
+ * @size: Length of buffer
+ * @mbx_id: id of mailbox to read
+ *
+ * returns SUCCESS if it successfuly read message from buffer
+ **/
+s32 ixgbe_read_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ DEBUGFUNC("ixgbe_read_mbx");
+
+ /* limit read to size of mailbox */
+ if (size > mbx->size)
+ size = mbx->size;
+
+ if (mbx->ops.read)
+ ret_val = mbx->ops.read(hw, msg, size, mbx_id);
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_write_mbx - Write a message to the mailbox
+ * @hw: pointer to the HW structure
+ * @msg: The message buffer
+ * @size: Length of buffer
+ * @mbx_id: id of mailbox to write
+ *
+ * returns SUCCESS if it successfully copied message into the buffer
+ **/
+s32 ixgbe_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ s32 ret_val = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_write_mbx");
+
+ if (size > mbx->size)
+ ret_val = IXGBE_ERR_MBX;
+
+ else if (mbx->ops.write)
+ ret_val = mbx->ops.write(hw, msg, size, mbx_id);
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_check_for_msg - checks to see if someone sent us mail
+ * @hw: pointer to the HW structure
+ * @mbx_id: id of mailbox to check
+ *
+ * returns SUCCESS if the Status bit was found or else ERR_MBX
+ **/
+s32 ixgbe_check_for_msg(struct ixgbe_hw *hw, u16 mbx_id)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ DEBUGFUNC("ixgbe_check_for_msg");
+
+ if (mbx->ops.check_for_msg)
+ ret_val = mbx->ops.check_for_msg(hw, mbx_id);
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_check_for_ack - checks to see if someone sent us ACK
+ * @hw: pointer to the HW structure
+ * @mbx_id: id of mailbox to check
+ *
+ * returns SUCCESS if the Status bit was found or else ERR_MBX
+ **/
+s32 ixgbe_check_for_ack(struct ixgbe_hw *hw, u16 mbx_id)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ DEBUGFUNC("ixgbe_check_for_ack");
+
+ if (mbx->ops.check_for_ack)
+ ret_val = mbx->ops.check_for_ack(hw, mbx_id);
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_check_for_rst - checks to see if other side has reset
+ * @hw: pointer to the HW structure
+ * @mbx_id: id of mailbox to check
+ *
+ * returns SUCCESS if the Status bit was found or else ERR_MBX
+ **/
+s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ DEBUGFUNC("ixgbe_check_for_rst");
+
+ if (mbx->ops.check_for_rst)
+ ret_val = mbx->ops.check_for_rst(hw, mbx_id);
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_poll_for_msg - Wait for message notification
+ * @hw: pointer to the HW structure
+ * @mbx_id: id of mailbox to write
+ *
+ * returns SUCCESS if it successfully received a message notification
+ **/
+static s32 ixgbe_poll_for_msg(struct ixgbe_hw *hw, u16 mbx_id)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ int countdown = mbx->timeout;
+
+ DEBUGFUNC("ixgbe_poll_for_msg");
+
+ if (!countdown || !mbx->ops.check_for_msg)
+ goto out;
+
+ while (countdown && mbx->ops.check_for_msg(hw, mbx_id)) {
+ countdown--;
+ if (!countdown)
+ break;
+ usec_delay(mbx->usec_delay);
+ }
+
+out:
+ return countdown ? IXGBE_SUCCESS : IXGBE_ERR_MBX;
+}
+
+/**
+ * ixgbe_poll_for_ack - Wait for message acknowledgement
+ * @hw: pointer to the HW structure
+ * @mbx_id: id of mailbox to write
+ *
+ * returns SUCCESS if it successfully received a message acknowledgement
+ **/
+static s32 ixgbe_poll_for_ack(struct ixgbe_hw *hw, u16 mbx_id)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ int countdown = mbx->timeout;
+
+ DEBUGFUNC("ixgbe_poll_for_ack");
+
+ if (!countdown || !mbx->ops.check_for_ack)
+ goto out;
+
+ while (countdown && mbx->ops.check_for_ack(hw, mbx_id)) {
+ countdown--;
+ if (!countdown)
+ break;
+ usec_delay(mbx->usec_delay);
+ }
+
+out:
+ return countdown ? IXGBE_SUCCESS : IXGBE_ERR_MBX;
+}
+
+/**
+ * ixgbe_read_posted_mbx - Wait for message notification and receive message
+ * @hw: pointer to the HW structure
+ * @msg: The message buffer
+ * @size: Length of buffer
+ * @mbx_id: id of mailbox to write
+ *
+ * returns SUCCESS if it successfully received a message notification and
+ * copied it into the receive buffer.
+ **/
+s32 ixgbe_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ DEBUGFUNC("ixgbe_read_posted_mbx");
+
+ if (!mbx->ops.read)
+ goto out;
+
+ ret_val = ixgbe_poll_for_msg(hw, mbx_id);
+
+ /* if ack received read message, otherwise we timed out */
+ if (!ret_val)
+ ret_val = mbx->ops.read(hw, msg, size, mbx_id);
+out:
+ return ret_val;
+}
+
+/**
+ * ixgbe_write_posted_mbx - Write a message to the mailbox, wait for ack
+ * @hw: pointer to the HW structure
+ * @msg: The message buffer
+ * @size: Length of buffer
+ * @mbx_id: id of mailbox to write
+ *
+ * returns SUCCESS if it successfully copied message into the buffer and
+ * received an ack to that message within delay * timeout period
+ **/
+s32 ixgbe_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size,
+ u16 mbx_id)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ DEBUGFUNC("ixgbe_write_posted_mbx");
+
+ /* exit if either we can't write or there isn't a defined timeout */
+ if (!mbx->ops.write || !mbx->timeout)
+ goto out;
+
+ /* send msg */
+ ret_val = mbx->ops.write(hw, msg, size, mbx_id);
+
+ /* if msg sent wait until we receive an ack */
+ if (!ret_val)
+ ret_val = ixgbe_poll_for_ack(hw, mbx_id);
+out:
+ return ret_val;
+}
+
+/**
+ * ixgbe_init_mbx_ops_generic - Initialize MB function pointers
+ * @hw: pointer to the HW structure
+ *
+ * Setups up the mailbox read and write message function pointers
+ **/
+void ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+
+ mbx->ops.read_posted = ixgbe_read_posted_mbx;
+ mbx->ops.write_posted = ixgbe_write_posted_mbx;
+}
+
+/**
+ * ixgbe_read_v2p_mailbox - read v2p mailbox
+ * @hw: pointer to the HW structure
+ *
+ * This function is used to read the v2p mailbox without losing the read to
+ * clear status bits.
+ **/
+static u32 ixgbe_read_v2p_mailbox(struct ixgbe_hw *hw)
+{
+ u32 v2p_mailbox = IXGBE_READ_REG(hw, IXGBE_VFMAILBOX);
+
+ v2p_mailbox |= hw->mbx.v2p_mailbox;
+ hw->mbx.v2p_mailbox |= v2p_mailbox & IXGBE_VFMAILBOX_R2C_BITS;
+
+ return v2p_mailbox;
+}
+
+/**
+ * ixgbe_check_for_bit_vf - Determine if a status bit was set
+ * @hw: pointer to the HW structure
+ * @mask: bitmask for bits to be tested and cleared
+ *
+ * This function is used to check for the read to clear bits within
+ * the V2P mailbox.
+ **/
+static s32 ixgbe_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask)
+{
+ u32 v2p_mailbox = ixgbe_read_v2p_mailbox(hw);
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ if (v2p_mailbox & mask)
+ ret_val = IXGBE_SUCCESS;
+
+ hw->mbx.v2p_mailbox &= ~mask;
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_check_for_msg_vf - checks to see if the PF has sent mail
+ * @hw: pointer to the HW structure
+ * @mbx_id: id of mailbox to check
+ *
+ * returns SUCCESS if the PF has set the Status bit or else ERR_MBX
+ **/
+static s32 ixgbe_check_for_msg_vf(struct ixgbe_hw *hw, u16 mbx_id)
+{
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ UNREFERENCED_1PARAMETER(mbx_id);
+ DEBUGFUNC("ixgbe_check_for_msg_vf");
+
+ if (!ixgbe_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFSTS)) {
+ ret_val = IXGBE_SUCCESS;
+ hw->mbx.stats.reqs++;
+ }
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_check_for_ack_vf - checks to see if the PF has ACK'd
+ * @hw: pointer to the HW structure
+ * @mbx_id: id of mailbox to check
+ *
+ * returns SUCCESS if the PF has set the ACK bit or else ERR_MBX
+ **/
+static s32 ixgbe_check_for_ack_vf(struct ixgbe_hw *hw, u16 mbx_id)
+{
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ UNREFERENCED_1PARAMETER(mbx_id);
+ DEBUGFUNC("ixgbe_check_for_ack_vf");
+
+ if (!ixgbe_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFACK)) {
+ ret_val = IXGBE_SUCCESS;
+ hw->mbx.stats.acks++;
+ }
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_check_for_rst_vf - checks to see if the PF has reset
+ * @hw: pointer to the HW structure
+ * @mbx_id: id of mailbox to check
+ *
+ * returns TRUE if the PF has set the reset done bit or else FALSE
+ **/
+static s32 ixgbe_check_for_rst_vf(struct ixgbe_hw *hw, u16 mbx_id)
+{
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ UNREFERENCED_1PARAMETER(mbx_id);
+ DEBUGFUNC("ixgbe_check_for_rst_vf");
+
+ if (!ixgbe_check_for_bit_vf(hw, (IXGBE_VFMAILBOX_RSTD |
+ IXGBE_VFMAILBOX_RSTI))) {
+ ret_val = IXGBE_SUCCESS;
+ hw->mbx.stats.rsts++;
+ }
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_obtain_mbx_lock_vf - obtain mailbox lock
+ * @hw: pointer to the HW structure
+ *
+ * return SUCCESS if we obtained the mailbox lock
+ **/
+static s32 ixgbe_obtain_mbx_lock_vf(struct ixgbe_hw *hw)
+{
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ DEBUGFUNC("ixgbe_obtain_mbx_lock_vf");
+
+ /* Take ownership of the buffer */
+ IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_VFU);
+
+ /* reserve mailbox for vf use */
+ if (ixgbe_read_v2p_mailbox(hw) & IXGBE_VFMAILBOX_VFU)
+ ret_val = IXGBE_SUCCESS;
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_write_mbx_vf - Write a message to the mailbox
+ * @hw: pointer to the HW structure
+ * @msg: The message buffer
+ * @size: Length of buffer
+ * @mbx_id: id of mailbox to write
+ *
+ * returns SUCCESS if it successfully copied message into the buffer
+ **/
+static s32 ixgbe_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,
+ u16 mbx_id)
+{
+ s32 ret_val;
+ u16 i;
+
+ UNREFERENCED_1PARAMETER(mbx_id);
+
+ DEBUGFUNC("ixgbe_write_mbx_vf");
+
+ /* lock the mailbox to prevent pf/vf race condition */
+ ret_val = ixgbe_obtain_mbx_lock_vf(hw);
+ if (ret_val)
+ goto out_no_write;
+
+ /* flush msg and acks as we are overwriting the message buffer */
+ ret_val = ixgbe_check_for_msg_vf(hw, 0);
+ if (ret_val)
+ goto out_no_write;
+ ret_val = ixgbe_check_for_ack_vf(hw, 0);
+ if (ret_val)
+ goto out_no_write;
+
+ /* copy the caller specified message to the mailbox memory buffer */
+ for (i = 0; i < size; i++)
+ IXGBE_WRITE_REG_ARRAY(hw, IXGBE_VFMBMEM, i, msg[i]);
+
+ /* update stats */
+ hw->mbx.stats.msgs_tx++;
+
+ /* Drop VFU and interrupt the PF to tell it a message has been sent */
+ IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_REQ);
+
+out_no_write:
+ return ret_val;
+}
+
+/**
+ * ixgbe_read_mbx_vf - Reads a message from the inbox intended for vf
+ * @hw: pointer to the HW structure
+ * @msg: The message buffer
+ * @size: Length of buffer
+ * @mbx_id: id of mailbox to read
+ *
+ * returns SUCCESS if it successfuly read message from buffer
+ **/
+static s32 ixgbe_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,
+ u16 mbx_id)
+{
+ s32 ret_val = IXGBE_SUCCESS;
+ u16 i;
+
+ DEBUGFUNC("ixgbe_read_mbx_vf");
+ UNREFERENCED_1PARAMETER(mbx_id);
+
+ /* lock the mailbox to prevent pf/vf race condition */
+ ret_val = ixgbe_obtain_mbx_lock_vf(hw);
+ if (ret_val)
+ goto out_no_read;
+
+ /* copy the message from the mailbox memory buffer */
+ for (i = 0; i < size; i++)
+ msg[i] = IXGBE_READ_REG_ARRAY(hw, IXGBE_VFMBMEM, i);
+
+ /* Acknowledge receipt and release mailbox, then we're done */
+ IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_ACK);
+
+ /* update stats */
+ hw->mbx.stats.msgs_rx++;
+
+out_no_read:
+ return ret_val;
+}
+
+/**
+ * ixgbe_init_mbx_params_vf - set initial values for vf mailbox
+ * @hw: pointer to the HW structure
+ *
+ * Initializes the hw->mbx struct to correct values for vf mailbox
+ */
+void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+
+ /* start mailbox as timed out and let the reset_hw call set the timeout
+ * value to begin communications */
+ mbx->timeout = 0;
+ mbx->usec_delay = IXGBE_VF_MBX_INIT_DELAY;
+
+ mbx->size = IXGBE_VFMAILBOX_SIZE;
+
+ mbx->ops.read = ixgbe_read_mbx_vf;
+ mbx->ops.write = ixgbe_write_mbx_vf;
+ mbx->ops.read_posted = ixgbe_read_posted_mbx;
+ mbx->ops.write_posted = ixgbe_write_posted_mbx;
+ mbx->ops.check_for_msg = ixgbe_check_for_msg_vf;
+ mbx->ops.check_for_ack = ixgbe_check_for_ack_vf;
+ mbx->ops.check_for_rst = ixgbe_check_for_rst_vf;
+
+ mbx->stats.msgs_tx = 0;
+ mbx->stats.msgs_rx = 0;
+ mbx->stats.reqs = 0;
+ mbx->stats.acks = 0;
+ mbx->stats.rsts = 0;
+}
+
+static s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index)
+{
+ u32 mbvficr = IXGBE_READ_REG(hw, IXGBE_MBVFICR(index));
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ if (mbvficr & mask) {
+ ret_val = IXGBE_SUCCESS;
+ IXGBE_WRITE_REG(hw, IXGBE_MBVFICR(index), mask);
+ }
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_check_for_msg_pf - checks to see if the VF has sent mail
+ * @hw: pointer to the HW structure
+ * @vf_number: the VF index
+ *
+ * returns SUCCESS if the VF has set the Status bit or else ERR_MBX
+ **/
+static s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number)
+{
+ s32 ret_val = IXGBE_ERR_MBX;
+ s32 index = IXGBE_MBVFICR_INDEX(vf_number);
+ u32 vf_bit = vf_number % 16;
+
+ DEBUGFUNC("ixgbe_check_for_msg_pf");
+
+ if (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFREQ_VF1 << vf_bit,
+ index)) {
+ ret_val = IXGBE_SUCCESS;
+ hw->mbx.stats.reqs++;
+ }
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_check_for_ack_pf - checks to see if the VF has ACKed
+ * @hw: pointer to the HW structure
+ * @vf_number: the VF index
+ *
+ * returns SUCCESS if the VF has set the Status bit or else ERR_MBX
+ **/
+static s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number)
+{
+ s32 ret_val = IXGBE_ERR_MBX;
+ s32 index = IXGBE_MBVFICR_INDEX(vf_number);
+ u32 vf_bit = vf_number % 16;
+
+ DEBUGFUNC("ixgbe_check_for_ack_pf");
+
+ if (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFACK_VF1 << vf_bit,
+ index)) {
+ ret_val = IXGBE_SUCCESS;
+ hw->mbx.stats.acks++;
+ }
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_check_for_rst_pf - checks to see if the VF has reset
+ * @hw: pointer to the HW structure
+ * @vf_number: the VF index
+ *
+ * returns SUCCESS if the VF has set the Status bit or else ERR_MBX
+ **/
+static s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)
+{
+ u32 reg_offset = (vf_number < 32) ? 0 : 1;
+ u32 vf_shift = vf_number % 32;
+ u32 vflre = 0;
+ s32 ret_val = IXGBE_ERR_MBX;
+
+ DEBUGFUNC("ixgbe_check_for_rst_pf");
+
+ switch (hw->mac.type) {
+ case ixgbe_mac_82599EB:
+ vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));
+ break;
+ case ixgbe_mac_X540:
+ vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));
+ break;
+ default:
+ break;
+ }
+
+ if (vflre & (1 << vf_shift)) {
+ ret_val = IXGBE_SUCCESS;
+ IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift));
+ hw->mbx.stats.rsts++;
+ }
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_obtain_mbx_lock_pf - obtain mailbox lock
+ * @hw: pointer to the HW structure
+ * @vf_number: the VF index
+ *
+ * return SUCCESS if we obtained the mailbox lock
+ **/
+static s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, u16 vf_number)
+{
+ s32 ret_val = IXGBE_ERR_MBX;
+ u32 p2v_mailbox;
+
+ DEBUGFUNC("ixgbe_obtain_mbx_lock_pf");
+
+ /* Take ownership of the buffer */
+ IXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_number), IXGBE_PFMAILBOX_PFU);
+
+ /* reserve mailbox for vf use */
+ p2v_mailbox = IXGBE_READ_REG(hw, IXGBE_PFMAILBOX(vf_number));
+ if (p2v_mailbox & IXGBE_PFMAILBOX_PFU)
+ ret_val = IXGBE_SUCCESS;
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_write_mbx_pf - Places a message in the mailbox
+ * @hw: pointer to the HW structure
+ * @msg: The message buffer
+ * @size: Length of buffer
+ * @vf_number: the VF index
+ *
+ * returns SUCCESS if it successfully copied message into the buffer
+ **/
+static s32 ixgbe_write_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,
+ u16 vf_number)
+{
+ s32 ret_val;
+ u16 i;
+
+ DEBUGFUNC("ixgbe_write_mbx_pf");
+
+ /* lock the mailbox to prevent pf/vf race condition */
+ ret_val = ixgbe_obtain_mbx_lock_pf(hw, vf_number);
+ if (ret_val)
+ goto out_no_write;
+
+ /* flush msg and acks as we are overwriting the message buffer */
+ ret_val = ixgbe_check_for_msg_vf(hw, 0);
+ if (ret_val)
+ goto out_no_write;
+ ret_val = ixgbe_check_for_ack_vf(hw, 0);
+ if (ret_val)
+ goto out_no_write;
+
+ /* copy the caller specified message to the mailbox memory buffer */
+ for (i = 0; i < size; i++)
+ IXGBE_WRITE_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_number), i, msg[i]);
+
+ /* Interrupt VF to tell it a message has been sent and release buffer*/
+ IXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_number), IXGBE_PFMAILBOX_STS);
+
+ /* update stats */
+ hw->mbx.stats.msgs_tx++;
+
+out_no_write:
+ return ret_val;
+
+}
+
+/**
+ * ixgbe_read_mbx_pf - Read a message from the mailbox
+ * @hw: pointer to the HW structure
+ * @msg: The message buffer
+ * @size: Length of buffer
+ * @vf_number: the VF index
+ *
+ * This function copies a message from the mailbox buffer to the caller's
+ * memory buffer. The presumption is that the caller knows that there was
+ * a message due to a VF request so no polling for message is needed.
+ **/
+static s32 ixgbe_read_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,
+ u16 vf_number)
+{
+ s32 ret_val;
+ u16 i;
+
+ DEBUGFUNC("ixgbe_read_mbx_pf");
+
+ /* lock the mailbox to prevent pf/vf race condition */
+ ret_val = ixgbe_obtain_mbx_lock_pf(hw, vf_number);
+ if (ret_val)
+ goto out_no_read;
+
+ /* copy the message to the mailbox memory buffer */
+ for (i = 0; i < size; i++)
+ msg[i] = IXGBE_READ_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_number), i);
+
+ /* Acknowledge the message and release buffer */
+ IXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_number), IXGBE_PFMAILBOX_ACK);
+
+ /* update stats */
+ hw->mbx.stats.msgs_rx++;
+
+out_no_read:
+ return ret_val;
+}
+
+/**
+ * ixgbe_init_mbx_params_pf - set initial values for pf mailbox
+ * @hw: pointer to the HW structure
+ *
+ * Initializes the hw->mbx struct to correct values for pf mailbox
+ */
+void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+
+ if (hw->mac.type != ixgbe_mac_82599EB &&
+ hw->mac.type != ixgbe_mac_X540)
+ return;
+
+ mbx->timeout = 0;
+ mbx->usec_delay = 0;
+
+ mbx->size = IXGBE_VFMAILBOX_SIZE;
+
+ mbx->ops.read = ixgbe_read_mbx_pf;
+ mbx->ops.write = ixgbe_write_mbx_pf;
+ mbx->ops.read_posted = ixgbe_read_posted_mbx;
+ mbx->ops.write_posted = ixgbe_write_posted_mbx;
+ mbx->ops.check_for_msg = ixgbe_check_for_msg_pf;
+ mbx->ops.check_for_ack = ixgbe_check_for_ack_pf;
+ mbx->ops.check_for_rst = ixgbe_check_for_rst_pf;
+
+ mbx->stats.msgs_tx = 0;
+ mbx->stats.msgs_rx = 0;
+ mbx->stats.reqs = 0;
+ mbx->stats.acks = 0;
+ mbx->stats.rsts = 0;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_mbx.h Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,112 @@
+/******************************************************************************
+
+ Copyright (c) 2001-2012, Intel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+******************************************************************************/
+/*$FreeBSD$*/
+
+#ifndef _IXGBE_MBX_H_
+#define _IXGBE_MBX_H_
+
+#include "ixgbe_type.h"
+
+#define IXGBE_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */
+#define IXGBE_ERR_MBX -100
+
+#define IXGBE_VFMAILBOX 0x002FC
+#define IXGBE_VFMBMEM 0x00200
+
+/* Define mailbox register bits */
+#define IXGBE_VFMAILBOX_REQ 0x00000001 /* Request for PF Ready bit */
+#define IXGBE_VFMAILBOX_ACK 0x00000002 /* Ack PF message received */
+#define IXGBE_VFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
+#define IXGBE_VFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
+#define IXGBE_VFMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */
+#define IXGBE_VFMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */
+#define IXGBE_VFMAILBOX_RSTI 0x00000040 /* PF has reset indication */
+#define IXGBE_VFMAILBOX_RSTD 0x00000080 /* PF has indicated reset done */
+#define IXGBE_VFMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */
+
+#define IXGBE_PFMAILBOX_STS 0x00000001 /* Initiate message send to VF */
+#define IXGBE_PFMAILBOX_ACK 0x00000002 /* Ack message recv'd from VF */
+#define IXGBE_PFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
+#define IXGBE_PFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
+#define IXGBE_PFMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */
+
+#define IXGBE_MBVFICR_VFREQ_MASK 0x0000FFFF /* bits for VF messages */
+#define IXGBE_MBVFICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */
+#define IXGBE_MBVFICR_VFACK_MASK 0xFFFF0000 /* bits for VF acks */
+#define IXGBE_MBVFICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */
+
+
+/* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the
+ * PF. The reverse is TRUE if it is IXGBE_PF_*.
+ * Message ACK's are the value or'd with 0xF0000000
+ */
+#define IXGBE_VT_MSGTYPE_ACK 0x80000000 /* Messages below or'd with
+ * this are the ACK */
+#define IXGBE_VT_MSGTYPE_NACK 0x40000000 /* Messages below or'd with
+ * this are the NACK */
+#define IXGBE_VT_MSGTYPE_CTS 0x20000000 /* Indicates that VF is still
+ * clear to send requests */
+#define IXGBE_VT_MSGINFO_SHIFT 16
+/* bits 23:16 are used for extra info for certain messages */
+#define IXGBE_VT_MSGINFO_MASK (0xFF << IXGBE_VT_MSGINFO_SHIFT)
+
+#define IXGBE_VF_RESET 0x01 /* VF requests reset */
+#define IXGBE_VF_SET_MAC_ADDR 0x02 /* VF requests PF to set MAC addr */
+#define IXGBE_VF_SET_MULTICAST 0x03 /* VF requests PF to set MC addr */
+#define IXGBE_VF_SET_VLAN 0x04 /* VF requests PF to set VLAN */
+#define IXGBE_VF_SET_LPE 0x05 /* VF requests PF to set VMOLR.LPE */
+#define IXGBE_VF_SET_MACVLAN 0x06 /* VF requests PF for unicast filter */
+
+/* length of permanent address message returned from PF */
+#define IXGBE_VF_PERMADDR_MSG_LEN 4
+/* word in permanent address message with the current multicast type */
+#define IXGBE_VF_MC_TYPE_WORD 3
+
+#define IXGBE_PF_CONTROL_MSG 0x0100 /* PF control message */
+
+
+#define IXGBE_VF_MBX_INIT_TIMEOUT 2000 /* number of retries on mailbox */
+#define IXGBE_VF_MBX_INIT_DELAY 500 /* microseconds between retries */
+
+s32 ixgbe_read_mbx(struct ixgbe_hw *, u32 *, u16, u16);
+s32 ixgbe_write_mbx(struct ixgbe_hw *, u32 *, u16, u16);
+s32 ixgbe_read_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);
+s32 ixgbe_write_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);
+s32 ixgbe_check_for_msg(struct ixgbe_hw *, u16);
+s32 ixgbe_check_for_ack(struct ixgbe_hw *, u16);
+s32 ixgbe_check_for_rst(struct ixgbe_hw *, u16);
+void ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw);
+void ixgbe_init_mbx_params_vf(struct ixgbe_hw *);
+void ixgbe_init_mbx_params_pf(struct ixgbe_hw *);
+
+#endif /* _IXGBE_MBX_H_ */
--- a/usr/src/uts/common/io/ixgbe/ixgbe_osdep.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_osdep.h Sun Aug 12 11:56:48 2012 +0100
@@ -26,6 +26,9 @@
/*
* Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
*/
+/*
+ * Copyright (c) 2012, Joyent, Inc. All rights reserved.
+ */
#ifndef _IXGBE_OSDEP_H
#define _IXGBE_OSDEP_H
@@ -54,6 +57,9 @@
#include <sys/note.h>
#include "ixgbe_debug.h"
+/* Cheesy hack for EWARN() */
+#define EWARN(H, W, S) cmn_err(CE_NOTE, W)
+
/* function declarations */
struct ixgbe_hw;
uint16_t ixgbe_read_pci_cfg(struct ixgbe_hw *, uint32_t);
@@ -100,7 +106,21 @@
#define IXGBE_NTOHL ntohl
#define IXGBE_NTOHS ntohs
-#define UNREFERENCED_PARAMETER(x) _NOTE(ARGUNUSED(x))
+#ifdef _BIG_ENDIAN
+#define IXGBE_CPU_TO_LE32 BSWAP_32
+#define IXGBE_LE32_TO_CPUS BSWAP_32
+#else
+#define IXGBE_CPU_TO_LE32(x) (x)
+#define IXGBE_LE32_TO_CPUS(x) (x)
+#endif /* _BIG_ENDIAN */
+
+#define UNREFERENCED_PARAMETER(x) _NOTE(ARGUNUSED(x))
+#define UNREFERENCED_1PARAMETER(_p) UNREFERENCED_PARAMETER(_p)
+#define UNREFERENCED_2PARAMETER(_p, _q) _NOTE(ARGUNUSED(_p, _q))
+#define UNREFERENCED_3PARAMETER(_p, _q, _r) _NOTE(ARGUNUSED(_p, _q, _r))
+#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) _NOTE(ARGUNUSED(_p, _q,_r, _s))
+
+
typedef int8_t s8;
typedef int16_t s16;
--- a/usr/src/uts/common/io/ixgbe/ixgbe_phy.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_phy.c Sun Aug 12 11:56:48 2012 +0100
@@ -1,6 +1,6 @@
/******************************************************************************
- Copyright (c) 2001-2010, Intel Corporation
+ Copyright (c) 2001-2012, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +30,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
#include "ixgbe_api.h"
#include "ixgbe_common.h"
@@ -43,11 +43,10 @@
static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
-static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
+static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
static bool ixgbe_get_i2c_data(u32 *i2cctl);
-void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
/**
* ixgbe_init_phy_ops_generic - Inits PHY function ptrs
@@ -75,7 +74,7 @@
phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
- phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic;
+ phy->ops.identify_sfp = &ixgbe_identify_module_generic;
phy->sfp_type = ixgbe_sfp_type_unknown;
phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
return IXGBE_SUCCESS;
@@ -101,21 +100,21 @@
hw->phy.addr = phy_addr;
(void) ixgbe_get_phy_id(hw);
hw->phy.type =
- ixgbe_get_phy_type_from_id(hw->phy.id);
+ ixgbe_get_phy_type_from_id(hw->phy.id);
if (hw->phy.type == ixgbe_phy_unknown) {
hw->phy.ops.read_reg(hw,
IXGBE_MDIO_PHY_EXT_ABILITY,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- &ext_ability);
+ IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+ &ext_ability);
if (ext_ability &
(IXGBE_MDIO_PHY_10GBASET_ABILITY |
IXGBE_MDIO_PHY_1000BASET_ABILITY))
hw->phy.type =
- ixgbe_phy_cu_unknown;
+ ixgbe_phy_cu_unknown;
else
hw->phy.type =
- ixgbe_phy_generic;
+ ixgbe_phy_generic;
}
status = IXGBE_SUCCESS;
@@ -146,7 +145,7 @@
hw->phy.addr = phy_addr;
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
+ IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
if (phy_id != 0xFFFF && phy_id != 0x0)
valid = TRUE;
@@ -168,14 +167,14 @@
DEBUGFUNC("ixgbe_get_phy_id");
status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- &phy_id_high);
+ IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+ &phy_id_high);
if (status == IXGBE_SUCCESS) {
hw->phy.id = (u32)(phy_id_high << 16);
status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- &phy_id_low);
+ IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+ &phy_id_low);
hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
}
@@ -197,7 +196,7 @@
case TN1010_PHY_ID:
phy_type = ixgbe_phy_tn;
break;
- case AQ1002_PHY_ID:
+ case X540_PHY_ID:
phy_type = ixgbe_phy_aq;
break;
case QT2022_PHY_ID:
@@ -243,8 +242,8 @@
* This will cause a soft reset to the PHY
*/
hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
- IXGBE_MDIO_PHY_XS_DEV_TYPE,
- IXGBE_MDIO_PHY_XS_RESET);
+ IXGBE_MDIO_PHY_XS_DEV_TYPE,
+ IXGBE_MDIO_PHY_XS_RESET);
/*
* Poll for reset bit to self-clear indicating reset is complete.
@@ -254,7 +253,7 @@
for (i = 0; i < 30; i++) {
msec_delay(100);
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
- IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
+ IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
usec_delay(2);
break;
@@ -277,7 +276,7 @@
* @phy_data: Pointer to read data from PHY register
**/
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
- u32 device_type, u16 *phy_data)
+ u32 device_type, u16 *phy_data)
{
u32 command;
u32 i;
@@ -292,15 +291,15 @@
else
gssr = IXGBE_GSSR_PHY0_SM;
- if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
+ if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
status = IXGBE_ERR_SWFW_SYNC;
if (status == IXGBE_SUCCESS) {
/* Setup and write the address cycle command */
command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
- (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
+ (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+ (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+ (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
@@ -329,9 +328,9 @@
* command
*/
command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
- (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
+ (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+ (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+ (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
@@ -363,7 +362,7 @@
}
}
- ixgbe_release_swfw_sync(hw, gssr);
+ hw->mac.ops.release_swfw_sync(hw, gssr);
}
return status;
@@ -377,7 +376,7 @@
* @phy_data: Data to write to the PHY register
**/
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
- u32 device_type, u16 phy_data)
+ u32 device_type, u16 phy_data)
{
u32 command;
u32 i;
@@ -391,7 +390,7 @@
else
gssr = IXGBE_GSSR_PHY0_SM;
- if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
+ if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
status = IXGBE_ERR_SWFW_SYNC;
if (status == IXGBE_SUCCESS) {
@@ -400,9 +399,9 @@
/* Setup and write the address cycle command */
command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
- (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
+ (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+ (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+ (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
@@ -431,9 +430,9 @@
* command
*/
command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
- (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
+ (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+ (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+ (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
@@ -457,7 +456,7 @@
}
}
- ixgbe_release_swfw_sync(hw, gssr);
+ hw->mac.ops.release_swfw_sync(hw, gssr);
}
return status;
@@ -471,7 +470,7 @@
**/
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
{
- s32 status = IXGBE_SUCCESS;
+ s32 status;
u32 time_out;
u32 max_time_out = 10;
u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
@@ -480,76 +479,79 @@
DEBUGFUNC("ixgbe_setup_phy_link_generic");
- (void) ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
+ status =
+ ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
+ if (status != IXGBE_SUCCESS)
+ return status;
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
/* Set or unset auto-negotiation 10G advertisement */
hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ &autoneg_reg);
autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ autoneg_reg);
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
/* Set or unset auto-negotiation 1G advertisement */
hw->phy.ops.read_reg(hw,
- IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
+ IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ &autoneg_reg);
autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
hw->phy.ops.write_reg(hw,
- IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
+ IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ autoneg_reg);
}
if (speed & IXGBE_LINK_SPEED_100_FULL) {
/* Set or unset auto-negotiation 100M advertisement */
hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ &autoneg_reg);
- autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
+ autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
+ IXGBE_MII_100BASE_T_ADVERTISE_HALF);
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ autoneg_reg);
}
/* Restart PHY autonegotiation and wait for completion */
hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
autoneg_reg |= IXGBE_MII_RESTART;
hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
/* Wait for autonegotiation to finish */
for (time_out = 0; time_out < max_time_out; time_out++) {
usec_delay(10);
/* Restart PHY autonegotiation and wait for completion */
status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ &autoneg_reg);
autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
- if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
+ if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
break;
- }
}
if (time_out == max_time_out) {
@@ -567,12 +569,11 @@
* @autoneg: TRUE if autonegotiation enabled
**/
s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete)
+ ixgbe_link_speed speed,
+ bool autoneg,
+ bool autoneg_wait_to_complete)
{
- UNREFERENCED_PARAMETER(autoneg);
- UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
+ UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete);
DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
@@ -606,8 +607,8 @@
* Determines the link capabilities by reading the AUTOC register.
**/
s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *autoneg)
+ ixgbe_link_speed *speed,
+ bool *autoneg)
{
s32 status = IXGBE_ERR_LINK_SETUP;
u16 speed_ability;
@@ -618,8 +619,8 @@
*autoneg = TRUE;
status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- &speed_ability);
+ IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+ &speed_ability);
if (status == IXGBE_SUCCESS) {
if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
@@ -641,7 +642,7 @@
* the PHY.
**/
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *link_up)
+ bool *link_up)
{
s32 status = IXGBE_SUCCESS;
u32 time_out;
@@ -664,13 +665,12 @@
for (time_out = 0; time_out < max_time_out; time_out++) {
usec_delay(10);
status = hw->phy.ops.read_reg(hw,
- IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
- IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
- &phy_data);
- phy_link = phy_data &
- IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
+ IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
+ IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
+ &phy_data);
+ phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
phy_speed = phy_data &
- IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
+ IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
*link_up = TRUE;
if (phy_speed ==
@@ -691,7 +691,7 @@
**/
s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
{
- s32 status = IXGBE_SUCCESS;
+ s32 status;
u32 time_out;
u32 max_time_out = 10;
u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
@@ -700,74 +700,76 @@
DEBUGFUNC("ixgbe_setup_phy_link_tnx");
- (void) ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
+ status =
+ ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
+ if (status != IXGBE_SUCCESS)
+ return status;
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
/* Set or unset auto-negotiation 10G advertisement */
hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ &autoneg_reg);
autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ autoneg_reg);
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
/* Set or unset auto-negotiation 1G advertisement */
hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ &autoneg_reg);
autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ autoneg_reg);
}
if (speed & IXGBE_LINK_SPEED_100_FULL) {
/* Set or unset auto-negotiation 100M advertisement */
hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ &autoneg_reg);
autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ autoneg_reg);
}
/* Restart PHY autonegotiation and wait for completion */
hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
autoneg_reg |= IXGBE_MII_RESTART;
hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
/* Wait for autonegotiation to finish */
for (time_out = 0; time_out < max_time_out; time_out++) {
usec_delay(10);
/* Restart PHY autonegotiation and wait for completion */
status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+ &autoneg_reg);
autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
- if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
+ if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
break;
- }
}
if (time_out == max_time_out) {
@@ -784,15 +786,15 @@
* @firmware_version: pointer to the PHY Firmware Version
**/
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
- u16 *firmware_version)
+ u16 *firmware_version)
{
s32 status = IXGBE_SUCCESS;
DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
- IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
- firmware_version);
+ IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
+ firmware_version);
return status;
}
@@ -803,15 +805,15 @@
* @firmware_version: pointer to the PHY Firmware Version
**/
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
- u16 *firmware_version)
+ u16 *firmware_version)
{
s32 status = IXGBE_SUCCESS;
DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
- IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
- firmware_version);
+ IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
+ firmware_version);
return status;
}
@@ -832,16 +834,16 @@
DEBUGFUNC("ixgbe_reset_phy_nl");
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
- IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
+ IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
/* reset the PHY and poll for completion */
hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
- IXGBE_MDIO_PHY_XS_DEV_TYPE,
- (phy_data | IXGBE_MDIO_PHY_XS_RESET));
+ IXGBE_MDIO_PHY_XS_DEV_TYPE,
+ (phy_data | IXGBE_MDIO_PHY_XS_RESET));
for (i = 0; i < 100; i++) {
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
- IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
+ IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
break;
msec_delay(10);
@@ -855,7 +857,7 @@
/* Get init offsets */
ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
- &data_offset);
+ &data_offset);
if (ret_val != IXGBE_SUCCESS)
goto out;
@@ -867,7 +869,7 @@
*/
ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
control = (eword & IXGBE_CONTROL_MASK_NL) >>
- IXGBE_CONTROL_SHIFT_NL;
+ IXGBE_CONTROL_SHIFT_NL;
edata = eword & IXGBE_DATA_MASK_NL;
switch (control) {
case IXGBE_DELAY_NL:
@@ -876,23 +878,23 @@
msec_delay(edata);
break;
case IXGBE_DATA_NL:
- DEBUGOUT("DATA: \n");
+ DEBUGOUT("DATA:\n");
data_offset++;
hw->eeprom.ops.read(hw, data_offset++,
- &phy_offset);
+ &phy_offset);
for (i = 0; i < edata; i++) {
hw->eeprom.ops.read(hw, data_offset, &eword);
hw->phy.ops.write_reg(hw, phy_offset,
- IXGBE_TWINAX_DEV, eword);
+ IXGBE_TWINAX_DEV, eword);
DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
- phy_offset);
+ phy_offset);
data_offset++;
phy_offset++;
}
break;
case IXGBE_CONTROL_NL:
data_offset++;
- DEBUGOUT("CONTROL: \n");
+ DEBUGOUT("CONTROL:\n");
if (edata == IXGBE_CONTROL_EOL_NL) {
DEBUGOUT("EOL\n");
end_data = TRUE;
@@ -916,6 +918,33 @@
}
/**
+ * ixgbe_identify_module_generic - Identifies module type
+ * @hw: pointer to hardware structure
+ *
+ * Determines HW type and calls appropriate function.
+ **/
+s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
+{
+ s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
+
+ DEBUGFUNC("ixgbe_identify_module_generic");
+
+ switch (hw->mac.ops.get_media_type(hw)) {
+ case ixgbe_media_type_fiber:
+ status = ixgbe_identify_sfp_module_generic(hw);
+ break;
+
+
+ default:
+ hw->phy.sfp_type = ixgbe_sfp_type_not_present;
+ status = IXGBE_ERR_SFP_NOT_PRESENT;
+ break;
+ }
+
+ return status;
+}
+
+/**
* ixgbe_identify_sfp_module_generic - Identifies SFP modules
* @hw: pointer to hardware structure
*
@@ -943,8 +972,8 @@
}
status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_IDENTIFIER,
- &identifier);
+ IXGBE_SFF_IDENTIFIER,
+ &identifier);
if (status == IXGBE_ERR_SWFW_SYNC ||
status == IXGBE_ERR_I2C ||
@@ -959,8 +988,8 @@
status = IXGBE_ERR_SFP_NOT_SUPPORTED;
} else {
status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_1GBE_COMP_CODES,
- &comp_codes_1g);
+ IXGBE_SFF_1GBE_COMP_CODES,
+ &comp_codes_1g);
if (status == IXGBE_ERR_SWFW_SYNC ||
status == IXGBE_ERR_I2C ||
@@ -968,16 +997,16 @@
goto err_read_i2c_eeprom;
status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_10GBE_COMP_CODES,
- &comp_codes_10g);
+ IXGBE_SFF_10GBE_COMP_CODES,
+ &comp_codes_10g);
if (status == IXGBE_ERR_SWFW_SYNC ||
status == IXGBE_ERR_I2C ||
status == IXGBE_ERR_SFP_NOT_PRESENT)
goto err_read_i2c_eeprom;
status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_CABLE_TECHNOLOGY,
- &cable_tech);
+ IXGBE_SFF_CABLE_TECHNOLOGY,
+ &cable_tech);
if (status == IXGBE_ERR_SWFW_SYNC ||
status == IXGBE_ERR_I2C ||
@@ -997,6 +1026,8 @@
* 8 SFP_act_lmt_DA_CORE1 - 82599-specific
* 9 SFP_1g_cu_CORE0 - 82599-specific
* 10 SFP_1g_cu_CORE1 - 82599-specific
+ * 11 SFP_1g_sx_CORE0 - 82599-specific
+ * 12 SFP_1g_sx_CORE1 - 82599-specific
*/
if (hw->mac.type == ixgbe_mac_82598EB) {
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
@@ -1011,10 +1042,10 @@
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
if (hw->bus.lan_id == 0)
hw->phy.sfp_type =
- ixgbe_sfp_type_da_cu_core0;
+ ixgbe_sfp_type_da_cu_core0;
else
hw->phy.sfp_type =
- ixgbe_sfp_type_da_cu_core1;
+ ixgbe_sfp_type_da_cu_core1;
} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
hw->phy.ops.read_i2c_eeprom(
hw, IXGBE_SFF_CABLE_SPEC_COMP,
@@ -1029,17 +1060,17 @@
ixgbe_sfp_type_da_act_lmt_core1;
} else {
hw->phy.sfp_type =
- ixgbe_sfp_type_unknown;
+ ixgbe_sfp_type_unknown;
}
} else if (comp_codes_10g &
(IXGBE_SFF_10GBASESR_CAPABLE |
IXGBE_SFF_10GBASELR_CAPABLE)) {
if (hw->bus.lan_id == 0)
hw->phy.sfp_type =
- ixgbe_sfp_type_srlr_core0;
+ ixgbe_sfp_type_srlr_core0;
else
hw->phy.sfp_type =
- ixgbe_sfp_type_srlr_core1;
+ ixgbe_sfp_type_srlr_core1;
} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
if (hw->bus.lan_id == 0)
hw->phy.sfp_type =
@@ -1047,6 +1078,13 @@
else
hw->phy.sfp_type =
ixgbe_sfp_type_1g_cu_core1;
+ } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_1g_sx_core0;
+ else
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_1g_sx_core1;
} else {
hw->phy.sfp_type = ixgbe_sfp_type_unknown;
}
@@ -1067,8 +1105,8 @@
if (hw->phy.type != ixgbe_phy_nl) {
hw->phy.id = identifier;
status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_VENDOR_OUI_BYTE0,
- &oui_bytes[0]);
+ IXGBE_SFF_VENDOR_OUI_BYTE0,
+ &oui_bytes[0]);
if (status == IXGBE_ERR_SWFW_SYNC ||
status == IXGBE_ERR_I2C ||
@@ -1076,8 +1114,8 @@
goto err_read_i2c_eeprom;
status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_VENDOR_OUI_BYTE1,
- &oui_bytes[1]);
+ IXGBE_SFF_VENDOR_OUI_BYTE1,
+ &oui_bytes[1]);
if (status == IXGBE_ERR_SWFW_SYNC ||
status == IXGBE_ERR_I2C ||
@@ -1085,8 +1123,8 @@
goto err_read_i2c_eeprom;
status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_VENDOR_OUI_BYTE2,
- &oui_bytes[2]);
+ IXGBE_SFF_VENDOR_OUI_BYTE2,
+ &oui_bytes[2]);
if (status == IXGBE_ERR_SWFW_SYNC ||
status == IXGBE_ERR_I2C ||
@@ -1102,7 +1140,7 @@
case IXGBE_SFF_VENDOR_OUI_TYCO:
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
hw->phy.type =
- ixgbe_phy_sfp_passive_tyco;
+ ixgbe_phy_sfp_passive_tyco;
break;
case IXGBE_SFF_VENDOR_OUI_FTL:
if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
@@ -1119,7 +1157,7 @@
default:
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
hw->phy.type =
- ixgbe_phy_sfp_passive_unknown;
+ ixgbe_phy_sfp_passive_unknown;
else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
hw->phy.type =
ixgbe_phy_sfp_active_unknown;
@@ -1139,7 +1177,9 @@
/* Verify supported 1G SFP modules */
if (comp_codes_10g == 0 &&
!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
hw->phy.type = ixgbe_phy_sfp_unsupported;
status = IXGBE_ERR_SFP_NOT_SUPPORTED;
goto out;
@@ -1154,14 +1194,31 @@
(void) ixgbe_get_device_caps(hw, &enforce_sfp);
if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
!((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
- (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
+ (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
+ (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
+ (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
/* Make sure we're a supported PHY type */
if (hw->phy.type == ixgbe_phy_sfp_intel) {
status = IXGBE_SUCCESS;
} else {
- DEBUGOUT("SFP+ module not supported\n");
- hw->phy.type = ixgbe_phy_sfp_unsupported;
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
+ if (hw->allow_unsupported_sfp == TRUE) {
+ EWARN(hw, "WARNING: Intel (R) Network "
+ "Connections are quality tested "
+ "using Intel (R) Ethernet Optics."
+ " Using untested modules is not "
+ "supported and may cause unstable"
+ " operation or damage to the "
+ "module or the adapter. Intel "
+ "Corporation is not responsible "
+ "for any harm caused by using "
+ "untested modules.\n", status);
+ status = IXGBE_SUCCESS;
+ } else {
+ DEBUGOUT("SFP+ module not supported\n");
+ hw->phy.type =
+ ixgbe_phy_sfp_unsupported;
+ status = IXGBE_ERR_SFP_NOT_SUPPORTED;
+ }
}
} else {
status = IXGBE_SUCCESS;
@@ -1180,6 +1237,8 @@
return IXGBE_ERR_SFP_NOT_PRESENT;
}
+
+
/**
* ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
* @hw: pointer to hardware structure
@@ -1190,8 +1249,8 @@
* so it returns the offsets to the phy init sequence block.
**/
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
- u16 *list_offset,
- u16 *data_offset)
+ u16 *list_offset,
+ u16 *data_offset)
{
u16 sfp_id;
u16 sfp_type = hw->phy.sfp_type;
@@ -1213,10 +1272,12 @@
* SR modules
*/
if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
- sfp_type == ixgbe_sfp_type_1g_cu_core0)
+ sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
+ sfp_type == ixgbe_sfp_type_1g_sx_core0)
sfp_type = ixgbe_sfp_type_srlr_core0;
else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
- sfp_type == ixgbe_sfp_type_1g_cu_core1)
+ sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
+ sfp_type == ixgbe_sfp_type_1g_sx_core1)
sfp_type = ixgbe_sfp_type_srlr_core1;
/* Read offset to PHY init contents */
@@ -1268,13 +1329,13 @@
* Performs byte read operation to SFP module's EEPROM over I2C interface.
**/
s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 *eeprom_data)
+ u8 *eeprom_data)
{
DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
return hw->phy.ops.read_i2c_byte(hw, byte_offset,
- IXGBE_I2C_EEPROM_DEV_ADDR,
- eeprom_data);
+ IXGBE_I2C_EEPROM_DEV_ADDR,
+ eeprom_data);
}
/**
@@ -1286,13 +1347,13 @@
* Performs byte write operation to SFP module's EEPROM over I2C interface.
**/
s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 eeprom_data)
+ u8 eeprom_data)
{
DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
return hw->phy.ops.write_i2c_byte(hw, byte_offset,
- IXGBE_I2C_EEPROM_DEV_ADDR,
- eeprom_data);
+ IXGBE_I2C_EEPROM_DEV_ADDR,
+ eeprom_data);
}
/**
@@ -1302,16 +1363,17 @@
* @data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface at
- * a specified deivce address.
+ * a specified device address.
**/
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 *data)
+ u8 dev_addr, u8 *data)
{
s32 status = IXGBE_SUCCESS;
u32 max_retry = 10;
u32 retry = 0;
u16 swfw_mask = 0;
bool nack = 1;
+ *data = 0;
DEBUGFUNC("ixgbe_read_i2c_byte_generic");
@@ -1321,7 +1383,8 @@
swfw_mask = IXGBE_GSSR_PHY0_SM;
do {
- if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
+ if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
+ != IXGBE_SUCCESS) {
status = IXGBE_ERR_SWFW_SYNC;
goto read_byte_out;
}
@@ -1368,7 +1431,7 @@
break;
fail:
- ixgbe_release_swfw_sync(hw, swfw_mask);
+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
msec_delay(100);
ixgbe_i2c_bus_clear(hw);
retry++;
@@ -1379,7 +1442,7 @@
} while (retry < max_retry);
- ixgbe_release_swfw_sync(hw, swfw_mask);
+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
read_byte_out:
return status;
@@ -1395,7 +1458,7 @@
* a specified device address.
**/
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 data)
+ u8 dev_addr, u8 data)
{
s32 status = IXGBE_SUCCESS;
u32 max_retry = 1;
@@ -1409,7 +1472,7 @@
else
swfw_mask = IXGBE_GSSR_PHY0_SM;
- if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
+ if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
status = IXGBE_ERR_SWFW_SYNC;
goto write_byte_out;
}
@@ -1453,7 +1516,7 @@
DEBUGOUT("I2C byte write error.\n");
} while (retry < max_retry);
- ixgbe_release_swfw_sync(hw, swfw_mask);
+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
write_byte_out:
return status;
@@ -1473,7 +1536,7 @@
/* Start condition must begin with data and clock high */
(void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
- (void) ixgbe_raise_i2c_clk(hw, &i2cctl);
+ ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Setup time for start condition (4.7us) */
usec_delay(IXGBE_I2C_T_SU_STA);
@@ -1504,7 +1567,7 @@
/* Stop condition must begin with data low and clock high */
(void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
- (void) ixgbe_raise_i2c_clk(hw, &i2cctl);
+ ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Setup time for stop condition (4us) */
usec_delay(IXGBE_I2C_T_SU_STO);
@@ -1524,18 +1587,16 @@
**/
static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
{
- s32 status = IXGBE_SUCCESS;
- s32 i;
+ s32 i, status = IXGBE_SUCCESS;
bool bit = 0;
DEBUGFUNC("ixgbe_clock_in_i2c_byte");
for (i = 7; i >= 0; i--) {
status = ixgbe_clock_in_i2c_bit(hw, &bit);
- *data |= bit << i;
-
if (status != IXGBE_SUCCESS)
break;
+ *data |= bit << i;
}
return status;
@@ -1569,6 +1630,7 @@
i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
i2cctl |= IXGBE_I2C_DATA_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
return status;
}
@@ -1581,7 +1643,7 @@
**/
static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
{
- s32 status;
+ s32 status = IXGBE_SUCCESS;
u32 i = 0;
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
u32 timeout = 10;
@@ -1589,10 +1651,8 @@
DEBUGFUNC("ixgbe_get_i2c_ack");
- status = ixgbe_raise_i2c_clk(hw, &i2cctl);
+ ixgbe_raise_i2c_clk(hw, &i2cctl);
- if (status != IXGBE_SUCCESS)
- goto out;
/* Minimum high period of clock is 4us */
usec_delay(IXGBE_I2C_T_HIGH);
@@ -1618,7 +1678,6 @@
/* Minimum low period of clock is 4.7 us */
usec_delay(IXGBE_I2C_T_LOW);
-out:
return status;
}
@@ -1631,12 +1690,11 @@
**/
static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
{
- s32 status;
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
DEBUGFUNC("ixgbe_clock_in_i2c_bit");
- status = ixgbe_raise_i2c_clk(hw, &i2cctl);
+ ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Minimum high period of clock is 4us */
usec_delay(IXGBE_I2C_T_HIGH);
@@ -1649,7 +1707,7 @@
/* Minimum low period of clock is 4.7 us */
usec_delay(IXGBE_I2C_T_LOW);
- return status;
+ return IXGBE_SUCCESS;
}
/**
@@ -1668,7 +1726,7 @@
status = ixgbe_set_i2c_data(hw, &i2cctl, data);
if (status == IXGBE_SUCCESS) {
- status = ixgbe_raise_i2c_clk(hw, &i2cctl);
+ ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Minimum high period of clock is 4us */
usec_delay(IXGBE_I2C_T_HIGH);
@@ -1693,20 +1751,26 @@
*
* Raises the I2C clock line '0'->'1'
**/
-static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
+static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
{
- s32 status = IXGBE_SUCCESS;
+ u32 i = 0;
+ u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
+ u32 i2cctl_r = 0;
DEBUGFUNC("ixgbe_raise_i2c_clk");
- *i2cctl |= IXGBE_I2C_CLK_OUT;
-
- IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+ for (i = 0; i < timeout; i++) {
+ *i2cctl |= IXGBE_I2C_CLK_OUT;
- /* SCL rise time (1000ns) */
- usec_delay(IXGBE_I2C_T_RISE);
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
+ /* SCL rise time (1000ns) */
+ usec_delay(IXGBE_I2C_T_RISE);
- return status;
+ i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+ if (i2cctl_r & IXGBE_I2C_CLK_IN)
+ break;
+ }
}
/**
@@ -1724,6 +1788,7 @@
*i2cctl &= ~IXGBE_I2C_CLK_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
/* SCL fall time (300ns) */
usec_delay(IXGBE_I2C_T_FALL);
@@ -1749,6 +1814,7 @@
*i2cctl &= ~IXGBE_I2C_DATA_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
@@ -1803,7 +1869,7 @@
(void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
for (i = 0; i < 9; i++) {
- (void) ixgbe_raise_i2c_clk(hw, &i2cctl);
+ ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Min high period of clock is 4us */
usec_delay(IXGBE_I2C_T_HIGH);
@@ -1821,7 +1887,7 @@
}
/**
- * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
+ * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
* @hw: pointer to hardware structure
*
* Checks if the LASI temp alarm status was triggered due to overtemp
--- a/usr/src/uts/common/io/ixgbe/ixgbe_phy.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_phy.h Sun Aug 12 11:56:48 2012 +0100
@@ -1,6 +1,6 @@
/******************************************************************************
- Copyright (c) 2001-2010, Intel Corporation
+ Copyright (c) 2001-2012, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -39,61 +39,61 @@
#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
/* EEPROM byte offsets */
-#define IXGBE_SFF_IDENTIFIER 0x0
-#define IXGBE_SFF_IDENTIFIER_SFP 0x3
-#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
-#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
-#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
-#define IXGBE_SFF_1GBE_COMP_CODES 0x6
-#define IXGBE_SFF_10GBE_COMP_CODES 0x3
-#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
-#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
+#define IXGBE_SFF_IDENTIFIER 0x0
+#define IXGBE_SFF_IDENTIFIER_SFP 0x3
+#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
+#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
+#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
+#define IXGBE_SFF_1GBE_COMP_CODES 0x6
+#define IXGBE_SFF_10GBE_COMP_CODES 0x3
+#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
+#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
/* Bitmasks */
-#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
-#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
-#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
-#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
-#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
-#define IXGBE_SFF_1GBASET_CAPABLE 0x8
-#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
-#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
-#define IXGBE_I2C_EEPROM_READ_MASK 0x100
-#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
-#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
-#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
-#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
-#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
+#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
+#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
+#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
+#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
+#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
+#define IXGBE_SFF_1GBASET_CAPABLE 0x8
+#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
+#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
+#define IXGBE_I2C_EEPROM_READ_MASK 0x100
+#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
+#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
+#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
+#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
+#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
/* Flow control defines */
-#define IXGBE_TAF_SYM_PAUSE 0x400
-#define IXGBE_TAF_ASM_PAUSE 0x800
+#define IXGBE_TAF_SYM_PAUSE 0x400
+#define IXGBE_TAF_ASM_PAUSE 0x800
/* Bit-shift macros */
-#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
-#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
-#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
+#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
+#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
+#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
-#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
-#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
-#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
-#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
+#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
+#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
+#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
+#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
/* I2C SDA and SCL timing parameters for standard mode */
-#define IXGBE_I2C_T_HD_STA 4
-#define IXGBE_I2C_T_LOW 5
-#define IXGBE_I2C_T_HIGH 4
-#define IXGBE_I2C_T_SU_STA 5
-#define IXGBE_I2C_T_HD_DATA 5
-#define IXGBE_I2C_T_SU_DATA 1
-#define IXGBE_I2C_T_RISE 1
-#define IXGBE_I2C_T_FALL 1
-#define IXGBE_I2C_T_SU_STO 4
-#define IXGBE_I2C_T_BUF 5
+#define IXGBE_I2C_T_HD_STA 4
+#define IXGBE_I2C_T_LOW 5
+#define IXGBE_I2C_T_HIGH 4
+#define IXGBE_I2C_T_SU_STA 5
+#define IXGBE_I2C_T_HD_DATA 5
+#define IXGBE_I2C_T_SU_DATA 1
+#define IXGBE_I2C_T_RISE 1
+#define IXGBE_I2C_T_FALL 1
+#define IXGBE_I2C_T_SU_STO 4
+#define IXGBE_I2C_T_BUF 5
-#define IXGBE_TN_LASI_STATUS_REG 0x9005
-#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
+#define IXGBE_TN_LASI_STATUS_REG 0x9005
+#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
@@ -102,40 +102,42 @@
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
- u32 device_type, u16 *phy_data);
+ u32 device_type, u16 *phy_data);
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
- u32 device_type, u16 phy_data);
+ u32 device_type, u16 phy_data);
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
+ ixgbe_link_speed speed,
+ bool autoneg,
+ bool autoneg_wait_to_complete);
s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *autoneg);
+ ixgbe_link_speed *speed,
+ bool *autoneg);
/* PHY specific */
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *link_up);
+ ixgbe_link_speed *speed,
+ bool *link_up);
s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
- u16 *firmware_version);
+ u16 *firmware_version);
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
- u16 *firmware_version);
+ u16 *firmware_version);
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
+s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
- u16 *list_offset,
- u16 *data_offset);
+ u16 *list_offset,
+ u16 *data_offset);
s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 *data);
+ u8 dev_addr, u8 *data);
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 data);
+ u8 dev_addr, u8 data);
s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 *eeprom_data);
+ u8 *eeprom_data);
s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 eeprom_data);
+ u8 eeprom_data);
+void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
#endif /* _IXGBE_PHY_H_ */
--- a/usr/src/uts/common/io/ixgbe/ixgbe_stat.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_stat.c Sun Aug 12 11:56:48 2012 +0100
@@ -25,6 +25,7 @@
/*
* Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
#include "ixgbe_sw.h"
@@ -112,6 +113,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
ixgbe_ks->qbtc[i].value.ui64 +=
IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
ixgbe_ks->qbtc[i].value.ui64 +=
@@ -165,6 +167,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
IXGBE_LXONRXCNT);
break;
@@ -180,6 +183,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
IXGBE_LXOFFRXCNT);
break;
@@ -556,6 +560,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
ixgbe_ks->qbtc[i].value.ui64 +=
IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
ixgbe_ks->qbtc[i].value.ui64 +=
--- a/usr/src/uts/common/io/ixgbe/ixgbe_tx.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_tx.c Sun Aug 12 11:56:48 2012 +0100
@@ -25,6 +25,7 @@
/*
* Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
#include "ixgbe_sw.h"
@@ -1078,8 +1079,8 @@
* The Insert Ethernet CRC (IFCS) bit and the checksum fields are only
* valid in the first descriptor of the packet.
* Setting paylen in every first_tbd for all parts.
- * 82599 requires the packet length in paylen field with or without
- * LSO and 82598 will ignore it in non-LSO mode.
+ * 82599 and X540 require the packet length in paylen field with or
+ * without LSO and 82598 will ignore it in non-LSO mode.
*/
ASSERT(first_tbd != NULL);
first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS;
@@ -1095,6 +1096,7 @@
break;
case ixgbe_mac_82599EB:
+ case ixgbe_mac_X540:
if (ctx != NULL && ctx->lso_flag) {
first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
first_tbd->read.olinfo_status |=
--- a/usr/src/uts/common/io/ixgbe/ixgbe_type.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_type.h Sun Aug 12 11:56:48 2012 +0100
@@ -30,6 +30,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_type.h,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
#ifndef _IXGBE_TYPE_H_
#define _IXGBE_TYPE_H_
@@ -38,1982 +39,2200 @@
/* Vendor ID */
-#define IXGBE_INTEL_VENDOR_ID 0x8086
+#define IXGBE_INTEL_VENDOR_ID 0x8086
/* Device IDs */
-#define IXGBE_DEV_ID_82598 0x10B6
-#define IXGBE_DEV_ID_82598_BX 0x1508
-#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
-#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
-#define IXGBE_DEV_ID_82598AT 0x10C8
-#define IXGBE_DEV_ID_82598AT2 0x150B
-#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
-#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
-#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
-#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
-#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
-#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
-#define IXGBE_DEV_ID_82599_KX4 0x10F7
-#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
-#define IXGBE_DEV_ID_82599_KR 0x1517
-#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
-#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
+#define IXGBE_DEV_ID_82598 0x10B6
+#define IXGBE_DEV_ID_82598_BX 0x1508
+#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
+#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
+#define IXGBE_DEV_ID_82598AT 0x10C8
+#define IXGBE_DEV_ID_82598AT2 0x150B
+#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
+#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
+#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
+#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
+#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
+#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
+#define IXGBE_DEV_ID_82599_KX4 0x10F7
+#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
+#define IXGBE_DEV_ID_82599_KR 0x1517
+#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
+#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
#define IXGBE_DEV_ID_82599_CX4 0x10F9
#define IXGBE_DEV_ID_82599_SFP 0x10FB
-#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
-#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
-#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
+#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
+#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
+#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
+#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
-#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
+#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
#define IXGBE_DEV_ID_82599EN_SFP 0x1557
-#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
-#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
-#define IXGBE_DEV_ID_82599_VF 0x10ED
+#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
+#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
+#define IXGBE_DEV_ID_82599_VF 0x10ED
+#define IXGBE_DEV_ID_X540_VF 0x1515
+#define IXGBE_DEV_ID_X540T 0x1528
+#define IXGBE_DEV_ID_X540T1 0x1560
/* General Registers */
-#define IXGBE_CTRL 0x00000
-#define IXGBE_STATUS 0x00008
-#define IXGBE_CTRL_EXT 0x00018
-#define IXGBE_ESDP 0x00020
-#define IXGBE_EODSDP 0x00028
-#define IXGBE_I2CCTL 0x00028
-#define IXGBE_LEDCTL 0x00200
-#define IXGBE_FRTIMER 0x00048
-#define IXGBE_TCPTIMER 0x0004C
-#define IXGBE_CORESPARE 0x00600
-#define IXGBE_EXVET 0x05078
+#define IXGBE_CTRL 0x00000
+#define IXGBE_STATUS 0x00008
+#define IXGBE_CTRL_EXT 0x00018
+#define IXGBE_ESDP 0x00020
+#define IXGBE_EODSDP 0x00028
+#define IXGBE_I2CCTL 0x00028
+#define IXGBE_PHY_GPIO 0x00028
+#define IXGBE_MAC_GPIO 0x00030
+#define IXGBE_PHYINT_STATUS0 0x00100
+#define IXGBE_PHYINT_STATUS1 0x00104
+#define IXGBE_PHYINT_STATUS2 0x00108
+#define IXGBE_LEDCTL 0x00200
+#define IXGBE_FRTIMER 0x00048
+#define IXGBE_TCPTIMER 0x0004C
+#define IXGBE_CORESPARE 0x00600
+#define IXGBE_EXVET 0x05078
/* NVM Registers */
-#define IXGBE_EEC 0x10010
-#define IXGBE_EERD 0x10014
-#define IXGBE_EEWR 0x10018
-#define IXGBE_FLA 0x1001C
-#define IXGBE_EEMNGCTL 0x10110
-#define IXGBE_EEMNGDATA 0x10114
-#define IXGBE_FLMNGCTL 0x10118
-#define IXGBE_FLMNGDATA 0x1011C
-#define IXGBE_FLMNGCNT 0x10120
-#define IXGBE_FLOP 0x1013C
-#define IXGBE_GRC 0x10200
+#define IXGBE_EEC 0x10010
+#define IXGBE_EERD 0x10014
+#define IXGBE_EEWR 0x10018
+#define IXGBE_FLA 0x1001C
+#define IXGBE_EEMNGCTL 0x10110
+#define IXGBE_EEMNGDATA 0x10114
+#define IXGBE_FLMNGCTL 0x10118
+#define IXGBE_FLMNGDATA 0x1011C
+#define IXGBE_FLMNGCNT 0x10120
+#define IXGBE_FLOP 0x1013C
+#define IXGBE_GRC 0x10200
+#define IXGBE_SRAMREL 0x10210
+#define IXGBE_PHYDBG 0x10218
/* General Receive Control */
-#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
-#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
+#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
+#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
-#define IXGBE_VPDDIAG0 0x10204
-#define IXGBE_VPDDIAG1 0x10208
+#define IXGBE_VPDDIAG0 0x10204
+#define IXGBE_VPDDIAG1 0x10208
/* I2CCTL Bit Masks */
-#define IXGBE_I2C_CLK_IN 0x00000001
-#define IXGBE_I2C_CLK_OUT 0x00000002
-#define IXGBE_I2C_DATA_IN 0x00000004
-#define IXGBE_I2C_DATA_OUT 0x00000008
+#define IXGBE_I2C_CLK_IN 0x00000001
+#define IXGBE_I2C_CLK_OUT 0x00000002
+#define IXGBE_I2C_DATA_IN 0x00000004
+#define IXGBE_I2C_DATA_OUT 0x00000008
+#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
+
/* Interrupt Registers */
-#define IXGBE_EICR 0x00800
-#define IXGBE_EICS 0x00808
-#define IXGBE_EIMS 0x00880
-#define IXGBE_EIMC 0x00888
-#define IXGBE_EIAC 0x00810
-#define IXGBE_EIAM 0x00890
-#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
-#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
-#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
-#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
+#define IXGBE_EICR 0x00800
+#define IXGBE_EICS 0x00808
+#define IXGBE_EIMS 0x00880
+#define IXGBE_EIMC 0x00888
+#define IXGBE_EIAC 0x00810
+#define IXGBE_EIAM 0x00890
+#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
+#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
+#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
+#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
/* 82599 EITR is only 12 bits, with the lower 3 always zero */
/*
* 82598 EITR is 16 bits but set the limits based on the max
* supported by all ixgbe hardware
*/
-#define IXGBE_MAX_INT_RATE 488281
-#define IXGBE_MIN_INT_RATE 956
-#define IXGBE_MAX_EITR 0x00000FF8
-#define IXGBE_MIN_EITR 8
-#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
- (0x012300 + (((_i) - 24) * 4)))
-#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
-#define IXGBE_EITR_LLI_MOD 0x00008000
-#define IXGBE_EITR_CNT_WDIS 0x80000000
-#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
-#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
-#define IXGBE_EITRSEL 0x00894
-#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
-#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
-#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
-#define IXGBE_GPIE 0x00898
+#define IXGBE_MAX_INT_RATE 488281
+#define IXGBE_MIN_INT_RATE 956
+#define IXGBE_MAX_EITR 0x00000FF8
+#define IXGBE_MIN_EITR 8
+#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
+ (0x012300 + (((_i) - 24) * 4)))
+#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
+#define IXGBE_EITR_LLI_MOD 0x00008000
+#define IXGBE_EITR_CNT_WDIS 0x80000000
+#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
+#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
+#define IXGBE_EITRSEL 0x00894
+#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
+#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
+#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
+#define IXGBE_GPIE 0x00898
/* Flow Control Registers */
-#define IXGBE_FCADBUL 0x03210
-#define IXGBE_FCADBUH 0x03214
-#define IXGBE_FCAMACL 0x04328
-#define IXGBE_FCAMACH 0x0432C
-#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_PFCTOP 0x03008
-#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
-#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
-#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
-#define IXGBE_FCRTV 0x032A0
-#define IXGBE_FCCFG 0x03D00
-#define IXGBE_TFCS 0x0CE00
+#define IXGBE_FCADBUL 0x03210
+#define IXGBE_FCADBUH 0x03214
+#define IXGBE_FCAMACL 0x04328
+#define IXGBE_FCAMACH 0x0432C
+#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_PFCTOP 0x03008
+#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
+#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
+#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
+#define IXGBE_FCRTV 0x032A0
+#define IXGBE_FCCFG 0x03D00
+#define IXGBE_TFCS 0x0CE00
/* Receive DMA Registers */
-#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
- (0x0D000 + ((_i - 64) * 0x40)))
-#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
- (0x0D004 + ((_i - 64) * 0x40)))
-#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
- (0x0D008 + ((_i - 64) * 0x40)))
-#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
- (0x0D010 + ((_i - 64) * 0x40)))
-#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
- (0x0D018 + ((_i - 64) * 0x40)))
-#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
- (0x0D028 + ((_i - 64) * 0x40)))
-#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
- (0x0D02C + ((_i - 64) * 0x40)))
-#define IXGBE_RSCDBU 0x03028
-#define IXGBE_RDDCC 0x02F20
-#define IXGBE_RXMEMWRAP 0x03190
-#define IXGBE_STARCTRL 0x03024
+#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
+ (0x0D000 + (((_i) - 64) * 0x40)))
+#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
+ (0x0D004 + (((_i) - 64) * 0x40)))
+#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
+ (0x0D008 + (((_i) - 64) * 0x40)))
+#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
+ (0x0D010 + (((_i) - 64) * 0x40)))
+#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
+ (0x0D018 + (((_i) - 64) * 0x40)))
+#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
+ (0x0D028 + (((_i) - 64) * 0x40)))
+#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
+ (0x0D02C + (((_i) - 64) * 0x40)))
+#define IXGBE_RSCDBU 0x03028
+#define IXGBE_RDDCC 0x02F20
+#define IXGBE_RXMEMWRAP 0x03190
+#define IXGBE_STARCTRL 0x03024
/*
* Split and Replication Receive Control Registers
* 00-15 : 0x02100 + n*4
* 16-64 : 0x01014 + n*0x40
* 64-127: 0x0D014 + (n-64)*0x40
*/
-#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
- (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
- (0x0D014 + ((_i - 64) * 0x40))))
+#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
+ (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
+ (0x0D014 + (((_i) - 64) * 0x40))))
/*
* Rx DCA Control Register:
* 00-15 : 0x02200 + n*4
* 16-64 : 0x0100C + n*0x40
* 64-127: 0x0D00C + (n-64)*0x40
*/
-#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
- (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
- (0x0D00C + ((_i - 64) * 0x40))))
-#define IXGBE_RDRXCTL 0x02F00
-#define IXGBE_RDRXCTL_RSC_PUSH 0x80
-#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
- /* 8 of these 0x03C00 - 0x03C1C */
-#define IXGBE_RXCTRL 0x03000
-#define IXGBE_DROPEN 0x03D04
-#define IXGBE_RXPBSIZE_SHIFT 10
+#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
+ (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
+ (0x0D00C + (((_i) - 64) * 0x40))))
+#define IXGBE_RDRXCTL 0x02F00
+#define IXGBE_RDRXCTL_RSC_PUSH 0x80
+/* 8 of these 0x03C00 - 0x03C1C */
+#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
+#define IXGBE_RXCTRL 0x03000
+#define IXGBE_DROPEN 0x03D04
+#define IXGBE_RXPBSIZE_SHIFT 10
/* Receive Registers */
-#define IXGBE_RXCSUM 0x05000
-#define IXGBE_RFCTL 0x05008
-#define IXGBE_DRECCCTL 0x02F08
-#define IXGBE_DRECCCTL_DISABLE 0
+#define IXGBE_RXCSUM 0x05000
+#define IXGBE_RFCTL 0x05008
+#define IXGBE_DRECCCTL 0x02F08
+#define IXGBE_DRECCCTL_DISABLE 0
+#define IXGBE_DRECCCTL2 0x02F8C
/* Multicast Table Array - 128 entries */
-#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
-#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
- (0x0A200 + ((_i) * 8)))
-#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
- (0x0A204 + ((_i) * 8)))
-#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
-#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
+#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
+#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
+ (0x0A200 + ((_i) * 8)))
+#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
+ (0x0A204 + ((_i) * 8)))
+#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
+#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
/* Packet split receive type */
-#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
- (0x0EA00 + ((_i) * 4)))
+#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
+ (0x0EA00 + ((_i) * 4)))
/* array of 4096 1-bit vlan filters */
-#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
+#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
/*array of 4096 4-bit vlan vmdq indices */
-#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
-#define IXGBE_FCTRL 0x05080
-#define IXGBE_VLNCTRL 0x05088
-#define IXGBE_MCSTCTRL 0x05090
-#define IXGBE_MRQC 0x05818
-#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
-#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
-#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
-#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
-#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
-#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
-#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
-#define IXGBE_RQTC 0x0EC70
-#define IXGBE_MTQC 0x08120
-#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
-#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
-#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
-#define IXGBE_VT_CTL 0x051B0
-#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
-#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
-#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
-#define IXGBE_QDE 0x2F04
-#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
-#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
-#define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
-#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
-#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
-#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
-#define IXGBE_LLITHRESH 0x0EC90
-#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_IMIRVP 0x05AC0
-#define IXGBE_VMD_CTL 0x0581C
-#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
-#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
+#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
+#define IXGBE_FCTRL 0x05080
+#define IXGBE_VLNCTRL 0x05088
+#define IXGBE_MCSTCTRL 0x05090
+#define IXGBE_MRQC 0x05818
+#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
+#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
+#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
+#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
+#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
+#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
+#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
+#define IXGBE_RQTC 0x0EC70
+#define IXGBE_MTQC 0x08120
+#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
+#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
+#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
+#define IXGBE_VT_CTL 0x051B0
+#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */
+/* 64 Mailboxes, 16 DW each */
+#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i)))
+#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */
+#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */
+#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
+#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
+#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
+#define IXGBE_QDE 0x2F04
+#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */
+#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
+#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
+#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
+#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
+#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
+#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
+#define IXGBE_RXFECCERR0 0x051B8
+#define IXGBE_LLITHRESH 0x0EC90
+#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_IMIRVP 0x05AC0
+#define IXGBE_VMD_CTL 0x0581C
+#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
+#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
/* Flow Director registers */
-#define IXGBE_FDIRCTRL 0x0EE00
-#define IXGBE_FDIRHKEY 0x0EE68
-#define IXGBE_FDIRSKEY 0x0EE6C
-#define IXGBE_FDIRDIP4M 0x0EE3C
-#define IXGBE_FDIRSIP4M 0x0EE40
-#define IXGBE_FDIRTCPM 0x0EE44
-#define IXGBE_FDIRUDPM 0x0EE48
-#define IXGBE_FDIRIP6M 0x0EE74
-#define IXGBE_FDIRM 0x0EE70
+#define IXGBE_FDIRCTRL 0x0EE00
+#define IXGBE_FDIRHKEY 0x0EE68
+#define IXGBE_FDIRSKEY 0x0EE6C
+#define IXGBE_FDIRDIP4M 0x0EE3C
+#define IXGBE_FDIRSIP4M 0x0EE40
+#define IXGBE_FDIRTCPM 0x0EE44
+#define IXGBE_FDIRUDPM 0x0EE48
+#define IXGBE_FDIRIP6M 0x0EE74
+#define IXGBE_FDIRM 0x0EE70
/* Flow Director Stats registers */
-#define IXGBE_FDIRFREE 0x0EE38
-#define IXGBE_FDIRLEN 0x0EE4C
-#define IXGBE_FDIRUSTAT 0x0EE50
-#define IXGBE_FDIRFSTAT 0x0EE54
-#define IXGBE_FDIRMATCH 0x0EE58
-#define IXGBE_FDIRMISS 0x0EE5C
+#define IXGBE_FDIRFREE 0x0EE38
+#define IXGBE_FDIRLEN 0x0EE4C
+#define IXGBE_FDIRUSTAT 0x0EE50
+#define IXGBE_FDIRFSTAT 0x0EE54
+#define IXGBE_FDIRMATCH 0x0EE58
+#define IXGBE_FDIRMISS 0x0EE5C
/* Flow Director Programming registers */
#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
-#define IXGBE_FDIRIPSA 0x0EE18
-#define IXGBE_FDIRIPDA 0x0EE1C
-#define IXGBE_FDIRPORT 0x0EE20
-#define IXGBE_FDIRVLAN 0x0EE24
-#define IXGBE_FDIRHASH 0x0EE28
-#define IXGBE_FDIRCMD 0x0EE2C
+#define IXGBE_FDIRIPSA 0x0EE18
+#define IXGBE_FDIRIPDA 0x0EE1C
+#define IXGBE_FDIRPORT 0x0EE20
+#define IXGBE_FDIRVLAN 0x0EE24
+#define IXGBE_FDIRHASH 0x0EE28
+#define IXGBE_FDIRCMD 0x0EE2C
/* Transmit DMA registers */
-#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
-#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
-#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
-#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
-#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
-#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
-#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
-#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
-#define IXGBE_DTXCTL 0x07E00
+#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/
+#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
+#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
+#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
+#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
+#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
+#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
+#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
+#define IXGBE_DTXCTL 0x07E00
-#define IXGBE_DMATXCTL 0x04A80
-#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
-#define IXGBE_PFDTXGSWC 0x08220
-#define IXGBE_DTXMXSZRQ 0x08100
-#define IXGBE_DTXTCPFLGL 0x04A88
-#define IXGBE_DTXTCPFLGH 0x04A8C
-#define IXGBE_LBDRPEN 0x0CA00
-#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
+#define IXGBE_DMATXCTL 0x04A80
+#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
+#define IXGBE_PFDTXGSWC 0x08220
+#define IXGBE_DTXMXSZRQ 0x08100
+#define IXGBE_DTXTCPFLGL 0x04A88
+#define IXGBE_DTXTCPFLGH 0x04A8C
+#define IXGBE_LBDRPEN 0x0CA00
+#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
-#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
-#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
-#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
-#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
+#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
+#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
+#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
+#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
-#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
+#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
/* Anti-spoofing defines */
-#define IXGBE_SPOOF_MACAS_MASK 0xFF
-#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
-#define IXGBE_SPOOF_VLANAS_SHIFT 8
-#define IXGBE_PFVFSPOOF_REG_COUNT 8
-#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
+#define IXGBE_SPOOF_MACAS_MASK 0xFF
+#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
+#define IXGBE_SPOOF_VLANAS_SHIFT 8
+#define IXGBE_PFVFSPOOF_REG_COUNT 8
+/* 16 of these (0-15) */
+#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4))
/* Tx DCA Control register : 128 of these (0-127) */
-#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
-#define IXGBE_TIPG 0x0CB00
-#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
-#define IXGBE_MNGTXMAP 0x0CD10
-#define IXGBE_TIPG_FIBER_DEFAULT 3
-#define IXGBE_TXPBSIZE_SHIFT 10
+#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
+#define IXGBE_TIPG 0x0CB00
+#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_MNGTXMAP 0x0CD10
+#define IXGBE_TIPG_FIBER_DEFAULT 3
+#define IXGBE_TXPBSIZE_SHIFT 10
/* Wake up registers */
-#define IXGBE_WUC 0x05800
-#define IXGBE_WUFC 0x05808
-#define IXGBE_WUS 0x05810
-#define IXGBE_IPAV 0x05838
-#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
-#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
+#define IXGBE_WUC 0x05800
+#define IXGBE_WUFC 0x05808
+#define IXGBE_WUS 0x05810
+#define IXGBE_IPAV 0x05838
+#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
+#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
-#define IXGBE_WUPL 0x05900
-#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
-#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
-#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
- * Filter Table */
+#define IXGBE_WUPL 0x05900
+#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
+#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
+/* Ext Flexible Host Filter Table */
+#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100))
-#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
-#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
+#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
+#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
/* Each Flexible Filter is at most 128 (0x80) bytes in length */
-#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
-#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
-#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
+#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
+#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
+#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
/* Definitions for power management and wakeup registers */
/* Wake Up Control */
-#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
-#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
-#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */
+#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
+#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
+#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */
/* Wake Up Filter Control */
-#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
-#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
-#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
-#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
-#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
-#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
-#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
-#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
-#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
+#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
+#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
+#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
+#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
+#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
+#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
+#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
+#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
+#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
-#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
-#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
-#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
-#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
-#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
-#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
-#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
-#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
-#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
-#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */
-#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
+#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
+#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
+#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
+#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
+#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
+#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
+#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
+#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
+/* Mask for Ext. flex filters */
+#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
+#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */
+#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
/* Wake Up Status */
-#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
-#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
-#define IXGBE_WUS_EX IXGBE_WUFC_EX
-#define IXGBE_WUS_MC IXGBE_WUFC_MC
-#define IXGBE_WUS_BC IXGBE_WUFC_BC
-#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
-#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
-#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
-#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
-#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
-#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
-#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
-#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
-#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
-#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
-#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
+#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
+#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
+#define IXGBE_WUS_EX IXGBE_WUFC_EX
+#define IXGBE_WUS_MC IXGBE_WUFC_MC
+#define IXGBE_WUS_BC IXGBE_WUFC_BC
+#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
+#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
+#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
+#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
+#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
+#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
+#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
+#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
+#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
+#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
+#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
/* Wake Up Packet Length */
-#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
+#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
/* DCB registers */
-#define IXGBE_RMCS 0x03D00
-#define IXGBE_DPMCS 0x07F40
-#define IXGBE_PDPMCS 0x0CD00
-#define IXGBE_RUPPBMR 0x050A0
-#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
-#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
-#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8
+#define IXGBE_RMCS 0x03D00
+#define IXGBE_DPMCS 0x07F40
+#define IXGBE_PDPMCS 0x0CD00
+#define IXGBE_RUPPBMR 0x050A0
+#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
+#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
+#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
/* Security Control Registers */
-#define IXGBE_SECTXCTRL 0x08800
-#define IXGBE_SECTXSTAT 0x08804
-#define IXGBE_SECTXBUFFAF 0x08808
-#define IXGBE_SECTXMINIFG 0x08810
-#define IXGBE_SECTXSTAT 0x08804
-#define IXGBE_SECRXCTRL 0x08D00
-#define IXGBE_SECRXSTAT 0x08D04
+#define IXGBE_SECTXCTRL 0x08800
+#define IXGBE_SECTXSTAT 0x08804
+#define IXGBE_SECTXBUFFAF 0x08808
+#define IXGBE_SECTXMINIFG 0x08810
+#define IXGBE_SECRXCTRL 0x08D00
+#define IXGBE_SECRXSTAT 0x08D04
/* Security Bit Fields and Masks */
-#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
-#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
-#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
+#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
+#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
+#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
-#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
-#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
+#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
+#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
-#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
-#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
+#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
+#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
-#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
-#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
+#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
+#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
/* LinkSec (MacSec) Registers */
-#define IXGBE_LSECTXCAP 0x08A00
-#define IXGBE_LSECRXCAP 0x08F00
-#define IXGBE_LSECTXCTRL 0x08A04
-#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
-#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
-#define IXGBE_LSECTXSA 0x08A10
-#define IXGBE_LSECTXPN0 0x08A14
-#define IXGBE_LSECTXPN1 0x08A18
-#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
-#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
-#define IXGBE_LSECRXCTRL 0x08F04
-#define IXGBE_LSECRXSCL 0x08F08
-#define IXGBE_LSECRXSCH 0x08F0C
-#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
-#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
-#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
-#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
-#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
-#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
-#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
-#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
-#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
-#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
-#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
-#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
-#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
-#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
-#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
-#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
-#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
-#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
-#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
-#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
-#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
-#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
+#define IXGBE_LSECTXCAP 0x08A00
+#define IXGBE_LSECRXCAP 0x08F00
+#define IXGBE_LSECTXCTRL 0x08A04
+#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
+#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
+#define IXGBE_LSECTXSA 0x08A10
+#define IXGBE_LSECTXPN0 0x08A14
+#define IXGBE_LSECTXPN1 0x08A18
+#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
+#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
+#define IXGBE_LSECRXCTRL 0x08F04
+#define IXGBE_LSECRXSCL 0x08F08
+#define IXGBE_LSECRXSCH 0x08F0C
+#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
+#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
+#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
+#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
+#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
+#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
+#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
+#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
+#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
+#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
+#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
+#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
+#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
+#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
+#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
+#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
+#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
+#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
+#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
+#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
+#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
+#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
/* LinkSec (MacSec) Bit Fields and Masks */
-#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
-#define IXGBE_LSECTXCAP_SUM_SHIFT 16
-#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
-#define IXGBE_LSECRXCAP_SUM_SHIFT 16
+#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
+#define IXGBE_LSECTXCAP_SUM_SHIFT 16
+#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
+#define IXGBE_LSECRXCAP_SUM_SHIFT 16
-#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
-#define IXGBE_LSECTXCTRL_DISABLE 0x0
-#define IXGBE_LSECTXCTRL_AUTH 0x1
-#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
-#define IXGBE_LSECTXCTRL_AISCI 0x00000020
-#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
-#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
+#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
+#define IXGBE_LSECTXCTRL_DISABLE 0x0
+#define IXGBE_LSECTXCTRL_AUTH 0x1
+#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
+#define IXGBE_LSECTXCTRL_AISCI 0x00000020
+#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
+#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
-#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
-#define IXGBE_LSECRXCTRL_EN_SHIFT 2
-#define IXGBE_LSECRXCTRL_DISABLE 0x0
-#define IXGBE_LSECRXCTRL_CHECK 0x1
-#define IXGBE_LSECRXCTRL_STRICT 0x2
-#define IXGBE_LSECRXCTRL_DROP 0x3
-#define IXGBE_LSECRXCTRL_PLSH 0x00000040
-#define IXGBE_LSECRXCTRL_RP 0x00000080
-#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
+#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
+#define IXGBE_LSECRXCTRL_EN_SHIFT 2
+#define IXGBE_LSECRXCTRL_DISABLE 0x0
+#define IXGBE_LSECRXCTRL_CHECK 0x1
+#define IXGBE_LSECRXCTRL_STRICT 0x2
+#define IXGBE_LSECRXCTRL_DROP 0x3
+#define IXGBE_LSECRXCTRL_PLSH 0x00000040
+#define IXGBE_LSECRXCTRL_RP 0x00000080
+#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
/* IpSec Registers */
-#define IXGBE_IPSTXIDX 0x08900
-#define IXGBE_IPSTXSALT 0x08904
-#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
-#define IXGBE_IPSRXIDX 0x08E00
-#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
-#define IXGBE_IPSRXSPI 0x08E14
-#define IXGBE_IPSRXIPIDX 0x08E18
-#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
-#define IXGBE_IPSRXSALT 0x08E2C
-#define IXGBE_IPSRXMOD 0x08E30
+#define IXGBE_IPSTXIDX 0x08900
+#define IXGBE_IPSTXSALT 0x08904
+#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
+#define IXGBE_IPSRXIDX 0x08E00
+#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
+#define IXGBE_IPSRXSPI 0x08E14
+#define IXGBE_IPSRXIPIDX 0x08E18
+#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
+#define IXGBE_IPSRXSALT 0x08E2C
+#define IXGBE_IPSRXMOD 0x08E30
-#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
+#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
/* DCB registers */
-#define IXGBE_RTRPCS 0x02430
-#define IXGBE_RTTDCS 0x04900
-#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
-#define IXGBE_RTTPCS 0x0CD00
-#define IXGBE_RTRUP2TC 0x03020
-#define IXGBE_RTTUP2TC 0x0C800
-#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTTDQSEL 0x04904
-#define IXGBE_RTTDT1C 0x04908
-#define IXGBE_RTTDT1S 0x0490C
-#define IXGBE_RTTDTECC 0x04990
-#define IXGBE_RTTDTECC_NO_BCN 0x00000100
+#define IXGBE_RTRPCS 0x02430
+#define IXGBE_RTTDCS 0x04900
+#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
+#define IXGBE_RTTPCS 0x0CD00
+#define IXGBE_RTRUP2TC 0x03020
+#define IXGBE_RTTUP2TC 0x0C800
+#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
+#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTTDQSEL 0x04904
+#define IXGBE_RTTDT1C 0x04908
+#define IXGBE_RTTDT1S 0x0490C
+#define IXGBE_RTTDTECC 0x04990
+#define IXGBE_RTTDTECC_NO_BCN 0x00000100
-#define IXGBE_RTTBCNRC 0x04984
-#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
-#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
-#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
+#define IXGBE_RTTBCNRC 0x04984
+#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
+#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
+#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
#define IXGBE_RTTBCNRC_RF_INT_MASK \
(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
+#define IXGBE_RTTBCNRM 0x04980
/* BCN (for DCB) Registers */
-#define IXGBE_RTTBCNRM 0x04980
-#define IXGBE_RTTBCNRS 0x04988
-#define IXGBE_RTTBCNCR 0x08B00
-#define IXGBE_RTTBCNACH 0x08B04
-#define IXGBE_RTTBCNACL 0x08B08
-#define IXGBE_RTTBCNTG 0x04A90
-#define IXGBE_RTTBCNIDX 0x08B0C
-#define IXGBE_RTTBCNCP 0x08B10
-#define IXGBE_RTFRTIMER 0x08B14
-#define IXGBE_RTTBCNRTT 0x05150
-#define IXGBE_RTTBCNRD 0x0498C
+#define IXGBE_RTTBCNRS 0x04988
+#define IXGBE_RTTBCNCR 0x08B00
+#define IXGBE_RTTBCNACH 0x08B04
+#define IXGBE_RTTBCNACL 0x08B08
+#define IXGBE_RTTBCNTG 0x04A90
+#define IXGBE_RTTBCNIDX 0x08B0C
+#define IXGBE_RTTBCNCP 0x08B10
+#define IXGBE_RTFRTIMER 0x08B14
+#define IXGBE_RTTBCNRTT 0x05150
+#define IXGBE_RTTBCNRD 0x0498C
/* FCoE DMA Context Registers */
-#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
-#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
-#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
-#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
-#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
-#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
-#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
-#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
-#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
-#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
-#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
-#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
-#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
-#define IXGBE_FCBUFF_OFFSET_SHIFT 16
-#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
-#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
-#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
-#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
-#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
+#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
+#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
+#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
+#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
+#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0*/
+#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
+#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
+#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
+#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
+#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
+#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
+#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
+#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
+#define IXGBE_FCBUFF_OFFSET_SHIFT 16
+#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
+#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
+#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
+#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
+#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
/* FCoE SOF/EOF */
-#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
-#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
-#define IXGBE_REOFF 0x05158 /* Rx FC EOF */
-#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
+#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
+#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
+#define IXGBE_REOFF 0x05158 /* Rx FC EOF */
+#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
/* FCoE Filter Context Registers */
-#define IXGBE_FCFLT 0x05108 /* FC FLT Context */
-#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
-#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
-#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
-#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
-#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
-#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
-#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
-#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
-#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
+#define IXGBE_FCFLT 0x05108 /* FC FLT Context */
+#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
+#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
+#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
+#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
+#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
+#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
+#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
+#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
+#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
/* FCoE Receive Control */
-#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
-#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
-#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
-#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
-#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
-#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
-#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
-#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
-#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
-#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
-#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
+#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
+#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
+#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
+#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
+#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
+#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
+#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
+#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
+#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
+#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
+#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
/* FCoE Redirection */
-#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
-#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
-#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
-#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
-#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
-#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
+#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
+#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
+#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
+#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
+#define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */
+#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
+#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
/* Stats registers */
-#define IXGBE_CRCERRS 0x04000
-#define IXGBE_ILLERRC 0x04004
-#define IXGBE_ERRBC 0x04008
-#define IXGBE_MSPDC 0x04010
-#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
-#define IXGBE_MLFC 0x04034
-#define IXGBE_MRFC 0x04038
-#define IXGBE_RLEC 0x04040
-#define IXGBE_LXONTXC 0x03F60
-#define IXGBE_LXONRXC 0x0CF60
-#define IXGBE_LXOFFTXC 0x03F68
-#define IXGBE_LXOFFRXC 0x0CF68
-#define IXGBE_LXONRXCNT 0x041A4
-#define IXGBE_LXOFFRXCNT 0x041A8
-#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
-#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
-#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
-#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
-#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
-#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
-#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
-#define IXGBE_PRC64 0x0405C
-#define IXGBE_PRC127 0x04060
-#define IXGBE_PRC255 0x04064
-#define IXGBE_PRC511 0x04068
-#define IXGBE_PRC1023 0x0406C
-#define IXGBE_PRC1522 0x04070
-#define IXGBE_GPRC 0x04074
-#define IXGBE_BPRC 0x04078
-#define IXGBE_MPRC 0x0407C
-#define IXGBE_GPTC 0x04080
-#define IXGBE_GORCL 0x04088
-#define IXGBE_GORCH 0x0408C
-#define IXGBE_GOTCL 0x04090
-#define IXGBE_GOTCH 0x04094
-#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
-#define IXGBE_RUC 0x040A4
-#define IXGBE_RFC 0x040A8
-#define IXGBE_ROC 0x040AC
-#define IXGBE_RJC 0x040B0
-#define IXGBE_MNGPRC 0x040B4
-#define IXGBE_MNGPDC 0x040B8
-#define IXGBE_MNGPTC 0x0CF90
-#define IXGBE_TORL 0x040C0
-#define IXGBE_TORH 0x040C4
-#define IXGBE_TPR 0x040D0
-#define IXGBE_TPT 0x040D4
-#define IXGBE_PTC64 0x040D8
-#define IXGBE_PTC127 0x040DC
-#define IXGBE_PTC255 0x040E0
-#define IXGBE_PTC511 0x040E4
-#define IXGBE_PTC1023 0x040E8
-#define IXGBE_PTC1522 0x040EC
-#define IXGBE_MPTC 0x040F0
-#define IXGBE_BPTC 0x040F4
-#define IXGBE_XEC 0x04120
-#define IXGBE_SSVPC 0x08780
+#define IXGBE_CRCERRS 0x04000
+#define IXGBE_ILLERRC 0x04004
+#define IXGBE_ERRBC 0x04008
+#define IXGBE_MSPDC 0x04010
+#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
+#define IXGBE_MLFC 0x04034
+#define IXGBE_MRFC 0x04038
+#define IXGBE_RLEC 0x04040
+#define IXGBE_LXONTXC 0x03F60
+#define IXGBE_LXONRXC 0x0CF60
+#define IXGBE_LXOFFTXC 0x03F68
+#define IXGBE_LXOFFRXC 0x0CF68
+#define IXGBE_LXONRXCNT 0x041A4
+#define IXGBE_LXOFFRXCNT 0x041A8
+#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
+#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
+#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
+#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
+#define IXGBE_PRC64 0x0405C
+#define IXGBE_PRC127 0x04060
+#define IXGBE_PRC255 0x04064
+#define IXGBE_PRC511 0x04068
+#define IXGBE_PRC1023 0x0406C
+#define IXGBE_PRC1522 0x04070
+#define IXGBE_GPRC 0x04074
+#define IXGBE_BPRC 0x04078
+#define IXGBE_MPRC 0x0407C
+#define IXGBE_GPTC 0x04080
+#define IXGBE_GORCL 0x04088
+#define IXGBE_GORCH 0x0408C
+#define IXGBE_GOTCL 0x04090
+#define IXGBE_GOTCH 0x04094
+#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
+#define IXGBE_RUC 0x040A4
+#define IXGBE_RFC 0x040A8
+#define IXGBE_ROC 0x040AC
+#define IXGBE_RJC 0x040B0
+#define IXGBE_MNGPRC 0x040B4
+#define IXGBE_MNGPDC 0x040B8
+#define IXGBE_MNGPTC 0x0CF90
+#define IXGBE_TORL 0x040C0
+#define IXGBE_TORH 0x040C4
+#define IXGBE_TPR 0x040D0
+#define IXGBE_TPT 0x040D4
+#define IXGBE_PTC64 0x040D8
+#define IXGBE_PTC127 0x040DC
+#define IXGBE_PTC255 0x040E0
+#define IXGBE_PTC511 0x040E4
+#define IXGBE_PTC1023 0x040E8
+#define IXGBE_PTC1522 0x040EC
+#define IXGBE_MPTC 0x040F0
+#define IXGBE_BPTC 0x040F4
+#define IXGBE_XEC 0x04120
+#define IXGBE_SSVPC 0x08780
-#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
-#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
- (0x08600 + ((_i) * 4)))
-#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
+#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
+#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
+ (0x08600 + ((_i) * 4)))
+#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
-#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
-#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
-#define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
-#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
-#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
-#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
-#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
-#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
-#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
-#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */
-#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */
+#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
+#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
+#define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */
+#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
+#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
+#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
+#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
+#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
+#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
+#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */
+#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */
+#define IXGBE_O2BGPTC 0x041C4
+#define IXGBE_O2BSPC 0x087B0
+#define IXGBE_B2OSPC 0x041C0
+#define IXGBE_B2OGPRC 0x02F90
+#define IXGBE_BUPRC 0x04180
+#define IXGBE_BMPRC 0x04184
+#define IXGBE_BBPRC 0x04188
+#define IXGBE_BUPTC 0x0418C
+#define IXGBE_BMPTC 0x04190
+#define IXGBE_BBPTC 0x04194
+#define IXGBE_BCRCERRS 0x04198
+#define IXGBE_BXONRXC 0x0419C
+#define IXGBE_BXOFFRXC 0x041E0
+#define IXGBE_BXONTXC 0x041E4
+#define IXGBE_BXOFFTXC 0x041E8
+#define IXGBE_PCRC8ECL 0x0E810
+#define IXGBE_PCRC8ECH 0x0E811
+#define IXGBE_PCRC8ECH_MASK 0x1F
+#define IXGBE_LDPCECL 0x0E820
+#define IXGBE_LDPCECH 0x0E821
/* Management */
-#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_MANC 0x05820
-#define IXGBE_MFVAL 0x05824
-#define IXGBE_MANC2H 0x05860
-#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_MIPAF 0x058B0
-#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
-#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
-#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
-#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
-#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_LSWFW 0x15014
+#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_MANC 0x05820
+#define IXGBE_MFVAL 0x05824
+#define IXGBE_MANC2H 0x05860
+#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_MIPAF 0x058B0
+#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
+#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
+#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
+#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
+#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_LSWFW 0x15014
+#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
+#define IXGBE_BMCIPVAL 0x05060
+#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
+#define IXGBE_BMCIP_IPADDR_VALID 0x00000002
+
+/* Management Bit Fields and Masks */
+#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */
+#define IXGBE_MANC_EN_BMC2OS_SHIFT 28
+
+/* Firmware Semaphore Register */
+#define IXGBE_FWSM_MODE_MASK 0xE
/* ARC Subsystem registers */
-#define IXGBE_HICR 0x15F00
-#define IXGBE_FWSTS 0x15F0C
-#define IXGBE_HSMC0R 0x15F04
-#define IXGBE_HSMC1R 0x15F08
-#define IXGBE_SWSR 0x15F10
-#define IXGBE_HFDR 0x15FE8
-#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
+#define IXGBE_HICR 0x15F00
+#define IXGBE_FWSTS 0x15F0C
+#define IXGBE_HSMC0R 0x15F04
+#define IXGBE_HSMC1R 0x15F08
+#define IXGBE_SWSR 0x15F10
+#define IXGBE_HFDR 0x15FE8
+#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
+
+#define IXGBE_HICR_EN 0x01 /* Enable bit - RO */
+/* Driver sets this bit when done to put command in RAM */
+#define IXGBE_HICR_C 0x02
+#define IXGBE_HICR_SV 0x04 /* Status Validity */
+#define IXGBE_HICR_FW_RESET_ENABLE 0x40
+#define IXGBE_HICR_FW_RESET 0x80
/* PCI-E registers */
-#define IXGBE_GCR 0x11000
-#define IXGBE_GTV 0x11004
-#define IXGBE_FUNCTAG 0x11008
-#define IXGBE_GLT 0x1100C
-#define IXGBE_GSCL_1 0x11010
-#define IXGBE_GSCL_2 0x11014
-#define IXGBE_GSCL_3 0x11018
-#define IXGBE_GSCL_4 0x1101C
-#define IXGBE_GSCN_0 0x11020
-#define IXGBE_GSCN_1 0x11024
-#define IXGBE_GSCN_2 0x11028
-#define IXGBE_GSCN_3 0x1102C
-#define IXGBE_FACTPS 0x10150
-#define IXGBE_PCIEANACTL 0x11040
-#define IXGBE_SWSM 0x10140
-#define IXGBE_FWSM 0x10148
-#define IXGBE_GSSR 0x10160
-#define IXGBE_MREVID 0x11064
-#define IXGBE_DCA_ID 0x11070
-#define IXGBE_DCA_CTRL 0x11074
-#define IXGBE_SWFW_SYNC IXGBE_GSSR
+#define IXGBE_GCR 0x11000
+#define IXGBE_GTV 0x11004
+#define IXGBE_FUNCTAG 0x11008
+#define IXGBE_GLT 0x1100C
+#define IXGBE_PCIEPIPEADR 0x11004
+#define IXGBE_PCIEPIPEDAT 0x11008
+#define IXGBE_GSCL_1 0x11010
+#define IXGBE_GSCL_2 0x11014
+#define IXGBE_GSCL_3 0x11018
+#define IXGBE_GSCL_4 0x1101C
+#define IXGBE_GSCN_0 0x11020
+#define IXGBE_GSCN_1 0x11024
+#define IXGBE_GSCN_2 0x11028
+#define IXGBE_GSCN_3 0x1102C
+#define IXGBE_FACTPS 0x10150
+#define IXGBE_PCIEANACTL 0x11040
+#define IXGBE_SWSM 0x10140
+#define IXGBE_FWSM 0x10148
+#define IXGBE_GSSR 0x10160
+#define IXGBE_MREVID 0x11064
+#define IXGBE_DCA_ID 0x11070
+#define IXGBE_DCA_CTRL 0x11074
+#define IXGBE_SWFW_SYNC IXGBE_GSSR
/* PCI-E registers 82599-Specific */
-#define IXGBE_GCR_EXT 0x11050
-#define IXGBE_GSCL_5_82599 0x11030
-#define IXGBE_GSCL_6_82599 0x11034
-#define IXGBE_GSCL_7_82599 0x11038
-#define IXGBE_GSCL_8_82599 0x1103C
-#define IXGBE_PHYADR_82599 0x11040
-#define IXGBE_PHYDAT_82599 0x11044
-#define IXGBE_PHYCTL_82599 0x11048
-#define IXGBE_PBACLR_82599 0x11068
-#define IXGBE_CIAA_82599 0x11088
-#define IXGBE_CIAD_82599 0x1108C
-#define IXGBE_INTRPT_CSR_82599 0x110B0
-#define IXGBE_INTRPT_MASK_82599 0x110B8
-#define IXGBE_CDQ_MBR_82599 0x110B4
-#define IXGBE_MISC_REG_82599 0x110F0
-#define IXGBE_ECC_CTRL_0_82599 0x11100
-#define IXGBE_ECC_CTRL_1_82599 0x11104
-#define IXGBE_ECC_STATUS_82599 0x110E0
-#define IXGBE_BAR_CTRL_82599 0x110F4
+#define IXGBE_GCR_EXT 0x11050
+#define IXGBE_GSCL_5_82599 0x11030
+#define IXGBE_GSCL_6_82599 0x11034
+#define IXGBE_GSCL_7_82599 0x11038
+#define IXGBE_GSCL_8_82599 0x1103C
+#define IXGBE_PHYADR_82599 0x11040
+#define IXGBE_PHYDAT_82599 0x11044
+#define IXGBE_PHYCTL_82599 0x11048
+#define IXGBE_PBACLR_82599 0x11068
+#define IXGBE_CIAA_82599 0x11088
+#define IXGBE_CIAD_82599 0x1108C
+#define IXGBE_PICAUSE 0x110B0
+#define IXGBE_PIENA 0x110B8
+#define IXGBE_CDQ_MBR_82599 0x110B4
+#define IXGBE_PCIESPARE 0x110BC
+#define IXGBE_MISC_REG_82599 0x110F0
+#define IXGBE_ECC_CTRL_0_82599 0x11100
+#define IXGBE_ECC_CTRL_1_82599 0x11104
+#define IXGBE_ECC_STATUS_82599 0x110E0
+#define IXGBE_BAR_CTRL_82599 0x110F4
/* PCI Express Control */
-#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
-#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
-#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
-#define IXGBE_GCR_CAP_VER2 0x00040000
+#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
+#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
+#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
+#define IXGBE_GCR_CAP_VER2 0x00040000
-#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
-#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
-#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
-#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
-#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
- IXGBE_GCR_EXT_VT_MODE_64)
+#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
+#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
+#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
+#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
+#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
+#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
+ IXGBE_GCR_EXT_VT_MODE_64)
+#define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003
/* Time Sync Registers */
-#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
-#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
-#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
-#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
-#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
-#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
-#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
-#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
-#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
-#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
-#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
-#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
-#define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW */
+#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
+#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
+#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
+#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
+#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
+#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
+#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
+#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
+#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
+#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
+#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
+#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
+#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */
+#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */
+#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */
+#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
+#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
+#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
+#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
+#define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */
+#define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */
+#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
+#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
+#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
+#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
+#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
+#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
/* Diagnostic Registers */
-#define IXGBE_RDSTATCTL 0x02C20
-#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
-#define IXGBE_RDHMPN 0x02F08
-#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
-#define IXGBE_RDPROBE 0x02F20
-#define IXGBE_RDMAM 0x02F30
-#define IXGBE_RDMAD 0x02F34
-#define IXGBE_TDSTATCTL 0x07C20
-#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
-#define IXGBE_TDHMPN 0x07F08
-#define IXGBE_TDHMPN2 0x082FC
-#define IXGBE_TXDESCIC 0x082CC
-#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
-#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
-#define IXGBE_TDPROBE 0x07F20
-#define IXGBE_TXBUFCTRL 0x0C600
-#define IXGBE_TXBUFDATA0 0x0C610
-#define IXGBE_TXBUFDATA1 0x0C614
-#define IXGBE_TXBUFDATA2 0x0C618
-#define IXGBE_TXBUFDATA3 0x0C61C
-#define IXGBE_RXBUFCTRL 0x03600
-#define IXGBE_RXBUFDATA0 0x03610
-#define IXGBE_RXBUFDATA1 0x03614
-#define IXGBE_RXBUFDATA2 0x03618
-#define IXGBE_RXBUFDATA3 0x0361C
-#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
-#define IXGBE_RFVAL 0x050A4
-#define IXGBE_MDFTC1 0x042B8
-#define IXGBE_MDFTC2 0x042C0
-#define IXGBE_MDFTFIFO1 0x042C4
-#define IXGBE_MDFTFIFO2 0x042C8
-#define IXGBE_MDFTS 0x042CC
-#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
-#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
-#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
-#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
-#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
-#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
-#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
-#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
-#define IXGBE_PCIEECCCTL 0x1106C
-#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
-#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
-#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
-#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
-#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
-#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
-#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
-#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
-#define IXGBE_PCIEECCCTL0 0x11100
-#define IXGBE_PCIEECCCTL1 0x11104
-#define IXGBE_RXDBUECC 0x03F70
-#define IXGBE_TXDBUECC 0x0CF70
-#define IXGBE_RXDBUEST 0x03F74
-#define IXGBE_TXDBUEST 0x0CF74
-#define IXGBE_PBTXECC 0x0C300
-#define IXGBE_PBRXECC 0x03300
-#define IXGBE_GHECCR 0x110B0
+#define IXGBE_RDSTATCTL 0x02C20
+#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
+#define IXGBE_RDHMPN 0x02F08
+#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
+#define IXGBE_RDPROBE 0x02F20
+#define IXGBE_RDMAM 0x02F30
+#define IXGBE_RDMAD 0x02F34
+#define IXGBE_TDSTATCTL 0x07C20
+#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
+#define IXGBE_TDHMPN 0x07F08
+#define IXGBE_TDHMPN2 0x082FC
+#define IXGBE_TXDESCIC 0x082CC
+#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
+#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
+#define IXGBE_TDPROBE 0x07F20
+#define IXGBE_TXBUFCTRL 0x0C600
+#define IXGBE_TXBUFDATA0 0x0C610
+#define IXGBE_TXBUFDATA1 0x0C614
+#define IXGBE_TXBUFDATA2 0x0C618
+#define IXGBE_TXBUFDATA3 0x0C61C
+#define IXGBE_RXBUFCTRL 0x03600
+#define IXGBE_RXBUFDATA0 0x03610
+#define IXGBE_RXBUFDATA1 0x03614
+#define IXGBE_RXBUFDATA2 0x03618
+#define IXGBE_RXBUFDATA3 0x0361C
+#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_RFVAL 0x050A4
+#define IXGBE_MDFTC1 0x042B8
+#define IXGBE_MDFTC2 0x042C0
+#define IXGBE_MDFTFIFO1 0x042C4
+#define IXGBE_MDFTFIFO2 0x042C8
+#define IXGBE_MDFTS 0x042CC
+#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
+#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
+#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
+#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
+#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
+#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
+#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
+#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
+#define IXGBE_PCIEECCCTL 0x1106C
+#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
+#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
+#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
+#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
+#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
+#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
+#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
+#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
+#define IXGBE_PCIEECCCTL0 0x11100
+#define IXGBE_PCIEECCCTL1 0x11104
+#define IXGBE_RXDBUECC 0x03F70
+#define IXGBE_TXDBUECC 0x0CF70
+#define IXGBE_RXDBUEST 0x03F74
+#define IXGBE_TXDBUEST 0x0CF74
+#define IXGBE_PBTXECC 0x0C300
+#define IXGBE_PBRXECC 0x03300
+#define IXGBE_GHECCR 0x110B0
/* MAC Registers */
-#define IXGBE_PCS1GCFIG 0x04200
-#define IXGBE_PCS1GLCTL 0x04208
-#define IXGBE_PCS1GLSTA 0x0420C
-#define IXGBE_PCS1GDBG0 0x04210
-#define IXGBE_PCS1GDBG1 0x04214
-#define IXGBE_PCS1GANA 0x04218
-#define IXGBE_PCS1GANLP 0x0421C
-#define IXGBE_PCS1GANNP 0x04220
-#define IXGBE_PCS1GANLPNP 0x04224
-#define IXGBE_HLREG0 0x04240
-#define IXGBE_HLREG1 0x04244
-#define IXGBE_PAP 0x04248
-#define IXGBE_MACA 0x0424C
-#define IXGBE_APAE 0x04250
-#define IXGBE_ARD 0x04254
-#define IXGBE_AIS 0x04258
-#define IXGBE_MSCA 0x0425C
-#define IXGBE_MSRWD 0x04260
-#define IXGBE_MLADD 0x04264
-#define IXGBE_MHADD 0x04268
-#define IXGBE_MAXFRS 0x04268
-#define IXGBE_TREG 0x0426C
-#define IXGBE_PCSS1 0x04288
-#define IXGBE_PCSS2 0x0428C
-#define IXGBE_XPCSS 0x04290
-#define IXGBE_MFLCN 0x04294
-#define IXGBE_SERDESC 0x04298
-#define IXGBE_MACS 0x0429C
-#define IXGBE_AUTOC 0x042A0
-#define IXGBE_LINKS 0x042A4
-#define IXGBE_LINKS2 0x04324
-#define IXGBE_AUTOC2 0x042A8
-#define IXGBE_AUTOC3 0x042AC
-#define IXGBE_ANLP1 0x042B0
-#define IXGBE_ANLP2 0x042B4
-#define IXGBE_ATLASCTL 0x04800
-#define IXGBE_MMNGC 0x042D0
-#define IXGBE_ANLPNP1 0x042D4
-#define IXGBE_ANLPNP2 0x042D8
-#define IXGBE_KRPCSFC 0x042E0
-#define IXGBE_KRPCSS 0x042E4
-#define IXGBE_FECS1 0x042E8
-#define IXGBE_FECS2 0x042EC
-#define IXGBE_SMADARCTL 0x14F10
-#define IXGBE_MPVC 0x04318
-#define IXGBE_SGMIIC 0x04314
+#define IXGBE_PCS1GCFIG 0x04200
+#define IXGBE_PCS1GLCTL 0x04208
+#define IXGBE_PCS1GLSTA 0x0420C
+#define IXGBE_PCS1GDBG0 0x04210
+#define IXGBE_PCS1GDBG1 0x04214
+#define IXGBE_PCS1GANA 0x04218
+#define IXGBE_PCS1GANLP 0x0421C
+#define IXGBE_PCS1GANNP 0x04220
+#define IXGBE_PCS1GANLPNP 0x04224
+#define IXGBE_HLREG0 0x04240
+#define IXGBE_HLREG1 0x04244
+#define IXGBE_PAP 0x04248
+#define IXGBE_MACA 0x0424C
+#define IXGBE_APAE 0x04250
+#define IXGBE_ARD 0x04254
+#define IXGBE_AIS 0x04258
+#define IXGBE_MSCA 0x0425C
+#define IXGBE_MSRWD 0x04260
+#define IXGBE_MLADD 0x04264
+#define IXGBE_MHADD 0x04268
+#define IXGBE_MAXFRS 0x04268
+#define IXGBE_TREG 0x0426C
+#define IXGBE_PCSS1 0x04288
+#define IXGBE_PCSS2 0x0428C
+#define IXGBE_XPCSS 0x04290
+#define IXGBE_MFLCN 0x04294
+#define IXGBE_SERDESC 0x04298
+#define IXGBE_MACS 0x0429C
+#define IXGBE_AUTOC 0x042A0
+#define IXGBE_LINKS 0x042A4
+#define IXGBE_LINKS2 0x04324
+#define IXGBE_AUTOC2 0x042A8
+#define IXGBE_AUTOC3 0x042AC
+#define IXGBE_ANLP1 0x042B0
+#define IXGBE_ANLP2 0x042B4
+#define IXGBE_MACC 0x04330
+#define IXGBE_ATLASCTL 0x04800
+#define IXGBE_MMNGC 0x042D0
+#define IXGBE_ANLPNP1 0x042D4
+#define IXGBE_ANLPNP2 0x042D8
+#define IXGBE_KRPCSFC 0x042E0
+#define IXGBE_KRPCSS 0x042E4
+#define IXGBE_FECS1 0x042E8
+#define IXGBE_FECS2 0x042EC
+#define IXGBE_SMADARCTL 0x14F10
+#define IXGBE_MPVC 0x04318
+#define IXGBE_SGMIIC 0x04314
+
+/* Statistics Registers */
+#define IXGBE_RXNFGPC 0x041B0
+#define IXGBE_RXNFGBCL 0x041B4
+#define IXGBE_RXNFGBCH 0x041B8
+#define IXGBE_RXDGPC 0x02F50
+#define IXGBE_RXDGBCL 0x02F54
+#define IXGBE_RXDGBCH 0x02F58
+#define IXGBE_RXDDGPC 0x02F5C
+#define IXGBE_RXDDGBCL 0x02F60
+#define IXGBE_RXDDGBCH 0x02F64
+#define IXGBE_RXLPBKGPC 0x02F68
+#define IXGBE_RXLPBKGBCL 0x02F6C
+#define IXGBE_RXLPBKGBCH 0x02F70
+#define IXGBE_RXDLPBKGPC 0x02F74
+#define IXGBE_RXDLPBKGBCL 0x02F78
+#define IXGBE_RXDLPBKGBCH 0x02F7C
+#define IXGBE_TXDGPC 0x087A0
+#define IXGBE_TXDGBCL 0x087A4
+#define IXGBE_TXDGBCH 0x087A8
+
+#define IXGBE_RXDSTATCTRL 0x02F40
/* Copper Pond 2 link timeout */
#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
/* Omer CORECTL */
-#define IXGBE_CORECTL 0x014F00
+#define IXGBE_CORECTL 0x014F00
/* BARCTRL */
-#define IXGBE_BARCTRL 0x110F4
-#define IXGBE_BARCTRL_FLSIZE 0x0700
-#define IXGBE_BARCTRL_FLSIZE_SHIFT 8
-#define IXGBE_BARCTRL_CSRSIZE 0x2000
+#define IXGBE_BARCTRL 0x110F4
+#define IXGBE_BARCTRL_FLSIZE 0x0700
+#define IXGBE_BARCTRL_FLSIZE_SHIFT 8
+#define IXGBE_BARCTRL_CSRSIZE 0x2000
/* RSCCTL Bit Masks */
-#define IXGBE_RSCCTL_RSCEN 0x01
-#define IXGBE_RSCCTL_MAXDESC_1 0x00
-#define IXGBE_RSCCTL_MAXDESC_4 0x04
-#define IXGBE_RSCCTL_MAXDESC_8 0x08
-#define IXGBE_RSCCTL_MAXDESC_16 0x0C
+#define IXGBE_RSCCTL_RSCEN 0x01
+#define IXGBE_RSCCTL_MAXDESC_1 0x00
+#define IXGBE_RSCCTL_MAXDESC_4 0x04
+#define IXGBE_RSCCTL_MAXDESC_8 0x08
+#define IXGBE_RSCCTL_MAXDESC_16 0x0C
/* RSCDBU Bit Masks */
-#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
-#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
+#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
+#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
/* RDRXCTL Bit Masks */
-#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
-#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
-#define IXGBE_RDRXCTL_MVMEN 0x00000020
-#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
-#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
-#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
-#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */
-#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */
-#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
+#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */
+#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
+#define IXGBE_RDRXCTL_MVMEN 0x00000020
+#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
+#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
+#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
+#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disabl RSC compl on LLI */
+#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */
+#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */
/* RQTC Bit Masks and Shifts */
-#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
-#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
-#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
-#define IXGBE_RQTC_TC2_MASK (0x7 << 8)
-#define IXGBE_RQTC_TC3_MASK (0x7 << 12)
-#define IXGBE_RQTC_TC4_MASK (0x7 << 16)
-#define IXGBE_RQTC_TC5_MASK (0x7 << 20)
-#define IXGBE_RQTC_TC6_MASK (0x7 << 24)
-#define IXGBE_RQTC_TC7_MASK (0x7 << 28)
+#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
+#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
+#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
+#define IXGBE_RQTC_TC2_MASK (0x7 << 8)
+#define IXGBE_RQTC_TC3_MASK (0x7 << 12)
+#define IXGBE_RQTC_TC4_MASK (0x7 << 16)
+#define IXGBE_RQTC_TC5_MASK (0x7 << 20)
+#define IXGBE_RQTC_TC6_MASK (0x7 << 24)
+#define IXGBE_RQTC_TC7_MASK (0x7 << 28)
/* PSRTYPE.RQPL Bit masks and shift */
-#define IXGBE_PSRTYPE_RQPL_MASK 0x7
-#define IXGBE_PSRTYPE_RQPL_SHIFT 29
+#define IXGBE_PSRTYPE_RQPL_MASK 0x7
+#define IXGBE_PSRTYPE_RQPL_SHIFT 29
/* CTRL Bit Masks */
-#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
-#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
-#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
+#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
+#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
+#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
+#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
/* FACTPS */
-#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
+#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
/* MHADD Bit Masks */
-#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
-#define IXGBE_MHADD_MFS_SHIFT 16
+#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
+#define IXGBE_MHADD_MFS_SHIFT 16
/* Extended Device Control */
-#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
-#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
-#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
-#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
+#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
+#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
+#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
+#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
/* Direct Cache Access (DCA) definitions */
-#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
-#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
+#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
+#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
-#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
-#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
+#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
+#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
-#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
-#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
-#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
-#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
-#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
-#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
-#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
-#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
-#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
+#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
+#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
+#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
+#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */
+#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */
+#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */
+#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */
+#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */
+#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */
-#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
-#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
-#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
-#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
-#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
-#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
+#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
+#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
+#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
+#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
+#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
+#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */
+#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
+#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
/* MSCA Bit Masks */
-#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
-#define IXGBE_MSCA_NP_ADDR_SHIFT 0
-#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
-#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
-#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
-#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
-#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
-#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
-#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
-#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
-#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */
-#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/
-#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
-#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
-#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
-#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
-#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
-#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
+#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */
+#define IXGBE_MSCA_NP_ADDR_SHIFT 0
+#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */
+#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */
+#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
+#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
+#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
+#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
+#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
+#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (wr) */
+#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (rd) */
+#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (rd auto inc)*/
+#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
+#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
+#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new prot) */
+#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old prot) */
+#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
+#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress ena */
/* MSRWD bit masks */
-#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
-#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
-#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
-#define IXGBE_MSRWD_READ_DATA_SHIFT 16
+#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
+#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
+#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
+#define IXGBE_MSRWD_READ_DATA_SHIFT 16
/* Atlas registers */
-#define IXGBE_ATLAS_PDN_LPBK 0x24
-#define IXGBE_ATLAS_PDN_10G 0xB
-#define IXGBE_ATLAS_PDN_1G 0xC
-#define IXGBE_ATLAS_PDN_AN 0xD
+#define IXGBE_ATLAS_PDN_LPBK 0x24
+#define IXGBE_ATLAS_PDN_10G 0xB
+#define IXGBE_ATLAS_PDN_1G 0xC
+#define IXGBE_ATLAS_PDN_AN 0xD
/* Atlas bit masks */
-#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
-#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
-#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
-#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
-#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
+#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
+#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
+#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
+#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
+#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
/* Omer bit masks */
-#define IXGBE_CORECTL_WRITE_CMD 0x00010000
+#define IXGBE_CORECTL_WRITE_CMD 0x00010000
/* Device Type definitions for new protocol MDIO commands */
-#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
-#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
-#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
-#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
-#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
-#define IXGBE_TWINAX_DEV 1
+#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
+#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
+#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
+#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
+#define IXGBE_TWINAX_DEV 1
-#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
+#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
-#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
-#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
-#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
-#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
-#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
-#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
-#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
-#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
-#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
-#define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */
-#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
-#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
-#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
-#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
-#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
-#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
-#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
-#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */
-#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */
-#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */
-#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */
-#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */
-#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */
+#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
+#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
+#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
+#define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */
+#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
+#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
+#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
+#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
+#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
+#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
+#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
+#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */
+#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */
+#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */
+#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */
+#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */
+#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */
-#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
-#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
-#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
-#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
+#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
+#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
+#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
+#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
/* MII clause 22/28 definitions */
-#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
+#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
-#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */
+#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */
#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
-#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
-#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */
-#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/
-#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
-#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
-#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */
-#define IXGBE_MII_RESTART 0x200
-#define IXGBE_MII_AUTONEG_COMPLETE 0x20
-#define IXGBE_MII_AUTONEG_LINK_UP 0x04
-#define IXGBE_MII_AUTONEG_REG 0x0
+#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
+#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */
+#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/
+#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
+#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
+#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */
+#define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */
+#define IXGBE_MII_RESTART 0x200
+#define IXGBE_MII_AUTONEG_COMPLETE 0x20
+#define IXGBE_MII_AUTONEG_LINK_UP 0x04
+#define IXGBE_MII_AUTONEG_REG 0x0
-#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
-#define IXGBE_MAX_PHY_ADDR 32
+#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
+#define IXGBE_MAX_PHY_ADDR 32
/* PHY IDs*/
-#define TN1010_PHY_ID 0x00A19410
-#define TNX_FW_REV 0xB
-#define AQ1002_PHY_ID 0x03A1B420
-#define AQ_FW_REV 0x20
-#define QT2022_PHY_ID 0x0043A400
-#define ATH_PHY_ID 0x03429050
+#define TN1010_PHY_ID 0x00A19410
+#define TNX_FW_REV 0xB
+#define X540_PHY_ID 0x01540200
+#define AQ_FW_REV 0x20
+#define QT2022_PHY_ID 0x0043A400
+#define ATH_PHY_ID 0x03429050
/* PHY Types */
-#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
+#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
/* Special PHY Init Routine */
-#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
-#define IXGBE_PHY_INIT_END_NL 0xFFFF
-#define IXGBE_CONTROL_MASK_NL 0xF000
-#define IXGBE_DATA_MASK_NL 0x0FFF
-#define IXGBE_CONTROL_SHIFT_NL 12
-#define IXGBE_DELAY_NL 0
-#define IXGBE_DATA_NL 1
-#define IXGBE_CONTROL_NL 0x000F
-#define IXGBE_CONTROL_EOL_NL 0x0FFF
-#define IXGBE_CONTROL_SOL_NL 0x0000
+#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
+#define IXGBE_PHY_INIT_END_NL 0xFFFF
+#define IXGBE_CONTROL_MASK_NL 0xF000
+#define IXGBE_DATA_MASK_NL 0x0FFF
+#define IXGBE_CONTROL_SHIFT_NL 12
+#define IXGBE_DELAY_NL 0
+#define IXGBE_DATA_NL 1
+#define IXGBE_CONTROL_NL 0x000F
+#define IXGBE_CONTROL_EOL_NL 0x0FFF
+#define IXGBE_CONTROL_SOL_NL 0x0000
/* General purpose Interrupt Enable */
-#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
-#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
-#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
-#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
-#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
-#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
-#define IXGBE_GPIE_EIAME 0x40000000
-#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
-#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
-#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
-#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
-#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
-#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
+#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
+#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
+#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
+#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
+#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
+#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
+#define IXGBE_GPIE_EIAME 0x40000000
+#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
+#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
+#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
+#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
+#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
+#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
+
+/* Packet Buffer Initialization */
+#define IXGBE_MAX_PACKET_BUFFERS 8
+
+#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */
+#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
+#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
+#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
+#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
+#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */
+#define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer */
+#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer */
+
+#define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
+#define IXGBE_MAX_PB 8
+
+/* Packet buffer allocation strategies */
+enum {
+ PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */
+#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
+ PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */
+#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
+};
/* Transmit Flow Control status */
-#define IXGBE_TFCS_TXOFF 0x00000001
-#define IXGBE_TFCS_TXOFF0 0x00000100
-#define IXGBE_TFCS_TXOFF1 0x00000200
-#define IXGBE_TFCS_TXOFF2 0x00000400
-#define IXGBE_TFCS_TXOFF3 0x00000800
-#define IXGBE_TFCS_TXOFF4 0x00001000
-#define IXGBE_TFCS_TXOFF5 0x00002000
-#define IXGBE_TFCS_TXOFF6 0x00004000
-#define IXGBE_TFCS_TXOFF7 0x00008000
+#define IXGBE_TFCS_TXOFF 0x00000001
+#define IXGBE_TFCS_TXOFF0 0x00000100
+#define IXGBE_TFCS_TXOFF1 0x00000200
+#define IXGBE_TFCS_TXOFF2 0x00000400
+#define IXGBE_TFCS_TXOFF3 0x00000800
+#define IXGBE_TFCS_TXOFF4 0x00001000
+#define IXGBE_TFCS_TXOFF5 0x00002000
+#define IXGBE_TFCS_TXOFF6 0x00004000
+#define IXGBE_TFCS_TXOFF7 0x00008000
/* TCP Timer */
-#define IXGBE_TCPTIMER_KS 0x00000100
-#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
-#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
-#define IXGBE_TCPTIMER_LOOP 0x00000800
-#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
+#define IXGBE_TCPTIMER_KS 0x00000100
+#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
+#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
+#define IXGBE_TCPTIMER_LOOP 0x00000800
+#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
/* HLREG0 Bit Masks */
-#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
-#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
-#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
-#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
-#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
-#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
-#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
-#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
-#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
-#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
-#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
-#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
-#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
-#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
-#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
+#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
+#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
+#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
+#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
+#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
+#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
+#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
+#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
+#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
+#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
+#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
+#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
+#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
+#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
+#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
/* VMD_CTL bitmasks */
-#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
-#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
+#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
+#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
/* VT_CTL bitmasks */
-#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
-#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
-#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
-#define IXGBE_VT_CTL_POOL_SHIFT 7
-#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
+#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
+#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
+#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
+#define IXGBE_VT_CTL_POOL_SHIFT 7
+#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
/* VMOLR bitmasks */
-#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
-#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
-#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
-#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
-#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
+#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
+#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
+#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
+#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
+#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
/* VFRE bitmask */
-#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
+#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
-#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
+#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
/* RDHMPN and TDHMPN bitmasks */
-#define IXGBE_RDHMPN_RDICADDR 0x007FF800
-#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
-#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
-#define IXGBE_TDHMPN_TDICADDR 0x003FF800
-#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
-#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
+#define IXGBE_RDHMPN_RDICADDR 0x007FF800
+#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
+#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
+#define IXGBE_TDHMPN_TDICADDR 0x003FF800
+#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
+#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
-#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
-#define IXGBE_RDMAM_DWORD_SHIFT 9
-#define IXGBE_RDMAM_DESC_COMP_FIFO 1
-#define IXGBE_RDMAM_DFC_CMD_FIFO 2
-#define IXGBE_RDMAM_RSC_HEADER_ADDR 3
-#define IXGBE_RDMAM_TCN_STATUS_RAM 4
-#define IXGBE_RDMAM_WB_COLL_FIFO 5
-#define IXGBE_RDMAM_QSC_CNT_RAM 6
-#define IXGBE_RDMAM_QSC_FCOE_RAM 7
-#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
-#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
-#define IXGBE_RDMAM_QSC_RSC_RAM 0xB
-#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
-#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
-#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
-#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
-#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32
-#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4
-#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
-#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
-#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
-#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
-#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
-#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
-#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512
-#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5
-#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
-#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
-#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
-#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
-#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32
-#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8
+#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
+#define IXGBE_RDMAM_DWORD_SHIFT 9
+#define IXGBE_RDMAM_DESC_COMP_FIFO 1
+#define IXGBE_RDMAM_DFC_CMD_FIFO 2
+#define IXGBE_RDMAM_RSC_HEADER_ADDR 3
+#define IXGBE_RDMAM_TCN_STATUS_RAM 4
+#define IXGBE_RDMAM_WB_COLL_FIFO 5
+#define IXGBE_RDMAM_QSC_CNT_RAM 6
+#define IXGBE_RDMAM_QSC_FCOE_RAM 7
+#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
+#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
+#define IXGBE_RDMAM_QSC_RSC_RAM 0xB
+#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
+#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
+#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
+#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
+#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32
+#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4
+#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
+#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
+#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
+#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
+#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
+#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
+#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512
+#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5
+#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
+#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
+#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
+#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
+#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32
+#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8
-#define IXGBE_TXDESCIC_READY 0x80000000
+#define IXGBE_TXDESCIC_READY 0x80000000
/* Receive Checksum Control */
-#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
-#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
+#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
+#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
/* FCRTL Bit Masks */
-#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
-#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
+#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
+#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
/* PAP bit masks*/
-#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
+#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
/* RMCS Bit Masks */
-#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
+#define IXGBE_RMCS_RRM 0x00000002 /* Rx Recycle Mode enable */
/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
-#define IXGBE_RMCS_RAC 0x00000004
-#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
-#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
-#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
-#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
+#define IXGBE_RMCS_RAC 0x00000004
+/* Deficit Fixed Prio ena */
+#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC
+#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
+#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
+#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
/* FCCFG Bit Masks */
-#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
-#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
+#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
+#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
/* Interrupt register bitmasks */
/* Extended Interrupt Cause Read */
-#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
-#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
-#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
-#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
-#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
-#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
-#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
-#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
-#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
-#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
-#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
-#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
-#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
-#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
-#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
-#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
+#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
+#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
+#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
+#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
+#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
+#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
+#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
+#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
+#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */
+#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */
+#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
+#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
+#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
+#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
+#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
+#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
+#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
+#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
/* Extended Interrupt Cause Set */
-#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
-#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
-#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
-#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
-#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
-#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
-#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
-#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
-#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
-#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
-#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
-#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
-#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
-#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
-#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
+#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
+#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
+#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
+#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
+#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
+#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
+#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
+#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
+#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
+#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
+#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
+#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
+#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
+#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
+#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
+#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
/* Extended Interrupt Mask Set */
-#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
-#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
-#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
-#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
-#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
-#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
-#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
-#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
-#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
-#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
-#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
-#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
-#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
-#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
-#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
+#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
+#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
+#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
+#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
+#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
+#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
+#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
+#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */
+#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
+#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
+#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
+#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
+#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
+#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
+#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
+#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
+#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
/* Extended Interrupt Mask Clear */
-#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
-#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
-#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
-#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
-#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
-#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
-#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
-#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
-#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
-#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
-#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
-#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
-#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
-#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
-#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
+#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
+#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
+#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
+#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
+#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
+#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
+#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
+#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
+#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
+#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
+#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
+#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
+#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
+#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
+#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
+#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
#define IXGBE_EIMS_ENABLE_MASK ( \
- IXGBE_EIMS_RTX_QUEUE | \
- IXGBE_EIMS_LSC | \
- IXGBE_EIMS_TCP_TIMER | \
- IXGBE_EIMS_OTHER)
+ IXGBE_EIMS_RTX_QUEUE | \
+ IXGBE_EIMS_LSC | \
+ IXGBE_EIMS_TCP_TIMER | \
+ IXGBE_EIMS_OTHER)
/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
-#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
-#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
-#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
-#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
-#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
-#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
-#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
-#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
-#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
-#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
-#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
-#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
-#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
-#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
-#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
-#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
-#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
-#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */
-#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
-#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
-#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
-#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
-#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
+#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
+#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
+#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
+#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
+#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
+#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
+#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
+#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
+#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
+#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
+#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
+#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
+#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
+#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
+#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
+#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
+#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
+#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass chk of ctrl bits */
+#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
+#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
+#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
+#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
+#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
-#define IXGBE_MAX_FTQF_FILTERS 128
-#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
-#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
-#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
-#define IXGBE_FTQF_PROTOCOL_SCTP 2
-#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
-#define IXGBE_FTQF_PRIORITY_SHIFT 2
-#define IXGBE_FTQF_POOL_MASK 0x0000003F
-#define IXGBE_FTQF_POOL_SHIFT 8
-#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
-#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
-#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
-#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
-#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
-#define IXGBE_FTQF_DEST_PORT_MASK 0x17
-#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
-#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
-#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
+#define IXGBE_MAX_FTQF_FILTERS 128
+#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
+#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
+#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
+#define IXGBE_FTQF_PROTOCOL_SCTP 2
+#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
+#define IXGBE_FTQF_PRIORITY_SHIFT 2
+#define IXGBE_FTQF_POOL_MASK 0x0000003F
+#define IXGBE_FTQF_POOL_SHIFT 8
+#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
+#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
+#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
+#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
+#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
+#define IXGBE_FTQF_DEST_PORT_MASK 0x17
+#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
+#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
+#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
/* Interrupt clear mask */
-#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
+#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
/* Interrupt Vector Allocation Registers */
-#define IXGBE_IVAR_REG_NUM 25
-#define IXGBE_IVAR_REG_NUM_82599 64
-#define IXGBE_IVAR_TXRX_ENTRY 96
-#define IXGBE_IVAR_RX_ENTRY 64
-#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
-#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
-#define IXGBE_IVAR_TX_ENTRY 32
+#define IXGBE_IVAR_REG_NUM 25
+#define IXGBE_IVAR_REG_NUM_82599 64
+#define IXGBE_IVAR_TXRX_ENTRY 96
+#define IXGBE_IVAR_RX_ENTRY 64
+#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
+#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
+#define IXGBE_IVAR_TX_ENTRY 32
-#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
-#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
+#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
+#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
-#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
+#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
-#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
+#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
/* ETYPE Queue Filter/Select Bit Masks */
-#define IXGBE_MAX_ETQF_FILTERS 8
-#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
-#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
-#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
-#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
-#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
+#define IXGBE_MAX_ETQF_FILTERS 8
+#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
+#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
+#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
+#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
+#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
+#define IXGBE_ETQF_POOL_SHIFT 20
-#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
-#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
-#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
-#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
+#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
+#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
+#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
+#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
/*
* ETQF filter list: one static filter per filter consumer. This is
- * to avoid filter collisions later. Add new filters
- * here!!
+ * to avoid filter collisions later. Add new filters
+ * here!!
*
* Current filters:
- * EAPOL 802.1x (0x888e): Filter 0
- * FCoE (0x8906): Filter 2
- * 1588 (0x88f7): Filter 3
- * FIP (0x8914): Filter 4
+ * EAPOL 802.1x (0x888e): Filter 0
+ * FCoE (0x8906): Filter 2
+ * 1588 (0x88f7): Filter 3
+ * FIP (0x8914): Filter 4
*/
-#define IXGBE_ETQF_FILTER_EAPOL 0
-#define IXGBE_ETQF_FILTER_FCOE 2
-#define IXGBE_ETQF_FILTER_1588 3
-#define IXGBE_ETQF_FILTER_FIP 4
+#define IXGBE_ETQF_FILTER_EAPOL 0
+#define IXGBE_ETQF_FILTER_FCOE 2
+#define IXGBE_ETQF_FILTER_1588 3
+#define IXGBE_ETQF_FILTER_FIP 4
/* VLAN Control Bit Masks */
-#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
-#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
-#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
-#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
-#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
+#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
+#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
+#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
+#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
+#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
/* VLAN pool filtering masks */
-#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
-#define IXGBE_VLVF_ENTRIES 64
-#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
+#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
+#define IXGBE_VLVF_ENTRIES 64
+#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
/* Per VF Port VLAN insertion rules */
-#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
-#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
+#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
+#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
-#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
+#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
/* STATUS Bit Masks */
-#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
-#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
-#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
+#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
+#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
+#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Ena Status */
-#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
-#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
+#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
+#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
/* ESDP Bit Masks */
-#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
-#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
-#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
-#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
-#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
-#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
-#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
-#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
-#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
+#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
+#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
+#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
+#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
+#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
+#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
+#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
+#define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */
+#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */
+#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */
+#define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */
+#define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */
+#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
+#define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */
+#define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */
+#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */
+#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */
+
/* LEDCTL Bit Masks */
-#define IXGBE_LED_IVRT_BASE 0x00000040
-#define IXGBE_LED_BLINK_BASE 0x00000080
-#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
-#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
-#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
-#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
-#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
-#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
+#define IXGBE_LED_IVRT_BASE 0x00000040
+#define IXGBE_LED_BLINK_BASE 0x00000080
+#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
+#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
+#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
+#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
+#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
+#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
/* LED modes */
-#define IXGBE_LED_LINK_UP 0x0
-#define IXGBE_LED_LINK_10G 0x1
-#define IXGBE_LED_MAC 0x2
-#define IXGBE_LED_FILTER 0x3
-#define IXGBE_LED_LINK_ACTIVE 0x4
-#define IXGBE_LED_LINK_1G 0x5
-#define IXGBE_LED_ON 0xE
-#define IXGBE_LED_OFF 0xF
+#define IXGBE_LED_LINK_UP 0x0
+#define IXGBE_LED_LINK_10G 0x1
+#define IXGBE_LED_MAC 0x2
+#define IXGBE_LED_FILTER 0x3
+#define IXGBE_LED_LINK_ACTIVE 0x4
+#define IXGBE_LED_LINK_1G 0x5
+#define IXGBE_LED_ON 0xE
+#define IXGBE_LED_OFF 0xF
/* AUTOC Bit Masks */
#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
-#define IXGBE_AUTOC_KX4_SUPP 0x80000000
-#define IXGBE_AUTOC_KX_SUPP 0x40000000
-#define IXGBE_AUTOC_PAUSE 0x30000000
-#define IXGBE_AUTOC_ASM_PAUSE 0x20000000
-#define IXGBE_AUTOC_SYM_PAUSE 0x10000000
-#define IXGBE_AUTOC_RF 0x08000000
-#define IXGBE_AUTOC_PD_TMR 0x06000000
-#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
-#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
-#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
-#define IXGBE_AUTOC_FECA 0x00040000
-#define IXGBE_AUTOC_FECR 0x00020000
-#define IXGBE_AUTOC_KR_SUPP 0x00010000
-#define IXGBE_AUTOC_AN_RESTART 0x00001000
-#define IXGBE_AUTOC_FLU 0x00000001
-#define IXGBE_AUTOC_LMS_SHIFT 13
-#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
-#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_KX4_SUPP 0x80000000
+#define IXGBE_AUTOC_KX_SUPP 0x40000000
+#define IXGBE_AUTOC_PAUSE 0x30000000
+#define IXGBE_AUTOC_ASM_PAUSE 0x20000000
+#define IXGBE_AUTOC_SYM_PAUSE 0x10000000
+#define IXGBE_AUTOC_RF 0x08000000
+#define IXGBE_AUTOC_PD_TMR 0x06000000
+#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
+#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
+#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
+#define IXGBE_AUTOC_FECA 0x00040000
+#define IXGBE_AUTOC_FECR 0x00020000
+#define IXGBE_AUTOC_KR_SUPP 0x00010000
+#define IXGBE_AUTOC_AN_RESTART 0x00001000
+#define IXGBE_AUTOC_FLU 0x00000001
+#define IXGBE_AUTOC_LMS_SHIFT 13
+#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
-#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
-#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
-#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
-#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
-#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
-#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
-#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
-#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
-#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
-#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
-#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
+#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
+#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
+#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
+#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
-#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
-#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
-#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
-#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
-#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
-#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
+#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
+#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
+#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
+#define IXGBE_MACC_FLU 0x00000001
+#define IXGBE_MACC_FSV_10G 0x00030000
+#define IXGBE_MACC_FS 0x00040000
+#define IXGBE_MAC_RX2TX_LPBK 0x00000002
/* LINKS Bit Masks */
-#define IXGBE_LINKS_KX_AN_COMP 0x80000000
-#define IXGBE_LINKS_UP 0x40000000
-#define IXGBE_LINKS_SPEED 0x20000000
-#define IXGBE_LINKS_MODE 0x18000000
-#define IXGBE_LINKS_RX_MODE 0x06000000
-#define IXGBE_LINKS_TX_MODE 0x01800000
-#define IXGBE_LINKS_XGXS_EN 0x00400000
-#define IXGBE_LINKS_SGMII_EN 0x02000000
-#define IXGBE_LINKS_PCS_1G_EN 0x00200000
-#define IXGBE_LINKS_1G_AN_EN 0x00100000
-#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
-#define IXGBE_LINKS_1G_SYNC 0x00040000
-#define IXGBE_LINKS_10G_ALIGN 0x00020000
-#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
-#define IXGBE_LINKS_TL_FAULT 0x00001000
-#define IXGBE_LINKS_SIGNAL 0x00000F00
+#define IXGBE_LINKS_KX_AN_COMP 0x80000000
+#define IXGBE_LINKS_UP 0x40000000
+#define IXGBE_LINKS_SPEED 0x20000000
+#define IXGBE_LINKS_MODE 0x18000000
+#define IXGBE_LINKS_RX_MODE 0x06000000
+#define IXGBE_LINKS_TX_MODE 0x01800000
+#define IXGBE_LINKS_XGXS_EN 0x00400000
+#define IXGBE_LINKS_SGMII_EN 0x02000000
+#define IXGBE_LINKS_PCS_1G_EN 0x00200000
+#define IXGBE_LINKS_1G_AN_EN 0x00100000
+#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
+#define IXGBE_LINKS_1G_SYNC 0x00040000
+#define IXGBE_LINKS_10G_ALIGN 0x00020000
+#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
+#define IXGBE_LINKS_TL_FAULT 0x00001000
+#define IXGBE_LINKS_SIGNAL 0x00000F00
-#define IXGBE_LINKS_SPEED_82599 0x30000000
-#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
-#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
-#define IXGBE_LINKS_SPEED_100_82599 0x10000000
-#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
-#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
+#define IXGBE_LINKS_SPEED_82599 0x30000000
+#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
+#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
+#define IXGBE_LINKS_SPEED_100_82599 0x10000000
+#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
+#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
-#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
+#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
/* PCS1GLSTA Bit Masks */
-#define IXGBE_PCS1GLSTA_LINK_OK 1
-#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
-#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
-#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
-#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
-#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
-#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
+#define IXGBE_PCS1GLSTA_LINK_OK 1
+#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
+#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
+#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
+#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
+#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
+#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
-#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
-#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
+#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
+#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
/* PCS1GLCTL Bit Masks */
-#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
-#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
-#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
-#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
-#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
-#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
+#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
+#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
+#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
+#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
+#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
+#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
/* ANLP1 Bit Masks */
-#define IXGBE_ANLP1_PAUSE 0x0C00
-#define IXGBE_ANLP1_SYM_PAUSE 0x0400
-#define IXGBE_ANLP1_ASM_PAUSE 0x0800
-#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
+#define IXGBE_ANLP1_PAUSE 0x0C00
+#define IXGBE_ANLP1_SYM_PAUSE 0x0400
+#define IXGBE_ANLP1_ASM_PAUSE 0x0800
+#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
/* SW Semaphore Register bitmasks */
-#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
-#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
-#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
-#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
+#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
+#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
+#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
+#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
/* SW_FW_SYNC/GSSR definitions */
-#define IXGBE_GSSR_EEP_SM 0x0001
-#define IXGBE_GSSR_PHY0_SM 0x0002
-#define IXGBE_GSSR_PHY1_SM 0x0004
-#define IXGBE_GSSR_MAC_CSR_SM 0x0008
-#define IXGBE_GSSR_FLASH_SM 0x0010
+#define IXGBE_GSSR_EEP_SM 0x0001
+#define IXGBE_GSSR_PHY0_SM 0x0002
+#define IXGBE_GSSR_PHY1_SM 0x0004
+#define IXGBE_GSSR_MAC_CSR_SM 0x0008
+#define IXGBE_GSSR_FLASH_SM 0x0010
+#define IXGBE_GSSR_SW_MNG_SM 0x0400
+
+/* FW Status register bitmask */
+#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
/* EEC Register */
-#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
-#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
-#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
-#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
-#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
-#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
-#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
-#define IXGBE_EEC_FWE_SHIFT 4
-#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
-#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
-#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
-#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
-#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
-#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
-#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
+#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
+#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
+#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
+#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
+#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
+#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
+#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
+#define IXGBE_EEC_FWE_SHIFT 4
+#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
+#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
+#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
+#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
+#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
+#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
+#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
/* EEPROM Addressing bits based on type (0-small, 1-large) */
-#define IXGBE_EEC_ADDR_SIZE 0x00000400
-#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
+#define IXGBE_EEC_ADDR_SIZE 0x00000400
+#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
+#define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */
-#define IXGBE_EEC_SIZE_SHIFT 11
-#define IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT 6
-#define IXGBE_EEPROM_OPCODE_BITS 8
+#define IXGBE_EEC_SIZE_SHIFT 11
+#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
+#define IXGBE_EEPROM_OPCODE_BITS 8
/* Part Number String Length */
-#define IXGBE_PBANUM_LENGTH 11
+#define IXGBE_PBANUM_LENGTH 11
/* Checksum and EEPROM pointers */
-#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
-#define IXGBE_EEPROM_CHECKSUM 0x3F
-#define IXGBE_EEPROM_SUM 0xBABA
-#define IXGBE_PCIE_ANALOG_PTR 0x03
-#define IXGBE_ATLAS0_CONFIG_PTR 0x04
-#define IXGBE_PHY_PTR 0x04
-#define IXGBE_ATLAS1_CONFIG_PTR 0x05
-#define IXGBE_OPTION_ROM_PTR 0x05
-#define IXGBE_PCIE_GENERAL_PTR 0x06
-#define IXGBE_PCIE_CONFIG0_PTR 0x07
-#define IXGBE_PCIE_CONFIG1_PTR 0x08
-#define IXGBE_CORE0_PTR 0x09
-#define IXGBE_CORE1_PTR 0x0A
-#define IXGBE_MAC0_PTR 0x0B
-#define IXGBE_MAC1_PTR 0x0C
-#define IXGBE_CSR0_CONFIG_PTR 0x0D
-#define IXGBE_CSR1_CONFIG_PTR 0x0E
-#define IXGBE_FW_PTR 0x0F
-#define IXGBE_PBANUM0_PTR 0x15
-#define IXGBE_PBANUM1_PTR 0x16
-#define IXGBE_SAN_MAC_ADDR_PTR 0x28
-#define IXGBE_DEVICE_CAPS 0x2C
-#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
-#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
-#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
+#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
+#define IXGBE_EEPROM_CHECKSUM 0x3F
+#define IXGBE_EEPROM_SUM 0xBABA
+#define IXGBE_PCIE_ANALOG_PTR 0x03
+#define IXGBE_ATLAS0_CONFIG_PTR 0x04
+#define IXGBE_PHY_PTR 0x04
+#define IXGBE_ATLAS1_CONFIG_PTR 0x05
+#define IXGBE_OPTION_ROM_PTR 0x05
+#define IXGBE_PCIE_GENERAL_PTR 0x06
+#define IXGBE_PCIE_CONFIG0_PTR 0x07
+#define IXGBE_PCIE_CONFIG1_PTR 0x08
+#define IXGBE_CORE0_PTR 0x09
+#define IXGBE_CORE1_PTR 0x0A
+#define IXGBE_MAC0_PTR 0x0B
+#define IXGBE_MAC1_PTR 0x0C
+#define IXGBE_CSR0_CONFIG_PTR 0x0D
+#define IXGBE_CSR1_CONFIG_PTR 0x0E
+#define IXGBE_FW_PTR 0x0F
+#define IXGBE_PBANUM0_PTR 0x15
+#define IXGBE_PBANUM1_PTR 0x16
+#define IXGBE_ALT_MAC_ADDR_PTR 0x37
+#define IXGBE_FREE_SPACE_PTR 0X3E
+
+#define IXGBE_SAN_MAC_ADDR_PTR 0x28
+#define IXGBE_DEVICE_CAPS 0x2C
+#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
+#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
+#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
+#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
+#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
/* MSI-X capability fields masks */
-#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
+#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
/* Legacy EEPROM word offsets */
-#define IXGBE_ISCSI_BOOT_CAPS 0x0033
-#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
-#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
+#define IXGBE_ISCSI_BOOT_CAPS 0x0033
+#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
+#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
/* EEPROM Commands - SPI */
-#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
-#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
-#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
-#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
-#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
-#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
+#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
+#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
+#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
+#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
+#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
+#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
/* EEPROM reset Write Enable latch */
-#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
-#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
-#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
-#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
-#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
-#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
+#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
+#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
+#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
+#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
+#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
+#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
/* EEPROM Read Register */
-#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */
-#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */
-#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
-#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
-#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
-#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */
+#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */
+#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */
+#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
+#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
+#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */
+#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */
-#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
+#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
+
+#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
+#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* words rd in burst */
+#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */
#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
-#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
+#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */
#endif
/* Number of 5 microseconds we wait for EERD read and
* EERW write to complete */
-#define IXGBE_EERD_EEWR_ATTEMPTS 100000
+#define IXGBE_EERD_EEWR_ATTEMPTS 100000
/* # attempts we wait for flush update to complete */
-#define IXGBE_FLUDONE_ATTEMPTS 20000
+#define IXGBE_FLUDONE_ATTEMPTS 20000
-#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */
-#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
-#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
-#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
+#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */
+#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
+#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
+#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
-#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
-#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
-#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
-#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
-#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
-#define IXGBE_FW_LESM_STATE_1 0x1
-#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
-#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
-#define IXGBE_FW_PATCH_VERSION_4 0x7
-#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
-#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
-#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
-#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */
-#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */
-#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
-#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
-#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
-#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
-#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
-#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
-#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
-#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
+#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
+#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
+#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
+#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
+#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
+#define IXGBE_FW_LESM_STATE_1 0x1
+#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
+#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
+#define IXGBE_FW_PATCH_VERSION_4 0x7
+#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
+#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
+#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
+#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */
+#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */
+#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
+#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */
+#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */
+#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */
+#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */
+#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */
+#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */
+#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */
+
+#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */
+#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */
+#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */
/* PCI Bus Info */
-#define IXGBE_PCI_DEVICE_STATUS 0xAA
-#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
-#define IXGBE_PCI_LINK_STATUS 0xB2
-#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
-#define IXGBE_PCI_LINK_WIDTH 0x3F0
-#define IXGBE_PCI_LINK_WIDTH_1 0x10
-#define IXGBE_PCI_LINK_WIDTH_2 0x20
-#define IXGBE_PCI_LINK_WIDTH_4 0x40
-#define IXGBE_PCI_LINK_WIDTH_8 0x80
-#define IXGBE_PCI_LINK_SPEED 0xF
-#define IXGBE_PCI_LINK_SPEED_2500 0x1
-#define IXGBE_PCI_LINK_SPEED_5000 0x2
-#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
-#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
-#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
+#define IXGBE_PCI_DEVICE_STATUS 0xAA
+#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
+#define IXGBE_PCI_LINK_STATUS 0xB2
+#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
+#define IXGBE_PCI_LINK_WIDTH 0x3F0
+#define IXGBE_PCI_LINK_WIDTH_1 0x10
+#define IXGBE_PCI_LINK_WIDTH_2 0x20
+#define IXGBE_PCI_LINK_WIDTH_4 0x40
+#define IXGBE_PCI_LINK_WIDTH_8 0x80
+#define IXGBE_PCI_LINK_SPEED 0xF
+#define IXGBE_PCI_LINK_SPEED_2500 0x1
+#define IXGBE_PCI_LINK_SPEED_5000 0x2
+#define IXGBE_PCI_LINK_SPEED_8000 0x3
+#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
+#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
+#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
/* Number of 100 microseconds we wait for PCI Express master disable */
-#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
+#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
-/* Check whether address is multicast. This is little-endian specific check.*/
+/* Check whether address is multicast. This is little-endian specific check.*/
#define IXGBE_IS_MULTICAST(Address) \
- (bool)(((u8 *)(Address))[0] & ((u8)0x01))
+ (bool)(((u8 *)(Address))[0] & ((u8)0x01))
/* Check whether an address is broadcast. */
-#define IXGBE_IS_BROADCAST(Address) \
- ((((u8 *)(Address))[0] == ((u8)0xff)) && \
- (((u8 *)(Address))[1] == ((u8)0xff)))
+#define IXGBE_IS_BROADCAST(Address) \
+ ((((u8 *)(Address))[0] == ((u8)0xff)) && \
+ (((u8 *)(Address))[1] == ((u8)0xff)))
/* RAH */
-#define IXGBE_RAH_VIND_MASK 0x003C0000
-#define IXGBE_RAH_VIND_SHIFT 18
-#define IXGBE_RAH_AV 0x80000000
-#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
+#define IXGBE_RAH_VIND_MASK 0x003C0000
+#define IXGBE_RAH_VIND_SHIFT 18
+#define IXGBE_RAH_AV 0x80000000
+#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
/* Header split receive */
-#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
-#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
-#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
-#define IXGBE_RFCTL_NFSW_DIS 0x00000040
-#define IXGBE_RFCTL_NFSR_DIS 0x00000080
-#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
-#define IXGBE_RFCTL_NFS_VER_SHIFT 8
-#define IXGBE_RFCTL_NFS_VER_2 0
-#define IXGBE_RFCTL_NFS_VER_3 1
-#define IXGBE_RFCTL_NFS_VER_4 2
-#define IXGBE_RFCTL_IPV6_DIS 0x00000400
-#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
-#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
-#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
-#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
+#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
+#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
+#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
+#define IXGBE_RFCTL_RSC_DIS 0x00000010
+#define IXGBE_RFCTL_NFSW_DIS 0x00000040
+#define IXGBE_RFCTL_NFSR_DIS 0x00000080
+#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
+#define IXGBE_RFCTL_NFS_VER_SHIFT 8
+#define IXGBE_RFCTL_NFS_VER_2 0
+#define IXGBE_RFCTL_NFS_VER_3 1
+#define IXGBE_RFCTL_NFS_VER_4 2
+#define IXGBE_RFCTL_IPV6_DIS 0x00000400
+#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
+#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
+#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
+#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
/* Transmit Config masks */
-#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
-#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
-#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
+#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */
+#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */
+#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
/* Enable short packet padding to 64 bytes */
-#define IXGBE_TX_PAD_ENABLE 0x00000400
-#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
+#define IXGBE_TX_PAD_ENABLE 0x00000400
+#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
/* This allows for 16K packets + 4k for vlan */
-#define IXGBE_MAX_FRAME_SZ 0x40040000
+#define IXGBE_MAX_FRAME_SZ 0x40040000
-#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
-#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
+#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
+#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
/* Receive Config masks */
-#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
-#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
-#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
-#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
+#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
+#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */
+#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */
+#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */
+#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */
+#define IXGBE_RXDCTL_RLPML_EN 0x00008000
+#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
+
+#define IXGBE_TSAUXC_EN_CLK 0x00000004
+#define IXGBE_TSAUXC_SYNCLK 0x00000008
+#define IXGBE_TSAUXC_SDP0_INT 0x00000040
+
+#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
+#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */
+
+#define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
+#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
+#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
+#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
+#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
+#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
+#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */
-#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
-#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
-#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
-#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
-#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
-#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
+#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF
+#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00
+#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01
+#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02
+#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03
+#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04
+
+#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00
+#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000
+#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100
+#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200
+#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
+#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800
+#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900
+#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
+#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00
+#define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00
+#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00
+
+#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
+#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
+#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
+#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
+#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
+#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
/* Receive Priority Flow Control Enable */
-#define IXGBE_FCTRL_RPFCE 0x00004000
-#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
-#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
-#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
-#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
-#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
+#define IXGBE_FCTRL_RPFCE 0x00004000
+#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
+#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
+#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
+#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
+#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
+#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */
+#define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */
/* Multiple Receive Queue Control */
-#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
-#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
-#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
-#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
-#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
-#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
-#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
-#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
-#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
-#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
-#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
-#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
-#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
-#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
+#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
+#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
+#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
+#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
+#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
+#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
+#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
+#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
+#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
+#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
+#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
+#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
+#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
+#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
-#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
-#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
-#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
-#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
-#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
+#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
+#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
+#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
+#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
+#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
-#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
+#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
/* Queue Drop Enable */
-#define IXGBE_QDE_ENABLE 0x00000001
-#define IXGBE_QDE_IDX_MASK 0x00007F00
-#define IXGBE_QDE_IDX_SHIFT 8
-
-#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
-#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
-#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
-#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
-#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
-#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
-#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
-#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
-#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
+#define IXGBE_QDE_ENABLE 0x00000001
+#define IXGBE_QDE_IDX_MASK 0x00007F00
+#define IXGBE_QDE_IDX_SHIFT 8
+#define IXGBE_QDE_WRITE 0x00010000
+#define IXGBE_QDE_READ 0x00020000
-#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
-#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
-#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
-#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
-#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
+#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
+#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
+#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
+#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
+#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
+#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
+#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
+#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
+#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
+
+#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
+#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
+#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
+#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
+#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
/* Multiple Transmit Queue Command Register */
-#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
-#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
-#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
-#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
-#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
-#define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */
-#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
+#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
+#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
+#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
+#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
+#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
+#define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */
+#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
/* Receive Descriptor bit definitions */
-#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
-#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
-#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
-#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
-#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
-#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
-#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
-#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
-#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
-#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
-#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
-#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
-#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
-#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
-#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
-#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
-#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
-#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
-#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
-#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
-#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
-#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
-#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
-#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
-#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
-#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
-#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
-#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
-#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */
-#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
-#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */
-#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */
-#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */
-#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
-#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
-#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
-#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
-#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
-#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
-#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
-#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
-#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
-#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
-#define IXGBE_RXD_PRI_SHIFT 13
-#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
-#define IXGBE_RXD_CFI_SHIFT 12
+#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
+#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
+#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
+#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
+#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
+#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
+#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
+#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
+#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
+#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
+#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
+#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
+#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
+#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
+#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
+#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
+#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
+#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
+#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
+#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
+#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
+#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
+#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
+#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
+#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
+#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
+#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
+#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
+#define IXGBE_RXDADV_ERR_RXE 0x20000000 /* Any MAC Error */
+#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */
+#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
+#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */
+#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */
+#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */
+#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
+#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
+#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
+#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
+#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
+#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
+#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
+#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
+#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
+#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
+#define IXGBE_RXD_PRI_SHIFT 13
+#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
+#define IXGBE_RXD_CFI_SHIFT 12
-#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
-#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
-#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
-#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
-#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
-#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
-#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
-#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
-#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
-#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
-#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
+#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
+#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
+#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
+#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
+#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
+#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
+#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
+#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
+#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
+#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
+#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
+#define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE1588 Time Stamp */
/* PSRTYPE bit definitions */
-#define IXGBE_PSRTYPE_TCPHDR 0x00000010
-#define IXGBE_PSRTYPE_UDPHDR 0x00000020
-#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
-#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
-#define IXGBE_PSRTYPE_L2HDR 0x00001000
+#define IXGBE_PSRTYPE_TCPHDR 0x00000010
+#define IXGBE_PSRTYPE_UDPHDR 0x00000020
+#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
+#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
+#define IXGBE_PSRTYPE_L2HDR 0x00001000
/* SRRCTL bit definitions */
-#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
-#define IXGBE_SRRCTL_RDMTS_SHIFT 22
-#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
-#define IXGBE_SRRCTL_DROP_EN 0x10000000
-#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
-#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
-#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
+#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
+#define IXGBE_SRRCTL_RDMTS_SHIFT 22
+#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
+#define IXGBE_SRRCTL_DROP_EN 0x10000000
+#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
+#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
+#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
-#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
+#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
-#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
+#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
-#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
-#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
+#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
+#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
-#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
-#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
-#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
-#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
-#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
-#define IXGBE_RXDADV_RSCCNT_SHIFT 17
-#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
-#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
-#define IXGBE_RXDADV_SPH 0x8000
+#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
+#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
+#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
+#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
+#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
+#define IXGBE_RXDADV_RSCCNT_SHIFT 17
+#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
+#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
+#define IXGBE_RXDADV_SPH 0x8000
/* RSS Hash results */
-#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
-#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
-#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
-#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
-#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
-#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
+#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
+#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
+#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
+#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
+#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
+#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
-#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
-#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
+#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
+#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
/* RSS Packet Types as indicated in the receive descriptor. */
-#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
-#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
-#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
-#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
-#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
-#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
-#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
-#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
-#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
-#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
-#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
-#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
-#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
-#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
-#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
+#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
+#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
+#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
+#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
+#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
+#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
+#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
+#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
+#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
+#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
+#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
+#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
+#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
+#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
+#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
/* Security Processing bit Indication */
-#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
-#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
-#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
-#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
-#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
+#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
+#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
+#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
+#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
+#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
/* Masks to determine if packets should be dropped due to frame errors */
#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
- IXGBE_RXD_ERR_CE | \
- IXGBE_RXD_ERR_LE | \
- IXGBE_RXD_ERR_PE | \
- IXGBE_RXD_ERR_OSE | \
- IXGBE_RXD_ERR_USE)
+ IXGBE_RXD_ERR_CE | \
+ IXGBE_RXD_ERR_LE | \
+ IXGBE_RXD_ERR_PE | \
+ IXGBE_RXD_ERR_OSE | \
+ IXGBE_RXD_ERR_USE)
#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
- IXGBE_RXDADV_ERR_CE | \
- IXGBE_RXDADV_ERR_LE | \
- IXGBE_RXDADV_ERR_PE | \
- IXGBE_RXDADV_ERR_OSE | \
- IXGBE_RXDADV_ERR_USE)
+ IXGBE_RXDADV_ERR_CE | \
+ IXGBE_RXDADV_ERR_LE | \
+ IXGBE_RXDADV_ERR_PE | \
+ IXGBE_RXDADV_ERR_OSE | \
+ IXGBE_RXDADV_ERR_USE)
+
+#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599 IXGBE_RXDADV_ERR_RXE
/* Multicast bit mask */
-#define IXGBE_MCSTCTRL_MFE 0x4
+#define IXGBE_MCSTCTRL_MFE 0x4
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
-#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
-#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
-#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
+#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
+#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
+#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
/* Vlan-specific macros */
-#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
-#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
-#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
-#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
+#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
+#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
+#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
+#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
/* SR-IOV specific macros */
-#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
-#define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4))
-#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
-#define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))
+#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
+#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4))
+#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
+#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4))
/* Little Endian defines */
#ifndef __le16
@@ -2034,97 +2253,138 @@
#endif
enum ixgbe_fdir_pballoc_type {
- IXGBE_FDIR_PBALLOC_64K = 0,
- IXGBE_FDIR_PBALLOC_128K,
- IXGBE_FDIR_PBALLOC_256K,
+ IXGBE_FDIR_PBALLOC_NONE = 0,
+ IXGBE_FDIR_PBALLOC_64K = 1,
+ IXGBE_FDIR_PBALLOC_128K = 2,
+ IXGBE_FDIR_PBALLOC_256K = 3,
};
-#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16
/* Flow Director register values */
-#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
-#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
-#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
-#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
-#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
-#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
-#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
-#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
-#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
-#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
-#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
-#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
-#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
+#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
+#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
+#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
+#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
+#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
+#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
+#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
+#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
+#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
+#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
+#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
+#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
+#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
-#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
-#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
-#define IXGBE_FDIRIP6M_DIPM_SHIFT 16
-#define IXGBE_FDIRM_VLANID 0x00000001
-#define IXGBE_FDIRM_VLANP 0x00000002
-#define IXGBE_FDIRM_POOL 0x00000004
-#define IXGBE_FDIRM_L4P 0x00000008
-#define IXGBE_FDIRM_FLEX 0x00000010
-#define IXGBE_FDIRM_DIPv6 0x00000020
+#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
+#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
+#define IXGBE_FDIRIP6M_DIPM_SHIFT 16
+#define IXGBE_FDIRM_VLANID 0x00000001
+#define IXGBE_FDIRM_VLANP 0x00000002
+#define IXGBE_FDIRM_POOL 0x00000004
+#define IXGBE_FDIRM_L4P 0x00000008
+#define IXGBE_FDIRM_FLEX 0x00000010
+#define IXGBE_FDIRM_DIPv6 0x00000020
+
+#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
+#define IXGBE_FDIRFREE_FREE_SHIFT 0
+#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
+#define IXGBE_FDIRFREE_COLL_SHIFT 16
+#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
+#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
+#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
+#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
+#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
+#define IXGBE_FDIRUSTAT_ADD_SHIFT 0
+#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
+#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
+#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
+#define IXGBE_FDIRFSTAT_FADD_SHIFT 0
+#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
+#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
+#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
+#define IXGBE_FDIRVLAN_FLEX_SHIFT 16
+#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
+#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
-#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
-#define IXGBE_FDIRFREE_FREE_SHIFT 0
-#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
-#define IXGBE_FDIRFREE_COLL_SHIFT 16
-#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
-#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
-#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
-#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
-#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
-#define IXGBE_FDIRUSTAT_ADD_SHIFT 0
-#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
-#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
-#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
-#define IXGBE_FDIRFSTAT_FADD_SHIFT 0
-#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
-#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
-#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
-#define IXGBE_FDIRVLAN_FLEX_SHIFT 16
-#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
-#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
+#define IXGBE_FDIRCMD_CMD_MASK 0x00000003
+#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
+#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
+#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
+#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004
+#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
+#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
+#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
+#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
+#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
+#define IXGBE_FDIRCMD_IPV6 0x00000080
+#define IXGBE_FDIRCMD_CLEARHT 0x00000100
+#define IXGBE_FDIRCMD_DROP 0x00000200
+#define IXGBE_FDIRCMD_INT 0x00000400
+#define IXGBE_FDIRCMD_LAST 0x00000800
+#define IXGBE_FDIRCMD_COLLISION 0x00001000
+#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
+#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
+#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
+#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
+#define IXGBE_FDIR_INIT_DONE_POLL 10
+#define IXGBE_FDIRCMD_CMD_POLL 10
+
+#define IXGBE_FDIR_DROP_QUEUE 127
+
+#define IXGBE_STATUS_OVERHEATING_BIT 20 /* STATUS overtemp bit num */
+
+/* Manageablility Host Interface defines */
+#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
+#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
+#define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */
-#define IXGBE_FDIRCMD_CMD_MASK 0x00000003
-#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
-#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
-#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
-#define IXGBE_FDIRCMD_CMD_QUERY_REM_HASH 0x00000007
-#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
-#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
-#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
-#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
-#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
-#define IXGBE_FDIRCMD_IPV6 0x00000080
-#define IXGBE_FDIRCMD_CLEARHT 0x00000100
-#define IXGBE_FDIRCMD_DROP 0x00000200
-#define IXGBE_FDIRCMD_INT 0x00000400
-#define IXGBE_FDIRCMD_LAST 0x00000800
-#define IXGBE_FDIRCMD_COLLISION 0x00001000
-#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
-#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
-#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
-#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
-#define IXGBE_FDIR_INIT_DONE_POLL 10
-#define IXGBE_FDIRCMD_CMD_POLL 10
+/* CEM Support */
+#define FW_CEM_HDR_LEN 0x4
+#define FW_CEM_CMD_DRIVER_INFO 0xDD
+#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
+#define FW_CEM_CMD_RESERVED 0X0
+#define FW_CEM_UNUSED_VER 0x0
+#define FW_CEM_MAX_RETRIES 3
+#define FW_CEM_RESP_STATUS_SUCCESS 0x1
+
+/* Host Interface Command Structures */
+
+struct ixgbe_hic_hdr {
+ u8 cmd;
+ u8 buf_len;
+ union {
+ u8 cmd_resv;
+ u8 ret_status;
+ } cmd_or_resp;
+ u8 checksum;
+};
+
+struct ixgbe_hic_drv_info {
+ struct ixgbe_hic_hdr hdr;
+ u8 port_num;
+ u8 ver_sub;
+ u8 ver_build;
+ u8 ver_min;
+ u8 ver_maj;
+ u8 pad; /* end spacing to ensure length is mult. of dword */
+ u16 pad2; /* end spacing to ensure length is mult. of dword2 */
+};
/* Transmit Descriptor - Legacy */
struct ixgbe_legacy_tx_desc {
- u64 buffer_addr; /* Address of the descriptor's data buffer */
+ u64 buffer_addr; /* Address of the descriptor's data buffer */
union {
__le32 data;
struct {
- __le16 length; /* Data buffer length */
- u8 cso; /* Checksum offset */
- u8 cmd; /* Descriptor control */
+ __le16 length; /* Data buffer length */
+ u8 cso; /* Checksum offset */
+ u8 cmd; /* Descriptor control */
} flags;
} lower;
union {
__le32 data;
struct {
- u8 status; /* Descriptor status */
- u8 css; /* Checksum start */
+ u8 status; /* Descriptor status */
+ u8 css; /* Checksum start */
__le16 vlan;
} fields;
} upper;
@@ -2133,12 +2393,12 @@
/* Transmit Descriptor - Advanced */
union ixgbe_adv_tx_desc {
struct {
- __le64 buffer_addr; /* Address of descriptor's data buf */
+ __le64 buffer_addr; /* Address of descriptor's data buf */
__le32 cmd_type_len;
__le32 olinfo_status;
} read;
struct {
- __le64 rsvd; /* Reserved */
+ __le64 rsvd; /* Reserved */
__le32 nxtseq_seed;
__le32 status;
} wb;
@@ -2147,10 +2407,10 @@
/* Receive Descriptor - Legacy */
struct ixgbe_legacy_rx_desc {
__le64 buffer_addr; /* Address of the descriptor's data buffer */
- __le16 length; /* Length of data DMAed into data buffer */
- __le16 csum; /* Packet checksum */
- u8 status; /* Descriptor status */
- u8 errors; /* Descriptor Errors */
+ __le16 length; /* Length of data DMAed into data buffer */
+ __le16 csum; /* Packet checksum */
+ u8 status; /* Descriptor status */
+ u8 errors; /* Descriptor Errors */
__le16 vlan;
};
@@ -2194,121 +2454,178 @@
};
/* Adv Transmit Descriptor Config Masks */
-#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
-#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
-#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
-#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
-#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
-#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
-#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
-#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
-#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
-#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
-#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
-#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
-#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
-#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
-#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
-#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
-#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
-#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
-#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
-#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
-#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
- IXGBE_ADVTXD_POPTS_SHIFT)
-#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
- IXGBE_ADVTXD_POPTS_SHIFT)
-#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
-#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
-#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
-#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
-#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
-#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
-#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
-#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
-#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
-#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
-#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
-#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
-#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
-#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
-#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
+#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
+#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
+#define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 time stamp */
+#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
+#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
+#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
+#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Adv Context Desc */
+#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Adv Data Descriptor */
+#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
+#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
+#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
+#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
+#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */
+#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
+#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
+#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
+#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
+#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
+#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
+#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
+#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
+#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
+ IXGBE_ADVTXD_POPTS_SHIFT)
+#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
+ IXGBE_ADVTXD_POPTS_SHIFT)
+#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
+#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
+#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
+/* 1st&Last TSO-full iSCSI PDU */
+#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800
+#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
+#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
+#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
+#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
+#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
+#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
+#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
+#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
+#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
+#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */
+#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
-#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
-#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
-#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
-#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
-#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */
-#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */
-#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
-#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
-#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
-#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
-#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
-#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
+#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
+#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
+#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
+#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
+#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */
+#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */
+#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
+#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
+#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
+#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
+#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
+#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
/* Autonegotiation advertised speeds */
typedef u32 ixgbe_autoneg_advertised;
/* Link speed */
typedef u32 ixgbe_link_speed;
-#define IXGBE_LINK_SPEED_UNKNOWN 0
-#define IXGBE_LINK_SPEED_100_FULL 0x0008
-#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
-#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
-#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
- IXGBE_LINK_SPEED_10GB_FULL)
-#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
- IXGBE_LINK_SPEED_1GB_FULL | \
- IXGBE_LINK_SPEED_10GB_FULL)
+#define IXGBE_LINK_SPEED_UNKNOWN 0
+#define IXGBE_LINK_SPEED_100_FULL 0x0008
+#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
+#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
+#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
+ IXGBE_LINK_SPEED_10GB_FULL)
+#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
+ IXGBE_LINK_SPEED_1GB_FULL | \
+ IXGBE_LINK_SPEED_10GB_FULL)
/* Physical layer type */
typedef u32 ixgbe_physical_layer;
-#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
-#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
-#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
-#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
-#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
-#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
-#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
-#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
-#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
-#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
-#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
-#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
-#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
-#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
-#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
+#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
+#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
+#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
+#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
+#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
+#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
+#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
+#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
+#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
+#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
+#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
+#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
+#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
+#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
+#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
+#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000
+
+/* Flow Control Data Sheet defined values
+ * Calculation and defines taken from 802.1bb Annex O
+ */
+
+/* BitTimes (BT) conversion */
+#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
+#define IXGBE_B2BT(BT) (BT * 8)
+
+/* Calculate Delay to respond to PFC */
+#define IXGBE_PFC_D 672
+
+/* Calculate Cable Delay */
+#define IXGBE_CABLE_DC 5556 /* Delay Copper */
+#define IXGBE_CABLE_DO 5000 /* Delay Optical */
+
+/* Calculate Interface Delay X540 */
+#define IXGBE_PHY_DC 25600 /* Delay 10G BASET */
+#define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */
+#define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */
+
+#define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
-/* Flow Control Macros */
-#define PAUSE_RTT 8
-#define PAUSE_MTU(MTU) ((MTU + 1024 - 1) / 1024)
+/* Calculate Interface Delay 82598, 82599 */
+#define IXGBE_PHY_D 12800
+#define IXGBE_MAC_D 4096
+#define IXGBE_XAUI_D (2 * 1024)
+
+#define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
+
+/* Calculate Delay incurred from higher layer */
+#define IXGBE_HD 6144
+
+/* Calculate PCI Bus delay for low thresholds */
+#define IXGBE_PCI_DELAY 10000
-#define FC_HIGH_WATER(MTU) ((((PAUSE_RTT + PAUSE_MTU(MTU)) * 144) + 99) / 100 +\
- PAUSE_MTU(MTU))
-#define FC_LOW_WATER(MTU) (2 * (2 * PAUSE_MTU(MTU) + PAUSE_RTT))
+/* Calculate X540 delay value in bit times */
+#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
+ ((36 * \
+ (IXGBE_B2BT(_max_frame_link) + \
+ IXGBE_PFC_D + \
+ (2 * IXGBE_CABLE_DC) + \
+ (2 * IXGBE_ID_X540) + \
+ IXGBE_HD) / 25 + 1) + \
+ 2 * IXGBE_B2BT(_max_frame_tc))
+
+/* Calculate 82599, 82598 delay value in bit times */
+#define IXGBE_DV(_max_frame_link, _max_frame_tc) \
+ ((36 * \
+ (IXGBE_B2BT(_max_frame_link) + \
+ IXGBE_PFC_D + \
+ (2 * IXGBE_CABLE_DC) + \
+ (2 * IXGBE_ID) + \
+ IXGBE_HD) / 25 + 1) + \
+ 2 * IXGBE_B2BT(_max_frame_tc))
+
+/* Calculate low threshold delay values */
+#define IXGBE_LOW_DV_X540(_max_frame_tc) \
+ (2 * IXGBE_B2BT(_max_frame_tc) + \
+ (36 * IXGBE_PCI_DELAY / 25) + 1)
+#define IXGBE_LOW_DV(_max_frame_tc) \
+ (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
/* Software ATR hash keys */
-#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
-#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
+#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
+#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
/* Software ATR input stream values and masks */
-#define IXGBE_ATR_HASH_MASK 0x7fff
-#define IXGBE_ATR_L4TYPE_MASK 0x3
-#define IXGBE_ATR_L4TYPE_UDP 0x1
-#define IXGBE_ATR_L4TYPE_TCP 0x2
-#define IXGBE_ATR_L4TYPE_SCTP 0x3
-#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
+#define IXGBE_ATR_HASH_MASK 0x7fff
+#define IXGBE_ATR_L4TYPE_MASK 0x3
+#define IXGBE_ATR_L4TYPE_UDP 0x1
+#define IXGBE_ATR_L4TYPE_TCP 0x2
+#define IXGBE_ATR_L4TYPE_SCTP 0x3
+#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
enum ixgbe_atr_flow_type {
- IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
- IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
- IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
- IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
- IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
- IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
- IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
- IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
+ IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
+ IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
+ IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
+ IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
+ IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
+ IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
+ IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
+ IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
};
/* Flow Director ATR input struct. */
@@ -2316,26 +2633,26 @@
/*
* Byte layout in order, all values with MSB first:
*
- * vm_pool - 1 byte
- * flow_type - 1 byte
- * vlan_id - 2 bytes
- * src_ip - 16 bytes
- * dst_ip - 16 bytes
- * src_port - 2 bytes
- * dst_port - 2 bytes
- * flex_bytes - 2 bytes
- * rsvd0 - 2 bytes - space reserved must be 0.
+ * vm_pool - 1 byte
+ * flow_type - 1 byte
+ * vlan_id - 2 bytes
+ * src_ip - 16 bytes
+ * dst_ip - 16 bytes
+ * src_port - 2 bytes
+ * dst_port - 2 bytes
+ * flex_bytes - 2 bytes
+ * bkt_hash - 2 bytes
*/
struct {
- u8 vm_pool;
- u8 flow_type;
+ u8 vm_pool;
+ u8 flow_type;
__be16 vlan_id;
__be32 dst_ip[4];
__be32 src_ip[4];
__be16 src_port;
__be16 dst_port;
__be16 flex_bytes;
- __be16 rsvd0;
+ __be16 bkt_hash;
} formatted;
__be32 dword_stream[11];
};
@@ -2357,25 +2674,15 @@
};
-struct ixgbe_atr_input_masks {
- __be16 rsvd0;
- __be16 vlan_id_mask;
- __be32 dst_ip_mask[4];
- __be32 src_ip_mask[4];
- __be16 src_port_mask;
- __be16 dst_port_mask;
- __be16 flex_mask;
-};
-
/*
* Unavailable: The FCoE Boot Option ROM is not present in the flash.
* Disabled: Present; boot order is not set for any targets on the port.
* Enabled: Present; boot order is set for at least one target on the port.
*/
enum ixgbe_fcoe_boot_status {
- ixgbe_fcoe_bootstatus_disabled = 0,
- ixgbe_fcoe_bootstatus_enabled = 1,
- ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
+ ixgbe_fcoe_bootstatus_disabled = 0,
+ ixgbe_fcoe_bootstatus_enabled = 1,
+ ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
};
enum ixgbe_eeprom_type {
@@ -2389,6 +2696,9 @@
ixgbe_mac_unknown = 0,
ixgbe_mac_82598EB,
ixgbe_mac_82599EB,
+ ixgbe_mac_82599_vf,
+ ixgbe_mac_X540,
+ ixgbe_mac_X540_vf,
ixgbe_num_macs
};
@@ -2421,10 +2731,10 @@
* 0 SFP_DA_CU
* 1 SFP_SR
* 2 SFP_LR
- * 3 SFP_DA_CU_CORE0 - 82599-specific
- * 4 SFP_DA_CU_CORE1 - 82599-specific
- * 5 SFP_SR/LR_CORE0 - 82599-specific
- * 6 SFP_SR/LR_CORE1 - 82599-specific
+ * 3 SFP_DA_CU_CORE0 - 82599-specific
+ * 4 SFP_DA_CU_CORE1 - 82599-specific
+ * 5 SFP_SR/LR_CORE0 - 82599-specific
+ * 6 SFP_SR/LR_CORE1 - 82599-specific
*/
enum ixgbe_sfp_type {
ixgbe_sfp_type_da_cu = 0,
@@ -2438,6 +2748,8 @@
ixgbe_sfp_type_da_act_lmt_core1 = 8,
ixgbe_sfp_type_1g_cu_core0 = 9,
ixgbe_sfp_type_1g_cu_core1 = 10,
+ ixgbe_sfp_type_1g_sx_core0 = 11,
+ ixgbe_sfp_type_1g_sx_core1 = 12,
ixgbe_sfp_type_not_present = 0xFFFE,
ixgbe_sfp_type_unknown = 0xFFFF
};
@@ -2479,26 +2791,27 @@
/* PCI bus speeds */
enum ixgbe_bus_speed {
- ixgbe_bus_speed_unknown = 0,
- ixgbe_bus_speed_33 = 33,
- ixgbe_bus_speed_66 = 66,
- ixgbe_bus_speed_100 = 100,
- ixgbe_bus_speed_120 = 120,
- ixgbe_bus_speed_133 = 133,
- ixgbe_bus_speed_2500 = 2500,
- ixgbe_bus_speed_5000 = 5000,
+ ixgbe_bus_speed_unknown = 0,
+ ixgbe_bus_speed_33 = 33,
+ ixgbe_bus_speed_66 = 66,
+ ixgbe_bus_speed_100 = 100,
+ ixgbe_bus_speed_120 = 120,
+ ixgbe_bus_speed_133 = 133,
+ ixgbe_bus_speed_2500 = 2500,
+ ixgbe_bus_speed_5000 = 5000,
+ ixgbe_bus_speed_8000 = 8000,
ixgbe_bus_speed_reserved
};
/* PCI bus widths */
enum ixgbe_bus_width {
- ixgbe_bus_width_unknown = 0,
- ixgbe_bus_width_pcie_x1 = 1,
- ixgbe_bus_width_pcie_x2 = 2,
- ixgbe_bus_width_pcie_x4 = 4,
- ixgbe_bus_width_pcie_x8 = 8,
- ixgbe_bus_width_32 = 32,
- ixgbe_bus_width_64 = 64,
+ ixgbe_bus_width_unknown = 0,
+ ixgbe_bus_width_pcie_x1 = 1,
+ ixgbe_bus_width_pcie_x2 = 2,
+ ixgbe_bus_width_pcie_x4 = 4,
+ ixgbe_bus_width_pcie_x8 = 8,
+ ixgbe_bus_width_32 = 32,
+ ixgbe_bus_width_64 = 64,
ixgbe_bus_width_reserved
};
@@ -2522,8 +2835,8 @@
/* Flow control parameters */
struct ixgbe_fc_info {
- u32 high_water; /* Flow Control High-water */
- u32 low_water; /* Flow Control Low-water */
+ u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
+ u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
u16 pause_time; /* Flow Control Pause timer */
bool send_xon; /* Flow control send XON */
bool strict_ieee; /* Strict IEEE mode */
@@ -2603,6 +2916,14 @@
u64 fcoeptc;
u64 fcoedwrc;
u64 fcoedwtc;
+ u64 fcoe_noddp;
+ u64 fcoe_noddp_ext_buff;
+ u64 ldpcec;
+ u64 pcrc8ec;
+ u64 b2ospc;
+ u64 b2ogprc;
+ u64 o2bgptc;
+ u64 o2bspc;
};
/* forward declaration */
@@ -2610,13 +2931,15 @@
/* iterator type for walking multicast address lists */
typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
- u32 *vmdq);
+ u32 *vmdq);
/* Function pointer table */
struct ixgbe_eeprom_operations {
s32 (*init_params)(struct ixgbe_hw *);
s32 (*read)(struct ixgbe_hw *, u16, u16 *);
+ s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
s32 (*write)(struct ixgbe_hw *, u16, u16);
+ s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
s32 (*update_checksum)(struct ixgbe_hw *);
u16 (*calc_checksum)(struct ixgbe_hw *);
@@ -2643,6 +2966,8 @@
s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
s32 (*setup_sfp)(struct ixgbe_hw *);
s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
+ s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
+ s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
void (*release_swfw_sync)(struct ixgbe_hw *, u16);
@@ -2653,7 +2978,10 @@
s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
- bool *);
+ bool *);
+
+ /* Packet Buffer manipulation */
+ void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
/* LED */
s32 (*led_on)(struct ixgbe_hw *, u32);
@@ -2663,25 +2991,31 @@
/* RAR, Multicast, VLAN */
s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
+ s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
s32 (*clear_rar)(struct ixgbe_hw *, u32);
s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
+ s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
s32 (*init_rx_addrs)(struct ixgbe_hw *);
s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
- ixgbe_mc_addr_itr);
+ ixgbe_mc_addr_itr);
s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
- ixgbe_mc_addr_itr);
+ ixgbe_mc_addr_itr, bool clear);
s32 (*enable_mc)(struct ixgbe_hw *);
s32 (*disable_mc)(struct ixgbe_hw *);
s32 (*clear_vfta)(struct ixgbe_hw *);
s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
+ s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *);
s32 (*init_uta_tables)(struct ixgbe_hw *);
void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
/* Flow Control */
- s32 (*fc_enable)(struct ixgbe_hw *, s32);
+ s32 (*fc_enable)(struct ixgbe_hw *);
+
+ /* Manageability interface */
+ s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
};
struct ixgbe_phy_operations {
@@ -2693,7 +3027,7 @@
s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
s32 (*setup_link)(struct ixgbe_hw *);
s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
- bool);
+ bool);
s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
@@ -2705,116 +3039,154 @@
};
struct ixgbe_eeprom_info {
- struct ixgbe_eeprom_operations ops;
- enum ixgbe_eeprom_type type;
- u32 semaphore_delay;
- u16 word_size;
- u16 address_bits;
+ struct ixgbe_eeprom_operations ops;
+ enum ixgbe_eeprom_type type;
+ u32 semaphore_delay;
+ u16 word_size;
+ u16 address_bits;
+ u16 word_page_size;
};
#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
struct ixgbe_mac_info {
- struct ixgbe_mac_operations ops;
- enum ixgbe_mac_type type;
- u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
- u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
- u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
+ struct ixgbe_mac_operations ops;
+ enum ixgbe_mac_type type;
+ u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
+ u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
+ u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
/* prefix for World Wide Node Name (WWNN) */
- u16 wwnn_prefix;
+ u16 wwnn_prefix;
/* prefix for World Wide Port Name (WWPN) */
- u16 wwpn_prefix;
+ u16 wwpn_prefix;
#define IXGBE_MAX_MTA 128
- u32 mta_shadow[IXGBE_MAX_MTA];
- s32 mc_filter_type;
- u32 mcft_size;
- u32 vft_size;
- u32 num_rar_entries;
- u32 rar_highwater;
- u32 rx_pb_size;
- u32 max_tx_queues;
- u32 max_rx_queues;
- u32 max_msix_vectors;
- bool msix_vectors_from_pcie;
- u32 orig_autoc;
- u32 orig_autoc2;
- bool orig_link_settings_stored;
- bool autotry_restart;
- u8 flags;
+ u32 mta_shadow[IXGBE_MAX_MTA];
+ s32 mc_filter_type;
+ u32 mcft_size;
+ u32 vft_size;
+ u32 num_rar_entries;
+ u32 rar_highwater;
+ u32 rx_pb_size;
+ u32 max_tx_queues;
+ u32 max_rx_queues;
+ u32 orig_autoc;
+ u8 san_mac_rar_index;
+ u32 orig_autoc2;
+ u16 max_msix_vectors;
+ bool arc_subsystem_valid;
+ bool orig_link_settings_stored;
+ bool autotry_restart;
+ u8 flags;
};
struct ixgbe_phy_info {
- struct ixgbe_phy_operations ops;
- enum ixgbe_phy_type type;
- u32 addr;
- u32 id;
- enum ixgbe_sfp_type sfp_type;
- bool sfp_setup_needed;
- u32 revision;
- enum ixgbe_media_type media_type;
- bool reset_disable;
- ixgbe_autoneg_advertised autoneg_advertised;
- enum ixgbe_smart_speed smart_speed;
- bool smart_speed_active;
- bool multispeed_fiber;
- bool reset_if_overtemp;
+ struct ixgbe_phy_operations ops;
+ enum ixgbe_phy_type type;
+ u32 addr;
+ u32 id;
+ enum ixgbe_sfp_type sfp_type;
+ bool sfp_setup_needed;
+ u32 revision;
+ enum ixgbe_media_type media_type;
+ bool reset_disable;
+ ixgbe_autoneg_advertised autoneg_advertised;
+ enum ixgbe_smart_speed smart_speed;
+ bool smart_speed_active;
+ bool multispeed_fiber;
+ bool reset_if_overtemp;
+};
+
+#include "ixgbe_mbx.h"
+
+struct ixgbe_mbx_operations {
+ void (*init_params)(struct ixgbe_hw *hw);
+ s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
+ s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
+ s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
+ s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
+ s32 (*check_for_msg)(struct ixgbe_hw *, u16);
+ s32 (*check_for_ack)(struct ixgbe_hw *, u16);
+ s32 (*check_for_rst)(struct ixgbe_hw *, u16);
+};
+
+struct ixgbe_mbx_stats {
+ u32 msgs_tx;
+ u32 msgs_rx;
+
+ u32 acks;
+ u32 reqs;
+ u32 rsts;
+};
+
+struct ixgbe_mbx_info {
+ struct ixgbe_mbx_operations ops;
+ struct ixgbe_mbx_stats stats;
+ u32 timeout;
+ u32 usec_delay;
+ u32 v2p_mailbox;
+ u16 size;
};
struct ixgbe_hw {
- u8 *hw_addr;
- void *back;
- struct ixgbe_mac_info mac;
- struct ixgbe_addr_filter_info addr_ctrl;
- struct ixgbe_fc_info fc;
- struct ixgbe_phy_info phy;
- struct ixgbe_eeprom_info eeprom;
- struct ixgbe_bus_info bus;
- u16 device_id;
- u16 vendor_id;
- u16 subsystem_device_id;
- u16 subsystem_vendor_id;
- u8 revision_id;
- bool adapter_stopped;
+ u8 *hw_addr;
+ void *back;
+ struct ixgbe_mac_info mac;
+ struct ixgbe_addr_filter_info addr_ctrl;
+ struct ixgbe_fc_info fc;
+ struct ixgbe_phy_info phy;
+ struct ixgbe_eeprom_info eeprom;
+ struct ixgbe_bus_info bus;
+ struct ixgbe_mbx_info mbx;
+ u16 device_id;
+ u16 vendor_id;
+ u16 subsystem_device_id;
+ u16 subsystem_vendor_id;
+ u8 revision_id;
+ bool adapter_stopped;
+ bool force_full_reset;
+ bool allow_unsupported_sfp;
};
#define ixgbe_call_func(hw, func, params, error) \
- (func != NULL) ? func params : error
+ (func != NULL) ? func params : error
/* Error Codes */
-#define IXGBE_SUCCESS 0
-#define IXGBE_ERR_EEPROM -1
-#define IXGBE_ERR_EEPROM_CHECKSUM -2
-#define IXGBE_ERR_PHY -3
-#define IXGBE_ERR_CONFIG -4
-#define IXGBE_ERR_PARAM -5
-#define IXGBE_ERR_MAC_TYPE -6
-#define IXGBE_ERR_UNKNOWN_PHY -7
-#define IXGBE_ERR_LINK_SETUP -8
-#define IXGBE_ERR_ADAPTER_STOPPED -9
-#define IXGBE_ERR_INVALID_MAC_ADDR -10
-#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
-#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
-#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
-#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
-#define IXGBE_ERR_RESET_FAILED -15
-#define IXGBE_ERR_SWFW_SYNC -16
-#define IXGBE_ERR_PHY_ADDR_INVALID -17
-#define IXGBE_ERR_I2C -18
-#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
-#define IXGBE_ERR_SFP_NOT_PRESENT -20
-#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
-#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
-#define IXGBE_ERR_FDIR_REINIT_FAILED -23
-#define IXGBE_ERR_EEPROM_VERSION -24
-#define IXGBE_ERR_NO_SPACE -25
-#define IXGBE_ERR_OVERTEMP -26
-#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
-#define IXGBE_ERR_FC_NOT_SUPPORTED -28
-#define IXGBE_ERR_FLOW_CONTROL -29
-#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
-#define IXGBE_ERR_PBA_SECTION -31
-#define IXGBE_ERR_INVALID_ARGUMENT -32
-#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
+#define IXGBE_SUCCESS 0
+#define IXGBE_ERR_EEPROM -1
+#define IXGBE_ERR_EEPROM_CHECKSUM -2
+#define IXGBE_ERR_PHY -3
+#define IXGBE_ERR_CONFIG -4
+#define IXGBE_ERR_PARAM -5
+#define IXGBE_ERR_MAC_TYPE -6
+#define IXGBE_ERR_UNKNOWN_PHY -7
+#define IXGBE_ERR_LINK_SETUP -8
+#define IXGBE_ERR_ADAPTER_STOPPED -9
+#define IXGBE_ERR_INVALID_MAC_ADDR -10
+#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
+#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
+#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
+#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
+#define IXGBE_ERR_RESET_FAILED -15
+#define IXGBE_ERR_SWFW_SYNC -16
+#define IXGBE_ERR_PHY_ADDR_INVALID -17
+#define IXGBE_ERR_I2C -18
+#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
+#define IXGBE_ERR_SFP_NOT_PRESENT -20
+#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
+#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
+#define IXGBE_ERR_FDIR_REINIT_FAILED -23
+#define IXGBE_ERR_EEPROM_VERSION -24
+#define IXGBE_ERR_NO_SPACE -25
+#define IXGBE_ERR_OVERTEMP -26
+#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
+#define IXGBE_ERR_FC_NOT_SUPPORTED -28
+#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
+#define IXGBE_ERR_PBA_SECTION -31
+#define IXGBE_ERR_INVALID_ARGUMENT -32
+#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
+#define IXGBE_ERR_OUT_OF_MEM -34
+
+#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
#endif /* _IXGBE_TYPE_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_x540.c Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,975 @@
+/******************************************************************************
+
+ Copyright (c) 2001-2012, Intel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+******************************************************************************/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_x540.c,v 1.2 2012/07/05 20:51:44 jfv Exp $*/
+
+#include "ixgbe_x540.h"
+#include "ixgbe_type.h"
+#include "ixgbe_api.h"
+#include "ixgbe_common.h"
+#include "ixgbe_phy.h"
+
+static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
+static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
+static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
+static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
+
+/**
+ * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
+ * @hw: pointer to hardware structure
+ *
+ * Initialize the function pointers and assign the MAC type for X540.
+ * Does not touch the hardware.
+ **/
+s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
+{
+ struct ixgbe_mac_info *mac = &hw->mac;
+ struct ixgbe_phy_info *phy = &hw->phy;
+ struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
+ s32 ret_val;
+
+ DEBUGFUNC("ixgbe_init_ops_X540");
+
+ ret_val = ixgbe_init_phy_ops_generic(hw);
+ ret_val = ixgbe_init_ops_generic(hw);
+
+
+ /* EEPROM */
+ eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
+ eeprom->ops.read = &ixgbe_read_eerd_X540;
+ eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
+ eeprom->ops.write = &ixgbe_write_eewr_X540;
+ eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
+ eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
+ eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
+ eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
+
+ /* PHY */
+ phy->ops.init = &ixgbe_init_phy_ops_generic;
+ phy->ops.reset = NULL;
+
+ /* MAC */
+ mac->ops.reset_hw = &ixgbe_reset_hw_X540;
+ mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
+ mac->ops.get_media_type = &ixgbe_get_media_type_X540;
+ mac->ops.get_supported_physical_layer =
+ &ixgbe_get_supported_physical_layer_X540;
+ mac->ops.read_analog_reg8 = NULL;
+ mac->ops.write_analog_reg8 = NULL;
+ mac->ops.start_hw = &ixgbe_start_hw_X540;
+ mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
+ mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
+ mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
+ mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
+ mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
+ mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
+ mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
+ mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
+ mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
+
+ /* RAR, Multicast, VLAN */
+ mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
+ mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
+ mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
+ mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
+ mac->rar_highwater = 1;
+ mac->ops.set_vfta = &ixgbe_set_vfta_generic;
+ mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
+ mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
+ mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
+ mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
+ mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
+
+ /* Link */
+ mac->ops.get_link_capabilities =
+ &ixgbe_get_copper_link_capabilities_generic;
+ mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
+ mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
+ mac->ops.check_link = &ixgbe_check_mac_link_generic;
+
+ mac->mcft_size = 128;
+ mac->vft_size = 128;
+ mac->num_rar_entries = 128;
+ mac->rx_pb_size = 384;
+ mac->max_tx_queues = 128;
+ mac->max_rx_queues = 128;
+ mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
+
+ /*
+ * FWSM register
+ * ARC supported; valid only if manageability features are
+ * enabled.
+ */
+ mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
+ IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
+
+ hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
+
+ /* LEDs */
+ mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
+ mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
+
+ /* Manageability interface */
+ mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
+
+ return ret_val;
+}
+
+/**
+ * ixgbe_get_link_capabilities_X540 - Determines link capabilities
+ * @hw: pointer to hardware structure
+ * @speed: pointer to link speed
+ * @autoneg: TRUE when autoneg or autotry is enabled
+ *
+ * Determines the link capabilities by reading the AUTOC register.
+ **/
+s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
+ ixgbe_link_speed *speed,
+ bool *autoneg)
+{
+ return ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
+}
+
+/**
+ * ixgbe_get_media_type_X540 - Get media type
+ * @hw: pointer to hardware structure
+ *
+ * Returns the media type (fiber, copper, backplane)
+ **/
+enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
+{
+ UNREFERENCED_1PARAMETER(hw);
+ return ixgbe_media_type_copper;
+}
+
+/**
+ * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
+ * @hw: pointer to hardware structure
+ * @speed: new link speed
+ * @autoneg: TRUE if autonegotiation enabled
+ * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
+ **/
+s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
+ ixgbe_link_speed speed, bool autoneg,
+ bool autoneg_wait_to_complete)
+{
+ DEBUGFUNC("ixgbe_setup_mac_link_X540");
+ return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
+ autoneg_wait_to_complete);
+}
+
+/**
+ * ixgbe_reset_hw_X540 - Perform hardware reset
+ * @hw: pointer to hardware structure
+ *
+ * Resets the hardware by resetting the transmit and receive units, masks
+ * and clears all interrupts, and perform a reset.
+ **/
+s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
+{
+ s32 status;
+ u32 ctrl, i;
+
+ DEBUGFUNC("ixgbe_reset_hw_X540");
+
+ /* Call adapter stop to disable tx/rx and clear interrupts */
+ status = hw->mac.ops.stop_adapter(hw);
+ if (status != IXGBE_SUCCESS)
+ goto reset_hw_out;
+
+ /* flush pending Tx transactions */
+ ixgbe_clear_tx_pending(hw);
+
+mac_reset_top:
+ ctrl = IXGBE_CTRL_RST;
+ ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
+ IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
+ IXGBE_WRITE_FLUSH(hw);
+
+ /* Poll for reset bit to self-clear indicating reset is complete */
+ for (i = 0; i < 10; i++) {
+ usec_delay(1);
+ ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
+ if (!(ctrl & IXGBE_CTRL_RST_MASK))
+ break;
+ }
+
+ if (ctrl & IXGBE_CTRL_RST_MASK) {
+ status = IXGBE_ERR_RESET_FAILED;
+ DEBUGOUT("Reset polling failed to complete.\n");
+ }
+ msec_delay(100);
+
+ /*
+ * Double resets are required for recovery from certain error
+ * conditions. Between resets, it is necessary to stall to allow time
+ * for any pending HW events to complete.
+ */
+ if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
+ hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
+ goto mac_reset_top;
+ }
+
+ /* Set the Rx packet buffer size. */
+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
+
+ /* Store the permanent mac address */
+ hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
+
+ /*
+ * Store MAC address from RAR0, clear receive address registers, and
+ * clear the multicast table. Also reset num_rar_entries to 128,
+ * since we modify this value when programming the SAN MAC address.
+ */
+ hw->mac.num_rar_entries = 128;
+ hw->mac.ops.init_rx_addrs(hw);
+
+ /* Store the permanent SAN mac address */
+ hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
+
+ /* Add the SAN MAC address to the RAR only if it's a valid address */
+ if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
+ hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
+ hw->mac.san_addr, 0, IXGBE_RAH_AV);
+
+ /* Save the SAN MAC RAR index */
+ hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
+
+ /* Reserve the last RAR for the SAN MAC address */
+ hw->mac.num_rar_entries--;
+ }
+
+ /* Store the alternative WWNN/WWPN prefix */
+ hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
+ &hw->mac.wwpn_prefix);
+
+reset_hw_out:
+ return status;
+}
+
+/**
+ * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
+ * @hw: pointer to hardware structure
+ *
+ * Starts the hardware using the generic start_hw function
+ * and the generation start_hw function.
+ * Then performs revision-specific operations, if any.
+ **/
+s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
+{
+ s32 ret_val = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_start_hw_X540");
+
+ ret_val = ixgbe_start_hw_generic(hw);
+ if (ret_val != IXGBE_SUCCESS)
+ goto out;
+
+ ret_val = ixgbe_start_hw_gen2(hw);
+
+out:
+ return ret_val;
+}
+
+/**
+ * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
+ * @hw: pointer to hardware structure
+ *
+ * Determines physical layer capabilities of the current configuration.
+ **/
+u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
+{
+ u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+ u16 ext_ability = 0;
+
+ DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
+
+ hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
+ IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
+ if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
+ physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
+ if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
+ physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
+ if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
+ physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
+
+ return physical_layer;
+}
+
+/**
+ * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
+ * @hw: pointer to hardware structure
+ *
+ * Initializes the EEPROM parameters ixgbe_eeprom_info within the
+ * ixgbe_hw struct in order to set up EEPROM access.
+ **/
+s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
+{
+ struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
+ u32 eec;
+ u16 eeprom_size;
+
+ DEBUGFUNC("ixgbe_init_eeprom_params_X540");
+
+ if (eeprom->type == ixgbe_eeprom_uninitialized) {
+ eeprom->semaphore_delay = 10;
+ eeprom->type = ixgbe_flash;
+
+ eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+ eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
+ IXGBE_EEC_SIZE_SHIFT);
+ eeprom->word_size = 1 << (eeprom_size +
+ IXGBE_EEPROM_WORD_SIZE_SHIFT);
+
+ DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
+ eeprom->type, eeprom->word_size);
+ }
+
+ return IXGBE_SUCCESS;
+}
+
+/**
+ * ixgbe_read_eerd_X540- Read EEPROM word using EERD
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in the EEPROM to read
+ * @data: word read from the EEPROM
+ *
+ * Reads a 16 bit word from the EEPROM using the EERD register.
+ **/
+s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
+{
+ s32 status = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_read_eerd_X540");
+ if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
+ IXGBE_SUCCESS)
+ status = ixgbe_read_eerd_generic(hw, offset, data);
+ else
+ status = IXGBE_ERR_SWFW_SYNC;
+
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+ return status;
+}
+
+/**
+ * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in the EEPROM to read
+ * @words: number of words
+ * @data: word(s) read from the EEPROM
+ *
+ * Reads a 16 bit word(s) from the EEPROM using the EERD register.
+ **/
+s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
+ u16 offset, u16 words, u16 *data)
+{
+ s32 status = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
+ if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
+ IXGBE_SUCCESS)
+ status = ixgbe_read_eerd_buffer_generic(hw, offset,
+ words, data);
+ else
+ status = IXGBE_ERR_SWFW_SYNC;
+
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+ return status;
+}
+
+/**
+ * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in the EEPROM to write
+ * @data: word write to the EEPROM
+ *
+ * Write a 16 bit word to the EEPROM using the EEWR register.
+ **/
+s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
+{
+ s32 status = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_write_eewr_X540");
+ if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
+ IXGBE_SUCCESS)
+ status = ixgbe_write_eewr_generic(hw, offset, data);
+ else
+ status = IXGBE_ERR_SWFW_SYNC;
+
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+ return status;
+}
+
+/**
+ * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in the EEPROM to write
+ * @words: number of words
+ * @data: word(s) write to the EEPROM
+ *
+ * Write a 16 bit word(s) to the EEPROM using the EEWR register.
+ **/
+s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
+ u16 offset, u16 words, u16 *data)
+{
+ s32 status = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
+ if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
+ IXGBE_SUCCESS)
+ status = ixgbe_write_eewr_buffer_generic(hw, offset,
+ words, data);
+ else
+ status = IXGBE_ERR_SWFW_SYNC;
+
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+ return status;
+}
+
+/**
+ * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
+ *
+ * This function does not use synchronization for EERD and EEWR. It can
+ * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
+ *
+ * @hw: pointer to hardware structure
+ **/
+u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
+{
+ u16 i;
+ u16 j;
+ u16 checksum = 0;
+ u16 length = 0;
+ u16 pointer = 0;
+ u16 word = 0;
+
+ /*
+ * Do not use hw->eeprom.ops.read because we do not want to take
+ * the synchronization semaphores here. Instead use
+ * ixgbe_read_eerd_generic
+ */
+
+ DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
+
+ /* Include 0x0-0x3F in the checksum */
+ for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
+ if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
+ DEBUGOUT("EEPROM read failed\n");
+ break;
+ }
+ checksum += word;
+ }
+
+ /*
+ * Include all data from pointers 0x3, 0x6-0xE. This excludes the
+ * FW, PHY module, and PCIe Expansion/Option ROM pointers.
+ */
+ for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
+ if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
+ continue;
+
+ if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
+ DEBUGOUT("EEPROM read failed\n");
+ break;
+ }
+
+ /* Skip pointer section if the pointer is invalid. */
+ if (pointer == 0xFFFF || pointer == 0 ||
+ pointer >= hw->eeprom.word_size)
+ continue;
+
+ if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
+ IXGBE_SUCCESS) {
+ DEBUGOUT("EEPROM read failed\n");
+ break;
+ }
+
+ /* Skip pointer section if length is invalid. */
+ if (length == 0xFFFF || length == 0 ||
+ (pointer + length) >= hw->eeprom.word_size)
+ continue;
+
+ for (j = pointer+1; j <= pointer+length; j++) {
+ if (ixgbe_read_eerd_generic(hw, j, &word) !=
+ IXGBE_SUCCESS) {
+ DEBUGOUT("EEPROM read failed\n");
+ break;
+ }
+ checksum += word;
+ }
+ }
+
+ checksum = (u16)IXGBE_EEPROM_SUM - checksum;
+
+ return checksum;
+}
+
+/**
+ * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
+ * @hw: pointer to hardware structure
+ * @checksum_val: calculated checksum
+ *
+ * Performs checksum calculation and validates the EEPROM checksum. If the
+ * caller does not need checksum_val, the value can be NULL.
+ **/
+s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
+ u16 *checksum_val)
+{
+ s32 status;
+ u16 checksum;
+ u16 read_checksum = 0;
+
+ DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
+
+ /*
+ * Read the first word from the EEPROM. If this times out or fails, do
+ * not continue or we could be in for a very long wait while every
+ * EEPROM read fails
+ */
+ status = hw->eeprom.ops.read(hw, 0, &checksum);
+
+ if (status != IXGBE_SUCCESS) {
+ DEBUGOUT("EEPROM read failed\n");
+ goto out;
+ }
+
+ if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
+ IXGBE_SUCCESS) {
+ checksum = hw->eeprom.ops.calc_checksum(hw);
+
+ /*
+ * Do not use hw->eeprom.ops.read because we do not want to take
+ * the synchronization semaphores twice here.
+ */
+ status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
+ &read_checksum);
+
+ if (status == IXGBE_SUCCESS) {
+ /*
+ * Verify read checksum from EEPROM is the same as
+ * calculated checksum
+ */
+ if (read_checksum != checksum)
+ status = IXGBE_ERR_EEPROM_CHECKSUM;
+
+ /* If the user cares, return the calculated checksum */
+ if (checksum_val)
+ *checksum_val = checksum;
+ }
+ } else {
+ status = IXGBE_ERR_SWFW_SYNC;
+ }
+
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+out:
+ return status;
+}
+
+/**
+ * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
+ * @hw: pointer to hardware structure
+ *
+ * After writing EEPROM to shadow RAM using EEWR register, software calculates
+ * checksum and updates the EEPROM and instructs the hardware to update
+ * the flash.
+ **/
+s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
+{
+ s32 status;
+ u16 checksum;
+
+ DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
+
+ /*
+ * Read the first word from the EEPROM. If this times out or fails, do
+ * not continue or we could be in for a very long wait while every
+ * EEPROM read fails
+ */
+ status = hw->eeprom.ops.read(hw, 0, &checksum);
+
+ if (status != IXGBE_SUCCESS)
+ DEBUGOUT("EEPROM read failed\n");
+
+ if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
+ IXGBE_SUCCESS) {
+ checksum = hw->eeprom.ops.calc_checksum(hw);
+
+ /*
+ * Do not use hw->eeprom.ops.write because we do not want to
+ * take the synchronization semaphores twice here.
+ */
+ status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
+ checksum);
+
+ if (status == IXGBE_SUCCESS)
+ status = ixgbe_update_flash_X540(hw);
+ else
+ status = IXGBE_ERR_SWFW_SYNC;
+ }
+
+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+
+ return status;
+}
+
+/**
+ * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
+ * @hw: pointer to hardware structure
+ *
+ * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
+ * EEPROM from shadow RAM to the flash device.
+ **/
+static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
+{
+ u32 flup;
+ s32 status = IXGBE_ERR_EEPROM;
+
+ DEBUGFUNC("ixgbe_update_flash_X540");
+
+ status = ixgbe_poll_flash_update_done_X540(hw);
+ if (status == IXGBE_ERR_EEPROM) {
+ DEBUGOUT("Flash update time out\n");
+ goto out;
+ }
+
+ flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
+ IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
+
+ status = ixgbe_poll_flash_update_done_X540(hw);
+ if (status == IXGBE_SUCCESS)
+ DEBUGOUT("Flash update complete\n");
+ else
+ DEBUGOUT("Flash update time out\n");
+
+ if (hw->revision_id == 0) {
+ flup = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+ if (flup & IXGBE_EEC_SEC1VAL) {
+ flup |= IXGBE_EEC_FLUP;
+ IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
+ }
+
+ status = ixgbe_poll_flash_update_done_X540(hw);
+ if (status == IXGBE_SUCCESS)
+ DEBUGOUT("Flash update complete\n");
+ else
+ DEBUGOUT("Flash update time out\n");
+ }
+out:
+ return status;
+}
+
+/**
+ * ixgbe_poll_flash_update_done_X540 - Poll flash update status
+ * @hw: pointer to hardware structure
+ *
+ * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
+ * flash update is done.
+ **/
+static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
+{
+ u32 i;
+ u32 reg;
+ s32 status = IXGBE_ERR_EEPROM;
+
+ DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
+
+ for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
+ reg = IXGBE_READ_REG(hw, IXGBE_EEC);
+ if (reg & IXGBE_EEC_FLUDONE) {
+ status = IXGBE_SUCCESS;
+ break;
+ }
+ usec_delay(5);
+ }
+ return status;
+}
+
+/**
+ * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
+ * @hw: pointer to hardware structure
+ * @mask: Mask to specify which semaphore to acquire
+ *
+ * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
+ * the specified function (CSR, PHY0, PHY1, NVM, Flash)
+ **/
+s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
+{
+ u32 swfw_sync;
+ u32 swmask = mask;
+ u32 fwmask = mask << 5;
+ u32 hwmask = 0;
+ u32 timeout = 200;
+ u32 i;
+ s32 ret_val = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
+
+ if (swmask == IXGBE_GSSR_EEP_SM)
+ hwmask = IXGBE_GSSR_FLASH_SM;
+
+ /* SW only mask doesn't have FW bit pair */
+ if (swmask == IXGBE_GSSR_SW_MNG_SM)
+ fwmask = 0;
+
+ for (i = 0; i < timeout; i++) {
+ /*
+ * SW NVM semaphore bit is used for access to all
+ * SW_FW_SYNC bits (not just NVM)
+ */
+ if (ixgbe_get_swfw_sync_semaphore(hw)) {
+ ret_val = IXGBE_ERR_SWFW_SYNC;
+ goto out;
+ }
+
+ swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+ if (!(swfw_sync & (fwmask | swmask | hwmask))) {
+ swfw_sync |= swmask;
+ IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+ ixgbe_release_swfw_sync_semaphore(hw);
+ msec_delay(5);
+ goto out;
+ } else {
+ /*
+ * Firmware currently using resource (fwmask), hardware
+ * currently using resource (hwmask), or other software
+ * thread currently using resource (swmask)
+ */
+ ixgbe_release_swfw_sync_semaphore(hw);
+ msec_delay(5);
+ }
+ }
+
+ /* Failed to get SW only semaphore */
+ if (swmask == IXGBE_GSSR_SW_MNG_SM) {
+ ret_val = IXGBE_ERR_SWFW_SYNC;
+ goto out;
+ }
+
+ /* If the resource is not released by the FW/HW the SW can assume that
+ * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
+ * of the requested resource(s) while ignoring the corresponding FW/HW
+ * bits in the SW_FW_SYNC register.
+ */
+ swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+ if (swfw_sync & (fwmask | hwmask)) {
+ if (ixgbe_get_swfw_sync_semaphore(hw)) {
+ ret_val = IXGBE_ERR_SWFW_SYNC;
+ goto out;
+ }
+
+ swfw_sync |= swmask;
+ IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+ ixgbe_release_swfw_sync_semaphore(hw);
+ msec_delay(5);
+ }
+
+out:
+ return ret_val;
+}
+
+/**
+ * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
+ * @hw: pointer to hardware structure
+ * @mask: Mask to specify which semaphore to release
+ *
+ * Releases the SWFW semaphore through the SW_FW_SYNC register
+ * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
+ **/
+void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
+{
+ u32 swfw_sync;
+ u32 swmask = mask;
+
+ DEBUGFUNC("ixgbe_release_swfw_sync_X540");
+
+ (void) ixgbe_get_swfw_sync_semaphore(hw);
+
+ swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+ swfw_sync &= ~swmask;
+ IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+
+ ixgbe_release_swfw_sync_semaphore(hw);
+ msec_delay(5);
+}
+
+/**
+ * ixgbe_get_nvm_semaphore - Get hardware semaphore
+ * @hw: pointer to hardware structure
+ *
+ * Sets the hardware semaphores so SW/FW can gain control of shared resources
+ **/
+static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
+{
+ s32 status = IXGBE_ERR_EEPROM;
+ u32 timeout = 2000;
+ u32 i;
+ u32 swsm;
+
+ DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
+
+ /* Get SMBI software semaphore between device drivers first */
+ for (i = 0; i < timeout; i++) {
+ /*
+ * If the SMBI bit is 0 when we read it, then the bit will be
+ * set and we have the semaphore
+ */
+ swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+ if (!(swsm & IXGBE_SWSM_SMBI)) {
+ status = IXGBE_SUCCESS;
+ break;
+ }
+ usec_delay(50);
+ }
+
+ /* Now get the semaphore between SW/FW through the REGSMP bit */
+ if (status == IXGBE_SUCCESS) {
+ for (i = 0; i < timeout; i++) {
+ swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+ if (!(swsm & IXGBE_SWFW_REGSMP))
+ break;
+
+ usec_delay(50);
+ }
+
+ /*
+ * Release semaphores and return error if SW NVM semaphore
+ * was not granted because we don't have access to the EEPROM
+ */
+ if (i >= timeout) {
+ DEBUGOUT("REGSMP Software NVM semaphore not "
+ "granted.\n");
+ ixgbe_release_swfw_sync_semaphore(hw);
+ status = IXGBE_ERR_EEPROM;
+ }
+ } else {
+ DEBUGOUT("Software semaphore SMBI between device drivers "
+ "not granted.\n");
+ }
+
+ return status;
+}
+
+/**
+ * ixgbe_release_nvm_semaphore - Release hardware semaphore
+ * @hw: pointer to hardware structure
+ *
+ * This function clears hardware semaphore bits.
+ **/
+static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
+{
+ u32 swsm;
+
+ DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
+
+ /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
+
+ swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+ swsm &= ~IXGBE_SWSM_SMBI;
+ IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
+
+ swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+ swsm &= ~IXGBE_SWFW_REGSMP;
+ IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
+
+ IXGBE_WRITE_FLUSH(hw);
+}
+
+/**
+ * ixgbe_blink_led_start_X540 - Blink LED based on index.
+ * @hw: pointer to hardware structure
+ * @index: led number to blink
+ *
+ * Devices that implement the version 2 interface:
+ * X540
+ **/
+s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
+{
+ u32 macc_reg;
+ u32 ledctl_reg;
+ ixgbe_link_speed speed;
+ bool link_up;
+
+ DEBUGFUNC("ixgbe_blink_led_start_X540");
+
+ /*
+ * Link should be up in order for the blink bit in the LED control
+ * register to work. Force link and speed in the MAC if link is down.
+ * This will be reversed when we stop the blinking.
+ */
+ hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
+ if (link_up == FALSE) {
+ macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
+ macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
+ IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
+ }
+ /* Set the LED to LINK_UP + BLINK. */
+ ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+ ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
+ ledctl_reg |= IXGBE_LED_BLINK(index);
+ IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
+ IXGBE_WRITE_FLUSH(hw);
+
+ return IXGBE_SUCCESS;
+}
+
+/**
+ * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
+ * @hw: pointer to hardware structure
+ * @index: led number to stop blinking
+ *
+ * Devices that implement the version 2 interface:
+ * X540
+ **/
+s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
+{
+ u32 macc_reg;
+ u32 ledctl_reg;
+
+ DEBUGFUNC("ixgbe_blink_led_stop_X540");
+
+ /* Restore the LED to its default value. */
+ ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+ ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
+ ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
+ ledctl_reg &= ~IXGBE_LED_BLINK(index);
+ IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
+
+ /* Unforce link and speed in the MAC. */
+ macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
+ macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
+ IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
+ IXGBE_WRITE_FLUSH(hw);
+
+ return IXGBE_SUCCESS;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_x540.h Sun Aug 12 11:56:48 2012 +0100
@@ -0,0 +1,65 @@
+/******************************************************************************
+
+ Copyright (c) 2001-2012, Intel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+******************************************************************************/
+/*$FreeBSD$*/
+
+#ifndef _IXGBE_X540_H_
+#define _IXGBE_X540_H_
+
+#include "ixgbe_type.h"
+
+s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
+ ixgbe_link_speed *speed, bool *autoneg);
+enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw);
+s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
+ bool autoneg, bool link_up_wait_to_complete);
+s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw);
+s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw);
+u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);
+
+s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw);
+s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data);
+s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words,
+ u16 *data);
+s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data);
+s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words,
+ u16 *data);
+s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);
+s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);
+u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);
+
+s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
+void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
+
+s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index);
+s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index);
+#endif /* _IXGBE_X540_H_ */
--- a/usr/src/uts/common/os/logsubr.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/os/logsubr.c Sun Aug 12 11:56:48 2012 +0100
@@ -246,7 +246,7 @@
/*
* Now that logging is enabled, emit the SunOS banner.
*/
- printf("\rOpenIndiana Build %s %u-bit (illumos 13740:836bfdf31fc4)\n",
+ printf("\rOpenIndiana Build %s %u-bit (illumos 13769:2317a7492de4)\n",
utsname.version, NBBY * (uint_t)sizeof (void *));
printf("SunOS Release %s - Copyright 1983-2010 Oracle and/or its "
"affiliates.\n", utsname.release);
--- a/usr/src/uts/common/smbsrv/smb_kproto.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/smbsrv/smb_kproto.h Sun Aug 12 11:56:48 2012 +0100
@@ -21,7 +21,7 @@
/*
* Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/
/*
@@ -381,7 +381,7 @@
int smb_server_spooldoc(smb_ioc_spooldoc_t *);
int smb_spool_add_doc(smb_kspooldoc_t *);
-int smb_spool_add_fid(uint16_t);
+void smb_spool_add_fid(smb_server_t *, uint16_t);
void smb_server_inc_nbt_sess(smb_server_t *);
void smb_server_dec_nbt_sess(smb_server_t *);
--- a/usr/src/uts/common/sys/dtrace.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/sys/dtrace.h Sun Aug 12 11:56:48 2012 +0100
@@ -26,6 +26,7 @@
/*
* Copyright (c) 2011, Joyent, Inc. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#ifndef _SYS_DTRACE_H
@@ -919,10 +920,10 @@
* DTrace Metadata Description Structures
*
* DTrace separates the trace data stream from the metadata stream. The only
- * metadata tokens placed in the data stream are enabled probe identifiers
- * (EPIDs) or (in the case of aggregations) aggregation identifiers. In order
- * to determine the structure of the data, DTrace consumers pass the token to
- * the kernel, and receive in return a corresponding description of the enabled
+ * metadata tokens placed in the data stream are the dtrace_rechdr_t (EPID +
+ * timestamp) or (in the case of aggregations) aggregation identifiers. To
+ * determine the structure of the data, DTrace consumers pass the token to the
+ * kernel, and receive in return a corresponding description of the enabled
* probe (via the dtrace_eprobedesc structure) or the aggregation (via the
* dtrace_aggdesc structure). Both of these structures are expressed in terms
* of record descriptions (via the dtrace_recdesc structure) that describe the
@@ -1017,7 +1018,8 @@
#define DTRACEOPT_AGGSORTREV 24 /* reverse-sort aggregations */
#define DTRACEOPT_AGGSORTPOS 25 /* agg. position to sort on */
#define DTRACEOPT_AGGSORTKEYPOS 26 /* agg. key position to sort on */
-#define DTRACEOPT_MAX 27 /* number of options */
+#define DTRACEOPT_TEMPORAL 27 /* temporally ordered output */
+#define DTRACEOPT_MAX 28 /* number of options */
#define DTRACEOPT_UNSET (dtrace_optval_t)-2 /* unset option */
@@ -1037,7 +1039,9 @@
* where user-level wishes the kernel to snapshot the buffer to (the
* dtbd_data field). The kernel uses the same structure to pass back some
* information regarding the buffer: the size of data actually copied out, the
- * number of drops, the number of errors, and the offset of the oldest record.
+ * number of drops, the number of errors, the offset of the oldest record,
+ * and the time of the snapshot.
+ *
* If the buffer policy is a "switch" policy, taking a snapshot of the
* principal buffer has the additional effect of switching the active and
* inactive buffers. Taking a snapshot of the aggregation buffer _always_ has
@@ -1050,9 +1054,30 @@
uint64_t dtbd_drops; /* number of drops */
DTRACE_PTR(char, dtbd_data); /* data */
uint64_t dtbd_oldest; /* offset of oldest record */
+ uint64_t dtbd_timestamp; /* hrtime of snapshot */
} dtrace_bufdesc_t;
/*
+ * Each record in the buffer (dtbd_data) begins with a header that includes
+ * the epid and a timestamp. The timestamp is split into two 4-byte parts
+ * so that we do not require 8-byte alignment.
+ */
+typedef struct dtrace_rechdr {
+ dtrace_epid_t dtrh_epid; /* enabled probe id */
+ uint32_t dtrh_timestamp_hi; /* high bits of hrtime_t */
+ uint32_t dtrh_timestamp_lo; /* low bits of hrtime_t */
+} dtrace_rechdr_t;
+
+#define DTRACE_RECORD_LOAD_TIMESTAMP(dtrh) \
+ ((dtrh)->dtrh_timestamp_lo + \
+ ((uint64_t)(dtrh)->dtrh_timestamp_hi << 32))
+
+#define DTRACE_RECORD_STORE_TIMESTAMP(dtrh, hrtime) { \
+ (dtrh)->dtrh_timestamp_lo = (uint32_t)hrtime; \
+ (dtrh)->dtrh_timestamp_hi = hrtime >> 32; \
+}
+
+/*
* DTrace Status
*
* The status of DTrace is relayed via the dtrace_status structure. This
--- a/usr/src/uts/common/sys/dtrace_impl.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/sys/dtrace_impl.h Sun Aug 12 11:56:48 2012 +0100
@@ -26,6 +26,7 @@
/*
* Copyright (c) 2011, Joyent, Inc. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#ifndef _SYS_DTRACE_IMPL_H
@@ -199,15 +200,18 @@
* predicate is non-NULL, the DIF object is executed. If the result is
* non-zero, the action list is processed, with each action being executed
* accordingly. When the action list has been completely executed, processing
- * advances to the next ECB. processing advances to the next ECB. If the
- * result is non-zero; For each ECB, it first determines the The ECB
- * abstraction allows disjoint consumers to multiplex on single probes.
+ * advances to the next ECB. The ECB abstraction allows disjoint consumers
+ * to multiplex on single probes.
+ *
+ * Execution of the ECB results in consuming dte_size bytes in the buffer
+ * to record data. During execution, dte_needed bytes must be available in
+ * the buffer. This space is used for both recorded data and tuple data.
*/
struct dtrace_ecb {
dtrace_epid_t dte_epid; /* enabled probe ID */
uint32_t dte_alignment; /* required alignment */
- size_t dte_needed; /* bytes needed */
- size_t dte_size; /* total size of payload */
+ size_t dte_needed; /* space needed for execution */
+ size_t dte_size; /* size of recorded payload */
dtrace_predicate_t *dte_predicate; /* predicate, if any */
dtrace_action_t *dte_action; /* actions, if any */
dtrace_ecb_t *dte_next; /* next ECB on probe */
@@ -265,27 +269,30 @@
* the EPID, the consumer can determine the data layout. (The data buffer
* layout is shown schematically below.) By assuring that one can determine
* data layout from the EPID, the metadata stream can be separated from the
- * data stream -- simplifying the data stream enormously.
+ * data stream -- simplifying the data stream enormously. The ECB always
+ * proceeds the recorded data as part of the dtrace_rechdr_t structure that
+ * includes the EPID and a high-resolution timestamp used for output ordering
+ * consistency.
*
- * base of data buffer ---> +------+--------------------+------+
- * | EPID | data | EPID |
- * +------+--------+------+----+------+
- * | data | EPID | data |
- * +---------------+------+-----------+
- * | data, cont. |
- * +------+--------------------+------+
- * | EPID | data | |
- * +------+--------------------+ |
- * | || |
- * | || |
- * | \/ |
- * : :
- * . .
- * . .
- * . .
- * : :
- * | |
- * limit of data buffer ---> +----------------------------------+
+ * base of data buffer ---> +--------+--------------------+--------+
+ * | rechdr | data | rechdr |
+ * +--------+------+--------+----+--------+
+ * | data | rechdr | data |
+ * +---------------+--------+-------------+
+ * | data, cont. |
+ * +--------+--------------------+--------+
+ * | rechdr | data | |
+ * +--------+--------------------+ |
+ * | || |
+ * | || |
+ * | \/ |
+ * : :
+ * . .
+ * . .
+ * . .
+ * : :
+ * | |
+ * limit of data buffer ---> +--------------------------------------+
*
* When evaluating an ECB, dtrace_probe() determines if the ECB's needs of the
* principal buffer (both scratch and payload) exceed the available space. If
--- a/usr/src/uts/common/sys/feature_tests.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/sys/feature_tests.h Sun Aug 12 11:56:48 2012 +0100
@@ -27,8 +27,6 @@
#ifndef _SYS_FEATURE_TESTS_H
#define _SYS_FEATURE_TESTS_H
-#pragma ident "%Z%%M% %I% %E% SMI"
-
#include <sys/ccompile.h>
#include <sys/isa_defs.h>
@@ -365,7 +363,7 @@
* compiler is used. This allows for the use of single prototype
* declarations regardless of compiler version.
*/
-#if (defined(__STDC__) && defined(_STDC_C99))
+#if (defined(__STDC__) && defined(_STDC_C99)) && !defined(__cplusplus)
#define _RESTRICT_KYWD restrict
#else
#define _RESTRICT_KYWD
--- a/usr/src/uts/common/sys/fs/hsfs_isospec.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/sys/fs/hsfs_isospec.h Sun Aug 12 11:56:48 2012 +0100
@@ -26,8 +26,6 @@
#ifndef _SYS_FS_HSFS_ISOSPEC_H
#define _SYS_FS_HSFS_ISOSPEC_H
-#pragma ident "%Z%%M% %I% %E% SMI"
-
/*
* ISO 9660 filesystem specification
*/
@@ -87,6 +85,7 @@
enum iso_voldesc_type {
ISO_VD_BOOT = 0, ISO_VD_PVD = 1, ISO_VD_SVD = 2, ISO_VD_VPD = 3,
+ ISO_VD_UNIX = 4, /* UNIX extension */
ISO_VD_EOV = 255
};
#define ISO_ID_STRING "CD001" /* ISO_std_id field */
@@ -138,7 +137,7 @@
#define ISO_file_struct_ver(x) (&((uchar_t *)x)[881])
/* macros to get the values of each field (strings are returned as ptrs) */
-#define ISO_DESC_TYPE(x) ((enum hs_voldesc_type)*(ISO_desc_type(x)))
+#define ISO_DESC_TYPE(x) ((enum iso_voldesc_type)*(ISO_desc_type(x)))
#define ISO_STD_ID(x) ISO_std_id(x)
#define ISO_STD_VER(x) *(ISO_std_ver(x))
#define ISO_SYS_ID(x) ISO_sys_id(x)
--- a/usr/src/uts/common/sys/fs/zfs.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/sys/fs/zfs.h Sun Aug 12 11:56:48 2012 +0100
@@ -52,6 +52,16 @@
ZFS_TYPE_POOL = 0x8
} zfs_type_t;
+typedef enum dmu_objset_type {
+ DMU_OST_NONE,
+ DMU_OST_META,
+ DMU_OST_ZFS,
+ DMU_OST_ZVOL,
+ DMU_OST_OTHER, /* For testing only! */
+ DMU_OST_ANY, /* Be careful! */
+ DMU_OST_NUMTYPES
+} dmu_objset_type_t;
+
#define ZFS_TYPE_DATASET \
(ZFS_TYPE_FILESYSTEM | ZFS_TYPE_VOLUME | ZFS_TYPE_SNAPSHOT)
@@ -518,6 +528,7 @@
#define ZPOOL_CONFIG_LOAD_INFO "load_info" /* not stored on disk */
#define ZPOOL_CONFIG_REWIND_INFO "rewind_info" /* not stored on disk */
#define ZPOOL_CONFIG_UNSUP_FEAT "unsup_feat" /* not stored on disk */
+#define ZPOOL_CONFIG_ENABLED_FEAT "enabled_feat" /* not stored on disk */
#define ZPOOL_CONFIG_CAN_RDONLY "can_rdonly" /* not stored on disk */
#define ZPOOL_CONFIG_FEATURES_FOR_READ "features_for_read"
#define ZPOOL_CONFIG_FEATURE_STATS "feature_stats" /* not stored on disk */
@@ -744,10 +755,10 @@
/*
* /dev/zfs ioctl numbers.
*/
-#define ZFS_IOC ('Z' << 8)
-
typedef enum zfs_ioc {
- ZFS_IOC_POOL_CREATE = ZFS_IOC,
+ ZFS_IOC_FIRST = ('Z' << 8),
+ ZFS_IOC = ZFS_IOC_FIRST,
+ ZFS_IOC_POOL_CREATE = ZFS_IOC_FIRST,
ZFS_IOC_POOL_DESTROY,
ZFS_IOC_POOL_IMPORT,
ZFS_IOC_POOL_EXPORT,
@@ -806,10 +817,15 @@
ZFS_IOC_OBJ_TO_STATS,
ZFS_IOC_SPACE_WRITTEN,
ZFS_IOC_SPACE_SNAPS,
- ZFS_IOC_DESTROY_SNAPS_NVL,
+ ZFS_IOC_DESTROY_SNAPS,
ZFS_IOC_POOL_REGUID,
ZFS_IOC_POOL_REOPEN,
- ZFS_IOC_SEND_PROGRESS
+ ZFS_IOC_SEND_PROGRESS,
+ ZFS_IOC_LOG_HISTORY,
+ ZFS_IOC_SEND_NEW,
+ ZFS_IOC_SEND_SPACE,
+ ZFS_IOC_CLONE,
+ ZFS_IOC_LAST
} zfs_ioc_t;
/*
@@ -846,6 +862,12 @@
#define ZPOOL_HIST_TXG "history txg"
#define ZPOOL_HIST_INT_EVENT "history internal event"
#define ZPOOL_HIST_INT_STR "history internal str"
+#define ZPOOL_HIST_INT_NAME "internal_name"
+#define ZPOOL_HIST_IOCTL "ioctl"
+#define ZPOOL_HIST_INPUT_NVL "in_nvl"
+#define ZPOOL_HIST_OUTPUT_NVL "out_nvl"
+#define ZPOOL_HIST_DSNAME "dsname"
+#define ZPOOL_HIST_DSID "dsid"
/*
* Flags for ZFS_IOC_VDEV_SET_STATE
@@ -891,56 +913,6 @@
#define ZFS_EV_VDEV_PATH "vdev_path"
#define ZFS_EV_VDEV_GUID "vdev_guid"
-/*
- * Note: This is encoded on-disk, so new events must be added to the
- * end, and unused events can not be removed. Be sure to edit
- * libzfs_pool.c: hist_event_table[].
- */
-typedef enum history_internal_events {
- LOG_NO_EVENT = 0,
- LOG_POOL_CREATE,
- LOG_POOL_VDEV_ADD,
- LOG_POOL_REMOVE,
- LOG_POOL_DESTROY,
- LOG_POOL_EXPORT,
- LOG_POOL_IMPORT,
- LOG_POOL_VDEV_ATTACH,
- LOG_POOL_VDEV_REPLACE,
- LOG_POOL_VDEV_DETACH,
- LOG_POOL_VDEV_ONLINE,
- LOG_POOL_VDEV_OFFLINE,
- LOG_POOL_UPGRADE,
- LOG_POOL_CLEAR,
- LOG_POOL_SCAN,
- LOG_POOL_PROPSET,
- LOG_DS_CREATE,
- LOG_DS_CLONE,
- LOG_DS_DESTROY,
- LOG_DS_DESTROY_BEGIN,
- LOG_DS_INHERIT,
- LOG_DS_PROPSET,
- LOG_DS_QUOTA,
- LOG_DS_PERM_UPDATE,
- LOG_DS_PERM_REMOVE,
- LOG_DS_PERM_WHO_REMOVE,
- LOG_DS_PROMOTE,
- LOG_DS_RECEIVE,
- LOG_DS_RENAME,
- LOG_DS_RESERVATION,
- LOG_DS_REPLAY_INC_SYNC,
- LOG_DS_REPLAY_FULL_SYNC,
- LOG_DS_ROLLBACK,
- LOG_DS_SNAPSHOT,
- LOG_DS_UPGRADE,
- LOG_DS_REFQUOTA,
- LOG_DS_REFRESERV,
- LOG_POOL_SCAN_DONE,
- LOG_DS_USER_HOLD,
- LOG_DS_USER_RELEASE,
- LOG_POOL_SPLIT,
- LOG_END
-} history_internal_events_t;
-
#ifdef __cplusplus
}
#endif
--- a/usr/src/uts/common/sys/sunddi.h Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/common/sys/sunddi.h Sun Aug 12 11:56:48 2012 +0100
@@ -22,6 +22,7 @@
/*
* Copyright (c) 1990, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright 2012 Garrett D'Amore <[email protected]>. All rights reserved.
+ * Copyright (c) 2012 by Delphix. All rights reserved.
*/
#ifndef _SYS_SUNDDI_H
@@ -460,6 +461,7 @@
extern size_t strlcat(char *, const char *, size_t);
extern size_t strlcpy(char *, const char *, size_t);
extern size_t strspn(const char *, const char *);
+extern size_t strcspn(const char *, const char *);
extern int bcmp(const void *, const void *, size_t) __PURE;
extern int stoi(char **);
extern void numtos(ulong_t, char *);
--- a/usr/src/uts/intel/io/acpica/acpi_enum.c Sat Jun 30 11:33:30 2012 +0100
+++ b/usr/src/uts/intel/io/acpica/acpi_enum.c Sun Aug 12 11:56:48 2012 +0100
@@ -19,6 +19,8 @@
* CDDL HEADER END
*/
/*
+ * Copyright (c) 2012 Gary Mills
+ *
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
@@ -436,7 +438,7 @@
}
static ACPI_STATUS
-parse_resources(ACPI_HANDLE handle, dev_info_t *xdip)
+parse_resources(ACPI_HANDLE handle, dev_info_t *xdip, char *path)
{
ACPI_BUFFER buf;
ACPI_RESOURCE *resource_ptr;
@@ -448,8 +450,26 @@
buf.Length = ACPI_ALLOCATE_BUFFER;
status = AcpiGetCurrentResources(handle, &buf);
- if (status != AE_OK) {
+ switch (status) {
+ case AE_OK:
+ break;
+ case AE_NOT_FOUND:
+ /*
+ * Workaround for faulty DSDT tables that omit the _CRS
+ * method for the UAR3 device but have a valid _PRS method
+ * for that device.
+ */
+ status = AcpiGetPossibleResources(handle, &buf);
+ if (status != AE_OK) {
+ return (status);
+ }
+ break;
+ default:
+ cmn_err(CE_WARN,
+ "!AcpiGetCurrentResources failed for %s, exception: %s",
+ path, AcpiFormatException(status));
return (status);
+ break;
}
io = (struct regspec *)kmem_zalloc(sizeof (struct regspec) *
MAX_PARSED_ACPI_RESOURCES, KM_SLEEP);
@@ -803,6 +823,11 @@
* Bit 2 -- device is shown in UI
*/
if (!((info->CurrentStatus & 0x7) == 7)) {
+ if (acpi_enum_debug & DEVICES_NOT_ENUMED) {
+ cmn_err(CE_NOTE, "parse_resources() "
+ "Bad status 0x%x for %s",
+ info->CurrentStatus, path);
+ }
goto done;
}
} else {
@@ -815,6 +840,10 @@
*/
if (!(info->Valid & ACPI_VALID_HID)) {
/* No _HID, we skip this node */
+ if (acpi_enum_debug & DEVICES_NOT_ENUMED) {
+ cmn_err(CE_NOTE, "parse_resources() "
+ "No _HID for %s", path);
+ }
goto done;
}
hidstr = info->HardwareId.String;
@@ -896,7 +925,7 @@
(void) ndi_prop_update_string(DDI_DEV_T_NONE,
xdip, "model", "PNP0Fxx mouse");
} else {
- (void) parse_resources(ObjHandle, xdip);
+ (void) parse_resources(ObjHandle, xdip, path);
goto done;
}
}
@@ -905,7 +934,7 @@
(void) ndi_prop_update_string(DDI_DEV_T_NONE, xdip, "acpi-namespace",
path);
- (void) parse_resources(ObjHandle, xdip);
+ (void) parse_resources(ObjHandle, xdip, path);
/* Special processing for mouse and keyboard devices per IEEE 1275 */
/* if master entry doesn't contain "compatible" then we add default */
@@ -1056,9 +1085,12 @@
process_master_file();
/*
- * Do the actual enumeration
+ * Do the actual enumeration. Avoid AcpiGetDevices because it
+ * has an unnecessary internal callback that duplicates
+ * determining if the device is present.
*/
- (void) AcpiGetDevices(NULL, isa_acpi_callback, isa_dip, 0);
+ (void) AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
+ UINT32_MAX, isa_acpi_callback, NULL, isa_dip, NULL);
free_master_data();
used_res_interrupts();