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1 diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c |
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2 index cdaa9ef..c6e3c9f 100644 |
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3 --- a/src/AtomBios/Decoder.c |
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4 +++ b/src/AtomBios/Decoder.c |
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5 @@ -210,7 +210,7 @@ CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTa |
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6 { |
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7 IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); |
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8 (*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); |
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9 -#if (PARSER_TYPE!=DRIVER_TYPE_PARSER) |
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10 +#if (!defined(__sparc__) && (PARSER_TYPE!=DRIVER_TYPE_PARSER)) |
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11 BIOS_STACK_MODIFIER(); |
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12 #endif |
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13 } |
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14 diff --git a/src/AtomBios/hwserv_drv.c b/src/AtomBios/hwserv_drv.c |
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15 index a5f5a5b..2a454a4 100644 |
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16 --- a/src/AtomBios/hwserv_drv.c |
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17 +++ b/src/AtomBios/hwserv_drv.c |
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18 @@ -105,6 +105,10 @@ UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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19 CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT8)); |
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20 return rvl; |
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21 } |
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22 +#else |
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23 +UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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24 +{ |
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25 +} |
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26 #endif |
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27 |
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28 |
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29 @@ -117,6 +121,10 @@ UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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30 return rvl; |
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31 |
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32 } |
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33 +#else |
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34 +UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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35 +{ |
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36 +} |
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37 #endif |
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38 |
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39 |
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40 @@ -129,6 +137,10 @@ UINT32 ReadPCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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41 CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT32)); |
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42 return rvl; |
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43 } |
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44 +#else |
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45 +UINT32 ReadPCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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46 +{ |
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47 +} |
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48 #endif |
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49 |
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50 |
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51 @@ -142,6 +154,10 @@ VOID WritePCIReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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52 |
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53 } |
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54 |
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55 +#else |
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56 +VOID WritePCIReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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57 +{ |
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58 +} |
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59 #endif |
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60 |
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61 |
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62 @@ -152,6 +168,10 @@ VOID WritePCIReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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63 CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT16)); |
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64 } |
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65 |
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66 +#else |
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67 +VOID WritePCIReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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68 +{ |
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69 +} |
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70 #endif |
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71 |
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72 |
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73 @@ -160,6 +180,10 @@ VOID WritePCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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74 { |
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75 CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT32)); |
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76 } |
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77 +#else |
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78 +VOID WritePCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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79 +{ |
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80 +} |
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81 #endif |
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82 |
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83 |
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84 @@ -174,6 +198,10 @@ UINT8 ReadSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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85 //rvl= (UINT8) ReadGenericPciCfg(dev,reg,sizeof(UINT8)); |
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86 return rvl; |
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87 } |
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88 +#else |
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89 +UINT8 ReadSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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90 +{ |
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91 +} |
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92 #endif |
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93 |
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94 |
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95 @@ -187,6 +215,10 @@ UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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96 return rvl; |
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97 |
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98 } |
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99 +#else |
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100 +UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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101 +{ |
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102 +} |
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103 #endif |
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104 |
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105 |
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106 @@ -200,6 +232,10 @@ UINT32 ReadSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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107 //rvl= (UINT32) ReadGenericPciCfg(dev,reg,sizeof(UINT32)); |
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108 return rvl; |
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109 } |
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110 +#else |
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111 +UINT32 ReadSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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112 +{ |
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113 +} |
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114 #endif |
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115 |
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116 |
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117 @@ -212,6 +248,10 @@ VOID WriteSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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118 //WriteGenericPciCfg(dev,reg,sizeof(UINT8),(UINT32)value); |
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119 } |
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120 |
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121 +#else |
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122 +VOID WriteSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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123 +{ |
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124 +} |
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125 #endif |
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126 |
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127 |
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128 @@ -222,6 +262,10 @@ VOID WriteSysIOReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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129 //WriteGenericPciCfg(dev,reg,sizeof(UINT16),(UINT32)value); |
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130 } |
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131 |
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132 +#else |
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133 +VOID WriteSysIOReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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134 +{ |
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135 +} |
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136 #endif |
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137 |
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138 |
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139 @@ -230,6 +274,10 @@ VOID WriteSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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140 { |
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141 //WriteGenericPciCfg(dev,reg,sizeof(UINT32),(UINT32)value); |
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142 } |
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143 +#else |
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144 +VOID WriteSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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145 +{ |
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146 +} |
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147 #endif |
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148 |
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149 // ATI Registers Memory Mapped Access |
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150 @@ -257,6 +305,24 @@ VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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151 CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1),pWorkingTableData->IndirectData ); |
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152 } |
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153 |
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154 +#else |
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155 +UINT32 ReadReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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156 +{ |
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157 +} |
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158 + |
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159 +VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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160 +{ |
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161 +} |
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162 + |
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163 + |
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164 +VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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165 +{ |
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166 +} |
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167 + |
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168 +VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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169 +{ |
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170 +} |
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171 + |
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172 #endif |
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173 |
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174 // ATI Registers IO Mapped Access |
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175 @@ -271,8 +337,17 @@ VOID WriteRegIO(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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176 { |
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177 // return CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32 ); |
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178 } |
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179 +#else |
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180 +UINT32 ReadRegIO (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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181 +{ |
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182 + return 0; |
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183 +} |
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184 +VOID WriteRegIO(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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185 +{ |
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186 +} |
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187 #endif |
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188 |
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189 +#if !defined(__sparc__) |
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190 // access to Frame buffer, dummy function, need more information to implement it |
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191 UINT32 ReadFrameBuffer32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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192 { |
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193 @@ -286,6 +361,15 @@ VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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194 CailWriteFBData(pWorkingTableData->pDeviceData->CAIL,(pWorkingTableData->Index <<2), pWorkingTableData->DestData32); |
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195 |
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196 } |
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197 +#else |
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198 +UINT32 ReadFrameBuffer32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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199 +{ |
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200 +} |
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201 + |
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202 +VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) |
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203 +{ |
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204 +} |
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205 +#endif /* __sparc__ */ |
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206 |
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207 |
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208 VOID *AllocateMemory(DEVICE_DATA *pDeviceData , UINT16 MemSize) |
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209 diff --git a/src/AtomBios/includes/CD_Structs.h b/src/AtomBios/includes/CD_Structs.h |
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210 index c43f81d..f61232a 100644 |
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211 --- a/src/AtomBios/includes/CD_Structs.h |
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212 +++ b/src/AtomBios/includes/CD_Structs.h |
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213 @@ -375,7 +375,7 @@ typedef UINT8 COMMAND_TYPE_OPCODE_ONLY; |
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214 typedef UINT8 COMMAND_HEADER_POINTER; |
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215 |
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216 |
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217 -#if (PARSER_TYPE==BIOS_TYPE_PARSER) |
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218 +#if (!defined(__sparc__) && (PARSER_TYPE==BIOS_TYPE_PARSER)) |
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219 |
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220 typedef struct _DEVICE_DATA { |
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221 UINT32 STACK_BASED *pParameterSpace; |
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222 diff --git a/src/AtomBios/includes/CD_binding.h b/src/AtomBios/includes/CD_binding.h |
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223 index 7b021d3..b74b5db 100644 |
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224 --- a/src/AtomBios/includes/CD_binding.h |
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225 +++ b/src/AtomBios/includes/CD_binding.h |
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226 @@ -36,7 +36,11 @@ |
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227 #define USE_SWITCH_COMMAND 1 |
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228 #define DRIVER_TYPE_PARSER 0x48 |
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229 |
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230 +#if !defined(__sparc__) |
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231 #define PARSER_TYPE DRIVER_TYPE_PARSER |
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232 +#else |
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233 +#define PARSER_TYPE 0 |
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234 +#endif /* __sparc__ */ |
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235 |
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236 #define AllocateWorkSpace(x,y) AllocateMemory(pDeviceData,y) |
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237 #define FreeWorkSpace(x,y) ReleaseMemory(x,y) |
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238 diff --git a/src/Makefile.am b/src/Makefile.am |
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239 index a146df3..7411677 100644 |
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240 --- a/src/Makefile.am |
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241 +++ b/src/Makefile.am |
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242 @@ -27,8 +27,6 @@ |
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243 # TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc. |
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244 |
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245 if DRI |
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246 -ATIMISC_DRI_SRCS = atidri.c |
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247 -R128_DRI_SRCS = r128_dri.c |
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248 RADEON_DRI_SRCS = radeon_dri.c |
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249 endif |
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250 |
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251 @@ -64,52 +62,17 @@ XMODE_SRCS=\ |
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252 modes/xf86Rotate.c \ |
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253 modes/xf86DiDGA.c |
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254 |
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255 -if ATIMISC_CPIO |
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256 -ATIMISC_CPIO_SOURCES = ativga.c ativgaio.c atibank.c atiwonder.c atiwonderio.c |
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257 -endif |
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258 - |
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259 -if ATIMISC_DGA |
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260 -ATIMISC_DGA_SOURCES = atidga.c |
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261 -endif |
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262 - |
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263 if USE_EXA |
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264 -ATIMISC_EXA_SOURCES = atimach64exa.c |
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265 RADEON_EXA_SOURCES = radeon_exa.c |
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266 endif |
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267 |
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268 -AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER -DFGL_LINUX -DDRIVER_PARSER |
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269 +AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER -DDRIVER_PARSER |
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270 INCLUDES = -I$(srcdir)/AtomBios/includes |
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271 |
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272 -ati_drv_la_LTLIBRARIES = ati_drv.la |
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273 -ati_drv_la_LDFLAGS = -module -avoid-version |
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274 -ati_drv_ladir = @moduledir@/drivers |
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275 -ati_drv_la_SOURCES = \ |
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276 - ati.c atimodule.c |
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277 - |
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278 -mach64_drv_la_LTLIBRARIES = mach64_drv.la |
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279 -mach64_drv_la_LDFLAGS = -module -avoid-version |
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280 -mach64_drv_ladir = @moduledir@/drivers |
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281 -mach64_drv_la_SOURCES = \ |
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282 - atibus.c atichip.c atiprobe.c atividmem.c \ |
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283 - atiadjust.c atiaudio.c aticlock.c aticonfig.c aticonsole.c \ |
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284 - atidac.c atidecoder.c atidsp.c atii2c.c \ |
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285 - atilock.c atimach64.c atimach64accel.c atimach64cursor.c \ |
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286 - atimach64i2c.c atimach64io.c atimach64xv.c atimode.c atipreinit.c \ |
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287 - atiprint.c atirgb514.c atiscreen.c atituner.c atiutil.c ativalid.c \ |
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288 - atiload.c atimisc.c atimach64probe.c $(ATIMISC_CPIO_SOURCES) \ |
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289 - $(ATIMISC_DGA_SOURCES) $(ATIMISC_DRI_SRCS) $(ATIMISC_EXA_SOURCES) |
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290 - |
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291 -r128_drv_la_LTLIBRARIES = r128_drv.la |
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292 -r128_drv_la_LDFLAGS = -module -avoid-version |
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293 -r128_drv_ladir = @moduledir@/drivers |
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294 -r128_drv_la_SOURCES = \ |
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295 - r128_accel.c r128_cursor.c r128_dga.c r128_driver.c \ |
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296 - r128_video.c r128_misc.c r128_probe.c $(R128_DRI_SRCS) |
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297 - |
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298 -radeon_drv_la_LTLIBRARIES = radeon_drv.la |
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299 -radeon_drv_la_LDFLAGS = -module -avoid-version |
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300 -radeon_drv_ladir = @moduledir@/drivers |
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301 -radeon_drv_la_SOURCES = \ |
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302 +efb_drv_la_LTLIBRARIES = efb_drv.la |
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303 +efb_drv_la_LDFLAGS = -module -avoid-version |
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304 +efb_drv_ladir = @moduledir@/drivers |
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305 +efb_drv_la_SOURCES = efb_driver.c \ |
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306 radeon_accel.c radeon_cursor.c radeon_dga.c \ |
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307 radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \ |
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308 radeon_vip.c radeon_misc.c radeon_probe.c \ |
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309 @@ -119,31 +82,10 @@ radeon_drv_la_SOURCES = \ |
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310 $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c |
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311 |
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312 if XMODES |
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313 -radeon_drv_la_SOURCES += \ |
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314 +efb_drv_la_SOURCES += \ |
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315 $(XMODE_SRCS) |
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316 endif |
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317 |
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318 -theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la |
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319 -theatre_detect_drv_la_LDFLAGS = -module -avoid-version |
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320 -theatre_detect_drv_ladir = @moduledir@/multimedia |
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321 -theatre_detect_drv_la_SOURCES = \ |
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322 - theatre_detect.c theatre_detect_module.c |
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323 - |
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324 -theatre_drv_la_LTLIBRARIES = theatre_drv.la |
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325 -theatre_drv_la_LDFLAGS = -module -avoid-version |
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326 -theatre_drv_ladir = @moduledir@/multimedia |
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327 - |
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328 -theatre_drv_la_SOURCES = \ |
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329 - theatre.c theatre_module.c |
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330 - |
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331 -theatre200_drv_la_LTLIBRARIES = theatre200_drv.la |
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332 -theatre200_drv_la_LDFLAGS = -module -avoid-version |
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333 -theatre200_drv_ladir = @moduledir@/multimedia |
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334 -theatre200_drv_la_CFLAGS = \ |
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335 - $(AM_CFLAGS) -DMICROC_DIR=\"$(theatre200_drv_ladir)\" |
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336 -theatre200_drv_la_SOURCES = \ |
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337 - theatre200.c theatre200_module.c |
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338 - |
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339 EXTRA_DIST = \ |
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340 $(XMODE_SRCS) \ |
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341 atimach64render.c \ |
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342 diff --git a/src/ati.c b/src/ati.c |
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343 index b3f07ca..084b27f 100644 |
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344 --- a/src/ati.c |
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345 +++ b/src/ati.c |
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346 @@ -68,7 +68,12 @@ |
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347 /* names duplicated from version headers */ |
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348 #define MACH64_DRIVER_NAME "mach64" |
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349 #define R128_DRIVER_NAME "r128" |
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350 + |
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351 +#if defined(__sparc__) |
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352 +#define RADEON_DRIVER_NAME "efb" |
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353 +#else |
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354 #define RADEON_DRIVER_NAME "radeon" |
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355 +#endif /* __sparc__ */ |
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356 |
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357 enum |
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358 { |
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359 diff --git a/src/aticonsole.c b/src/aticonsole.c |
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360 index 8efe897..aa3905a 100644 |
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361 --- a/src/aticonsole.c |
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362 +++ b/src/aticonsole.c |
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363 @@ -514,6 +514,20 @@ ATIEnterGraphics |
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364 ATIPtr pATI |
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365 ) |
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366 { |
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367 + unsigned int PciReg; |
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368 + pciConfigPtr pPCI; |
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369 + pciVideoPtr pVideo, *xf86PciVideoInfo = xf86GetPciVideoInfo(); |
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370 + |
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371 + pVideo = xf86PciVideoInfo[pScreenInfo->scrnIndex]; |
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372 + pPCI = pVideo->thisCard; |
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373 +/* |
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374 +* Possibly fix block I/O indicator in PCI configuration space. |
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375 +*/ |
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376 + PciReg = pciReadLong(pPCI->tag, PCI_REG_USERCONFIG); |
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377 + if (!(PciReg & 0x00000004U)) |
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378 + pciWriteLong(pPCI->tag, PCI_REG_USERCONFIG, PciReg | |
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379 + 0x00000004U); |
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380 + |
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381 /* Map apertures */ |
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382 if (!ATIMapApertures(pScreenInfo->scrnIndex, pATI)) |
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383 return FALSE; |
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384 diff --git a/src/radeon.h b/src/radeon.h |
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385 index 7d63f28..ddb779e 100644 |
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386 --- a/src/radeon.h |
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387 +++ b/src/radeon.h |
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388 @@ -167,7 +167,15 @@ typedef enum { |
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389 OPTION_TVDAC_LOAD_DETECT, |
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390 OPTION_FORCE_TVOUT, |
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391 OPTION_TVSTD, |
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392 - OPTION_IGNORE_LID_STATUS |
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393 + OPTION_IGNORE_LID_STATUS, |
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394 +#if defined(__sparc__) |
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395 + OPTION_DUAL_DISPLAY, |
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396 + OPTION_DUAL_DISPLAY_VERTICAL, |
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397 + OPTION_STREAM_XOFFSET, |
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398 + OPTION_STREAM_YOFFSET, |
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399 + OPTION_OUTPUTS, |
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400 + OPTION_DISABLE_RANDR, |
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401 +#endif |
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402 } RADEONOpts; |
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403 |
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404 |
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405 @@ -734,6 +742,12 @@ typedef struct { |
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406 |
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407 Bool r600_shadow_fb; |
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408 void *fb_shadow; |
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409 + |
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410 +#if defined(__sparc__) |
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411 + char *deviceName; |
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412 + int fd; |
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413 +#endif /* __sparc__ */ |
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414 + |
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415 } RADEONInfoRec, *RADEONInfoPtr; |
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416 |
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417 #define RADEONWaitForFifo(pScrn, entries) \ |
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418 @@ -1182,4 +1196,8 @@ static __inline__ int radeon_timedout(const struct timeval *endtime) |
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419 now.tv_usec > endtime->tv_usec : now.tv_sec > endtime->tv_sec; |
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420 } |
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421 |
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422 +#if defined(__sparc__) |
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423 +#include "efb.h" |
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424 +#endif /* __sparc__ */ |
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425 + |
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426 #endif /* _RADEON_H_ */ |
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427 diff --git a/src/radeon_accel.c b/src/radeon_accel.c |
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428 index 8b2f167..b581719 100644 |
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429 --- a/src/radeon_accel.c |
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430 +++ b/src/radeon_accel.c |
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431 @@ -280,7 +280,11 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) |
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432 INREG(RADEON_RBBM_SOFT_RESET); |
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433 } |
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434 |
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435 +#if !defined(__sparc__) |
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436 + // soft reset the HDP causes system panic on some SPARC machines |
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437 OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET); |
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438 +#endif |
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439 + |
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440 INREG(RADEON_HOST_PATH_CNTL); |
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441 OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl); |
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442 |
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443 diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c |
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444 index e3b37c1..52856ec 100644 |
|
445 --- a/src/radeon_accelfuncs.c |
|
446 +++ b/src/radeon_accelfuncs.c |
|
447 @@ -723,7 +723,11 @@ FUNC_NAME(RADEONSetupForScanlineCPUToScreenColorExpandFill)(ScrnInfoPtr pScrn, |
|
448 #else |
|
449 BEGIN_ACCEL(5); |
|
450 |
|
451 +#if !defined(__sparc__) |
|
452 OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); |
|
453 +#else |
|
454 + OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT); |
|
455 +#endif |
|
456 #endif |
|
457 OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip); |
|
458 OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); |
|
459 diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h |
|
460 index 9cb279e..ba1b462 100644 |
|
461 --- a/src/radeon_atombios.h |
|
462 +++ b/src/radeon_atombios.h |
|
463 @@ -245,9 +245,13 @@ typedef struct _atomBiosHandle { |
|
464 unsigned int BIOSImageSize; |
|
465 } atomBiosHandleRec; |
|
466 |
|
467 -# endif |
|
468 - |
|
469 extern Bool |
|
470 RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, int32_t *pixel_clock); |
|
471 |
|
472 +#else |
|
473 + |
|
474 +extern Bool |
|
475 +RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, void *crtc_timing, int32_t *pixel_clock); |
|
476 + |
|
477 +#endif |
|
478 #endif /* RHD_ATOMBIOS_H_ */ |
|
479 diff --git a/src/radeon_common.h b/src/radeon_common.h |
|
480 index 467addf..c081088 100644 |
|
481 --- a/src/radeon_common.h |
|
482 +++ b/src/radeon_common.h |
|
483 @@ -73,6 +73,7 @@ |
|
484 #define DRM_RADEON_SETPARAM 0x19 |
|
485 #define DRM_RADEON_SURF_ALLOC 0x1a |
|
486 #define DRM_RADEON_SURF_FREE 0x1b |
|
487 +#define DRM_RADEON_GET_PCICONFIG 0x1c |
|
488 #define DRM_RADEON_MAX_DRM_COMMAND_INDEX 0x39 |
|
489 |
|
490 |
|
491 diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c |
|
492 index 8c4b598..2ff5bcb 100644 |
|
493 --- a/src/radeon_commonfuncs.c |
|
494 +++ b/src/radeon_commonfuncs.c |
|
495 @@ -285,12 +285,34 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) |
|
496 RADEONWaitForFifoFunction(pScrn, 64); |
|
497 |
|
498 for (;;) { |
|
499 + |
|
500 + /* execute a tight loop to wait for idle. If timeout, then |
|
501 + execute a slower loop for half a second. If then timeout, |
|
502 + reset the engine. |
|
503 + */ |
|
504 for (i = 0; i < RADEON_TIMEOUT; i++) { |
|
505 if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { |
|
506 RADEONEngineFlush(pScrn); |
|
507 return; |
|
508 } |
|
509 } |
|
510 + |
|
511 +#ifdef __sparc__ |
|
512 + { |
|
513 + hrtime_t limit; |
|
514 + limit = gethrtime() + (hrtime_t)1000000000; /* 1000 ms from now */ |
|
515 + while (((unsigned int)(INREG(RADEON_RBBM_STATUS)) & RADEON_RBBM_ACTIVE) |
|
516 + && (gethrtime() < limit)) { |
|
517 + yield(); |
|
518 + } |
|
519 + } |
|
520 + |
|
521 + if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { |
|
522 + RADEONEngineFlush(pScrn); |
|
523 + return; |
|
524 + } |
|
525 +#endif /* __sparc__ */ |
|
526 + |
|
527 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, |
|
528 "Idle timed out: %u entries, stat=0x%08x\n", |
|
529 (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, |
|
530 diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c |
|
531 index 3524b75..da1153a 100644 |
|
532 --- a/src/radeon_crtc.c |
|
533 +++ b/src/radeon_crtc.c |
|
534 @@ -218,6 +218,11 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, |
|
535 } else { |
|
536 legacy_crtc_mode_set(crtc, mode, adjusted_mode, x, y); |
|
537 } |
|
538 + |
|
539 +#if defined(__sparc__) |
|
540 + pScrn->currentMode = mode; |
|
541 + EFBNotifyModeChanged(pScrn); |
|
542 +#endif |
|
543 } |
|
544 |
|
545 static void |
|
546 @@ -238,6 +243,9 @@ radeon_crtc_mode_commit(xf86CrtcPtr crtc) |
|
547 } |
|
548 |
|
549 radeon_crtc_dpms(crtc, DPMSModeOn); |
|
550 + |
|
551 + if (crtc->scrn->pScreen != NULL) |
|
552 + xf86_reload_cursors (crtc->scrn->pScreen); |
|
553 } |
|
554 |
|
555 void |
|
556 diff --git a/src/radeon_dri.h b/src/radeon_dri.h |
|
557 index 3b54626..57ff2d8 100644 |
|
558 --- a/src/radeon_dri.h |
|
559 +++ b/src/radeon_dri.h |
|
560 @@ -80,20 +80,25 @@ typedef struct { |
|
561 /* MMIO register data */ |
|
562 drm_handle_t registerHandle; |
|
563 drmSize registerSize; |
|
564 + int padding0; |
|
565 |
|
566 /* CP in-memory status information */ |
|
567 drm_handle_t statusHandle; |
|
568 drmSize statusSize; |
|
569 + int padding1; |
|
570 |
|
571 /* CP GART Texture data */ |
|
572 drm_handle_t gartTexHandle; |
|
573 drmSize gartTexMapSize; |
|
574 + int padding2; |
|
575 int log2GARTTexGran; |
|
576 int gartTexOffset; |
|
577 unsigned int sarea_priv_offset; |
|
578 |
|
579 #ifdef PER_CONTEXT_SAREA |
|
580 drmSize perctx_sarea_size; |
|
581 +#else |
|
582 + int padding3; |
|
583 #endif |
|
584 } RADEONDRIRec, *RADEONDRIPtr; |
|
585 |
|
586 diff --git a/src/radeon_driver.c b/src/radeon_driver.c |
|
587 index 25d912d..095d71b 100644 |
|
588 --- a/src/radeon_driver.c |
|
589 +++ b/src/radeon_driver.c |
|
590 @@ -115,6 +115,10 @@ |
|
591 |
|
592 #include "radeon_chipinfo_gen.h" |
|
593 |
|
594 +#if defined(__sparc__) |
|
595 +#include "efb.h" |
|
596 +#endif /* __sparc__ */ |
|
597 + |
|
598 /* Forward definitions for driver functions */ |
|
599 static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen); |
|
600 static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode); |
|
601 @@ -221,6 +225,14 @@ static const OptionInfoRec RADEONOptions[] = { |
|
602 { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, |
|
603 { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, |
|
604 { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, |
|
605 +#if defined(__sparc__) |
|
606 + { OPTION_DUAL_DISPLAY, "DoubleWide", OPTV_STRING, {0}, FALSE }, |
|
607 + { OPTION_DUAL_DISPLAY_VERTICAL, "DoubleHigh", OPTV_STRING, {0}, FALSE }, |
|
608 + { OPTION_STREAM_XOFFSET, "StreamXOffset", OPTV_INTEGER, {0}, FALSE }, |
|
609 + { OPTION_STREAM_YOFFSET, "StreamYOffset", OPTV_INTEGER, {0}, FALSE }, |
|
610 + { OPTION_OUTPUTS, "Outputs", OPTV_STRING, {0}, FALSE }, |
|
611 + { OPTION_DISABLE_RANDR, "DisableRANDR", OPTV_BOOLEAN, {0}, FALSE }, |
|
612 +#endif /* __sparc__ */ |
|
613 { -1, NULL, OPTV_NONE, {0}, FALSE } |
|
614 }; |
|
615 |
|
616 @@ -367,7 +379,7 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) |
|
617 } |
|
618 |
|
619 /* Allocate our private RADEONInfoRec */ |
|
620 -static Bool RADEONGetRec(ScrnInfoPtr pScrn) |
|
621 +Bool RADEONGetRec(ScrnInfoPtr pScrn) |
|
622 { |
|
623 if (pScrn->driverPrivate) return TRUE; |
|
624 |
|
625 @@ -383,6 +395,41 @@ static void RADEONFreeRec(ScrnInfoPtr pScrn) |
|
626 pScrn->driverPrivate = NULL; |
|
627 } |
|
628 |
|
629 +static pciVideoPtr RADEONGetPciInfo(RADEONInfoPtr info) |
|
630 +{ |
|
631 +#if !defined(__sparc__) |
|
632 + return (xf86GetPciInfoForEntity(info->pEnt->index)); |
|
633 +#else |
|
634 + return (EFBGetPciInfo(info)); |
|
635 +#endif |
|
636 +} |
|
637 + |
|
638 + |
|
639 +pointer |
|
640 +RADEONMapVidMem(ScrnInfoPtr pScrn, unsigned int flags, PCITAG picTag, |
|
641 + unsigned long base, unsigned long size) |
|
642 +{ |
|
643 +#if !defined(__sparc__) |
|
644 + return (xf86MapPciMem(pScrn->scrnIndex, flags, pciTag, base, size)); |
|
645 +#else |
|
646 + return (EFBMapVidMem(pScrn, flags, picTag, base, size)); |
|
647 +#endif /* sparc */ |
|
648 +} |
|
649 + |
|
650 +void |
|
651 +RADEONUnmapVidMem(ScrnInfoPtr pScrn, pointer base, unsigned long size) |
|
652 +{ |
|
653 +#if !defined(__sparc__) |
|
654 + xf86UnMapVidMem(pScrn->scrnIndex, base, size); |
|
655 +#else |
|
656 + EFBUnmapVidMem(pScrn, base, size); |
|
657 +#endif |
|
658 + |
|
659 + return; |
|
660 +} |
|
661 + |
|
662 + |
|
663 + |
|
664 /* Memory map the MMIO region. Used during pre-init and by RADEONMapMem, |
|
665 * below |
|
666 */ |
|
667 @@ -390,9 +437,9 @@ static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) |
|
668 { |
|
669 RADEONInfoPtr info = RADEONPTR(pScrn); |
|
670 |
|
671 -#ifndef XSERVER_LIBPCIACCESS |
|
672 +#if !defined(XSERVER_LIBPCIACCESS) || defined(__sparc__) |
|
673 |
|
674 - info->MMIO = xf86MapPciMem(pScrn->scrnIndex, |
|
675 + info->MMIO = RADEONMapVidMem(pScrn, |
|
676 VIDMEM_MMIO | VIDMEM_READSIDEEFFECT, |
|
677 info->PciTag, |
|
678 info->MMIOAddr, |
|
679 @@ -428,8 +475,8 @@ static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) |
|
680 { |
|
681 RADEONInfoPtr info = RADEONPTR(pScrn); |
|
682 |
|
683 -#ifndef XSERVER_LIBPCIACCESS |
|
684 - xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize); |
|
685 +#if !defined(XSERVER_LIBPCIACCESS) || defined(__sparc__) |
|
686 + RADEONUnmapVidMem(pScrn, info->MMIO, info->MMIOSize); |
|
687 #else |
|
688 pci_device_unmap_range(info->PciInfo, info->MMIO, info->MMIOSize); |
|
689 #endif |
|
690 @@ -446,9 +493,9 @@ static Bool RADEONMapFB(ScrnInfoPtr pScrn) |
|
691 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, |
|
692 "Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); |
|
693 |
|
694 -#ifndef XSERVER_LIBPCIACCESS |
|
695 +#if !defined(XSERVER_LIBPCIACCESS) || defined(__sparc__) |
|
696 |
|
697 - info->FB = xf86MapPciMem(pScrn->scrnIndex, |
|
698 + info->FB = RADEONMapVidMem(pScrn, |
|
699 VIDMEM_FRAMEBUFFER, |
|
700 info->PciTag, |
|
701 info->LinearAddr, |
|
702 @@ -482,8 +529,8 @@ static Bool RADEONUnmapFB(ScrnInfoPtr pScrn) |
|
703 { |
|
704 RADEONInfoPtr info = RADEONPTR(pScrn); |
|
705 |
|
706 -#ifndef XSERVER_LIBPCIACCESS |
|
707 - xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize); |
|
708 +#if !defined(XSERVER_LIBPCIACCESS) || defined(__sparc__) |
|
709 + RADEONUnmapVidMem(pScrn, info->FB, info->FbMapSize); |
|
710 #else |
|
711 pci_device_unmap_range(info->PciInfo, info->FB, info->FbMapSize); |
|
712 #endif |
|
713 @@ -1261,6 +1308,10 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) |
|
714 } |
|
715 #endif |
|
716 |
|
717 +#if !defined(__sparc__) |
|
718 + // |
|
719 + // don't reinitialize mc_fb_location on sparc |
|
720 + // |
|
721 if (info->ChipFamily != CHIP_FAMILY_RS690) { |
|
722 if (info->IsIGP) |
|
723 info->mc_fb_location = INREG(RADEON_NB_TOM); |
|
724 @@ -1306,6 +1357,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) |
|
725 } |
|
726 } |
|
727 } |
|
728 +#endif |
|
729 + |
|
730 if (info->ChipFamily >= CHIP_FAMILY_R600) { |
|
731 info->fbLocation = (info->mc_fb_location & 0xffff) << 24; |
|
732 } else { |
|
733 @@ -1429,6 +1482,12 @@ static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) |
|
734 return aper_size * 2; |
|
735 } |
|
736 |
|
737 +#if defined(__sparc__) |
|
738 + else if (info->ChipFamily == CHIP_FAMILY_RV100) { |
|
739 + return aper_size; |
|
740 + } |
|
741 +#endif /* __sparc__ */ |
|
742 + |
|
743 /* Older cards have all sorts of funny issues to deal with. First |
|
744 * check if it's a multifunction card by reading the PCI config |
|
745 * header type... Limit those to one aperture size |
|
746 @@ -1492,8 +1551,12 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) |
|
747 bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024; |
|
748 if (bar_size == 0) |
|
749 bar_size = 0x20000; |
|
750 + |
|
751 + |
|
752 +#if ccl |
|
753 if (accessible > bar_size) |
|
754 accessible = bar_size; |
|
755 +#endif |
|
756 |
|
757 xf86DrvMsg(pScrn->scrnIndex, X_INFO, |
|
758 "Detected total video RAM=%dK, accessible=%uK (PCI BAR=%uK)\n", |
|
759 @@ -2190,8 +2253,16 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) |
|
760 { |
|
761 RADEONInfoPtr info = RADEONPTR(pScrn); |
|
762 |
|
763 +#if !defined(__sparc__) |
|
764 info->allowColorTiling = xf86ReturnOptValBool(info->Options, |
|
765 OPTION_COLOR_TILING, TRUE); |
|
766 +#else |
|
767 + /* |
|
768 + * disable Tiling for now because of coherent console |
|
769 + */ |
|
770 + info->allowColorTiling = FALSE; |
|
771 +#endif /* __sparc__ */ |
|
772 + |
|
773 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { |
|
774 /* this may be 4096 on r4xx -- need to double check */ |
|
775 info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ |
|
776 @@ -2551,6 +2622,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) |
|
777 info->IsPrimary = FALSE; |
|
778 |
|
779 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); |
|
780 + |
|
781 +#if defined(__sparc__) |
|
782 + if (info->fd == -1) { |
|
783 + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, |
|
784 + "invalid device %s\n", info->deviceName); |
|
785 + goto fail1; |
|
786 + } |
|
787 + info->pEnt->location.type = BUS_PCI; |
|
788 +#endif /* __sparc__ */ |
|
789 + |
|
790 if (info->pEnt->location.type != BUS_PCI) goto fail; |
|
791 |
|
792 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], |
|
793 @@ -2580,7 +2661,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) |
|
794 info->ModeReg = &pRADEONEnt->ModeReg; |
|
795 } |
|
796 |
|
797 - info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); |
|
798 + info->PciInfo = RADEONGetPciInfo(info); |
|
799 info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), |
|
800 PCI_DEV_DEV(info->PciInfo), |
|
801 PCI_DEV_FUNC(info->PciInfo)); |
|
802 @@ -2639,8 +2720,10 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) |
|
803 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) |
|
804 goto fail; |
|
805 |
|
806 +#if !defined(__sparc__) |
|
807 if (xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr)) |
|
808 goto fail; |
|
809 +#endif /* __sparc__ */ |
|
810 |
|
811 pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; |
|
812 #endif |
|
813 @@ -2693,7 +2776,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) |
|
814 if (!RADEONPreInitWeight(pScrn)) |
|
815 goto fail; |
|
816 |
|
817 +#if !defined(__sparc__) |
|
818 info->DispPriority = 1; |
|
819 +#else |
|
820 + info->DispPriority = 2; |
|
821 +#endif /* __sparc__ */ |
|
822 + |
|
823 if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { |
|
824 if (strcmp(s, "AUTO") == 0) { |
|
825 info->DispPriority = 1; |
|
826 @@ -2713,7 +2801,9 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) |
|
827 if (!RADEONPreInitChipType(pScrn)) |
|
828 goto fail; |
|
829 |
|
830 +#if !defined(__sparc__) |
|
831 RADEONPreInitBIOS(pScrn, pInt10); |
|
832 +#endif /* __sparc__ */ |
|
833 |
|
834 #ifdef XF86DRI |
|
835 /* PreInit DRI first of all since we need that for getting a proper |
|
836 @@ -2726,6 +2816,15 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) |
|
837 |
|
838 RADEONPreInitColorTiling(pScrn); |
|
839 |
|
840 +#if defined(__sparc__) |
|
841 + RADEONPreInitDDC(pScrn); |
|
842 + |
|
843 + if (!RADEONPreInitControllers(pScrn)) |
|
844 + goto fail; |
|
845 + |
|
846 + EFBPreInitOutputConfiguration(pScrn, xf86_config); |
|
847 +#endif /* __sparc__ */ |
|
848 + |
|
849 /* we really need an FB manager... */ |
|
850 if (pScrn->display->virtualX) { |
|
851 crtc_max_X = pScrn->display->virtualX; |
|
852 @@ -2767,10 +2866,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) |
|
853 /*xf86CrtcSetSizeRange (pScrn, 320, 200, info->MaxSurfaceWidth, info->MaxLines);*/ |
|
854 xf86CrtcSetSizeRange (pScrn, 320, 200, crtc_max_X, crtc_max_Y); |
|
855 |
|
856 +#if !defined(__sparc__) |
|
857 RADEONPreInitDDC(pScrn); |
|
858 |
|
859 if (!RADEONPreInitControllers(pScrn)) |
|
860 goto fail; |
|
861 +#endif /* __sparc__ */ |
|
862 |
|
863 |
|
864 ErrorF("before xf86InitialConfiguration\n"); |
|
865 @@ -2985,6 +3086,7 @@ RADEONPointerMoved(int index, int x, int y) |
|
866 (*info->PointerMoved)(index, newX, newY); |
|
867 } |
|
868 |
|
869 +#if !defined(__sparc__) |
|
870 static void |
|
871 RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) |
|
872 { |
|
873 @@ -3028,6 +3130,7 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) |
|
874 } |
|
875 |
|
876 } |
|
877 +#endif /* __sparc__ */ |
|
878 |
|
879 |
|
880 /* Called at the start of each server generation. */ |
|
881 @@ -3077,8 +3180,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, |
|
882 |
|
883 RADEONSave(pScrn); |
|
884 |
|
885 +#if !defined(__sparc__) |
|
886 /* set initial bios scratch reg state */ |
|
887 RADEONInitBIOSRegisters(pScrn); |
|
888 +#endif /* __sparc__ */ |
|
889 |
|
890 /* blank the outputs/crtcs */ |
|
891 RADEONBlank(pScrn); |
|
892 @@ -3514,6 +3619,13 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, |
|
893 if (!xf86CrtcScreenInit (pScreen)) |
|
894 return FALSE; |
|
895 |
|
896 +#if defined(__sparc__) |
|
897 + /* |
|
898 + * Give the sparc driver a chance to do any necessary initialization |
|
899 + */ |
|
900 + EFBScreenInit(pScrn); |
|
901 +#endif /* __sparc__ */ |
|
902 + |
|
903 /* Wrap pointer motion to flip touch screen around */ |
|
904 info->PointerMoved = pScrn->PointerMoved; |
|
905 pScrn->PointerMoved = RADEONPointerMoved; |
|
906 @@ -3623,7 +3735,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, |
|
907 * reprogrammed |
|
908 */ |
|
909 if (mc_fb_loc != restore->mc_fb_location || |
|
910 - mc_agp_loc != restore->mc_agp_location) { |
|
911 + mc_agp_loc != restore->mc_agp_location) |
|
912 + { |
|
913 CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; |
|
914 CARD32 old_mc_status, status_idle; |
|
915 |
|
916 @@ -4509,6 +4622,7 @@ void RADEONRestore(ScrnInfoPtr pScrn) |
|
917 RADEONRestoreMemMapRegisters(pScrn, restore); |
|
918 RADEONRestoreCommonRegisters(pScrn, restore); |
|
919 |
|
920 +#if !defined(__sparc__) |
|
921 if (pRADEONEnt->HasCRTC2) { |
|
922 RADEONRestoreCrtc2Registers(pScrn, restore); |
|
923 RADEONRestorePLL2Registers(pScrn, restore); |
|
924 @@ -4516,6 +4630,25 @@ void RADEONRestore(ScrnInfoPtr pScrn) |
|
925 |
|
926 RADEONRestoreCrtcRegisters(pScrn, restore); |
|
927 RADEONRestorePLLRegisters(pScrn, restore); |
|
928 +#else |
|
929 + /* |
|
930 + On sparc, leave the mode untouched when switching |
|
931 + back to the console mode, but make sure to leave |
|
932 + the CRT on |
|
933 + */ |
|
934 + if (pRADEONEnt->HasCRTC2) { |
|
935 + OUTREGP(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | 0x200), |
|
936 + ~(RADEON_CRTC2_EN | RADEON_CRTC2_DISP_REQ_EN_B | |
|
937 + 0xf00)); |
|
938 + } |
|
939 + |
|
940 + OUTREGP(RADEON_CRTC_EXT_CNTL, RADEON_CRTC_CRT_ON, |
|
941 + ~(RADEON_CRTC_CRT_ON)); |
|
942 + OUTREGP(RADEON_CRTC_GEN_CNTL, (RADEON_CRTC_EN), |
|
943 + ~(RADEON_CRTC_EN | RADEON_CRTC_DISP_REQ_EN_B |
|
944 + )); |
|
945 +#endif /* __sparc__ */ |
|
946 + |
|
947 RADEONRestoreRMXRegisters(pScrn, restore); |
|
948 RADEONRestoreFPRegisters(pScrn, restore); |
|
949 RADEONRestoreFP2Registers(pScrn, restore); |
|
950 @@ -4710,6 +4843,7 @@ ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode, |
|
951 RADEONInfoPtr info = RADEONPTR(pScrn); |
|
952 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); |
|
953 |
|
954 +#if !defined(__sparc__) |
|
955 /* |
|
956 * RN50 has effective maximum mode bandwidth of about 300MiB/s. |
|
957 * XXX should really do this for all chips by properly computing |
|
958 @@ -4719,6 +4853,7 @@ ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode, |
|
959 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) |
|
960 return MODE_BANDWIDTH; |
|
961 } |
|
962 +#endif |
|
963 |
|
964 /* There are problems with double scan mode at high clocks |
|
965 * They're likely related PLL and display buffer settings. |
|
966 @@ -5046,9 +5181,15 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) |
|
967 } |
|
968 #endif /* USE_XAA */ |
|
969 |
|
970 +#if !defined(__sparc__) |
|
971 + // |
|
972 + // When running on sparc, no need to restore the video state when |
|
973 + // switch back to console mode |
|
974 + // |
|
975 if (pScrn->vtSema) { |
|
976 RADEONRestore(pScrn); |
|
977 } |
|
978 +#endif /* __sparc__ */ |
|
979 |
|
980 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, |
|
981 "Disposing accel...\n"); |
|
982 @@ -5088,6 +5229,13 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) |
|
983 |
|
984 xf86ClearPrimInitDone(info->pEnt->index); |
|
985 |
|
986 +#if defined(__sparc__) |
|
987 + /* |
|
988 + * Give the sparc driver a chance to do any necessary cleanup |
|
989 + */ |
|
990 + EFBCloseScreen(pScrn); |
|
991 +#endif /* __sparc__ */ |
|
992 + |
|
993 pScreen->BlockHandler = info->BlockHandler; |
|
994 pScreen->CloseScreen = info->CloseScreen; |
|
995 return (*pScreen->CloseScreen)(scrnIndex, pScreen); |
|
996 diff --git a/src/radeon_macros.h b/src/radeon_macros.h |
|
997 index 7f532a8..b8e8218 100644 |
|
998 --- a/src/radeon_macros.h |
|
999 +++ b/src/radeon_macros.h |
|
1000 @@ -60,12 +60,40 @@ |
|
1001 (info->VBIOS[(v) + 3] << 24)) |
|
1002 |
|
1003 /* Memory mapped register access macros */ |
|
1004 +#if defined(__sparc__) |
|
1005 + |
|
1006 +#define READ_MMIO_UCHAR(base, offset) \ |
|
1007 + *((unsigned char *)((unsigned char *)base + (offset))) |
|
1008 + |
|
1009 +#define READ_MMIO_USHORT(base, offset) \ |
|
1010 + *((unsigned short *)((unsigned char *)base + (offset))) |
|
1011 + |
|
1012 +#define READ_MMIO_UINT(base, offset) \ |
|
1013 + *((unsigned int *)((unsigned char *)base + (offset))) |
|
1014 + |
|
1015 +#define WRITE_MMIO_UCHAR(base, offset, val) \ |
|
1016 + *((unsigned char *)((unsigned char *)base + (offset))) = val |
|
1017 + |
|
1018 +#define WRITE_MMIO_USHORT(base, offset, val) \ |
|
1019 + *((unsigned short *)((unsigned char *)base + (offset))) = val |
|
1020 + |
|
1021 +#define WRITE_MMIO_UINT(base, offset, val) \ |
|
1022 + *((unsigned int *)((unsigned char *)base + (offset))) = val |
|
1023 + |
|
1024 +#define INREG8(addr) READ_MMIO_UCHAR(RADEONMMIO, addr) |
|
1025 +#define INREG16(addr) READ_MMIO_USHORT(RADEONMMIO, addr) |
|
1026 +#define INREG(addr) READ_MMIO_UINT(RADEONMMIO, addr) |
|
1027 +#define OUTREG8(addr, val) WRITE_MMIO_UCHAR(RADEONMMIO, addr, val) |
|
1028 +#define OUTREG16(addr, val) WRITE_MMIO_USHORT(RADEONMMIO, addr, val) |
|
1029 +#define OUTREG(addr, val) WRITE_MMIO_UINT(RADEONMMIO, addr, val) |
|
1030 +#else |
|
1031 #define INREG8(addr) MMIO_IN8(RADEONMMIO, addr) |
|
1032 #define INREG16(addr) MMIO_IN16(RADEONMMIO, addr) |
|
1033 #define INREG(addr) MMIO_IN32(RADEONMMIO, addr) |
|
1034 #define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val) |
|
1035 #define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val) |
|
1036 #define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val) |
|
1037 +#endif /* __sparc__ */ |
|
1038 |
|
1039 #define ADDRREG(addr) ((volatile CARD32 *)(pointer)(RADEONMMIO + (addr))) |
|
1040 |
|
1041 diff --git a/src/radeon_modes.c b/src/radeon_modes.c |
|
1042 index 2c72395..140975f 100644 |
|
1043 --- a/src/radeon_modes.c |
|
1044 +++ b/src/radeon_modes.c |
|
1045 @@ -258,6 +258,18 @@ static void RADEONAddScreenModes(xf86OutputPtr output, DisplayModePtr *modeList) |
|
1046 } |
|
1047 |
|
1048 DisplayModePtr |
|
1049 +RADEONOutputGetEDIDModes(xf86OutputPtr output) |
|
1050 +{ |
|
1051 +#if !defined(__sparc__) |
|
1052 + return (xf86OutputGetEDIDModes(output)); |
|
1053 +#else |
|
1054 + extern DisplayModePtr EFBOutputGetEDIDModes(); |
|
1055 + |
|
1056 + return (EFBOutputGetEDIDModes(output)); |
|
1057 +#endif /* __sparc__ */ |
|
1058 +} |
|
1059 + |
|
1060 +DisplayModePtr |
|
1061 RADEONProbeOutputModes(xf86OutputPtr output) |
|
1062 { |
|
1063 RADEONOutputPrivatePtr radeon_output = output->driver_private; |
|
1064 @@ -283,7 +295,8 @@ RADEONProbeOutputModes(xf86OutputPtr output) |
|
1065 } |
|
1066 } else { |
|
1067 if (output->MonInfo) |
|
1068 - modes = xf86OutputGetEDIDModes (output); |
|
1069 + modes = RADEONOutputGetEDIDModes (output); |
|
1070 + |
|
1071 if (modes == NULL) { |
|
1072 if ((radeon_output->type == OUTPUT_LVDS) && info->IsAtomBios) { |
|
1073 atomBiosResult = RHDAtomBiosFunc(pScrn->scrnIndex, |
|
1074 @@ -292,7 +305,7 @@ RADEONProbeOutputModes(xf86OutputPtr output) |
|
1075 if (atomBiosResult == ATOM_SUCCESS) { |
|
1076 output->MonInfo = xf86InterpretEDID(pScrn->scrnIndex, |
|
1077 atomBiosArg.EDIDBlock); |
|
1078 - modes = xf86OutputGetEDIDModes(output); |
|
1079 + modes = RADEONOutputGetEDIDModes(output); |
|
1080 } |
|
1081 } |
|
1082 if (modes == NULL) { |
|
1083 diff --git a/src/radeon_output.c b/src/radeon_output.c |
|
1084 index aceb3d8..93c5654 100644 |
|
1085 --- a/src/radeon_output.c |
|
1086 +++ b/src/radeon_output.c |
|
1087 @@ -514,6 +514,7 @@ radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode) |
|
1088 RADEONInfoPtr info = RADEONPTR(pScrn); |
|
1089 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); |
|
1090 |
|
1091 +#if !defined(__sparc__) |
|
1092 /* |
|
1093 * RN50 has effective maximum mode bandwidth of about 300MiB/s. |
|
1094 * XXX should really do this for all chips by properly computing |
|
1095 @@ -523,6 +524,7 @@ radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode) |
|
1096 if (xf86ModeBandwidth(pMode, pScrn->bitsPerPixel) > 300) |
|
1097 return MODE_BANDWIDTH; |
|
1098 } |
|
1099 +#endif |
|
1100 |
|
1101 if (OUTPUT_IS_TV) { |
|
1102 /* FIXME: Update when more modes are added */ |
|
1103 @@ -670,6 +672,10 @@ radeon_bios_output_lock(xf86OutputPtr output, Bool lock) |
|
1104 unsigned char *RADEONMMIO = info->MMIO; |
|
1105 RADEONSavePtr save = info->ModeReg; |
|
1106 |
|
1107 +#if defined(__sparc__) |
|
1108 + return; |
|
1109 +#endif /* __sparc__ */ |
|
1110 + |
|
1111 if (info->IsAtomBios) { |
|
1112 if (lock) { |
|
1113 save->bios_6_scratch |= (ATOM_S6_CRITICAL_STATE | ATOM_S6_ACC_MODE); |
|
1114 @@ -698,6 +704,10 @@ radeon_bios_output_dpms(xf86OutputPtr output, int mode) |
|
1115 unsigned char *RADEONMMIO = info->MMIO; |
|
1116 RADEONSavePtr save = info->ModeReg; |
|
1117 |
|
1118 +#if defined(__sparc__) |
|
1119 + return; |
|
1120 +#endif /* __sparc__ */ |
|
1121 + |
|
1122 if (info->IsAtomBios) { |
|
1123 if (mode == DPMSModeOn) { |
|
1124 if (radeon_output->MonType == MT_STV || |
|
1125 @@ -845,6 +855,10 @@ radeon_bios_output_crtc(xf86OutputPtr output) |
|
1126 xf86CrtcPtr crtc = output->crtc; |
|
1127 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; |
|
1128 |
|
1129 +#if defined(__sparc__) |
|
1130 + return; |
|
1131 +#endif /* __sparc__ */ |
|
1132 + |
|
1133 if (info->IsAtomBios) { |
|
1134 if (radeon_output->MonType == MT_STV || |
|
1135 radeon_output->MonType == MT_CTV) { |
|
1136 @@ -924,6 +938,10 @@ radeon_bios_output_connected(xf86OutputPtr output, Bool connected) |
|
1137 unsigned char *RADEONMMIO = info->MMIO; |
|
1138 RADEONSavePtr save = info->ModeReg; |
|
1139 |
|
1140 +#if defined(__sparc__) |
|
1141 + return; |
|
1142 +#endif /* __sparc__ */ |
|
1143 + |
|
1144 if (info->ChipFamily >= CHIP_FAMILY_R600) |
|
1145 return; |
|
1146 |
|
1147 @@ -1577,6 +1595,23 @@ radeon_set_property(xf86OutputPtr output, Atom property, |
|
1148 return TRUE; |
|
1149 } |
|
1150 |
|
1151 +#if defined(__sparc__) |
|
1152 +static const xf86OutputFuncsRec radeon_output_funcs = { |
|
1153 + .create_resources = radeon_create_resources, |
|
1154 + .dpms = radeon_dpms, |
|
1155 + .save = radeon_save, |
|
1156 + .restore = radeon_restore, |
|
1157 + .mode_valid = radeon_mode_valid, |
|
1158 + .mode_fixup = radeon_mode_fixup, |
|
1159 + .prepare = radeon_mode_prepare, |
|
1160 + .mode_set = radeon_mode_set, |
|
1161 + .commit = radeon_mode_commit, |
|
1162 + .detect = radeon_detect, |
|
1163 + .get_modes = efb_get_modes, |
|
1164 + .set_property = radeon_set_property, |
|
1165 + .destroy = radeon_destroy |
|
1166 +}; |
|
1167 +#else |
|
1168 static const xf86OutputFuncsRec radeon_output_funcs = { |
|
1169 .create_resources = radeon_create_resources, |
|
1170 .dpms = radeon_dpms, |
|
1171 @@ -1592,6 +1627,7 @@ static const xf86OutputFuncsRec radeon_output_funcs = { |
|
1172 .set_property = radeon_set_property, |
|
1173 .destroy = radeon_destroy |
|
1174 }; |
|
1175 +#endif /* __sparc__ */ |
|
1176 |
|
1177 void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output) |
|
1178 { |
|
1179 @@ -2439,6 +2475,17 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) |
|
1180 info->BiosConnector[1].TMDSType = TMDS_EXT; |
|
1181 info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; |
|
1182 info->BiosConnector[1].valid = TRUE; |
|
1183 +#elif defined(__sparc__) |
|
1184 + info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); |
|
1185 + info->BiosConnector[1].DACType = DAC_PRIMARY; |
|
1186 + info->BiosConnector[1].TMDSType = TMDS_EXT; |
|
1187 + info->BiosConnector[1].valid = TRUE; |
|
1188 + |
|
1189 + if (info->ChipFamily == CHIP_FAMILY_RV380) { |
|
1190 + info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; |
|
1191 + } else { |
|
1192 + info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; |
|
1193 + } |
|
1194 #else |
|
1195 info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); |
|
1196 info->BiosConnector[1].DACType = DAC_PRIMARY; |
|
1197 @@ -2782,6 +2829,10 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) |
|
1198 but I'm not sure it's worth the trouble */ |
|
1199 output->possible_clones = 0; |
|
1200 |
|
1201 +#if defined(__sparc__) |
|
1202 + xf86OutputUseScreenMonitor(output, TRUE); |
|
1203 +#endif /* __sparc__ */ |
|
1204 + |
|
1205 RADEONInitConnector(output); |
|
1206 } |
|
1207 } |
|
1208 diff --git a/src/radeon_probe.c b/src/radeon_probe.c |
|
1209 index 36451f9..6f7eafa 100644 |
|
1210 --- a/src/radeon_probe.c |
|
1211 +++ b/src/radeon_probe.c |
|
1212 @@ -31,7 +31,9 @@ |
|
1213 #endif |
|
1214 |
|
1215 #include <string.h> |
|
1216 +#include <sys/fcntl.h> |
|
1217 |
|
1218 +#include <sys/visual_io.h> |
|
1219 /* |
|
1220 * Authors: |
|
1221 * Kevin E. Martin <[email protected]> |
|
1222 @@ -53,6 +55,7 @@ |
|
1223 #include "radeon_chipset_gen.h" |
|
1224 |
|
1225 #include "radeon_pci_chipset_gen.h" |
|
1226 +#include "radeon.h" |
|
1227 |
|
1228 |
|
1229 #ifdef XSERVER_LIBPCIACCESS |
|
1230 @@ -63,6 +66,7 @@ |
|
1231 static Bool RADEONProbe(DriverPtr drv, int flags); |
|
1232 #endif |
|
1233 |
|
1234 +_X_EXPORT |
|
1235 int gRADEONEntityIndex = -1; |
|
1236 |
|
1237 /* Return the options for supported chipset 'n'; NULL otherwise */ |
|
1238 @@ -81,18 +85,22 @@ RADEONIdentify(int flags) |
|
1239 RADEONChipsets); |
|
1240 } |
|
1241 |
|
1242 -static Bool |
|
1243 +static ScrnInfoPtr |
|
1244 radeon_get_scrninfo(int entity_num) |
|
1245 { |
|
1246 ScrnInfoPtr pScrn = NULL; |
|
1247 EntityInfoPtr pEnt; |
|
1248 |
|
1249 +#if !defined(__sparc__) |
|
1250 pScrn = xf86ConfigPciEntity(pScrn, 0, entity_num, RADEONPciChipsets, |
|
1251 NULL, |
|
1252 NULL, NULL, NULL, NULL); |
|
1253 +#else |
|
1254 + pScrn = xf86ConfigFbEntity(pScrn, 0, entity_num, NULL,NULL,NULL,NULL); |
|
1255 +#endif |
|
1256 |
|
1257 if (!pScrn) |
|
1258 - return FALSE; |
|
1259 + return NULL; |
|
1260 |
|
1261 pScrn->driverVersion = RADEON_VERSION_CURRENT; |
|
1262 pScrn->driverName = RADEON_DRIVER_NAME; |
|
1263 @@ -146,10 +154,14 @@ radeon_get_scrninfo(int entity_num) |
|
1264 |
|
1265 xfree(pEnt); |
|
1266 |
|
1267 - return TRUE; |
|
1268 + return pScrn; |
|
1269 } |
|
1270 |
|
1271 -#ifndef XSERVER_LIBPCIACCESS |
|
1272 +#if defined(__sparc__) |
|
1273 +#define RADEON_DEFAULT_DEVICE_PATH "/dev/fb" |
|
1274 +#endif /* __sparc__ */ |
|
1275 + |
|
1276 +#if !defined(XSERVER_LIBPCIACCESS) || defined(__sparc__) |
|
1277 |
|
1278 /* Return TRUE if chipset is present; FALSE otherwise. */ |
|
1279 static Bool |
|
1280 @@ -161,13 +173,17 @@ RADEONProbe(DriverPtr drv, int flags) |
|
1281 GDevPtr *devSections; |
|
1282 Bool foundScreen = FALSE; |
|
1283 int i; |
|
1284 + ScrnInfoPtr pScrn; |
|
1285 |
|
1286 +#if !defined(__sparc__) |
|
1287 if (!xf86GetPciVideoInfo()) return FALSE; |
|
1288 +#endif /* __sparc__ */ |
|
1289 |
|
1290 numDevSections = xf86MatchDevice(RADEON_NAME, &devSections); |
|
1291 |
|
1292 if (!numDevSections) return FALSE; |
|
1293 |
|
1294 +#if !defined(__sparc__) |
|
1295 numUsed = xf86MatchPciInstances(RADEON_NAME, |
|
1296 PCI_VENDOR_ATI, |
|
1297 RADEONChipsets, |
|
1298 @@ -183,12 +199,50 @@ RADEONProbe(DriverPtr drv, int flags) |
|
1299 foundScreen = TRUE; |
|
1300 } else { |
|
1301 for (i = 0; i < numUsed; i++) { |
|
1302 - if (radeon_get_scrninfo(usedChips[i])) |
|
1303 + if (pScrn = radeon_get_scrninfo(usedChips[i])) |
|
1304 foundScreen = TRUE; |
|
1305 } |
|
1306 } |
|
1307 |
|
1308 xfree(usedChips); |
|
1309 +#else |
|
1310 + |
|
1311 + |
|
1312 + // CR 6876840 - fix the core dump, but it still won't support |
|
1313 + // -configure option |
|
1314 + |
|
1315 + if (flags & PROBE_DETECT) { |
|
1316 + if (devSections) |
|
1317 + xfree(devSections); |
|
1318 + return TRUE; |
|
1319 + } |
|
1320 + |
|
1321 + for (i = 0; i < numDevSections; i++) { |
|
1322 + char * dev; |
|
1323 + int entity; |
|
1324 + RADEONInfoPtr info; |
|
1325 + int fd; |
|
1326 + |
|
1327 + entity = xf86ClaimFbSlot(drv, 0, devSections[i], TRUE); |
|
1328 + if (pScrn = radeon_get_scrninfo(entity)) { |
|
1329 + dev = xf86FindOptionValue(devSections[i]->options, "device"); |
|
1330 + if (dev == NULL) { |
|
1331 + dev = RADEON_DEFAULT_DEVICE_PATH; |
|
1332 + } |
|
1333 + |
|
1334 + if (((fd = open(dev, O_RDWR, 0)) >= 0)) { |
|
1335 + foundScreen = TRUE; |
|
1336 + } |
|
1337 + |
|
1338 + if (RADEONGetRec(pScrn)) { |
|
1339 + info = RADEONPTR(pScrn); |
|
1340 + info->deviceName = dev; |
|
1341 + info->fd = fd; |
|
1342 + } |
|
1343 + } |
|
1344 + } |
|
1345 +#endif /* __sparc__ */ |
|
1346 + |
|
1347 xfree(devSections); |
|
1348 |
|
1349 return foundScreen; |
|
1350 @@ -196,7 +250,7 @@ RADEONProbe(DriverPtr drv, int flags) |
|
1351 |
|
1352 #else /* XSERVER_LIBPCIACCESS */ |
|
1353 |
|
1354 -static Bool |
|
1355 +static ScrnInfoPtr |
|
1356 radeon_pci_probe( |
|
1357 DriverPtr pDriver, |
|
1358 int entity_num, |
|
1359 @@ -204,7 +258,48 @@ radeon_pci_probe( |
|
1360 intptr_t match_data |
|
1361 ) |
|
1362 { |
|
1363 - return radeon_get_scrninfo(entity_num); |
|
1364 + ScrnInfoPtr pScrn; |
|
1365 + pScrn = radeon_get_scrninfo(entity_num); |
|
1366 + |
|
1367 +#if defined(__sparc__) |
|
1368 + if (pScrn != NULL) { |
|
1369 + char * dev; |
|
1370 + RADEONInfoPtr info = NULL; |
|
1371 + int fd = -1; |
|
1372 + int i, numDevSections; |
|
1373 + GDevPtr *devSections; |
|
1374 + |
|
1375 + numDevSections = xf86MatchDevice(RADEON_NAME, &devSections); |
|
1376 + |
|
1377 + if (RADEONGetRec(pScrn)) { |
|
1378 + info = RADEONPTR(pScrn); |
|
1379 + info->fd = -1; |
|
1380 + } |
|
1381 + |
|
1382 + for (i = 0; i < numDevSections; i++) { |
|
1383 + dev = xf86FindOptionValue(devSections[i]->options, "device"); |
|
1384 + if (dev == NULL) { |
|
1385 + dev = RADEON_DEFAULT_DEVICE_PATH; |
|
1386 + } |
|
1387 + |
|
1388 + if (((fd = open(dev, O_RDWR, 0)) >= 0)) { |
|
1389 + if (RADEONGetRec(pScrn)) { |
|
1390 + info = RADEONPTR(pScrn); |
|
1391 + info->deviceName = dev; |
|
1392 + info->fd = fd; |
|
1393 + } |
|
1394 + } |
|
1395 + } |
|
1396 + |
|
1397 + if (info->fd == -1) { |
|
1398 + dev = RADEON_DEFAULT_DEVICE_PATH; |
|
1399 + info->deviceName = dev; |
|
1400 + info->fd = open(dev, O_RDWR, 0); |
|
1401 + } |
|
1402 + } |
|
1403 +#endif /* __sparc__ */ |
|
1404 + |
|
1405 + return pScrn; |
|
1406 } |
|
1407 |
|
1408 #endif /* XSERVER_LIBPCIACCESS */ |
|
1409 @@ -214,7 +309,7 @@ _X_EXPORT DriverRec RADEON = |
|
1410 RADEON_VERSION_CURRENT, |
|
1411 RADEON_DRIVER_NAME, |
|
1412 RADEONIdentify, |
|
1413 -#ifdef XSERVER_LIBPCIACCESS |
|
1414 +#if defined(XSERVER_LIBPCIACCESS) && !defined(__sparc__) |
|
1415 NULL, |
|
1416 #else |
|
1417 RADEONProbe, |
|
1418 @@ -223,7 +318,7 @@ _X_EXPORT DriverRec RADEON = |
|
1419 NULL, |
|
1420 0, |
|
1421 NULL, |
|
1422 -#ifdef XSERVER_LIBPCIACCESS |
|
1423 +#if defined(XSERVER_LIBPCIACCESS) && !defined(__sparc__) |
|
1424 radeon_device_match, |
|
1425 radeon_pci_probe |
|
1426 #endif |
|
1427 diff --git a/src/radeon_version.h b/src/radeon_version.h |
|
1428 index ccc1367..01958af 100644 |
|
1429 --- a/src/radeon_version.h |
|
1430 +++ b/src/radeon_version.h |
|
1431 @@ -34,8 +34,14 @@ |
|
1432 #undef RADEON_VERSION_STRINGIFY |
|
1433 #undef RADEON_VERSION_NAME |
|
1434 |
|
1435 +#if !defined(__sparc__) |
|
1436 #define RADEON_NAME "RADEON" |
|
1437 #define RADEON_DRIVER_NAME "radeon" |
|
1438 +#else |
|
1439 +#define RADEON_NAME "efb" |
|
1440 +#define RADEON_DRIVER_NAME "efb" |
|
1441 +#endif /* __sparc__ */ |
|
1442 + |
|
1443 #define R200_DRIVER_NAME "r200" |
|
1444 #define R300_DRIVER_NAME "r300" |
|
1445 |