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/*
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* GRUB -- GRand Unified Bootloader
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* Copyright (C) 2006 Free Software Foundation, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
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* Use is subject to license terms.
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*/
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#ifndef _SYS_CONTROLREGS_H
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#define _SYS_CONTROLREGS_H
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#pragma ident "%Z%%M% %I% %E% SMI"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* This file describes the x86 architecture control registers which
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* are part of the privileged architecture.
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*
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* Many of these definitions are shared between IA-32-style and
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* AMD64-style processors.
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*/
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/* CR0 Register */
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#define CR0_PG 0x80000000 /* paging enabled */
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#define CR0_CD 0x40000000 /* cache disable */
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#define CR0_NW 0x20000000 /* not writethrough */
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#define CR0_AM 0x00040000 /* alignment mask */
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#define CR0_WP 0x00010000 /* write protect */
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#define CR0_NE 0x00000020 /* numeric error */
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#define CR0_ET 0x00000010 /* extension type */
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#define CR0_TS 0x00000008 /* task switch */
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#define CR0_EM 0x00000004 /* emulation */
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#define CR0_MP 0x00000002 /* monitor coprocessor */
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#define CR0_PE 0x00000001 /* protection enabled */
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/* XX64 eliminate these compatibility defines */
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#define CR0_CE CR0_CD
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#define CR0_WT CR0_NW
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#define FMT_CR0 \
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"\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe"
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/* CR3 Register */
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#define CR3_PCD 0x00000010 /* cache disable */
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#define CR3_PWT 0x00000008 /* write through */
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#define FMT_CR3 "\20\5pcd\4pwt"
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/* CR4 Register */
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#define CR4_VME 0x0001 /* virtual-8086 mode extensions */
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#define CR4_PVI 0x0002 /* protected-mode virtual interrupts */
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#define CR4_TSD 0x0004 /* time stamp disable */
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#define CR4_DE 0x0008 /* debugging extensions */
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#define CR4_PSE 0x0010 /* page size extensions */
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#define CR4_PAE 0x0020 /* physical address extension */
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#define CR4_MCE 0x0040 /* machine check enable */
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#define CR4_PGE 0x0080 /* page global enable */
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#define CR4_PCE 0x0100 /* perf-monitoring counter enable */
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#define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */
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#define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */
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#define FMT_CR4 \
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"\20\13xmme\12fxsr\11pce\10pge\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
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/* Intel's SYSENTER configuration registers */
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#define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */
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#define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */
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#define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */
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/* AMD's EFER register */
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#define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */
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#define AMD_EFER_NXE 0x800 /* no-execute enable */
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#define AMD_EFER_LMA 0x400 /* long mode active (read-only) */
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#define AMD_EFER_LME 0x100 /* long mode enable */
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#define AMD_EFER_SCE 0x001 /* system call extensions */
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#define FMT_AMD_EFER \
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"\20\14nxe\13lma\11lme\1sce"
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/* AMD's SYSCFG register */
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#define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */
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#define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */
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#define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */
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#define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */
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#define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */
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#define FMT_AMD_SYSCFG \
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"\20\26tom2\25mvdm\24mfdm\23mfde"
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/* AMD's syscall/sysret MSRs */
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#define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */
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#define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */
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#define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */
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#define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */
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/* AMD's FS.base and GS.base MSRs */
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#define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */
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#define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */
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#define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */
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/* AMD's configuration MSRs, weakly documented in the revision guide */
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#define MSR_AMD_DC_CFG 0xc0011022
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#define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3)
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#define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10)
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/* AMD's HWCR MSR */
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#define MSR_AMD_HWCR 0xc0010015
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#define AMD_HWCR_FFDIS 0x00040 /* disable TLB Flush Filter */
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#define AMD_HWCR_MCI_STATUS_WREN 0x40000 /* enable write of MCi_STATUS */
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/* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */
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#define MSR_AMD_NB_CFG 0xc001001f
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#define MSR_BU_CFG 0xc0011023
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#define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20)
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#define AMD_NB_CFG_SRQ_SPR (UINT64_C(1) << 32)
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/* AMD */
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#define MSR_AMD_PATCHLEVEL 0x8b
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#ifdef __cplusplus
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}
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#endif
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#endif /* !_SYS_CONTROLREGS_H */
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