18 * information: Portions Copyright [yyyy] [name of copyright owner] |
18 * information: Portions Copyright [yyyy] [name of copyright owner] |
19 * |
19 * |
20 * CDDL HEADER END |
20 * CDDL HEADER END |
21 */ |
21 */ |
22 /* |
22 /* |
23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. |
23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. |
24 * Use is subject to license terms. |
24 * Use is subject to license terms. |
25 */ |
25 */ |
26 |
26 |
27 #pragma ident "%Z%%M% %I% %E% SMI" |
27 #pragma ident "%Z%%M% %I% %E% SMI" |
28 |
28 |
401 { |
401 { |
402 opt_pcbe_config_t *cfgs[4] = { &nullcfgs[0], &nullcfgs[1], |
402 opt_pcbe_config_t *cfgs[4] = { &nullcfgs[0], &nullcfgs[1], |
403 &nullcfgs[2], &nullcfgs[3] }; |
403 &nullcfgs[2], &nullcfgs[3] }; |
404 opt_pcbe_config_t *pcfg = NULL; |
404 opt_pcbe_config_t *pcfg = NULL; |
405 int i; |
405 int i; |
406 uint64_t tmp; |
|
407 uint32_t curcr4 = getcr4(); |
406 uint32_t curcr4 = getcr4(); |
408 |
407 |
409 /* |
408 /* |
410 * Allow nonprivileged code to read the performance counters if desired. |
409 * Allow nonprivileged code to read the performance counters if desired. |
411 */ |
410 */ |
431 * and the second loop enables the counters. This ensures that the |
430 * and the second loop enables the counters. This ensures that the |
432 * counters are all enabled as closely together in time as possible. |
431 * counters are all enabled as closely together in time as possible. |
433 */ |
432 */ |
434 |
433 |
435 for (i = 0; i < 4; i++) { |
434 for (i = 0; i < 4; i++) { |
436 wrmsr(PES_BASE_ADDR + i, &cfgs[i]->opt_evsel); |
435 wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel); |
437 wrmsr(PIC_BASE_ADDR + i, &cfgs[i]->opt_rawpic); |
436 wrmsr(PIC_BASE_ADDR + i, cfgs[i]->opt_rawpic); |
438 } |
437 } |
439 |
438 |
440 for (i = 0; i < 4; i++) { |
439 for (i = 0; i < 4; i++) { |
441 tmp = cfgs[i]->opt_evsel | OPT_PES_ENABLE; |
440 wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel | |
442 wrmsr(PES_BASE_ADDR + i, &tmp); |
441 (uint64_t)(uintptr_t)OPT_PES_ENABLE); |
443 } |
442 } |
444 } |
443 } |
445 |
444 |
446 static void |
445 static void |
447 opt_pcbe_allstop(void) |
446 opt_pcbe_allstop(void) |
448 { |
447 { |
449 int i; |
448 int i; |
450 uint64_t tmp = 0; |
|
451 |
449 |
452 for (i = 0; i < 4; i++) |
450 for (i = 0; i < 4; i++) |
453 wrmsr(PES_BASE_ADDR + i, &tmp); |
451 wrmsr(PES_BASE_ADDR + i, 0ULL); |
454 |
452 |
455 /* |
453 /* |
456 * Disable non-privileged access to the counter registers. |
454 * Disable non-privileged access to the counter registers. |
457 */ |
455 */ |
458 setcr4((uint32_t)getcr4() & ~CR4_PCE); |
456 setcr4((uint32_t)getcr4() & ~CR4_PCE); |