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6363034 Update bge and fix some errors onnv_32
authorly149593
Tue, 17 Jan 2006 21:18:31 -0800
changeset 1287 17aa1390b9f0
parent 1286 bc80117c34ab
child 1288 317cceffd26d
6363034 Update bge and fix some errors 6371677 Schumacher crashed with "Fatal PCI bus error(s)" while running ttcp stress test
usr/src/uts/common/io/bge/bge_chip.c file | annotate | diff | comparison | revisions 
--- a/usr/src/uts/common/io/bge/bge_chip.c	Tue Jan 17 19:37:56 2006 -0800
+++ b/usr/src/uts/common/io/bge/bge_chip.c	Tue Jan 17 21:18:31 2006 -0800
@@ -1972,10 +1972,8 @@
 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
-		if (cidp->rx_rings > BGE_RECV_RINGS_MAX_5705)
-			cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
-		if (cidp->tx_rings > BGE_SEND_RINGS_MAX_5705)
-			cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
+		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
+		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
 		cidp->statistic_type = BGE_STAT_REG;
 		dev_ok = B_TRUE;
@@ -1995,10 +1993,8 @@
 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
-		if (cidp->rx_rings > BGE_RECV_RINGS_MAX_5705)
-			cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
-		if (cidp->tx_rings > BGE_SEND_RINGS_MAX_5705)
-			cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
+		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
+		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
 		cidp->statistic_type = BGE_STAT_REG;
 		dev_ok = B_TRUE;
@@ -2012,6 +2008,8 @@
 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
+		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
+		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
 		cidp->statistic_type = BGE_STAT_REG;
 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
 		dev_ok = B_TRUE;
@@ -2028,6 +2026,8 @@
 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714;
 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
+		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
+		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
 		cidp->pci_type = BGE_PCI_E;
 		cidp->statistic_type = BGE_STAT_REG;
 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
@@ -2041,6 +2041,8 @@
 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715;
 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
+		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
+		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
 		cidp->pci_type = BGE_PCI_E;
 		cidp->statistic_type = BGE_STAT_REG;
 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
@@ -2053,6 +2055,8 @@
 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
+		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
+		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
 		cidp->pci_type = BGE_PCI_E;
 		cidp->statistic_type = BGE_STAT_REG;
 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
@@ -2066,6 +2070,8 @@
 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
+		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
+		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
 		cidp->pci_type = BGE_PCI_E;
 		cidp->statistic_type = BGE_STAT_REG;
 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
@@ -2327,7 +2333,11 @@
 #ifdef	__sparcv9
 		membar_sync();
 #endif	/* __sparcv9 */
-		drv_usecwait(200);
+		/*
+		 * On some platforms,system need about 300us for
+		 * link setup.
+		 */
+		drv_usecwait(300);
 
 		if (bgep->chipid.pci_type == BGE_PCI_E) {
 			/* PCI-E device need more reset time */
@@ -3077,6 +3087,7 @@
 	uint32_t coalmode;
 	uint32_t ledctl;
 	uint32_t mtu;
+	uint32_t maxring;
 	uint64_t ring;
 
 	BGE_TRACE(("bge_chip_start($%p)",
@@ -3188,27 +3199,33 @@
 	 */
 	bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
 		&bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
-	bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
-		&bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
-	bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
-		&bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
+	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
+		bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
+			&bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
+		bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
+			&bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
+	}
 
 	/*
 	 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
 	 */
 	bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
-	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
+	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
 		bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
 		    bge_replenish_jumbo);
-	if (bgep->chipid.device == DEVICE_ID_5700)
 		bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
 		    bge_replenish_mini);
+	}
 
 	/*
 	 * Steps 41-43: clear Send Ring Producer Indices and initialise
 	 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
 	 */
-	for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) {
+	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
+		maxring = BGE_SEND_RINGS_MAX;
+	else
+		maxring = BGE_SEND_RINGS_MAX_5705;
+	for (ring = 0; ring < maxring; ++ring) {
 		bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
 		bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
 		bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
@@ -3219,7 +3236,11 @@
 	 * Steps 44-45: initialise Receive Return Rings
 	 * (0x0200-0x02ff in NIC-local memory)
 	 */
-	for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring)
+	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
+		maxring = BGE_RECV_RINGS_MAX;
+	else
+		maxring = BGE_RECV_RINGS_MAX_5705;
+	for (ring = 0; ring < maxring; ++ring)
 		bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
 			&bgep->recv[ring].hw_rcb);
 
@@ -3227,11 +3248,10 @@
 	 * Step 46: initialise Receive Buffer (Producer) Ring indexes
 	 */
 	bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
-	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
+	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
 		bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
-	if (bgep->chipid.device == DEVICE_ID_5700)
 		bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
-
+	}
 	/*
 	 * Step 47: configure the MAC unicast address
 	 * Step 48: configure the random backoff seed
upstream/oracle/onnv-gate-zfscrypto