Sparc assembler and fixes a bug in JIT.
Also some endian patch.

--- comm-esr31/mozilla/js/src/assembler/assembler/MacroAssemblerSparc.h.orig	2015-06-04 17:42:51.654203814 -0700
+++ comm-esr31/mozilla/js/src/assembler/assembler/MacroAssemblerSparc.h	2015-06-04 17:42:51.667707756 -0700
@@ -337,6 +337,17 @@
             }
         }
 
+        void load16Unaligned(BaseIndex address, RegisterID dest)
+        {
+            m_assembler.sll_imm(address.index, address.scale, SparcRegisters::g2);
+            add32(Imm32(address.offset+1), SparcRegisters::g2);
+            m_assembler.ldub_r(address.base, SparcRegisters::g2, dest);
+            m_assembler.subcc_imm(SparcRegisters::g2, 1, SparcRegisters::g2);
+            m_assembler.ldub_r(address.base, SparcRegisters::g2, SparcRegisters::g3);
+            m_assembler.sll_imm(SparcRegisters::g3, 8, SparcRegisters::g3);
+            m_assembler.or_r(SparcRegisters::g3, dest, dest);
+        }
+
         void store8(RegisterID src, ImplicitAddress address)
         {
             if (m_assembler.isimm13(address.offset))
@@ -416,6 +427,11 @@
             }
         }
 
+        void load8(BaseIndex address, RegisterID dest)
+        {
+            load8ZeroExtend(address, dest);
+        }
+
         void load8SignExtend(BaseIndex address, RegisterID dest)
         {
             m_assembler.sll_imm(address.index, address.scale, SparcRegisters::g2);
--- comm-esr31/mozilla/js/src/assembler/assembler/SparcAssembler.h.orig	2015-06-04 17:42:51.659564348 -0700
+++ comm-esr31/mozilla/js/src/assembler/assembler/SparcAssembler.h	2015-06-04 17:42:51.667904536 -0700
@@ -161,6 +161,10 @@
             {
             }
 
+            bool isSet() const {
+                return m_offset != -1;
+            }
+
         private:
             JmpSrc(int offset)
                 : m_offset(offset)
--- comm-esr31/mozilla/js/src/yarr/YarrJIT.cpp.orig	2015-06-04 17:42:51.665227855 -0700
+++ comm-esr31/mozilla/js/src/yarr/YarrJIT.cpp	2015-06-04 17:42:51.668284205 -0700
@@ -84,6 +84,7 @@
     static const RegisterID regT1 = SparcRegisters::i5;
 
     static const RegisterID returnRegister = SparcRegisters::i0;
+    static const RegisterID returnRegister2 = SparcRegisters::i1;
 #elif WTF_CPU_X86
     static const RegisterID input = X86Registers::eax;
     static const RegisterID index = X86Registers::edx;
@@ -824,6 +825,18 @@
                 ignoreCaseMask |= 32 << shiftAmount;
         }
 
+#if WTF_CPU_BIG_ENDIAN
+        if (m_charSize == Char8) {
+            allCharacters = (allCharacters << 24) | ((allCharacters << 8) & 0xff0000) |
+                            ((allCharacters >> 8) & 0xff00) | ((allCharacters >> 24) & 0xff);
+            ignoreCaseMask = (ignoreCaseMask << 24) | ((ignoreCaseMask << 8) & 0xff0000) |
+                             ((ignoreCaseMask >> 8) & 0xff00) | ((ignoreCaseMask >> 24) & 0xff);
+        } else {
+            allCharacters = (allCharacters << 16) | ((allCharacters >> 16) & 0xffff);
+            ignoreCaseMask = (ignoreCaseMask << 16) | ((ignoreCaseMask >> 16) & 0xffff);
+        }
+#endif
+
         if (m_charSize == Char8) {
             switch (numberCharacters) {
             case 1: