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1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.43 2003/11/06 18:38:00 tsi Exp $ */ |
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2 /* |
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3 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
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4 * VA Linux Systems Inc., Fremont, California. |
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5 * |
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6 * All Rights Reserved. |
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7 * |
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8 * Permission is hereby granted, free of charge, to any person obtaining |
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9 * a copy of this software and associated documentation files (the |
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10 * "Software"), to deal in the Software without restriction, including |
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11 * without limitation on the rights to use, copy, modify, merge, |
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12 * publish, distribute, sublicense, and/or sell copies of the Software, |
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13 * and to permit persons to whom the Software is furnished to do so, |
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14 * subject to the following conditions: |
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15 * |
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16 * The above copyright notice and this permission notice (including the |
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17 * next paragraph) shall be included in all copies or substantial |
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18 * portions of the Software. |
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19 * |
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20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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21 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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23 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR |
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24 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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25 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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27 * DEALINGS IN THE SOFTWARE. |
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28 */ |
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29 |
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30 /* |
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31 * Authors: |
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32 * Kevin E. Martin <[email protected]> |
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33 * Rickard E. Faith <[email protected]> |
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34 * Alan Hourihane <[email protected]> |
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35 * |
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36 */ |
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37 |
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38 #ifndef _RADEON_H_ |
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39 #define _RADEON_H_ |
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40 |
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41 #include "xf86str.h" |
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42 #include "xf86_ansic.h" |
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43 #include "compiler.h" |
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44 #include "xf86fbman.h" |
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45 |
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46 /* PCI support */ |
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47 #include "xf86Pci.h" |
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48 |
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49 #ifdef USE_EXA |
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50 #include "exa.h" |
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51 #endif |
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52 #ifdef USE_XAA |
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53 #include "xaa.h" |
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54 #endif |
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55 |
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56 /* Exa and Cursor Support */ |
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57 #include "vbe.h" |
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58 #include "xf86Cursor.h" |
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59 |
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60 /* DDC support */ |
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61 #include "xf86DDC.h" |
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62 |
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63 /* Xv support */ |
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64 #include "xf86xv.h" |
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65 |
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66 #include "radeon_probe.h" |
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67 /* DRI support */ |
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68 #ifdef XF86DRI |
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69 #define _XF86DRI_SERVER_ |
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70 #include "radeon_dripriv.h" |
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71 #include "dri.h" |
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72 #include "GL/glxint.h" |
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73 #endif |
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74 |
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75 /* Render support */ |
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76 #ifdef RENDER |
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77 #include "picturestr.h" |
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78 #endif |
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79 |
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80 /* ------- mergedfb support ------------- */ |
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81 /* Psuedo Xinerama support */ |
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82 #define NEED_REPLIES /* ? */ |
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83 #define EXTENSION_PROC_ARGS void * |
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84 #include "extnsionst.h" /* required */ |
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85 #include <X11/extensions/panoramiXproto.h> /* required */ |
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86 #define RADEON_XINERAMA_MAJOR_VERSION 1 |
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87 #define RADEON_XINERAMA_MINOR_VERSION 1 |
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88 |
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89 |
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90 /* Relative merge position */ |
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91 typedef enum { |
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92 radeonLeftOf, |
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93 radeonRightOf, |
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94 radeonAbove, |
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95 radeonBelow, |
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96 radeonClone |
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97 } RADEONScrn2Rel; |
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98 |
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99 typedef struct _region { |
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100 int x0,x1,y0,y1; |
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101 } region; |
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102 |
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103 /* ------------------------------------- */ |
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104 |
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105 #define RADEON_DEBUG 0 /* Turn off debugging output */ |
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106 #define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ |
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107 #define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ |
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108 #define RADEON_MMIOSIZE 0x80000 |
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109 |
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110 /* Buffer are aligned on 4096 byte boundaries */ |
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111 #define RADEON_BUFFER_ALIGN 0x00000fff |
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112 #define RADEON_VBIOS_SIZE 0x00010000 |
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113 #define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX |
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114 * Need to comfirm this is not used |
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115 * for something else. |
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116 */ |
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117 |
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118 #if RADEON_DEBUG |
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119 #define RADEONTRACE(x) \ |
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120 do { \ |
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121 ErrorF("(**) %s(%d): ", RADEON_NAME, pScrn->scrnIndex); \ |
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122 ErrorF x; \ |
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123 } while(0) |
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124 #else |
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125 #define RADEONTRACE(x) do { } while(0) |
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126 #endif |
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127 |
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128 |
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129 /* Other macros */ |
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130 #define RADEON_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) |
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131 #define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) |
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132 #define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate) |
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133 |
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134 |
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135 typedef struct { |
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136 /* Common registers */ |
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137 CARD32 ovr_clr; |
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138 CARD32 ovr_wid_left_right; |
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139 CARD32 ovr_wid_top_bottom; |
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140 CARD32 ov0_scale_cntl; |
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141 CARD32 mpp_tb_config; |
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142 CARD32 mpp_gp_config; |
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143 CARD32 subpic_cntl; |
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144 CARD32 viph_control; |
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145 CARD32 i2c_cntl_1; |
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146 CARD32 gen_int_cntl; |
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147 CARD32 cap0_trig_cntl; |
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148 CARD32 cap1_trig_cntl; |
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149 CARD32 bus_cntl; |
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150 CARD32 bios_4_scratch; |
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151 CARD32 bios_5_scratch; |
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152 CARD32 bios_6_scratch; |
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153 CARD32 surface_cntl; |
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154 CARD32 surfaces[8][3]; |
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155 CARD32 mc_agp_location; |
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156 CARD32 mc_fb_location; |
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157 CARD32 display_base_addr; |
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158 CARD32 display2_base_addr; |
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159 CARD32 ov0_base_addr; |
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160 |
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161 /* Other registers to save for VT switches */ |
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162 CARD32 dp_datatype; |
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163 CARD32 rbbm_soft_reset; |
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164 CARD32 clock_cntl_index; |
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165 CARD32 amcgpio_en_reg; |
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166 CARD32 amcgpio_mask; |
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167 |
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168 /* CRTC registers */ |
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169 CARD32 crtc_gen_cntl; |
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170 CARD32 crtc_ext_cntl; |
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171 CARD32 dac_cntl; |
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172 CARD32 crtc_h_total_disp; |
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173 CARD32 crtc_h_sync_strt_wid; |
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174 CARD32 crtc_v_total_disp; |
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175 CARD32 crtc_v_sync_strt_wid; |
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176 CARD32 crtc_offset; |
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177 CARD32 crtc_offset_cntl; |
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178 CARD32 crtc_pitch; |
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179 CARD32 disp_merge_cntl; |
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180 CARD32 grph_buffer_cntl; |
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181 CARD32 crtc_more_cntl; |
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182 |
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183 /* CRTC2 registers */ |
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184 CARD32 crtc2_gen_cntl; |
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185 |
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186 CARD32 dac2_cntl; |
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187 CARD32 disp_output_cntl; |
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188 CARD32 disp_hw_debug; |
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189 CARD32 disp2_merge_cntl; |
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190 CARD32 grph2_buffer_cntl; |
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191 CARD32 crtc2_h_total_disp; |
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192 CARD32 crtc2_h_sync_strt_wid; |
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193 CARD32 crtc2_v_total_disp; |
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194 CARD32 crtc2_v_sync_strt_wid; |
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195 CARD32 crtc2_offset; |
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196 CARD32 crtc2_offset_cntl; |
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197 CARD32 crtc2_pitch; |
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198 /* Flat panel registers */ |
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199 CARD32 fp_crtc_h_total_disp; |
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200 CARD32 fp_crtc_v_total_disp; |
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201 CARD32 fp_gen_cntl; |
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202 CARD32 fp2_gen_cntl; |
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203 CARD32 fp_h_sync_strt_wid; |
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204 CARD32 fp2_h_sync_strt_wid; |
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205 CARD32 fp_horz_stretch; |
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206 CARD32 fp_panel_cntl; |
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207 CARD32 fp_v_sync_strt_wid; |
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208 CARD32 fp2_v_sync_strt_wid; |
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209 CARD32 fp_vert_stretch; |
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210 CARD32 lvds_gen_cntl; |
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211 CARD32 lvds_pll_cntl; |
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212 CARD32 tmds_pll_cntl; |
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213 CARD32 tmds_transmitter_cntl; |
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214 |
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215 /* Computed values for PLL */ |
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216 CARD32 dot_clock_freq; |
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217 CARD32 pll_output_freq; |
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218 int feedback_div; |
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219 int post_div; |
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220 |
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221 /* PLL registers */ |
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222 unsigned ppll_ref_div; |
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223 unsigned ppll_div_3; |
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224 CARD32 htotal_cntl; |
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225 |
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226 /* Computed values for PLL2 */ |
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227 CARD32 dot_clock_freq_2; |
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228 CARD32 pll_output_freq_2; |
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229 int feedback_div_2; |
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230 int post_div_2; |
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231 |
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232 /* PLL2 registers */ |
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233 CARD32 p2pll_ref_div; |
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234 CARD32 p2pll_div_0; |
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235 CARD32 htotal_cntl2; |
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236 |
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237 /* Pallet */ |
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238 Bool palette_valid; |
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239 CARD32 palette[256]; |
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240 CARD32 palette2[256]; |
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241 |
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242 CARD32 tv_dac_cntl; |
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243 |
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244 } RADEONSaveRec, *RADEONSavePtr; |
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245 |
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246 typedef struct { |
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247 CARD16 reference_freq; |
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248 CARD16 reference_div; |
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249 CARD32 min_pll_freq; |
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250 CARD32 max_pll_freq; |
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251 CARD16 xclk; |
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252 } RADEONPLLRec, *RADEONPLLPtr; |
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253 |
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254 typedef struct { |
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255 int bitsPerPixel; |
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256 int depth; |
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257 int displayWidth; |
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258 int displayHeight; |
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259 int pixel_code; |
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260 int pixel_bytes; |
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261 DisplayModePtr mode; |
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262 } RADEONFBLayout; |
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263 |
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264 typedef enum { |
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265 CHIP_FAMILY_UNKNOW, |
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266 CHIP_FAMILY_LEGACY, |
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267 CHIP_FAMILY_RADEON, |
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268 CHIP_FAMILY_RV100, |
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269 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ |
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270 CHIP_FAMILY_RV200, |
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271 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ |
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272 CHIP_FAMILY_R200, |
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273 CHIP_FAMILY_RV250, |
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274 CHIP_FAMILY_RS300, /* RS300/RS350 */ |
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275 CHIP_FAMILY_RV280, |
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276 CHIP_FAMILY_R300, |
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277 CHIP_FAMILY_R350, |
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278 CHIP_FAMILY_RV350, |
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279 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ |
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280 CHIP_FAMILY_R420, /* R420/R423/M18 */ |
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281 CHIP_FAMILY_RV410, /* RV410, M26 */ |
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282 CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */ |
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283 CHIP_FAMILY_LAST |
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284 } RADEONChipFamily; |
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285 |
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286 #define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100) || \ |
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287 (info->ChipFamily == CHIP_FAMILY_RV200) || \ |
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288 (info->ChipFamily == CHIP_FAMILY_RS100) || \ |
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289 (info->ChipFamily == CHIP_FAMILY_RS200) || \ |
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290 (info->ChipFamily == CHIP_FAMILY_RV250) || \ |
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291 (info->ChipFamily == CHIP_FAMILY_RV280) || \ |
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292 (info->ChipFamily == CHIP_FAMILY_RS300)) |
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293 |
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294 |
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295 #define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \ |
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296 (info->ChipFamily == CHIP_FAMILY_RV350) || \ |
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297 (info->ChipFamily == CHIP_FAMILY_R350) || \ |
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298 (info->ChipFamily == CHIP_FAMILY_RV380) || \ |
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299 (info->ChipFamily == CHIP_FAMILY_R420) || \ |
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300 (info->ChipFamily == CHIP_FAMILY_RV410) || \ |
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301 (info->ChipFamily == CHIP_FAMILY_RS400)) |
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302 |
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303 /* |
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304 * Errata workarounds |
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305 */ |
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306 typedef enum { |
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307 CHIP_ERRATA_R300_CG = 0x00000001, |
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308 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
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309 CHIP_ERRATA_PLL_DELAY = 0x00000004 |
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310 } RADEONErrata; |
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311 |
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312 typedef enum { |
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313 CARD_PCI, |
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314 CARD_AGP, |
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315 CARD_PCIE |
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316 } RADEONCardType; |
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317 |
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318 typedef struct { |
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319 CARD32 freq; |
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320 CARD32 value; |
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321 }RADEONTMDSPll; |
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322 |
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323 typedef struct { |
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324 EntityInfoPtr pEnt; |
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325 pciVideoPtr PciInfo; |
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326 PCITAG PciTag; |
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327 int Chipset; |
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328 RADEONChipFamily ChipFamily; |
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329 RADEONErrata ChipErrata; |
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330 |
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331 Bool FBDev; |
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332 |
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333 unsigned long LinearAddr; /* Frame buffer physical address */ |
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334 unsigned long MMIOAddr; /* MMIO region physical address */ |
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335 unsigned long BIOSAddr; /* BIOS physical address */ |
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336 unsigned int fbLocation; |
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337 CARD32 mc_fb_location; |
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338 CARD32 mc_agp_location; |
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339 |
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340 unsigned char *MMIO; /* Map of MMIO region */ |
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341 unsigned char *FB; /* Map of frame buffer */ |
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342 CARD8 *VBIOS; /* Video BIOS pointer */ |
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343 |
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344 Bool IsAtomBios; /* New BIOS used in R420 etc. */ |
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345 int ROMHeaderStart; /* Start of the ROM Info Table */ |
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346 int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ |
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347 |
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348 CARD32 MemCntl; |
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349 CARD32 BusCntl; |
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350 unsigned long FbMapSize; /* Size of frame buffer, in bytes */ |
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351 unsigned long FbSecureSize; /* Size of secured fb area at end of |
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352 framebuffer */ |
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353 int Flags; /* Saved copy of mode flags */ |
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354 |
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355 /* VE/M6 support */ |
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356 RADEONMonitorType DisplayType; /* Monitor connected on */ |
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357 RADEONDDCType DDCType; |
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358 RADEONConnectorType ConnectorType; |
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359 Bool HasCRTC2; /* All cards except original Radeon */ |
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360 Bool IsMobility; /* Mobile chips for laptops */ |
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361 Bool IsIGP; /* IGP chips */ |
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362 Bool HasSingleDAC; /* only TVDAC on chip */ |
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363 Bool IsSecondary; /* Second Screen */ |
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364 Bool IsPrimary; /* Primary Screen */ |
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365 Bool IsSwitching; /* Flag for switching mode */ |
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366 Bool OverlayOnCRTC2; |
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367 Bool PanelOff; /* Force panel (LCD/DFP) off */ |
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368 Bool ddc_mode; /* Validate mode by matching exactly |
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369 * the modes supported in DDC data |
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370 */ |
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371 Bool R300CGWorkaround; |
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372 |
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373 /* EDID or BIOS values for FPs */ |
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374 int PanelXRes; |
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375 int PanelYRes; |
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376 int HOverPlus; |
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377 int HSyncWidth; |
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378 int HBlank; |
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379 int VOverPlus; |
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380 int VSyncWidth; |
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381 int VBlank; |
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382 int PanelPwrDly; |
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383 int DotClock; |
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384 int RefDivider; |
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385 int FeedbackDivider; |
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386 int PostDivider; |
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387 Bool UseBiosDividers; |
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388 /* EDID data using DDC interface */ |
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389 Bool ddc_bios; |
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390 Bool ddc1; |
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391 Bool ddc2; |
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392 I2CBusPtr pI2CBus; |
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393 CARD32 DDCReg; |
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394 |
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395 RADEONPLLRec pll; |
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396 RADEONTMDSPll tmds_pll[4]; |
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397 int RamWidth; |
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398 float sclk; /* in MHz */ |
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399 float mclk; /* in MHz */ |
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400 Bool IsDDR; |
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401 int DispPriority; |
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402 |
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403 RADEONSaveRec SavedReg; /* Original (text) mode */ |
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404 RADEONSaveRec ModeReg; /* Current mode */ |
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405 Bool (*CloseScreen)(int, ScreenPtr); |
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406 |
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407 void (*BlockHandler)(int, pointer, pointer, pointer); |
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408 |
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409 Bool PaletteSavedOnVT; /* Palette saved on last VT switch */ |
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410 |
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411 #ifdef USE_EXA |
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412 ExaDriverRec exa; |
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413 int engineMode; |
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414 #define EXA_ENGINEMODE_UNKNOWN 0 |
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415 #define EXA_ENGINEMODE_2D 1 |
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416 #define EXA_ENGINEMODE_3D 2 |
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417 #endif |
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418 #ifdef USE_XAA |
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419 XAAInfoRecPtr accel; |
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420 #endif |
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421 Bool accelOn; |
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422 xf86CursorInfoPtr cursor; |
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423 #ifdef USE_EXA |
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424 ExaOffscreenArea *cursorArea; |
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425 #endif |
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426 unsigned long cursor_offset; |
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427 #ifdef USE_XAA |
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428 unsigned long cursor_end; |
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429 #endif |
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430 Bool allowColorTiling; |
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431 Bool tilingEnabled; /* mirror of sarea->tiling_enabled */ |
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432 #ifdef ARGB_CURSOR |
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433 Bool cursor_argb; |
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434 #endif |
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435 int cursor_fg; |
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436 int cursor_bg; |
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437 |
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438 #ifdef USE_XAA |
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439 /* |
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440 * XAAForceTransBlit is used to change the behavior of the XAA |
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441 * SetupForScreenToScreenCopy function, to make it DGA-friendly. |
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442 */ |
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443 Bool XAAForceTransBlit; |
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444 #endif |
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445 |
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446 int fifo_slots; /* Free slots in the FIFO (64 max) */ |
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447 int pix24bpp; /* Depth of pixmap for 24bpp fb */ |
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448 Bool dac6bits; /* Use 6 bit DAC? */ |
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449 |
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450 /* Computed values for Radeon */ |
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451 int pitch; |
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452 int datatype; |
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453 CARD32 dp_gui_master_cntl; |
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454 CARD32 dp_gui_master_cntl_clip; |
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455 CARD32 trans_color; |
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456 |
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457 /* Saved values for ScreenToScreenCopy */ |
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458 int xdir; |
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459 int ydir; |
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460 |
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461 #ifdef USE_XAA |
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462 /* ScanlineScreenToScreenColorExpand support */ |
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463 unsigned char *scratch_buffer[1]; |
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464 unsigned char *scratch_save; |
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465 int scanline_x; |
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466 int scanline_y; |
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467 int scanline_w; |
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468 int scanline_h; |
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469 int scanline_h_w; |
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470 int scanline_words; |
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471 int scanline_direct; |
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472 int scanline_bpp; /* Only used for ImageWrite */ |
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473 int scanline_fg; |
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474 int scanline_bg; |
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475 int scanline_hpass; |
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476 int scanline_x1clip; |
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477 int scanline_x2clip; |
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478 #endif |
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479 /* Saved values for DashedTwoPointLine */ |
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480 int dashLen; |
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481 CARD32 dashPattern; |
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482 int dash_fg; |
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483 int dash_bg; |
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484 |
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485 DGAModePtr DGAModes; |
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486 int numDGAModes; |
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487 Bool DGAactive; |
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488 int DGAViewportStatus; |
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489 DGAFunctionRec DGAFuncs; |
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490 |
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491 RADEONFBLayout CurrentLayout; |
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492 CARD32 dst_pitch_offset; |
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493 #ifdef XF86DRI |
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494 Bool noBackBuffer; |
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495 Bool directRenderingEnabled; |
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496 Bool directRenderingInited; |
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497 Bool newMemoryMap; |
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498 drmVersionPtr pLibDRMVersion; |
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499 drmVersionPtr pKernelDRMVersion; |
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500 DRIInfoPtr pDRIInfo; |
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501 int drmFD; |
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502 int numVisualConfigs; |
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503 __GLXvisualConfig *pVisualConfigs; |
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504 RADEONConfigPrivPtr pVisualConfigsPriv; |
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505 Bool (*DRICloseScreen)(int, ScreenPtr); |
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506 |
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507 drm_handle_t fbHandle; |
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508 |
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509 drmSize registerSize; |
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510 drm_handle_t registerHandle; |
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511 |
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512 RADEONCardType cardType; /* Current card is a PCI card */ |
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513 drmSize pciSize; |
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514 drm_handle_t pciMemHandle; |
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515 unsigned char *PCI; /* Map */ |
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516 |
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517 Bool depthMoves; /* Enable depth moves -- slow! */ |
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518 Bool allowPageFlip; /* Enable 3d page flipping */ |
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519 Bool have3DWindows; /* Are there any 3d clients? */ |
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520 |
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521 drmSize gartSize; |
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522 drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ |
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523 unsigned long gartOffset; |
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524 unsigned char *AGP; /* Map */ |
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525 int agpMode; |
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526 int agpFastWrite; |
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527 |
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528 CARD32 pciCommand; |
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529 |
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530 Bool CPRuns; /* CP is running */ |
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531 Bool CPInUse; /* CP has been used by X server */ |
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532 Bool CPStarted; /* CP has started */ |
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533 int CPMode; /* CP mode that server/clients use */ |
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534 int CPFifoSize; /* Size of the CP command FIFO */ |
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535 int CPusecTimeout; /* CP timeout in usecs */ |
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536 |
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537 /* CP ring buffer data */ |
|
538 unsigned long ringStart; /* Offset into GART space */ |
|
539 drm_handle_t ringHandle; /* Handle from drmAddMap */ |
|
540 drmSize ringMapSize; /* Size of map */ |
|
541 int ringSize; /* Size of ring (in MB) */ |
|
542 unsigned char *ring; /* Map */ |
|
543 int ringSizeLog2QW; |
|
544 |
|
545 unsigned long ringReadOffset; /* Offset into GART space */ |
|
546 drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ |
|
547 drmSize ringReadMapSize; /* Size of map */ |
|
548 unsigned char *ringReadPtr; /* Map */ |
|
549 |
|
550 /* CP vertex/indirect buffer data */ |
|
551 unsigned long bufStart; /* Offset into GART space */ |
|
552 drm_handle_t bufHandle; /* Handle from drmAddMap */ |
|
553 drmSize bufMapSize; /* Size of map */ |
|
554 int bufSize; /* Size of buffers (in MB) */ |
|
555 unsigned char *buf; /* Map */ |
|
556 int bufNumBufs; /* Number of buffers */ |
|
557 drmBufMapPtr buffers; /* Buffer map */ |
|
558 |
|
559 /* CP GART Texture data */ |
|
560 unsigned long gartTexStart; /* Offset into GART space */ |
|
561 drm_handle_t gartTexHandle; /* Handle from drmAddMap */ |
|
562 drmSize gartTexMapSize; /* Size of map */ |
|
563 int gartTexSize; /* Size of GART tex space (in MB) */ |
|
564 unsigned char *gartTex; /* Map */ |
|
565 int log2GARTTexGran; |
|
566 |
|
567 /* CP accleration */ |
|
568 drmBufPtr indirectBuffer; |
|
569 int indirectStart; |
|
570 |
|
571 /* DRI screen private data */ |
|
572 int fbX; |
|
573 int fbY; |
|
574 int backX; |
|
575 int backY; |
|
576 int depthX; |
|
577 int depthY; |
|
578 |
|
579 int frontOffset; |
|
580 int frontPitch; |
|
581 int backOffset; |
|
582 int backPitch; |
|
583 int depthOffset; |
|
584 int depthPitch; |
|
585 int textureOffset; |
|
586 int textureSize; |
|
587 int log2TexGran; |
|
588 |
|
589 int pciGartSize; |
|
590 CARD32 pciGartOffset; |
|
591 void *pciGartBackup; |
|
592 #ifdef USE_XAA |
|
593 CARD32 frontPitchOffset; |
|
594 CARD32 backPitchOffset; |
|
595 CARD32 depthPitchOffset; |
|
596 |
|
597 /* offscreen memory management */ |
|
598 int backLines; |
|
599 FBAreaPtr backArea; |
|
600 int depthTexLines; |
|
601 FBAreaPtr depthTexArea; |
|
602 #endif |
|
603 |
|
604 /* Saved scissor values */ |
|
605 CARD32 sc_left; |
|
606 CARD32 sc_right; |
|
607 CARD32 sc_top; |
|
608 CARD32 sc_bottom; |
|
609 |
|
610 CARD32 re_top_left; |
|
611 CARD32 re_width_height; |
|
612 |
|
613 CARD32 aux_sc_cntl; |
|
614 |
|
615 int irq; |
|
616 |
|
617 Bool DMAForXv; |
|
618 |
|
619 #ifdef PER_CONTEXT_SAREA |
|
620 int perctx_sarea_size; |
|
621 #endif |
|
622 |
|
623 /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ |
|
624 int dma_begin_count; |
|
625 char *dma_debug_func; |
|
626 int dma_debug_lineno; |
|
627 #endif /* XF86DRI */ |
|
628 |
|
629 /* XVideo */ |
|
630 XF86VideoAdaptorPtr adaptor; |
|
631 void (*VideoTimerCallback)(ScrnInfoPtr, Time); |
|
632 int videoKey; |
|
633 int RageTheatreCrystal; |
|
634 int RageTheatreTunerPort; |
|
635 int RageTheatreCompositePort; |
|
636 int RageTheatreSVideoPort; |
|
637 int tunerType; |
|
638 char* RageTheatreMicrocPath; |
|
639 char* RageTheatreMicrocType; |
|
640 Bool MM_TABLE_valid; |
|
641 struct { |
|
642 CARD8 table_revision; |
|
643 CARD8 table_size; |
|
644 CARD8 tuner_type; |
|
645 CARD8 audio_chip; |
|
646 CARD8 product_id; |
|
647 CARD8 tuner_voltage_teletext_fm; |
|
648 CARD8 i2s_config; /* configuration of the sound chip */ |
|
649 CARD8 video_decoder_type; |
|
650 CARD8 video_decoder_host_config; |
|
651 CARD8 input[5]; |
|
652 } MM_TABLE; |
|
653 CARD16 video_decoder_type; |
|
654 |
|
655 /* Render */ |
|
656 Bool RenderAccel; |
|
657 #ifdef USE_XAA |
|
658 FBLinearPtr RenderTex; |
|
659 void (*RenderCallback)(ScrnInfoPtr); |
|
660 Time RenderTimeout; |
|
661 #endif |
|
662 |
|
663 /* general */ |
|
664 Bool showCache; |
|
665 OptionInfoPtr Options; |
|
666 |
|
667 Bool useEXA; |
|
668 #ifdef XFree86LOADER |
|
669 #ifdef USE_EXA |
|
670 XF86ModReqInfo exaReq; |
|
671 #endif |
|
672 #ifdef USE_XAA |
|
673 XF86ModReqInfo xaaReq; |
|
674 #endif |
|
675 #endif |
|
676 |
|
677 /* X itself has the 3D context */ |
|
678 Bool XInited3D; |
|
679 |
|
680 /* merged fb stuff, also covers clone modes */ |
|
681 Bool MergedFB; |
|
682 RADEONScrn2Rel CRT2Position; |
|
683 char * CRT2HSync; |
|
684 char * CRT2VRefresh; |
|
685 char * MetaModes; |
|
686 ScrnInfoPtr CRT2pScrn; |
|
687 DisplayModePtr CRT1Modes; |
|
688 DisplayModePtr CRT1CurrentMode; |
|
689 int CRT1frameX0; |
|
690 int CRT1frameY0; |
|
691 int CRT1frameX1; |
|
692 int CRT1frameY1; |
|
693 RADEONMonitorType MergeType; |
|
694 RADEONDDCType MergeDDCType; |
|
695 void (*PointerMoved)(int index, int x, int y); |
|
696 /* pseudo xinerama support for mergedfb */ |
|
697 int maxCRT1_X1, maxCRT1_X2, maxCRT1_Y1, maxCRT1_Y2; |
|
698 int maxCRT2_X1, maxCRT2_X2, maxCRT2_Y1, maxCRT2_Y2; |
|
699 int maxClone_X1, maxClone_X2, maxClone_Y1, maxClone_Y2; |
|
700 Bool UseRADEONXinerama; |
|
701 Bool CRT2IsScrn0; |
|
702 ExtensionEntry *XineramaExtEntry; |
|
703 int RADEONXineramaVX, RADEONXineramaVY; |
|
704 Bool AtLeastOneNonClone; |
|
705 int MergedFBXDPI, MergedFBYDPI; |
|
706 Bool NoVirtual; |
|
707 int CRT1XOffs, CRT1YOffs, CRT2XOffs, CRT2YOffs; |
|
708 int MBXNR1XMAX, MBXNR1YMAX, MBXNR2XMAX, MBXNR2YMAX; |
|
709 Bool NonRect, HaveNonRect, HaveOffsRegions, MouseRestrictions; |
|
710 region NonRectDead, OffDead1, OffDead2; |
|
711 |
|
712 /* special handlings for DELL triple-head server */ |
|
713 Bool IsDellServer; |
|
714 |
|
715 /* enable bios hotkey output switching */ |
|
716 Bool BiosHotkeys; |
|
717 |
|
718 Bool VGAAccess; |
|
719 |
|
720 int MaxSurfaceWidth; |
|
721 int MaxLines; |
|
722 |
|
723 } RADEONInfoRec, *RADEONInfoPtr; |
|
724 |
|
725 #define RADEONWaitForFifo(pScrn, entries) \ |
|
726 do { \ |
|
727 if (info->fifo_slots < entries) \ |
|
728 RADEONWaitForFifoFunction(pScrn, entries); \ |
|
729 info->fifo_slots -= entries; \ |
|
730 } while (0) |
|
731 |
|
732 extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); |
|
733 extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); |
|
734 extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); |
|
735 #ifdef XF86DRI |
|
736 extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); |
|
737 #endif |
|
738 |
|
739 extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, |
|
740 int clone); |
|
741 |
|
742 extern void RADEONEngineReset(ScrnInfoPtr pScrn); |
|
743 extern void RADEONEngineFlush(ScrnInfoPtr pScrn); |
|
744 extern void RADEONEngineRestore(ScrnInfoPtr pScrn); |
|
745 |
|
746 extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); |
|
747 extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data); |
|
748 |
|
749 extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); |
|
750 extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); |
|
751 |
|
752 extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); |
|
753 |
|
754 extern Bool RADEONAccelInit(ScreenPtr pScreen); |
|
755 #ifdef USE_EXA |
|
756 extern Bool RADEONSetupMemEXA (ScreenPtr pScreen); |
|
757 extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); |
|
758 #ifdef XF86DRI |
|
759 extern Bool RADEONDrawInitCP(ScreenPtr pScreen); |
|
760 #endif |
|
761 #endif |
|
762 #ifdef USE_XAA |
|
763 extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a); |
|
764 #endif |
|
765 extern void RADEONEngineInit(ScrnInfoPtr pScrn); |
|
766 extern Bool RADEONCursorInit(ScreenPtr pScreen); |
|
767 extern Bool RADEONDGAInit(ScreenPtr pScreen); |
|
768 |
|
769 extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); |
|
770 |
|
771 extern int RADEONMinBits(int val); |
|
772 |
|
773 extern void RADEONInitVideo(ScreenPtr pScreen); |
|
774 extern void RADEONResetVideo(ScrnInfoPtr pScrn); |
|
775 extern void R300CGWorkaround(ScrnInfoPtr pScrn); |
|
776 |
|
777 extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); |
|
778 extern void RADEONPllErrataAfterData(RADEONInfoPtr info); |
|
779 |
|
780 #ifdef XF86DRI |
|
781 #ifdef USE_XAA |
|
782 extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); |
|
783 #endif |
|
784 extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn); |
|
785 extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); |
|
786 extern void RADEONDRICloseScreen(ScreenPtr pScreen); |
|
787 extern void RADEONDRIResume(ScreenPtr pScreen); |
|
788 extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); |
|
789 extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); |
|
790 extern void RADEONDRIInitPageFlip(ScreenPtr pScreen); |
|
791 extern void RADEONDRIStop(ScreenPtr pScreen); |
|
792 |
|
793 extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); |
|
794 extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); |
|
795 extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn); |
|
796 extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info); |
|
797 |
|
798 extern CARD8* RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int bpp, |
|
799 unsigned int w, CARD32 dstPitch, |
|
800 CARD32 *bufPitch, CARD8 **dst, |
|
801 unsigned int *h, unsigned int *hpass); |
|
802 extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, |
|
803 unsigned int bpp, |
|
804 CARD8 *dst, CARD8 *src, |
|
805 unsigned int hpass, |
|
806 unsigned int dstPitch, |
|
807 unsigned int srcPitch); |
|
808 extern void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, |
|
809 int swap); |
|
810 |
|
811 extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10); |
|
812 extern Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn); |
|
813 extern Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn); |
|
814 extern Bool RADEONGetLVDSInfoFromBIOS (ScrnInfoPtr pScrn); |
|
815 extern Bool RADEONGetTMDSInfoFromBIOS (ScrnInfoPtr pScrn); |
|
816 extern Bool RADEONGetHardCodedEDIDFromBIOS (ScrnInfoPtr pScrn); |
|
817 |
|
818 #define RADEONCP_START(pScrn, info) \ |
|
819 do { \ |
|
820 int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_START); \ |
|
821 if (_ret) { \ |
|
822 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ |
|
823 "%s: CP start %d\n", __FUNCTION__, _ret); \ |
|
824 } \ |
|
825 info->CPStarted = TRUE; \ |
|
826 } while (0) |
|
827 |
|
828 #define RADEONCP_STOP(pScrn, info) \ |
|
829 do { \ |
|
830 int _ret; \ |
|
831 if (info->CPStarted) { \ |
|
832 _ret = RADEONCPStop(pScrn, info); \ |
|
833 if (_ret) { \ |
|
834 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ |
|
835 "%s: CP stop %d\n", __FUNCTION__, _ret); \ |
|
836 } \ |
|
837 info->CPStarted = FALSE; \ |
|
838 } \ |
|
839 RADEONEngineRestore(pScrn); \ |
|
840 info->CPRuns = FALSE; \ |
|
841 } while (0) |
|
842 |
|
843 #define RADEONCP_RESET(pScrn, info) \ |
|
844 do { \ |
|
845 if (RADEONCP_USE_RING_BUFFER(info->CPMode)) { \ |
|
846 int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESET); \ |
|
847 if (_ret) { \ |
|
848 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ |
|
849 "%s: CP reset %d\n", __FUNCTION__, _ret); \ |
|
850 } \ |
|
851 } \ |
|
852 } while (0) |
|
853 |
|
854 #define RADEONCP_REFRESH(pScrn, info) \ |
|
855 do { \ |
|
856 if (!info->CPInUse) { \ |
|
857 RADEON_WAIT_UNTIL_IDLE(); \ |
|
858 BEGIN_RING(6); \ |
|
859 OUT_RING_REG(RADEON_RE_TOP_LEFT, info->re_top_left); \ |
|
860 OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, info->re_width_height); \ |
|
861 OUT_RING_REG(RADEON_AUX_SC_CNTL, info->aux_sc_cntl); \ |
|
862 ADVANCE_RING(); \ |
|
863 info->CPInUse = TRUE; \ |
|
864 } \ |
|
865 } while (0) |
|
866 |
|
867 |
|
868 #define CP_PACKET0(reg, n) \ |
|
869 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) |
|
870 #define CP_PACKET1(reg0, reg1) \ |
|
871 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) |
|
872 #define CP_PACKET2() \ |
|
873 (RADEON_CP_PACKET2) |
|
874 #define CP_PACKET3(pkt, n) \ |
|
875 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
|
876 |
|
877 |
|
878 #define RADEON_VERBOSE 0 |
|
879 |
|
880 #define RING_LOCALS CARD32 *__head = NULL; int __expected; int __count = 0 |
|
881 |
|
882 #define BEGIN_RING(n) do { \ |
|
883 if (RADEON_VERBOSE) { \ |
|
884 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ |
|
885 "BEGIN_RING(%d) in %s\n", n, __FUNCTION__); \ |
|
886 } \ |
|
887 if (++info->dma_begin_count != 1) { \ |
|
888 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ |
|
889 "BEGIN_RING without end at %s:%d\n", \ |
|
890 info->dma_debug_func, info->dma_debug_lineno); \ |
|
891 info->dma_begin_count = 1; \ |
|
892 } \ |
|
893 info->dma_debug_func = __FILE__; \ |
|
894 info->dma_debug_lineno = __LINE__; \ |
|
895 if (!info->indirectBuffer) { \ |
|
896 info->indirectBuffer = RADEONCPGetBuffer(pScrn); \ |
|
897 info->indirectStart = 0; \ |
|
898 } else if (info->indirectBuffer->used + (n) * (int)sizeof(CARD32) > \ |
|
899 info->indirectBuffer->total) { \ |
|
900 RADEONCPFlushIndirect(pScrn, 1); \ |
|
901 } \ |
|
902 __expected = n; \ |
|
903 __head = (pointer)((char *)info->indirectBuffer->address + \ |
|
904 info->indirectBuffer->used); \ |
|
905 __count = 0; \ |
|
906 } while (0) |
|
907 |
|
908 #define ADVANCE_RING() do { \ |
|
909 if (info->dma_begin_count-- != 1) { \ |
|
910 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ |
|
911 "ADVANCE_RING without begin at %s:%d\n", \ |
|
912 __FILE__, __LINE__); \ |
|
913 info->dma_begin_count = 0; \ |
|
914 } \ |
|
915 if (__count != __expected) { \ |
|
916 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ |
|
917 "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \ |
|
918 __count, __expected, __FILE__, __LINE__); \ |
|
919 } \ |
|
920 if (RADEON_VERBOSE) { \ |
|
921 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ |
|
922 "ADVANCE_RING() start: %d used: %d count: %d\n", \ |
|
923 info->indirectStart, \ |
|
924 info->indirectBuffer->used, \ |
|
925 __count * (int)sizeof(CARD32)); \ |
|
926 } \ |
|
927 info->indirectBuffer->used += __count * (int)sizeof(CARD32); \ |
|
928 } while (0) |
|
929 |
|
930 #define OUT_RING(x) do { \ |
|
931 if (RADEON_VERBOSE) { \ |
|
932 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ |
|
933 " OUT_RING(0x%08x)\n", (unsigned int)(x)); \ |
|
934 } \ |
|
935 __head[__count++] = (x); \ |
|
936 } while (0) |
|
937 |
|
938 #define OUT_RING_REG(reg, val) \ |
|
939 do { \ |
|
940 OUT_RING(CP_PACKET0(reg, 0)); \ |
|
941 OUT_RING(val); \ |
|
942 } while (0) |
|
943 |
|
944 #define FLUSH_RING() \ |
|
945 do { \ |
|
946 if (RADEON_VERBOSE) \ |
|
947 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ |
|
948 "FLUSH_RING in %s\n", __FUNCTION__); \ |
|
949 if (info->indirectBuffer) { \ |
|
950 RADEONCPFlushIndirect(pScrn, 0); \ |
|
951 } \ |
|
952 } while (0) |
|
953 |
|
954 |
|
955 #define RADEON_WAIT_UNTIL_2D_IDLE() \ |
|
956 do { \ |
|
957 BEGIN_RING(2); \ |
|
958 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ |
|
959 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ |
|
960 RADEON_WAIT_HOST_IDLECLEAN)); \ |
|
961 ADVANCE_RING(); \ |
|
962 } while (0) |
|
963 |
|
964 #define RADEON_WAIT_UNTIL_3D_IDLE() \ |
|
965 do { \ |
|
966 BEGIN_RING(2); \ |
|
967 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ |
|
968 OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \ |
|
969 RADEON_WAIT_HOST_IDLECLEAN)); \ |
|
970 ADVANCE_RING(); \ |
|
971 } while (0) |
|
972 |
|
973 #define RADEON_WAIT_UNTIL_IDLE() \ |
|
974 do { \ |
|
975 if (RADEON_VERBOSE) { \ |
|
976 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ |
|
977 "WAIT_UNTIL_IDLE() in %s\n", __FUNCTION__); \ |
|
978 } \ |
|
979 BEGIN_RING(2); \ |
|
980 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ |
|
981 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ |
|
982 RADEON_WAIT_3D_IDLECLEAN | \ |
|
983 RADEON_WAIT_HOST_IDLECLEAN)); \ |
|
984 ADVANCE_RING(); \ |
|
985 } while (0) |
|
986 |
|
987 #define RADEON_FLUSH_CACHE() \ |
|
988 do { \ |
|
989 BEGIN_RING(2); \ |
|
990 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ |
|
991 OUT_RING(RADEON_RB3D_DC_FLUSH); \ |
|
992 ADVANCE_RING(); \ |
|
993 } while (0) |
|
994 |
|
995 #define RADEON_PURGE_CACHE() \ |
|
996 do { \ |
|
997 BEGIN_RING(2); \ |
|
998 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ |
|
999 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ |
|
1000 ADVANCE_RING(); \ |
|
1001 } while (0) |
|
1002 |
|
1003 #endif /* XF86DRI */ |
|
1004 |
|
1005 static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) |
|
1006 { |
|
1007 #ifdef USE_EXA |
|
1008 if (info->useEXA) |
|
1009 exaMarkSync(pScrn->pScreen); |
|
1010 #endif |
|
1011 #ifdef USE_XAA |
|
1012 if (!info->useEXA) |
|
1013 SET_SYNC_FLAG(info->accel); |
|
1014 #endif |
|
1015 } |
|
1016 |
|
1017 static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) |
|
1018 { |
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1019 #ifdef USE_EXA |
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1020 if (info->useEXA) |
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1021 exaWaitSync(pScrn->pScreen); |
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1022 #endif |
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1023 #ifdef USE_XAA |
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1024 if (!info->useEXA && info->accel) |
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1025 info->accel->Sync(pScrn); |
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1026 #endif |
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1027 } |
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1028 |
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1029 #endif /* _RADEON_H_ */ |