1 From 3c03d9f1efbbacec6e8be58da99bf0977a8e0fec Mon Sep 17 00:00:00 2001 |
|
2 From: Adam Jackson <[email protected]> |
|
3 Date: Mon, 18 Aug 2008 14:37:42 -0400 |
|
4 Subject: [PATCH] Remove sparcPci.c |
|
5 |
|
6 There is no way this code can have been building for anyone since pciaccess |
|
7 was merged. BSD and Linux were already using OS code on sparc, the only |
|
8 people who could want this are Solaris, who should be using pciaccess |
|
9 anyway. |
|
10 --- |
|
11 configure.ac | 3 |
|
12 hw/xfree86/os-support/bus/Makefile.am | 4 |
|
13 hw/xfree86/os-support/bus/Pci.h | 10 |
|
14 hw/xfree86/os-support/bus/sparcPci.c | 979 --------------------------------- |
|
15 4 files changed, 2 insertions(+), 994 deletions(-) |
|
16 |
|
17 diff --git a/configure.ac b/configure.ac |
|
18 index 95a084f..52d35c3 100644 |
|
19 --- a/configure.ac |
|
20 +++ b/configure.ac |
|
21 @@ -1217,7 +1217,6 @@ AC_MSG_RESULT([$XORG]) |
|
22 xorg_bus_linuxpci=no |
|
23 xorg_bus_bsdpci=no |
|
24 xorg_bus_ix86pci=no |
|
25 -xorg_bus_sparcpci=no |
|
26 xorg_bus_sparc=no |
|
27 |
|
28 if test "x$XORG" = xyes; then |
|
29 @@ -1344,7 +1343,6 @@ if test "x$XORG" = xyes; then |
|
30 |
|
31 case $host_cpu in |
|
32 sparc*) |
|
33 - xorg_bus_sparcpci="yes" |
|
34 xorg_bus_sparc="yes" |
|
35 ;; |
|
36 i*86|x86_64*|amd64*) |
|
37 @@ -1450,7 +1448,6 @@ AM_CONDITIONAL([XORG], [test "x$XORG" = |
|
38 AM_CONDITIONAL([XORG_BUS_LINUXPCI], [test "x$xorg_bus_linuxpci" = xyes]) |
|
39 AM_CONDITIONAL([XORG_BUS_BSDPCI], [test "x$xorg_bus_bsdpci" = xyes]) |
|
40 AM_CONDITIONAL([XORG_BUS_IX86PCI], [test "x$xorg_bus_ix86pci" = xyes]) |
|
41 -AM_CONDITIONAL([XORG_BUS_SPARCPCI], [test "x$xorg_bus_sparcpci" = xyes]) |
|
42 AM_CONDITIONAL([XORG_BUS_SPARC], [test "x$xorg_bus_sparc" = xyes]) |
|
43 AM_CONDITIONAL([LINUX_IA64], [test "x$linux_ia64" = xyes]) |
|
44 AM_CONDITIONAL([LINUX_ALPHA], [test "x$linux_alpha" = xyes]) |
|
45 diff --git a/hw/xfree86/os-support/bus/Makefile.am b/hw/xfree86/os-support/bus/Makefile.am |
|
46 index 94c3750..5199340 100644 |
|
47 --- a/hw/xfree86/os-support/bus/Makefile.am |
|
48 +++ b/hw/xfree86/os-support/bus/Makefile.am |
|
49 @@ -15,10 +15,6 @@ if XORG_BUS_IX86PCI |
|
50 PCI_SOURCES += ix86Pci.c |
|
51 endif |
|
52 |
|
53 -if XORG_BUS_SPARCPCI |
|
54 -PCI_SOURCES += sparcPci.c |
|
55 -endif |
|
56 - |
|
57 if XORG_BUS_SPARC |
|
58 PLATFORM_SOURCES = Sbus.c |
|
59 sdk_HEADERS += xf86Sbus.h |
|
60 diff --git a/hw/xfree86/os-support/bus/Pci.h b/hw/xfree86/os-support/bus/Pci.h |
|
61 index 26ba947..e56d61e 100644 |
|
62 --- a/hw/xfree86/os-support/bus/Pci.h |
|
63 +++ b/hw/xfree86/os-support/bus/Pci.h |
|
64 @@ -198,15 +198,9 @@ #endif /* defined(linux) */ |
|
65 |
|
66 #if !defined(ARCH_PCI_INIT) |
|
67 #warning You really need to port to libpciaccess. |
|
68 -/* |
|
69 - * Select architecture specific PCI init function |
|
70 - */ |
|
71 #if defined(__i386__) || defined(__i386) || defined(__amd64__) || defined(__amd64) |
|
72 -# define ARCH_PCI_INIT ix86PciInit |
|
73 -#elif defined(__sparc__) || defined(sparc) |
|
74 -# define ARCH_PCI_INIT sparcPciInit |
|
75 -# define ARCH_PCI_PCI_BRIDGE sparcPciPciBridge |
|
76 -#endif |
|
77 +#define ARCH_PCI_INIT ix86PciInit |
|
78 +#endif /* i386/amd64 */ |
|
79 #endif /* !defined(ARCH_PCI_INIT) */ |
|
80 |
|
81 #ifndef ARCH_PCI_INIT |
|
82 diff --git a/hw/xfree86/os-support/bus/sparcPci.c b/hw/xfree86/os-support/bus/sparcPci.c |
|
83 deleted file mode 100644 |
|
84 index 2d8039c..0000000 |
|
85 --- a/hw/xfree86/os-support/bus/sparcPci.c |
|
86 +++ /dev/null |
|
87 @@ -1,979 +0,0 @@ |
|
88 -/* |
|
89 - * Copyright (C) 2001-2003 The XFree86 Project, Inc. All Rights Reserved. |
|
90 - * |
|
91 - * Permission is hereby granted, free of charge, to any person obtaining a copy |
|
92 - * of this software and associated documentation files (the "Software"), to |
|
93 - * deal in the Software without restriction, including without limitation the |
|
94 - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
|
95 - * sell copies of the Software, and to permit persons to whom the Software is |
|
96 - * furnished to do so, subject to the following conditions: |
|
97 - * |
|
98 - * The above copyright notice and this permission notice shall be included in |
|
99 - * all copies or substantial portions of the Software. |
|
100 - * |
|
101 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
|
102 - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|
103 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
|
104 - * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER |
|
105 - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
|
106 - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
|
107 - * |
|
108 - * Except as contained in this notice, the name of the XFree86 Project shall |
|
109 - * not be used in advertising or otherwise to promote the sale, use or other |
|
110 - * dealings in this Software without prior written authorization from the |
|
111 - * XFree86 Project. |
|
112 - */ |
|
113 - |
|
114 -#ifdef HAVE_XORG_CONFIG_H |
|
115 -#include <xorg-config.h> |
|
116 -#endif |
|
117 - |
|
118 -#include "xf86.h" |
|
119 -#include "xf86Priv.h" |
|
120 -#include "xf86_OSlib.h" |
|
121 -#include "Pci.h" |
|
122 -#include "xf86sbusBus.h" |
|
123 - |
|
124 -#if defined(sun) |
|
125 - |
|
126 -extern char *apertureDevName; |
|
127 -static int apertureFd = -1; |
|
128 - |
|
129 -/* |
|
130 - * A version of xf86MapVidMem() that allows for 64-bit displacements (but not |
|
131 - * sizes). Areas thus mapped can be unmapped by xf86UnMapVidMem(). |
|
132 - */ |
|
133 -static pointer |
|
134 -sparcMapAperture(int iScreen, int Flags, |
|
135 - unsigned long long Base, unsigned long Size) |
|
136 -{ |
|
137 - pointer result; |
|
138 - static int lastFlags = 0; |
|
139 - |
|
140 - /* Assume both Base & Size are multiples of the page size */ |
|
141 - |
|
142 - if ((apertureFd < 0) || (Flags != lastFlags)) { |
|
143 - if (apertureFd >= 0) |
|
144 - close(apertureFd); |
|
145 - lastFlags = Flags; |
|
146 - apertureFd = open(apertureDevName, |
|
147 - (Flags & VIDMEM_READONLY) ? O_RDONLY : O_RDWR); |
|
148 - if (apertureFd < 0) |
|
149 - FatalError("sparcMapAperture: open failure: %s\n", |
|
150 - strerror(errno)); |
|
151 - } |
|
152 - |
|
153 - result = mmap(NULL, Size, |
|
154 - (Flags & VIDMEM_READONLY) ? |
|
155 - PROT_READ : (PROT_READ | PROT_WRITE), |
|
156 - MAP_SHARED, apertureFd, (off_t)Base); |
|
157 - |
|
158 - if (result == MAP_FAILED) |
|
159 - FatalError("sparcMapAperture: mmap failure: %s\n", strerror(errno)); |
|
160 - |
|
161 - return result; |
|
162 -} |
|
163 - |
|
164 -/* |
|
165 - * Platform-specific bus privates. |
|
166 - */ |
|
167 -typedef struct _sparcDomainRec { |
|
168 - unsigned long long io_addr, io_size; |
|
169 - unsigned long long mem_addr, mem_size; |
|
170 - pointer pci, io; |
|
171 - int bus_min, bus_max; |
|
172 - unsigned char dfn_mask[256 / 8]; |
|
173 -} sparcDomainRec, *sparcDomainPtr; |
|
174 - |
|
175 -#define SetBitInMap(bit, map) \ |
|
176 - do { \ |
|
177 - int _bit = (bit); \ |
|
178 - (map)[_bit >> 3] |= 1 << (_bit & 7); \ |
|
179 - } while (0) |
|
180 - |
|
181 -#define IsBitSetInMap(bit, map) \ |
|
182 - ((map)[(bit) >> 3] & (1 << ((bit) & 7))) |
|
183 - |
|
184 -/* |
|
185 - * Domain 0 is reserved for the one that represents the system as a whole, i.e. |
|
186 - * the one without any resource relocations. |
|
187 - */ |
|
188 -#define MAX_DOMAINS (MAX_PCI_BUSES / 256) |
|
189 -static sparcDomainPtr xf86DomainInfo[MAX_DOMAINS]; |
|
190 -static int pciNumDomains = 1; |
|
191 - |
|
192 -/* Variables that are assigned this must be declared volatile */ |
|
193 -#define PciReg(base, tag, off, type) \ |
|
194 - *(volatile type *)(pointer)((char *)(base) + \ |
|
195 - (PCI_TAG_NO_DOMAIN(tag) | (off))) |
|
196 - |
|
197 -/* Generic SPARC PCI access functions */ |
|
198 -static CARD32 |
|
199 -sparcPciCfgRead32(PCITAG tag, int off) |
|
200 -{ |
|
201 - pciBusInfo_t *pBusInfo; |
|
202 - sparcDomainPtr pDomain; |
|
203 - volatile CARD32 result = (CARD32)(-1); /* Must be volatile */ |
|
204 - int bus; |
|
205 - |
|
206 - if ((off >= 0) && (off <= 252) && !(off & 3) && |
|
207 - ((bus = PCI_BUS_FROM_TAG(tag)) < pciNumBuses) && |
|
208 - (pBusInfo = pciBusInfo[bus]) && (pDomain = pBusInfo->pciBusPriv) && |
|
209 - (bus >= pDomain->bus_min) && (bus < pDomain->bus_max) && |
|
210 - ((bus > pDomain->bus_min) || |
|
211 - IsBitSetInMap(PCI_DFN_FROM_TAG(tag), pDomain->dfn_mask))) { |
|
212 - result = PciReg(pDomain->pci, tag, off, CARD32); |
|
213 - |
|
214 - result = PCI_CPU(result); |
|
215 - } |
|
216 - |
|
217 - return result; |
|
218 -} |
|
219 - |
|
220 -static void |
|
221 -sparcPciCfgWrite32(PCITAG tag, int off, CARD32 val) |
|
222 -{ |
|
223 - pciBusInfo_t *pBusInfo; |
|
224 - sparcDomainPtr pDomain; |
|
225 - int bus; |
|
226 - |
|
227 - if ((off < 0) || (off > 252) || (off & 3) || |
|
228 - ((bus = PCI_BUS_FROM_TAG(tag)) >= pciNumBuses) || |
|
229 - !(pBusInfo = pciBusInfo[bus]) || !(pDomain = pBusInfo->pciBusPriv) || |
|
230 - (bus < pDomain->bus_min) || (bus >= pDomain->bus_max) || |
|
231 - ((bus == pDomain->bus_min) && |
|
232 - !IsBitSetInMap(PCI_DFN_FROM_TAG(tag), pDomain->dfn_mask))) |
|
233 - return; |
|
234 - |
|
235 - val = PCI_CPU(val); |
|
236 - PciReg(pDomain->pci, tag, off, CARD32) = val; |
|
237 -} |
|
238 - |
|
239 -static void |
|
240 -sparcPciCfgSetBits32(PCITAG tag, int off, CARD32 mask, CARD32 bits) |
|
241 -{ |
|
242 - CARD32 PciVal; |
|
243 - |
|
244 - PciVal = sparcPciCfgRead32(tag, off); |
|
245 - PciVal &= ~mask; |
|
246 - PciVal |= bits; |
|
247 - sparcPciCfgWrite32(tag, off, PciVal); |
|
248 -} |
|
249 - |
|
250 -static pciBusFuncs_t sparcPCIFunctions = |
|
251 -{ |
|
252 - sparcPciCfgRead32, |
|
253 - sparcPciCfgWrite32, |
|
254 - sparcPciCfgSetBits32, |
|
255 - pciAddrNOOP, |
|
256 - pciAddrNOOP |
|
257 -}; |
|
258 - |
|
259 -/* |
|
260 - * Sabre-specific versions of the above because of its peculiar access size |
|
261 - * requirements. |
|
262 - */ |
|
263 -static CARD32 |
|
264 -sabrePciCfgRead32(PCITAG tag, int off) |
|
265 -{ |
|
266 - pciBusInfo_t *pBusInfo; |
|
267 - sparcDomainPtr pDomain; |
|
268 - volatile CARD32 result; /* Must be volatile */ |
|
269 - int bus; |
|
270 - |
|
271 - if (PCI_BDEV_FROM_TAG(tag)) |
|
272 - return sparcPciCfgRead32(tag, off); |
|
273 - |
|
274 - if (PCI_FUNC_FROM_TAG(tag) || (off < 0) || (off > 252) || (off & 3) || |
|
275 - ((bus = PCI_BUS_FROM_TAG(tag)) >= pciNumBuses) || |
|
276 - !(pBusInfo = pciBusInfo[bus]) || !(pDomain = pBusInfo->pciBusPriv) || |
|
277 - (bus != pDomain->bus_min)) |
|
278 - return (CARD32)(-1); |
|
279 - |
|
280 - if (off < 8) { |
|
281 - result = (PciReg(pDomain->pci, tag, off, CARD16) << 16) | |
|
282 - PciReg(pDomain->pci, tag, off + 2, CARD16); |
|
283 - return PCI_CPU(result); |
|
284 - } |
|
285 - |
|
286 - result = (PciReg(pDomain->pci, tag, off + 3, CARD8) << 24) | |
|
287 - (PciReg(pDomain->pci, tag, off + 2, CARD8) << 16) | |
|
288 - (PciReg(pDomain->pci, tag, off + 1, CARD8) << 8) | |
|
289 - (PciReg(pDomain->pci, tag, off , CARD8) ); |
|
290 - return result; |
|
291 -} |
|
292 - |
|
293 -static void |
|
294 -sabrePciCfgWrite32(PCITAG tag, int off, CARD32 val) |
|
295 -{ |
|
296 - pciBusInfo_t *pBusInfo; |
|
297 - sparcDomainPtr pDomain; |
|
298 - int bus; |
|
299 - |
|
300 - if (PCI_BDEV_FROM_TAG(tag)) |
|
301 - sparcPciCfgWrite32(tag, off, val); |
|
302 - else if (!PCI_FUNC_FROM_TAG(tag) && |
|
303 - (off >= 0) && (off <= 252) && !(off & 3) && |
|
304 - ((bus = PCI_BUS_FROM_TAG(tag)) < pciNumBuses) && |
|
305 - (pBusInfo = pciBusInfo[bus]) && |
|
306 - (pDomain = pBusInfo->pciBusPriv) && |
|
307 - (bus == pDomain->bus_min)) { |
|
308 - if (off < 8) { |
|
309 - val = PCI_CPU(val); |
|
310 - PciReg(pDomain->pci, tag, off , CARD16) = val >> 16; |
|
311 - PciReg(pDomain->pci, tag, off + 2, CARD16) = val; |
|
312 - } else { |
|
313 - PciReg(pDomain->pci, tag, off , CARD8) = val; |
|
314 - PciReg(pDomain->pci, tag, off + 1, CARD8) = val >> 8; |
|
315 - PciReg(pDomain->pci, tag, off + 2, CARD8) = val >> 16; |
|
316 - PciReg(pDomain->pci, tag, off + 3, CARD8) = val >> 24; |
|
317 - } |
|
318 - } |
|
319 -} |
|
320 - |
|
321 -static void |
|
322 -sabrePciCfgSetBits32(PCITAG tag, int off, CARD32 mask, CARD32 bits) |
|
323 -{ |
|
324 - CARD32 PciVal; |
|
325 - |
|
326 - PciVal = sabrePciCfgRead32(tag, off); |
|
327 - PciVal &= ~mask; |
|
328 - PciVal |= bits; |
|
329 - sabrePciCfgWrite32(tag, off, PciVal); |
|
330 -} |
|
331 - |
|
332 -static pciBusFuncs_t sabrePCIFunctions = |
|
333 -{ |
|
334 - sabrePciCfgRead32, |
|
335 - sabrePciCfgWrite32, |
|
336 - sabrePciCfgSetBits32, |
|
337 - pciAddrNOOP, |
|
338 - pciAddrNOOP |
|
339 -}; |
|
340 - |
|
341 -static int pagemask; |
|
342 - |
|
343 -/* Scan PROM for all PCI host bridges in the system */ |
|
344 -void |
|
345 -sparcPciInit(void) |
|
346 -{ |
|
347 - int node, node2; |
|
348 - |
|
349 - if (!xf86LinearVidMem()) |
|
350 - return; |
|
351 - |
|
352 - apertureFd = open(apertureDevName, O_RDWR); |
|
353 - if (apertureFd < 0) { |
|
354 - xf86Msg(X_ERROR, |
|
355 - "sparcPciInit: open failure: %s\n", strerror(errno)); |
|
356 - return; |
|
357 - } |
|
358 - |
|
359 - sparcPromInit(); |
|
360 - pagemask = getpagesize() - 1; |
|
361 - |
|
362 - for (node = promGetChild(promRootNode); |
|
363 - node; |
|
364 - node = promGetSibling(node)) { |
|
365 - unsigned long long pci_addr; |
|
366 - sparcDomainRec domain; |
|
367 - sparcDomainPtr pDomain; |
|
368 - pciBusFuncs_p pFunctions; |
|
369 - char *prop_val; |
|
370 - int prop_len, bus; |
|
371 - |
|
372 - prop_val = promGetProperty("name", &prop_len); |
|
373 - /* Some PROMs include the trailing null; some don't */ |
|
374 - if (!prop_val || (prop_len < 3) || (prop_len > 4) || |
|
375 - strcmp(prop_val, "pci")) |
|
376 - continue; |
|
377 - |
|
378 - prop_val = promGetProperty("model", &prop_len); |
|
379 - if (!prop_val || (prop_len <= 0)) { |
|
380 - prop_val = promGetProperty("compatible", &prop_len); |
|
381 - if (!prop_val || (prop_len <= 0)) |
|
382 - continue; |
|
383 - } |
|
384 - |
|
385 - pFunctions = &sparcPCIFunctions; |
|
386 - (void)memset(&domain, 0, sizeof(domain)); |
|
387 - |
|
388 - if (!strncmp("SUNW,sabre", prop_val, prop_len) || |
|
389 - !strncmp("pci108e,a000", prop_val, prop_len) || |
|
390 - !strncmp("pci108e,a001", prop_val, prop_len)) { |
|
391 - /* |
|
392 - * There can only be one "Sabre" bridge in a system. It provides |
|
393 - * PCI configuration space, a 24-bit I/O space and a 32-bit memory |
|
394 - * space, all three of which are at fixed physical CPU addresses. |
|
395 - */ |
|
396 - static Bool sabre_seen = FALSE; |
|
397 - |
|
398 - xf86Msg(X_INFO, |
|
399 - "Sabre or Hummingbird PCI host bridge found (\"%s\")\n", |
|
400 - prop_val); |
|
401 - |
|
402 - /* There can only be one Sabre */ |
|
403 - if (sabre_seen) |
|
404 - continue; |
|
405 - sabre_seen = TRUE; |
|
406 - |
|
407 - /* Get "bus-range" property */ |
|
408 - prop_val = promGetProperty("bus-range", &prop_len); |
|
409 - if (!prop_val || (prop_len != 8) || |
|
410 - (((unsigned int *)prop_val)[0]) || |
|
411 - (((unsigned int *)prop_val)[1] >= 256)) |
|
412 - continue; |
|
413 - |
|
414 - pci_addr = 0x01fe01000000ull; |
|
415 - domain.io_addr = 0x01fe02000000ull; |
|
416 - domain.io_size = 0x000001000000ull; |
|
417 - domain.mem_addr = 0x01ff00000000ull; |
|
418 - domain.mem_size = 0x000100000000ull; |
|
419 - domain.bus_min = 0; /* Always */ |
|
420 - domain.bus_max = ((int *)prop_val)[1]; |
|
421 - |
|
422 - pFunctions = &sabrePCIFunctions; |
|
423 - } else |
|
424 - if (!strncmp("SUNW,psycho", prop_val, prop_len) || |
|
425 - !strncmp("pci108e,8000", prop_val, prop_len)) { |
|
426 - /* |
|
427 - * A "Psycho" host bridge provides two PCI interfaces, each with |
|
428 - * its own 16-bit I/O and 31-bit memory spaces. Both share the |
|
429 - * same PCI configuration space. Here, they are assigned separate |
|
430 - * domain numbers to prevent unintentional I/O and/or memory |
|
431 - * resource conflicts. |
|
432 - */ |
|
433 - xf86Msg(X_INFO, |
|
434 - "Psycho PCI host bridge found (\"%s\")\n", prop_val); |
|
435 - |
|
436 - /* Get "bus-range" property */ |
|
437 - prop_val = promGetProperty("bus-range", &prop_len); |
|
438 - if (!prop_val || (prop_len != 8) || |
|
439 - (((unsigned int *)prop_val)[1] >= 256) || |
|
440 - (((unsigned int *)prop_val)[0] > ((unsigned int *)prop_val)[1])) |
|
441 - continue; |
|
442 - |
|
443 - domain.bus_min = ((int *)prop_val)[0]; |
|
444 - domain.bus_max = ((int *)prop_val)[1]; |
|
445 - |
|
446 - /* Get "ranges" property */ |
|
447 - prop_val = promGetProperty("ranges", &prop_len); |
|
448 - if (!prop_val || (prop_len != 112) || |
|
449 - prop_val[0] || (prop_val[28] != 0x01u) || |
|
450 - (prop_val[56] != 0x02u) || (prop_val[84] != 0x03u) || |
|
451 - (((unsigned int *)prop_val)[4] != 0x01000000u) || |
|
452 - ((unsigned int *)prop_val)[5] || |
|
453 - ((unsigned int *)prop_val)[12] || |
|
454 - (((unsigned int *)prop_val)[13] != 0x00010000u) || |
|
455 - ((unsigned int *)prop_val)[19] || |
|
456 - (((unsigned int *)prop_val)[20] != 0x80000000u) || |
|
457 - ((((unsigned int *)prop_val)[11] & ~0x00010000u) != |
|
458 - 0x02000000u) || |
|
459 - (((unsigned int *)prop_val)[18] & ~0x80000000u) || |
|
460 - (((unsigned int *)prop_val)[3] != |
|
461 - ((unsigned int *)prop_val)[10]) || |
|
462 - (((unsigned int *)prop_val)[17] != |
|
463 - ((unsigned int *)prop_val)[24]) || |
|
464 - (((unsigned int *)prop_val)[18] != |
|
465 - ((unsigned int *)prop_val)[25]) || |
|
466 - (((unsigned int *)prop_val)[19] != |
|
467 - ((unsigned int *)prop_val)[26]) || |
|
468 - (((unsigned int *)prop_val)[20] != |
|
469 - ((unsigned int *)prop_val)[27])) |
|
470 - continue; |
|
471 - |
|
472 - /* Use memcpy() to avoid alignment issues */ |
|
473 - (void)memcpy(&pci_addr, prop_val + 12, |
|
474 - sizeof(pci_addr)); |
|
475 - (void)memcpy(&domain.io_addr, prop_val + 40, |
|
476 - sizeof(domain.io_addr)); |
|
477 - (void)memcpy(&domain.mem_addr, prop_val + 68, |
|
478 - sizeof(domain.mem_addr)); |
|
479 - |
|
480 - domain.io_size = 0x000000010000ull; |
|
481 - domain.mem_size = 0x000080000000ull; |
|
482 - } else |
|
483 - if (!strncmp("SUNW,schizo", prop_val, prop_len) || |
|
484 - !strncmp("pci108e,8001", prop_val, prop_len)) { |
|
485 - /* |
|
486 - * I have no docs on the "Schizo", but judging from the Linux |
|
487 - * kernel, it also provides two PCI domains. Each PCI |
|
488 - * configuration space is the usual 16M in size, followed by a |
|
489 - * variable-length I/O space. Each domain also provides a |
|
490 - * variable-length memory space. The kernel seems to think the I/O |
|
491 - * spaces are 16M long, and the memory spaces, 2G, but these |
|
492 - * assumptions are actually only present in source code comments. |
|
493 - * Sun has, however, confirmed to me the validity of these |
|
494 - * assumptions. |
|
495 - */ |
|
496 - volatile unsigned long long mem_match, mem_mask, io_match, io_mask; |
|
497 - unsigned long Offset; |
|
498 - pointer pSchizo; |
|
499 - |
|
500 - xf86Msg(X_INFO, |
|
501 - "Schizo PCI host bridge found (\"%s\")\n", prop_val); |
|
502 - |
|
503 - /* Get "bus-range" property */ |
|
504 - prop_val = promGetProperty("bus-range", &prop_len); |
|
505 - if (!prop_val || (prop_len != 8) || |
|
506 - (((unsigned int *)prop_val)[1] >= 256) || |
|
507 - (((unsigned int *)prop_val)[0] > ((unsigned int *)prop_val)[1])) |
|
508 - continue; |
|
509 - |
|
510 - domain.bus_min = ((int *)prop_val)[0]; |
|
511 - domain.bus_max = ((int *)prop_val)[1]; |
|
512 - |
|
513 - /* Get "reg" property */ |
|
514 - prop_val = promGetProperty("reg", &prop_len); |
|
515 - if (!prop_val || (prop_len != 48)) |
|
516 - continue; |
|
517 - |
|
518 - /* Temporarily map some of Schizo's registers */ |
|
519 - pSchizo = sparcMapAperture(-1, VIDMEM_MMIO, |
|
520 - ((unsigned long long *)prop_val)[2] - 0x000000010000ull, |
|
521 - 0x00010000ul); |
|
522 - |
|
523 - /* Determine where PCI config, I/O and memory spaces reside */ |
|
524 - if ((((unsigned long long *)prop_val)[0] & 0x000000700000ull) == |
|
525 - 0x000000600000ull) |
|
526 - Offset = 0x0040; |
|
527 - else |
|
528 - Offset = 0x0060; |
|
529 - |
|
530 - mem_match = PciReg(pSchizo, 0, Offset, unsigned long long); |
|
531 - mem_mask = PciReg(pSchizo, 0, Offset + 8, unsigned long long); |
|
532 - io_match = PciReg(pSchizo, 0, Offset + 16, unsigned long long); |
|
533 - io_mask = PciReg(pSchizo, 0, Offset + 24, unsigned long long); |
|
534 - |
|
535 - /* Unmap Schizo registers */ |
|
536 - xf86UnMapVidMem(-1, pSchizo, 0x00010000ul); |
|
537 - |
|
538 - /* Calculate sizes */ |
|
539 - mem_mask = (((mem_mask - 1) ^ mem_mask) >> 1) + 1; |
|
540 - io_mask = (((io_mask - 1) ^ io_mask ) >> 1) + 1; |
|
541 - |
|
542 - if (io_mask <= 0x000001000000ull) /* Nothing left for I/O */ |
|
543 - continue; |
|
544 - |
|
545 - domain.mem_addr = mem_match & ~0x8000000000000000ull; |
|
546 - domain.mem_size = mem_mask; |
|
547 - pci_addr = io_match & ~0x8000000000000000ull; |
|
548 - domain.io_addr = pci_addr + 0x0000000001000000ull; |
|
549 - domain.io_size = io_mask - 0x0000000001000000ull; |
|
550 - } else { |
|
551 - xf86Msg(X_WARNING, "Unknown PCI host bridge: \"%s\"\n", prop_val); |
|
552 - continue; |
|
553 - } |
|
554 - |
|
555 - /* Only map as much PCI configuration as we need */ |
|
556 - domain.pci = (char *)sparcMapAperture(-1, VIDMEM_MMIO, |
|
557 - pci_addr + PCI_MAKE_TAG(domain.bus_min, 0, 0), |
|
558 - PCI_MAKE_TAG(domain.bus_max - domain.bus_min + 1, 0, 0)) - |
|
559 - PCI_MAKE_TAG(domain.bus_min, 0, 0); |
|
560 - |
|
561 - /* Allocate a domain record */ |
|
562 - pDomain = xnfalloc(sizeof(sparcDomainRec)); |
|
563 - *pDomain = domain; |
|
564 - |
|
565 - /* |
|
566 - * Allocate and prime pciBusInfo records. These are allocated one at a |
|
567 - * time because those for empty buses are eventually released. |
|
568 - */ |
|
569 - bus = pDomain->bus_min = |
|
570 - PCI_MAKE_BUS(pciNumDomains, domain.bus_min); |
|
571 - pciNumBuses = pDomain->bus_max = |
|
572 - PCI_MAKE_BUS(pciNumDomains, domain.bus_max) + 1; |
|
573 - |
|
574 - pciBusInfo[bus] = xnfcalloc(1, sizeof(pciBusInfo_t)); |
|
575 - pciBusInfo[bus]->configMech = PCI_CFG_MECH_OTHER; |
|
576 - pciBusInfo[bus]->numDevices = 32; |
|
577 - pciBusInfo[bus]->funcs = pFunctions; |
|
578 - pciBusInfo[bus]->pciBusPriv = pDomain; |
|
579 - while (++bus < pciNumBuses) { |
|
580 - pciBusInfo[bus] = xnfalloc(sizeof(pciBusInfo_t)); |
|
581 - *(pciBusInfo[bus]) = *(pciBusInfo[bus - 1]); |
|
582 - pciBusInfo[bus]->funcs = &sparcPCIFunctions; |
|
583 - } |
|
584 - |
|
585 - /* Next domain, please... */ |
|
586 - xf86DomainInfo[pciNumDomains++] = pDomain; |
|
587 - |
|
588 - /* |
|
589 - * OK, enough of the straight-forward stuff. Time to deal with some |
|
590 - * brokenness... |
|
591 - * |
|
592 - * The PCI specs require that when a bus transaction remains unclaimed |
|
593 - * for too long, the master entity on that bus is to cancel the |
|
594 - * transaction it issued or passed on with a master abort. Two |
|
595 - * outcomes are possible: |
|
596 - * |
|
597 - * - the master abort can be treated as an error that is propogated |
|
598 - * back through the bus tree to the entity that ultimately originated |
|
599 - * the transaction; or |
|
600 - * - the transaction can be allowed to complete normally, which means |
|
601 - * that writes are ignored and reads return all ones. |
|
602 - * |
|
603 - * In the first case, if the CPU happens to be at the tail end of the |
|
604 - * tree path through one of its host bridges, it will be told there is |
|
605 - * a hardware mal-function, despite being generated by software. |
|
606 - * |
|
607 - * For a software function (be it firmware, OS or userland application) |
|
608 - * to determine how a PCI bus tree is populated, it must be able to |
|
609 - * detect when master aborts occur. Obviously, PCI discovery is much |
|
610 - * simpler when master aborts are allowed to complete normally. |
|
611 - * |
|
612 - * Unfortunately, a number of non-Intel PCI implementations have chosen |
|
613 - * to treat master aborts as severe errors. The net effect is to |
|
614 - * cripple PCI discovery algorithms in userland. |
|
615 - * |
|
616 - * On SPARCs, master aborts cause a number of different behaviours, |
|
617 - * including delivering a signal to the userland application, rebooting |
|
618 - * the system, "dropping down" to firmware, or, worst of all, bus |
|
619 - * lockouts. Even in the first case, the SIGBUS signal that is |
|
620 - * eventually generated isn't delivered in a timely enough fashion to |
|
621 - * allow an application to reliably detect the master abort that |
|
622 - * ultimately caused it. |
|
623 - * |
|
624 - * This can be somewhat mitigated. On all architectures, master aborts |
|
625 - * that occur on secondary buses can be forced to complete normally |
|
626 - * because the PCI-to-PCI bridges that serve them are governed by an |
|
627 - * industry-wide specification. (This is just another way of saying |
|
628 - * that whatever justification there might be for erroring out master |
|
629 - * aborts is deemed by the industry as insufficient to generate more |
|
630 - * PCI non-compliance than there already is...) |
|
631 - * |
|
632 - * This leaves us with master aborts that occur on primary buses. |
|
633 - * There is no specification for host-to-PCI bridges. Bridges used in |
|
634 - * SPARCs can be told to ignore all PCI errors, but not specifically |
|
635 - * master aborts. Not only is this too coarse-grained, but |
|
636 - * master-aborted read transactions on the primary bus end up returning |
|
637 - * garbage rather than all ones. |
|
638 - * |
|
639 - * I have elected to work around this the only way I can think of doing |
|
640 - * so right now. The following scans an additional PROM level and |
|
641 - * builds a device/function map for the primary bus. I can only hope |
|
642 - * this PROM information represents all devices on the primary bus, |
|
643 - * rather than only a subset of them. |
|
644 - * |
|
645 - * Master aborts are useful in other ways too, that are not addressed |
|
646 - * here. These include determining whether or not a domain provides |
|
647 - * VGA, or if a PCI device actually implements PCI disablement. |
|
648 - * |
|
649 - * --- TSI @ UQV 2001.09.19 |
|
650 - */ |
|
651 - for (node2 = promGetChild(node); |
|
652 - node2; |
|
653 - node2 = promGetSibling(node2)) { |
|
654 - /* Get "reg" property */ |
|
655 - prop_val = promGetProperty("reg", &prop_len); |
|
656 - if (!prop_val || (prop_len % 20)) |
|
657 - continue; |
|
658 - |
|
659 - /* |
|
660 - * It's unnecessary to scan the entire "reg" property, but I'll do |
|
661 - * so anyway. |
|
662 - */ |
|
663 - prop_len /= 20; |
|
664 - for (; prop_len--; prop_val += 20) |
|
665 - SetBitInMap(PCI_DFN_FROM_TAG(*(PCITAG *)prop_val), |
|
666 - pDomain->dfn_mask); |
|
667 - } |
|
668 - |
|
669 - /* Assume the host bridge is device 0, function 0 on its bus */ |
|
670 - SetBitInMap(0, pDomain->dfn_mask); |
|
671 - } |
|
672 - |
|
673 - sparcPromClose(); |
|
674 - |
|
675 - close(apertureFd); |
|
676 - apertureFd = -1; |
|
677 -} |
|
678 - |
|
679 -#ifndef INCLUDE_XF86_NO_DOMAIN |
|
680 - |
|
681 -_X_EXPORT int |
|
682 -xf86GetPciDomain(PCITAG Tag) |
|
683 -{ |
|
684 - return PCI_DOM_FROM_TAG(Tag); |
|
685 -} |
|
686 - |
|
687 -_X_EXPORT pointer |
|
688 -xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, |
|
689 - ADDRESS Base, unsigned long Size) |
|
690 -{ |
|
691 - sparcDomainPtr pDomain; |
|
692 - pointer result; |
|
693 - int domain = PCI_DOM_FROM_TAG(Tag); |
|
694 - |
|
695 - if ((domain <= 0) || (domain >= pciNumDomains) || |
|
696 - !(pDomain = xf86DomainInfo[domain]) || |
|
697 - (((unsigned long long)Base + (unsigned long long)Size) > |
|
698 - pDomain->mem_size)) |
|
699 - FatalError("xf86MapDomainMemory() called with invalid parameters.\n"); |
|
700 - |
|
701 - result = sparcMapAperture(ScreenNum, Flags, pDomain->mem_addr + Base, Size); |
|
702 - |
|
703 - if (apertureFd >= 0) { |
|
704 - close(apertureFd); |
|
705 - apertureFd = -1; |
|
706 - } |
|
707 - |
|
708 - return result; |
|
709 -} |
|
710 - |
|
711 -_X_EXPORT IOADDRESS |
|
712 -xf86MapLegacyIO(int ScreenNum, int Flags, PCITAG Tag, |
|
713 - IOADDRESS Base, unsigned long Size) |
|
714 -{ |
|
715 - sparcDomainPtr pDomain; |
|
716 - int domain = PCI_DOM_FROM_TAG(Tag); |
|
717 - |
|
718 - if ((domain <= 0) || (domain >= pciNumDomains) || |
|
719 - !(pDomain = xf86DomainInfo[domain]) || |
|
720 - (((unsigned long long)Base + (unsigned long long)Size) > |
|
721 - pDomain->io_size)) |
|
722 - FatalError("xf86MapLegacyIO() called with invalid parameters.\n"); |
|
723 - |
|
724 - /* Permanently map all of I/O space */ |
|
725 - if (!pDomain->io) { |
|
726 - pDomain->io = sparcMapAperture(ScreenNum, Flags, |
|
727 - pDomain->io_addr, pDomain->io_size); |
|
728 - |
|
729 - if (apertureFd >= 0) { |
|
730 - close(apertureFd); |
|
731 - apertureFd = -1; |
|
732 - } |
|
733 - } |
|
734 - |
|
735 - return (IOADDRESS)pDomain->io + Base; |
|
736 -} |
|
737 - |
|
738 -resPtr |
|
739 -xf86AccResFromOS(resPtr pRes) |
|
740 -{ |
|
741 - sparcDomainPtr pDomain; |
|
742 - resRange range; |
|
743 - int domain; |
|
744 - |
|
745 - for (domain = 1; domain < pciNumDomains; domain++) { |
|
746 - if (!(pDomain = xf86DomainInfo[domain])) |
|
747 - continue; |
|
748 - |
|
749 - /* |
|
750 - * At minimum, the top and bottom resources must be claimed, so that |
|
751 - * resources that are (or appear to be) unallocated can be relocated. |
|
752 - */ |
|
753 - RANGE(range, 0x00000000u, 0x0009ffffu, |
|
754 - RANGE_TYPE(ResExcMemBlock, domain)); |
|
755 - pRes = xf86AddResToList(pRes, &range, -1); |
|
756 - RANGE(range, 0x000c0000u, 0x000effffu, |
|
757 - RANGE_TYPE(ResExcMemBlock, domain)); |
|
758 - pRes = xf86AddResToList(pRes, &range, -1); |
|
759 - RANGE(range, 0x000f0000u, 0x000fffffu, |
|
760 - RANGE_TYPE(ResExcMemBlock, domain)); |
|
761 - pRes = xf86AddResToList(pRes, &range, -1); |
|
762 - |
|
763 - RANGE(range, pDomain->mem_size - 1, pDomain->mem_size - 1, |
|
764 - RANGE_TYPE(ResExcMemBlock, domain)); |
|
765 - pRes = xf86AddResToList(pRes, &range, -1); |
|
766 - |
|
767 - RANGE(range, 0x00000000u, 0x00000000u, |
|
768 - RANGE_TYPE(ResExcIoBlock, domain)); |
|
769 - pRes = xf86AddResToList(pRes, &range, -1); |
|
770 - RANGE(range, pDomain->io_size - 1, pDomain->io_size - 1, |
|
771 - RANGE_TYPE(ResExcIoBlock, domain)); |
|
772 - pRes = xf86AddResToList(pRes, &range, -1); |
|
773 - } |
|
774 - |
|
775 - return pRes; |
|
776 -} |
|
777 - |
|
778 -#endif /* !INCLUDE_XF86_NO_DOMAIN */ |
|
779 - |
|
780 -#endif /* defined(sun) */ |
|
781 - |
|
782 -#if defined(ARCH_PCI_PCI_BRIDGE) |
|
783 - |
|
784 -/* Definitions specific to Sun's APB P2P bridge (a.k.a. Simba) */ |
|
785 -#define APB_IO_ADDRESS_MAP 0xDE |
|
786 -#define APB_MEM_ADDRESS_MAP 0xDF |
|
787 - |
|
788 -/* |
|
789 - * Simba's can only occur on bus 0. Furthermore, Simba's must have a non-zero |
|
790 - * device/function number because the Sabre interface they must connect to |
|
791 - * occupies the 0:0:0 slot. Also, there can be only one Sabre interface in the |
|
792 - * system, and therefore, only one Simba function can route any particular |
|
793 - * resource. Thus, it is appropriate to use a single set of static variables |
|
794 - * to hold the tag of the Simba function routing a VGA resource range at any |
|
795 - * one time, and to test these variables for non-zero to determine whether or |
|
796 - * not the Sabre would master-abort a VGA access (and kill the system). |
|
797 - * |
|
798 - * The trick is to determine when it is safe to re-route VGA, because doing so |
|
799 - * re-routes much more. |
|
800 - */ |
|
801 -static PCITAG simbavgaIOTag = 0, simbavgaMemTag = 0; |
|
802 -static Bool simbavgaRoutingAllow = TRUE; |
|
803 - |
|
804 -/* |
|
805 - * Scan the bus subtree rooted at 'bus' for a non-display device that might be |
|
806 - * decoding the bottom 2 MB of I/O space and/or the bottom 512 MB of memory |
|
807 - * space. Reset simbavgaRoutingAllow if such a device is found. |
|
808 - * |
|
809 - * XXX For now, this is very conservative and should be made less so as the |
|
810 - * need arises. |
|
811 - */ |
|
812 -static void |
|
813 -simbaCheckBus(CARD16 pcicommand, int bus) |
|
814 -{ |
|
815 - pciConfigPtr pPCI, *ppPCI = xf86scanpci(0); |
|
816 - |
|
817 - while ((pPCI = *ppPCI++)) { |
|
818 - if (pPCI->busnum < bus) |
|
819 - continue; |
|
820 - if (pPCI->busnum > bus) |
|
821 - break; |
|
822 - |
|
823 - /* XXX Assume all devices respect PCI disablement */ |
|
824 - if (!(pcicommand & pPCI->pci_command)) |
|
825 - continue; |
|
826 - |
|
827 - /* XXX This doesn't deal with mis-advertised classes */ |
|
828 - switch (pPCI->pci_base_class) { |
|
829 - case PCI_CLASS_PREHISTORIC: |
|
830 - if (pPCI->pci_sub_class == PCI_SUBCLASS_PREHISTORIC_VGA) |
|
831 - continue; /* Ignore VGA */ |
|
832 - break; |
|
833 - |
|
834 - case PCI_CLASS_DISPLAY: |
|
835 - continue; |
|
836 - |
|
837 - case PCI_CLASS_BRIDGE: |
|
838 - switch (pPCI->pci_sub_class) { |
|
839 - case PCI_SUBCLASS_BRIDGE_PCI: |
|
840 - case PCI_SUBCLASS_BRIDGE_CARDBUS: |
|
841 - /* Scan secondary bus */ |
|
842 - /* XXX First check bridge routing? */ |
|
843 - simbaCheckBus(pcicommand & pPCI->pci_command, |
|
844 - PCI_SECONDARY_BUS_EXTRACT(pPCI->pci_pp_bus_register, |
|
845 - pPCI->tag)); |
|
846 - if (!simbavgaRoutingAllow) |
|
847 - return; |
|
848 - |
|
849 - default: |
|
850 - break; |
|
851 - } |
|
852 - |
|
853 - default: |
|
854 - break; |
|
855 - } |
|
856 - |
|
857 - /* |
|
858 - * XXX We could check the device's bases here, but PCI doesn't limit |
|
859 - * the device's decoding to them. |
|
860 - */ |
|
861 - |
|
862 - simbavgaRoutingAllow = FALSE; |
|
863 - break; |
|
864 - } |
|
865 -} |
|
866 - |
|
867 -static pciConfigPtr |
|
868 -simbaVerifyBus(int bus) |
|
869 -{ |
|
870 - pciConfigPtr pPCI; |
|
871 - if ((bus < 0) || (bus >= pciNumBuses) || |
|
872 - !pciBusInfo[bus] || !(pPCI = pciBusInfo[bus]->bridge) || |
|
873 - (pPCI->pci_device_vendor != DEVID(VENDOR_SUN, CHIP_SIMBA))) |
|
874 - return NULL; |
|
875 - |
|
876 - return pPCI; |
|
877 -} |
|
878 - |
|
879 -static CARD16 |
|
880 -simbaControlBridge(int bus, CARD16 mask, CARD16 value) |
|
881 -{ |
|
882 - pciConfigPtr pPCI; |
|
883 - CARD16 current = 0, tmp; |
|
884 - CARD8 iomap, memmap; |
|
885 - |
|
886 - if ((pPCI = simbaVerifyBus(bus))) { |
|
887 - /* |
|
888 - * The Simba does not implement VGA enablement as described in the P2P |
|
889 - * spec. It does however route I/O and memory in large enough chunks |
|
890 - * so that we can determine were VGA resources would be routed |
|
891 - * (including ISA VGA I/O aliases). We can allow changes to that |
|
892 - * routing only under certain circumstances. |
|
893 - */ |
|
894 - iomap = pciReadByte(pPCI->tag, APB_IO_ADDRESS_MAP); |
|
895 - memmap = pciReadByte(pPCI->tag, APB_MEM_ADDRESS_MAP); |
|
896 - if (iomap & memmap & 0x01) { |
|
897 - current |= PCI_PCI_BRIDGE_VGA_EN; |
|
898 - if ((mask & PCI_PCI_BRIDGE_VGA_EN) && |
|
899 - !(value & PCI_PCI_BRIDGE_VGA_EN)) { |
|
900 - if (!simbavgaRoutingAllow) { |
|
901 - xf86MsgVerb(X_WARNING, 3, "Attempt to disable VGA routing" |
|
902 - " through Simba at %x:%x:%x disallowed.\n", |
|
903 - pPCI->busnum, pPCI->devnum, pPCI->funcnum); |
|
904 - value |= PCI_PCI_BRIDGE_VGA_EN; |
|
905 - } else { |
|
906 - pciWriteByte(pPCI->tag, APB_IO_ADDRESS_MAP, |
|
907 - iomap & ~0x01); |
|
908 - pciWriteByte(pPCI->tag, APB_MEM_ADDRESS_MAP, |
|
909 - memmap & ~0x01); |
|
910 - simbavgaIOTag = simbavgaMemTag = 0; |
|
911 - } |
|
912 - } |
|
913 - } else { |
|
914 - if (mask & value & PCI_PCI_BRIDGE_VGA_EN) { |
|
915 - if (!simbavgaRoutingAllow) { |
|
916 - xf86MsgVerb(X_WARNING, 3, "Attempt to enable VGA routing" |
|
917 - " through Simba at %x:%x:%x disallowed.\n", |
|
918 - pPCI->busnum, pPCI->devnum, pPCI->funcnum); |
|
919 - value &= ~PCI_PCI_BRIDGE_VGA_EN; |
|
920 - } else { |
|
921 - if (pPCI->tag != simbavgaIOTag) { |
|
922 - if (simbavgaIOTag) { |
|
923 - tmp = pciReadByte(simbavgaIOTag, |
|
924 - APB_IO_ADDRESS_MAP); |
|
925 - pciWriteByte(simbavgaIOTag, APB_IO_ADDRESS_MAP, |
|
926 - tmp & ~0x01); |
|
927 - } |
|
928 - |
|
929 - pciWriteByte(pPCI->tag, APB_IO_ADDRESS_MAP, |
|
930 - iomap | 0x01); |
|
931 - simbavgaIOTag = pPCI->tag; |
|
932 - } |
|
933 - |
|
934 - if (pPCI->tag != simbavgaMemTag) { |
|
935 - if (simbavgaMemTag) { |
|
936 - tmp = pciReadByte(simbavgaMemTag, |
|
937 - APB_MEM_ADDRESS_MAP); |
|
938 - pciWriteByte(simbavgaMemTag, APB_MEM_ADDRESS_MAP, |
|
939 - tmp & ~0x01); |
|
940 - } |
|
941 - |
|
942 - pciWriteByte(pPCI->tag, APB_MEM_ADDRESS_MAP, |
|
943 - memmap | 0x01); |
|
944 - simbavgaMemTag = pPCI->tag; |
|
945 - } |
|
946 - } |
|
947 - } |
|
948 - } |
|
949 - |
|
950 - /* Move on to master abort failure enablement (as per P2P spec) */ |
|
951 - tmp = pciReadWord(pPCI->tag, PCI_PCI_BRIDGE_CONTROL_REG); |
|
952 - current |= tmp; |
|
953 - if (tmp & PCI_PCI_BRIDGE_MASTER_ABORT_EN) { |
|
954 - if ((mask & PCI_PCI_BRIDGE_MASTER_ABORT_EN) && |
|
955 - !(value & PCI_PCI_BRIDGE_MASTER_ABORT_EN)) |
|
956 - pciWriteWord(pPCI->tag, PCI_PCI_BRIDGE_CONTROL_REG, |
|
957 - tmp & ~PCI_PCI_BRIDGE_MASTER_ABORT_EN); |
|
958 - } else { |
|
959 - if (mask & value & PCI_PCI_BRIDGE_MASTER_ABORT_EN) |
|
960 - pciWriteWord(pPCI->tag, PCI_PCI_BRIDGE_CONTROL_REG, |
|
961 - tmp | PCI_PCI_BRIDGE_MASTER_ABORT_EN); |
|
962 - } |
|
963 - |
|
964 - /* Insert emulation of other P2P controls here */ |
|
965 - } |
|
966 - |
|
967 - return (current & ~mask) | (value & mask); |
|
968 -} |
|
969 - |
|
970 -static void |
|
971 -simbaGetBridgeResources(int bus, |
|
972 - pointer *ppIoRes, |
|
973 - pointer *ppMemRes, |
|
974 - pointer *ppPmemRes) |
|
975 -{ |
|
976 - pciConfigPtr pPCI = simbaVerifyBus(bus); |
|
977 - resRange range; |
|
978 - int i; |
|
979 - |
|
980 - if (!pPCI) |
|
981 - return; |
|
982 - |
|
983 - if (ppIoRes) { |
|
984 - xf86FreeResList(*ppIoRes); |
|
985 - *ppIoRes = NULL; |
|
986 - |
|
987 - if (pPCI->pci_command & PCI_CMD_IO_ENABLE) { |
|
988 - unsigned char iomap = pciReadByte(pPCI->tag, APB_IO_ADDRESS_MAP); |
|
989 - if (simbavgaRoutingAllow) |
|
990 - iomap |= 0x01; |
|
991 - for (i = 0; i < 8; i++) { |
|
992 - if (iomap & (1 << i)) { |
|
993 - RANGE(range, i << 21, ((i + 1) << 21) - 1, |
|
994 - RANGE_TYPE(ResExcIoBlock, |
|
995 - xf86GetPciDomain(pPCI->tag))); |
|
996 - *ppIoRes = xf86AddResToList(*ppIoRes, &range, -1); |
|
997 - } |
|
998 - } |
|
999 - } |
|
1000 - } |
|
1001 - |
|
1002 - if (ppMemRes) { |
|
1003 - xf86FreeResList(*ppMemRes); |
|
1004 - *ppMemRes = NULL; |
|
1005 - |
|
1006 - if (pPCI->pci_command & PCI_CMD_MEM_ENABLE) { |
|
1007 - unsigned char memmap = pciReadByte(pPCI->tag, APB_MEM_ADDRESS_MAP); |
|
1008 - if (simbavgaRoutingAllow) |
|
1009 - memmap |= 0x01; |
|
1010 - for (i = 0; i < 8; i++) { |
|
1011 - if (memmap & (1 << i)) { |
|
1012 - RANGE(range, i << 29, ((i + 1) << 29) - 1, |
|
1013 - RANGE_TYPE(ResExcMemBlock, |
|
1014 - xf86GetPciDomain(pPCI->tag))); |
|
1015 - *ppMemRes = xf86AddResToList(*ppMemRes, &range, -1); |
|
1016 - } |
|
1017 - } |
|
1018 - } |
|
1019 - } |
|
1020 - |
|
1021 - if (ppPmemRes) { |
|
1022 - xf86FreeResList(*ppPmemRes); |
|
1023 - *ppPmemRes = NULL; |
|
1024 - } |
|
1025 -} |
|
1026 - |
|
1027 -void ARCH_PCI_PCI_BRIDGE(pciConfigPtr pPCI) |
|
1028 -{ |
|
1029 - static pciBusFuncs_t simbaBusFuncs; |
|
1030 - pciBusInfo_t *pBusInfo; |
|
1031 - CARD16 pcicommand; |
|
1032 - |
|
1033 - if (pPCI->pci_device_vendor != DEVID(VENDOR_SUN, CHIP_SIMBA)) |
|
1034 - return; |
|
1035 - |
|
1036 - pBusInfo = pPCI->businfo; |
|
1037 - |
|
1038 - simbaBusFuncs = *(pBusInfo->funcs); |
|
1039 - simbaBusFuncs.pciControlBridge = simbaControlBridge; |
|
1040 - simbaBusFuncs.pciGetBridgeResources = simbaGetBridgeResources; |
|
1041 - |
|
1042 - pBusInfo->funcs = &simbaBusFuncs; |
|
1043 - |
|
1044 - if (!simbavgaRoutingAllow) |
|
1045 - return; |
|
1046 - |
|
1047 - pcicommand = 0; |
|
1048 - |
|
1049 - if (pciReadByte(pPCI->tag, APB_IO_ADDRESS_MAP) & 0x01) { |
|
1050 - pcicommand |= PCI_CMD_IO_ENABLE; |
|
1051 - simbavgaIOTag = pPCI->tag; |
|
1052 - } |
|
1053 - |
|
1054 - if (pciReadByte(pPCI->tag, APB_MEM_ADDRESS_MAP) & 0x01) { |
|
1055 - pcicommand |= PCI_CMD_MEM_ENABLE; |
|
1056 - simbavgaMemTag = pPCI->tag; |
|
1057 - } |
|
1058 - |
|
1059 - if (!pcicommand) |
|
1060 - return; |
|
1061 - |
|
1062 - simbaCheckBus(pcicommand, |
|
1063 - PCI_SECONDARY_BUS_EXTRACT(pPCI->pci_pp_bus_register, pPCI->tag)); |
|
1064 -} |
|
1065 - |
|
1066 -#endif /* defined(ARCH_PCI_PCI_BRIDGE) */ |
|
1067 -- |
|
1068 1.4.1 |
|
1069 |
|