open-src/driver/xf86-video-intel/Render-register-clock-gating-disable-fix-on-4-series.patch
author Alan Coopersmith <Alan.Coopersmith@Sun.COM>
Thu, 15 Jan 2009 12:55:00 -0800
changeset 606 068c11b419c9
permissions -rw-r--r--
6582489 X11R7.4: Xorg server 1.5.3, Mesa 7.2, and associated driver updates Includes changes contributed by Liang, Kan <[email protected]>: - G41 support patches - DRM_CAS in libdrm type error can cause deadlock and hang the glxgears. Includes changes contributed by Martin Bochnig <[email protected]>: - Make SUNWxorg-mesa package platform-clean

From 1cc15ba454fdf54a7dea9da066e0a023a4742fab Mon Sep 17 00:00:00 2001
From: Zhenyu Wang <[email protected]>
Date: Fri, 26 Sep 2008 10:01:52 +0800
Subject: [PATCH] Render register clock gating disable fix on 4 series chipset

---
 src/i810_reg.h    |    3 +++
 src/i830_driver.c |   14 ++++++++++----
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/i810_reg.h b/src/i810_reg.h
index 5b90e12..6458008 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -1167,6 +1167,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
 
 #define RENCLK_GATE_D2		0x6208
+#define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
+#define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
+#define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
 #define RAMCLK_GATE_D		0x6210		/* CRL only */
 #define DEUC			0x6214          /* CRL only */
 
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 1317c1d..389775f 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -965,12 +965,18 @@ i830_init_clock_gating(ScrnInfoPtr pScrn)
     /* Disable clock gating reported to work incorrectly according to the specs.
      */
     if (IS_GM45(pI830) || IS_G4X(pI830)) {
+	uint32_t dspclk_gate;
 	OUTREG(RENCLK_GATE_D1, 0);
-	OUTREG(RENCLK_GATE_D2, 0);
+	OUTREG(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
+		GS_UNIT_CLOCK_GATE_DISABLE |
+		CL_UNIT_CLOCK_GATE_DISABLE);
 	OUTREG(RAMCLK_GATE_D, 0);
-	OUTREG(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE |
-	       OVRUNIT_CLOCK_GATE_DISABLE |
-	       OVCUNIT_CLOCK_GATE_DISABLE);
+	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
+	    OVRUNIT_CLOCK_GATE_DISABLE |
+	    OVCUNIT_CLOCK_GATE_DISABLE;
+	if (IS_GM45(pI830))
+	    dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
+	OUTREG(DSPCLK_GATE_D, dspclk_gate);
     } else if (IS_I965GM(pI830)) {
 	OUTREG(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
 	OUTREG(RENCLK_GATE_D2, 0);
-- 
1.5.6.5