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1 From 1cc15ba454fdf54a7dea9da066e0a023a4742fab Mon Sep 17 00:00:00 2001 |
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2 From: Zhenyu Wang <[email protected]> |
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3 Date: Fri, 26 Sep 2008 10:01:52 +0800 |
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4 Subject: [PATCH] Render register clock gating disable fix on 4 series chipset |
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5 |
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6 --- |
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7 src/i810_reg.h | 3 +++ |
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8 src/i830_driver.c | 14 ++++++++++---- |
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9 2 files changed, 13 insertions(+), 4 deletions(-) |
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10 |
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11 diff --git a/src/i810_reg.h b/src/i810_reg.h |
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12 index 5b90e12..6458008 100644 |
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13 --- a/src/i810_reg.h |
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14 +++ b/src/i810_reg.h |
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15 @@ -1167,6 +1167,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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16 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) |
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17 |
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18 #define RENCLK_GATE_D2 0x6208 |
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19 +#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
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20 +#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
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21 +#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
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22 #define RAMCLK_GATE_D 0x6210 /* CRL only */ |
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23 #define DEUC 0x6214 /* CRL only */ |
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24 |
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25 diff --git a/src/i830_driver.c b/src/i830_driver.c |
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26 index 1317c1d..389775f 100644 |
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27 --- a/src/i830_driver.c |
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28 +++ b/src/i830_driver.c |
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29 @@ -965,12 +965,18 @@ i830_init_clock_gating(ScrnInfoPtr pScrn) |
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30 /* Disable clock gating reported to work incorrectly according to the specs. |
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31 */ |
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32 if (IS_GM45(pI830) || IS_G4X(pI830)) { |
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33 + uint32_t dspclk_gate; |
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34 OUTREG(RENCLK_GATE_D1, 0); |
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35 - OUTREG(RENCLK_GATE_D2, 0); |
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36 + OUTREG(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
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37 + GS_UNIT_CLOCK_GATE_DISABLE | |
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38 + CL_UNIT_CLOCK_GATE_DISABLE); |
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39 OUTREG(RAMCLK_GATE_D, 0); |
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40 - OUTREG(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE | |
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41 - OVRUNIT_CLOCK_GATE_DISABLE | |
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42 - OVCUNIT_CLOCK_GATE_DISABLE); |
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43 + dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
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44 + OVRUNIT_CLOCK_GATE_DISABLE | |
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45 + OVCUNIT_CLOCK_GATE_DISABLE; |
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46 + if (IS_GM45(pI830)) |
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47 + dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
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48 + OUTREG(DSPCLK_GATE_D, dspclk_gate); |
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49 } else if (IS_I965GM(pI830)) { |
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50 OUTREG(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
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51 OUTREG(RENCLK_GATE_D2, 0); |
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52 -- |
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53 1.5.6.5 |
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54 |