20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 * DEALINGS IN THE SOFTWARE. |
21 * DEALINGS IN THE SOFTWARE. |
22 */ |
22 */ |
23 |
23 |
24 #ifndef AST_H |
24 #ifndef AST_H |
25 #define AST_H |
25 #define AST_H |
26 |
26 |
27 #include <sys/types.h> |
27 #define AST_REG_SIZE_LOG2 18 |
28 #include <stdio.h> |
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29 #include <sys/mman.h> |
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30 |
28 |
31 #include "gfx_common.h" /* GFX Common definitions */ |
29 #define PCI_MAP_MEMORY 0x00000000 |
32 #include "graphicstest.h" |
30 #define PCI_MAP_IO 0x00000001 |
33 #include "libvtsSUNWast.h" /* Common VTS library definitions */ |
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34 |
31 |
35 #include "X11/Xlib.h" |
32 #define PCI_MAP_MEMORY_TYPE 0x00000007 |
36 #include "gfx_vts.h" /* VTS Graphics Test common routines */ |
33 #define PCI_MAP_IO_TYPE 0x00000003 |
37 |
34 |
38 #define AST_REG_SIZE_LOG2 18 |
35 #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 |
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36 #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
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37 #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
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38 #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
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39 #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
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40 #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
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41 #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
39 |
42 |
40 struct pci_info { |
43 #define PCI_MAP_IO_ATTR_MASK 0x00000003 |
41 unsigned long memBase[6]; |
44 #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
42 unsigned long ioBase[6]; |
45 #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
43 unsigned int type [6]; |
46 |
44 unsigned int size [6]; |
47 #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
45 }; |
48 |
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49 #define PCI_MAP_IS64BITMEM(b) \ |
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50 (((b) & PCI_MAP_MEMORY_TYPE) == PCI_MAP_MEMORY_TYPE_64BIT) |
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51 |
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52 #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
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53 |
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54 #define PCI_REGION_BASE(_pcidev, _b, _type) \ |
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55 (((_type) == REGION_MEM) ? (_pcidev)->memBase[(_b)] : \ |
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56 (_pcidev)->ioBase[(_b)]) |
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57 |
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58 #define AR_PORT_WRITE 0x40 |
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59 #define MISC_PORT_WRITE 0x42 |
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60 #define SEQ_PORT 0x44 |
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61 #define DAC_INDEX_READ 0x47 |
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62 #define DAC_INDEX_WRITE 0x48 |
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63 #define DAC_DATA 0x49 |
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64 #define GR_PORT 0x4E |
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65 #define CRTC_PORT 0x54 |
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66 #define INPUT_STATUS1_READ 0x5A |
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67 #define MISC_PORT_READ 0x4C |
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68 |
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69 #define AST_MMIO_SIZE 0x00020000 |
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70 #define AST_VRAM_SIZE_08M 0x00800000 |
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71 #define AST_VRAM_SIZE_16M 0x01000000 |
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72 #define AST_VRAM_SIZE_32M 0x02000000 |
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73 #define AST_VRAM_SIZE_64M 0x04000000 |
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74 #define AST_VRAM_SIZE_128M 0x08000000 |
46 |
75 |
47 |
76 |
48 #define PKT_NULL_CMD 0x00009561 |
77 #define MASK_SRC_PITCH 0x1FFF |
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78 #define MASK_DST_PITCH 0x1FFF |
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79 #define MASK_DST_HEIGHT 0x7FF |
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80 #define MASK_SRC_X 0xFFF |
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81 #define MASK_SRC_Y 0xFFF |
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82 #define MASK_DST_X 0xFFF |
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83 #define MASK_DST_Y 0xFFF |
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84 #define MASK_RECT_WIDTH 0x7FF |
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85 #define MASK_RECT_HEIGHT 0x7FF |
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86 #define MASK_CLIP 0xFFF |
49 |
87 |
50 #define PKT_SINGLE_LENGTH 8 |
88 #define MASK_LINE_X 0xFFF |
51 #define PKT_SINGLE_CMD_HEADER 0x00009562 |
89 #define MASK_LINE_Y 0xFFF |
52 |
90 #define MASK_LINE_ERR 0x3FFFFF |
53 typedef struct _PKT_SC |
91 #define MASK_LINE_WIDTH 0x7FF |
54 { |
92 #define MASK_LINE_K1 0x3FFFFF |
55 unsigned int header; |
93 #define MASK_LINE_K2 0x3FFFFF |
56 unsigned int data[1]; |
94 #define MASK_AIPLINE_X 0xFFF |
57 } PKT_SC, *PPKT_SC; |
95 #define MASK_AIPLINE_Y 0xFFF |
58 |
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59 |
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60 #define CMD_QUEUE_GUARD_BAND 0x20 |
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61 |
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62 typedef struct { |
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63 |
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64 unsigned long ulCMDQSize; |
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65 unsigned long ulCMDQType; |
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66 |
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67 unsigned long ulCMDQOffset; |
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68 unsigned char *pjCMDQvaddr; |
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69 |
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70 unsigned char *pjCmdQBasePort; |
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71 unsigned char *pjWritePort; |
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72 unsigned char *pjReadPort; |
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73 unsigned char *pjEngStatePort; |
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74 |
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75 unsigned long ulCMDQMask; |
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76 unsigned long ulCMDQueueLen; |
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77 |
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78 unsigned long ulWritePointer; |
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79 unsigned long ulReadPointer; |
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80 unsigned long ulReadPointer_OK; /* for Eng_DBGChk */ |
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81 |
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82 } CMDQINFO, *PCMDQINFO; |
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83 |
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84 |
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85 typedef unsigned int (*PFNRead32) (unsigned char *); |
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86 typedef void (*PFNWrite32) (unsigned char *, unsigned int); |
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87 |
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88 struct ast_info { |
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89 int fd; |
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90 |
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91 int screenWidth; |
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92 int screenHeight; |
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93 int screenPitch; |
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94 int bytesPerPixel; |
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95 |
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96 int MMIO2D; |
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97 |
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98 unsigned long FBPhysAddr; |
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99 unsigned long MMIOPhysAddr; |
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100 unsigned long RelocateIO; |
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101 |
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102 int FBMapSize; |
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103 int MMIOMapSize; |
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104 |
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105 unsigned char *FBvaddr; |
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106 unsigned char *MMIOvaddr; |
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107 |
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108 CMDQINFO CMDQInfo; |
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109 unsigned long cmdreg; |
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110 |
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111 unsigned int save_dst_base; |
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112 unsigned int save_line_xy; |
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113 unsigned int save_line_err; |
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114 unsigned int save_line_width; |
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115 unsigned int save_line_k1; |
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116 unsigned int save_line_k2; |
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117 unsigned int save_mono_pat1; |
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118 unsigned int save_mono_pat2; |
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119 |
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120 PFNRead32 read32; |
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121 PFNWrite32 write32; |
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122 }; |
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123 |
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124 #define PCI_MAP_MEMORY 0x00000000 |
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125 #define PCI_MAP_IO 0x00000001 |
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126 |
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127 #define PCI_MAP_MEMORY_TYPE 0x00000007 |
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128 #define PCI_MAP_IO_TYPE 0x00000003 |
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129 |
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130 #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 |
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131 #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
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132 #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
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133 #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
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134 #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
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135 #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
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136 #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
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137 |
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138 #define PCI_MAP_IO_ATTR_MASK 0x00000003 |
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139 #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
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140 #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
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141 |
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142 #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
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143 |
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144 #define PCI_MAP_IS64BITMEM(b) \ |
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145 (((b) & PCI_MAP_MEMORY_TYPE) == PCI_MAP_MEMORY_TYPE_64BIT) |
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146 |
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147 #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
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148 |
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149 #define PCI_REGION_BASE(_pcidev, _b, _type) \ |
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150 (((_type) == REGION_MEM) ? (_pcidev)->memBase[(_b)] \ |
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151 : (_pcidev)->ioBase[(_b)]) |
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152 |
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153 #define AR_PORT_WRITE 0x40 |
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154 #define MISC_PORT_WRITE 0x42 |
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155 #define SEQ_PORT 0x44 |
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156 #define DAC_INDEX_READ 0x47 |
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157 #define DAC_INDEX_WRITE 0x48 |
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158 #define DAC_DATA 0x49 |
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159 #define GR_PORT 0x4E |
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160 #define CRTC_PORT 0x54 |
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161 #define INPUT_STATUS1_READ 0x5A |
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162 #define MISC_PORT_READ 0x4C |
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163 |
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164 #define AST_MMIO_SIZE 0x00020000 |
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165 #define AST_VRAM_SIZE_08M 0x00800000 |
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166 #define AST_VRAM_SIZE_16M 0x01000000 |
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167 #define AST_VRAM_SIZE_32M 0x02000000 |
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168 #define AST_VRAM_SIZE_64M 0x04000000 |
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169 #define AST_VRAM_SIZE_128M 0x08000000 |
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170 |
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171 |
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172 #define MASK_SRC_PITCH 0x1FFF |
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173 #define MASK_DST_PITCH 0x1FFF |
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174 #define MASK_DST_HEIGHT 0x7FF |
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175 #define MASK_SRC_X 0xFFF |
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176 #define MASK_SRC_Y 0xFFF |
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177 #define MASK_DST_X 0xFFF |
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178 #define MASK_DST_Y 0xFFF |
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179 #define MASK_RECT_WIDTH 0x7FF |
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180 #define MASK_RECT_HEIGHT 0x7FF |
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181 #define MASK_CLIP 0xFFF |
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182 |
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183 #define MASK_LINE_X 0xFFF |
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184 #define MASK_LINE_Y 0xFFF |
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185 #define MASK_LINE_ERR 0x3FFFFF |
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186 #define MASK_LINE_WIDTH 0x7FF |
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187 #define MASK_LINE_K1 0x3FFFFF |
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188 #define MASK_LINE_K2 0x3FFFFF |
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189 #define MASK_AIPLINE_X 0xFFF |
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190 #define MASK_AIPLINE_Y 0xFFF |
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191 |
96 |
192 |
97 |
193 /* CMDQ Reg */ |
98 /* CMDQ Reg */ |
194 #define CMDQREG_SRC_BASE (0x00 << 24) |
99 #define CMDQREG_SRC_BASE (0x00 << 24) |
195 #define CMDQREG_SRC_PITCH (0x01 << 24) |
100 #define CMDQREG_SRC_PITCH (0x01 << 24) |
196 #define CMDQREG_DST_BASE (0x02 << 24) |
101 #define CMDQREG_DST_BASE (0x02 << 24) |
197 #define CMDQREG_DST_PITCH (0x03 << 24) |
102 #define CMDQREG_DST_PITCH (0x03 << 24) |
198 #define CMDQREG_DST_XY (0x04 << 24) |
103 #define CMDQREG_DST_XY (0x04 << 24) |
199 #define CMDQREG_SRC_XY (0x05 << 24) |
104 #define CMDQREG_SRC_XY (0x05 << 24) |
200 #define CMDQREG_RECT_XY (0x06 << 24) |
105 #define CMDQREG_RECT_XY (0x06 << 24) |
201 #define CMDQREG_FG (0x07 << 24) |
106 #define CMDQREG_FG (0x07 << 24) |
202 #define CMDQREG_BG (0x08 << 24) |
107 #define CMDQREG_BG (0x08 << 24) |
203 #define CMDQREG_FG_SRC (0x09 << 24) |
108 #define CMDQREG_FG_SRC (0x09 << 24) |
204 #define CMDQREG_BG_SRC (0x0A << 24) |
109 #define CMDQREG_BG_SRC (0x0A << 24) |
205 #define CMDQREG_MONO1 (0x0B << 24) |
110 #define CMDQREG_MONO1 (0x0B << 24) |
206 #define CMDQREG_MONO2 (0x0C << 24) |
111 #define CMDQREG_MONO2 (0x0C << 24) |
207 #define CMDQREG_CLIP1 (0x0D << 24) |
112 #define CMDQREG_CLIP1 (0x0D << 24) |
208 #define CMDQREG_CLIP2 (0x0E << 24) |
113 #define CMDQREG_CLIP2 (0x0E << 24) |
209 #define CMDQREG_CMD (0x0F << 24) |
114 #define CMDQREG_CMD (0x0F << 24) |
210 #define CMDQREG_PAT (0x40 << 24) |
115 #define CMDQREG_PAT (0x40 << 24) |
211 |
116 |
212 #define CMDQREG_LINE_XY (0x04 << 24) |
117 #define CMDQREG_LINE_XY (0x04 << 24) |
213 #define CMDQREG_LINE_Err (0x05 << 24) |
118 #define CMDQREG_LINE_ERR (0x05 << 24) |
214 #define CMDQREG_LINE_WIDTH (0x06 << 24) |
119 #define CMDQREG_LINE_WIDTH (0x06 << 24) |
215 #define CMDQREG_LINE_K1 (0x09 << 24) |
120 #define CMDQREG_LINE_K1 (0x09 << 24) |
216 #define CMDQREG_LINE_K2 (0x0A << 24) |
121 #define CMDQREG_LINE_K2 (0x0A << 24) |
217 #define CMDQREG_LINE_STYLE1 (0x0B << 24) |
122 #define CMDQREG_LINE_STYLE1 (0x0B << 24) |
218 #define CMDQREG_LINE_STYLE2 (0x0C << 24) |
123 #define CMDQREG_LINE_STYLE2 (0x0C << 24) |
219 #define CMDQREG_LINE_XY2 (0x05 << 24) |
124 #define CMDQREG_LINE_XY2 (0x05 << 24) |
220 #define CMDQREG_LINE_NUMBER (0x06 << 24) |
125 #define CMDQREG_LINE_NUMBER (0x06 << 24) |
221 |
126 |
222 #define CMD_BITBLT 0x00000000 |
127 #define CMD_BITBLT 0x00000000 |
223 #define CMD_LINEDRAW 0x00000001 |
128 #define CMD_LINEDRAW 0x00000001 |
224 #define CMD_COLOREXP 0x00000002 |
129 #define CMD_COLOREXP 0x00000002 |
225 #define CMD_ENHCOLOREXP 0x00000003 |
130 #define CMD_ENHCOLOREXP 0x00000003 |
226 #define CMD_TRANSPARENTBLT 0x00000004 |
131 #define CMD_TRANSPARENTBLT 0x00000004 |
227 #define CMD_MASK 0x00000007 |
132 #define CMD_MASK 0x00000007 |
228 |
133 |
229 #define CMD_DISABLE_CLIP 0x00000000 |
134 #define CMD_DISABLE_CLIP 0x00000000 |
230 #define CMD_ENABLE_CLIP 0x00000008 |
135 #define CMD_ENABLE_CLIP 0x00000008 |
231 |
136 |
232 #define CMD_COLOR_08 0x00000000 |
137 #define CMD_COLOR_08 0x00000000 |
233 #define CMD_COLOR_16 0x00000010 |
138 #define CMD_COLOR_16 0x00000010 |
234 #define CMD_COLOR_32 0x00000020 |
139 #define CMD_COLOR_32 0x00000020 |
235 |
140 |
236 #define CMD_SRC_SIQ 0x00000040 |
141 #define CMD_SRC_SIQ 0x00000040 |
237 |
142 |
238 #define CMD_TRANSPARENT 0x00000080 |
143 #define CMD_TRANSPARENT 0x00000080 |
239 |
144 |
240 #define CMD_PAT_FGCOLOR 0x00000000 |
145 #define CMD_PAT_FGCOLOR 0x00000000 |
241 #define CMD_PAT_MONOMASK 0x00010000 |
146 #define CMD_PAT_MONOMASK 0x00010000 |
242 #define CMD_PAT_PATREG 0x00020000 |
147 #define CMD_PAT_PATREG 0x00020000 |
243 |
148 |
244 #define CMD_OPAQUE 0x00000000 |
149 #define CMD_OPAQUE 0x00000000 |
245 #define CMD_FONT_TRANSPARENT 0x00040000 |
150 #define CMD_FONT_TRANSPARENT 0x00040000 |
246 |
151 |
247 #define CMD_X_INC 0x00000000 |
152 #define CMD_X_INC 0x00000000 |
248 #define CMD_X_DEC 0x00200000 |
153 #define CMD_X_DEC 0x00200000 |
249 |
154 |
250 #define CMD_Y_INC 0x00000000 |
155 #define CMD_Y_INC 0x00000000 |
251 #define CMD_Y_DEC 0x00100000 |
156 #define CMD_Y_DEC 0x00100000 |
252 |
157 |
253 #define CMD_NT_LINE 0x00000000 |
158 #define CMD_NT_LINE 0x00000000 |
254 #define CMD_NORMAL_LINE 0x00400000 |
159 #define CMD_NORMAL_LINE 0x00400000 |
255 |
160 |
256 #define CMD_DRAW_LAST_PIXEL 0x00000000 |
161 #define CMD_DRAW_LAST_PIXEL 0x00000000 |
257 #define CMD_NOT_DRAW_LAST_PIXEL 0x00800000 |
162 #define CMD_NOT_DRAW_LAST_PIXEL 0x00800000 |
258 |
163 |
259 #define CMD_DISABLE_LINE_STYLE 0x00000000 |
164 #define CMD_DISABLE_LINE_STYLE 0x00000000 |
260 #define CMD_ENABLE_LINE_STYLE 0x40000000 |
165 #define CMD_ENABLE_LINE_STYLE 0x40000000 |
261 |
166 |
262 #define CMD_RESET_STYLE_COUNTER 0x80000000 |
167 #define CMD_RESET_STYLE_COUNTER 0x80000000 |
263 #define CMD_NOT_RESET_STYLE_COUNTER 0x00000000 |
168 #define CMD_NOT_RESET_STYLE_COUNTER 0x00000000 |
264 |
169 |
265 #define BURST_FORCE_CMD 0x80000000 |
170 #define QUEUE_MEMORY_MAP 0x02000000 |
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171 #define STAT_BUSY 0x80000000 |
266 |
172 |
267 #define MMIOREG_DST_BASE (pAST->MMIOvaddr + 0x8008) |
173 #define BURST_FORCE_CMD 0x80000000 |
268 #define MMIOREG_DST_PITCH (pAST->MMIOvaddr + 0x800C) |
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269 #define MMIOREG_DST_XY (pAST->MMIOvaddr + 0x8010) |
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270 #define MMIOREG_SRC_XY (pAST->MMIOvaddr + 0x8014) |
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271 #define MMIOREG_RECT_XY (pAST->MMIOvaddr + 0x8018) |
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272 #define MMIOREG_FG (pAST->MMIOvaddr + 0x801C) |
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273 #define MMIOREG_BG (pAST->MMIOvaddr + 0x8020) |
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274 #define MMIOREG_MONO1 (pAST->MMIOvaddr + 0x802C) |
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275 #define MMIOREG_MONO2 (pAST->MMIOvaddr + 0x8030) |
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276 #define MMIOREG_CLIP1 (pAST->MMIOvaddr + 0x8034) |
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277 #define MMIOREG_CLIP2 (pAST->MMIOvaddr + 0x8038) |
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278 #define MMIOREG_CMD (pAST->MMIOvaddr + 0x803C) |
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279 #define MMIOREG_PAT (pAST->MMIOvaddr + 0x8100) |
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280 |
174 |
281 #define MMIOREG_LINE_XY (pAST->MMIOvaddr + 0x8010) |
175 #define MMIOREG_DST_BASE 0x8008 |
282 #define MMIOREG_LINE_Err (pAST->MMIOvaddr + 0x8014) |
176 #define MMIOREG_DST_PITCH 0x800C |
283 #define MMIOREG_LINE_WIDTH (pAST->MMIOvaddr + 0x8018) |
177 #define MMIOREG_DST_XY 0x8010 |
284 #define MMIOREG_LINE_K1 (pAST->MMIOvaddr + 0x8024) |
178 #define MMIOREG_SRC_XY 0x8014 |
285 #define MMIOREG_LINE_K2 (pAST->MMIOvaddr + 0x8028) |
179 #define MMIOREG_RECT_XY 0x8018 |
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180 #define MMIOREG_FG 0x801C |
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181 #define MMIOREG_BG 0x8020 |
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182 #define MMIOREG_MONO1 0x802C |
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183 #define MMIOREG_MONO2 0x8030 |
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184 #define MMIOREG_CLIP1 0x8034 |
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185 #define MMIOREG_CLIP2 0x8038 |
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186 #define MMIOREG_CMD 0x803C |
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187 #define MMIOREG_QUEUE 0x8044 |
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188 #define MMIOREG_STAT 0x804C |
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189 #define MMIOREG_PAT 0x8100 |
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190 |
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191 #define MMIOREG_LINE_XY 0x8010 |
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192 #define MMIOREG_LINE_ERR 0x8014 |
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193 #define MMIOREG_LINE_WIDTH 0x8018 |
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194 #define MMIOREG_LINE_K1 0x8024 |
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195 #define MMIOREG_LINE_K2 0x8028 |
286 |
196 |
287 |
197 |
288 int ast_get_pci_info(int fd, struct pci_info *pci_info); |
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289 int ast_get_mem_info(struct pci_info *pci_info, struct ast_info *pAST); |
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290 int ast_map_mem(struct ast_info *pAST, return_packet *rp, int test); |
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291 int ast_unmap_mem(struct ast_info *pAST, return_packet *rp, int test); |
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292 |
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293 void ASTSetReg(int fd, int offset, int value); |
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294 void ASTGetReg(int fd, int offset, int *value); |
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295 void ASTSetIndexReg(int fd, int offset, int index, unsigned char value); |
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296 void ASTGetIndexReg(int fd, int offset, int index, unsigned char *value); |
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297 void ASTSetIndexRegMask(int fd, int offset, int index, int and, unsigned char value); |
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298 void ASTGetIndexRegMask(int fd, int offset, int index, int and, unsigned char *value); |
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299 void ASTOpenKey(int fd); |
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300 unsigned int ASTMMIORead32(unsigned char *addr); |
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301 void ASTMMIOWrite32(unsigned char *addr, unsigned int data); |
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302 |
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303 int ast_init_info(struct ast_info *); |
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304 |
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305 #endif /* AST_H */ |
198 #endif /* AST_H */ |