20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 * DEALINGS IN THE SOFTWARE. |
21 * DEALINGS IN THE SOFTWARE. |
23 */ |
22 */ |
24 |
23 |
25 #include <sys/types.h> |
24 #include "libvtsSUNWast.h" |
26 #include <stdio.h> |
25 |
27 #include <sys/mman.h> |
26 hrtime_t ast_loop_time = (hrtime_t)10 * NANOSEC; /* time to busy wait */ |
28 |
27 |
29 #include "gfx_common.h" /* GFX Common definitions */ |
28 |
30 #include "graphicstest.h" |
29 int |
31 #include "libvtsSUNWast.h" /* Common VTS library definitions */ |
30 ast_map_mem( |
32 |
31 register return_packet *const rp, |
33 #include "X11/Xlib.h" |
32 register int const test) |
34 #include "gfx_vts.h" /* VTS Graphics Test common routines */ |
33 { |
35 #include "ast.h" |
34 register int const pagesize = getpagesize(); |
36 |
35 |
37 void |
36 if (ast_get_pci_info() != 0) { |
38 ASTSetReg(int fd, int offset, int value) |
37 gfx_vts_set_message(rp, 1, test, "get pci info failed"); |
39 { |
38 return (-1); |
40 ast_io_reg io_reg; |
39 } |
41 |
40 |
42 io_reg.offset = offset; |
41 |
43 io_reg.value = value; |
42 ast_info.ast_fb_size = (ast_info.ast_fb_size + pagesize - 1) / |
44 ioctl(fd, AST_SET_IO_REG, &io_reg); |
43 pagesize * pagesize; |
45 } |
|
46 |
|
47 void |
|
48 ASTGetReg(int fd, int offset, int *value) |
|
49 { |
|
50 ast_io_reg io_reg; |
|
51 |
|
52 io_reg.offset = offset; |
|
53 ioctl(fd, AST_GET_IO_REG, &io_reg); |
|
54 *value = io_reg.value; |
|
55 } |
|
56 |
|
57 void |
|
58 ASTSetIndexReg(int fd, int offset, int index, unsigned char value) |
|
59 { |
|
60 ast_io_reg io_reg; |
|
61 |
|
62 io_reg.offset = offset; |
|
63 io_reg.value = index; |
|
64 ioctl(fd, AST_SET_IO_REG, &io_reg); |
|
65 io_reg.offset = offset + 1; |
|
66 io_reg.value = value; |
|
67 ioctl(fd, AST_SET_IO_REG, &io_reg); |
|
68 } |
|
69 |
|
70 void |
|
71 ASTGetIndexReg(int fd, int offset, int index, unsigned char *value) |
|
72 { |
|
73 ast_io_reg io_reg; |
|
74 |
|
75 io_reg.offset = offset; |
|
76 io_reg.value = index; |
|
77 ioctl(fd, AST_SET_IO_REG, &io_reg); |
|
78 io_reg.offset = offset + 1; |
|
79 ioctl(fd, AST_GET_IO_REG, &io_reg); |
|
80 *value = io_reg.value; |
|
81 } |
|
82 |
|
83 void |
|
84 ASTSetIndexRegMask(int fd, int offset, int index, int and, unsigned char value) |
|
85 { |
|
86 ast_io_reg io_reg; |
|
87 unsigned char temp; |
|
88 |
|
89 io_reg.offset = offset; |
|
90 io_reg.value = index; |
|
91 ioctl(fd, AST_SET_IO_REG, &io_reg); |
|
92 io_reg.offset = offset + 1; |
|
93 ioctl(fd, AST_GET_IO_REG, &io_reg); |
|
94 temp = (io_reg.value & and) | value; |
|
95 io_reg.offset = offset; |
|
96 io_reg.value = index; |
|
97 ioctl(fd, AST_SET_IO_REG, &io_reg); |
|
98 io_reg.offset = offset + 1; |
|
99 io_reg.value = temp; |
|
100 ioctl(fd, AST_SET_IO_REG, &io_reg); |
|
101 } |
|
102 |
|
103 void |
|
104 ASTGetIndexRegMask(int fd, int offset, int index, int and, unsigned char *value) |
|
105 { |
|
106 ast_io_reg io_reg; |
|
107 unsigned char temp; |
|
108 |
|
109 io_reg.offset = offset; |
|
110 io_reg.value = index; |
|
111 ioctl(fd, AST_SET_IO_REG, &io_reg); |
|
112 io_reg.offset = offset + 1; |
|
113 ioctl(fd, AST_GET_IO_REG, &io_reg); |
|
114 *value = io_reg.value & and; |
|
115 } |
|
116 |
|
117 void |
|
118 ASTOpenKey(int fd) |
|
119 { |
|
120 ASTSetIndexReg(fd, CRTC_PORT, 0x80, 0xA8); |
|
121 } |
|
122 |
|
123 unsigned int |
|
124 ASTMMIORead32(unsigned char *addr) |
|
125 { |
|
126 return (*(volatile unsigned int *)(addr)); |
|
127 } |
|
128 |
|
129 void |
|
130 ASTMMIOWrite32(unsigned char *addr, unsigned int data) |
|
131 { |
|
132 *(unsigned int *)(addr) = data; |
|
133 } |
|
134 |
|
135 |
|
136 unsigned int |
|
137 ASTMMIORead32_8pp(unsigned char *addr) |
|
138 { |
|
139 union |
|
140 { |
|
141 unsigned int ul; |
|
142 unsigned char b[4]; |
|
143 } data; |
|
144 |
|
145 unsigned int m; |
|
146 |
|
147 data.ul = *((volatile unsigned int *)(addr)); |
|
148 |
|
149 m = (((unsigned int)data.b[3]) << 24) | |
|
150 (((unsigned int)data.b[2]) << 16) | |
|
151 (((unsigned int)data.b[1]) << 8) | |
|
152 (((unsigned int)data.b[0])); |
|
153 return (m); |
|
154 } |
|
155 |
|
156 void |
|
157 ASTMMIOWrite32_8pp(unsigned char *addr, unsigned int val) |
|
158 { |
|
159 union |
|
160 { |
|
161 unsigned int ul; |
|
162 unsigned char b[4]; |
|
163 } data; |
|
164 |
|
165 unsigned int m; |
|
166 |
|
167 data.ul = val; |
|
168 m = (((unsigned int)data.b[3]) << 24) | |
|
169 (((unsigned int)data.b[2]) << 16) | |
|
170 (((unsigned int)data.b[1]) << 8) | |
|
171 (((unsigned int)data.b[0])); |
|
172 |
|
173 *(unsigned int*)(addr) = m; |
|
174 } |
|
175 |
|
176 void |
|
177 ASTWaitEngIdle(struct ast_info *pAST) |
|
178 { |
|
179 unsigned int ulEngState, ulEngState2; |
|
180 unsigned char reg; |
|
181 unsigned int ulEngCheckSetting; |
|
182 |
|
183 |
|
184 if (pAST->MMIO2D) |
|
185 return; |
|
186 |
|
187 ulEngCheckSetting = 0x80000000; |
|
188 |
|
189 ASTGetIndexRegMask(pAST->fd, CRTC_PORT, 0xA4, 0x01, ®); |
|
190 if (!reg) { |
|
191 printf("2d disabled\n"); |
|
192 return; |
|
193 } |
|
194 |
|
195 ASTGetIndexRegMask(pAST->fd, CRTC_PORT, 0xA3, 0x0F, ®); |
|
196 if (!reg) { |
|
197 printf("2d not work if in std mode\n"); |
|
198 return; |
|
199 } |
|
200 |
|
201 do |
|
202 { |
|
203 ulEngState = pAST->read32((pAST->CMDQInfo.pjEngStatePort)); |
|
204 ulEngState2 = pAST->read32((pAST->CMDQInfo.pjEngStatePort)); |
|
205 ulEngState2 = pAST->read32((pAST->CMDQInfo.pjEngStatePort)); |
|
206 ulEngState2 = pAST->read32((pAST->CMDQInfo.pjEngStatePort)); |
|
207 ulEngState2 = pAST->read32((pAST->CMDQInfo.pjEngStatePort)); |
|
208 ulEngState2 = pAST->read32((pAST->CMDQInfo.pjEngStatePort)); |
|
209 ulEngState &= 0xFFFC0000; |
|
210 ulEngState2 &= 0xFFFC0000; |
|
211 } while ((ulEngState & ulEngCheckSetting) || (ulEngState != ulEngState2)); |
|
212 } |
|
213 |
|
214 void |
|
215 ASTSaveState(struct ast_info *pAST) |
|
216 { |
|
217 pAST->save_dst_base = pAST->read32(MMIOREG_DST_BASE); |
|
218 pAST->save_line_xy = pAST->read32(MMIOREG_LINE_XY); |
|
219 pAST->save_line_err = pAST->read32(MMIOREG_LINE_Err); |
|
220 pAST->save_line_width = pAST->read32(MMIOREG_LINE_WIDTH); |
|
221 pAST->save_line_k1 = pAST->read32(MMIOREG_LINE_K1); |
|
222 pAST->save_line_k2 = pAST->read32(MMIOREG_LINE_K2); |
|
223 pAST->save_mono_pat1 = pAST->read32(MMIOREG_MONO1); |
|
224 pAST->save_mono_pat2 = pAST->read32(MMIOREG_MONO2); |
|
225 } |
|
226 |
|
227 void |
|
228 ASTResetState(struct ast_info *pAST) |
|
229 { |
|
230 pAST->write32(MMIOREG_DST_BASE, pAST->save_dst_base); |
|
231 pAST->write32(MMIOREG_LINE_XY, pAST->save_line_xy); |
|
232 pAST->write32(MMIOREG_LINE_Err, pAST->save_line_err); |
|
233 pAST->write32(MMIOREG_LINE_WIDTH, pAST->save_line_width); |
|
234 pAST->write32(MMIOREG_LINE_K1, pAST->save_line_k1); |
|
235 pAST->write32(MMIOREG_LINE_K2, pAST->save_line_k2); |
|
236 pAST->write32(MMIOREG_MONO1, pAST->save_mono_pat1); |
|
237 pAST->write32(MMIOREG_MONO2, pAST->save_mono_pat2); |
|
238 } |
|
239 |
|
240 int |
|
241 ASTInitCMDQ(struct ast_info *pAST) |
|
242 { |
|
243 int availableLen; |
|
244 |
|
245 availableLen = pAST->FBMapSize - |
|
246 (pAST->screenWidth * pAST->bytesPerPixel * pAST->screenHeight); |
|
247 |
|
248 if (availableLen < 0x100000) { |
|
249 |
|
250 #if DEBUG |
|
251 printf("Not enough memory to initialize CMDQ, fallback to MMIO\n"); |
|
252 #endif |
|
253 return -1; |
|
254 } |
|
255 |
|
256 pAST->CMDQInfo.pjCmdQBasePort = pAST->MMIOvaddr + 0x8044; |
|
257 pAST->CMDQInfo.pjWritePort = pAST->MMIOvaddr + 0x8048; |
|
258 pAST->CMDQInfo.pjReadPort = pAST->MMIOvaddr + 0x804C; |
|
259 pAST->CMDQInfo.pjEngStatePort = pAST->MMIOvaddr + 0x804C; |
|
260 |
|
261 pAST->CMDQInfo.ulCMDQSize = 0x40000; /* byte */ |
|
262 pAST->CMDQInfo.ulCMDQOffset = |
|
263 (pAST->screenWidth * pAST->bytesPerPixel * pAST->screenHeight); |
|
264 pAST->CMDQInfo.pjCMDQvaddr = pAST->FBvaddr + pAST->CMDQInfo.ulCMDQOffset; |
|
265 pAST->CMDQInfo.ulCMDQueueLen = pAST->CMDQInfo.ulCMDQSize - CMD_QUEUE_GUARD_BAND; |
|
266 pAST->CMDQInfo.ulCMDQMask = pAST->CMDQInfo.ulCMDQSize - 1; |
|
267 |
|
268 |
|
269 pAST->CMDQInfo.ulWritePointer = 0; |
|
270 |
|
271 return 0; |
|
272 } |
|
273 |
|
274 ASTEnableCMDQ(struct ast_info *pAST) |
|
275 { |
|
276 unsigned int ulVMCmdQBasePort = 0; |
|
277 |
|
278 ASTWaitEngIdle(pAST); |
|
279 |
|
280 ulVMCmdQBasePort = pAST->CMDQInfo.ulCMDQOffset >> 3; |
|
281 |
44 |
282 /* |
45 /* |
283 * set CMDQ Threshold |
46 * Map framebuffer |
284 */ |
47 */ |
285 ulVMCmdQBasePort |= 0xF0000000; |
48 |
286 |
49 if (ast_map_fb() != 0) { |
287 pAST->write32((pAST->CMDQInfo.pjCmdQBasePort), ulVMCmdQBasePort); |
50 gfx_vts_set_message(rp, 1, test, "map framebuffer failed"); |
288 pAST->CMDQInfo.ulWritePointer = pAST->read32((pAST->CMDQInfo.pjWritePort)); |
51 return (-1); |
289 pAST->CMDQInfo.ulWritePointer <<= 3; /* byte offset */ |
52 } |
290 } |
53 |
291 |
54 |
292 |
55 ast_info.ast_mmio_size = (ast_info.ast_mmio_size + pagesize - 1) / |
293 ASTEnable2D(struct ast_info *pAST) |
56 pagesize * pagesize; |
294 { |
57 |
295 unsigned int ulData; |
58 /* |
296 |
59 * Map MMIO |
297 pAST->write32((pAST->MMIOvaddr + 0xF004), 0x1e6e0000); |
60 */ |
298 pAST->write32((pAST->MMIOvaddr + 0xF000), 0x1); |
61 if (ast_map_mmio() != 0) { |
299 |
62 gfx_vts_set_message(rp, 1, test, "map MMIO failed"); |
300 ulData = pAST->read32((pAST->MMIOvaddr + 0x1200c)); |
63 return (-1); |
301 pAST->write32((pAST->MMIOvaddr + 0x1200c), (ulData & 0xFFFFFFFD)); |
64 } |
302 |
65 |
303 ASTSetIndexRegMask(pAST->fd, CRTC_PORT, 0xA4, 0xFE, 0x01); |
66 return (0); |
304 } |
67 } |
305 |
68 |
306 unsigned int |
69 |
307 ASTGetCMDQLength(struct ast_info *pAST, unsigned int ulWritePointer, unsigned int ulCMDQMask) |
70 int |
308 { |
71 ast_get_pci_info( |
309 unsigned long ulReadPointer, ulReadPointer2; |
72 void) |
310 |
73 { |
311 do { |
74 struct gfx_pci_cfg pciconfig; |
312 ulReadPointer = pAST->read32((pAST->CMDQInfo.pjReadPort)); |
|
313 ulReadPointer2 = pAST->read32((pAST->CMDQInfo.pjReadPort)); |
|
314 ulReadPointer2 = pAST->read32((pAST->CMDQInfo.pjReadPort)); |
|
315 ulReadPointer2 = pAST->read32((pAST->CMDQInfo.pjReadPort)); |
|
316 ulReadPointer2 = pAST->read32((pAST->CMDQInfo.pjReadPort)); |
|
317 ulReadPointer2 = pAST->read32((pAST->CMDQInfo.pjReadPort)); |
|
318 ulReadPointer &= 0x3FFFF; |
|
319 ulReadPointer2 &= 0x3FFFF; |
|
320 } while (ulReadPointer != ulReadPointer2); |
|
321 |
|
322 return ((ulReadPointer << 3) - ulWritePointer - CMD_QUEUE_GUARD_BAND) & ulCMDQMask; |
|
323 } |
|
324 |
|
325 PKT_SC * |
|
326 ASTRequestCMDQ(struct ast_info *pAST, int ncmd) |
|
327 { |
|
328 unsigned char *pjBuffer; |
|
329 unsigned long i, ulWritePointer, ulCMDQMask, ulCurCMDQLen, ulContinueCMDQLen; |
|
330 unsigned long ulDataLen; |
|
331 |
|
332 ulDataLen = ncmd * 2 * 4; |
|
333 ulWritePointer = pAST->CMDQInfo.ulWritePointer; |
|
334 ulContinueCMDQLen = pAST->CMDQInfo.ulCMDQSize - ulWritePointer; |
|
335 ulCMDQMask = pAST->CMDQInfo.ulCMDQMask; |
|
336 |
|
337 if (ulContinueCMDQLen >= ulDataLen) |
|
338 { |
|
339 /* Get CMDQ Buffer */ |
|
340 if (pAST->CMDQInfo.ulCMDQueueLen >= ulDataLen) |
|
341 { |
|
342 ; |
|
343 } |
|
344 else |
|
345 { |
|
346 do |
|
347 { |
|
348 ulCurCMDQLen = ASTGetCMDQLength(pAST, ulWritePointer, ulCMDQMask); |
|
349 } while (ulCurCMDQLen < ulDataLen); |
|
350 |
|
351 pAST->CMDQInfo.ulCMDQueueLen = ulCurCMDQLen; |
|
352 |
|
353 } |
|
354 |
|
355 pjBuffer = pAST->CMDQInfo.pjCMDQvaddr + ulWritePointer; |
|
356 pAST->CMDQInfo.ulCMDQueueLen -= ulDataLen; |
|
357 pAST->CMDQInfo.ulWritePointer = (ulWritePointer + ulDataLen) & ulCMDQMask; |
|
358 return (PKT_SC *)pjBuffer; |
|
359 } |
|
360 else |
|
361 { /* Fill NULL CMD to the last of the CMDQ */ |
|
362 if (pAST->CMDQInfo.ulCMDQueueLen >= ulContinueCMDQLen) |
|
363 { |
|
364 ; |
|
365 } |
|
366 else |
|
367 { |
|
368 |
|
369 do |
|
370 { |
|
371 ulCurCMDQLen = ASTGetCMDQLength(pAST, ulWritePointer, ulCMDQMask); |
|
372 } while (ulCurCMDQLen < ulContinueCMDQLen); |
|
373 |
|
374 pAST->CMDQInfo.ulCMDQueueLen = ulCurCMDQLen; |
|
375 |
|
376 } |
|
377 |
|
378 pjBuffer = pAST->CMDQInfo.pjCMDQvaddr + ulWritePointer; |
|
379 for (i = 0; i<ulContinueCMDQLen/8; i++, pjBuffer+=8) |
|
380 { |
|
381 pAST->write32(pjBuffer , (unsigned long) PKT_NULL_CMD); |
|
382 pAST->write32((pjBuffer+4) , 0); |
|
383 |
|
384 } |
|
385 pAST->CMDQInfo.ulCMDQueueLen -= ulContinueCMDQLen; |
|
386 pAST->CMDQInfo.ulWritePointer = ulWritePointer = 0; |
|
387 |
|
388 /* Get CMDQ Buffer */ |
|
389 if (pAST->CMDQInfo.ulCMDQueueLen >= ulDataLen) |
|
390 { |
|
391 ; |
|
392 } |
|
393 else |
|
394 { |
|
395 |
|
396 do |
|
397 { |
|
398 ulCurCMDQLen = ASTGetCMDQLength(pAST, ulWritePointer, ulCMDQMask); |
|
399 } while (ulCurCMDQLen < ulDataLen); |
|
400 |
|
401 pAST->CMDQInfo.ulCMDQueueLen = ulCurCMDQLen; |
|
402 |
|
403 } |
|
404 |
|
405 pAST->CMDQInfo.ulCMDQueueLen -= ulDataLen; |
|
406 pjBuffer = pAST->CMDQInfo.pjCMDQvaddr + ulWritePointer; |
|
407 pAST->CMDQInfo.ulWritePointer = (ulWritePointer + ulDataLen) & ulCMDQMask; |
|
408 return (PKT_SC *)pjBuffer; |
|
409 } |
|
410 } |
|
411 |
|
412 void |
|
413 ASTUpdateWritePointer(struct ast_info *pAST) |
|
414 { |
|
415 pAST->write32((pAST->CMDQInfo.pjWritePort), (pAST->CMDQInfo.ulWritePointer >> 3)); |
|
416 } |
|
417 |
|
418 |
|
419 void |
|
420 ASTSetupCmdArg1(struct ast_info *pAST, PKT_SC *pCMD, unsigned int header, unsigned int arg) |
|
421 { |
|
422 pAST->write32((unsigned char *)&pCMD->header, PKT_SINGLE_CMD_HEADER + header); |
|
423 pAST->write32((unsigned char *)pCMD->data, arg); |
|
424 return; |
|
425 } |
|
426 |
|
427 void |
|
428 ASTSetupCmdArg2(struct ast_info *pAST, PKT_SC *pCMD, unsigned int header, |
|
429 unsigned int arg1, unsigned int arg2, |
|
430 unsigned int shift1, unsigned int shift2) |
|
431 { |
|
432 unsigned int ul; |
|
433 |
|
434 pAST->write32((unsigned char *)&pCMD->header, PKT_SINGLE_CMD_HEADER + header); |
|
435 ul = (arg1 << shift1) | (arg2 << shift2); |
|
436 pAST->write32((unsigned char *)pCMD->data, ul); |
|
437 return; |
|
438 } |
|
439 |
|
440 |
|
441 void |
|
442 ASTSetupMMIOArg1(struct ast_info *pAST, unsigned char *addr, unsigned int arg) |
|
443 { |
|
444 unsigned int argr; |
|
445 |
|
446 do { |
|
447 pAST->write32(addr, arg); |
|
448 argr = pAST->read32(addr); |
|
449 } while (arg != argr); |
|
450 |
|
451 return; |
|
452 } |
|
453 |
|
454 void |
|
455 ASTSetupMMIOArg2(struct ast_info *pAST, unsigned char *addr, |
|
456 unsigned int arg1, unsigned int arg2, |
|
457 unsigned int shift1, unsigned int shift2) |
|
458 { |
|
459 unsigned int ul; |
|
460 unsigned int ulr; |
|
461 |
|
462 ul = (arg1 << shift1) | (arg2 << shift2); |
|
463 |
|
464 do { |
|
465 pAST->write32(addr, ul); |
|
466 ulr = pAST->read32(addr); |
|
467 } while (ul != ulr); |
|
468 |
|
469 return; |
|
470 } |
|
471 |
|
472 |
|
473 void * |
|
474 ASTSetupForMonoPatternFill(struct ast_info *pAST, int patx, int paty, int fg, int bg, int rop) |
|
475 { |
|
476 unsigned int cmdreg; |
|
477 unsigned int ul; |
|
478 PKT_SC *pCMD; |
|
479 |
|
480 cmdreg = CMD_BITBLT | CMD_PAT_MONOMASK; |
|
481 switch (pAST->bytesPerPixel) { |
|
482 case 1: |
|
483 cmdreg |= CMD_COLOR_08; |
|
484 break; |
|
485 case 2: |
|
486 cmdreg |= CMD_COLOR_16; |
|
487 break; |
|
488 case 3: |
|
489 case 4: |
|
490 default: |
|
491 cmdreg |= CMD_COLOR_32; |
|
492 break; |
|
493 } |
|
494 |
|
495 cmdreg |= rop << 8; |
|
496 pAST->cmdreg = cmdreg; |
|
497 |
|
498 if (!pAST->MMIO2D) { |
|
499 pCMD = ASTRequestCMDQ(pAST, 5); |
|
500 |
|
501 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_DST_PITCH, pAST->screenPitch, MASK_DST_HEIGHT, 16, 0); |
|
502 pCMD++; |
|
503 |
|
504 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_FG, fg); |
|
505 pCMD++; |
|
506 |
|
507 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_BG, bg); |
|
508 pCMD++; |
|
509 |
|
510 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_MONO1, patx); |
|
511 pCMD++; |
|
512 |
|
513 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_MONO2, paty); |
|
514 |
|
515 } else { |
|
516 ASTSetupMMIOArg2(pAST, MMIOREG_DST_PITCH, pAST->screenPitch, MASK_DST_HEIGHT, 16, 0); |
|
517 ASTSetupMMIOArg1(pAST, MMIOREG_FG, fg); |
|
518 ASTSetupMMIOArg1(pAST, MMIOREG_BG, bg); |
|
519 ASTSetupMMIOArg1(pAST, MMIOREG_MONO1, patx); |
|
520 ASTSetupMMIOArg1(pAST, MMIOREG_MONO2, paty); |
|
521 } |
|
522 } |
|
523 |
|
524 void |
|
525 ASTMonoPatternFill(struct ast_info *pAST, int patx, int paty, int x, int y, |
|
526 int width, int height) |
|
527 { |
|
528 unsigned int cmdreg; |
|
529 PKT_SC *pCMD; |
|
530 |
|
531 cmdreg = pAST->cmdreg; |
|
532 |
|
533 if (!pAST->MMIO2D) { |
|
534 |
|
535 pCMD = ASTRequestCMDQ(pAST, 4); |
|
536 |
|
537 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_DST_BASE, 0); |
|
538 pCMD++; |
|
539 |
|
540 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_DST_XY, x, y, 16, 0); |
|
541 pCMD++; |
|
542 |
|
543 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_RECT_XY, width, height, 16, 0); |
|
544 pCMD++; |
|
545 |
|
546 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_CMD, cmdreg); |
|
547 |
|
548 ASTUpdateWritePointer(pAST); |
|
549 |
|
550 } else { |
|
551 |
|
552 ASTSetupMMIOArg1(pAST, MMIOREG_DST_BASE, 0); |
|
553 ASTSetupMMIOArg2(pAST, MMIOREG_DST_XY, x, y, 16, 0); |
|
554 ASTSetupMMIOArg2(pAST, MMIOREG_RECT_XY, width, height, 16, 0); |
|
555 ASTSetupMMIOArg1(pAST, MMIOREG_CMD, cmdreg); |
|
556 } |
|
557 } |
|
558 |
|
559 void |
|
560 ASTSetupForSolidFill(struct ast_info *pAST, int color, int rop) |
|
561 { |
|
562 unsigned int cmdreg; |
|
563 unsigned int ul; |
|
564 PKT_SC *pCMD; |
|
565 |
|
566 cmdreg = CMD_BITBLT | CMD_PAT_FGCOLOR; |
|
567 switch (pAST->bytesPerPixel) { |
|
568 case 1: |
|
569 cmdreg |= CMD_COLOR_08; |
|
570 break; |
|
571 case 2: |
|
572 cmdreg |= CMD_COLOR_16; |
|
573 break; |
|
574 case 3: |
|
575 case 4: |
|
576 default: |
|
577 cmdreg |= CMD_COLOR_32; |
|
578 break; |
|
579 } |
|
580 |
|
581 cmdreg |= rop << 8; |
|
582 pAST->cmdreg = cmdreg; |
|
583 |
|
584 if (!pAST->MMIO2D) { |
|
585 |
|
586 pCMD = ASTRequestCMDQ(pAST, 2); |
|
587 |
|
588 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_DST_PITCH, pAST->screenPitch, MASK_DST_HEIGHT, 16, 0); |
|
589 pCMD++; |
|
590 |
|
591 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_FG, color); |
|
592 pCMD++; |
|
593 |
|
594 } else { |
|
595 |
|
596 ASTSetupMMIOArg2(pAST, MMIOREG_DST_PITCH, pAST->screenPitch, MASK_DST_HEIGHT, 16, 0); |
|
597 ASTSetupMMIOArg1(pAST, MMIOREG_FG, color); |
|
598 } |
|
599 } |
|
600 |
|
601 void |
|
602 ASTSolidFillRect(struct ast_info *pAST, int x, int y, int width, int height) |
|
603 { |
|
604 unsigned int cmdreg; |
|
605 unsigned int ul; |
|
606 PKT_SC *pCMD; |
|
607 |
|
608 cmdreg = pAST->cmdreg; |
|
609 |
|
610 |
|
611 if (!pAST->MMIO2D) { |
|
612 |
|
613 pCMD = ASTRequestCMDQ(pAST, 4); |
|
614 |
|
615 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_DST_BASE, 0); |
|
616 pCMD++; |
|
617 |
|
618 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_DST_XY, x, y, 16, 0); |
|
619 pCMD++; |
|
620 |
|
621 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_RECT_XY, width, height, 16, 0); |
|
622 pCMD++; |
|
623 |
|
624 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_CMD, cmdreg); |
|
625 pCMD++; |
|
626 |
|
627 ASTUpdateWritePointer(pAST); |
|
628 |
|
629 } else { |
|
630 |
|
631 ASTSetupMMIOArg1(pAST, MMIOREG_DST_BASE, 0); |
|
632 ASTSetupMMIOArg2(pAST, MMIOREG_DST_XY, x, y, 16, 0); |
|
633 ASTSetupMMIOArg2(pAST, MMIOREG_RECT_XY, width, height, 16, 0); |
|
634 ASTSetupMMIOArg1(pAST, MMIOREG_CMD, cmdreg); |
|
635 } |
|
636 } |
|
637 |
|
638 void |
|
639 ASTSetupForSolidLine(struct ast_info *pAST, int color, int rop) |
|
640 { |
|
641 unsigned int cmdreg; |
|
642 unsigned int ul; |
|
643 PKT_SC *pCMD; |
|
644 |
|
645 cmdreg = CMD_BITBLT; |
|
646 switch (pAST->bytesPerPixel) { |
|
647 case 1: |
|
648 cmdreg |= CMD_COLOR_08; |
|
649 break; |
|
650 case 2: |
|
651 cmdreg |= CMD_COLOR_16; |
|
652 break; |
|
653 case 3: |
|
654 case 4: |
|
655 default: |
|
656 cmdreg |= CMD_COLOR_32; |
|
657 break; |
|
658 } |
|
659 |
|
660 cmdreg |= rop << 8; |
|
661 pAST->cmdreg = cmdreg; |
|
662 |
|
663 if (!pAST->MMIO2D) { |
|
664 |
|
665 pCMD = ASTRequestCMDQ(pAST, 3); |
|
666 |
|
667 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_DST_PITCH, pAST->screenPitch, MASK_DST_HEIGHT, 16, 0); |
|
668 pCMD++; |
|
669 |
|
670 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_FG, color); |
|
671 pCMD++; |
|
672 |
|
673 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_BG, 0); |
|
674 pCMD++; |
|
675 |
|
676 } else { |
|
677 |
|
678 ASTSetupMMIOArg2(pAST, MMIOREG_DST_PITCH, pAST->screenPitch, MASK_DST_HEIGHT, 16, 0); |
|
679 ASTSetupMMIOArg1(pAST, MMIOREG_FG, color); |
|
680 ASTSetupMMIOArg1(pAST, MMIOREG_BG, 0); |
|
681 } |
|
682 } |
|
683 |
|
684 void |
|
685 ASTSolidLine(struct ast_info *pAST, int x1, int y1, int x2, int y2) |
|
686 { |
|
687 unsigned int cmdreg; |
|
688 unsigned int ul; |
|
689 PKT_SC *pCMD; |
|
690 int GAbsX, GAbsY; |
|
691 int MM, mm, err, k1, k2, xm; |
|
692 int width, height; |
|
693 |
|
694 cmdreg = (pAST->cmdreg & (~CMD_MASK)) | CMD_ENABLE_CLIP | CMD_NOT_DRAW_LAST_PIXEL; |
|
695 |
|
696 GAbsX = abs(x1 - x2); |
|
697 GAbsY = abs(y1 - y2); |
|
698 |
|
699 cmdreg |= CMD_LINEDRAW; |
|
700 |
|
701 if (GAbsX >= GAbsY) { |
|
702 MM = GAbsX; |
|
703 mm = GAbsY; |
|
704 xm = 1; |
|
705 } else { |
|
706 MM = GAbsY; |
|
707 mm = GAbsX; |
|
708 xm = 0; |
|
709 } |
|
710 |
|
711 if (x1 >= x2) { |
|
712 cmdreg |= CMD_X_DEC; |
|
713 } |
|
714 |
|
715 if (y1 >= y2) { |
|
716 cmdreg |= CMD_Y_DEC; |
|
717 } |
|
718 |
|
719 err = (signed) (2 * mm - MM); |
|
720 k1 = 2 * mm; |
|
721 k2 = (signed) 2 * mm - 2 * MM; |
|
722 |
|
723 |
|
724 if (!pAST->MMIO2D) { |
|
725 |
|
726 pCMD = ASTRequestCMDQ(pAST, 7); |
|
727 |
|
728 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_DST_BASE, 0); |
|
729 pCMD++; |
|
730 |
|
731 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_LINE_XY, x1, y1, 16, 0); |
|
732 pCMD++; |
|
733 |
|
734 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_LINE_Err, xm, (err & MASK_LINE_ERR), 24, 0); |
|
735 pCMD++; |
|
736 |
|
737 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_LINE_WIDTH, (MM & MASK_LINE_WIDTH), 0, 16, 0); |
|
738 pCMD++; |
|
739 |
|
740 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_LINE_K1, (k1 & MASK_LINE_K1)); |
|
741 pCMD++; |
|
742 |
|
743 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_LINE_K2, (k2 & MASK_LINE_K2)); |
|
744 pCMD++; |
|
745 |
|
746 ASTSetupCmdArg1(pAST, pCMD, CMDQREG_CMD, cmdreg); |
|
747 pCMD++; |
|
748 |
|
749 ASTUpdateWritePointer(pAST); |
|
750 |
|
751 ASTWaitEngIdle(pAST); |
|
752 |
|
753 } else { |
|
754 |
|
755 ASTSetupMMIOArg1(pAST, MMIOREG_DST_BASE, 0); |
|
756 ASTSetupMMIOArg2(pAST, MMIOREG_LINE_XY, x1, y1, 16, 0); |
|
757 ASTSetupMMIOArg2(pAST, MMIOREG_LINE_Err, xm, (err & MASK_LINE_ERR), 24, 0); |
|
758 ASTSetupMMIOArg2(pAST, MMIOREG_LINE_WIDTH, (MM & MASK_LINE_WIDTH), 0, 16, 0); |
|
759 ASTSetupMMIOArg1(pAST, MMIOREG_LINE_K1, (k1 & MASK_LINE_K1)); |
|
760 ASTSetupMMIOArg1(pAST, MMIOREG_LINE_K2, (k1 & MASK_LINE_K2)); |
|
761 ASTSetupMMIOArg1(pAST, MMIOREG_CMD, cmdreg); |
|
762 } |
|
763 } |
|
764 |
|
765 void |
|
766 ASTSetClippingRectangle(struct ast_info *pAST, int left, int top, int right, int bottom) |
|
767 { |
|
768 PKT_SC *pCMD; |
|
769 |
|
770 if (!pAST->MMIO2D) { |
|
771 |
|
772 pCMD = ASTRequestCMDQ(pAST, 2); |
|
773 |
|
774 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_CLIP1, (left & MASK_CLIP), (top & MASK_CLIP), 16, 0); |
|
775 pCMD++; |
|
776 |
|
777 ASTSetupCmdArg2(pAST, pCMD, CMDQREG_CLIP2, (right & MASK_CLIP), (bottom & MASK_CLIP), 16, 0); |
|
778 ASTUpdateWritePointer(pAST); |
|
779 |
|
780 } else { |
|
781 |
|
782 ASTSetupMMIOArg2(pAST, MMIOREG_CLIP1, (left & MASK_CLIP), (top & MASK_CLIP), 16, 0); |
|
783 ASTSetupMMIOArg2(pAST, MMIOREG_CLIP2, (right & MASK_CLIP), (bottom & MASK_CLIP), 16, 0); |
|
784 } |
|
785 } |
|
786 |
|
787 int |
|
788 ast_get_pci_info(int fd, struct pci_info *pciInfo) |
|
789 { |
|
790 struct gfx_pci_cfg pciCfg; |
|
791 int i; |
75 int i; |
792 unsigned int bar; |
76 uint_t bar; |
793 |
77 uint_t bar_hi; |
794 if (ioctl(fd, GFX_IOCTL_GET_PCI_CONFIG, &pciCfg) == -1) { |
78 offset_t mem_base[6]; |
795 return -1; |
79 offset_t io_base[6]; |
796 } |
80 int type[6]; |
|
81 uchar_t pots; |
|
82 |
|
83 if (ioctl(ast_info.ast_fd, GFX_IOCTL_GET_PCI_CONFIG, |
|
84 &pciconfig) != 0) { |
|
85 return (-1); |
|
86 } |
|
87 |
|
88 ast_info.ast_vendor = pciconfig.VendorID; |
|
89 ast_info.ast_device = pciconfig.DeviceID; |
797 |
90 |
798 for (i = 0; i < 6; i++) { |
91 for (i = 0; i < 6; i++) { |
799 bar = pciCfg.bar[i]; |
92 type[i] = 0; |
800 if (bar != 0) { |
93 mem_base[i] = 0; |
801 if (bar & PCI_MAP_IO) { |
94 io_base[i] = 0; |
802 pciInfo->ioBase[i] = PCIGETIO(bar); |
95 } |
803 pciInfo->type[i] = bar & PCI_MAP_IO_ATTR_MASK; |
96 |
804 } else { |
97 for (i = 0; i < 6; i++) { |
805 pciInfo->type[i] = bar & PCI_MAP_MEMORY_ATTR_MASK; |
98 bar = pciconfig.bar[i]; |
806 pciInfo->memBase[i] = PCIGETMEMORY(bar); |
99 if (bar != 0) { |
807 if (PCI_MAP_IS64BITMEM(bar)) { |
100 if (bar & PCI_MAP_IO) { |
808 if (i == 5) { |
101 io_base[i] = PCIGETIO(bar); |
809 pciInfo->memBase[i] = 0; |
102 type[i] = bar & PCI_MAP_IO_ATTR_MASK; |
810 } else { |
103 } else { |
811 int bar_hi = pciCfg.bar[i+1]; |
104 type[i] = bar & PCI_MAP_MEMORY_ATTR_MASK; |
812 pciInfo->memBase[i] |= (bar_hi << 32); |
105 mem_base[i] = PCIGETMEMORY(bar); |
813 ++i; |
106 if (PCI_MAP_IS64BITMEM(bar)) { |
|
107 if (i == 5) { |
|
108 mem_base[i] = 0; |
|
109 } else { |
|
110 bar_hi = pciconfig.bar[i+1]; |
|
111 mem_base[i] |= |
|
112 ((offset_t)bar_hi << 32); |
|
113 ++i; |
|
114 } |
|
115 } |
814 } |
116 } |
815 } |
|
816 pciInfo->size[i] = AST_REG_SIZE_LOG2; |
|
817 } |
117 } |
818 } |
118 } |
819 } |
119 |
820 |
120 ast_info.ast_fb_addr = mem_base[0] & 0xfff00000; |
821 return 0; |
121 ast_info.ast_fb_size = 0; |
822 } |
122 |
823 |
123 ast_info.ast_mmio_addr = mem_base[1] & 0xffff0000; |
824 int |
124 ast_info.ast_mmio_size = AST_MMIO_SIZE; |
825 ast_get_mem_info(struct pci_info *pci_info, struct ast_info *pAST) |
125 |
826 { |
126 ast_info.ast_relocate_io = io_base[2]; |
827 unsigned char reg; |
127 |
828 |
128 if (ast_open_key() != 0) |
829 pAST->FBPhysAddr = pci_info->memBase[0] & 0xfff00000; |
129 return (-1); |
830 pAST->FBMapSize = 0; |
130 |
831 |
131 if (ast_get_index_reg(&pots, CRTC_PORT, 0xAA) != 0) |
832 pAST->MMIOPhysAddr = pci_info->memBase[1] & 0xffff0000; |
132 return (-1); |
833 pAST->MMIOMapSize = AST_MMIO_SIZE; |
133 |
834 |
134 switch (pots & 0x03) { |
835 pAST->RelocateIO = pci_info->ioBase[2]; |
135 case 0x00: |
836 |
136 ast_info.ast_fb_size = AST_VRAM_SIZE_08M; |
837 ASTOpenKey(pAST->fd); |
137 break; |
838 ASTGetIndexRegMask(pAST->fd, CRTC_PORT, 0xAA, 0xFF, ®); |
138 |
839 switch (reg & 0x03) |
139 case 0x01: |
840 { |
140 ast_info.ast_fb_size = AST_VRAM_SIZE_16M; |
841 case 0x00: |
141 break; |
842 pAST->FBMapSize = AST_VRAM_SIZE_08M; |
142 |
843 break; |
143 case 0x02: |
844 case 0x01: |
144 ast_info.ast_fb_size = AST_VRAM_SIZE_32M; |
845 pAST->FBMapSize = AST_VRAM_SIZE_16M; |
145 break; |
846 break; |
146 |
847 case 0x02: |
147 case 0x03: |
848 pAST->FBMapSize = AST_VRAM_SIZE_32M; |
148 ast_info.ast_fb_size = AST_VRAM_SIZE_64M; |
849 break; |
149 break; |
850 case 0x03: |
150 } |
851 pAST->FBMapSize = AST_VRAM_SIZE_64M; |
151 |
852 break; |
152 if (gfx_vts_debug_mask & VTS_DEBUG) { |
853 default: |
153 printf("ast_vendor = 0x%04x, ast_device = 0x%04x\n", |
854 pAST->FBMapSize = AST_VRAM_SIZE_08M; |
154 ast_info.ast_vendor, ast_info.ast_device); |
855 break; |
155 printf("ast_fb_addr 0x%llx, ast_fb_size 0x%lx\n", |
856 } |
156 (unsigned long long)ast_info.ast_fb_addr, |
857 |
157 (unsigned long)ast_info.ast_fb_size); |
858 #if DEBUG |
158 printf("ast_mmio_addr 0x%llx, ast_mmio_size 0x%lx\n", |
859 printf("FBPhysAddr=0x%x FBMapSize=0x%x\n", pAST->FBPhysAddr, pAST->FBMapSize); |
159 (unsigned long long)ast_info.ast_mmio_addr, |
860 printf("MMIOPhysAddr=0x%x MMIOMapSize=0x%x\n", pAST->MMIOPhysAddr, pAST->MMIOMapSize); |
160 (unsigned long)ast_info.ast_mmio_size); |
861 printf("RelocateIO=0x%x\n", pAST->RelocateIO); |
161 printf("ast_relocate_io 0x%llx\n", |
862 #endif |
162 (unsigned long long)ast_info.ast_relocate_io); |
863 |
163 } |
864 return 0; |
164 |
865 } |
165 return (0); |
866 |
166 } |
867 |
167 |
868 int |
168 int |
869 ast_init_info(struct ast_info *pAST) |
169 ast_map_mmio( |
870 { |
170 void) |
871 unsigned char val; |
171 { |
872 unsigned int status = 0; |
172 register void *ptr; |
873 |
173 |
874 /* |
174 if (ast_info.ast_mmio_ptr == NULL) { |
|
175 ptr = mmap(NULL, ast_info.ast_mmio_size, |
|
176 PROT_READ | PROT_WRITE, MAP_SHARED, |
|
177 ast_info.ast_fd, ast_info.ast_mmio_addr); |
|
178 |
|
179 if (ptr == MAP_FAILED) |
|
180 return (-1); |
|
181 } |
|
182 |
|
183 ast_info.ast_mmio_ptr = (uchar_t *)ptr; |
|
184 |
|
185 if (gfx_vts_debug_mask & VTS_DEBUG) |
|
186 printf("ast_mmio_ptr = 0x%llx\n", |
|
187 (unsigned long long)ast_info.ast_mmio_ptr); |
|
188 |
|
189 return (0); |
|
190 } |
|
191 |
|
192 |
|
193 int |
|
194 ast_map_fb( |
|
195 void) |
|
196 { |
|
197 register void *ptr; |
|
198 |
|
199 if (ast_info.ast_fb_ptr == NULL) { |
|
200 ptr = mmap(NULL, ast_info.ast_fb_size, |
|
201 PROT_READ | PROT_WRITE, MAP_SHARED, |
|
202 ast_info.ast_fd, ast_info.ast_fb_addr); |
|
203 |
|
204 if (ptr == MAP_FAILED) |
|
205 return (-1); |
|
206 |
|
207 ast_info.ast_fb_ptr = (uchar_t *)ptr; |
|
208 } |
|
209 |
|
210 if (gfx_vts_debug_mask & VTS_DEBUG) |
|
211 printf("ast_fb_ptr = 0x%llx\n", |
|
212 (unsigned long long)ast_info.ast_fb_ptr); |
|
213 |
|
214 return (0); |
|
215 } |
|
216 |
|
217 |
|
218 int |
|
219 ast_init_info( |
|
220 register return_packet *const rp, |
|
221 register int const test) |
|
222 { |
|
223 register uint_t mode; |
|
224 register uint_t width; |
|
225 register uint_t height; |
|
226 register uint_t depth; |
|
227 register uint_t pixelsize; |
|
228 register uint_t offset; |
|
229 register uint_t memsize; |
|
230 uchar_t save_gctl; |
|
231 uchar_t misc; |
|
232 uchar_t hde; |
|
233 uchar_t ovf; |
|
234 uchar_t vde; |
|
235 uchar_t off; |
|
236 uchar_t undloc; |
|
237 uchar_t modectl; |
|
238 uchar_t pcicr3; |
|
239 uchar_t ecm; |
|
240 uchar_t xhovf; |
|
241 uchar_t xvovf; |
|
242 uchar_t offovf; |
|
243 unsigned int status = 0; |
|
244 |
|
245 /* |
875 * first check if the hardware is already initialized. |
246 * first check if the hardware is already initialized. |
876 * If not, abort |
247 * If not, abort |
877 */ |
248 */ |
878 ioctl(pAST->fd, AST_GET_STATUS_FLAGS, &status); |
249 if (ioctl(ast_info.ast_fd, AST_GET_STATUS_FLAGS, &status) != 0) { |
879 if (!(status & AST_STATUS_HW_INITIALIZED)) |
250 gfx_vts_set_message(rp, 1, test, |
880 return -1; |
251 "AST_GET_STATUS_FLAGS failed"); |
881 |
252 return (-1); |
882 pAST->MMIO2D = 0; |
253 } |
883 |
254 |
884 ASTOpenKey(pAST->fd); |
255 if (!(status & AST_STATUS_HW_INITIALIZED)) { |
885 |
256 gfx_vts_set_message(rp, 1, test, |
886 /* |
257 "AST_GET_STATUS_FLAGS not initialized"); |
887 * get the VDE |
258 return (-1); |
888 */ |
259 } |
889 ASTGetIndexRegMask(pAST->fd, CRTC_PORT, 0x01, 0xff, &val); |
260 |
890 pAST->screenWidth = ((int)(val + 1)) << 3; |
261 if (ast_open_key() != 0) { |
891 |
262 gfx_vts_set_message(rp, 1, test, "unable to open key"); |
892 switch (pAST->screenWidth) { |
263 return (-1); |
893 case 1920: |
264 } |
894 case 1600: |
265 |
895 pAST->screenHeight = 1200; |
266 if (ast_get_reg(&save_gctl, GR_PORT) != 0) { |
896 break; |
267 gfx_vts_set_message(rp, 1, test, |
897 case 1280: |
268 "unable to get the gctl index"); |
898 pAST->screenHeight = 1024; |
269 return (-1); |
899 break; |
270 } |
900 case 1024: |
271 |
901 pAST->screenHeight = 768; |
272 if (ast_get_index_reg(&misc, GR_PORT, 0x06) != 0) { |
902 break; |
273 gfx_vts_set_message(rp, 1, test, "unable to get the misc"); |
903 case 800: |
274 return (-1); |
904 pAST->screenHeight = 600; |
275 } |
905 break; |
276 |
906 case 640: |
277 if (ast_set_reg(GR_PORT, save_gctl) != 0) { |
907 default: |
278 gfx_vts_set_message(rp, 1, test, |
908 pAST->screenHeight = 480; |
279 "unable to set the gctl index"); |
909 break; |
280 return (-1); |
910 } |
281 } |
911 |
282 |
912 /* |
283 if (ast_get_index_reg(&hde, CRTC_PORT, 0x01) != 0) { |
913 * get the display depth info |
284 gfx_vts_set_message(rp, 1, test, "unable to get the hde"); |
914 */ |
285 return (-1); |
915 ASTGetIndexRegMask(pAST->fd, CRTC_PORT, 0xA2, 0xff, &val); |
286 } |
916 if (val & 0x80) { |
287 |
917 /* 32 bits */ |
288 if (ast_get_index_reg(&ovf, CRTC_PORT, 0x07) != 0) { |
918 pAST->bytesPerPixel = 4; |
289 gfx_vts_set_message(rp, 1, test, "unable to get the ovf"); |
919 pAST->read32 = (PFNRead32) ASTMMIORead32; |
290 return (-1); |
920 pAST->write32 = (PFNWrite32) ASTMMIOWrite32; |
291 } |
921 |
292 |
|
293 if (ast_get_index_reg(&vde, CRTC_PORT, 0x12) != 0) { |
|
294 gfx_vts_set_message(rp, 1, test, "unable to get the vde"); |
|
295 return (-1); |
|
296 } |
|
297 |
|
298 if (ast_get_index_reg(&off, CRTC_PORT, 0x13) != 0) { |
|
299 gfx_vts_set_message(rp, 1, test, "unable to get the offset"); |
|
300 return (-1); |
|
301 } |
|
302 |
|
303 if (ast_get_index_reg(&undloc, CRTC_PORT, 0x14) != 0) { |
|
304 gfx_vts_set_message(rp, 1, test, "unable to get the undloc"); |
|
305 return (-1); |
|
306 } |
|
307 |
|
308 if (ast_get_index_reg(&modectl, CRTC_PORT, 0x17) != 0) { |
|
309 gfx_vts_set_message(rp, 1, test, "unable to get the modectl"); |
|
310 return (-1); |
|
311 } |
|
312 |
|
313 if (ast_get_index_reg(&pcicr3, CRTC_PORT, 0xa2) != 0) { |
|
314 gfx_vts_set_message(rp, 1, test, "unable to get the pcicr3"); |
|
315 return (-1); |
|
316 } |
|
317 |
|
318 if (ast_get_index_reg(&ecm, CRTC_PORT, 0xa3) != 0) { |
|
319 gfx_vts_set_message(rp, 1, test, "unable to get the ecm"); |
|
320 return (-1); |
|
321 } |
|
322 |
|
323 if (ast_get_index_reg(&xhovf, CRTC_PORT, 0xac) != 0) { |
|
324 gfx_vts_set_message(rp, 1, test, "unable to get the xhovf"); |
|
325 return (-1); |
|
326 } |
|
327 |
|
328 if (ast_get_index_reg(&xvovf, CRTC_PORT, 0xae) != 0) { |
|
329 gfx_vts_set_message(rp, 1, test, "unable to get the xvovf"); |
|
330 return (-1); |
|
331 } |
|
332 |
|
333 if (ast_get_index_reg(&offovf, CRTC_PORT, 0xb0) != 0) { |
|
334 gfx_vts_set_message(rp, 1, test, "unable to get the offovf"); |
|
335 return (-1); |
|
336 } |
|
337 |
|
338 width = (((((uint_t)xhovf & 0x4) >> 2 << 8) | |
|
339 (uint_t)hde) + 1) << 3; |
|
340 |
|
341 height = ((((uint_t)xvovf & 0x2) >> 1 << 10) | |
|
342 (((uint_t)ovf & 0x40) >> 6 << 9) | |
|
343 (((uint_t)ovf & 0x02) >> 1 << 8) | |
|
344 (uint_t)vde) + 1; |
|
345 |
|
346 offset = (((uint_t)offovf & 0x3f) << 8) | (uint_t)off; |
|
347 |
|
348 memsize = (undloc & 0x40) ? 4 : |
|
349 ((modectl & 0x40) ? 1 : 2); |
|
350 |
|
351 if (!(misc & 0x01)) { |
|
352 if (!(ecm & 0x01)) { |
|
353 mode = VIS_TEXT; |
|
354 depth = 4; |
|
355 width /= 8; |
|
356 height /= 16; |
|
357 pixelsize = 2; |
|
358 } else { |
|
359 mode = VIS_PIXEL; |
|
360 depth = 8; |
|
361 pixelsize = 1; |
|
362 } |
922 } else { |
363 } else { |
923 pAST->bytesPerPixel = 1; |
364 mode = VIS_PIXEL; |
924 pAST->read32 = (PFNRead32) ASTMMIORead32_8pp; |
365 |
925 pAST->write32 = (PFNWrite32) ASTMMIOWrite32_8pp; |
366 switch (ecm & 0xf) { |
926 } |
367 case 0x01: |
927 |
368 /* enable enhanced 256 color display mode */ |
928 pAST->screenPitch = pAST->screenWidth * pAST->bytesPerPixel; |
369 depth = 8; |
|
370 pixelsize = 1; |
|
371 break; |
|
372 |
|
373 case 0x02: |
|
374 /* enable 15-bpp high color display mode (rgb:555) */ |
|
375 depth = 15; |
|
376 pixelsize = 2; |
|
377 break; |
|
378 |
|
379 case 0x04: |
|
380 /* enable 16-bpp high color display mode (rgb:565) */ |
|
381 depth = 16; |
|
382 pixelsize = 2; |
|
383 break; |
|
384 |
|
385 case 0x08: |
|
386 /* enable 32-bpp true color display mode (argb:8888) */ |
|
387 depth = 32; |
|
388 pixelsize = 4; |
|
389 break; |
|
390 |
|
391 default: |
|
392 gfx_vts_set_message(rp, 1, test, "invalid ecm"); |
|
393 return (-1); |
|
394 } |
|
395 } |
|
396 |
|
397 ast_info.ast_mode = mode; |
|
398 ast_info.ast_width = width; |
|
399 ast_info.ast_height = height; |
|
400 ast_info.ast_depth = depth; |
|
401 ast_info.ast_pixelsize = pixelsize; |
|
402 ast_info.ast_linesize = offset * memsize * 2; |
|
403 |
|
404 switch (pcicr3 & 0xc0) { |
|
405 case 0x00: /* little endian */ |
|
406 case 0x40: |
|
407 ast_info.ast_endian = 0; |
|
408 break; |
|
409 |
|
410 case 0x80: /* big endian 32 */ |
|
411 ast_info.ast_endian = 2; |
|
412 break; |
|
413 |
|
414 case 0xc0: /* big endian 16 */ |
|
415 ast_info.ast_endian = 1; |
|
416 break; |
|
417 } |
|
418 |
|
419 if (gfx_vts_debug_mask & VTS_DEBUG) { |
|
420 printf("width=%d height=%d depth=%d pitch=%d\n", |
|
421 ast_info.ast_width, ast_info.ast_height, |
|
422 ast_info.ast_depth, ast_info.ast_linesize); |
|
423 } |
|
424 |
|
425 return (0); |
|
426 } |
|
427 |
|
428 |
|
429 int |
|
430 ast_init_graphics( |
|
431 void) |
|
432 { |
|
433 unsigned int ulData; |
|
434 register int status = 0; |
929 |
435 |
930 /* |
436 /* |
931 * Enable MMIO |
437 * Enable MMIO |
932 */ |
438 */ |
933 ASTSetIndexRegMask(pAST->fd, CRTC_PORT, 0xA1, 0xff, 0x04); |
439 |
934 |
440 if (ast_get_index_reg(&ast_info.ast_pcicr2, CRTC_PORT, 0xA1) != 0) |
935 return 0; |
441 return (-1); |
936 } |
442 |
937 |
443 if (ast_set_index_reg(CRTC_PORT, 0xA1, 0x4) != 0) |
938 int |
444 return (-1); |
939 ast_map_mem(struct ast_info *pAST, return_packet *rp, int test) |
445 |
940 { |
446 ast_info.ast_remap_base = ast_mmio_read32(0xF004); |
941 struct pci_info pci_info; |
447 ast_info.ast_prot_key = ast_mmio_read32(0xF000); |
942 int pageSize, size; |
448 if (ast_get_index_reg(&ast_info.ast_misc_control, CRTC_PORT, 0xA4) != 0) |
943 int fd = pAST->fd; |
449 return (-1); |
944 |
450 |
945 if (ast_get_pci_info(fd, &pci_info) == -1) { |
451 ast_mmio_write32(0xF004, 0x1e6e0000); |
946 gfx_vts_set_message(rp, 1, test, "get pci info failed"); |
452 ast_mmio_write32(0xF000, 0x1); |
947 return -1; |
453 |
948 } |
454 ulData = ast_mmio_read32(0x1200c); |
949 |
455 ast_mmio_write32(0x1200c, ulData & 0xFFFFFFFD); |
950 |
456 |
951 if (ast_get_mem_info(&pci_info, pAST) == -1) { |
457 if (!(ast_info.ast_misc_control & 0x01)) { |
952 gfx_vts_set_message(rp, 1, test, "get mem info failed"); |
458 if (ast_set_index_reg(CRTC_PORT, 0xA4, |
953 return -1; |
459 ast_info.ast_misc_control | 0x01) != 0) |
954 } |
460 return (-1); |
955 |
461 status = 1; |
956 /* |
462 } |
957 * Map framebuffer |
463 |
958 */ |
464 if (!ast_wait_idle()) |
959 pageSize = getpagesize(); |
465 return (-1); |
960 size = pAST->FBMapSize + (pageSize - 1) & (~(pageSize - 1)); |
466 |
961 |
467 ast_info.ast_queue = ast_mmio_read32(MMIOREG_QUEUE); |
962 pAST->FBvaddr = (unsigned char *)mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, |
468 ast_info.ast_dst_base = ast_mmio_read32(MMIOREG_DST_BASE); |
963 fd, pAST->FBPhysAddr); |
469 ast_info.ast_dst_pitch = ast_mmio_read32(MMIOREG_DST_PITCH); |
964 |
470 ast_info.ast_dst_xy = ast_mmio_read32(MMIOREG_DST_XY); |
965 if (pAST->FBvaddr == MAP_FAILED) { |
471 ast_info.ast_line_err = ast_mmio_read32(MMIOREG_LINE_ERR); |
966 gfx_vts_set_message(rp, 1, test, "map framebuffer failed"); |
472 ast_info.ast_rect_xy = ast_mmio_read32(MMIOREG_RECT_XY); |
967 return -1; |
473 ast_info.ast_fg = ast_mmio_read32(MMIOREG_FG); |
968 } |
474 ast_info.ast_bg = ast_mmio_read32(MMIOREG_BG); |
969 |
475 ast_info.ast_mono1 = ast_mmio_read32(MMIOREG_MONO1); |
970 |
476 ast_info.ast_mono2 = ast_mmio_read32(MMIOREG_MONO2); |
971 /* |
477 ast_info.ast_clip1 = ast_mmio_read32(MMIOREG_CLIP1); |
972 * Map MMIO |
478 ast_info.ast_clip2 = ast_mmio_read32(MMIOREG_CLIP2); |
973 */ |
479 |
974 size = pAST->MMIOMapSize + (pageSize - 1) & (~(pageSize - 1)); |
480 if (!(ast_info.ast_queue & QUEUE_MEMORY_MAP)) { |
975 |
481 ast_mmio_write32(MMIOREG_QUEUE, |
976 pAST->MMIOvaddr = (unsigned char *)mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, |
482 ast_info.ast_queue | QUEUE_MEMORY_MAP); |
977 fd, pAST->MMIOPhysAddr); |
483 status = 1; |
978 |
484 } |
979 if (pAST->MMIOvaddr == MAP_FAILED) { |
485 |
980 gfx_vts_set_message(rp, 1, test, "map MMIO failed"); |
486 if (!ast_store_mmio(MMIOREG_CLIP1, |
981 return -1; |
487 ((0 & MASK_CLIP) << 16) | |
982 } |
488 (0 & MASK_CLIP))) |
983 |
489 return (-1); |
984 return 0; |
490 |
985 } |
491 if (!ast_store_mmio(MMIOREG_CLIP2, |
986 |
492 ((ast_info.ast_width & MASK_CLIP) << 16) | |
987 int |
493 (ast_info.ast_height & MASK_CLIP))) |
988 ast_unmap_mem(struct ast_info *pAST, return_packet *rp, int test) |
494 return (-1); |
989 { |
495 |
990 /* |
496 return (status); |
991 * Unmap Frame Buffer |
497 } |
992 */ |
498 |
993 |
499 |
994 if (munmap((void *)pAST->FBvaddr, pAST->FBMapSize) == -1) { |
500 int |
995 gfx_vts_set_message(rp, 1, test, "unmap framebuffer failed"); |
501 ast_finish_graphics( |
996 return -1; |
502 void) |
997 } |
503 { |
998 |
504 register int status = 0; |
999 if (munmap((void *)pAST->MMIOvaddr, pAST->MMIOMapSize) == -1) { |
505 |
1000 gfx_vts_set_message(rp, 1, test, "unmap MMIO failed"); |
506 ast_store_mmio(MMIOREG_DST_BASE, ast_info.ast_dst_base); |
1001 return -1; |
507 ast_store_mmio(MMIOREG_DST_PITCH, ast_info.ast_dst_pitch); |
1002 } |
508 ast_store_mmio(MMIOREG_DST_XY, ast_info.ast_dst_xy); |
1003 |
509 ast_store_mmio(MMIOREG_LINE_ERR, ast_info.ast_line_err); |
1004 return 0; |
510 ast_store_mmio(MMIOREG_RECT_XY, ast_info.ast_rect_xy); |
1005 } |
511 ast_store_mmio(MMIOREG_FG, ast_info.ast_fg); |
|
512 ast_store_mmio(MMIOREG_BG, ast_info.ast_bg); |
|
513 ast_store_mmio(MMIOREG_MONO1, ast_info.ast_mono1); |
|
514 ast_store_mmio(MMIOREG_MONO2, ast_info.ast_mono2); |
|
515 ast_store_mmio(MMIOREG_CLIP1, ast_info.ast_clip1); |
|
516 ast_store_mmio(MMIOREG_CLIP2, ast_info.ast_clip2); |
|
517 |
|
518 ast_store_mmio(MMIOREG_QUEUE, ast_info.ast_queue); |
|
519 |
|
520 if (!(ast_info.ast_misc_control & 0x01)) { |
|
521 if (ast_set_index_reg(CRTC_PORT, |
|
522 0xA4, ast_info.ast_misc_control) != 0) |
|
523 status = -1; |
|
524 else |
|
525 status = 1; |
|
526 } |
|
527 |
|
528 ast_mmio_write32(0xF004, ast_info.ast_remap_base); |
|
529 ast_mmio_write32(0xF000, ast_info.ast_prot_key); |
|
530 |
|
531 if (ast_set_index_reg(CRTC_PORT, 0xA1, ast_info.ast_pcicr2) != 0) |
|
532 status = -1; |
|
533 |
|
534 return (status); |
|
535 } |
|
536 |
|
537 |
|
538 int |
|
539 ast_save_palet( |
|
540 void) |
|
541 { |
|
542 register uint_t coloron; |
|
543 register int status = 1; |
|
544 uchar_t junk; |
|
545 |
|
546 for (coloron = 0; coloron < 256; coloron++) { |
|
547 if (ast_set_reg(DAC_INDEX_READ, coloron) != 0) |
|
548 status = -1; |
|
549 |
|
550 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
551 status = -1; |
|
552 |
|
553 if (ast_get_reg(&ast_info.ast_red[coloron], DAC_DATA) != 0) |
|
554 status = -1; |
|
555 |
|
556 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
557 status = -1; |
|
558 |
|
559 if (ast_get_reg(&ast_info.ast_green[coloron], DAC_DATA) != 0) |
|
560 status = -1; |
|
561 |
|
562 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
563 status = -1; |
|
564 |
|
565 if (ast_get_reg(&ast_info.ast_blue[coloron], DAC_DATA) != 0) |
|
566 status = -1; |
|
567 |
|
568 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
569 status = -1; |
|
570 } |
|
571 |
|
572 return (status); |
|
573 } |
|
574 |
|
575 |
|
576 int |
|
577 ast_set_palet( |
|
578 void) |
|
579 { |
|
580 register uint_t coloron; |
|
581 register int status = 1; |
|
582 register uint_t maxdac; |
|
583 uchar_t ramdac_ctrl; |
|
584 uchar_t new_red[256]; |
|
585 uchar_t new_green[256]; |
|
586 uchar_t new_blue[256]; |
|
587 uchar_t junk; |
|
588 |
|
589 if (ast_get_index_reg(&ramdac_ctrl, CRTC_PORT, 0xA8) != 0) |
|
590 return (-1); |
|
591 |
|
592 maxdac = (ramdac_ctrl & 0x2) ? 255 : 63; |
|
593 |
|
594 switch (ast_info.ast_depth) { |
|
595 case 8: /* 3, 3, 2 */ |
|
596 for (coloron = 0; coloron < 256; coloron++) { |
|
597 new_red[coloron] = |
|
598 (uint8_t)(((coloron >> 5) & 0x7) * maxdac / 7); |
|
599 new_green[coloron] = |
|
600 (uint8_t)(((coloron >> 2) & 0x7) * maxdac / 7); |
|
601 new_blue[coloron] = |
|
602 (uint8_t)((coloron & 0x3) * maxdac / 3); |
|
603 } |
|
604 break; |
|
605 |
|
606 case 15: /* 5, 5, 5 */ |
|
607 for (coloron = 0; coloron < 256; coloron++) { |
|
608 new_red[coloron] = |
|
609 (uint8_t)((coloron / 8) * maxdac / 31); |
|
610 new_green[coloron] = |
|
611 (uint8_t)((coloron / 8) * maxdac / 31); |
|
612 new_blue[coloron] = |
|
613 (uint8_t)((coloron / 8) * maxdac / 31); |
|
614 } |
|
615 break; |
|
616 |
|
617 case 16: /* 5, 6, 5 */ |
|
618 for (coloron = 0; coloron < 256; coloron++) { |
|
619 new_red[coloron] = |
|
620 (uint8_t)((coloron / 8) * maxdac / 31); |
|
621 new_green[coloron] = |
|
622 (uint8_t)((coloron / 4) * maxdac / 63); |
|
623 new_blue[coloron] = |
|
624 (uint8_t)((coloron / 8) * maxdac / 31); |
|
625 } |
|
626 break; |
|
627 |
|
628 default: /* 8, 8, 8 */ |
|
629 for (coloron = 0; coloron < 256; coloron++) { |
|
630 new_red[coloron] = |
|
631 (uint8_t)(coloron * maxdac / 255); |
|
632 new_green[coloron] = |
|
633 (uint8_t)(coloron * maxdac / 255); |
|
634 new_blue[coloron] = |
|
635 (uint8_t)(coloron * maxdac / 255); |
|
636 } |
|
637 break; |
|
638 } |
|
639 |
|
640 /* Don't set the palet if it matches what we will set. */ |
|
641 |
|
642 for (coloron = 0; coloron < 256; coloron++) { |
|
643 if ((ast_info.ast_red[coloron] != new_red[coloron]) || |
|
644 (ast_info.ast_green[coloron] != new_green[coloron]) || |
|
645 (ast_info.ast_blue[coloron] != new_blue[coloron])) |
|
646 break; |
|
647 } |
|
648 |
|
649 if (coloron == 256) |
|
650 return (0); |
|
651 |
|
652 ast_info.ast_palet_changed = 1; |
|
653 |
|
654 for (coloron = 0; coloron < 256; coloron++) { |
|
655 if (ast_set_reg(DAC_INDEX_WRITE, coloron) != 0) |
|
656 status = -1; |
|
657 |
|
658 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
659 status = -1; |
|
660 |
|
661 if (ast_set_reg(DAC_DATA, new_red[coloron]) != 0) |
|
662 status = -1; |
|
663 |
|
664 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
665 status = -1; |
|
666 |
|
667 if (ast_set_reg(DAC_DATA, new_green[coloron]) != 0) |
|
668 status = -1; |
|
669 |
|
670 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
671 status = -1; |
|
672 |
|
673 if (ast_set_reg(DAC_DATA, new_blue[coloron]) != 0) |
|
674 status = -1; |
|
675 |
|
676 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
677 status = -1; |
|
678 } |
|
679 |
|
680 return (status); |
|
681 } |
|
682 |
|
683 |
|
684 int |
|
685 ast_restore_palet( |
|
686 void) |
|
687 { |
|
688 register uint_t coloron; |
|
689 register int status = 1; |
|
690 uchar_t junk; |
|
691 |
|
692 if (!ast_info.ast_palet_changed) |
|
693 return (0); |
|
694 |
|
695 for (coloron = 0; coloron < 256; coloron++) { |
|
696 if (ast_set_reg(DAC_INDEX_WRITE, coloron) != 0) |
|
697 status = -1; |
|
698 |
|
699 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
700 status = -1; |
|
701 |
|
702 if (ast_set_reg(DAC_DATA, ast_info.ast_red[coloron]) != 0) |
|
703 status = -1; |
|
704 |
|
705 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
706 status = -1; |
|
707 |
|
708 if (ast_set_reg(DAC_DATA, ast_info.ast_green[coloron]) != 0) |
|
709 status = -1; |
|
710 |
|
711 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
712 status = -1; |
|
713 |
|
714 if (ast_set_reg(DAC_DATA, ast_info.ast_blue[coloron]) != 0) |
|
715 status = -1; |
|
716 |
|
717 if (ast_get_reg(&junk, SEQ_PORT) != 0) |
|
718 status = -1; |
|
719 } |
|
720 |
|
721 ast_info.ast_palet_changed = 0; |
|
722 return (status); |
|
723 } |
|
724 |
|
725 |
|
726 uint_t |
|
727 ast_color( |
|
728 register uint_t const red, |
|
729 register uint_t const green, |
|
730 register uint_t const blue) |
|
731 { |
|
732 register uint_t value; |
|
733 |
|
734 switch (ast_info.ast_depth) { |
|
735 case 8: /* 3, 3, 2 */ |
|
736 value = ((red >> 5) & 0x7) << 5; |
|
737 value |= ((green >> 5) & 0x7) << 2; |
|
738 value |= (blue >> 6) & 0x3; |
|
739 break; |
|
740 |
|
741 case 15: /* 5, 5, 5 */ |
|
742 value = ((red >> 3) & 0x1f) << 10; |
|
743 value |= ((green >> 3) & 0x1f) << 5; |
|
744 value |= (blue >> 3) & 0x1f; |
|
745 break; |
|
746 |
|
747 case 16: /* 5, 6, 5 */ |
|
748 value = ((red >> 3) & 0x1f) << 11; |
|
749 value |= ((green >> 2) & 0x3f) << 5; |
|
750 value |= (blue >> 3) & 0x1f; |
|
751 break; |
|
752 |
|
753 default: /* 8, 8, 8 */ |
|
754 value = (red & 0xff) << 16; |
|
755 value |= (green & 0xff) << 8; |
|
756 value |= blue & 0xff; |
|
757 break; |
|
758 } |
|
759 |
|
760 return (value); |
|
761 } |
|
762 |
|
763 |
|
764 int |
|
765 ast_open_key( |
|
766 void) |
|
767 { |
|
768 if (ast_set_index_reg(CRTC_PORT, 0x80, 0xA8) != 0) |
|
769 return (-1); |
|
770 return (0); |
|
771 } |
|
772 |
|
773 |
|
774 int |
|
775 ast_fill_solid_rect( |
|
776 register uint_t const x1, |
|
777 register uint_t const y1, |
|
778 register uint_t const x2, |
|
779 register uint_t const y2, |
|
780 register uint_t const fg) |
|
781 { |
|
782 register uint_t cmdreg; |
|
783 |
|
784 cmdreg = CMD_BITBLT | CMD_PAT_FGCOLOR | 0xf000; |
|
785 switch (ast_info.ast_pixelsize) { |
|
786 case 1: |
|
787 cmdreg |= CMD_COLOR_08; |
|
788 break; |
|
789 case 2: |
|
790 cmdreg |= CMD_COLOR_16; |
|
791 break; |
|
792 case 3: |
|
793 case 4: |
|
794 default: |
|
795 cmdreg |= CMD_COLOR_32; |
|
796 break; |
|
797 } |
|
798 |
|
799 if (!ast_store_mmio(MMIOREG_DST_PITCH, |
|
800 (ast_info.ast_linesize << 16) | MASK_DST_HEIGHT)) |
|
801 return (0); |
|
802 |
|
803 if (!ast_store_mmio(MMIOREG_FG, fg)) |
|
804 return (0); |
|
805 |
|
806 if (!ast_store_mmio(MMIOREG_DST_BASE, 0)) |
|
807 return (0); |
|
808 |
|
809 if (!ast_store_mmio(MMIOREG_DST_XY, |
|
810 (x1 << 16) | y1)) |
|
811 return (0); |
|
812 |
|
813 if (!ast_store_mmio(MMIOREG_RECT_XY, |
|
814 ((x2 - x1) << 16) | (y2 - y1))) |
|
815 return (0); |
|
816 |
|
817 if (!ast_store_mmio(MMIOREG_CMD, cmdreg)) |
|
818 return (0); |
|
819 |
|
820 return (1); |
|
821 } |
|
822 |
|
823 |
|
824 int |
|
825 ast_fill_pattern_rect( |
|
826 register uint_t const x1, |
|
827 register uint_t const y1, |
|
828 register uint_t const x2, |
|
829 register uint_t const y2, |
|
830 register uint_t const bg, |
|
831 register uint_t const fg, |
|
832 register uint64_t const pat) |
|
833 { |
|
834 register uint_t cmdreg; |
|
835 |
|
836 cmdreg = CMD_BITBLT | CMD_PAT_MONOMASK | 0xf000; |
|
837 switch (ast_info.ast_pixelsize) { |
|
838 case 1: |
|
839 cmdreg |= CMD_COLOR_08; |
|
840 break; |
|
841 case 2: |
|
842 cmdreg |= CMD_COLOR_16; |
|
843 break; |
|
844 case 3: |
|
845 case 4: |
|
846 default: |
|
847 cmdreg |= CMD_COLOR_32; |
|
848 break; |
|
849 } |
|
850 |
|
851 if (!ast_store_mmio(MMIOREG_DST_PITCH, |
|
852 (ast_info.ast_linesize << 16) | MASK_DST_HEIGHT)) |
|
853 return (0); |
|
854 |
|
855 if (!ast_store_mmio(MMIOREG_FG, fg)) |
|
856 return (0); |
|
857 |
|
858 if (!ast_store_mmio(MMIOREG_BG, bg)) |
|
859 return (0); |
|
860 |
|
861 if (!ast_store_mmio(MMIOREG_MONO1, (uint_t)(pat >> 32))) |
|
862 return (0); |
|
863 |
|
864 if (!ast_store_mmio(MMIOREG_MONO2, (uint_t)pat)) |
|
865 return (0); |
|
866 |
|
867 if (!ast_store_mmio(MMIOREG_DST_BASE, 0)) |
|
868 return (0); |
|
869 |
|
870 if (!ast_store_mmio(MMIOREG_DST_XY, |
|
871 (x1 << 16) | y1)) |
|
872 return (0); |
|
873 |
|
874 if (!ast_store_mmio(MMIOREG_RECT_XY, |
|
875 ((x2 - x1) << 16) | (y2 - y1))) |
|
876 return (0); |
|
877 |
|
878 if (!ast_store_mmio(MMIOREG_CMD, cmdreg)) |
|
879 return (0); |
|
880 |
|
881 return (1); |
|
882 } |
|
883 |
|
884 |
|
885 int |
|
886 ast_draw_solid_line( |
|
887 register uint_t const x1, |
|
888 register uint_t const y1, |
|
889 register uint_t const x2, |
|
890 register uint_t const y2, |
|
891 register uint_t const fg) |
|
892 { |
|
893 register uint_t cmdreg; |
|
894 register uint_t GAbsX; |
|
895 register uint_t GAbsY; |
|
896 register uint_t MM; |
|
897 register uint_t mm; |
|
898 register int err; |
|
899 register int k1; |
|
900 register int k2; |
|
901 register int xm; |
|
902 |
|
903 cmdreg = 0xf000 | CMD_LINEDRAW | CMD_ENABLE_CLIP | |
|
904 CMD_NOT_DRAW_LAST_PIXEL; |
|
905 switch (ast_info.ast_pixelsize) { |
|
906 case 1: |
|
907 cmdreg |= CMD_COLOR_08; |
|
908 break; |
|
909 case 2: |
|
910 cmdreg |= CMD_COLOR_16; |
|
911 break; |
|
912 case 3: |
|
913 case 4: |
|
914 default: |
|
915 cmdreg |= CMD_COLOR_32; |
|
916 break; |
|
917 } |
|
918 |
|
919 if (x1 < x2) |
|
920 GAbsX = x2 - x1; |
|
921 else |
|
922 GAbsX = x1 - x2; |
|
923 |
|
924 if (y1 < y2) |
|
925 GAbsY = y2 - y1; |
|
926 else |
|
927 GAbsY = y1 - y2; |
|
928 |
|
929 if (GAbsX >= GAbsY) { |
|
930 MM = GAbsX; |
|
931 mm = GAbsY; |
|
932 xm = 1; |
|
933 } else { |
|
934 MM = GAbsY; |
|
935 mm = GAbsX; |
|
936 xm = 0; |
|
937 } |
|
938 |
|
939 if (x1 >= x2) |
|
940 cmdreg |= CMD_X_DEC; |
|
941 |
|
942 if (y1 >= y2) |
|
943 cmdreg |= CMD_Y_DEC; |
|
944 |
|
945 err = (int)(2 * mm) - (int)MM; |
|
946 k1 = 2 * mm; |
|
947 k2 = (int)(2 * mm) - (int)(2 * MM); |
|
948 |
|
949 if (!ast_store_mmio(MMIOREG_DST_BASE, 0)) |
|
950 return (0); |
|
951 |
|
952 if (!ast_store_mmio(MMIOREG_DST_PITCH, |
|
953 (ast_info.ast_linesize << 16) | MASK_DST_HEIGHT)) |
|
954 return (0); |
|
955 |
|
956 if (!ast_store_mmio(MMIOREG_FG, fg)) |
|
957 return (0); |
|
958 |
|
959 if (!ast_store_mmio(MMIOREG_LINE_XY, |
|
960 (x1 << 16) | y1)) |
|
961 return (0); |
|
962 |
|
963 if (!ast_store_mmio(MMIOREG_LINE_ERR, |
|
964 (xm << 24) | (err & MASK_LINE_ERR))) |
|
965 return (0); |
|
966 |
|
967 if (!ast_store_mmio(MMIOREG_LINE_WIDTH, |
|
968 (MM & MASK_LINE_WIDTH) << 16)) |
|
969 return (0); |
|
970 |
|
971 if (!ast_store_mmio(MMIOREG_LINE_K1, |
|
972 (k1 & MASK_LINE_K1))) |
|
973 return (0); |
|
974 |
|
975 if (!ast_store_mmio(MMIOREG_LINE_K2, |
|
976 (k2 & MASK_LINE_K2))) |
|
977 return (0); |
|
978 |
|
979 if (!ast_store_mmio(MMIOREG_CMD, cmdreg)) |
|
980 return (0); |
|
981 |
|
982 return (1); |
|
983 } |
|
984 |
|
985 int |
|
986 ast_unmap_mem( |
|
987 register return_packet *const rp, |
|
988 register int const test) |
|
989 { |
|
990 if (ast_unmap_fb() != 0) { |
|
991 gfx_vts_set_message(rp, 1, test, "unmap framebuffer failed"); |
|
992 return (-1); |
|
993 } |
|
994 |
|
995 if (ast_unmap_mmio() != 0) { |
|
996 gfx_vts_set_message(rp, 1, test, "unmap MMIO failed"); |
|
997 return (-1); |
|
998 } |
|
999 |
|
1000 return (0); |
|
1001 } |
|
1002 |
|
1003 |
|
1004 int |
|
1005 ast_unmap_fb( |
|
1006 void) |
|
1007 { |
|
1008 register int status; |
|
1009 |
|
1010 if (ast_info.ast_fb_ptr == NULL) |
|
1011 return (0); |
|
1012 |
|
1013 status = munmap((char *)ast_info.ast_fb_ptr, ast_info.ast_fb_size); |
|
1014 ast_info.ast_fb_ptr = NULL; |
|
1015 |
|
1016 return (status); |
|
1017 } |
|
1018 |
|
1019 |
|
1020 int |
|
1021 ast_unmap_mmio( |
|
1022 void) |
|
1023 { |
|
1024 register int status; |
|
1025 |
|
1026 if (ast_info.ast_mmio_ptr == NULL) |
|
1027 return (0); |
|
1028 |
|
1029 status = munmap((char *)ast_info.ast_mmio_ptr, |
|
1030 ast_info.ast_mmio_size); |
|
1031 ast_info.ast_mmio_ptr = NULL; |
|
1032 |
|
1033 return (status); |
|
1034 } |
|
1035 |
|
1036 |
|
1037 |
|
1038 int |
|
1039 ast_store_mmio( |
|
1040 register uint_t const port, |
|
1041 register uint_t const value) |
|
1042 { |
|
1043 register uint_t readvalue; |
|
1044 register hrtime_t starttime; |
|
1045 register hrtime_t curtime; |
|
1046 register hrtime_t endtime; |
|
1047 register ulong_t count = 0; |
|
1048 |
|
1049 ast_mmio_write32(port, value); |
|
1050 readvalue = ast_mmio_read32(port); |
|
1051 |
|
1052 if (readvalue == value) |
|
1053 return (1); |
|
1054 |
|
1055 starttime = gethrtime(); |
|
1056 endtime = starttime + ast_loop_time; |
|
1057 |
|
1058 do { |
|
1059 count++; |
|
1060 ast_mmio_write32(port, value); |
|
1061 readvalue = ast_mmio_read32(port); |
|
1062 |
|
1063 if (readvalue == value) |
|
1064 return (1); |
|
1065 curtime = gethrtime(); |
|
1066 } while (curtime < endtime); |
|
1067 |
|
1068 ast_mmio_write32(port, value); |
|
1069 readvalue = ast_mmio_read32(port); |
|
1070 |
|
1071 if (readvalue == value) |
|
1072 return (1); |
|
1073 |
|
1074 return (0); |
|
1075 } |
|
1076 |
|
1077 int |
|
1078 ast_get_index_reg( |
|
1079 register uchar_t *const valueptr, |
|
1080 register uchar_t const offset, |
|
1081 register uchar_t const index) |
|
1082 { |
|
1083 if (ast_set_reg(offset, index) != 0) |
|
1084 return (-1); |
|
1085 |
|
1086 if (ast_get_reg(valueptr, offset + 1) != 0) |
|
1087 return (-1); |
|
1088 |
|
1089 return (0); |
|
1090 } |
|
1091 |
|
1092 |
|
1093 int |
|
1094 ast_set_index_reg( |
|
1095 register uchar_t const offset, |
|
1096 register uchar_t const index, |
|
1097 register uchar_t const value) |
|
1098 { |
|
1099 if (ast_set_reg(offset, index) != 0) |
|
1100 return (-1); |
|
1101 |
|
1102 if (ast_set_reg(offset + 1, value) != 0) |
|
1103 return (-1); |
|
1104 |
|
1105 return (0); |
|
1106 } |
|
1107 |
|
1108 |
|
1109 int |
|
1110 ast_get_reg( |
|
1111 register uchar_t *const valueptr, |
|
1112 register uchar_t const offset) |
|
1113 { |
|
1114 ast_io_reg io_reg; |
|
1115 |
|
1116 io_reg.offset = offset; |
|
1117 io_reg.value = (uchar_t)-1; |
|
1118 |
|
1119 if (ioctl(ast_info.ast_fd, AST_GET_IO_REG, &io_reg) != 0) |
|
1120 return (-1); |
|
1121 |
|
1122 *valueptr = io_reg.value; |
|
1123 return (0); |
|
1124 } |
|
1125 |
|
1126 |
|
1127 int |
|
1128 ast_set_reg( |
|
1129 register uchar_t const offset, |
|
1130 register uchar_t const value) |
|
1131 { |
|
1132 ast_io_reg io_reg; |
|
1133 |
|
1134 io_reg.offset = offset; |
|
1135 io_reg.value = value; |
|
1136 |
|
1137 if (ioctl(ast_info.ast_fd, AST_SET_IO_REG, &io_reg) != 0) |
|
1138 return (-1); |
|
1139 |
|
1140 return (0); |
|
1141 } |
|
1142 |
|
1143 |
|
1144 uint_t |
|
1145 ast_mmio_read32( |
|
1146 register uint_t const port) |
|
1147 { |
|
1148 register uint_t volatile const *const addr = |
|
1149 (uint_t volatile const *) (ast_info.ast_mmio_ptr + port); |
|
1150 register uint_t value; |
|
1151 |
|
1152 union { |
|
1153 uint_t l; |
|
1154 ushort_t w[2]; |
|
1155 uchar_t b[4]; |
|
1156 } data; |
|
1157 |
|
1158 data.l = *addr; |
|
1159 |
|
1160 switch (ast_info.ast_endian) { |
|
1161 case 0: /* little endian */ |
|
1162 value = ((uint_t)data.b[3] << 24) | |
|
1163 ((uint_t)data.b[2] << 16) | |
|
1164 ((uint_t)data.b[1] << 8) | |
|
1165 (uint_t)data.b[0]; |
|
1166 break; |
|
1167 |
|
1168 case 1: /* big endian 16 */ |
|
1169 case 2: /* big endian 32 */ |
|
1170 value = ((uint_t)data.b[0] << 24) | |
|
1171 ((uint_t)data.b[1] << 16) | |
|
1172 ((uint_t)data.b[2] << 8) | |
|
1173 (uint_t)data.b[3]; |
|
1174 break; |
|
1175 } |
|
1176 |
|
1177 return (value); |
|
1178 } |
|
1179 |
|
1180 |
|
1181 |
|
1182 void |
|
1183 ast_mmio_write32( |
|
1184 register uint_t const port, |
|
1185 register uint_t const val) |
|
1186 { |
|
1187 register uint_t volatile *const addr = |
|
1188 (uint_t volatile *) (ast_info.ast_mmio_ptr + port); |
|
1189 register uint_t value; |
|
1190 |
|
1191 union { |
|
1192 uint_t l; |
|
1193 ushort_t w[2]; |
|
1194 uchar_t b[4]; |
|
1195 } data; |
|
1196 |
|
1197 data.l = val; |
|
1198 |
|
1199 switch (ast_info.ast_endian) { |
|
1200 case 0: /* little endian */ |
|
1201 value = ((uint_t)data.b[3] << 24) | |
|
1202 ((uint_t)data.b[2] << 16) | |
|
1203 ((uint_t)data.b[1] << 8) | |
|
1204 (uint_t)data.b[0]; |
|
1205 break; |
|
1206 |
|
1207 case 1: /* big endian 16 */ |
|
1208 case 2: /* big endian 32 */ |
|
1209 value = ((uint_t)data.b[0] << 24) | |
|
1210 ((uint_t)data.b[1] << 16) | |
|
1211 ((uint_t)data.b[2] << 8) | |
|
1212 (uint_t)data.b[3]; |
|
1213 break; |
|
1214 } |
|
1215 |
|
1216 *addr = value; |
|
1217 } |
|
1218 |
|
1219 |
|
1220 int |
|
1221 ast_wait_idle( |
|
1222 void) |
|
1223 { |
|
1224 register hrtime_t starttime; |
|
1225 register hrtime_t curtime; |
|
1226 register hrtime_t endtime; |
|
1227 register ulong_t count = 0; |
|
1228 |
|
1229 if (!(ast_mmio_read32(MMIOREG_STAT) & STAT_BUSY)) |
|
1230 return (1); |
|
1231 |
|
1232 starttime = gethrtime(); |
|
1233 endtime = starttime + ast_loop_time; |
|
1234 |
|
1235 do { |
|
1236 count++; |
|
1237 if (!(ast_mmio_read32(MMIOREG_STAT) & STAT_BUSY)) |
|
1238 return (1); |
|
1239 curtime = gethrtime(); |
|
1240 } while (curtime < endtime); |
|
1241 |
|
1242 if (!(ast_mmio_read32(MMIOREG_STAT) & STAT_BUSY)) |
|
1243 return (1); |
|
1244 |
|
1245 return (0); |
|
1246 } |