/*

 * CDDL HEADER START

 *

 * The contents of this file are subject to the terms of the

 * Common Development and Distribution License (the "License").

 * You may not use this file except in compliance with the License.

 *

 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

 * or http://www.opensolaris.org/os/licensing.

 * See the License for the specific language governing permissions

 * and limitations under the License.

 *

 * When distributing Covered Code, include this CDDL HEADER in each

 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.

 * If applicable, add the following below this CDDL HEADER, with the

 * fields enclosed by brackets "[]" replaced with your own identifying

 * information: Portions Copyright [yyyy] [name of copyright owner]

 *

 * CDDL HEADER END

 */

/*

 */

#include <qlge.h>

#include <sys/atomic.h>

#include <sys/strsubr.h>

#include <sys/pattr.h>

#include <netinet/in.h>

#include <netinet/ip.h>

#include <netinet/ip6.h>

#include <netinet/tcp.h>

#include <netinet/udp.h>

#include <inet/ip.h>

/*

 * Local variables

 */

static struct ether_addr ql_ether_broadcast_addr =

	{0xff, 0xff, 0xff, 0xff, 0xff, 0xff};

/*

 * Local function prototypes

 */

static void ql_fini_kstats(qlge_t *);

static uint32_t ql_get_link_state(qlge_t *);

static void ql_read_conf(qlge_t *);

static int ql_alloc_phys(dev_info_t *, ddi_dma_handle_t *,

    ddi_device_acc_attr_t *, uint_t, ddi_acc_handle_t *,

    size_t, size_t, caddr_t *, ddi_dma_cookie_t *);

static void ql_free_phys(ddi_dma_handle_t *, ddi_acc_handle_t *);

static int ql_set_routing_reg(qlge_t *, uint32_t, uint32_t, int);

static int ql_route_initialize(qlge_t *);

static int ql_attach(dev_info_t *, ddi_attach_cmd_t);

static int ql_detach(dev_info_t *, ddi_detach_cmd_t);

static int ql_bringdown_adapter(qlge_t *);

static int ql_bringup_adapter(qlge_t *);

static int ql_asic_reset(qlge_t *);

static void ql_wake_mpi_reset_soft_intr(qlge_t *);

static void ql_stop_timer(qlge_t *qlge);

/*

 * TX dma maping handlers allow multiple sscatter-gather lists

 */

ddi_dma_attr_t  tx_mapping_dma_attr = {

	DMA_ATTR_V0,			/* dma_attr_version */

	QL_DMA_LOW_ADDRESS,		/* low DMA address range */

	QL_DMA_HIGH_64BIT_ADDRESS,	/* high DMA address range */

	QL_DMA_XFER_COUNTER,		/* DMA counter register */

	QL_DMA_ADDRESS_ALIGNMENT,	/* DMA address alignment, default - 8 */

	QL_DMA_BURSTSIZES,		/* DMA burstsizes */

	QL_DMA_MIN_XFER_SIZE,		/* min effective DMA size */

	QL_DMA_MAX_XFER_SIZE,		/* max DMA xfer size */

	QL_DMA_SEGMENT_BOUNDARY,	/* segment boundary */

	QL_MAX_TX_DMA_HANDLES,		/* s/g list length */

	QL_DMA_GRANULARITY,		/* granularity of device */

};

/*

 * Receive buffers and Request/Response queues do not allow scatter-gather lists

 */

ddi_dma_attr_t  dma_attr = {

	DMA_ATTR_V0,			/* dma_attr_version */

	QL_DMA_LOW_ADDRESS,		/* low DMA address range */

	QL_DMA_HIGH_64BIT_ADDRESS,	/* high DMA address range */

	QL_DMA_XFER_COUNTER,		/* DMA counter register */

	QL_DMA_ADDRESS_ALIGNMENT,	/* DMA address alignment, default - 8 */

	QL_DMA_BURSTSIZES,		/* DMA burstsizes */

	QL_DMA_MIN_XFER_SIZE,		/* min effective DMA size */

	QL_DMA_MAX_XFER_SIZE,		/* max DMA xfer size */

	QL_DMA_SEGMENT_BOUNDARY,	/* segment boundary */

	1,				/* s/g list length, i.e no sg list */

	QL_DMA_GRANULARITY,		/* granularity of device */

	QL_DMA_XFER_FLAGS		/* DMA transfer flags */

};

/*

 * DMA access attribute structure.

 */

/* device register access from host */

ddi_device_acc_attr_t ql_dev_acc_attr = {

	DDI_DEVICE_ATTR_V0,

	DDI_STRUCTURE_LE_ACC,

	DDI_STRICTORDER_ACC

};

/* host ring descriptors */

ddi_device_acc_attr_t ql_desc_acc_attr = {

	DDI_DEVICE_ATTR_V0,

	DDI_NEVERSWAP_ACC,

	DDI_STRICTORDER_ACC

};

/* host ring buffer */

ddi_device_acc_attr_t ql_buf_acc_attr = {

	DDI_DEVICE_ATTR_V0,

	DDI_NEVERSWAP_ACC,

	DDI_STRICTORDER_ACC

};

/*

 * Hash key table for Receive Side Scaling (RSS) support

 */

const uint8_t key_data[] = {

	0x23, 0x64, 0xa1, 0xaa, 0x37, 0xc0, 0xed, 0x05, 0x2b, 0x36,

	0x50, 0x5c, 0x45, 0x1e, 0x7e, 0xc8, 0x5d, 0x2a, 0x54, 0x2f,

	0xe4, 0x3d, 0x0f, 0xbb, 0x91, 0xd9, 0x25, 0x60, 0xd4, 0xf8,

	0x12, 0xa0, 0x59, 0x4b, 0x9e, 0x8a, 0x51, 0xda, 0xcd, 0x49};

/*

 * Shadow Registers:

 * Outbound queues have a consumer index that is maintained by the chip.

 * Inbound queues have a producer index that is maintained by the chip.

 * For lower overhead, these registers are "shadowed" to host memory

 * which allows the device driver to track the queue progress without

 * PCI reads. When an entry is placed on an inbound queue, the chip will

 * update the relevant index register and then copy the value to the

 * shadow register in host memory.

 */

static inline unsigned int

}

/*

 * Read 32 bit atomically

 */

uint32_t

ql_atomic_read_32(volatile uint32_t *target)

{

	/*

	 * atomic_add_32_nv returns the new value after the add,

	 * we are adding 0 so we should get the original value

	 */

	return (atomic_add_32_nv(target, 0));

}

/*

 * Set 32 bit atomically

 */

void

ql_atomic_set_32(volatile uint32_t *target, uint32_t newval)

{

	(void) atomic_swap_32(target, newval);

}

/*

 * Setup device PCI configuration registers.

 * Kernel context.

 */

static void

ql_pci_config(qlge_t *qlge)

{

	uint16_t w;

	qlge->vendor_id = (uint16_t)pci_config_get16(qlge->pci_handle,

	    PCI_CONF_VENID);

	qlge->device_id = (uint16_t)pci_config_get16(qlge->pci_handle,

	    PCI_CONF_DEVID);

	/*

	 * we want to respect framework's setting of PCI

	 * configuration space command register and also

	 * want to make sure that all bits of interest to us

	 * are properly set in PCI Command register(0x04).

	 * PCI_COMM_IO		0x1	 I/O access enable

	 * PCI_COMM_MAE		0x2	 Memory access enable

	 * PCI_COMM_ME		0x4	 bus master enable

	 * PCI_COMM_MEMWR_INVAL	0x10	 memory write and invalidate enable.

	 */

	w = (uint16_t)pci_config_get16(qlge->pci_handle, PCI_CONF_COMM);

	w = (uint16_t)(w & (~PCI_COMM_IO));

	w = (uint16_t)(w | PCI_COMM_MAE | PCI_COMM_ME |

	    /* PCI_COMM_MEMWR_INVAL | */

	    PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE);

	pci_config_put16(qlge->pci_handle, PCI_CONF_COMM, w);

	ql_dump_pci_config(qlge);

}

/*

 * This routine parforms the neccessary steps to set GLD mac information

 * such as Function number, xgmac mask and shift bits

 */

static int

ql_set_mac_info(qlge_t *qlge)

{

	uint32_t value;

	uint32_t fn0_net, fn1_net;

	/* set default value */

	qlge->fn0_net = FN0_NET;

	qlge->fn1_net = FN1_NET;

	if (ql_read_processor_data(qlge, MPI_REG, &value) != DDI_SUCCESS) {

		cmn_err(CE_WARN, "%s(%d) read MPI register failed",

		    __func__, qlge->instance);

	} else {

		fn0_net = (value >> 1) & 0x07;

		fn1_net = (value >> 5) & 0x07;

		if ((fn0_net > 4) || (fn1_net > 4) || (fn0_net == fn1_net)) {

			cmn_err(CE_WARN, "%s(%d) bad mpi register value %x, \n"

			    "nic0 function number %d,"

			    "nic1 function number %d "

			    "use default\n",

			    __func__, qlge->instance, value, fn0_net, fn1_net);

		} else {

			qlge->fn0_net = fn0_net;

			qlge->fn1_net = fn1_net;

		}

	}

	/* Get the function number that the driver is associated with */

	value = ql_read_reg(qlge, REG_STATUS);

	qlge->func_number = (uint8_t)((value >> 6) & 0x03);

	QL_PRINT(DBG_INIT, ("status register is:%x, func_number: %d\n",

	    value, qlge->func_number));

	/* The driver is loaded on a non-NIC function? */

	if ((qlge->func_number != qlge->fn0_net) &&

	    (qlge->func_number != qlge->fn1_net)) {

		cmn_err(CE_WARN,

		    "Invalid function number = 0x%x\n", qlge->func_number);

	}

	/* network port 0? */

	if (qlge->func_number == qlge->fn0_net) {

		qlge->xgmac_sem_mask = QL_PORT0_XGMAC_SEM_MASK;

		qlge->xgmac_sem_bits = QL_PORT0_XGMAC_SEM_BITS;

	} else {

		qlge->xgmac_sem_mask = QL_PORT1_XGMAC_SEM_MASK;

		qlge->xgmac_sem_bits = QL_PORT1_XGMAC_SEM_BITS;

	}

	return (rval);

}

/*

 * write to doorbell register

 */

void

ql_write_doorbell_reg(qlge_t *qlge, uint32_t *addr, uint32_t data)

{

	ddi_put32(qlge->dev_doorbell_reg_handle, addr, data);

}

/*

 * read from doorbell register

 */

uint32_t

ql_read_doorbell_reg(qlge_t *qlge, uint32_t *addr)

{

	uint32_t ret;

	ret = ddi_get32(qlge->dev_doorbell_reg_handle, addr);

	return	(ret);

}

/*

 * This function waits for a specific bit to come ready

 * in a given register.  It is used mostly by the initialize

 * process, but is also used in kernel thread API such as

 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.

 */

static int

ql_wait_reg_rdy(qlge_t *qlge, uint32_t reg, uint32_t bit, uint32_t err_bit)

{

	uint32_t temp;

	int count = UDELAY_COUNT;

	while (count) {

		temp = ql_read_reg(qlge, reg);

		/* check for errors */

		if ((temp & err_bit) != 0) {

			break;

		} else if ((temp & bit) != 0)

			return (DDI_SUCCESS);

		qlge_delay(UDELAY_DELAY);

		count--;

	}

	cmn_err(CE_WARN,

	    "Waiting for reg %x to come ready failed.", reg);

	return (DDI_FAILURE);

}

/*

 * The CFG register is used to download TX and RX control blocks

 * to the chip. This function waits for an operation to complete.

 */

static int

ql_wait_cfg(qlge_t *qlge, uint32_t bit)

{

}

/*

 * Used to issue init control blocks to hw. Maps control block,

 * sets address, triggers download, waits for completion.

 */

static int

ql_write_cfg(qlge_t *qlge, uint32_t bit, uint64_t phy_addr, uint16_t q_id)

{

	int status = DDI_SUCCESS;

	uint32_t mask;

	uint32_t value;

	status = ql_sem_spinlock(qlge, SEM_ICB_MASK);

	if (status != DDI_SUCCESS) {

		goto exit;

	}

	status = ql_wait_cfg(qlge, bit);

	if (status != DDI_SUCCESS) {

		goto exit;

	}

	ql_write_reg(qlge, REG_ICB_ACCESS_ADDRESS_LOWER, LS_64BITS(phy_addr));

	ql_write_reg(qlge, REG_ICB_ACCESS_ADDRESS_UPPER, MS_64BITS(phy_addr));

	mask = CFG_Q_MASK | (bit << 16);

	value = bit | (q_id << CFG_Q_SHIFT);

	ql_write_reg(qlge, REG_CONFIGURATION, (mask | value));

	/*

	 * Wait for the bit to clear after signaling hw.

	 */

	status = ql_wait_cfg(qlge, bit);

	ql_sem_unlock(qlge, SEM_ICB_MASK); /* does flush too */

exit:

	return (status);

}

/*

 * Initialize adapter instance

 */

static int

ql_init_instance(qlge_t *qlge)

{

	int i;

	/* Default value */

	qlge->mac_flags = QL_MAC_INIT;

	qlge->mtu = ETHERMTU;		/* set normal size as default */

	qlge->page_size = VM_PAGE_SIZE;	/* default page size */

	for (i = 0; i < MAX_RX_RINGS; i++) {

		qlge->rx_polls[i] = 0;

		qlge->rx_interrupts[i] = 0;

	}

	/*

	 * Set up the operating parameters.

	 */

	qlge->multicast_list_count = 0;

	/*

	 * Set up the max number of unicast list

	 */

	qlge->unicst_total = MAX_UNICAST_LIST_SIZE;

	qlge->unicst_avail = MAX_UNICAST_LIST_SIZE;

	/*

	 * read user defined properties in .conf file

	 */

	ql_read_conf(qlge); /* mtu, pause, LSO etc */

	QL_PRINT(DBG_INIT, ("mtu is %d \n", qlge->mtu));

	/* choose Memory Space mapping and get Vendor Id, Device ID etc */

	ql_pci_config(qlge);

	qlge->ip_hdr_offset = 0;

	if (qlge->device_id == 0x8000) {

		/* Schultz card */

		qlge->cfg_flags |= CFG_CHIP_8100;

		/* enable just ipv4 chksum offload for Schultz */

		qlge->cfg_flags |= CFG_CKSUM_FULL_IPv4;

		/*

		 * Schultz firmware does not do pseduo IP header checksum

		 * calculation, needed to be done by driver

		 */

		qlge->cfg_flags |= CFG_HW_UNABLE_PSEUDO_HDR_CKSUM;

		if (qlge->lso_enable)

			qlge->cfg_flags |= CFG_LSO;

		qlge->cfg_flags |= CFG_SUPPORT_SCATTER_GATHER;

		/* Schultz must split packet header */

		qlge->cfg_flags |= CFG_ENABLE_SPLIT_HEADER;

		qlge->max_read_mbx = 5;

		qlge->ip_hdr_offset = 2;

	}

	/* Set Function Number and some of the iocb mac information */

	if (ql_set_mac_info(qlge) != DDI_SUCCESS)

		return (DDI_FAILURE);

	/* Read network settings from NVRAM */

	/* After nvram is read successfully, update dev_addr */

	if (ql_get_flash_params(qlge) == DDI_SUCCESS) {

		QL_PRINT(DBG_INIT, ("mac%d address is \n", qlge->func_number));

		for (i = 0; i < ETHERADDRL; i++) {

			qlge->dev_addr.ether_addr_octet[i] =

			    qlge->nic_config.factory_MAC[i];

		}

	} else {

		cmn_err(CE_WARN, "%s(%d): Failed to read flash memory",

		    __func__, qlge->instance);

		return (DDI_FAILURE);

	}

	bcopy(qlge->dev_addr.ether_addr_octet,

	    qlge->unicst_addr[0].addr.ether_addr_octet,

	    ETHERADDRL);

	QL_DUMP(DBG_INIT, "\t flash mac address dump:\n",

	    &qlge->dev_addr.ether_addr_octet[0], 8, ETHERADDRL);

	qlge->port_link_state = LS_DOWN;

	return (DDI_SUCCESS);

}

/*

 * This hardware semaphore provides the mechanism for exclusive access to

 * resources shared between the NIC driver, MPI firmware,

 * FCOE firmware and the FC driver.

 */

static int

ql_sem_trylock(qlge_t *qlge, uint32_t sem_mask)

{

	uint32_t sem_bits = 0;

	switch (sem_mask) {

	case SEM_XGMAC0_MASK:

		sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;

		break;

	case SEM_XGMAC1_MASK:

		sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;

		break;

	case SEM_ICB_MASK:

		sem_bits = SEM_SET << SEM_ICB_SHIFT;