/*

 * CDDL HEADER START

 *

 * The contents of this file are subject to the terms of the

 * Common Development and Distribution License (the "License").

 * You may not use this file except in compliance with the License.

 *

 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

 * or http://www.opensolaris.org/os/licensing.

 * See the License for the specific language governing permissions

 * and limitations under the License.

 *

 * When distributing Covered Code, include this CDDL HEADER in each

 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.

 * If applicable, add the following below this CDDL HEADER, with the

 * fields enclosed by brackets "[]" replaced with your own identifying

 * information: Portions Copyright [yyyy] [name of copyright owner]

 *

 * CDDL HEADER END

 */

/*

 */

#include <qlge.h>

static int ql_async_event_parser(qlge_t *, mbx_data_t *);

/*

 * Wait upto timeout seconds for Processor Interrupt

 * if timeout is 0, then wait for default waittime

 */

static int

ql_poll_processor_intr(qlge_t *qlge, uint8_t timeout)

{

	int rtn_val = DDI_SUCCESS;

	if (ql_wait_reg_bit(qlge, REG_STATUS, STS_PI, BIT_SET, timeout)

	    != DDI_SUCCESS) {

		cmn_err(CE_WARN, "Polling for processor interrupt failed.");

		rtn_val = DDI_FAILURE;

	}

	return (rtn_val);

}

/*

 * Wait for mailbox Processor Register Ready

 */

static int

ql_wait_processor_addr_reg_ready(qlge_t *qlge)

{

	int rtn_val = DDI_SUCCESS;

	if (ql_wait_reg_bit(qlge, REG_PROCESSOR_ADDR,

	    PROCESSOR_ADDRESS_RDY, BIT_SET, 0) != DDI_SUCCESS) {

		cmn_err(CE_WARN,

		    "Wait for processor address register ready timeout.");

		rtn_val = DDI_FAILURE;

	}

	return (rtn_val);

}

/*

 * Read and write MPI registers using the indirect register interface

 * Assume all the locks&semaphore have been acquired

 */

int

ql_write_processor_data(qlge_t *qlge, uint32_t addr, uint32_t data)

{

	int rtn_val = DDI_FAILURE;

	/* wait for processor address register ready */

	if (ql_wait_processor_addr_reg_ready(qlge) == DDI_FAILURE)

		goto out;

	/* write the data to the data reg */

	ql_write_reg(qlge, REG_PROCESSOR_DATA, data);

	/* trigger the write */

	ql_write_reg(qlge, REG_PROCESSOR_ADDR, addr);

	/* wait for register to come ready */

	if (ql_wait_processor_addr_reg_ready(qlge) == DDI_FAILURE)

		goto out;

	rtn_val = DDI_SUCCESS;

out:

	return (rtn_val);

}

/*

 * Read from processor register

 */

int

ql_read_processor_data(qlge_t *qlge, uint32_t addr, uint32_t *data)

{

	int rtn_val = DDI_FAILURE;

	/* enable read operation */

	addr |= PROCESSOR_ADDRESS_READ;

	/* wait for processor address register ready */

	if (ql_wait_processor_addr_reg_ready(qlge) == DDI_FAILURE)

		goto out;

	/* Write read address, wait for data ready in Data register */

	ql_write_reg(qlge, REG_PROCESSOR_ADDR, addr);

	/* wait for data ready */

	if (ql_wait_processor_addr_reg_ready(qlge) == DDI_FAILURE)

		goto out;

	/* read data */

	*data = ql_read_reg(qlge, REG_PROCESSOR_DATA);

	rtn_val = DDI_SUCCESS;

out:

	return (rtn_val);

}

/*

 * Read "count" number of outgoing Mailbox register starting

 * from mailbox #0 if count is 0 then read all mailboxes

 */

static int

ql_read_mailbox_cmd(qlge_t *qlge, mbx_data_t *mbx_buf, uint32_t count)

{

	int rtn_val = DDI_FAILURE;

	uint32_t reg_status;

	uint32_t addr;

	int i;

	if (ql_sem_spinlock(qlge, QL_PROCESSOR_SEM_MASK) != DDI_SUCCESS) {

		cmn_err(CE_WARN,

		    "%s(%d) get QL_PROCESSOR_SEM_MASK time out error",

		    __func__, qlge->instance);

		return (DDI_FAILURE);

	}

	if (qlge->func_number == qlge->fn0_net)

		addr = FUNC_0_OUT_MAILBOX_0_REG_OFFSET;

	else

		addr = FUNC_1_OUT_MAILBOX_0_REG_OFFSET;

	if (count == 0)

		count = NUM_MAILBOX_REGS;

	for (i = 0; i < count; i++) {

		if (ql_read_processor_data(qlge, addr, &reg_status)

		    == DDI_FAILURE)

			goto out;

		QL_PRINT(DBG_MBX, ("%s(%d) mailbox %d value 0x%x\n",

		    __func__, qlge->instance, i, reg_status));

		mbx_buf->mb[i] = reg_status;

		addr ++;

	}

	rtn_val = DDI_SUCCESS;

out:

	ql_sem_unlock(qlge, QL_PROCESSOR_SEM_MASK);

	return (rtn_val);

}

/*

 * Write mail box command (upto 16) to MPI Firmware

 */

int

ql_issue_mailbox_cmd(qlge_t *qlge, mbx_cmd_t *mbx_cmd)

{

	int rtn_val = DDI_FAILURE;

	uint32_t addr;

	int i;

	/*

	 * Get semaphore to access Processor Address and

	 * Processor Data Registers

	 */

	if (ql_sem_spinlock(qlge, QL_PROCESSOR_SEM_MASK) != DDI_SUCCESS) {

		return (DDI_FAILURE);

	}

	/* ensure no overwriting current command */

	if (ql_wait_reg_bit(qlge, REG_HOST_CMD_STATUS,

	    HOST_TO_MPI_INTR_NOT_DONE, BIT_RESET, 0) != DDI_SUCCESS) {

		goto out;

	}

	if (qlge->func_number == qlge->fn0_net)

		addr = FUNC_0_IN_MAILBOX_0_REG_OFFSET;

	else

		addr = FUNC_1_IN_MAILBOX_0_REG_OFFSET;

	/* wait for mailbox registers to be ready to access */

	if (ql_wait_processor_addr_reg_ready(qlge) == DDI_FAILURE)

		goto out;

	/* issue mailbox command one by one */

	for (i = 0; i < NUM_MAILBOX_REGS; i++) {

		/* write sending cmd to mailbox data register */

		ql_write_reg(qlge, REG_PROCESSOR_DATA, mbx_cmd->mb[i]);

		/* write mailbox address to address register */

		ql_write_reg(qlge, REG_PROCESSOR_ADDR, addr);

		QL_PRINT(DBG_MBX, ("%s(%d) write %x to mailbox(%x) addr %x \n",

		    __func__, qlge->instance, mbx_cmd->mb[i], i, addr));

		addr++;

		/*

		 * wait for mailbox cmd to be written before

		 * next write can start

		 */

		if (ql_wait_processor_addr_reg_ready(qlge) == DDI_FAILURE)

			goto out;

	}

	/* inform MPI that new mailbox commands are available */

	ql_write_reg(qlge, REG_HOST_CMD_STATUS, HOST_CMD_SET_RISC_INTR);

	rtn_val = DDI_SUCCESS;

out:

	ql_sem_unlock(qlge, QL_PROCESSOR_SEM_MASK);

	return (rtn_val);

}

/*

 * Send mail box command (upto 16) to MPI Firmware

 * and polling for MPI mailbox completion response when

 * interrupt is not enabled.

 * The MBX_LOCK mutexe should have been held and released

 * externally

 */

int

ql_issue_mailbox_cmd_and_poll_rsp(qlge_t *qlge, mbx_cmd_t *mbx_cmd,

    mbx_data_t *p_results)

{

	int rtn_val = DDI_FAILURE;

	boolean_t done;

	int max_wait;

	if (mbx_cmd == NULL)

		goto err;

	rtn_val = ql_issue_mailbox_cmd(qlge, mbx_cmd);

	if (rtn_val != DDI_SUCCESS) {

		cmn_err(CE_WARN, "%s(%d) ql_issue_mailbox_cmd failed",

		    __func__, qlge->instance);

		goto err;

	}

	done = B_FALSE;

	max_wait = 5; /* wait upto 5 PI interrupt */

	/* delay for the processor interrupt is received */

	while ((done != B_TRUE) && (max_wait--)) {

		/* wait up to 5s for PI interrupt */

		if (ql_poll_processor_intr(qlge, (uint8_t)mbx_cmd->timeout)

		    == DDI_SUCCESS) {

			QL_PRINT(DBG_MBX, ("%s(%d) PI Intr received",

			    __func__, qlge->instance));

			(void) ql_read_mailbox_cmd(qlge, p_results, 0);

			/*

			 * Sometimes, the incoming messages is not what we are

			 * waiting for, ie. async events, then, continue to

			 * wait. If it is the result * of previous mailbox

			 * command, then Done. No matter what, send

			 * HOST_CMD_CLEAR_RISC_TO_HOST_INTR to clear each

			 * PI interrupt

			 */

			if (ql_async_event_parser(qlge, p_results) == B_FALSE) {

				/*

				 * we get what we are waiting for,

				 * clear the interrupt

				 */

				rtn_val = DDI_SUCCESS;

				done = B_TRUE;

			} else {

				/*EMPTY*/

				QL_PRINT(DBG_MBX,

				    ("%s(%d) result ignored, not we wait for\n",

				    __func__, qlge->instance));

			}

			ql_write_reg(qlge, REG_HOST_CMD_STATUS,

			    HOST_CMD_CLEAR_RISC_TO_HOST_INTR);

		} else { /* timeout */

			done = B_TRUE;

		}

		rtn_val = DDI_SUCCESS;

	}

err:

	return (rtn_val);

}

/*

 * Send mail box command (upto 16) to MPI Firmware

 * and wait for MPI mailbox completion response which

 * is saved in interrupt. Thus, this function can only

 * be used after interrupt is enabled.

 * Must hold MBX mutex before calling this function

 */

static int

ql_issue_mailbox_cmd_and_wait_rsp(qlge_t *qlge, mbx_cmd_t *mbx_cmd)

{

	int rtn_val = DDI_FAILURE;

	clock_t timer;

	int i;

	int done = 0;

	if (mbx_cmd == NULL)

		goto err;

	ASSERT(mutex_owned(&qlge->mbx_mutex));

	/* if interrupts are not enabled, poll when results are available */

	if (!(qlge->flags & INTERRUPTS_ENABLED)) {

		rtn_val = ql_issue_mailbox_cmd_and_poll_rsp(qlge, mbx_cmd,

		    &qlge->received_mbx_cmds);

		if (rtn_val == DDI_SUCCESS) {

			for (i = 0; i < NUM_MAILBOX_REGS; i++)

				mbx_cmd->mb[i] = qlge->received_mbx_cmds.mb[i];

		}

	} else {

		rtn_val = ql_issue_mailbox_cmd(qlge, mbx_cmd);

		if (rtn_val != DDI_SUCCESS) {

			cmn_err(CE_WARN, "%s(%d) ql_issue_mailbox_cmd failed",

			    __func__, qlge->instance);

			goto err;

		}

		qlge->mbx_wait_completion = 1;

		while (!done && qlge->mbx_wait_completion && !ddi_in_panic()) {

			/* default 5 seconds from now to timeout */

			timer = ddi_get_lbolt();

			if (mbx_cmd->timeout) {

				timer +=

				    mbx_cmd->timeout * drv_usectohz(1000000);

			} else {

				timer += 5 * drv_usectohz(1000000);

			}

			if (cv_timedwait(&qlge->cv_mbx_intr, &qlge->mbx_mutex,

			    timer) == -1) {

				/*

				 * The timeout time 'timer' was

				 * reached or expired without the condition

				 * being signaled.

				 */

				cmn_err(CE_WARN, "%s(%d) Wait for Mailbox cmd "

				    "complete timeout.",

				    __func__, qlge->instance);

				rtn_val = DDI_FAILURE;

				done = 1;

			} else {

				QL_PRINT(DBG_MBX,

				    ("%s(%d) mailbox completion signal received"

				    " \n", __func__, qlge->instance));

				for (i = 0; i < NUM_MAILBOX_REGS; i++) {

					mbx_cmd->mb[i] =

					    qlge->received_mbx_cmds.mb[i];

				}

				rtn_val = DDI_SUCCESS;

				done = 1;

			}

		}

	}

err:

	return (rtn_val);

}

/*

 * Inteprete incoming asynchronous events

 */

static int

ql_async_event_parser(qlge_t *qlge, mbx_data_t *mbx_cmds)

{

	uint32_t link_status, cmd;

	uint8_t link_speed;

	uint8_t link_type;

	boolean_t proc_done = B_TRUE;

	mbx_cmd_t reply_cmd = {0};

	switch (mbx_cmds->mb[0]) {

	case MBA_IDC_INTERMEDIATE_COMPLETE /* 1000h */:

		QL_PRINT(DBG_MBX, ("%s(%d):"

		    "MBA_IDC_INTERMEDIATE_COMPLETE received\n",

		    __func__, qlge->instance));

		break;

	case MBA_SYSTEM_ERR /* 8002h */:

		cmn_err(CE_WARN, "%s(%d): MBA_SYSTEM_ERR received",

		    __func__, qlge->instance);

		cmn_err(CE_WARN, "%s(%d): File id %x, Line # %x,"

		    "Firmware Ver# %x",

		    __func__, qlge->instance, mbx_cmds->mb[1],

		    mbx_cmds->mb[2], mbx_cmds->mb[3]);

		(void) ql_8xxx_binary_core_dump(qlge, &qlge->ql_mpi_coredump);

		break;

	case MBA_LINK_UP /* 8011h */:

		QL_PRINT(DBG_MBX, ("%s(%d): MBA_LINK_UP received\n",

		    __func__, qlge->instance));

		link_status = mbx_cmds->mb[1];

		QL_PRINT(DBG_MBX, ("%s(%d): Link Status %x \n",

		    __func__, qlge->instance, link_status));

		link_speed = (uint8_t)((link_status >> 3) & 0x07);

		if (link_speed == 0) {

			qlge->speed = SPEED_100;

			QL_PRINT(DBG_MBX, ("%s(%d):Link speed 100M\n",

			    __func__, qlge->instance));

		} else if (link_speed == 1) {

			qlge->speed = SPEED_1000;

			QL_PRINT(DBG_MBX, ("%s(%d):Link speed 1G\n",

			    __func__, qlge->instance));

		} else if (link_speed == 2) {

			qlge->speed = SPEED_10G;

			QL_PRINT(DBG_MBX, ("%s(%d):Link speed 10G\n",

			    __func__, qlge->instance));

			}

		qlge->link_type = link_type = (uint8_t)(link_status & 0x07);

		if (link_type == XFI_NETWORK_INTERFACE) {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d):Link type XFI_NETWORK_INTERFACE\n",

			    __func__, qlge->instance));

		} else if (link_type == XAUI_NETWORK_INTERFACE) {

			/* EMPTY */

			QL_PRINT(DBG_MBX, ("%s(%d):Link type"

			    "XAUI_NETWORK_INTERFACE\n",

			    __func__, qlge->instance));

		} else if (link_type == XFI_BACKPLANE_INTERFACE) {

			/* EMPTY */

			QL_PRINT(DBG_MBX, ("%s(%d):Link type"

			    "XFI_BACKPLANE_INTERFACE\n",

			    __func__, qlge->instance));

		} else if (link_type == XAUI_BACKPLANE_INTERFACE) {

			/* EMPTY */

			QL_PRINT(DBG_MBX, ("%s(%d):Link type "

			    "XAUI_BACKPLANE_INTERFACE\n",

			    __func__, qlge->instance));

		} else if (link_type == EXT_10GBASE_T_PHY) {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d):Link type EXT_10GBASE_T_PHY\n",

			    __func__, qlge->instance));

		} else if (link_type == EXT_EXT_EDC_PHY) {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d):Link type EXT_EXT_EDC_PHY\n",

			    __func__, qlge->instance));

		} else {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d):unknown Link type \n",

			    __func__, qlge->instance));

		}

		/*

		 * start timer if not started to delay some time then

		 * check if link is really up or down

		 */

		ql_restart_timer(qlge);

		break;

	case MBA_LINK_DOWN /* 8012h */:

		QL_PRINT(DBG_MBX,

		    ("%s(%d): MBA_LINK_DOWN received\n",

		    __func__, qlge->instance));

		link_status = mbx_cmds->mb[1];

		QL_PRINT(DBG_MBX, ("%s(%d): Link Status %x \n",

		    __func__, qlge->instance, link_status));

		if (link_status & 0x1) {

			/* EMPTY */

			QL_PRINT(DBG_MBX, ("%s(%d): Loss of signal \n",

			    __func__, qlge->instance));

		}

		if (link_status & 0x2) {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d): Auto-Negotiation Failed \n",

			    __func__, qlge->instance));

		}

		if (link_status & 0x4) {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d): XTI-Training Failed \n",

			    __func__, qlge->instance));

		}

		ql_restart_timer(qlge);

		break;

	case MBA_IDC_COMPLETE /* 8100h */:

		QL_PRINT(DBG_MBX,

		    ("%s(%d): MBA_IDC_COMPLETE received\n",

		    __func__, qlge->instance));

		cmd = mbx_cmds->mb[1];

		if (cmd == MBC_STOP_FIRMWARE) {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d): STOP_FIRMWARE event completed\n",

			    __func__, qlge->instance));

		} else if (cmd == MBC_IDC_REQUEST) {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d): IDC_REQUEST event completed\n",

			    __func__, qlge->instance));

		} else if (cmd == MBC_PORT_RESET) {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d): PORT_RESET event completed\n",

			    __func__, qlge->instance));

		} else if (cmd == MBC_SET_PORT_CONFIG) {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d): SET_PORT_CONFIG event "

			    "completed\n", __func__, qlge->instance));

		} else {

			/* EMPTY */

			QL_PRINT(DBG_MBX,

			    ("%s(%d): unknown IDC completion request"

			    " event %x %x\n", __func__, qlge->instance,

			    mbx_cmds->mb[1], mbx_cmds->mb[2]));

		}

		proc_done = B_FALSE;

		break;

	case MBA_IDC_REQUEST_NOTIFICATION /* 8101h */:

		QL_PRINT(DBG_MBX,

		    ("%s(%d): MBA_IDC_REQUEST_NOTIFICATION "

		    "received\n", __func__, qlge->instance));

		cmd = mbx_cmds->mb[1];