/*

 * CDDL HEADER START

 *

 * The contents of this file are subject to the terms of the

 * Common Development and Distribution License (the "License").

 * You may not use this file except in compliance with the License.

 *

 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

 * or http://www.opensolaris.org/os/licensing.

 * See the License for the specific language governing permissions

 * and limitations under the License.

 *

 * When distributing Covered Code, include this CDDL HEADER in each

 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.

 * If applicable, add the following below this CDDL HEADER, with the

 * fields enclosed by brackets "[]" replaced with your own identifying

 * information: Portions Copyright [yyyy] [name of copyright owner]

 *

 * CDDL HEADER END

 */

/*

 */

#ifndef _QLGE_H

#define	_QLGE_H

#ifdef __cplusplus

extern "C" {

#endif

#include <sys/ddi.h>

#include <sys/sunddi.h>

#include <sys/sunmdi.h>

#include <sys/modctl.h>

#include <sys/pci.h>

#include <sys/dlpi.h>

#include <sys/sdt.h>

#include <sys/mac_provider.h>

#include <sys/mac.h>

#include <sys/mac_flow.h>

#include <sys/mac_ether.h>

#include <sys/vlan.h>

#include <sys/netlb.h>

#include <sys/kmem.h>

#include <sys/file.h>

#include <sys/proc.h>

#include <sys/callb.h>

#include <sys/disp.h>

#include <sys/strsun.h>

#include <sys/ethernet.h>

#include <sys/miiregs.h>

#include <sys/kstat.h>

#include <sys/byteorder.h>

#include <qlge_hw.h>

#include <qlge_dbg.h>

#include <qlge_open.h>

#define	ADAPTER_NAME		"qlge"

/*

 * Local Macro Definitions.

 */

#ifdef  TRUE

#undef  TRUE

#endif

#define	TRUE	1

#ifdef  FALSE

#undef  FALSE

#endif

#define	FALSE	0

/* #define QLGE_TRACK_BUFFER_USAGE */

/*

 * byte order, sparc is big endian, x86 is little endian,

 * but PCI is little endian only

 */

#ifdef sparc

#define	cpu_to_le64(x)	BSWAP_64(x)

#define	cpu_to_le32(x)	BSWAP_32(x)

#define	cpu_to_le16(x)	BSWAP_16(x)

#define	le64_to_cpu(x)	cpu_to_le64(x)

#define	le32_to_cpu(x)	cpu_to_le32(x)

#define	le16_to_cpu(x)	cpu_to_le16(x)

#else

#define	cpu_to_le64(x)	(x)

#define	cpu_to_le32(x)	(x)

#define	cpu_to_le16(x)	(x)

#define	le64_to_cpu(x)	(x)

#define	le32_to_cpu(x)	(x)

#define	le16_to_cpu(x)	(x)

#endif

/*

 * Macros to help code, maintain, etc.

 */

#define	LSB(x)			(uint8_t)(x)

#define	MSB(x)			(uint8_t)((uint16_t)(x) >> 8)

#define	MSW(x)			(uint16_t)((uint32_t)(x) >> 16)

#define	LSW(x)			(uint16_t)(x)

#define	MS32(x)			(uint32_t)((uint32_t)(x) >> 32)

#define	LS32(x)			(uint32_t)(x)

#define	MSW_LSB(x)		(uint8_t)(LSB(MSW(x)))

#define	MSW_MSB(x)		(uint8_t)(MSB(MSW(x)))

#define	LSD(x)			(uint32_t)(x)

#define	MSD(x)			(uint32_t)((uint64_t)(x) >> 32)

#define	SHORT_TO_LONG(a, b)	(uint32_t)((uint16_t)b << 16 | (uint16_t)a)

#define	CHAR_TO_SHORT(a, b)	(uint16_t)((uint8_t)b << 8 | (uint8_t)a)

#define	SWAP_ENDIAN_16(x)	((LSB(x) << 8) | MSB(x))

#define	SWAP_ENDIAN_32(x)	((SWAP_ENDIAN_16(LSW(x)) << 16) | \

				    SWAP_ENDIAN_16(MSW(x)))

#define	SWAP_ENDIAN_64(x)	((SWAP_ENDIAN_32(LS32(x)) << 32) | \

				    SWAP_ENDIAN_32(MS32(x)))

#define	QL_MIN(x, y)		((x < y) ? x : y)

#define	CARRIER_ON(qlge)	mac_link_update((qlge)->mh, LINK_STATE_UP)

#define	CARRIER_OFF(qlge)	mac_link_update((qlge)->mh, LINK_STATE_DOWN)

/*

 * qlge local function return status codes

 */

#define	QL_ERROR		1

#define	QL_SUCCESS		0

/*

 * Solaris version compatibility definitions.

 */

#define	QL_GET_LBOLT(timer)	timer = ddi_get_lbolt()

#define	QL_DMA_XFER_COUNTER	(uint64_t)0xffffffff

#define	QL_DRIVER_NAME(dip)	ddi_driver_name(ddi_get_parent(dip))

#define	MINOR_NODE_FLAG		8

/*

 * Host adapter default definitions.

 */

/* Timeout timer counts in seconds (must greater than 1 second). */

#define	USEC_PER_TICK		drv_hztousec(1)

#define	TICKS_PER_SEC		drv_usectohz(1000000)

#define	QL_ONE_SEC_DELAY	1000000

#define	QL_ONE_MSEC_DELAY	1000

#define	TX_TIMEOUT		3*TICKS_PER_SEC

/*

 * DMA attributes definitions.

 */

#define	QL_DMA_LOW_ADDRESS		(uint64_t)0

#define	QL_DMA_HIGH_64BIT_ADDRESS	(uint64_t)0xffffffffffffffffull

#define	QL_DMA_HIGH_32BIT_ADDRESS	(uint64_t)0xffffffff

#define	QL_DMA_ADDRESS_ALIGNMENT	(uint64_t)8

#define	QL_DMA_ALIGN_8_BYTE_BOUNDARY	(uint64_t)BIT_3

#define	QL_DMA_RING_ADDRESS_ALIGNMENT	(uint64_t)64

#define	QL_DMA_ALIGN_64_BYTE_BOUNDARY	(uint64_t)BIT_6

#define	QL_DMA_BURSTSIZES		0xfff

#define	QL_DMA_MIN_XFER_SIZE		1

#define	QL_DMA_MAX_XFER_SIZE		(uint64_t)0xffffffff

#define	QL_DMA_SEGMENT_BOUNDARY		(uint64_t)0xffffffff

#define	QL_DMA_GRANULARITY		1

#define	QL_DMA_XFER_FLAGS		0

#define	QL_MAX_COOKIES			16

/*

 * ISP PCI Configuration.

 */

#define	QL_INTR_INTERVAL	128	/* default interrupt interval 128us */

#define	QL_INTR_PKTS		8	/* default packet count threshold 8us */

/* GLD */

#define	QL_STREAM_OPS(dev_ops, attach, detach)	\

	DDI_DEFINE_STREAM_OPS(dev_ops, nulldev, nulldev, attach, detach, \

	    nodev, NULL, D_MP, NULL, ql_quiesce)

#define	QL_GET_DEV(dip)		((qlge_t *)(ddi_get_driver_private(dip)))

#define	RESUME_TX(tx_ring)		mac_tx_update(tx_ring->qlge->mh);

#define	RX_UPSTREAM(rx_ring, mp)	mac_rx(rx_ring->qlge->mh, \

					    rx_ring->qlge->handle, mp);

/* GLD DMA */

extern ddi_device_acc_attr_t ql_dev_acc_attr;

extern ddi_device_acc_attr_t ql_desc_acc_attr;

extern ddi_device_acc_attr_t ql_buf_acc_attr;

struct dma_info {

	void		 *vaddr;

	ddi_dma_handle_t dma_handle;

	ddi_acc_handle_t acc_handle;

	uint64_t	 dma_addr;

	size_t		 mem_len; /* allocated size */

	offset_t	 offset;  /* relative to handle	*/

};

/*

 * Sync a DMA area described by a dma_info

 */

#define	DMA_SYNC(area, flag)	((void) ddi_dma_sync((area).dma_handle,	\

				    (area).offset, (area).mem_len, (flag)))

/*

 * Find the (kernel virtual) address of block of memory

 * described by a dma_info

 */

#define	DMA_VPTR(area)		((area).vaddr)

/*

 * Zero a block of memory described by a dma_info

 */

#define	DMA_ZERO(area)		bzero(DMA_VPTR(area), (area).mem_len)

#define	MAX_SG_ELEMENTS		16

#define	QL_MAX_TX_DMA_HANDLES	MAX_SG_ELEMENTS

#define	TOTAL_SG_ELEMENTS	(MAX_SG_ELEMENTS + TX_DESC_PER_IOCB)

/*

 * ISP PCI Configuration.

 */

/* Initialize steps */

#define	INIT_SOFTSTATE_ALLOC 		BIT_0

#define	INIT_REGS_SETUP			BIT_1

#define	INIT_DOORBELL_REGS_SETUP	BIT_2

#define	INIT_MAC_ALLOC			BIT_3

#define	INIT_PCI_CONFIG_SETUP   	BIT_4

#define	INIT_SETUP_RINGS		BIT_5

#define	INIT_MEMORY_ALLOC		BIT_6

#define	INIT_INTR_ALLOC			BIT_7

#define	INIT_ADD_INTERRUPT		BIT_8

#define	INIT_LOCKS_CREATED		BIT_9

#define	INIT_ADD_SOFT_INTERRUPT		BIT_10

#define	INIT_MUTEX			BIT_11

#define	ADAPTER_INIT			BIT_12

#define	INIT_MAC_REGISTERED		BIT_13

#define	INIT_KSTATS			BIT_14

#define	LS_64BITS(x)	(uint32_t)(0xffffffff & ((uint64_t)x))

#define	MS_64BITS(x)	(uint32_t)(0xffffffff & (((uint64_t)x)>>16>>16))

typedef uint64_t dma_addr_t;

extern int ql_quiesce(dev_info_t *dip);

/*

 * which only has 8 TX OALs, additional OALs must be applied separately.

 */

enum tx_mode_t {

	USE_DMA,

	USE_COPY

};

#define	QL_MAX_COPY_LENGTH	256

#define	MAX_FRAGMENTS_IN_IOCB	7

#ifndef VLAN_ID_MASK

#define	VLAN_ID_MASK		0x0fffu

#endif

#ifndef VLAN_TAGSZ

#define	VLAN_TAGSZ		4

#endif

#ifndef	ETHERTYPE_VLAN

#define	ETHERTYPE_VLAN		0x8100

#endif

#ifndef	MBLKL

#define	MBLKL(mp)	((uintptr_t)(mp)->b_wptr - (uintptr_t)(mp)->b_rptr)

#endif

/*

 * Checksum Offload

 */

#define	TCP_CKSUM_OFFSET	16

#define	UDP_CKSUM_OFFSET	6

#define	IPPROTO_IPv6OVERv4	41

/*

 * Driver must be in one of these states

 */

enum mac_state {

	QL_MAC_INIT,		/* in the initialization stage */

	QL_MAC_ATTACHED,	/* driver attached */

	QL_MAC_STARTED,		/* interrupt enabled, driver is ready */

	QL_MAC_BRINGDOWN,	/* in the bring down process */

	QL_MAC_STOPPED,		/* stoped, no more interrupts */

	QL_MAC_DETACH,		/* to be detached */

	QL_MAC_SUSPENDED

};

/*

 * Soft Request Flag

 */

#define	NEED_HW_RESET	BIT_0	/* need hardware reset */

#define	NEED_MPI_RESET	BIT_1	/* need MPI RISC reset */

/*

 * (Internal) return values from ioctl subroutines

 */

enum ioc_reply {

	IOC_INVAL = -1,			/* bad, NAK with EINVAL	*/

	IOC_DONE,			/* OK, reply sent	*/

	IOC_ACK,			/* OK, just send ACK	*/

	IOC_REPLY,			/* OK, just send reply	*/

	IOC_RESTART_ACK,		/* OK, restart & ACK	*/

	IOC_RESTART_REPLY		/* OK, restart & reply	*/

};

/*

 * Link Speed,in Mbps

 */

#define	SPEED_10		10

#define	SPEED_100		100

#define	SPEED_1000		1000

#define	SPEED_10G		10000

/*

 * Multicast List

 */

typedef struct {

	struct ether_addr	addr;

	unsigned char		reserved[2];

} ql_multicast_addr;

#define	MAX_MULTICAST_LIST_SIZE	128

typedef struct {

	struct ether_addr	addr;		/* in canonical form	*/

	boolean_t		set;		/* B_TRUE => valid	*/

} qlge_mac_addr_t;

#define	MAX_UNICAST_LIST_SIZE	128

/*

 * Device kstate structure.

 */

enum {

	QL_KSTAT_CHIP = 0,

	QL_KSTAT_LINK,

	QL_KSTAT_REG,

	QL_KSTAT_COUNT

};

/*

 * Register Bit Set/Reset

 */

enum {

	BIT_SET = 0,

	BIT_RESET

};

/*

 * Flash Image Search State

 */

enum {	STOP_SEARCH,		/* Image address bad, no more search */

	CONTINUE_SEARCH,	/* Image address ok, continue search */

	LAST_IMAGE_FOUND	/* Found last image and FLTDS address */

};

/*

 * Loop Back Modes

 */

enum {	QLGE_LOOP_NONE,

	QLGE_LOOP_INTERNAL_PARALLEL,

	QLGE_LOOP_INTERNAL_SERIAL,

	QLGE_LOOP_EXTERNAL_PHY

};

/* for soft state routine */

typedef struct {

	offset_t	index;

	char		*name;

} ql_ksindex_t;

struct bq_desc {

	struct		dma_info bd_dma;

	struct		bq_desc *next;

	struct		rx_ring *rx_ring;

	mblk_t		*mp;

	frtn_t		rx_recycle;	/* recycle function - called after mp */

					/* is to be freed by OS */

	uint16_t	index;

	uint16_t	free_buf;	/* Set to indicate the buffer is */

					/* being freed, new one should not */

					/* be allocated */

	uint32_t	upl_inuse;	/* buffer in use by upper layers */

};

#define	VM_PAGE_SIZE		4096

#define	QLGE_POLL_ALL		-1

#define	SMALL_BUFFER_SIZE	512

#define	LARGE_BUFFER_SIZE	4096

#define	MAX_TX_WAIT_COUNT	1000

#define	MAX_RX_WAIT_COUNT	25	/* 25 second */

#define	MIN_BUFFERS_ARM_COUNT	16

#define	MIN_BUFFERS_FREE_COUNT	32	/* If free buffer count go over this */

					/* value, arm the chip */

/* if less than 16 free lrg buf nodes in the free list, then */

/* rx has to use copy method to send packets upstream */

#define	RX_COPY_MODE_THRESHOLD	(MIN_BUFFERS_ARM_COUNT/4)

/* if there are more than TX_STOP_THRESHOLD free tx buffers, try to send it */

#define	TX_STOP_THRESHOLD	16

#define	TX_RESUME_THRESHOLD	8

struct tx_ring_desc {

	struct ob_mac_iocb_req *queue_entry;	/* tx descriptor of this */

	struct dma_info		dma_mem_area;	/* tx buffer */

	ddi_dma_handle_t	tx_dma_handle[QL_MAX_TX_DMA_HANDLES];

	int			tx_dma_handle_used;

	enum tx_mode_t		tx_type;	/* map mode or copy mode */

	mblk_t			*mp;		/* requested sending packet */

	uint32_t		index;

	caddr_t			copy_buffer;

	uint64_t		copy_buffer_dma_addr;

	struct dma_info		oal_dma;	/* oal is premapped */

	uint64_t		oal_dma_addr;	/* oal dma address premapped */

	uint32_t		tx_bytes;

	void			*oal;

};

struct tx_ring {

	struct qlge		*qlge;

	struct dma_info		wqicb_dma;

	uint16_t		cq_id;		/* completion (rx) queue for */

						/* tx completions */

	uint8_t			wq_id;

	uint32_t		wq_size;

	uint32_t		wq_len;

	kmutex_t		tx_lock;

	struct dma_info		wq_dma;

	volatile uint32_t	tx_free_count;

	uint32_t		tx_mode;

	boolean_t		queue_stopped;	/* Tx no resource */

	uint32_t		*prod_idx_db_reg;

	uint16_t		prod_idx;

	uint32_t		*valid_db_reg;	/* PCI doorbell mem area + 4 */

	struct tx_ring_desc	*wq_desc;

				/* shadow copy of consumer idx */

	uint32_t		*cnsmr_idx_sh_reg;

				/* dma-shadow copy consumer */

	uint64_t		cnsmr_idx_sh_reg_dma;

	uint32_t		defer;	/* tx no resource */

	uint64_t		obytes;

	uint64_t		opackets;

	uint32_t		errxmt;

	uint64_t		brdcstxmt;

	uint64_t		multixmt;

	uint64_t		tx_fail_dma_bind;

	uint64_t		tx_no_dma_handle;

	uint64_t		tx_no_dma_cookie;

	enum mac_state		mac_flags;

};

struct bq_element {

uint32_t addr_lo;

uint32_t addr_hi;

};

/*

 * Type of inbound queue.

 */

enum {

	DEFAULT_Q = 2,		/* Handles slow queue and chip/MPI events. */

	TX_Q = 3,		/* Handles outbound completions. */

	RX_Q = 4,		/* Handles inbound completions. */

};

struct rx_ring {

	struct dma_info		cqicb_dma;

	/* GLD required flags */

	uint64_t		ring_gen_num;

	/* statistics */

	uint64_t		rx_packets;

	uint64_t		rx_bytes;

	uint32_t		frame_too_long;

	uint32_t		frame_too_short;

	uint32_t		fcs_err;

	uint32_t		rx_packets_dropped_no_buffer;

	uint32_t		rx_pkt_dropped_mac_unenabled;

	volatile uint32_t	rx_indicate;

	/* miscellaneous */

	int			type; /* DEFAULT_Q, TX_Q, RX_Q */

	kmutex_t		rx_lock;

	uint32_t		irq;

	struct qlge		*qlge;

	uint32_t		cpu;	/* Which CPU this should run on. */

	enum mac_state		mac_flags;

	/* completion queue */

	struct dma_info		cq_dma;	/* virtual addr and phy addr */

	uint32_t		cq_size;

	uint32_t		cq_len;

	uint16_t		cq_id;

	volatile uint32_t	*prod_idx_sh_reg;	/* Shadowed prod reg */

	uint64_t		prod_idx_sh_reg_dma;	/* Physical address */

	uint32_t		*cnsmr_idx_db_reg;	/* PCI db mem area 0 */

	uint32_t		cnsmr_idx;		/* current sw idx */

	struct net_rsp_iocb	*curr_entry;	/* next entry on queue */

	uint32_t		*valid_db_reg;	/* PCI doorbell mem area + 4 */

	/* large buffer queue */