/*

 * CDDL HEADER START

 *

 * The contents of this file are subject to the terms of the

 * Common Development and Distribution License (the "License").

 * You may not use this file except in compliance with the License.

 *

 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

 * or http://www.opensolaris.org/os/licensing.

 * See the License for the specific language governing permissions

 * and limitations under the License.

 *

 * When distributing Covered Code, include this CDDL HEADER in each

 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.

 * If applicable, add the following below this CDDL HEADER, with the

 * fields enclosed by brackets "[]" replaced with your own identifying

 * information: Portions Copyright [yyyy] [name of copyright owner]

 *

 * CDDL HEADER END

 */

/*

 */

#ifndef _QLGE_HW_H

#define	_QLGE_HW_H

#ifdef __cplusplus

extern "C" {

#endif

#define	ISP_SCHULTZ 0x8000

#define	MB_REG_COUNT		8

#define	MB_DATA_REG_COUNT	(MB_REG_COUNT-1)

#define	QLA_SCHULTZ(qlge) ((qlge)->device_id == ISP_SCHULTZ)

/*

 * Data bit definitions.

 */

#define	BIT_0	0x1

#define	BIT_1	0x2

#define	BIT_2	0x4

#define	BIT_3	0x8

#define	BIT_4	0x10

#define	BIT_5	0x20

#define	BIT_6	0x40

#define	BIT_7	0x80

#define	BIT_8	0x100

#define	BIT_9	0x200

#define	BIT_10	0x400

#define	BIT_11	0x800

#define	BIT_12	0x1000

#define	BIT_13	0x2000

#define	BIT_14	0x4000

#define	BIT_15	0x8000

#define	BIT_16	0x10000

#define	BIT_17	0x20000

#define	BIT_18	0x40000

#define	BIT_19	0x80000

#define	BIT_20	0x100000

#define	BIT_21	0x200000

#define	BIT_22	0x400000

#define	BIT_23	0x800000

#define	BIT_24	0x1000000

#define	BIT_25	0x2000000

#define	BIT_26	0x4000000

#define	BIT_27	0x8000000

#define	BIT_28	0x10000000

#define	BIT_29	0x20000000

#define	BIT_30	0x40000000

#define	BIT_31	0x80000000

typedef struct ql_stats

{

	uint32_t	intr_type;

	/* software statics */

	uint32_t	intr;

	uint64_t	speed;

	uint32_t	duplex;

	uint32_t	media;

	/* TX */

	uint64_t	obytes;

	uint64_t	opackets;

	uint32_t	nocarrier;

	uint32_t	defer;

	/* RX */

	uint64_t	rbytes;

	uint64_t	rpackets;

	uint32_t	norcvbuf;

	uint32_t	frame_too_long;

	uint32_t	crc;

	ulong_t		multircv;

	ulong_t		brdcstrcv;

	uint32_t	errrcv;

	uint32_t	frame_too_short;

	/* statics by hw */

	uint32_t	errxmt;

	uint32_t	frame_err;

	ulong_t		multixmt;

	ulong_t		brdcstxmt;

	uint32_t	phy_addr;

	uint32_t	jabber_err;

}ql_stats_t;

#define	ETHERNET_CRC_SIZE	4

/*

 * Register Definitions...

 */

#define	MAILBOX_COUNT	16

/* System Register 0x00 */

#define	PROC_ADDR_RDY	BIT_31

#define	PROC_ADDR_R	BIT_30

#define	PROC_ADDR_ERR	BIT_29

#define	PROC_ADDR_DA	BIT_28

#define	PROC_ADDR_FUNC0_MBI	0x00001180

#define	PROC_ADDR_FUNC0_MBO	(PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT)

#define	PROC_ADDR_FUNC0_CTL	0x000011a1

#define	PROC_ADDR_FUNC2_MBI	0x00001280

#define	PROC_ADDR_FUNC2_MBO	(PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT)

#define	PROC_ADDR_FUNC2_CTL	0x000012a1

#define	PROC_ADDR_MPI_RISC	0x00000000

#define	PROC_ADDR_MDE		0x00010000

#define	PROC_ADDR_REGBLOCK	0x00020000

#define	PROC_ADDR_RISC_REG	0x00030000

/* System Register 0x08 */

#define	SYSTEM_EFE_FAE		0x3u

#define	SYSTEM_EFE_FAE_MASK	(SYSTEM_EFE_FAE<<16)

enum {

	SYS_EFE = (1 << 0),

	SYS_FAE = (1 << 1),

	SYS_MDC = (1 << 2),

	SYS_DST = (1 << 3),

	SYS_DWC = (1 << 4),

	SYS_EVW = (1 << 5),

	SYS_OMP_DLY_MASK = 0x3f000000,

	/*

	 * There are no values defined as of edit #15.

	 */

	SYS_ODI = (1 << 14)

};

/*

 * Reset/Failover Register (RST_FO) bit definitions.

 */

#define	RST_FO_TFO		(1 << 0)

#define	RST_FO_RR_MASK		0x00060000

#define	RST_FO_RR_CQ_CAM	0x00000000

#define	RST_FO_RR_DROP		0x00000001

#define	RST_FO_RR_DQ		0x00000002

#define	RST_FO_RR_RCV_FUNC_CQ	0x00000003

#define	RST_FO_FRB		BIT_12

#define	RST_FO_MOP		BIT_13

#define	RST_FO_REG		BIT_14

#define	RST_FO_FR		0x8000u

/*

 * Function Specific Control Register (FSC) bit definitions.

 */

enum {

	FSC_DBRST_MASK = 0x00070000,

	FSC_DBRST_256 = 0x00000000,

	FSC_DBRST_512 = 0x00000001,

	FSC_DBRST_768 = 0x00000002,

	FSC_DBRST_1024 = 0x00000003,

	FSC_DBL_MASK = 0x00180000,

	FSC_DBL_DBRST = 0x00000000,

	FSC_DBL_MAX_PLD = 0x00000008,

	FSC_DBL_MAX_BRST = 0x00000010,

	FSC_DBL_128_BYTES = 0x00000018,

	FSC_EC = (1 << 5),

	FSC_EPC_MASK = 0x00c00000,

	FSC_EPC_INBOUND = (1 << 6),

	FSC_EPC_OUTBOUND = (1 << 7),

	FSC_VM_PAGESIZE_MASK = 0x07000000,

	FSC_VM_PAGE_2K = 0x00000100,

	FSC_VM_PAGE_4K = 0x00000200,

	FSC_VM_PAGE_8K = 0x00000300,

	FSC_VM_PAGE_64K = 0x00000600,

	FSC_SH = (1 << 11),

	FSC_DSB = (1 << 12),

	FSC_STE = (1 << 13),

	FSC_FE = (1 << 15)

};

/*

 * Host Command Status Register (CSR) bit definitions.

 */

#define	CSR_ERR_STS_MASK	0x0000003f

/*

 * There are no valued defined as of edit #15.

 */

#define	CSR_RR			BIT_8

#define	CSR_HRI			BIT_9

#define	CSR_RP			BIT_10

#define	CSR_CMD_PARM_SHIFT	22

#define	CSR_CMD_NOP		0x00000000

#define	CSR_CMD_SET_RST		0x1000000

#define	CSR_CMD_CLR_RST		0x20000000

#define	CSR_CMD_SET_PAUSE	0x30000000

#define	CSR_CMD_CLR_PAUSE	0x40000000

#define	CSR_CMD_SET_H2R_INT	0x50000000

#define	CSR_CMD_CLR_H2R_INT	0x60000000

#define	CSR_CMD_PAR_EN		0x70000000

#define	CSR_CMD_SET_BAD_PAR	0x80000000u

#define	CSR_CMD_CLR_BAD_PAR	0x90000000u

#define	CSR_CMD_CLR_R2PCI_INT	0xa0000000u

/*

 * Configuration Register (CFG) bit definitions.

 */

enum {

	CFG_LRQ = (1 << 0),

	CFG_DRQ = (1 << 1),

	CFG_LR = (1 << 2),

	CFG_DR = (1 << 3),

	CFG_LE = (1 << 5),

	CFG_LCQ = (1 << 6),

	CFG_DCQ = (1 << 7),

	CFG_Q_SHIFT = 8,

	CFG_Q_MASK = 0x7f000000

};

/*

 *  Status Register (STS) bit definitions.

 */

enum {

	STS_FE = (1 << 0),

	STS_PI = (1 << 1),

	STS_PL0 = (1 << 2),

	STS_PL1 = (1 << 3),

	STS_PI0 = (1 << 4),

	STS_PI1 = (1 << 5),

	STS_FUNC_ID_MASK = 0x000000c0,

	STS_FUNC_ID_SHIFT = 6,

	STS_F0E = (1 << 8),

	STS_F1E = (1 << 9),

	STS_F2E = (1 << 10),

	STS_F3E = (1 << 11),

	STS_NFE = (1 << 12)

};

/*

 * Register (REV_ID) bit definitions.

 */

enum {

	REV_ID_MASK = 0x0000000f,

	REV_ID_NICROLL_SHIFT = 0,

	REV_ID_NICREV_SHIFT = 4,

	REV_ID_XGROLL_SHIFT = 8,

	REV_ID_XGREV_SHIFT = 12,

	REV_ID_CHIPREV_SHIFT = 28

};

/*

 *  Force ECC Error Register (FRC_ECC_ERR) bit definitions.

 */

enum {

	FRC_ECC_ERR_VW = (1 << 12),

	FRC_ECC_ERR_VB = (1 << 13),

	FRC_ECC_ERR_NI = (1 << 14),

	FRC_ECC_ERR_NO = (1 << 15),

	FRC_ECC_PFE_SHIFT = 16,

	FRC_ECC_ERR_DO = (1 << 18),

	FRC_ECC_P14 = (1 << 19)

};

/*

 * Error Status Register (ERR_STS) bit definitions.

 */

enum {

	ERR_STS_NOF = (1 << 0),

	ERR_STS_NIF = (1 << 1),

	ERR_STS_DRP = (1 << 2),

	ERR_STS_XGP = (1 << 3),

	ERR_STS_FOU = (1 << 4),

	ERR_STS_FOC = (1 << 5),

	ERR_STS_FOF = (1 << 6),

	ERR_STS_FIU = (1 << 7),

	ERR_STS_FIC = (1 << 8),

	ERR_STS_FIF = (1 << 9),

	ERR_STS_MOF = (1 << 10),

	ERR_STS_TA = (1 << 11),

	ERR_STS_MA = (1 << 12),

	ERR_STS_MPE = (1 << 13),

	ERR_STS_SCE = (1 << 14),

	ERR_STS_STE = (1 << 15),

	ERR_STS_FOW = (1 << 16),

	ERR_STS_UE = (1 << 17),

	ERR_STS_MCH = (1 << 26),

	ERR_STS_LOC_SHIFT = 27

};

/*

 * Semaphore Register (SEM) bit definitions.

 */

/*

 * Example:

 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)

 */

#define	SEM_CLEAR		0

#define	SEM_SET			1

#define	SEM_FORCE		3

#define	SEM_XGMAC0_SHIFT	0

#define	SEM_XGMAC1_SHIFT	2

#define	SEM_ICB_SHIFT		4

#define	SEM_MAC_ADDR_SHIFT	6

#define	SEM_FLASH_SHIFT		8

#define	SEM_PROBE_SHIFT		10

#define	SEM_RT_IDX_SHIFT	12

#define	SEM_PROC_REG_SHIFT	14

#define	SEM_XGMAC0_MASK		0x00030000

#define	SEM_XGMAC1_MASK		0x000c0000

#define	SEM_ICB_MASK		0x00300000

#define	SEM_MAC_ADDR_MASK	0x00c00000

#define	SEM_FLASH_MASK		0x03000000

#define	SEM_PROBE_MASK		0x0c000000

#define	SEM_RT_IDX_MASK		0x30000000

#define	SEM_PROC_REG_MASK	0xc0000000

/*

 * Stop CQ Processing Register (CQ_STOP) bit definitions.

 */

enum {

	CQ_STOP_QUEUE_MASK = (0x007f0000),

	CQ_STOP_TYPE_MASK = (0x03000000),

	CQ_STOP_TYPE_START = 0x00000100,

	CQ_STOP_TYPE_STOP = 0x00000200,

	CQ_STOP_TYPE_READ = 0x00000300,

	CQ_STOP_EN = (1 << 15)

};

/*

 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.

 */

#define	MAC_ADDR_IDX_SHIFT		4

#define	MAC_ADDR_TYPE_SHIFT		16

#define	MAC_ADDR_TYPE_MASK 		0x000f0000

#define	MAC_ADDR_TYPE_CAM_MAC		0x00000000

#define	MAC_ADDR_TYPE_MULTI_MAC		0x00010000

#define	MAC_ADDR_TYPE_VLAN		0x00020000

#define	MAC_ADDR_TYPE_MULTI_FLTR	0x00030000

#define	MAC_ADDR_TYPE_FC_MAC		0x00040000

#define	MAC_ADDR_TYPE_MGMT_MAC		0x00050000

#define	MAC_ADDR_TYPE_MGMT_VLAN		0x00060000

#define	MAC_ADDR_TYPE_MGMT_V4		0x00070000

#define	MAC_ADDR_TYPE_MGMT_V6		0x00080000

#define	MAC_ADDR_TYPE_MGMT_TU_DP	0x00090000

#define	MAC_ADDR_ADR			BIT_25

#define	MAC_ADDR_RS			BIT_26

#define	MAC_ADDR_E  			BIT_27

#define	MAC_ADDR_MR  			BIT_30

#define	MAC_ADDR_MW  			BIT_31

#define	MAX_MULTICAST_HW_SIZE		32

/*

 *  MAC Protocol Address Index Register (SPLT_HDR, 0xC0) bit definitions.

 */

#define	SPLT_HDR_EP	BIT_31

/*

 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.

 */

enum {

	NIC_RCV_CFG_PPE = (1 << 0),

	NIC_RCV_CFG_VLAN_MASK = 0x00060000,

	NIC_RCV_CFG_VLAN_ALL = 0x00000000,

	NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,

	NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,

	NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,

	NIC_RCV_CFG_RV = (1 << 3),

	NIC_RCV_CFG_DFQ_MASK = (0x7f000000),

	NIC_RCV_CFG_DFQ_SHIFT = 8,

	NIC_RCV_CFG_DFQ = 0	/* HARDCODE default queue to 0. */

};

/*

 * Routing Index Register (RT_IDX) bit definitions.

 */

#define	RT_IDX_IDX_SHIFT	8

#define	RT_IDX_TYPE_MASK	0x000f0000

#define	RT_IDX_TYPE_RT		0x00000000

#define	RT_IDX_TYPE_RT_INV	0x00010000

#define	RT_IDX_TYPE_NICQ	0x00020000

#define	RT_IDX_TYPE_NICQ_INV	0x00030000

#define	RT_IDX_DST_MASK		0x00700000

#define	RT_IDX_DST_RSS		0x00000000

#define	RT_IDX_DST_CAM_Q	0x00100000

#define	RT_IDX_DST_COS_Q	0x00200000

#define	RT_IDX_DST_DFLT_Q	0x00300000

#define	RT_IDX_DST_DEST_Q	0x00400000

#define	RT_IDX_RS		BIT_26

#define	RT_IDX_E		BIT_27

#define	RT_IDX_MR		BIT_30

#define	RT_IDX_MW		BIT_31

/* Nic Queue format - type 2 bits */

#define	RT_IDX_BCAST		1

#define	RT_IDX_MCAST		BIT_1

#define	RT_IDX_MCAST_MATCH	BIT_2

#define	RT_IDX_MCAST_REG_MATCH	BIT_3

#define	RT_IDX_MCAST_HASH_MATCH	BIT_4

#define	RT_IDX_FC_MACH		BIT_5

#define	RT_IDX_ETH_FCOE		BIT_6

#define	RT_IDX_CAM_HIT		BIT_7

#define	RT_IDX_CAM_BIT0		BIT_8

#define	RT_IDX_CAM_BIT1		BIT_9

#define	RT_IDX_VLAN_TAG		BIT_10

#define	RT_IDX_VLAN_MATCH	BIT_11

#define	RT_IDX_VLAN_FILTER	BIT_12

#define	RT_IDX_ETH_SKIP1	BIT_13

#define	RT_IDX_ETH_SKIP2	BIT_14

#define	RT_IDX_BCAST_MCAST_MATCH	BIT_15

#define	RT_IDX_802_3		BIT_16

#define	RT_IDX_LLDP		BIT_17

#define	RT_IDX_UNUSED018	BIT_18

#define	RT_IDX_UNUSED019	BIT_19

#define	RT_IDX_UNUSED20		BIT_20

#define	RT_IDX_UNUSED21		BIT_21

#define	RT_IDX_ERR		BIT_22

#define	RT_IDX_VALID		BIT_23

#define	RT_IDX_TU_CSUM_ERR	BIT_24

#define	RT_IDX_IP_CSUM_ERR	BIT_25

#define	RT_IDX_MAC_ERR		BIT_26

#define	RT_IDX_RSS_TCP6		BIT_27

#define	RT_IDX_RSS_TCP4		BIT_28

#define	RT_IDX_RSS_IPV6		BIT_29

#define	RT_IDX_RSS_IPV4		BIT_30

#define	RT_IDX_RSS_MATCH	BIT_31

/* Hierarchy for the NIC Queue Mask */

enum {

	RT_IDX_ALL_ERR_SLOT = 0,

	RT_IDX_MAC_ERR_SLOT = 0,

	RT_IDX_IP_CSUM_ERR_SLOT = 1,

	RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,

	RT_IDX_BCAST_SLOT = 3,

	RT_IDX_MCAST_MATCH_SLOT = 4,

	RT_IDX_ALLMULTI_SLOT = 5,

	RT_IDX_UNUSED6_SLOT = 6,

	RT_IDX_UNUSED7_SLOT = 7,

	RT_IDX_RSS_MATCH_SLOT = 8,

	RT_IDX_RSS_IPV4_SLOT = 8,

	RT_IDX_RSS_IPV6_SLOT = 9,

	RT_IDX_RSS_TCP4_SLOT = 10,

	RT_IDX_RSS_TCP6_SLOT = 11,

	RT_IDX_CAM_HIT_SLOT = 12,

	RT_IDX_UNUSED013 = 13,

	RT_IDX_UNUSED014 = 14,

	RT_IDX_PROMISCUOUS_SLOT = 15,

	RT_IDX_MAX_SLOTS = 16

};

enum {

	CAM_OUT_ROUTE_FC = 0,

	CAM_OUT_ROUTE_NIC = 1,

	CAM_OUT_FUNC_SHIFT = 2,

	CAM_OUT_RV = (1 << 4),

	CAM_OUT_SH = (1 << 15),

	CAM_OUT_CQ_ID_SHIFT = 5

};

/* Reset/Failover Register 0C */

#define	FUNCTION_RESET		0x8000u

#define	FUNCTION_RESET_MASK	(FUNCTION_RESET<<16)

/* Function Specific Control Register 0x10 */

#define	FSC_MASK	(0x97ffu << 16)

#define	FSC_FE		0x8000

/* Configuration Register 0x28 */

#define	LOAD_LCQ	0x40

#define	LOAD_LCQ_MASK	(0x7F40u << 16)

#define	LOAD_ICB_ERR	0x20

#define	LOAD_LRQ	0x01

#define	LOAD_LRQ_MASK	(0x7F01u << 16)

#define	FN0_NET	0

#define	FN1_NET	1

#define	FN0_FC	2

#define	FN1_FC	3

/*

 * Semaphore Register (SEM) bit definitions.

 */

#define	SEM_CLEAR		0

#define	SEM_SET			1

#define	SEM_FORCE		3

#define	SEM_XGMAC0_SHIFT	0

#define	SEM_XGMAC1_SHIFT	2

#define	SEM_ICB_SHIFT		4

#define	SEM_MAC_ADDR_SHIFT	6

#define	SEM_FLASH_SHIFT		8

#define	SEM_PROBE_SHIFT		10

#define	SEM_RT_IDX_SHIFT	12

#define	SEM_PROC_REG_SHIFT	14

#define	SEM_XGMAC0_MASK		0x00030000

#define	SEM_XGMAC1_MASK		0x000c0000

#define	SEM_ICB_MASK		0x00300000

#define	SEM_MAC_ADDR_MASK	0x00c00000

#define	SEM_FLASH_MASK		0x03000000

#define	SEM_PROBE_MASK		0x0c000000

#define	SEM_RT_IDX_MASK		0x30000000

#define	SEM_PROC_REG_MASK	0xc0000000

/* System Register 0x08 */

#define	SYSTEM_EFE_FAE	0x3u

#define	SYSTEM_EFE_FAE_MASK	(SYSTEM_EFE_FAE<<16)

/* Interrupt Status Register-1		0x3C */

#define	CQ_0_NOT_EMPTY			BIT_0

#define	CQ_1_NOT_EMPTY			BIT_1

#define	CQ_2_NOT_EMPTY			BIT_2

#define	CQ_3_NOT_EMPTY			BIT_3

#define	CQ_4_NOT_EMPTY			BIT_4

#define	CQ_5_NOT_EMPTY			BIT_5

#define	CQ_6_NOT_EMPTY			BIT_6

#define	CQ_7_NOT_EMPTY			BIT_7

#define	CQ_8_NOT_EMPTY			BIT_8