author | kucharsk |
Thu, 27 Oct 2005 14:59:45 -0700 | |
changeset 770 | 0eda482eb80f |
parent 0 | 68f95e015346 |
child 771 | 1c25a2120ec0 |
permissions | -rw-r--r-- |
0 | 1 |
/* |
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* CDDL HEADER START |
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* |
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* The contents of this file are subject to the terms of the |
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* Common Development and Distribution License, Version 1.0 only |
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* (the "License"). You may not use this file except in compliance |
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* with the License. |
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* |
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE |
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* or http://www.opensolaris.org/os/licensing. |
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* See the License for the specific language governing permissions |
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* and limitations under the License. |
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* |
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* When distributing Covered Code, include this CDDL HEADER in each |
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE. |
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* If applicable, add the following below this CDDL HEADER, with the |
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* fields enclosed by brackets "[]" replaced with your own identifying |
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* information: Portions Copyright [yyyy] [name of copyright owner] |
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* |
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* CDDL HEADER END |
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*/ |
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/* |
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* Copyright 2005 Sun Microsystems, Inc. All rights reserved. |
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* Use is subject to license terms. |
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*/ |
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||
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#ifndef _SYS_X86_ARCHEXT_H |
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#define _SYS_X86_ARCHEXT_H |
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||
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#pragma ident "%Z%%M% %I% %E% SMI" |
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||
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#if !defined(_ASM) |
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#include <sys/regset.h> |
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#include <sys/processor.h> |
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#include <vm/seg_enum.h> |
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#include <vm/page.h> |
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#endif /* _ASM */ |
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||
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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||
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/* |
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* cpuid instruction feature flags in %edx (standard function 1) |
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*/ |
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||
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#define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ |
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#define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ |
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#define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ |
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#define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ |
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#define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ |
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#define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ |
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#define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ |
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#define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ |
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#define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ |
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#define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ |
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/* 0x400 - reserved */ |
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#define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ |
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#define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ |
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#define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ |
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#define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ |
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#define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ |
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#define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ |
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#define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ |
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#define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ |
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#define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ |
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/* 0x100000 - reserved */ |
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#define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ |
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#define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ |
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#define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ |
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#define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ |
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#define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ |
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#define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ |
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#define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ |
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#define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ |
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#define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ |
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/* 0x40000000 - reserved */ |
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#define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ |
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||
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#define FMT_CPUID_INTC_EDX \ |
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"\20" \ |
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"\40pbe\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ |
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"\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat"\ |
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"\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ |
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"\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" |
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||
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/* |
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* cpuid instruction feature flags in %ecx (standard function 1) |
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*/ |
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#define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ |
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/* 0x00000002 - reserved */ |
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/* 0x00000004 - reserved */ |
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#define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ |
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#define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ |
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/* 0x00000020 - reserved */ |
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/* 0x00000040 - reserved */ |
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#define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ |
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#define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ |
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/* 0x00000200 - reserved */ |
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#define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ |
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/* 0x00000800 - reserved */ |
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/* 0x00001000 - reserved */ |
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/* 0x00002000 - reserved */ |
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#define CPUID_INTC_ECX_XTPR 0x00004000 /* disable task pri messages */ |
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||
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#define FMT_CPUID_INTC_ECX \ |
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"\20" \ |
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"\20\17xtpr\13cid\11tm2" \ |
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"\10est\5dscpl\4monitor\1sse3" |
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/* |
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* cpuid instruction feature flags in %edx (extended function 0x80000001) |
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*/ |
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||
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#define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ |
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#define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ |
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#define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ |
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#define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ |
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#define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ |
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#define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ |
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#define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ |
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#define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ |
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#define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ |
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#define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ |
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/* 0x00000400 - sysc on K6m6 */ |
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#define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ |
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#define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ |
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#define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ |
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#define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ |
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#define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ |
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#define CPUID_AMD_EDX_PAT 0x00010000 /* page attribute table */ |
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#define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ |
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/* 0x00040000 - reserved */ |
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/* 0x00080000 - reserved */ |
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#define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ |
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/* 0x00200000 - reserved */ |
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#define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ |
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#define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ |
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#define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ |
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/* 0x02000000 - reserved */ |
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/* 0x04000000 - reserved */ |
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/* 0x08000000 - reserved */ |
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/* 0x10000000 - reserved */ |
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#define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ |
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#define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ |
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#define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ |
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||
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#define FMT_CPUID_AMD_EDX \ |
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"\20" \ |
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"\40a3d\37a3d+\36lm\31fxsr" \ |
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"\30mmx\27mmxext\25nx\22pse\21pat" \ |
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"\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ |
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"\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" |
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#define CPUID_AMD_ECX_HTvalid 0x00000001 /* AMD: HTT bit valid */ |
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#define FMT_CPUID_AMD_ECX \ |
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"\20" \ |
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"\1htvalid" |
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#define P5_MCHADDR 0x0 |
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#define P5_CESR 0x11 |
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#define P5_CTR0 0x12 |
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#define P5_CTR1 0x13 |
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#define K5_MCHADDR 0x0 |
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#define K5_MCHTYPE 0x01 |
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#define K5_TSC 0x10 |
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#define K5_TR12 0x12 |
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||
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#define REG_MTRRCAP 0xfe |
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#define REG_MTRRDEF 0x2ff |
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#define REG_MTRR64K 0x250 |
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#define REG_MTRR16K1 0x258 |
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#define REG_MTRR16K2 0x259 |
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#define REG_MTRR4K1 0x268 |
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#define REG_MTRR4K2 0x269 |
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#define REG_MTRR4K3 0x26a |
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#define REG_MTRR4K4 0x26b |
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#define REG_MTRR4K5 0x26c |
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#define REG_MTRR4K6 0x26d |
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#define REG_MTRR4K7 0x26e |
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#define REG_MTRR4K8 0x26f |
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#define REG_MTRRPAT 0x277 |
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||
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#define REG_MTRRPHYSBASE0 0x200 |
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#define REG_MTRRPHYSMASK7 0x20f |
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#define REG_MC0_CTL 0x400 |
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#define REG_MC5_MISC 0x417 |
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#define REG_PERFCTR0 0xc1 |
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#define REG_PERFCTR1 0xc2 |
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#define REG_PERFEVNT0 0x186 |
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#define REG_PERFEVNT1 0x187 |
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||
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#define REG_TSC 0x10 /* timestamp counter */ |
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#define REG_APIC_BASE_MSR 0x1b |
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#define MSR_DEBUGCTL 0x1d9 |
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#define DEBUGCTL_LBR 0x01 |
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#define DEBUGCTL_BTF 0x02 |
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/* Intel P6, AMD */ |
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#define MSR_LBR_FROM 0x1db |
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#define MSR_LBR_TO 0x1dc |
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#define MSR_LEX_FROM 0x1dd |
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#define MSR_LEX_TO 0x1de |
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/* Intel P4 (pre-Prescott, non P4 M) */ |
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#define MSR_P4_LBSTK_TOS 0x1da |
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#define MSR_P4_LBSTK_0 0x1db |
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#define MSR_P4_LBSTK_1 0x1dc |
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#define MSR_P4_LBSTK_2 0x1dd |
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#define MSR_P4_LBSTK_3 0x1de |
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||
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/* Intel Pentium M */ |
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#define MSR_P6M_LBSTK_TOS 0x1c9 |
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#define MSR_P6M_LBSTK_0 0x040 |
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#define MSR_P6M_LBSTK_1 0x041 |
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#define MSR_P6M_LBSTK_2 0x042 |
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#define MSR_P6M_LBSTK_3 0x043 |
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#define MSR_P6M_LBSTK_4 0x044 |
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#define MSR_P6M_LBSTK_5 0x045 |
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#define MSR_P6M_LBSTK_6 0x046 |
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#define MSR_P6M_LBSTK_7 0x047 |
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||
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/* Intel P4 (Prescott) */ |
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#define MSR_PRP4_LBSTK_TOS 0x1da |
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#define MSR_PRP4_LBSTK_FROM_0 0x680 |
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#define MSR_PRP4_LBSTK_FROM_1 0x681 |
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#define MSR_PRP4_LBSTK_FROM_2 0x682 |
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#define MSR_PRP4_LBSTK_FROM_3 0x683 |
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#define MSR_PRP4_LBSTK_FROM_4 0x684 |
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#define MSR_PRP4_LBSTK_FROM_5 0x685 |
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#define MSR_PRP4_LBSTK_FROM_6 0x686 |
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#define MSR_PRP4_LBSTK_FROM_7 0x687 |
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#define MSR_PRP4_LBSTK_FROM_8 0x688 |
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#define MSR_PRP4_LBSTK_FROM_9 0x689 |
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#define MSR_PRP4_LBSTK_FROM_10 0x68a |
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#define MSR_PRP4_LBSTK_FROM_11 0x68b |
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#define MSR_PRP4_LBSTK_FROM_12 0x68c |
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#define MSR_PRP4_LBSTK_FROM_13 0x68d |
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#define MSR_PRP4_LBSTK_FROM_14 0x68e |
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#define MSR_PRP4_LBSTK_FROM_15 0x68f |
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#define MSR_PRP4_LBSTK_TO_0 0x6c0 |
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#define MSR_PRP4_LBSTK_TO_1 0x6c1 |
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#define MSR_PRP4_LBSTK_TO_2 0x6c2 |
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#define MSR_PRP4_LBSTK_TO_3 0x6c3 |
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#define MSR_PRP4_LBSTK_TO_4 0x6c4 |
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#define MSR_PRP4_LBSTK_TO_5 0x6c5 |
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#define MSR_PRP4_LBSTK_TO_6 0x6c6 |
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#define MSR_PRP4_LBSTK_TO_7 0x6c7 |
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#define MSR_PRP4_LBSTK_TO_8 0x6c8 |
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#define MSR_PRP4_LBSTK_TO_9 0x6c9 |
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#define MSR_PRP4_LBSTK_TO_10 0x6ca |
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#define MSR_PRP4_LBSTK_TO_11 0x6cb |
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#define MSR_PRP4_LBSTK_TO_12 0x6cc |
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#define MSR_PRP4_LBSTK_TO_13 0x6cd |
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#define MSR_PRP4_LBSTK_TO_14 0x6ce |
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#define MSR_PRP4_LBSTK_TO_15 0x6cf |
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||
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#define REG_MCG_CAP 0x179 |
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#define REG_MCG_STATUS 0x17a |
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#define REG_MCG_CTL 0x17b |
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||
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#define REG_MC0_CTL 0x400 |
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#define REG_MC0_STATUS 0x401 |
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#define REG_MC0_ADDR 0x402 |
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#define REG_MC0_MISC 0x403 |
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#define REG_MC1_CTL 0x404 |
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#define REG_MC1_STATUS 0x405 |
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#define REG_MC1_ADDR 0x406 |
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#define REG_MC1_MISC 0x407 |
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#define REG_MC2_CTL 0x408 |
|
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#define REG_MC2_STATUS 0x409 |
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#define REG_MC2_ADDR 0x40a |
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#define REG_MC2_MISC 0x40b |
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#define REG_MC4_CTL 0x40c |
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#define REG_MC4_STATUS 0x40d |
|
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#define REG_MC4_ADDR 0x40e |
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#define REG_MC4_MISC 0x40f |
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#define REG_MC3_CTL 0x410 |
|
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#define REG_MC3_STATUS 0x411 |
|
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#define REG_MC3_ADDR 0x412 |
|
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#define REG_MC3_MISC 0x413 |
|
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||
289 |
#define P6_MCG_CAP_COUNT 5 |
|
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#define MCG_CAP_COUNT_MASK 0xff |
|
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#define MCG_CAP_CTL_P 0x100 |
|
292 |
||
293 |
#define MCG_STATUS_RIPV 0x01 |
|
294 |
#define MCG_STATUS_EIPV 0x02 |
|
295 |
#define MCG_STATUS_MCIP 0x04 |
|
296 |
||
297 |
#define MCG_CTL_VALUE 0xffffffff |
|
298 |
||
299 |
#define MCI_CTL_VALUE 0xffffffff |
|
300 |
#define MCI_STATUS_ERRCODE 0xffff |
|
301 |
#define MCI_STATUS_MSERRCODE 0xffff0000 |
|
302 |
#define MCI_STATUS_PCC ((long long)0x200000000000000) |
|
303 |
#define MCI_STATUS_ADDRV ((long long)0x400000000000000) |
|
304 |
#define MCI_STATUS_MISCV ((long long)0x800000000000000) |
|
305 |
#define MCI_STATUS_EN ((long long)0x1000000000000000) |
|
306 |
#define MCI_STATUS_UC ((long long)0x2000000000000000) |
|
307 |
#define MCI_STATUS_O ((long long)0x4000000000000000) |
|
308 |
#define MCI_STATUS_VAL ((long long)0x8000000000000000) |
|
309 |
||
310 |
#define MSERRCODE_SHFT 16 |
|
311 |
||
312 |
||
313 |
#define MTRRTYPE_MASK 0xff |
|
314 |
||
315 |
||
316 |
#define MTRRCAP_FIX 0x100 |
|
317 |
#define MTRRCAP_VCNTMASK 0xff |
|
318 |
#define MTRRCAP_USWC 0x400 |
|
319 |
||
320 |
#define MTRRDEF_E 0x800 |
|
321 |
#define MTRRDEF_FE 0x400 |
|
322 |
||
323 |
#define MTRRPHYSMASK_V 0x800 |
|
324 |
||
325 |
#define MTRR_TYPE_UC 0 |
|
326 |
#define MTRR_TYPE_WC 1 |
|
327 |
#define MTRR_TYPE_WT 4 |
|
328 |
#define MTRR_TYPE_WP 5 |
|
329 |
#define MTRR_TYPE_WB 6 |
|
330 |
||
331 |
/* |
|
332 |
* Page attribute table is setup in the following way |
|
333 |
* PAT0 Write-BACK |
|
334 |
* PAT1 Write-Through |
|
335 |
* PAT2 Unchacheable |
|
336 |
* PAT3 Uncacheable |
|
337 |
* PAT4 Uncacheable |
|
338 |
* PAT5 Write-Protect |
|
339 |
* PAT6 Write-Combine |
|
340 |
* PAT7 Uncacheable |
|
341 |
*/ |
|
342 |
#define PAT_DEFAULT_ATTRIBUTE \ |
|
343 |
((uint64_t)MTRR_TYPE_WC << 48)|((uint64_t)MTRR_TYPE_WP << 40)| \ |
|
344 |
(MTRR_TYPE_WT << 8)|(MTRR_TYPE_WB) |
|
345 |
||
346 |
||
347 |
#define MTRR_SETTYPE(a, t) ((a &= (uint64_t)~0xff),\ |
|
348 |
(a |= ((t) & 0xff))) |
|
349 |
#define MTRR_SETVINVALID(a) ((a) &= ~MTRRPHYSMASK_V) |
|
350 |
||
351 |
||
352 |
#define MTRR_SETVBASE(a, b, t) ((a) =\ |
|
353 |
((((uint64_t)(b)) & 0xffffff000)|\ |
|
354 |
(((uint32_t)(t)) & 0xff))) |
|
355 |
||
356 |
#define MTRR_SETVMASK(a, s, v) ((a) =\ |
|
357 |
((~(((uint64_t)(s)) - 1) & 0xffffff000)|\ |
|
358 |
(((uint32_t)(v)) << 11))) |
|
359 |
||
360 |
#define MTRR_GETVBASE(a) (((uint64_t)(a)) & 0xffffff000) |
|
361 |
#define MTRR_GETVTYPE(a) (((uint64_t)(a)) & 0xff) |
|
362 |
#define MTRR_GETVSIZE(a) ((~((uint64_t)(a)) + 1) & 0xffffff000) |
|
363 |
||
364 |
||
365 |
#define MAX_MTRRVAR 8 |
|
366 |
||
367 |
#if !defined(_ASM) |
|
368 |
typedef struct mtrrvar { |
|
369 |
uint64_t mtrrphys_base; |
|
370 |
uint64_t mtrrphys_mask; |
|
371 |
} mtrrvar_t; |
|
372 |
#endif /* _ASM */ |
|
373 |
||
374 |
#define X86_LARGEPAGE 0x00000001 |
|
375 |
#define X86_TSC 0x00000002 |
|
376 |
#define X86_MSR 0x00000004 |
|
377 |
#define X86_MTRR 0x00000008 |
|
378 |
#define X86_PGE 0x00000010 |
|
379 |
#define X86_CMOV 0x00000040 |
|
380 |
#define X86_MMX 0x00000080 |
|
381 |
#define X86_MCA 0x00000100 |
|
382 |
#define X86_PAE 0x00000200 |
|
383 |
#define X86_CX8 0x00000400 |
|
384 |
#define X86_PAT 0x00000800 |
|
385 |
#define X86_SEP 0x00001000 |
|
386 |
#define X86_SSE 0x00002000 |
|
387 |
#define X86_SSE2 0x00004000 |
|
388 |
#define X86_HTT 0x00008000 |
|
389 |
#define X86_ASYSC 0x00010000 |
|
390 |
#define X86_NX 0x00020000 |
|
391 |
#define X86_SSE3 0x00040000 |
|
392 |
#define X86_CX16 0x00080000 |
|
393 |
#define X86_CMP 0x00100000 |
|
394 |
#define X86_CPUID 0x01000000 |
|
395 |
||
396 |
#define FMT_X86_FEATURE \ |
|
397 |
"\20" \ |
|
398 |
"\31cpuid" \ |
|
399 |
"\25cmp\24cx16\23sse3\22nx\21asysc" \ |
|
400 |
"\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca" \ |
|
401 |
"\10mmx\7cmov\5pge\4mtrr\3msr\2tsc\1lgpg" |
|
402 |
||
403 |
/* |
|
404 |
* x86_type is a legacy concept; this is supplanted |
|
405 |
* for most purposes by x86_feature; modern CPUs |
|
406 |
* should be X86_TYPE_OTHER |
|
407 |
*/ |
|
408 |
#define X86_TYPE_OTHER 0 |
|
409 |
#define X86_TYPE_486 1 |
|
410 |
#define X86_TYPE_P5 2 |
|
411 |
#define X86_TYPE_P6 3 |
|
412 |
#define X86_TYPE_CYRIX_486 4 |
|
413 |
#define X86_TYPE_CYRIX_6x86L 5 |
|
414 |
#define X86_TYPE_CYRIX_6x86 6 |
|
415 |
#define X86_TYPE_CYRIX_GXm 7 |
|
416 |
#define X86_TYPE_CYRIX_6x86MX 8 |
|
417 |
#define X86_TYPE_CYRIX_MediaGX 9 |
|
418 |
#define X86_TYPE_CYRIX_MII 10 |
|
419 |
#define X86_TYPE_VIA_CYRIX_III 11 |
|
420 |
#define X86_TYPE_P4 12 |
|
421 |
||
422 |
/* |
|
423 |
* x86_vendor allows us to select between |
|
424 |
* implementation features and helps guide |
|
425 |
* the interpretation of the cpuid instruction. |
|
426 |
*/ |
|
427 |
#define X86_VENDOR_Intel 0 /* GenuineIntel */ |
|
428 |
#define X86_VENDOR_IntelClone 1 /* (an Intel clone) */ |
|
429 |
#define X86_VENDOR_AMD 2 /* AuthenticAMD */ |
|
430 |
#define X86_VENDOR_Cyrix 3 /* CyrixInstead */ |
|
431 |
#define X86_VENDOR_UMC 4 /* UMC UMC UMC */ |
|
432 |
#define X86_VENDOR_NexGen 5 /* NexGenDriven */ |
|
433 |
#define X86_VENDOR_Centaur 6 /* CentaurHauls */ |
|
434 |
#define X86_VENDOR_Rise 7 /* RiseRiseRise */ |
|
435 |
#define X86_VENDOR_SiS 8 /* SiS SiS SiS */ |
|
436 |
#define X86_VENDOR_TM 9 /* GenuineTMx86 */ |
|
437 |
#define X86_VENDOR_NSC 10 /* Geode by NSC */ |
|
438 |
||
439 |
#if !defined(_ASM) |
|
440 |
||
441 |
#if defined(_KERNEL) || defined(_KMEMUSER) |
|
442 |
||
443 |
extern uint_t x86_feature; |
|
444 |
extern uint_t x86_type; |
|
445 |
extern uint_t x86_vendor; |
|
446 |
||
447 |
extern ulong_t cr4_value; |
|
448 |
extern uint_t pentiumpro_bug4046376; |
|
449 |
extern uint_t pentiumpro_bug4064495; |
|
450 |
||
451 |
extern uint_t enable486; |
|
452 |
||
453 |
extern const char CyrixInstead[]; |
|
454 |
||
455 |
#endif |
|
456 |
||
457 |
#if defined(_KERNEL) |
|
458 |
||
459 |
||
770
0eda482eb80f
6311933 rdmsr/wrmsr do not need to set/pass values via memory pointers
kucharsk
parents:
0
diff
changeset
|
460 |
extern uint64_t rdmsr(uint_t); |
0eda482eb80f
6311933 rdmsr/wrmsr do not need to set/pass values via memory pointers
kucharsk
parents:
0
diff
changeset
|
461 |
extern void wrmsr(uint_t, const uint64_t); |
0 | 462 |
extern void invalidate_cache(void); |
463 |
struct regs; |
|
464 |
extern int mca_exception(struct regs *); |
|
465 |
extern ulong_t getcr4(void); |
|
466 |
extern void setcr4(ulong_t); |
|
467 |
extern void mtrr_sync(void); |
|
468 |
||
469 |
extern void cpu_fast_syscall_enable(void *); |
|
470 |
extern void cpu_fast_syscall_disable(void *); |
|
471 |
||
472 |
struct cpu; |
|
473 |
||
474 |
extern int cpuid_checkpass(struct cpu *, int); |
|
475 |
extern uint32_t cpuid_insn(struct cpu *, |
|
476 |
uint32_t, uint32_t *, uint32_t *, uint32_t *); |
|
477 |
extern uint32_t __cpuid_insn(uint32_t, uint32_t *, uint32_t *, uint32_t *); |
|
478 |
extern int cpuid_getbrandstr(struct cpu *, char *, size_t); |
|
479 |
extern int cpuid_getidstr(struct cpu *, char *, size_t); |
|
480 |
extern const char *cpuid_getvendorstr(struct cpu *); |
|
481 |
extern uint_t cpuid_getvendor(struct cpu *); |
|
482 |
extern uint_t cpuid_getfamily(struct cpu *); |
|
483 |
extern uint_t cpuid_getmodel(struct cpu *); |
|
484 |
extern uint_t cpuid_getstep(struct cpu *); |
|
485 |
extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); |
|
486 |
extern int cpuid_is_ht(struct cpu *); |
|
487 |
extern int cpuid_syscall32_insn(struct cpu *); |
|
488 |
extern int getl2cacheinfo(struct cpu *, int *, int *, int *); |
|
489 |
||
490 |
extern int cpuid_opteron_erratum(struct cpu *, uint_t); |
|
491 |
||
492 |
struct cpuid_info; |
|
493 |
||
494 |
extern void setx86isalist(void); |
|
495 |
extern uint_t cpuid_pass1(struct cpu *); |
|
496 |
extern void cpuid_pass2(struct cpu *); |
|
497 |
extern void cpuid_pass3(struct cpu *); |
|
498 |
extern uint_t cpuid_pass4(struct cpu *); |
|
499 |
extern void add_cpunode2devtree(processorid_t, struct cpuid_info *); |
|
500 |
||
501 |
extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); |
|
502 |
extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); |
|
503 |
||
504 |
extern uint_t workaround_errata(struct cpu *); |
|
505 |
||
506 |
#if defined(OPTERON_ERRATUM_93) |
|
507 |
extern int opteron_erratum_93; |
|
508 |
#endif |
|
509 |
||
510 |
#if defined(OPTERON_ERRATUM_91) |
|
511 |
extern int opteron_erratum_91; |
|
512 |
#endif |
|
513 |
||
514 |
#if defined(OPTERON_ERRATUM_100) |
|
515 |
extern int opteron_erratum_100; |
|
516 |
#endif |
|
517 |
||
518 |
#if defined(OPTERON_ERRATUM_121) |
|
519 |
extern int opteron_erratum_121; |
|
520 |
#endif |
|
521 |
||
522 |
#endif /* _KERNEL */ |
|
523 |
||
524 |
#endif |
|
525 |
||
526 |
#ifdef __cplusplus |
|
527 |
} |
|
528 |
#endif |
|
529 |
||
530 |
#endif /* _SYS_X86_ARCHEXT_H */ |