/*

 * CDDL HEADER START

 *

 * The contents of this file are subject to the terms of the

 * Common Development and Distribution License (the "License").

 * You may not use this file except in compliance with the License.

 *

 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

 * or http://www.opensolaris.org/os/licensing.

 * See the License for the specific language governing permissions

 * and limitations under the License.

 *

 * When distributing Covered Code, include this CDDL HEADER in each

 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.

 * If applicable, add the following below this CDDL HEADER, with the

 * fields enclosed by brackets "[]" replaced with your own identifying

 * information: Portions Copyright [yyyy] [name of copyright owner]

 *

 * CDDL HEADER END

 */

/*

 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.

 */

#include <sys/asm_linkage.h>

#include <sys/asm_misc.h>

#include <sys/regset.h>

#include <sys/privregs.h>

#include <sys/x86_archext.h>

#include <sys/cpr_wakecode.h>

#if !defined(__lint)

#include <sys/segments.h>

#include "assym.h"

#endif

#ifdef  DEBUG

#define LED     1

#define SERIAL  1

#endif	/*	DEBUG	*/

#ifdef	DEBUG

#define	COM1	0x3f8

#define	COM2	0x2f8

#define	WC_COM	COM2	/* either COM1 or COM2			*/

#define	WC_LED	0x80    /* diagnostic led port ON motherboard	*/

/*

 * defined as offsets from the data register

 */

#define	DLL	0	/* divisor latch (lsb) */

#define	DLH	1	/* divisor latch (msb) */

#define	LCR	3	/* line control register		*/

#define	MCR	4	/* modem control register		*/

#define	DLAB	0x80    /* divisor latch access bit		*/

#define	B9600L	0X0c	/* lsb bit pattern for 9600 baud	*/

#define	B9600H	0X0	/* hsb bit pattern for 9600 baud	*/

#define	DTR	0x01    /* Data Terminal Ready			*/

#define	RTS	0x02    /* Request To Send			*/

#define	STOP1	0x00	/* 1 stop bit				*/

#define	BITS8	0x03    /* 8 bits per char			*/

#endif	/*	DEBUG	*/

/*

 *	This file contains the low level routines involved in getting

 *	into and out of ACPI S3, including those needed for restarting

 *	the non-boot cpus.

 *

 *	Our assumptions:

 *

 *	Our actions:

 *

 */

#if defined(lint) || defined(__lint)

/*ARGSUSED*/

int

wc_save_context(wc_cpu_t *pcpu)

{ return 0; }

#else	/* lint */

#if defined(__GNU_AS__)

	NOTHING AT ALL YET!

#else	/* !defined(__GNU_AS__) */

#if defined(__amd64)

	ENTRY_NP(wc_save_context)

	movq	(%rsp), %rdx		/ return address

	movq	%rdx, WC_RETADDR(%rdi)

	pushq	%rbp

	movq	%rsp,%rbp

	movq    %rdi, WC_VIRTADDR(%rdi)

	movq    %rdi, WC_RDI(%rdi)

	movq    %rdx, WC_RDX(%rdi)

/ stash everything else we need

	sgdt	WC_GDT(%rdi)

	sidt	WC_IDT(%rdi)

	sldt	WC_LDT(%rdi)

	str	WC_TR(%rdi)

	movq	%cr0, %rdx

	movq	%rdx, WC_CR0(%rdi)

	movq	%cr3, %rdx

	movq	%rdx, WC_CR3(%rdi)

	movq	%cr4, %rdx

	movq	%rdx, WC_CR4(%rdi)

	movq	%cr8, %rdx

	movq	%rdx, WC_CR8(%rdi)

	movq    %r8, WC_R8(%rdi)

	movq    %r9, WC_R9(%rdi)

	movq    %r10, WC_R10(%rdi)

	movq    %r11, WC_R11(%rdi)

	movq    %r12, WC_R12(%rdi)

	movq    %r13, WC_R13(%rdi)

	movq    %r14, WC_R14(%rdi)

	movq    %r15, WC_R15(%rdi)

	movq    %rax, WC_RAX(%rdi)

	movq    %rbp, WC_RBP(%rdi)

	movq    %rbx, WC_RBX(%rdi)

	movq    %rcx, WC_RCX(%rdi)

	movq    %rsi, WC_RSI(%rdi)

	movq    %rsp, WC_RSP(%rdi)

	movw	%ss, WC_SS(%rdi)

	movw	%cs, WC_CS(%rdi)

	movw	%ds, WC_DS(%rdi)

	movw	%es, WC_ES(%rdi)

	movq	$0, %rcx		/ save %fs register

	movw    %fs, %cx

	movq    %rcx, WC_FS(%rdi)

	movl    $MSR_AMD_FSBASE, %ecx

	rdmsr

	movl    %eax, WC_FSBASE(%rdi)

	movl    %edx, WC_FSBASE+4(%rdi)

	movq	$0, %rcx		/ save %gs register

	movw    %gs, %cx

	movq    %rcx, WC_GS(%rdi)

	movl    $MSR_AMD_GSBASE, %ecx	/ save gsbase msr

	rdmsr

	movl    %eax, WC_GSBASE(%rdi)

	movl    %edx, WC_GSBASE+4(%rdi)

	movl    $MSR_AMD_KGSBASE, %ecx	/ save kgsbase msr

	rdmsr

	movl    %eax, WC_KGSBASE(%rdi)

	movl    %edx, WC_KGSBASE+4(%rdi)

	movq	%gs:CPU_ID, %rax	/ save current cpu id

	movq	%rax, WC_CPU_ID(%rdi)

	pushfq

	popq	WC_EFLAGS(%rdi)

	wbinvd				/ flush the cache

	mfence

	movq	$1, %rax		/ at suspend return 1

	leave

	ret

	SET_SIZE(wc_save_context)

#elif defined(__i386)

	ENTRY_NP(wc_save_context)

	movl	4(%esp), %eax		/ wc_cpu_t *

	movl	%eax, WC_VIRTADDR(%eax)

	movl	(%esp), %edx		/ return address

	movl	%edx, WC_RETADDR(%eax)

	str	WC_TR(%eax)		/ stash everything else we need

	sgdt	WC_GDT(%eax)

	sldt	WC_LDT(%eax)

	sidt	WC_IDT(%eax)

	movl	%cr0, %edx

	movl	%edx, WC_CR0(%eax)

	movl	%cr3, %edx

	movl	%edx, WC_CR3(%eax)

	movl	%cr4, %edx

	movl	%edx, WC_CR4(%eax)

	movl	%ebx, WC_EBX(%eax)

	movl	%edi, WC_EDI(%eax)

	movl	%esi, WC_ESI(%eax)

	movl	%ebp, WC_EBP(%eax)

	movl	%esp, WC_ESP(%eax)

	movw	%ss, WC_SS(%eax)

	movw	%cs, WC_CS(%eax)

	movw	%ds, WC_DS(%eax)

	movw	%es, WC_ES(%eax)

	movw	%fs, WC_FS(%eax)

	movw	%gs, WC_GS(%eax)

	pushfl

	popl	WC_EFLAGS(%eax)

	pushl	%gs:CPU_ID		/ save current cpu id

	popl	WC_CPU_ID(%eax)

	wbinvd				/ flush the cache

	mfence

	movl	$1, %eax		/ at suspend return 1

	ret

	SET_SIZE(wc_save_context)

#endif	/* __amd64 */

#endif	/* __GNU_AS__ */

#endif /* lint */

/*

 *	Our assumptions:

 *		- We are running in real mode.

 *		- Interrupts are disabled.

 *

 *	Our actions:

 *		- We start using our GDT by loading correct values in the

 *		  selector registers (cs=KCS_SEL, ds=es=ss=KDS_SEL, fs=KFS_SEL,

 *		  gs=KGS_SEL).

 *		- We change over to using our IDT.

 *		- We load the default LDT into the hardware LDT register.

 *		- We load the default TSS into the hardware task register.

 *		- We restore registers

 *		- We return to original caller (a la setjmp)

 */

#if defined(lint) || defined(__lint)

void

wc_rm_start(void)

{}

void

wc_rm_end(void)

{}

#else	/* lint */

#if defined(__GNU_AS__)

	NOTHING AT ALL YET!

#else	/* __GNU_AS__ */

#if defined(__amd64)

	ENTRY_NP(wc_rm_start)

	/*

	 * For vulcan as we need to do a .code32 and mentally invert the

	 * meaning of the addr16 and data16 prefixes to get 32-bit access when

	 * generating code to be executed in 16-bit mode (sigh...)

	 */

	.code32

	cli

	movw		%cs, %ax

	movw		%ax, %ds		/ establish ds ...

	movw		%ax, %ss		/ ... and ss:esp

	D16 movl	$WC_STKSTART, %esp

/ using the following value blows up machines! - DO NOT USE

/	D16 movl	0xffc, %esp

#if     LED

	D16 movl        $WC_LED, %edx

	D16 movb        $0xd1, %al

	outb    (%dx)

#endif

#if     SERIAL

	D16 movl        $WC_COM, %edx

	D16 movb        $0x61, %al

	outb    (%dx)

#endif

	D16 call	cominit

	/*

	 * Enable protected-mode, write protect, and alignment mask

	 * %cr0 has already been initialsed to zero

	 */

	movl		%cr0, %eax

	D16 orl		$[CR0_PE|CR0_WP|CR0_AM], %eax

	movl		%eax, %cr0

	/*

	 * Do a jmp immediately after writing to cr0 when enabling protected

	 * mode to clear the real mode prefetch queue (per Intel's docs)

	 */

	jmp		pestart

pestart:

#if     LED

	D16 movl        $WC_LED, %edx

	D16 movb        $0xd2, %al

	outb    (%dx)

#endif

#if     SERIAL

	D16 movl        $WC_COM, %edx

	D16 movb        $0x62, %al

	outb    (%dx)

#endif

	/*

	 * 16-bit protected mode is now active, so prepare to turn on long

	 * mode

	 */

#if     LED

	D16 movl        $WC_LED, %edx

	D16 movb        $0xd3, %al

	outb    (%dx)

#endif

#if     SERIAL

	D16 movl        $WC_COM, %edx

	D16 movb        $0x63, %al

	outb    (%dx)

#endif

	/*

 	 * Add any initial cr4 bits

	 */

	movl		%cr4, %eax

	A16 D16 orl	CR4OFF, %eax

	/*

	 * Enable PAE mode (CR4.PAE)

	 */

	D16 orl		$CR4_PAE, %eax

	movl		%eax, %cr4

#if     LED

	D16 movl        $WC_LED, %edx

	D16 movb        $0xd4, %al

	outb    (%dx)

#endif

#if     SERIAL

	D16 movl        $WC_COM, %edx

	D16 movb        $0x64, %al

	outb    (%dx)

#endif

	/*

	 * Point cr3 to the 64-bit long mode page tables.

	 *

	 * Note that these MUST exist in 32-bit space, as we don't have

	 * a way to load %cr3 with a 64-bit base address for the page tables

	 * until the CPU is actually executing in 64-bit long mode.

	 */

	A16 D16 movl	CR3OFF, %eax

	movl		%eax, %cr3

	/*

	 * Set long mode enable in EFER (EFER.LME = 1)

	 */

	D16 movl	$MSR_AMD_EFER, %ecx

	rdmsr

	D16 orl		$AMD_EFER_LME, %eax

	wrmsr

#if     LED

	D16 movl        $WC_LED, %edx

	D16 movb        $0xd5, %al

	outb    (%dx)

#endif

#if     SERIAL

	D16 movl        $WC_COM, %edx

	D16 movb        $0x65, %al

	outb    (%dx)

#endif

	/*

	 * Finally, turn on paging (CR0.PG = 1) to activate long mode.

	 */

	movl		%cr0, %eax

	D16 orl		$CR0_PG, %eax

	movl		%eax, %cr0

	/*

	 * The instruction after enabling paging in CR0 MUST be a branch.

	 */

	jmp		long_mode_active

long_mode_active:

#if     LED

	D16 movl        $WC_LED, %edx

	D16 movb        $0xd6, %al

	outb    (%dx)

#endif

#if     SERIAL

	D16 movl        $WC_COM, %edx

	D16 movb        $0x66, %al

	outb    (%dx)

#endif

	/*

	 * Long mode is now active but since we're still running with the

	 * original 16-bit CS we're actually in 16-bit compatability mode.

	 *

	 * We have to load an intermediate GDT and IDT here that we know are

	 * in 32-bit space before we can use the kernel's GDT and IDT, which

	 * may be in the 64-bit address space, and since we're in compatability

	 * mode, we only have access to 16 and 32-bit instructions at the

	 * moment.

	 */

	A16 D16 lgdt	TEMPGDTOFF	/* load temporary GDT */

	A16 D16 lidt	TEMPIDTOFF	/* load temporary IDT */

	/*

 	 * Do a far transfer to 64-bit mode.  Set the CS selector to a 64-bit

	 * long mode selector (CS.L=1) in the temporary 32-bit GDT and jump

	 * to the real mode platter address of wc_long_mode_64 as until the

	 * 64-bit CS is in place we don't have access to 64-bit instructions

	 * and thus can't reference a 64-bit %rip.

	 */

#if     LED

	D16 movl        $WC_LED, %edx

	D16 movb        $0xd7, %al

	outb    (%dx)

#endif

#if     SERIAL

	D16 movl        $WC_COM, %edx

	D16 movb        $0x67, %al

	outb    (%dx)

#endif

	D16 	pushl 	$TEMP_CS64_SEL

	A16 D16 pushl	LM64OFF

	D16 lret

/*

 * Support routine to re-initialize VGA subsystem

 */

vgainit:

	D16 ret

/*

 * Support routine to re-initialize keyboard (which is USB - help!)

 */

kbdinit:

	D16 ret

/*

 * Support routine to re-initialize COM ports to something sane

 */

cominit:

	/ init COM1 & COM2

#if     DEBUG

/*

 * on debug kernels we need to initialize COM1 & COM2 here, so that

 * we can get debug output before the asy driver has resumed

 */

/ select COM1

	D16 movl	$[COM1+LCR], %edx

	D16 movb	$DLAB, %al		/ divisor latch

	outb	(%dx)

	D16 movl	$[COM1+DLL], %edx	/ divisor latch lsb

	D16 movb	$B9600L, %al		/ divisor latch

	outb	(%dx)

	D16 movl	$[COM1+DLH], %edx	/ divisor latch hsb

	D16 movb	$B9600H, %al		/ divisor latch

	outb	(%dx)

	D16 movl	$[COM1+LCR], %edx	/ select COM1

	D16 movb	$[STOP1|BITS8], %al	/ 1 stop bit, 8bit word len

	outb	(%dx)

	D16 movl	$[COM1+MCR], %edx	/ select COM1

	D16 movb	$[RTS|DTR], %al		/ data term ready & req to send

	outb	(%dx)

/ select COM2

	D16 movl	$[COM2+LCR], %edx

	D16 movb	$DLAB, %al		/ divisor latch

	outb	(%dx)