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/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License, Version 1.0 only
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* (the "License"). You may not use this file except in compliance
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* with the License.
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*
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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* or http://www.opensolaris.org/os/licensing.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*/
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/*
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* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
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* Use is subject to license terms.
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*/
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#pragma ident "%Z%%M% %I% %E% SMI"
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/*
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* Various routines to handle identification
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* and classification of x86 processors.
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*/
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#include <sys/types.h>
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#include <sys/archsystm.h>
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#include <sys/x86_archext.h>
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#include <sys/kmem.h>
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#include <sys/systm.h>
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#include <sys/cmn_err.h>
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#include <sys/sunddi.h>
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#include <sys/sunndi.h>
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#include <sys/cpuvar.h>
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#include <sys/processor.h>
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#include <sys/chip.h>
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#include <sys/fp.h>
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#include <sys/controlregs.h>
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#include <sys/auxv_386.h>
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#include <sys/bitmap.h>
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#include <sys/controlregs.h>
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#include <sys/memnode.h>
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/*
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* Pass 0 of cpuid feature analysis happens in locore. It contains special code
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* to recognize Cyrix processors that are not cpuid-compliant, and to deal with
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* them accordingly. For most modern processors, feature detection occurs here
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* in pass 1.
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*
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* Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
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* for the boot CPU and does the basic analysis that the early kernel needs.
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* x86_feature is set based on the return value of cpuid_pass1() of the boot
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* CPU.
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*
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* Pass 1 includes:
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*
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* o Determining vendor/model/family/stepping and setting x86_type and
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* x86_vendor accordingly.
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* o Processing the feature flags returned by the cpuid instruction while
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* applying any workarounds or tricks for the specific processor.
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* o Mapping the feature flags into Solaris feature bits (X86_*).
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* o Processing extended feature flags if supported by the processor,
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* again while applying specific processor knowledge.
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* o Determining the CMT characteristics of the system.
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*
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* Pass 1 is done on non-boot CPUs during their initialization and the results
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* are used only as a meager attempt at ensuring that all processors within the
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* system support the same features.
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*
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* Pass 2 of cpuid feature analysis happens just at the beginning
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* of startup(). It just copies in and corrects the remainder
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* of the cpuid data we depend on: standard cpuid functions that we didn't
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* need for pass1 feature analysis, and extended cpuid functions beyond the
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* simple feature processing done in pass1.
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*
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* Pass 3 of cpuid analysis is invoked after basic kernel services; in
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* particular kernel memory allocation has been made available. It creates a
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* readable brand string based on the data collected in the first two passes.
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*
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* Pass 4 of cpuid analysis is invoked after post_startup() when all
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* the support infrastructure for various hardware features has been
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* initialized. It determines which processor features will be reported
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* to userland via the aux vector.
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*
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* All passes are executed on all CPUs, but only the boot CPU determines what
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* features the kernel will use.
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*
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* Much of the worst junk in this file is for the support of processors
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* that didn't really implement the cpuid instruction properly.
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*
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* NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
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* the pass numbers. Accordingly, changes to the pass code may require changes
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* to the accessor code.
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*/
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uint_t x86_feature = 0;
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uint_t x86_vendor = X86_VENDOR_IntelClone;
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uint_t x86_type = X86_TYPE_OTHER;
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ulong_t cr4_value;
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uint_t pentiumpro_bug4046376;
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uint_t pentiumpro_bug4064495;
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uint_t enable486;
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/*
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* This set of strings are for processors rumored to support the cpuid
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* instruction, and is used by locore.s to figure out how to set x86_vendor
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*/
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const char CyrixInstead[] = "CyrixInstead";
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struct cpuidr {
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uint32_t cp_eax;
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uint32_t cp_ebx;
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uint32_t cp_ecx;
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uint32_t cp_edx;
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};
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/*
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* These constants determine how many of the elements of the
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* cpuid we cache in the cpuid_info data structure; the
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* remaining elements are accessible via the cpuid instruction.
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*/
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#define NMAX_CPI_STD 6 /* eax = 0 .. 5 */
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#define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */
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struct cpuid_info {
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uint_t cpi_pass; /* last pass completed */
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/*
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* standard function information
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*/
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uint_t cpi_maxeax; /* fn 0: %eax */
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char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
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uint_t cpi_vendor; /* enum of cpi_vendorstr */
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uint_t cpi_family; /* fn 1: extended family */
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uint_t cpi_model; /* fn 1: extended model */
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uint_t cpi_step; /* fn 1: stepping */
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chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */
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uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
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int cpi_clogid; /* fn 1: %ebx: thread # */
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uint_t cpi_ncpu_per_chip;
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uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
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uint_t cpi_ncache; /* fn 2: number of elements */
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struct cpuidr cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */
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/*
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* extended function information
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*/
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uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */
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char cpi_brandstr[49]; /* fn 0x8000000[234] */
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uint8_t cpi_pabits; /* fn 0x80000006: %eax */
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uint8_t cpi_vabits; /* fn 0x80000006: %eax */
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struct cpuidr cpi_extd[NMAX_CPI_EXTD]; /* 0x80000000 .. 0x80000008 */
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/*
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* supported feature information
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*/
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uint32_t cpi_support[4];
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#define STD_EDX_FEATURES 0
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#define AMD_EDX_FEATURES 1
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#define TM_EDX_FEATURES 2
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#define STD_ECX_FEATURES 3
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};
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static struct cpuid_info cpuid_info0;
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/*
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* These bit fields are defined by the Intel Application Note AP-485
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* "Intel Processor Identification and the CPUID Instruction"
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*/
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#define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
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#define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
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#define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
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#define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
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#define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
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#define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
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#define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
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#define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
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#define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
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#define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
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#define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
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#define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
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#define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
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#define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
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#define CPI_MAXEAX_MAX 0x100 /* sanity control */
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#define CPI_XMAXEAX_MAX 0x80000100
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/*
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* Some undocumented ways of patching the results of the cpuid
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* instruction to permit running Solaris 10 on future cpus that
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* we don't currently support. Could be set to non-zero values
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* via settings in eeprom.
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*/
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uint32_t cpuid_feature_ecx_include;
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uint32_t cpuid_feature_ecx_exclude;
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uint32_t cpuid_feature_edx_include;
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uint32_t cpuid_feature_edx_exclude;
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uint_t
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cpuid_pass1(cpu_t *cpu)
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{
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uint32_t mask_ecx, mask_edx;
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uint_t feature = X86_CPUID;
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struct cpuid_info *cpi;
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struct cpuidr *cp;
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int xcpuid;
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/*
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* By convention, cpu0 is the boot cpu, which is called
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* before memory allocation is available. Other cpus are
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* initialized when memory becomes available.
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*/
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if (cpu->cpu_id == 0)
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cpu->cpu_m.mcpu_cpi = cpi = &cpuid_info0;
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else
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cpu->cpu_m.mcpu_cpi = cpi =
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kmem_zalloc(sizeof (*cpi), KM_SLEEP);
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cp = &cpi->cpi_std[0];
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cp->cp_eax = __cpuid_insn(0, &cp->cp_ebx, &cp->cp_ecx, &cp->cp_edx);
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cpi->cpi_maxeax = cp->cp_eax;
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{
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uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr;
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*iptr++ = cp->cp_ebx;
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*iptr++ = cp->cp_edx;
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*iptr++ = cp->cp_ecx;
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*(char *)&cpi->cpi_vendorstr[12] = '\0';
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}
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/*
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* Map the vendor string to a type code
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*/
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if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0)
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cpi->cpi_vendor = X86_VENDOR_Intel;
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else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0)
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cpi->cpi_vendor = X86_VENDOR_AMD;
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else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0)
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cpi->cpi_vendor = X86_VENDOR_TM;
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else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0)
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/*
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* CyrixInstead is a variable used by the Cyrix detection code
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* in locore.
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*/
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cpi->cpi_vendor = X86_VENDOR_Cyrix;
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else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0)
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cpi->cpi_vendor = X86_VENDOR_UMC;
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else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0)
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cpi->cpi_vendor = X86_VENDOR_NexGen;
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else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0)
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cpi->cpi_vendor = X86_VENDOR_Centaur;
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else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0)
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cpi->cpi_vendor = X86_VENDOR_Rise;
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else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0)
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cpi->cpi_vendor = X86_VENDOR_SiS;
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else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0)
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cpi->cpi_vendor = X86_VENDOR_NSC;
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else
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cpi->cpi_vendor = X86_VENDOR_IntelClone;
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x86_vendor = cpi->cpi_vendor; /* for compatibility */
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/*
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* Limit the range in case of weird hardware
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*/
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if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
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cpi->cpi_maxeax = CPI_MAXEAX_MAX;
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if (cpi->cpi_maxeax < 1)
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goto pass1_done;
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284 |
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cp = &cpi->cpi_std[1];
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cp->cp_eax = __cpuid_insn(1, &cp->cp_ebx, &cp->cp_ecx, &cp->cp_edx);
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287 |
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/*
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* Extract identifying constants for easy access.
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*/
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cpi->cpi_model = CPI_MODEL(cpi);
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cpi->cpi_family = CPI_FAMILY(cpi);
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if (cpi->cpi_family == 0xf) {
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cpi->cpi_family += CPI_FAMILY_XTD(cpi);
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cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
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}
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cpi->cpi_step = CPI_STEP(cpi);
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cpi->cpi_brandid = CPI_BRANDID(cpi);
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/*
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* *default* assumptions:
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* - believe %edx feature word
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* - ignore %ecx feature word
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* - 32-bit virtual and physical addressing
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*/
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308 |
mask_edx = 0xffffffff;
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mask_ecx = 0;
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310 |
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311 |
cpi->cpi_pabits = cpi->cpi_vabits = 32;
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312 |
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313 |
switch (cpi->cpi_vendor) {
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case X86_VENDOR_Intel:
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if (cpi->cpi_family == 5)
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x86_type = X86_TYPE_P5;
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|
317 |
else if (cpi->cpi_family == 6) {
|
|
|
318 |
x86_type = X86_TYPE_P6;
|
|
|
319 |
pentiumpro_bug4046376 = 1;
|
|
|
320 |
pentiumpro_bug4064495 = 1;
|
|
|
321 |
/*
|
|
|
322 |
* Clear the SEP bit when it was set erroneously
|
|
|
323 |
*/
|
|
|
324 |
if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
|
|
|
325 |
cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
|
|
|
326 |
} else if (cpi->cpi_family == 0xf) {
|
|
|
327 |
x86_type = X86_TYPE_P4;
|
|
|
328 |
/*
|
|
|
329 |
* We don't currently depend on any of the %ecx
|
|
|
330 |
* features until Prescott, so we'll only check
|
|
|
331 |
* this from P4 onwards. We might want to revisit
|
|
|
332 |
* that idea later.
|
|
|
333 |
*/
|
|
|
334 |
mask_ecx = 0xffffffff;
|
|
|
335 |
} else if (cpi->cpi_family > 0xf)
|
|
|
336 |
mask_ecx = 0xffffffff;
|
|
|
337 |
break;
|
|
|
338 |
case X86_VENDOR_IntelClone:
|
|
|
339 |
default:
|
|
|
340 |
break;
|
|
|
341 |
case X86_VENDOR_AMD:
|
|
|
342 |
#if defined(OPTERON_ERRATUM_108)
|
|
|
343 |
if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
|
|
|
344 |
cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0;
|
|
|
345 |
cpi->cpi_model = 0xc;
|
|
|
346 |
} else
|
|
|
347 |
#endif
|
|
|
348 |
if (cpi->cpi_family == 5) {
|
|
|
349 |
/*
|
|
|
350 |
* AMD K5 and K6
|
|
|
351 |
*
|
|
|
352 |
* These CPUs have an incomplete implementation
|
|
|
353 |
* of MCA/MCE which we mask away.
|
|
|
354 |
*/
|
|
|
355 |
mask_edx =
|
|
|
356 |
CPUID_INTC_EDX_DE |
|
|
|
357 |
CPUID_INTC_EDX_PSE |
|
|
|
358 |
CPUID_INTC_EDX_TSC |
|
|
|
359 |
CPUID_INTC_EDX_MSR |
|
|
|
360 |
CPUID_INTC_EDX_CX8 |
|
|
|
361 |
CPUID_INTC_EDX_PGE;
|
|
|
362 |
if (cpi->cpi_model == 0) {
|
|
|
363 |
/*
|
|
|
364 |
* Model 0 uses the wrong (APIC) bit
|
|
|
365 |
* to indicate PGE. Fix it here.
|
|
|
366 |
*/
|
|
|
367 |
if (cp->cp_edx & 0x200) {
|
|
|
368 |
cp->cp_edx &= ~0x200;
|
|
|
369 |
cp->cp_edx |= CPUID_INTC_EDX_PGE;
|
|
|
370 |
}
|
|
|
371 |
} else if (cpi->cpi_model >= 6)
|
|
|
372 |
mask_edx |= CPUID_INTC_EDX_MMX;
|
|
|
373 |
}
|
|
|
374 |
break;
|
|
|
375 |
case X86_VENDOR_TM:
|
|
|
376 |
/*
|
|
|
377 |
* workaround the NT workaround in CMS 4.1
|
|
|
378 |
*/
|
|
|
379 |
if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
|
|
|
380 |
(cpi->cpi_step == 2 || cpi->cpi_step == 3))
|
|
|
381 |
cp->cp_edx |= CPUID_INTC_EDX_CX8;
|
|
|
382 |
break;
|
|
|
383 |
case X86_VENDOR_Centaur:
|
|
|
384 |
/*
|
|
|
385 |
* workaround the NT workarounds again
|
|
|
386 |
*/
|
|
|
387 |
if (cpi->cpi_family == 6)
|
|
|
388 |
cp->cp_edx |= CPUID_INTC_EDX_CX8;
|
|
|
389 |
break;
|
|
|
390 |
case X86_VENDOR_Cyrix:
|
|
|
391 |
/*
|
|
|
392 |
* We rely heavily on the probing in locore
|
|
|
393 |
* to actually figure out what parts, if any,
|
|
|
394 |
* of the Cyrix cpuid instruction to believe.
|
|
|
395 |
*/
|
|
|
396 |
switch (x86_type) {
|
|
|
397 |
case X86_TYPE_CYRIX_486:
|
|
|
398 |
mask_edx = 0;
|
|
|
399 |
break;
|
|
|
400 |
case X86_TYPE_CYRIX_6x86:
|
|
|
401 |
mask_edx = 0;
|
|
|
402 |
break;
|
|
|
403 |
case X86_TYPE_CYRIX_6x86L:
|
|
|
404 |
mask_edx =
|
|
|
405 |
CPUID_INTC_EDX_DE |
|
|
|
406 |
CPUID_INTC_EDX_CX8;
|
|
|
407 |
break;
|
|
|
408 |
case X86_TYPE_CYRIX_6x86MX:
|
|
|
409 |
mask_edx =
|
|
|
410 |
CPUID_INTC_EDX_DE |
|
|
|
411 |
CPUID_INTC_EDX_MSR |
|
|
|
412 |
CPUID_INTC_EDX_CX8 |
|
|
|
413 |
CPUID_INTC_EDX_PGE |
|
|
|
414 |
CPUID_INTC_EDX_CMOV |
|
|
|
415 |
CPUID_INTC_EDX_MMX;
|
|
|
416 |
break;
|
|
|
417 |
case X86_TYPE_CYRIX_GXm:
|
|
|
418 |
mask_edx =
|
|
|
419 |
CPUID_INTC_EDX_MSR |
|
|
|
420 |
CPUID_INTC_EDX_CX8 |
|
|
|
421 |
CPUID_INTC_EDX_CMOV |
|
|
|
422 |
CPUID_INTC_EDX_MMX;
|
|
|
423 |
break;
|
|
|
424 |
case X86_TYPE_CYRIX_MediaGX:
|
|
|
425 |
break;
|
|
|
426 |
case X86_TYPE_CYRIX_MII:
|
|
|
427 |
case X86_TYPE_VIA_CYRIX_III:
|
|
|
428 |
mask_edx =
|
|
|
429 |
CPUID_INTC_EDX_DE |
|
|
|
430 |
CPUID_INTC_EDX_TSC |
|
|
|
431 |
CPUID_INTC_EDX_MSR |
|
|
|
432 |
CPUID_INTC_EDX_CX8 |
|
|
|
433 |
CPUID_INTC_EDX_PGE |
|
|
|
434 |
CPUID_INTC_EDX_CMOV |
|
|
|
435 |
CPUID_INTC_EDX_MMX;
|
|
|
436 |
break;
|
|
|
437 |
default:
|
|
|
438 |
break;
|
|
|
439 |
}
|
|
|
440 |
break;
|
|
|
441 |
}
|
|
|
442 |
|
|
|
443 |
/*
|
|
|
444 |
* Now we've figured out the masks that determine
|
|
|
445 |
* which bits we choose to believe, apply the masks
|
|
|
446 |
* to the feature words, then map the kernel's view
|
|
|
447 |
* of these feature words into its feature word.
|
|
|
448 |
*/
|
|
|
449 |
cp->cp_edx &= mask_edx;
|
|
|
450 |
cp->cp_ecx &= mask_ecx;
|
|
|
451 |
|
|
|
452 |
/*
|
|
|
453 |
* fold in fix ups
|
|
|
454 |
*/
|
|
|
455 |
|
|
|
456 |
cp->cp_edx |= cpuid_feature_edx_include;
|
|
|
457 |
cp->cp_edx &= ~cpuid_feature_edx_exclude;
|
|
|
458 |
|
|
|
459 |
|
|
|
460 |
cp->cp_ecx |= cpuid_feature_ecx_include;
|
|
|
461 |
cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
|
|
|
462 |
|
|
|
463 |
if (cp->cp_edx & CPUID_INTC_EDX_PSE)
|
|
|
464 |
feature |= X86_LARGEPAGE;
|
|
|
465 |
if (cp->cp_edx & CPUID_INTC_EDX_TSC)
|
|
|
466 |
feature |= X86_TSC;
|
|
|
467 |
if (cp->cp_edx & CPUID_INTC_EDX_MSR)
|
|
|
468 |
feature |= X86_MSR;
|
|
|
469 |
if (cp->cp_edx & CPUID_INTC_EDX_MTRR)
|
|
|
470 |
feature |= X86_MTRR;
|
|
|
471 |
if (cp->cp_edx & CPUID_INTC_EDX_PGE)
|
|
|
472 |
feature |= X86_PGE;
|
|
|
473 |
if (cp->cp_edx & CPUID_INTC_EDX_CMOV)
|
|
|
474 |
feature |= X86_CMOV;
|
|
|
475 |
if (cp->cp_edx & CPUID_INTC_EDX_MMX)
|
|
|
476 |
feature |= X86_MMX;
|
|
|
477 |
if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
|
|
|
478 |
(cp->cp_edx & CPUID_INTC_EDX_MCA) != 0)
|
|
|
479 |
feature |= X86_MCA;
|
|
|
480 |
if (cp->cp_edx & CPUID_INTC_EDX_PAE)
|
|
|
481 |
feature |= X86_PAE;
|
|
|
482 |
if (cp->cp_edx & CPUID_INTC_EDX_CX8)
|
|
|
483 |
feature |= X86_CX8;
|
|
|
484 |
#if defined(CPUID_INTC_ECX_CX16)
|
|
|
485 |
/*
|
|
|
486 |
* In the July 16 2004 edition of AN 485, Intel rescinded
|
|
|
487 |
* the definition of this bit -- it's now in the "Do not count on
|
|
|
488 |
* their value" category.
|
|
|
489 |
*/
|
|
|
490 |
if (cp->cp_ecx & CPUID_INTC_ECX_CX16)
|
|
|
491 |
feature |= X86_CX16;
|
|
|
492 |
#endif
|
|
|
493 |
if (cp->cp_edx & CPUID_INTC_EDX_PAT)
|
|
|
494 |
feature |= X86_PAT;
|
|
|
495 |
if (cp->cp_edx & CPUID_INTC_EDX_SEP)
|
|
|
496 |
feature |= X86_SEP;
|
|
|
497 |
if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
|
|
|
498 |
/*
|
|
|
499 |
* In our implementation, fxsave/fxrstor
|
|
|
500 |
* are prerequisites before we'll even
|
|
|
501 |
* try and do SSE things.
|
|
|
502 |
*/
|
|
|
503 |
if (cp->cp_edx & CPUID_INTC_EDX_SSE)
|
|
|
504 |
feature |= X86_SSE;
|
|
|
505 |
if (cp->cp_edx & CPUID_INTC_EDX_SSE2)
|
|
|
506 |
feature |= X86_SSE2;
|
|
|
507 |
if (cp->cp_ecx & CPUID_INTC_ECX_SSE3)
|
|
|
508 |
feature |= X86_SSE3;
|
|
|
509 |
}
|
|
|
510 |
if (cp->cp_edx & CPUID_INTC_EDX_DE)
|
|
|
511 |
cr4_value |= CR4_DE;
|
|
|
512 |
|
|
|
513 |
if (feature & X86_PAE)
|
|
|
514 |
cpi->cpi_pabits = 36;
|
|
|
515 |
|
|
|
516 |
/*
|
|
|
517 |
* Hyperthreading configuration is slightly tricky on Intel
|
|
|
518 |
* and pure clones, and even trickier on AMD.
|
|
|
519 |
*
|
|
|
520 |
* (AMD chose to set the HTT bit on their CMP processors,
|
|
|
521 |
* even though they're not actually hyperthreaded. Thus it
|
|
|
522 |
* takes a bit more work to figure out what's really going
|
|
|
523 |
* on ... see the handling of the HTvalid bit below)
|
|
|
524 |
*/
|
|
|
525 |
if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
|
|
|
526 |
cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
|
|
|
527 |
if (cpi->cpi_ncpu_per_chip > 1)
|
|
|
528 |
feature |= X86_HTT;
|
|
|
529 |
}
|
|
|
530 |
|
|
|
531 |
/*
|
|
|
532 |
* Work on the "extended" feature information, doing
|
|
|
533 |
* some basic initialization for cpuid_pass2()
|
|
|
534 |
*/
|
|
|
535 |
xcpuid = 0;
|
|
|
536 |
switch (cpi->cpi_vendor) {
|
|
|
537 |
case X86_VENDOR_Intel:
|
|
|
538 |
if (cpi->cpi_family >= 0xf)
|
|
|
539 |
xcpuid++;
|
|
|
540 |
break;
|
|
|
541 |
case X86_VENDOR_AMD:
|
|
|
542 |
if (cpi->cpi_family > 5 ||
|
|
|
543 |
(cpi->cpi_family == 5 && cpi->cpi_model >= 1))
|
|
|
544 |
xcpuid++;
|
|
|
545 |
break;
|
|
|
546 |
case X86_VENDOR_Cyrix:
|
|
|
547 |
/*
|
|
|
548 |
* Only these Cyrix CPUs are -known- to support
|
|
|
549 |
* extended cpuid operations.
|
|
|
550 |
*/
|
|
|
551 |
if (x86_type == X86_TYPE_VIA_CYRIX_III ||
|
|
|
552 |
x86_type == X86_TYPE_CYRIX_GXm)
|
|
|
553 |
xcpuid++;
|
|
|
554 |
break;
|
|
|
555 |
case X86_VENDOR_Centaur:
|
|
|
556 |
case X86_VENDOR_TM:
|
|
|
557 |
default:
|
|
|
558 |
xcpuid++;
|
|
|
559 |
break;
|
|
|
560 |
}
|
|
|
561 |
|
|
|
562 |
if (xcpuid) {
|
|
|
563 |
cp = &cpi->cpi_extd[0];
|
|
|
564 |
cpi->cpi_xmaxeax = cp->cp_eax = __cpuid_insn(0x80000000,
|
|
|
565 |
&cp->cp_ebx, &cp->cp_ecx, &cp->cp_edx);
|
|
|
566 |
}
|
|
|
567 |
|
|
|
568 |
if (cpi->cpi_xmaxeax & 0x80000000) {
|
|
|
569 |
|
|
|
570 |
if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
|
|
|
571 |
cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
|
|
|
572 |
|
|
|
573 |
switch (cpi->cpi_vendor) {
|
|
|
574 |
case X86_VENDOR_Intel:
|
|
|
575 |
case X86_VENDOR_AMD:
|
|
|
576 |
if (cpi->cpi_xmaxeax < 0x80000001)
|
|
|
577 |
break;
|
|
|
578 |
cp = &cpi->cpi_extd[1];
|
|
|
579 |
cp->cp_eax = __cpuid_insn(0x80000001,
|
|
|
580 |
&cp->cp_ebx, &cp->cp_ecx, &cp->cp_edx);
|
|
|
581 |
if (cpi->cpi_vendor == X86_VENDOR_AMD &&
|
|
|
582 |
cpi->cpi_family == 5 &&
|
|
|
583 |
cpi->cpi_model == 6 &&
|
|
|
584 |
cpi->cpi_step == 6) {
|
|
|
585 |
/*
|
|
|
586 |
* K6 model 6 uses bit 10 to indicate SYSC
|
|
|
587 |
* Later models use bit 11. Fix it here.
|
|
|
588 |
*/
|
|
|
589 |
if (cp->cp_edx & 0x400) {
|
|
|
590 |
cp->cp_edx &= ~0x400;
|
|
|
591 |
cp->cp_edx |= CPUID_AMD_EDX_SYSC;
|
|
|
592 |
}
|
|
|
593 |
}
|
|
|
594 |
|
|
|
595 |
/*
|
|
|
596 |
* Compute the additions to the kernel's feature word.
|
|
|
597 |
*/
|
|
|
598 |
if (cp->cp_edx & CPUID_AMD_EDX_NX)
|
|
|
599 |
feature |= X86_NX;
|
|
|
600 |
|
|
|
601 |
/*
|
|
|
602 |
* Unless both the HTT bit is set, and the
|
|
|
603 |
* HTvalid bit is set, then we're not actually
|
|
|
604 |
* HyperThreaded at all..
|
|
|
605 |
*/
|
|
|
606 |
if (cpi->cpi_vendor == X86_VENDOR_AMD &&
|
|
|
607 |
(feature & X86_HTT) == X86_HTT &&
|
|
|
608 |
(cp->cp_ecx & CPUID_AMD_ECX_HTvalid) == 0)
|
|
|
609 |
feature &= ~X86_HTT;
|
|
|
610 |
#if defined(_LP64)
|
|
|
611 |
/*
|
|
|
612 |
* It's really tricky to support syscall/sysret in
|
|
|
613 |
* the i386 kernel; we rely on sysenter/sysexit
|
|
|
614 |
* instead. In the amd64 kernel, things are -way-
|
|
|
615 |
* better.
|
|
|
616 |
*/
|
|
|
617 |
if (cp->cp_edx & CPUID_AMD_EDX_SYSC)
|
|
|
618 |
feature |= X86_ASYSC;
|
|
|
619 |
|
|
|
620 |
/*
|
|
|
621 |
* While we're thinking about system calls, note
|
|
|
622 |
* that AMD processors don't support sysenter
|
|
|
623 |
* in long mode at all, so don't try to program them.
|
|
|
624 |
*/
|
|
|
625 |
if (x86_vendor == X86_VENDOR_AMD)
|
|
|
626 |
feature &= ~X86_SEP;
|
|
|
627 |
#endif
|
|
|
628 |
break;
|
|
|
629 |
default:
|
|
|
630 |
break;
|
|
|
631 |
}
|
|
|
632 |
|
|
|
633 |
switch (cpi->cpi_vendor) {
|
|
|
634 |
case X86_VENDOR_Intel:
|
|
|
635 |
case X86_VENDOR_AMD:
|
|
|
636 |
if (cpi->cpi_xmaxeax < 0x80000008)
|
|
|
637 |
break;
|
|
|
638 |
cp = &cpi->cpi_extd[8];
|
|
|
639 |
cp->cp_eax = __cpuid_insn(0x80000008,
|
|
|
640 |
&cp->cp_ebx, &cp->cp_ecx, &cp->cp_edx);
|
|
|
641 |
/*
|
|
|
642 |
* Virtual and physical address limits from
|
|
|
643 |
* cpuid override previously guessed values.
|
|
|
644 |
*/
|
|
|
645 |
cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
|
|
|
646 |
cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
|
|
|
647 |
|
|
|
648 |
/*
|
|
|
649 |
* This -might- be a CMP processor?
|
|
|
650 |
*/
|
|
|
651 |
if (cpi->cpi_vendor == X86_VENDOR_AMD) {
|
|
|
652 |
cpi->cpi_ncpu_per_chip =
|
|
|
653 |
1 + BITX(cp->cp_ecx, 7, 0);
|
|
|
654 |
if (cpi->cpi_ncpu_per_chip > 1)
|
|
|
655 |
feature |= X86_CMP;
|
|
|
656 |
}
|
|
|
657 |
break;
|
|
|
658 |
default:
|
|
|
659 |
break;
|
|
|
660 |
}
|
|
|
661 |
}
|
|
|
662 |
|
|
|
663 |
if ((feature & (X86_HTT | X86_CMP)) == 0) {
|
|
|
664 |
cpi->cpi_chipid = -1;
|
|
|
665 |
cpi->cpi_clogid = 0;
|
|
|
666 |
} else if (cpi->cpi_ncpu_per_chip > 1) {
|
|
|
667 |
uint_t i, cid_shift, apic_id;
|
|
|
668 |
|
|
|
669 |
for (i = 1, cid_shift = 0;
|
|
|
670 |
i < cpi->cpi_ncpu_per_chip; i <<= 1)
|
|
|
671 |
cid_shift++;
|
|
|
672 |
apic_id = CPI_APIC_ID(cpi);
|
|
|
673 |
cpi->cpi_chipid = apic_id >> cid_shift;
|
|
|
674 |
cpi->cpi_clogid = apic_id & ((1 << cid_shift) - 1);
|
|
|
675 |
}
|
|
|
676 |
|
|
|
677 |
pass1_done:
|
|
|
678 |
cpi->cpi_pass = 1;
|
|
|
679 |
return (feature);
|
|
|
680 |
}
|
|
|
681 |
|
|
|
682 |
/*
|
|
|
683 |
* Make copies of the cpuid table entries we depend on, in
|
|
|
684 |
* part for ease of parsing now, in part so that we have only
|
|
|
685 |
* one place to correct any of it, in part for ease of
|
|
|
686 |
* later export to userland, and in part so we can look at
|
|
|
687 |
* this stuff in a crash dump.
|
|
|
688 |
*/
|
|
|
689 |
|
|
|
690 |
/*ARGSUSED*/
|
|
|
691 |
void
|
|
|
692 |
cpuid_pass2(cpu_t *cpu)
|
|
|
693 |
{
|
|
|
694 |
uint_t n, nmax;
|
|
|
695 |
int i;
|
|
|
696 |
struct cpuidr *cp;
|
|
|
697 |
uint8_t *dp;
|
|
|
698 |
uint32_t *iptr;
|
|
|
699 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
|
|
|
700 |
|
|
|
701 |
ASSERT(cpi->cpi_pass == 1);
|
|
|
702 |
|
|
|
703 |
if (cpi->cpi_maxeax < 1)
|
|
|
704 |
goto pass2_done;
|
|
|
705 |
|
|
|
706 |
if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
|
|
|
707 |
nmax = NMAX_CPI_STD;
|
|
|
708 |
/*
|
|
|
709 |
* (We already handled n == 0 and n == 1 in pass 1)
|
|
|
710 |
*/
|
|
|
711 |
for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
|
|
|
712 |
cp->cp_eax = __cpuid_insn(n,
|
|
|
713 |
&cp->cp_ebx, &cp->cp_ecx, &cp->cp_edx);
|
|
|
714 |
switch (n) {
|
|
|
715 |
case 2:
|
|
|
716 |
/*
|
|
|
717 |
* "the lower 8 bits of the %eax register
|
|
|
718 |
* contain a value that identifies the number
|
|
|
719 |
* of times the cpuid [instruction] has to be
|
|
|
720 |
* executed to obtain a complete image of the
|
|
|
721 |
* processor's caching systems."
|
|
|
722 |
*
|
|
|
723 |
* How *do* they make this stuff up?
|
|
|
724 |
*/
|
|
|
725 |
cpi->cpi_ncache = sizeof (*cp) *
|
|
|
726 |
BITX(cp->cp_eax, 7, 0);
|
|
|
727 |
if (cpi->cpi_ncache == 0)
|
|
|
728 |
break;
|
|
|
729 |
cpi->cpi_ncache--; /* skip count byte */
|
|
|
730 |
|
|
|
731 |
/*
|
|
|
732 |
* Well, for now, rather than attempt to implement
|
|
|
733 |
* this slightly dubious algorithm, we just look
|
|
|
734 |
* at the first 15 ..
|
|
|
735 |
*/
|
|
|
736 |
if (cpi->cpi_ncache > (sizeof (*cp) - 1))
|
|
|
737 |
cpi->cpi_ncache = sizeof (*cp) - 1;
|
|
|
738 |
|
|
|
739 |
dp = cpi->cpi_cacheinfo;
|
|
|
740 |
if (BITX(cp->cp_eax, 31, 31) == 0) {
|
|
|
741 |
uint8_t *p = (void *)&cp->cp_eax;
|
|
|
742 |
for (i = 1; i < 3; i++)
|
|
|
743 |
if (p[i] != 0)
|
|
|
744 |
*dp++ = p[i];
|
|
|
745 |
}
|
|
|
746 |
if (BITX(cp->cp_ebx, 31, 31) == 0) {
|
|
|
747 |
uint8_t *p = (void *)&cp->cp_ebx;
|
|
|
748 |
for (i = 0; i < 4; i++)
|
|
|
749 |
if (p[i] != 0)
|
|
|
750 |
*dp++ = p[i];
|
|
|
751 |
}
|
|
|
752 |
if (BITX(cp->cp_ecx, 31, 31) == 0) {
|
|
|
753 |
uint8_t *p = (void *)&cp->cp_ecx;
|
|
|
754 |
for (i = 0; i < 4; i++)
|
|
|
755 |
if (p[i] != 0)
|
|
|
756 |
*dp++ = p[i];
|
|
|
757 |
}
|
|
|
758 |
if (BITX(cp->cp_edx, 31, 31) == 0) {
|
|
|
759 |
uint8_t *p = (void *)&cp->cp_edx;
|
|
|
760 |
for (i = 0; i < 4; i++)
|
|
|
761 |
if (p[i] != 0)
|
|
|
762 |
*dp++ = p[i];
|
|
|
763 |
}
|
|
|
764 |
break;
|
|
|
765 |
case 3: /* Processor serial number, if PSN supported */
|
|
|
766 |
case 4: /* Deterministic cache parameters */
|
|
|
767 |
case 5: /* Monitor/Mwait parameters */
|
|
|
768 |
default:
|
|
|
769 |
break;
|
|
|
770 |
}
|
|
|
771 |
}
|
|
|
772 |
|
|
|
773 |
if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
|
|
|
774 |
goto pass2_done;
|
|
|
775 |
|
|
|
776 |
if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
|
|
|
777 |
nmax = NMAX_CPI_EXTD;
|
|
|
778 |
/*
|
|
|
779 |
* Copy the extended properties, fixing them as we go.
|
|
|
780 |
* (We already handled n == 0 and n == 1 in pass 1)
|
|
|
781 |
*/
|
|
|
782 |
iptr = (void *)cpi->cpi_brandstr;
|
|
|
783 |
for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
|
|
|
784 |
cp->cp_eax = __cpuid_insn(n + 0x80000000,
|
|
|
785 |
&cp->cp_ebx, &cp->cp_ecx, &cp->cp_edx);
|
|
|
786 |
switch (n) {
|
|
|
787 |
case 2:
|
|
|
788 |
case 3:
|
|
|
789 |
case 4:
|
|
|
790 |
/*
|
|
|
791 |
* Extract the brand string
|
|
|
792 |
*/
|
|
|
793 |
*iptr++ = cp->cp_eax;
|
|
|
794 |
*iptr++ = cp->cp_ebx;
|
|
|
795 |
*iptr++ = cp->cp_ecx;
|
|
|
796 |
*iptr++ = cp->cp_edx;
|
|
|
797 |
break;
|
|
|
798 |
case 5:
|
|
|
799 |
switch (cpi->cpi_vendor) {
|
|
|
800 |
case X86_VENDOR_AMD:
|
|
|
801 |
/*
|
|
|
802 |
* The Athlon and Duron were the first
|
|
|
803 |
* parts to report the sizes of the
|
|
|
804 |
* TLB for large pages. Before then,
|
|
|
805 |
* we don't trust the data.
|
|
|
806 |
*/
|
|
|
807 |
if (cpi->cpi_family < 6 ||
|
|
|
808 |
(cpi->cpi_family == 6 &&
|
|
|
809 |
cpi->cpi_model < 1))
|
|
|
810 |
cp->cp_eax = 0;
|
|
|
811 |
break;
|
|
|
812 |
default:
|
|
|
813 |
break;
|
|
|
814 |
}
|
|
|
815 |
break;
|
|
|
816 |
case 6:
|
|
|
817 |
switch (cpi->cpi_vendor) {
|
|
|
818 |
case X86_VENDOR_AMD:
|
|
|
819 |
/*
|
|
|
820 |
* The Athlon and Duron were the first
|
|
|
821 |
* AMD parts with L2 TLB's.
|
|
|
822 |
* Before then, don't trust the data.
|
|
|
823 |
*/
|
|
|
824 |
if (cpi->cpi_family < 6 ||
|
|
|
825 |
cpi->cpi_family == 6 &&
|
|
|
826 |
cpi->cpi_model < 1)
|
|
|
827 |
cp->cp_eax = cp->cp_ebx = 0;
|
|
|
828 |
/*
|
|
|
829 |
* AMD Duron rev A0 reports L2
|
|
|
830 |
* cache size incorrectly as 1K
|
|
|
831 |
* when it is really 64K
|
|
|
832 |
*/
|
|
|
833 |
if (cpi->cpi_family == 6 &&
|
|
|
834 |
cpi->cpi_model == 3 &&
|
|
|
835 |
cpi->cpi_step == 0) {
|
|
|
836 |
cp->cp_ecx &= 0xffff;
|
|
|
837 |
cp->cp_ecx |= 0x400000;
|
|
|
838 |
}
|
|
|
839 |
break;
|
|
|
840 |
case X86_VENDOR_Cyrix: /* VIA C3 */
|
|
|
841 |
/*
|
|
|
842 |
* VIA C3 processors are a bit messed
|
|
|
843 |
* up w.r.t. encoding cache sizes in %ecx
|
|
|
844 |
*/
|
|
|
845 |
if (cpi->cpi_family != 6)
|
|
|
846 |
break;
|
|
|
847 |
/*
|
|
|
848 |
* model 7 and 8 were incorrectly encoded
|
|
|
849 |
*
|
|
|
850 |
* xxx is model 8 really broken?
|
|
|
851 |
*/
|
|
|
852 |
if (cpi->cpi_model == 7 ||
|
|
|
853 |
cpi->cpi_model == 8)
|
|
|
854 |
cp->cp_ecx =
|
|
|
855 |
BITX(cp->cp_ecx, 31, 24) << 16 |
|
|
|
856 |
BITX(cp->cp_ecx, 23, 16) << 12 |
|
|
|
857 |
BITX(cp->cp_ecx, 15, 8) << 8 |
|
|
|
858 |
BITX(cp->cp_ecx, 7, 0);
|
|
|
859 |
/*
|
|
|
860 |
* model 9 stepping 1 has wrong associativity
|
|
|
861 |
*/
|
|
|
862 |
if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
|
|
|
863 |
cp->cp_ecx |= 8 << 12;
|
|
|
864 |
break;
|
|
|
865 |
case X86_VENDOR_Intel:
|
|
|
866 |
/*
|
|
|
867 |
* Extended L2 Cache features function.
|
|
|
868 |
* First appeared on Prescott.
|
|
|
869 |
*/
|
|
|
870 |
default:
|
|
|
871 |
break;
|
|
|
872 |
}
|
|
|
873 |
break;
|
|
|
874 |
default:
|
|
|
875 |
break;
|
|
|
876 |
}
|
|
|
877 |
}
|
|
|
878 |
|
|
|
879 |
pass2_done:
|
|
|
880 |
cpi->cpi_pass = 2;
|
|
|
881 |
}
|
|
|
882 |
|
|
|
883 |
static const char *
|
|
|
884 |
intel_cpubrand(const struct cpuid_info *cpi)
|
|
|
885 |
{
|
|
|
886 |
int i;
|
|
|
887 |
|
|
|
888 |
if ((x86_feature & X86_CPUID) == 0 ||
|
|
|
889 |
cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
|
|
|
890 |
return ("i486");
|
|
|
891 |
|
|
|
892 |
switch (cpi->cpi_family) {
|
|
|
893 |
case 5:
|
|
|
894 |
return ("Intel Pentium(r)");
|
|
|
895 |
case 6:
|
|
|
896 |
switch (cpi->cpi_model) {
|
|
|
897 |
uint_t celeron, xeon;
|
|
|
898 |
const struct cpuidr *cp;
|
|
|
899 |
case 0:
|
|
|
900 |
case 1:
|
|
|
901 |
case 2:
|
|
|
902 |
return ("Intel Pentium(r) Pro");
|
|
|
903 |
case 3:
|
|
|
904 |
case 4:
|
|
|
905 |
return ("Intel Pentium(r) II");
|
|
|
906 |
case 6:
|
|
|
907 |
return ("Intel Celeron(r)");
|
|
|
908 |
case 5:
|
|
|
909 |
case 7:
|
|
|
910 |
celeron = xeon = 0;
|
|
|
911 |
cp = &cpi->cpi_std[2]; /* cache info */
|
|
|
912 |
|
|
|
913 |
for (i = 1; i < 3; i++) {
|
|
|
914 |
uint_t tmp;
|
|
|
915 |
|
|
|
916 |
tmp = (cp->cp_eax >> (8 * i)) & 0xff;
|
|
|
917 |
if (tmp == 0x40)
|
|
|
918 |
celeron++;
|
|
|
919 |
if (tmp >= 0x44 && tmp <= 0x45)
|
|
|
920 |
xeon++;
|
|
|
921 |
}
|
|
|
922 |
|
|
|
923 |
for (i = 0; i < 2; i++) {
|
|
|
924 |
uint_t tmp;
|
|
|
925 |
|
|
|
926 |
tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
|
|
|
927 |
if (tmp == 0x40)
|
|
|
928 |
celeron++;
|
|
|
929 |
else if (tmp >= 0x44 && tmp <= 0x45)
|
|
|
930 |
xeon++;
|
|
|
931 |
}
|
|
|
932 |
|
|
|
933 |
for (i = 0; i < 4; i++) {
|
|
|
934 |
uint_t tmp;
|
|
|
935 |
|
|
|
936 |
tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
|
|
|
937 |
if (tmp == 0x40)
|
|
|
938 |
celeron++;
|
|
|
939 |
else if (tmp >= 0x44 && tmp <= 0x45)
|
|
|
940 |
xeon++;
|
|
|
941 |
}
|
|
|
942 |
|
|
|
943 |
for (i = 0; i < 4; i++) {
|
|
|
944 |
uint_t tmp;
|
|
|
945 |
|
|
|
946 |
tmp = (cp->cp_edx >> (8 * i)) & 0xff;
|
|
|
947 |
if (tmp == 0x40)
|
|
|
948 |
celeron++;
|
|
|
949 |
else if (tmp >= 0x44 && tmp <= 0x45)
|
|
|
950 |
xeon++;
|
|
|
951 |
}
|
|
|
952 |
|
|
|
953 |
if (celeron)
|
|
|
954 |
return ("Intel Celeron(r)");
|
|
|
955 |
if (xeon)
|
|
|
956 |
return (cpi->cpi_model == 5 ?
|
|
|
957 |
"Intel Pentium(r) II Xeon(tm)" :
|
|
|
958 |
"Intel Pentium(r) III Xeon(tm)");
|
|
|
959 |
return (cpi->cpi_model == 5 ?
|
|
|
960 |
"Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
|
|
|
961 |
"Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
|
|
|
962 |
default:
|
|
|
963 |
break;
|
|
|
964 |
}
|
|
|
965 |
default:
|
|
|
966 |
break;
|
|
|
967 |
}
|
|
|
968 |
|
|
|
969 |
if (cpi->cpi_family <= 0xf && cpi->cpi_model <= 0xf &&
|
|
|
970 |
cpi->cpi_brandid != 0) {
|
|
|
971 |
static const struct {
|
|
|
972 |
uint_t bt_bid;
|
|
|
973 |
const char *bt_str;
|
|
|
974 |
} brand_tbl[] = {
|
|
|
975 |
{ 0x1, "Intel(r) Celeron(r)" },
|
|
|
976 |
{ 0x2, "Intel(r) Pentium(r) III" },
|
|
|
977 |
{ 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
|
|
|
978 |
{ 0x4, "Intel(r) Pentium(r) III" },
|
|
|
979 |
{ 0x6, "Mobile Intel(r) Pentium(r) III" },
|
|
|
980 |
{ 0x7, "Mobile Intel(r) Celeron(r)" },
|
|
|
981 |
{ 0x8, "Intel(r) Pentium(r) 4" },
|
|
|
982 |
{ 0x9, "Intel(r) Pentium(r) 4" },
|
|
|
983 |
{ 0xa, "Intel(r) Celeron(r)" },
|
|
|
984 |
{ 0xb, "Intel(r) Xeon(tm)" },
|
|
|
985 |
{ 0xc, "Intel(r) Xeon(tm) MP" },
|
|
|
986 |
{ 0xe, "Mobile Intel(r) Pentium(r) 4" },
|
|
|
987 |
{ 0xf, "Mobile Intel(r) Celeron(r)" }
|
|
|
988 |
};
|
|
|
989 |
uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
|
|
|
990 |
uint_t sgn;
|
|
|
991 |
|
|
|
992 |
sgn = (cpi->cpi_family << 8) |
|
|
|
993 |
(cpi->cpi_model << 4) | cpi->cpi_step;
|
|
|
994 |
|
|
|
995 |
for (i = 0; i < btblmax; i++)
|
|
|
996 |
if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
|
|
|
997 |
break;
|
|
|
998 |
if (i < btblmax) {
|
|
|
999 |
if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
|
|
|
1000 |
return ("Intel(r) Celeron(r)");
|
|
|
1001 |
if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
|
|
|
1002 |
return ("Intel(r) Xeon(tm) MP");
|
|
|
1003 |
if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
|
|
|
1004 |
return ("Intel(r) Xeon(tm)");
|
|
|
1005 |
return (brand_tbl[i].bt_str);
|
|
|
1006 |
}
|
|
|
1007 |
}
|
|
|
1008 |
|
|
|
1009 |
return (NULL);
|
|
|
1010 |
}
|
|
|
1011 |
|
|
|
1012 |
static const char *
|
|
|
1013 |
amd_cpubrand(const struct cpuid_info *cpi)
|
|
|
1014 |
{
|
|
|
1015 |
if ((x86_feature & X86_CPUID) == 0 ||
|
|
|
1016 |
cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
|
|
|
1017 |
return ("i486 compatible");
|
|
|
1018 |
|
|
|
1019 |
switch (cpi->cpi_family) {
|
|
|
1020 |
case 5:
|
|
|
1021 |
switch (cpi->cpi_model) {
|
|
|
1022 |
case 0:
|
|
|
1023 |
case 1:
|
|
|
1024 |
case 2:
|
|
|
1025 |
case 3:
|
|
|
1026 |
case 4:
|
|
|
1027 |
case 5:
|
|
|
1028 |
return ("AMD-K5(r)");
|
|
|
1029 |
case 6:
|
|
|
1030 |
case 7:
|
|
|
1031 |
return ("AMD-K6(r)");
|
|
|
1032 |
case 8:
|
|
|
1033 |
return ("AMD-K6(r)-2");
|
|
|
1034 |
case 9:
|
|
|
1035 |
return ("AMD-K6(r)-III");
|
|
|
1036 |
default:
|
|
|
1037 |
return ("AMD (family 5)");
|
|
|
1038 |
}
|
|
|
1039 |
case 6:
|
|
|
1040 |
switch (cpi->cpi_model) {
|
|
|
1041 |
case 1:
|
|
|
1042 |
return ("AMD-K7(tm)");
|
|
|
1043 |
case 0:
|
|
|
1044 |
case 2:
|
|
|
1045 |
case 4:
|
|
|
1046 |
return ("AMD Athlon(tm)");
|
|
|
1047 |
case 3:
|
|
|
1048 |
case 7:
|
|
|
1049 |
return ("AMD Duron(tm)");
|
|
|
1050 |
case 6:
|
|
|
1051 |
case 8:
|
|
|
1052 |
case 10:
|
|
|
1053 |
/*
|
|
|
1054 |
* Use the L2 cache size to distinguish
|
|
|
1055 |
*/
|
|
|
1056 |
return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
|
|
|
1057 |
"AMD Athlon(tm)" : "AMD Duron(tm)");
|
|
|
1058 |
default:
|
|
|
1059 |
return ("AMD (family 6)");
|
|
|
1060 |
}
|
|
|
1061 |
default:
|
|
|
1062 |
break;
|
|
|
1063 |
}
|
|
|
1064 |
|
|
|
1065 |
if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
|
|
|
1066 |
cpi->cpi_brandid != 0) {
|
|
|
1067 |
switch (BITX(cpi->cpi_brandid, 7, 5)) {
|
|
|
1068 |
case 3:
|
|
|
1069 |
return ("AMD Opteron(tm) UP 1xx");
|
|
|
1070 |
case 4:
|
|
|
1071 |
return ("AMD Opteron(tm) DP 2xx");
|
|
|
1072 |
case 5:
|
|
|
1073 |
return ("AMD Opteron(tm) MP 8xx");
|
|
|
1074 |
default:
|
|
|
1075 |
return ("AMD Opteron(tm)");
|
|
|
1076 |
}
|
|
|
1077 |
}
|
|
|
1078 |
|
|
|
1079 |
return (NULL);
|
|
|
1080 |
}
|
|
|
1081 |
|
|
|
1082 |
static const char *
|
|
|
1083 |
cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
|
|
|
1084 |
{
|
|
|
1085 |
if ((x86_feature & X86_CPUID) == 0 ||
|
|
|
1086 |
cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 ||
|
|
|
1087 |
type == X86_TYPE_CYRIX_486)
|
|
|
1088 |
return ("i486 compatible");
|
|
|
1089 |
|
|
|
1090 |
switch (type) {
|
|
|
1091 |
case X86_TYPE_CYRIX_6x86:
|
|
|
1092 |
return ("Cyrix 6x86");
|
|
|
1093 |
case X86_TYPE_CYRIX_6x86L:
|
|
|
1094 |
return ("Cyrix 6x86L");
|
|
|
1095 |
case X86_TYPE_CYRIX_6x86MX:
|
|
|
1096 |
return ("Cyrix 6x86MX");
|
|
|
1097 |
case X86_TYPE_CYRIX_GXm:
|
|
|
1098 |
return ("Cyrix GXm");
|
|
|
1099 |
case X86_TYPE_CYRIX_MediaGX:
|
|
|
1100 |
return ("Cyrix MediaGX");
|
|
|
1101 |
case X86_TYPE_CYRIX_MII:
|
|
|
1102 |
return ("Cyrix M2");
|
|
|
1103 |
case X86_TYPE_VIA_CYRIX_III:
|
|
|
1104 |
return ("VIA Cyrix M3");
|
|
|
1105 |
default:
|
|
|
1106 |
/*
|
|
|
1107 |
* Have another wild guess ..
|
|
|
1108 |
*/
|
|
|
1109 |
if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
|
|
|
1110 |
return ("Cyrix 5x86");
|
|
|
1111 |
else if (cpi->cpi_family == 5) {
|
|
|
1112 |
switch (cpi->cpi_model) {
|
|
|
1113 |
case 2:
|
|
|
1114 |
return ("Cyrix 6x86"); /* Cyrix M1 */
|
|
|
1115 |
case 4:
|
|
|
1116 |
return ("Cyrix MediaGX");
|
|
|
1117 |
default:
|
|
|
1118 |
break;
|
|
|
1119 |
}
|
|
|
1120 |
} else if (cpi->cpi_family == 6) {
|
|
|
1121 |
switch (cpi->cpi_model) {
|
|
|
1122 |
case 0:
|
|
|
1123 |
return ("Cyrix 6x86MX"); /* Cyrix M2? */
|
|
|
1124 |
case 5:
|
|
|
1125 |
case 6:
|
|
|
1126 |
case 7:
|
|
|
1127 |
case 8:
|
|
|
1128 |
case 9:
|
|
|
1129 |
return ("VIA C3");
|
|
|
1130 |
default:
|
|
|
1131 |
break;
|
|
|
1132 |
}
|
|
|
1133 |
}
|
|
|
1134 |
break;
|
|
|
1135 |
}
|
|
|
1136 |
return (NULL);
|
|
|
1137 |
}
|
|
|
1138 |
|
|
|
1139 |
/*
|
|
|
1140 |
* This only gets called in the case that the CPU extended
|
|
|
1141 |
* feature brand string (0x80000002, 0x80000003, 0x80000004)
|
|
|
1142 |
* aren't available, or contain null bytes for some reason.
|
|
|
1143 |
*/
|
|
|
1144 |
static void
|
|
|
1145 |
fabricate_brandstr(struct cpuid_info *cpi)
|
|
|
1146 |
{
|
|
|
1147 |
const char *brand = NULL;
|
|
|
1148 |
|
|
|
1149 |
switch (cpi->cpi_vendor) {
|
|
|
1150 |
case X86_VENDOR_Intel:
|
|
|
1151 |
brand = intel_cpubrand(cpi);
|
|
|
1152 |
break;
|
|
|
1153 |
case X86_VENDOR_AMD:
|
|
|
1154 |
brand = amd_cpubrand(cpi);
|
|
|
1155 |
break;
|
|
|
1156 |
case X86_VENDOR_Cyrix:
|
|
|
1157 |
brand = cyrix_cpubrand(cpi, x86_type);
|
|
|
1158 |
break;
|
|
|
1159 |
case X86_VENDOR_NexGen:
|
|
|
1160 |
if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
|
|
|
1161 |
brand = "NexGen Nx586";
|
|
|
1162 |
break;
|
|
|
1163 |
case X86_VENDOR_Centaur:
|
|
|
1164 |
if (cpi->cpi_family == 5)
|
|
|
1165 |
switch (cpi->cpi_model) {
|
|
|
1166 |
case 4:
|
|
|
1167 |
brand = "Centaur C6";
|
|
|
1168 |
break;
|
|
|
1169 |
case 8:
|
|
|
1170 |
brand = "Centaur C2";
|
|
|
1171 |
break;
|
|
|
1172 |
case 9:
|
|
|
1173 |
brand = "Centaur C3";
|
|
|
1174 |
break;
|
|
|
1175 |
default:
|
|
|
1176 |
break;
|
|
|
1177 |
}
|
|
|
1178 |
break;
|
|
|
1179 |
case X86_VENDOR_Rise:
|
|
|
1180 |
if (cpi->cpi_family == 5 &&
|
|
|
1181 |
(cpi->cpi_model == 0 || cpi->cpi_model == 2))
|
|
|
1182 |
brand = "Rise mP6";
|
|
|
1183 |
break;
|
|
|
1184 |
case X86_VENDOR_SiS:
|
|
|
1185 |
if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
|
|
|
1186 |
brand = "SiS 55x";
|
|
|
1187 |
break;
|
|
|
1188 |
case X86_VENDOR_TM:
|
|
|
1189 |
if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
|
|
|
1190 |
brand = "Transmeta Crusoe TM3x00 or TM5x00";
|
|
|
1191 |
break;
|
|
|
1192 |
case X86_VENDOR_NSC:
|
|
|
1193 |
case X86_VENDOR_UMC:
|
|
|
1194 |
default:
|
|
|
1195 |
break;
|
|
|
1196 |
}
|
|
|
1197 |
if (brand) {
|
|
|
1198 |
(void) strcpy((char *)cpi->cpi_brandstr, brand);
|
|
|
1199 |
return;
|
|
|
1200 |
}
|
|
|
1201 |
|
|
|
1202 |
/*
|
|
|
1203 |
* If all else fails ...
|
|
|
1204 |
*/
|
|
|
1205 |
(void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
|
|
|
1206 |
"%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
|
|
|
1207 |
cpi->cpi_model, cpi->cpi_step);
|
|
|
1208 |
}
|
|
|
1209 |
|
|
|
1210 |
/*
|
|
|
1211 |
* This routine is called just after kernel memory allocation
|
|
|
1212 |
* becomes available on cpu0, and as part of mp_startup() on
|
|
|
1213 |
* the other cpus.
|
|
|
1214 |
*
|
|
|
1215 |
* Fixup the brand string.
|
|
|
1216 |
*/
|
|
|
1217 |
/*ARGSUSED*/
|
|
|
1218 |
void
|
|
|
1219 |
cpuid_pass3(cpu_t *cpu)
|
|
|
1220 |
{
|
|
|
1221 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
|
|
|
1222 |
|
|
|
1223 |
ASSERT(cpi->cpi_pass == 2);
|
|
|
1224 |
|
|
|
1225 |
if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
|
|
|
1226 |
fabricate_brandstr(cpi);
|
|
|
1227 |
goto pass3_done;
|
|
|
1228 |
}
|
|
|
1229 |
|
|
|
1230 |
/*
|
|
|
1231 |
* If we successfully extracted a brand string from the cpuid
|
|
|
1232 |
* instruction, clean it up by removing leading spaces and
|
|
|
1233 |
* similar junk.
|
|
|
1234 |
*/
|
|
|
1235 |
if (cpi->cpi_brandstr[0]) {
|
|
|
1236 |
size_t maxlen = sizeof (cpi->cpi_brandstr);
|
|
|
1237 |
char *src, *dst;
|
|
|
1238 |
|
|
|
1239 |
dst = src = (char *)cpi->cpi_brandstr;
|
|
|
1240 |
src[maxlen - 1] = '\0';
|
|
|
1241 |
/*
|
|
|
1242 |
* strip leading spaces
|
|
|
1243 |
*/
|
|
|
1244 |
while (*src == ' ')
|
|
|
1245 |
src++;
|
|
|
1246 |
/*
|
|
|
1247 |
* Remove any 'Genuine' or "Authentic" prefixes
|
|
|
1248 |
*/
|
|
|
1249 |
if (strncmp(src, "Genuine ", 8) == 0)
|
|
|
1250 |
src += 8;
|
|
|
1251 |
if (strncmp(src, "Authentic ", 10) == 0)
|
|
|
1252 |
src += 10;
|
|
|
1253 |
|
|
|
1254 |
/*
|
|
|
1255 |
* Now do an in-place copy.
|
|
|
1256 |
* Map (R) to (r) and (TM) to (tm).
|
|
|
1257 |
* The era of teletypes is long gone, and there's
|
|
|
1258 |
* -really- no need to shout.
|
|
|
1259 |
*/
|
|
|
1260 |
while (*src != '\0') {
|
|
|
1261 |
if (src[0] == '(') {
|
|
|
1262 |
if (strncmp(src + 1, "R)", 2) == 0) {
|
|
|
1263 |
(void) strncpy(dst, "(r)", 3);
|
|
|
1264 |
src += 3;
|
|
|
1265 |
dst += 3;
|
|
|
1266 |
continue;
|
|
|
1267 |
}
|
|
|
1268 |
if (strncmp(src + 1, "TM)", 3) == 0) {
|
|
|
1269 |
(void) strncpy(dst, "(tm)", 4);
|
|
|
1270 |
src += 4;
|
|
|
1271 |
dst += 4;
|
|
|
1272 |
continue;
|
|
|
1273 |
}
|
|
|
1274 |
}
|
|
|
1275 |
*dst++ = *src++;
|
|
|
1276 |
}
|
|
|
1277 |
*dst = '\0';
|
|
|
1278 |
|
|
|
1279 |
/*
|
|
|
1280 |
* Finally, remove any trailing spaces
|
|
|
1281 |
*/
|
|
|
1282 |
while (--dst > cpi->cpi_brandstr)
|
|
|
1283 |
if (*dst == ' ')
|
|
|
1284 |
*dst = '\0';
|
|
|
1285 |
else
|
|
|
1286 |
break;
|
|
|
1287 |
} else
|
|
|
1288 |
fabricate_brandstr(cpi);
|
|
|
1289 |
|
|
|
1290 |
pass3_done:
|
|
|
1291 |
cpi->cpi_pass = 3;
|
|
|
1292 |
}
|
|
|
1293 |
|
|
|
1294 |
/*
|
|
|
1295 |
* This routine is called out of bind_hwcap() much later in the life
|
|
|
1296 |
* of the kernel (post_startup()). The job of this routine is to resolve
|
|
|
1297 |
* the hardware feature support and kernel support for those features into
|
|
|
1298 |
* what we're actually going to tell applications via the aux vector.
|
|
|
1299 |
*/
|
|
|
1300 |
uint_t
|
|
|
1301 |
cpuid_pass4(cpu_t *cpu)
|
|
|
1302 |
{
|
|
|
1303 |
struct cpuid_info *cpi;
|
|
|
1304 |
uint_t hwcap_flags = 0;
|
|
|
1305 |
|
|
|
1306 |
if (cpu == NULL)
|
|
|
1307 |
cpu = CPU;
|
|
|
1308 |
cpi = cpu->cpu_m.mcpu_cpi;
|
|
|
1309 |
|
|
|
1310 |
ASSERT(cpi->cpi_pass == 3);
|
|
|
1311 |
|
|
|
1312 |
if (cpi->cpi_maxeax >= 1) {
|
|
|
1313 |
uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
|
|
|
1314 |
uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
|
|
|
1315 |
|
|
|
1316 |
*edx = CPI_FEATURES_EDX(cpi);
|
|
|
1317 |
*ecx = CPI_FEATURES_ECX(cpi);
|
|
|
1318 |
|
|
|
1319 |
/*
|
|
|
1320 |
* [these require explicit kernel support]
|
|
|
1321 |
*/
|
|
|
1322 |
if ((x86_feature & X86_SEP) == 0)
|
|
|
1323 |
*edx &= ~CPUID_INTC_EDX_SEP;
|
|
|
1324 |
|
|
|
1325 |
if ((x86_feature & X86_SSE) == 0)
|
|
|
1326 |
*edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE);
|
|
|
1327 |
if ((x86_feature & X86_SSE2) == 0)
|
|
|
1328 |
*edx &= ~CPUID_INTC_EDX_SSE2;
|
|
|
1329 |
|
|
|
1330 |
if ((x86_feature & X86_HTT) == 0)
|
|
|
1331 |
*edx &= ~CPUID_INTC_EDX_HTT;
|
|
|
1332 |
|
|
|
1333 |
if ((x86_feature & X86_SSE3) == 0)
|
|
|
1334 |
*ecx &= ~CPUID_INTC_ECX_SSE3;
|
|
|
1335 |
|
|
|
1336 |
/*
|
|
|
1337 |
* [no explicit support required beyond x87 fp context]
|
|
|
1338 |
*/
|
|
|
1339 |
if (!fpu_exists)
|
|
|
1340 |
*edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX);
|
|
|
1341 |
|
|
|
1342 |
/*
|
|
|
1343 |
* Now map the supported feature vector to things that we
|
|
|
1344 |
* think userland will care about.
|
|
|
1345 |
*/
|
|
|
1346 |
if (*edx & CPUID_INTC_EDX_SEP)
|
|
|
1347 |
hwcap_flags |= AV_386_SEP;
|
|
|
1348 |
if (*edx & CPUID_INTC_EDX_SSE)
|
|
|
1349 |
hwcap_flags |= AV_386_FXSR | AV_386_SSE;
|
|
|
1350 |
if (*edx & CPUID_INTC_EDX_SSE2)
|
|
|
1351 |
hwcap_flags |= AV_386_SSE2;
|
|
|
1352 |
if (*ecx & CPUID_INTC_ECX_SSE3)
|
|
|
1353 |
hwcap_flags |= AV_386_SSE3;
|
|
|
1354 |
|
|
|
1355 |
if (*edx & CPUID_INTC_EDX_FPU)
|
|
|
1356 |
hwcap_flags |= AV_386_FPU;
|
|
|
1357 |
if (*edx & CPUID_INTC_EDX_MMX)
|
|
|
1358 |
hwcap_flags |= AV_386_MMX;
|
|
|
1359 |
|
|
|
1360 |
if (*edx & CPUID_INTC_EDX_TSC)
|
|
|
1361 |
hwcap_flags |= AV_386_TSC;
|
|
|
1362 |
if (*edx & CPUID_INTC_EDX_CX8)
|
|
|
1363 |
hwcap_flags |= AV_386_CX8;
|
|
|
1364 |
if (*edx & CPUID_INTC_EDX_CMOV)
|
|
|
1365 |
hwcap_flags |= AV_386_CMOV;
|
|
|
1366 |
if (*ecx & CPUID_INTC_ECX_MON)
|
|
|
1367 |
hwcap_flags |= AV_386_MON;
|
|
|
1368 |
#if defined(CPUID_INTC_ECX_CX16)
|
|
|
1369 |
if (*ecx & CPUID_INTC_ECX_CX16)
|
|
|
1370 |
hwcap_flags |= AV_386_CX16;
|
|
|
1371 |
#endif
|
|
|
1372 |
}
|
|
|
1373 |
|
|
|
1374 |
if (cpuid_is_ht(cpu))
|
|
|
1375 |
hwcap_flags |= AV_386_PAUSE;
|
|
|
1376 |
|
|
|
1377 |
if (cpi->cpi_xmaxeax < 0x80000001)
|
|
|
1378 |
goto pass4_done;
|
|
|
1379 |
|
|
|
1380 |
switch (cpi->cpi_vendor) {
|
|
|
1381 |
uint32_t junk, *edx;
|
|
|
1382 |
|
|
|
1383 |
case X86_VENDOR_Intel: /* sigh */
|
|
|
1384 |
case X86_VENDOR_AMD:
|
|
|
1385 |
edx = &cpi->cpi_support[AMD_EDX_FEATURES];
|
|
|
1386 |
|
|
|
1387 |
*edx = CPI_FEATURES_XTD_EDX(cpi);
|
|
|
1388 |
|
|
|
1389 |
/*
|
|
|
1390 |
* [no explicit support required beyond
|
|
|
1391 |
* x87 fp context and exception handlers]
|
|
|
1392 |
*/
|
|
|
1393 |
if (!fpu_exists)
|
|
|
1394 |
*edx &= ~(CPUID_AMD_EDX_MMXamd |
|
|
|
1395 |
CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx);
|
|
|
1396 |
|
|
|
1397 |
if ((x86_feature & X86_ASYSC) == 0)
|
|
|
1398 |
*edx &= ~CPUID_AMD_EDX_SYSC;
|
|
|
1399 |
if ((x86_feature & X86_NX) == 0)
|
|
|
1400 |
*edx &= ~CPUID_AMD_EDX_NX;
|
|
|
1401 |
#if !defined(_LP64)
|
|
|
1402 |
*edx &= ~CPUID_AMD_EDX_LM;
|
|
|
1403 |
#endif
|
|
|
1404 |
/*
|
|
|
1405 |
* Now map the supported feature vector to
|
|
|
1406 |
* things that we think userland will care about.
|
|
|
1407 |
*/
|
|
|
1408 |
if (*edx & CPUID_AMD_EDX_SYSC)
|
|
|
1409 |
hwcap_flags |= AV_386_AMD_SYSC;
|
|
|
1410 |
if (*edx & CPUID_AMD_EDX_MMXamd)
|
|
|
1411 |
hwcap_flags |= AV_386_AMD_MMX;
|
|
|
1412 |
if (*edx & CPUID_AMD_EDX_3DNow)
|
|
|
1413 |
hwcap_flags |= AV_386_AMD_3DNow;
|
|
|
1414 |
if (*edx & CPUID_AMD_EDX_3DNowx)
|
|
|
1415 |
hwcap_flags |= AV_386_AMD_3DNowx;
|
|
|
1416 |
break;
|
|
|
1417 |
|
|
|
1418 |
case X86_VENDOR_TM:
|
|
|
1419 |
edx = &cpi->cpi_support[TM_EDX_FEATURES];
|
|
|
1420 |
(void) __cpuid_insn(0x80860001, &junk, &junk, edx);
|
|
|
1421 |
break;
|
|
|
1422 |
|
|
|
1423 |
default:
|
|
|
1424 |
break;
|
|
|
1425 |
}
|
|
|
1426 |
|
|
|
1427 |
pass4_done:
|
|
|
1428 |
cpi->cpi_pass = 4;
|
|
|
1429 |
return (hwcap_flags);
|
|
|
1430 |
}
|
|
|
1431 |
|
|
|
1432 |
|
|
|
1433 |
/*
|
|
|
1434 |
* Simulate the cpuid instruction using the data we previously
|
|
|
1435 |
* captured about this CPU. We try our best to return the truth
|
|
|
1436 |
* about the hardware, independently of kernel support.
|
|
|
1437 |
*/
|
|
|
1438 |
uint32_t
|
|
|
1439 |
cpuid_insn(cpu_t *cpu,
|
|
|
1440 |
uint32_t eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
|
|
|
1441 |
{
|
|
|
1442 |
struct cpuid_info *cpi;
|
|
|
1443 |
struct cpuidr *cp;
|
|
|
1444 |
|
|
|
1445 |
if (cpu == NULL)
|
|
|
1446 |
cpu = CPU;
|
|
|
1447 |
cpi = cpu->cpu_m.mcpu_cpi;
|
|
|
1448 |
|
|
|
1449 |
ASSERT(cpuid_checkpass(cpu, 3));
|
|
|
1450 |
|
|
|
1451 |
/*
|
|
|
1452 |
* CPUID data is cached in two separate places: cpi_std for standard
|
|
|
1453 |
* CPUID functions, and cpi_extd for extended CPUID functions.
|
|
|
1454 |
*/
|
|
|
1455 |
if (eax <= cpi->cpi_maxeax && eax < NMAX_CPI_STD)
|
|
|
1456 |
cp = &cpi->cpi_std[eax];
|
|
|
1457 |
else if (eax >= 0x80000000 && eax <= cpi->cpi_xmaxeax &&
|
|
|
1458 |
eax < 0x80000000 + NMAX_CPI_EXTD)
|
|
|
1459 |
cp = &cpi->cpi_extd[eax - 0x80000000];
|
|
|
1460 |
else
|
|
|
1461 |
/*
|
|
|
1462 |
* The caller is asking for data from an input parameter which
|
|
|
1463 |
* the kernel has not cached. In this case we go fetch from
|
|
|
1464 |
* the hardware and return the data directly to the user.
|
|
|
1465 |
*/
|
|
|
1466 |
return (__cpuid_insn(eax, ebx, ecx, edx));
|
|
|
1467 |
*ebx = cp->cp_ebx;
|
|
|
1468 |
*ecx = cp->cp_ecx;
|
|
|
1469 |
*edx = cp->cp_edx;
|
|
|
1470 |
return (cp->cp_eax);
|
|
|
1471 |
}
|
|
|
1472 |
|
|
|
1473 |
int
|
|
|
1474 |
cpuid_checkpass(cpu_t *cpu, int pass)
|
|
|
1475 |
{
|
|
|
1476 |
return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
|
|
|
1477 |
cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
|
|
|
1478 |
}
|
|
|
1479 |
|
|
|
1480 |
int
|
|
|
1481 |
cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n)
|
|
|
1482 |
{
|
|
|
1483 |
ASSERT(cpuid_checkpass(cpu, 3));
|
|
|
1484 |
|
|
|
1485 |
return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
|
|
|
1486 |
}
|
|
|
1487 |
|
|
|
1488 |
int
|
|
|
1489 |
cpuid_is_ht(cpu_t *cpu)
|
|
|
1490 |
{
|
|
|
1491 |
if (cpu == NULL)
|
|
|
1492 |
cpu = CPU;
|
|
|
1493 |
|
|
|
1494 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1495 |
|
|
|
1496 |
return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
|
|
|
1497 |
}
|
|
|
1498 |
|
|
|
1499 |
/*
|
|
|
1500 |
* AMD and Intel both implement the 64-bit variant of the syscall
|
|
|
1501 |
* instruction (syscallq), so if there's -any- support for syscall,
|
|
|
1502 |
* cpuid currently says "yes, we support this".
|
|
|
1503 |
*
|
|
|
1504 |
* However, Intel decided to -not- implement the 32-bit variant of the
|
|
|
1505 |
* syscall instruction, so we provide a predicate to allow our caller
|
|
|
1506 |
* to test that subtlety here.
|
|
|
1507 |
*/
|
|
|
1508 |
/*ARGSUSED*/
|
|
|
1509 |
int
|
|
|
1510 |
cpuid_syscall32_insn(cpu_t *cpu)
|
|
|
1511 |
{
|
|
|
1512 |
ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
|
|
|
1513 |
|
|
|
1514 |
if (x86_feature & X86_ASYSC)
|
|
|
1515 |
return (x86_vendor != X86_VENDOR_Intel);
|
|
|
1516 |
return (0);
|
|
|
1517 |
}
|
|
|
1518 |
|
|
|
1519 |
int
|
|
|
1520 |
cpuid_getidstr(cpu_t *cpu, char *s, size_t n)
|
|
|
1521 |
{
|
|
|
1522 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
|
|
|
1523 |
|
|
|
1524 |
static const char fmt[] =
|
|
|
1525 |
"x86 (%s family %d model %d step %d clock %d MHz)";
|
|
|
1526 |
static const char fmt_ht[] =
|
|
|
1527 |
"x86 (chipid 0x%x %s family %d model %d step %d clock %d MHz)";
|
|
|
1528 |
|
|
|
1529 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1530 |
|
|
|
1531 |
if (cpuid_is_ht(cpu))
|
|
|
1532 |
return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
|
|
|
1533 |
cpi->cpi_vendorstr, cpi->cpi_family, cpi->cpi_model,
|
|
|
1534 |
cpi->cpi_step, cpu->cpu_type_info.pi_clock));
|
|
|
1535 |
return (snprintf(s, n, fmt,
|
|
|
1536 |
cpi->cpi_vendorstr, cpi->cpi_family, cpi->cpi_model,
|
|
|
1537 |
cpi->cpi_step, cpu->cpu_type_info.pi_clock));
|
|
|
1538 |
}
|
|
|
1539 |
|
|
|
1540 |
const char *
|
|
|
1541 |
cpuid_getvendorstr(cpu_t *cpu)
|
|
|
1542 |
{
|
|
|
1543 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1544 |
return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
|
|
|
1545 |
}
|
|
|
1546 |
|
|
|
1547 |
uint_t
|
|
|
1548 |
cpuid_getvendor(cpu_t *cpu)
|
|
|
1549 |
{
|
|
|
1550 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1551 |
return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
|
|
|
1552 |
}
|
|
|
1553 |
|
|
|
1554 |
uint_t
|
|
|
1555 |
cpuid_getfamily(cpu_t *cpu)
|
|
|
1556 |
{
|
|
|
1557 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1558 |
return (cpu->cpu_m.mcpu_cpi->cpi_family);
|
|
|
1559 |
}
|
|
|
1560 |
|
|
|
1561 |
uint_t
|
|
|
1562 |
cpuid_getmodel(cpu_t *cpu)
|
|
|
1563 |
{
|
|
|
1564 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1565 |
return (cpu->cpu_m.mcpu_cpi->cpi_model);
|
|
|
1566 |
}
|
|
|
1567 |
|
|
|
1568 |
uint_t
|
|
|
1569 |
cpuid_get_ncpu_per_chip(cpu_t *cpu)
|
|
|
1570 |
{
|
|
|
1571 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1572 |
return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
|
|
|
1573 |
}
|
|
|
1574 |
|
|
|
1575 |
uint_t
|
|
|
1576 |
cpuid_getstep(cpu_t *cpu)
|
|
|
1577 |
{
|
|
|
1578 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1579 |
return (cpu->cpu_m.mcpu_cpi->cpi_step);
|
|
|
1580 |
}
|
|
|
1581 |
|
|
|
1582 |
chipid_t
|
|
|
1583 |
chip_plat_get_chipid(cpu_t *cpu)
|
|
|
1584 |
{
|
|
|
1585 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1586 |
|
|
|
1587 |
if (cpuid_is_ht(cpu))
|
|
|
1588 |
return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
|
|
|
1589 |
return (cpu->cpu_id);
|
|
|
1590 |
}
|
|
|
1591 |
|
|
|
1592 |
int
|
|
|
1593 |
chip_plat_get_clogid(cpu_t *cpu)
|
|
|
1594 |
{
|
|
|
1595 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1596 |
return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
|
|
|
1597 |
}
|
|
|
1598 |
|
|
|
1599 |
void
|
|
|
1600 |
cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits)
|
|
|
1601 |
{
|
|
|
1602 |
struct cpuid_info *cpi;
|
|
|
1603 |
|
|
|
1604 |
if (cpu == NULL)
|
|
|
1605 |
cpu = CPU;
|
|
|
1606 |
cpi = cpu->cpu_m.mcpu_cpi;
|
|
|
1607 |
|
|
|
1608 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1609 |
|
|
|
1610 |
if (pabits)
|
|
|
1611 |
*pabits = cpi->cpi_pabits;
|
|
|
1612 |
if (vabits)
|
|
|
1613 |
*vabits = cpi->cpi_vabits;
|
|
|
1614 |
}
|
|
|
1615 |
|
|
|
1616 |
/*
|
|
|
1617 |
* Returns the number of data TLB entries for a corresponding
|
|
|
1618 |
* pagesize. If it can't be computed, or isn't known, the
|
|
|
1619 |
* routine returns zero. If you ask about an architecturally
|
|
|
1620 |
* impossible pagesize, the routine will panic (so that the
|
|
|
1621 |
* hat implementor knows that things are inconsistent.)
|
|
|
1622 |
*/
|
|
|
1623 |
uint_t
|
|
|
1624 |
cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
|
|
|
1625 |
{
|
|
|
1626 |
struct cpuid_info *cpi;
|
|
|
1627 |
uint_t dtlb_nent = 0;
|
|
|
1628 |
|
|
|
1629 |
if (cpu == NULL)
|
|
|
1630 |
cpu = CPU;
|
|
|
1631 |
cpi = cpu->cpu_m.mcpu_cpi;
|
|
|
1632 |
|
|
|
1633 |
ASSERT(cpuid_checkpass(cpu, 1));
|
|
|
1634 |
|
|
|
1635 |
/*
|
|
|
1636 |
* Check the L2 TLB info
|
|
|
1637 |
*/
|
|
|
1638 |
if (cpi->cpi_xmaxeax >= 0x80000006) {
|
|
|
1639 |
struct cpuidr *cp = &cpi->cpi_extd[6];
|
|
|
1640 |
|
|
|
1641 |
switch (pagesize) {
|
|
|
1642 |
|
|
|
1643 |
case 4 * 1024:
|
|
|
1644 |
/*
|
|
|
1645 |
* All zero in the top 16 bits of the register
|
|
|
1646 |
* indicates a unified TLB. Size is in low 16 bits.
|
|
|
1647 |
*/
|
|
|
1648 |
if ((cp->cp_ebx & 0xffff0000) == 0)
|
|
|
1649 |
dtlb_nent = cp->cp_ebx & 0x0000ffff;
|
|
|
1650 |
else
|
|
|
1651 |
dtlb_nent = BITX(cp->cp_ebx, 27, 16);
|
|
|
1652 |
break;
|
|
|
1653 |
|
|
|
1654 |
case 2 * 1024 * 1024:
|
|
|
1655 |
if ((cp->cp_eax & 0xffff0000) == 0)
|
|
|
1656 |
dtlb_nent = cp->cp_eax & 0x0000ffff;
|
|
|
1657 |
else
|
|
|
1658 |
dtlb_nent = BITX(cp->cp_eax, 27, 16);
|
|
|
1659 |
break;
|
|
|
1660 |
|
|
|
1661 |
default:
|
|
|
1662 |
panic("unknown L2 pagesize");
|
|
|
1663 |
/*NOTREACHED*/
|
|
|
1664 |
}
|
|
|
1665 |
}
|
|
|
1666 |
|
|
|
1667 |
if (dtlb_nent != 0)
|
|
|
1668 |
return (dtlb_nent);
|
|
|
1669 |
|
|
|
1670 |
/*
|
|
|
1671 |
* No L2 TLB support for this size, try L1.
|
|
|
1672 |
*/
|
|
|
1673 |
if (cpi->cpi_xmaxeax >= 0x80000005) {
|
|
|
1674 |
struct cpuidr *cp = &cpi->cpi_extd[5];
|
|
|
1675 |
|
|
|
1676 |
switch (pagesize) {
|
|
|
1677 |
case 4 * 1024:
|
|
|
1678 |
dtlb_nent = BITX(cp->cp_ebx, 23, 16);
|
|
|
1679 |
break;
|
|
|
1680 |
case 2 * 1024 * 1024:
|
|
|
1681 |
dtlb_nent = BITX(cp->cp_eax, 23, 16);
|
|
|
1682 |
break;
|
|
|
1683 |
default:
|
|
|
1684 |
panic("unknown L1 d-TLB pagesize");
|
|
|
1685 |
/*NOTREACHED*/
|
|
|
1686 |
}
|
|
|
1687 |
}
|
|
|
1688 |
|
|
|
1689 |
return (dtlb_nent);
|
|
|
1690 |
}
|
|
|
1691 |
|
|
|
1692 |
/*
|
|
|
1693 |
* Return 0 if the erratum is not present or not applicable, positive
|
|
|
1694 |
* if it is, and negative if the status of the erratum is unknown.
|
|
|
1695 |
*
|
|
|
1696 |
* See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
|
|
|
1697 |
* Processors" #25759, Rev 3.50, May 2005
|
|
|
1698 |
*/
|
|
|
1699 |
int
|
|
|
1700 |
cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
|
|
|
1701 |
{
|
|
|
1702 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
|
|
|
1703 |
uint_t eax;
|
|
|
1704 |
|
|
|
1705 |
if (cpi->cpi_vendor != X86_VENDOR_AMD)
|
|
|
1706 |
return (0);
|
|
|
1707 |
|
|
|
1708 |
eax = cpi->cpi_std[1].cp_eax;
|
|
|
1709 |
|
|
|
1710 |
#define SH_B0(eax) (eax == 0xf40 || eax == 0xf50)
|
|
|
1711 |
#define SH_B3(eax) (eax == 0xf51)
|
|
|
1712 |
#define B(eax) (SH_B0(eax) | SH_B3(eax))
|
|
|
1713 |
|
|
|
1714 |
#define SH_C0(eax) (eax == 0xf48 || eax == 0xf58)
|
|
|
1715 |
|
|
|
1716 |
#define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a)
|
|
|
1717 |
#define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0)
|
|
|
1718 |
#define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2)
|
|
|
1719 |
#define CG(eax) (SH_CG(eax) | DH_CG(eax) | CH_CG(eax))
|
|
|
1720 |
|
|
|
1721 |
#define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70)
|
|
|
1722 |
#define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0)
|
|
|
1723 |
#define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0)
|
|
|
1724 |
#define D0(eax) (SH_D0(eax) | DH_D0(eax) | CH_D0(eax))
|
|
|
1725 |
|
|
|
1726 |
#define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70)
|
|
|
1727 |
#define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */
|
|
|
1728 |
#define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0)
|
|
|
1729 |
#define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71)
|
|
|
1730 |
#define BH_E4(eax) (eax == 0x20fb1)
|
|
|
1731 |
#define SH_E5(eax) (eax == 0x20f42)
|
|
|
1732 |
#define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2)
|
|
|
1733 |
#define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32)
|
|
|
1734 |
#define EX(eax) (SH_E0(eax) | JH_E1(eax) | DH_E3(eax) | SH_E4(eax) | \
|
|
|
1735 |
BH_E4(eax) | SH_E5(eax) | DH_E6(eax) | JH_E6(eax))
|
|
|
1736 |
|
|
|
1737 |
switch (erratum) {
|
|
|
1738 |
case 1:
|
|
|
1739 |
return (1);
|
|
|
1740 |
case 51: /* what does the asterisk mean? */
|
|
|
1741 |
return (B(eax) || SH_C0(eax) || CG(eax));
|
|
|
1742 |
case 52:
|
|
|
1743 |
return (B(eax));
|
|
|
1744 |
case 57:
|
|
|
1745 |
return (1);
|
|
|
1746 |
case 58:
|
|
|
1747 |
return (B(eax));
|
|
|
1748 |
case 60:
|
|
|
1749 |
return (1);
|
|
|
1750 |
case 61:
|
|
|
1751 |
case 62:
|
|
|
1752 |
case 63:
|
|
|
1753 |
case 64:
|
|
|
1754 |
case 65:
|
|
|
1755 |
case 66:
|
|
|
1756 |
case 68:
|
|
|
1757 |
case 69:
|
|
|
1758 |
case 70:
|
|
|
1759 |
case 71:
|
|
|
1760 |
return (B(eax));
|
|
|
1761 |
case 72:
|
|
|
1762 |
return (SH_B0(eax));
|
|
|
1763 |
case 74:
|
|
|
1764 |
return (B(eax));
|
|
|
1765 |
case 75:
|
|
|
1766 |
return (1);
|
|
|
1767 |
case 76:
|
|
|
1768 |
return (B(eax));
|
|
|
1769 |
case 77:
|
|
|
1770 |
return (1);
|
|
|
1771 |
case 78:
|
|
|
1772 |
return (B(eax) || SH_C0(eax));
|
|
|
1773 |
case 79:
|
|
|
1774 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
|
|
|
1775 |
case 80:
|
|
|
1776 |
case 81:
|
|
|
1777 |
case 82:
|
|
|
1778 |
return (B(eax));
|
|
|
1779 |
case 83:
|
|
|
1780 |
return (B(eax) || SH_C0(eax) || CG(eax));
|
|
|
1781 |
case 85:
|
|
|
1782 |
return (1);
|
|
|
1783 |
case 86:
|
|
|
1784 |
return (SH_C0(eax) || CG(eax));
|
|
|
1785 |
case 88:
|
|
|
1786 |
#if !defined(__amd64)
|
|
|
1787 |
return (0);
|
|
|
1788 |
#else
|
|
|
1789 |
return (B(eax) || SH_C0(eax));
|
|
|
1790 |
#endif
|
|
|
1791 |
case 89:
|
|
|
1792 |
return (1);
|
|
|
1793 |
case 90:
|
|
|
1794 |
return (B(eax) || SH_C0(eax) || CG(eax));
|
|
|
1795 |
case 91:
|
|
|
1796 |
case 92:
|
|
|
1797 |
return (B(eax) || SH_C0(eax));
|
|
|
1798 |
case 93:
|
|
|
1799 |
return (SH_C0(eax));
|
|
|
1800 |
case 94:
|
|
|
1801 |
return (B(eax) || SH_C0(eax) || CG(eax));
|
|
|
1802 |
case 95:
|
|
|
1803 |
#if !defined(__amd64)
|
|
|
1804 |
return (0);
|
|
|
1805 |
#else
|
|
|
1806 |
return (B(eax) || SH_C0(eax));
|
|
|
1807 |
#endif
|
|
|
1808 |
case 96:
|
|
|
1809 |
return (B(eax) || SH_C0(eax) || CG(eax));
|
|
|
1810 |
case 97:
|
|
|
1811 |
case 98:
|
|
|
1812 |
return (SH_C0(eax) || CG(eax));
|
|
|
1813 |
case 99:
|
|
|
1814 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
|
|
|
1815 |
case 100:
|
|
|
1816 |
return (B(eax) || SH_C0(eax));
|
|
|
1817 |
case 101:
|
|
|
1818 |
case 103:
|
|
|
1819 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
|
|
|
1820 |
case 104:
|
|
|
1821 |
return (SH_C0(eax) || CG(eax) || D0(eax));
|
|
|
1822 |
case 105:
|
|
|
1823 |
case 106:
|
|
|
1824 |
case 107:
|
|
|
1825 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
|
|
|
1826 |
case 108:
|
|
|
1827 |
return (DH_CG(eax));
|
|
|
1828 |
case 109:
|
|
|
1829 |
return (SH_C0(eax) || CG(eax) || D0(eax));
|
|
|
1830 |
case 110:
|
|
|
1831 |
return (D0(eax) || EX(eax));
|
|
|
1832 |
case 111:
|
|
|
1833 |
return (CG(eax));
|
|
|
1834 |
case 112:
|
|
|
1835 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
|
|
|
1836 |
case 113:
|
|
|
1837 |
return (eax == 0x20fc0);
|
|
|
1838 |
case 114:
|
|
|
1839 |
return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
|
|
|
1840 |
case 115:
|
|
|
1841 |
return (SH_E0(eax) || JH_E1(eax));
|
|
|
1842 |
case 116:
|
|
|
1843 |
return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
|
|
|
1844 |
case 117:
|
|
|
1845 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
|
|
|
1846 |
case 118:
|
|
|
1847 |
return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) ||
|
|
|
1848 |
JH_E6(eax));
|
|
|
1849 |
case 121:
|
|
|
1850 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
|
|
|
1851 |
case 122:
|
|
|
1852 |
return (SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
|
|
|
1853 |
case 123:
|
|
|
1854 |
return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax));
|
|
|
1855 |
|
|
|
1856 |
default:
|
|
|
1857 |
return (-1);
|
|
|
1858 |
}
|
|
|
1859 |
}
|
|
|
1860 |
|
|
|
1861 |
static const char assoc_str[] = "associativity";
|
|
|
1862 |
static const char line_str[] = "line-size";
|
|
|
1863 |
static const char size_str[] = "size";
|
|
|
1864 |
|
|
|
1865 |
static void
|
|
|
1866 |
add_cache_prop(dev_info_t *devi, const char *label, const char *type,
|
|
|
1867 |
uint32_t val)
|
|
|
1868 |
{
|
|
|
1869 |
char buf[128];
|
|
|
1870 |
|
|
|
1871 |
/*
|
|
|
1872 |
* ndi_prop_update_int() is used because it is desirable for
|
|
|
1873 |
* DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
|
|
|
1874 |
*/
|
|
|
1875 |
if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
|
|
|
1876 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
|
|
|
1877 |
}
|
|
|
1878 |
|
|
|
1879 |
/*
|
|
|
1880 |
* Intel-style cache/tlb description
|
|
|
1881 |
*
|
|
|
1882 |
* Standard cpuid level 2 gives a randomly ordered
|
|
|
1883 |
* selection of tags that index into a table that describes
|
|
|
1884 |
* cache and tlb properties.
|
|
|
1885 |
*/
|
|
|
1886 |
|
|
|
1887 |
static const char l1_icache_str[] = "l1-icache";
|
|
|
1888 |
static const char l1_dcache_str[] = "l1-dcache";
|
|
|
1889 |
static const char l2_cache_str[] = "l2-cache";
|
|
|
1890 |
static const char itlb4k_str[] = "itlb-4K";
|
|
|
1891 |
static const char dtlb4k_str[] = "dtlb-4K";
|
|
|
1892 |
static const char itlb4M_str[] = "itlb-4M";
|
|
|
1893 |
static const char dtlb4M_str[] = "dtlb-4M";
|
|
|
1894 |
static const char itlb424_str[] = "itlb-4K-2M-4M";
|
|
|
1895 |
static const char dtlb44_str[] = "dtlb-4K-4M";
|
|
|
1896 |
static const char sl1_dcache_str[] = "sectored-l1-dcache";
|
|
|
1897 |
static const char sl2_cache_str[] = "sectored-l2-cache";
|
|
|
1898 |
static const char itrace_str[] = "itrace-cache";
|
|
|
1899 |
static const char sl3_cache_str[] = "sectored-l3-cache";
|
|
|
1900 |
|
|
|
1901 |
static const struct cachetab {
|
|
|
1902 |
uint8_t ct_code;
|
|
|
1903 |
uint8_t ct_assoc;
|
|
|
1904 |
uint16_t ct_line_size;
|
|
|
1905 |
size_t ct_size;
|
|
|
1906 |
const char *ct_label;
|
|
|
1907 |
} intel_ctab[] = {
|
|
|
1908 |
/* maintain descending order! */
|
|
|
1909 |
{ 0xb3, 4, 0, 128, dtlb4k_str },
|
|
|
1910 |
{ 0xb0, 4, 0, 128, itlb4k_str },
|
|
|
1911 |
{ 0x87, 8, 64, 1024*1024, l2_cache_str},
|
|
|
1912 |
{ 0x86, 4, 64, 512*1024, l2_cache_str},
|
|
|
1913 |
{ 0x85, 8, 32, 2*1024*1024, l2_cache_str},
|
|
|
1914 |
{ 0x84, 8, 32, 1024*1024, l2_cache_str},
|
|
|
1915 |
{ 0x83, 8, 32, 512*1024, l2_cache_str},
|
|
|
1916 |
{ 0x82, 8, 32, 256*1024, l2_cache_str},
|
|
|
1917 |
{ 0x81, 8, 32, 128*1024, l2_cache_str}, /* suspect! */
|
|
|
1918 |
{ 0x7f, 2, 64, 512*1024, l2_cache_str},
|
|
|
1919 |
{ 0x7d, 8, 64, 2*1024*1024, sl2_cache_str},
|
|
|
1920 |
{ 0x7c, 8, 64, 1024*1024, sl2_cache_str},
|
|
|
1921 |
{ 0x7b, 8, 64, 512*1024, sl2_cache_str},
|
|
|
1922 |
{ 0x7a, 8, 64, 256*1024, sl2_cache_str},
|
|
|
1923 |
{ 0x79, 8, 64, 128*1024, sl2_cache_str},
|
|
|
1924 |
{ 0x78, 8, 64, 1024*1024, l2_cache_str},
|
|
|
1925 |
{ 0x72, 8, 0, 32*1024, itrace_str},
|
|
|
1926 |
{ 0x71, 8, 0, 16*1024, itrace_str},
|
|
|
1927 |
{ 0x70, 8, 0, 12*1024, itrace_str},
|
|
|
1928 |
{ 0x68, 4, 64, 32*1024, sl1_dcache_str},
|
|
|
1929 |
{ 0x67, 4, 64, 16*1024, sl1_dcache_str},
|
|
|
1930 |
{ 0x66, 4, 64, 8*1024, sl1_dcache_str},
|
|
|
1931 |
{ 0x60, 8, 64, 16*1024, sl1_dcache_str},
|
|
|
1932 |
{ 0x5d, 0, 0, 256, dtlb44_str},
|
|
|
1933 |
{ 0x5c, 0, 0, 128, dtlb44_str},
|
|
|
1934 |
{ 0x5b, 0, 0, 64, dtlb44_str},
|
|
|
1935 |
{ 0x52, 0, 0, 256, itlb424_str},
|
|
|
1936 |
{ 0x51, 0, 0, 128, itlb424_str},
|
|
|
1937 |
{ 0x50, 0, 0, 64, itlb424_str},
|
|
|
1938 |
{ 0x45, 4, 32, 2*1024*1024, l2_cache_str},
|
|
|
1939 |
{ 0x44, 4, 32, 1024*1024, l2_cache_str},
|
|
|
1940 |
{ 0x43, 4, 32, 512*1024, l2_cache_str},
|
|
|
1941 |
{ 0x42, 4, 32, 256*1024, l2_cache_str},
|
|
|
1942 |
{ 0x41, 4, 32, 128*1024, l2_cache_str},
|
|
|
1943 |
{ 0x3c, 4, 64, 256*1024, sl2_cache_str},
|
|
|
1944 |
{ 0x3b, 2, 64, 128*1024, sl2_cache_str},
|
|
|
1945 |
{ 0x39, 4, 64, 128*1024, sl2_cache_str},
|
|
|
1946 |
{ 0x30, 8, 64, 32*1024, l1_icache_str},
|
|
|
1947 |
{ 0x2c, 8, 64, 32*1024, l1_dcache_str},
|
|
|
1948 |
{ 0x29, 8, 64, 4096*1024, sl3_cache_str},
|
|
|
1949 |
{ 0x25, 8, 64, 2048*1024, sl3_cache_str},
|
|
|
1950 |
{ 0x23, 8, 64, 1024*1024, sl3_cache_str},
|
|
|
1951 |
{ 0x22, 4, 64, 512*1024, sl3_cache_str},
|
|
|
1952 |
{ 0x0c, 4, 32, 16*1024, l1_dcache_str},
|
|
|
1953 |
{ 0x0a, 2, 32, 8*1024, l1_dcache_str},
|
|
|
1954 |
{ 0x08, 4, 32, 16*1024, l1_icache_str},
|
|
|
1955 |
{ 0x06, 4, 32, 8*1024, l1_icache_str},
|
|
|
1956 |
{ 0x04, 4, 0, 8, dtlb4M_str},
|
|
|
1957 |
{ 0x03, 4, 0, 64, dtlb4k_str},
|
|
|
1958 |
{ 0x02, 4, 0, 2, itlb4M_str},
|
|
|
1959 |
{ 0x01, 4, 0, 32, itlb4k_str},
|
|
|
1960 |
{ 0 }
|
|
|
1961 |
};
|
|
|
1962 |
|
|
|
1963 |
static const struct cachetab cyrix_ctab[] = {
|
|
|
1964 |
{ 0x70, 4, 0, 32, "tlb-4K" },
|
|
|
1965 |
{ 0x80, 4, 16, 16*1024, "l1-cache" },
|
|
|
1966 |
{ 0 }
|
|
|
1967 |
};
|
|
|
1968 |
|
|
|
1969 |
/*
|
|
|
1970 |
* Search a cache table for a matching entry
|
|
|
1971 |
*/
|
|
|
1972 |
static const struct cachetab *
|
|
|
1973 |
find_cacheent(const struct cachetab *ct, uint_t code)
|
|
|
1974 |
{
|
|
|
1975 |
if (code != 0) {
|
|
|
1976 |
for (; ct->ct_code != 0; ct++)
|
|
|
1977 |
if (ct->ct_code <= code)
|
|
|
1978 |
break;
|
|
|
1979 |
if (ct->ct_code == code)
|
|
|
1980 |
return (ct);
|
|
|
1981 |
}
|
|
|
1982 |
return (NULL);
|
|
|
1983 |
}
|
|
|
1984 |
|
|
|
1985 |
/*
|
|
|
1986 |
* Walk the cacheinfo descriptor, applying 'func' to every valid element
|
|
|
1987 |
* The walk is terminated if the walker returns non-zero.
|
|
|
1988 |
*/
|
|
|
1989 |
static void
|
|
|
1990 |
intel_walk_cacheinfo(struct cpuid_info *cpi,
|
|
|
1991 |
void *arg, int (*func)(void *, const struct cachetab *))
|
|
|
1992 |
{
|
|
|
1993 |
const struct cachetab *ct;
|
|
|
1994 |
uint8_t *dp;
|
|
|
1995 |
int i;
|
|
|
1996 |
|
|
|
1997 |
if ((dp = cpi->cpi_cacheinfo) == NULL)
|
|
|
1998 |
return;
|
|
|
1999 |
for (i = 0; i < cpi->cpi_ncache; i++, dp++)
|
|
|
2000 |
if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
|
|
|
2001 |
if (func(arg, ct) != 0)
|
|
|
2002 |
break;
|
|
|
2003 |
}
|
|
|
2004 |
}
|
|
|
2005 |
|
|
|
2006 |
/*
|
|
|
2007 |
* (Like the Intel one, except for Cyrix CPUs)
|
|
|
2008 |
*/
|
|
|
2009 |
static void
|
|
|
2010 |
cyrix_walk_cacheinfo(struct cpuid_info *cpi,
|
|
|
2011 |
void *arg, int (*func)(void *, const struct cachetab *))
|
|
|
2012 |
{
|
|
|
2013 |
const struct cachetab *ct;
|
|
|
2014 |
uint8_t *dp;
|
|
|
2015 |
int i;
|
|
|
2016 |
|
|
|
2017 |
if ((dp = cpi->cpi_cacheinfo) == NULL)
|
|
|
2018 |
return;
|
|
|
2019 |
for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
|
|
|
2020 |
/*
|
|
|
2021 |
* Search Cyrix-specific descriptor table first ..
|
|
|
2022 |
*/
|
|
|
2023 |
if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
|
|
|
2024 |
if (func(arg, ct) != 0)
|
|
|
2025 |
break;
|
|
|
2026 |
continue;
|
|
|
2027 |
}
|
|
|
2028 |
/*
|
|
|
2029 |
* .. else fall back to the Intel one
|
|
|
2030 |
*/
|
|
|
2031 |
if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
|
|
|
2032 |
if (func(arg, ct) != 0)
|
|
|
2033 |
break;
|
|
|
2034 |
continue;
|
|
|
2035 |
}
|
|
|
2036 |
}
|
|
|
2037 |
}
|
|
|
2038 |
|
|
|
2039 |
/*
|
|
|
2040 |
* A cacheinfo walker that adds associativity, line-size, and size properties
|
|
|
2041 |
* to the devinfo node it is passed as an argument.
|
|
|
2042 |
*/
|
|
|
2043 |
static int
|
|
|
2044 |
add_cacheent_props(void *arg, const struct cachetab *ct)
|
|
|
2045 |
{
|
|
|
2046 |
dev_info_t *devi = arg;
|
|
|
2047 |
|
|
|
2048 |
add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
|
|
|
2049 |
if (ct->ct_line_size != 0)
|
|
|
2050 |
add_cache_prop(devi, ct->ct_label, line_str,
|
|
|
2051 |
ct->ct_line_size);
|
|
|
2052 |
add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
|
|
|
2053 |
return (0);
|
|
|
2054 |
}
|
|
|
2055 |
|
|
|
2056 |
static const char fully_assoc[] = "fully-associative?";
|
|
|
2057 |
|
|
|
2058 |
/*
|
|
|
2059 |
* AMD style cache/tlb description
|
|
|
2060 |
*
|
|
|
2061 |
* Extended functions 5 and 6 directly describe properties of
|
|
|
2062 |
* tlbs and various cache levels.
|
|
|
2063 |
*/
|
|
|
2064 |
static void
|
|
|
2065 |
add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc)
|
|
|
2066 |
{
|
|
|
2067 |
switch (assoc) {
|
|
|
2068 |
case 0: /* reserved; ignore */
|
|
|
2069 |
break;
|
|
|
2070 |
default:
|
|
|
2071 |
add_cache_prop(devi, label, assoc_str, assoc);
|
|
|
2072 |
break;
|
|
|
2073 |
case 0xff:
|
|
|
2074 |
add_cache_prop(devi, label, fully_assoc, 1);
|
|
|
2075 |
break;
|
|
|
2076 |
}
|
|
|
2077 |
}
|
|
|
2078 |
|
|
|
2079 |
static void
|
|
|
2080 |
add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
|
|
|
2081 |
{
|
|
|
2082 |
if (size == 0)
|
|
|
2083 |
return;
|
|
|
2084 |
add_cache_prop(devi, label, size_str, size);
|
|
|
2085 |
add_amd_assoc(devi, label, assoc);
|
|
|
2086 |
}
|
|
|
2087 |
|
|
|
2088 |
static void
|
|
|
2089 |
add_amd_cache(dev_info_t *devi, const char *label,
|
|
|
2090 |
uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
|
|
|
2091 |
{
|
|
|
2092 |
if (size == 0 || line_size == 0)
|
|
|
2093 |
return;
|
|
|
2094 |
add_amd_assoc(devi, label, assoc);
|
|
|
2095 |
/*
|
|
|
2096 |
* Most AMD parts have a sectored cache. Multiple cache lines are
|
|
|
2097 |
* associated with each tag. A sector consists of all cache lines
|
|
|
2098 |
* associated with a tag. For example, the AMD K6-III has a sector
|
|
|
2099 |
* size of 2 cache lines per tag.
|
|
|
2100 |
*/
|
|
|
2101 |
if (lines_per_tag != 0)
|
|
|
2102 |
add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
|
|
|
2103 |
add_cache_prop(devi, label, line_str, line_size);
|
|
|
2104 |
add_cache_prop(devi, label, size_str, size * 1024);
|
|
|
2105 |
}
|
|
|
2106 |
|
|
|
2107 |
static void
|
|
|
2108 |
add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc)
|
|
|
2109 |
{
|
|
|
2110 |
switch (assoc) {
|
|
|
2111 |
case 0: /* off */
|
|
|
2112 |
break;
|
|
|
2113 |
case 1:
|
|
|
2114 |
case 2:
|
|
|
2115 |
case 4:
|
|
|
2116 |
add_cache_prop(devi, label, assoc_str, assoc);
|
|
|
2117 |
break;
|
|
|
2118 |
case 6:
|
|
|
2119 |
add_cache_prop(devi, label, assoc_str, 8);
|
|
|
2120 |
break;
|
|
|
2121 |
case 8:
|
|
|
2122 |
add_cache_prop(devi, label, assoc_str, 16);
|
|
|
2123 |
break;
|
|
|
2124 |
case 0xf:
|
|
|
2125 |
add_cache_prop(devi, label, fully_assoc, 1);
|
|
|
2126 |
break;
|
|
|
2127 |
default: /* reserved; ignore */
|
|
|
2128 |
break;
|
|
|
2129 |
}
|
|
|
2130 |
}
|
|
|
2131 |
|
|
|
2132 |
static void
|
|
|
2133 |
add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
|
|
|
2134 |
{
|
|
|
2135 |
if (size == 0 || assoc == 0)
|
|
|
2136 |
return;
|
|
|
2137 |
add_amd_l2_assoc(devi, label, assoc);
|
|
|
2138 |
add_cache_prop(devi, label, size_str, size);
|
|
|
2139 |
}
|
|
|
2140 |
|
|
|
2141 |
static void
|
|
|
2142 |
add_amd_l2_cache(dev_info_t *devi, const char *label,
|
|
|
2143 |
uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
|
|
|
2144 |
{
|
|
|
2145 |
if (size == 0 || assoc == 0 || line_size == 0)
|
|
|
2146 |
return;
|
|
|
2147 |
add_amd_l2_assoc(devi, label, assoc);
|
|
|
2148 |
if (lines_per_tag != 0)
|
|
|
2149 |
add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
|
|
|
2150 |
add_cache_prop(devi, label, line_str, line_size);
|
|
|
2151 |
add_cache_prop(devi, label, size_str, size * 1024);
|
|
|
2152 |
}
|
|
|
2153 |
|
|
|
2154 |
static void
|
|
|
2155 |
amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi)
|
|
|
2156 |
{
|
|
|
2157 |
struct cpuidr *cp;
|
|
|
2158 |
|
|
|
2159 |
if (cpi->cpi_xmaxeax < 0x80000005)
|
|
|
2160 |
return;
|
|
|
2161 |
cp = &cpi->cpi_extd[5];
|
|
|
2162 |
|
|
|
2163 |
/*
|
|
|
2164 |
* 4M/2M L1 TLB configuration
|
|
|
2165 |
*
|
|
|
2166 |
* We report the size for 2M pages because AMD uses two
|
|
|
2167 |
* TLB entries for one 4M page.
|
|
|
2168 |
*/
|
|
|
2169 |
add_amd_tlb(devi, "dtlb-2M",
|
|
|
2170 |
BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
|
|
|
2171 |
add_amd_tlb(devi, "itlb-2M",
|
|
|
2172 |
BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
|
|
|
2173 |
|
|
|
2174 |
/*
|
|
|
2175 |
* 4K L1 TLB configuration
|
|
|
2176 |
*/
|
|
|
2177 |
|
|
|
2178 |
switch (cpi->cpi_vendor) {
|
|
|
2179 |
uint_t nentries;
|
|
|
2180 |
case X86_VENDOR_TM:
|
|
|
2181 |
if (cpi->cpi_family >= 5) {
|
|
|
2182 |
/*
|
|
|
2183 |
* Crusoe processors have 256 TLB entries, but
|
|
|
2184 |
* cpuid data format constrains them to only
|
|
|
2185 |
* reporting 255 of them.
|
|
|
2186 |
*/
|
|
|
2187 |
if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
|
|
|
2188 |
nentries = 256;
|
|
|
2189 |
/*
|
|
|
2190 |
* Crusoe processors also have a unified TLB
|
|
|
2191 |
*/
|
|
|
2192 |
add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
|
|
|
2193 |
nentries);
|
|
|
2194 |
break;
|
|
|
2195 |
}
|
|
|
2196 |
/*FALLTHROUGH*/
|
|
|
2197 |
default:
|
|
|
2198 |
add_amd_tlb(devi, itlb4k_str,
|
|
|
2199 |
BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
|
|
|
2200 |
add_amd_tlb(devi, dtlb4k_str,
|
|
|
2201 |
BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
|
|
|
2202 |
break;
|
|
|
2203 |
}
|
|
|
2204 |
|
|
|
2205 |
/*
|
|
|
2206 |
* data L1 cache configuration
|
|
|
2207 |
*/
|
|
|
2208 |
|
|
|
2209 |
add_amd_cache(devi, l1_dcache_str,
|
|
|
2210 |
BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
|
|
|
2211 |
BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
|
|
|
2212 |
|
|
|
2213 |
/*
|
|
|
2214 |
* code L1 cache configuration
|
|
|
2215 |
*/
|
|
|
2216 |
|
|
|
2217 |
add_amd_cache(devi, l1_icache_str,
|
|
|
2218 |
BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
|
|
|
2219 |
BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
|
|
|
2220 |
|
|
|
2221 |
if (cpi->cpi_xmaxeax < 0x80000006)
|
|
|
2222 |
return;
|
|
|
2223 |
cp = &cpi->cpi_extd[6];
|
|
|
2224 |
|
|
|
2225 |
/* Check for a unified L2 TLB for large pages */
|
|
|
2226 |
|
|
|
2227 |
if (BITX(cp->cp_eax, 31, 16) == 0)
|
|
|
2228 |
add_amd_l2_tlb(devi, "l2-tlb-2M",
|
|
|
2229 |
BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
|
|
|
2230 |
else {
|
|
|
2231 |
add_amd_l2_tlb(devi, "l2-dtlb-2M",
|
|
|
2232 |
BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
|
|
|
2233 |
add_amd_l2_tlb(devi, "l2-itlb-2M",
|
|
|
2234 |
BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
|
|
|
2235 |
}
|
|
|
2236 |
|
|
|
2237 |
/* Check for a unified L2 TLB for 4K pages */
|
|
|
2238 |
|
|
|
2239 |
if (BITX(cp->cp_ebx, 31, 16) == 0) {
|
|
|
2240 |
add_amd_l2_tlb(devi, "l2-tlb-4K",
|
|
|
2241 |
BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
|
|
|
2242 |
} else {
|
|
|
2243 |
add_amd_l2_tlb(devi, "l2-dtlb-4K",
|
|
|
2244 |
BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
|
|
|
2245 |
add_amd_l2_tlb(devi, "l2-itlb-4K",
|
|
|
2246 |
BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
|
|
|
2247 |
}
|
|
|
2248 |
|
|
|
2249 |
add_amd_l2_cache(devi, l2_cache_str,
|
|
|
2250 |
BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
|
|
|
2251 |
BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
|
|
|
2252 |
}
|
|
|
2253 |
|
|
|
2254 |
/*
|
|
|
2255 |
* There are two basic ways that the x86 world describes it cache
|
|
|
2256 |
* and tlb architecture - Intel's way and AMD's way.
|
|
|
2257 |
*
|
|
|
2258 |
* Return which flavor of cache architecture we should use
|
|
|
2259 |
*/
|
|
|
2260 |
static int
|
|
|
2261 |
x86_which_cacheinfo(struct cpuid_info *cpi)
|
|
|
2262 |
{
|
|
|
2263 |
switch (cpi->cpi_vendor) {
|
|
|
2264 |
case X86_VENDOR_Intel:
|
|
|
2265 |
if (cpi->cpi_maxeax >= 2)
|
|
|
2266 |
return (X86_VENDOR_Intel);
|
|
|
2267 |
break;
|
|
|
2268 |
case X86_VENDOR_AMD:
|
|
|
2269 |
/*
|
|
|
2270 |
* The K5 model 1 was the first part from AMD that reported
|
|
|
2271 |
* cache sizes via extended cpuid functions.
|
|
|
2272 |
*/
|
|
|
2273 |
if (cpi->cpi_family > 5 ||
|
|
|
2274 |
(cpi->cpi_family == 5 && cpi->cpi_model >= 1))
|
|
|
2275 |
return (X86_VENDOR_AMD);
|
|
|
2276 |
break;
|
|
|
2277 |
case X86_VENDOR_TM:
|
|
|
2278 |
if (cpi->cpi_family >= 5)
|
|
|
2279 |
return (X86_VENDOR_AMD);
|
|
|
2280 |
/*FALLTHROUGH*/
|
|
|
2281 |
default:
|
|
|
2282 |
/*
|
|
|
2283 |
* If they have extended CPU data for 0x80000005
|
|
|
2284 |
* then we assume they have AMD-format cache
|
|
|
2285 |
* information.
|
|
|
2286 |
*
|
|
|
2287 |
* If not, and the vendor happens to be Cyrix,
|
|
|
2288 |
* then try our-Cyrix specific handler.
|
|
|
2289 |
*
|
|
|
2290 |
* If we're not Cyrix, then assume we're using Intel's
|
|
|
2291 |
* table-driven format instead.
|
|
|
2292 |
*/
|
|
|
2293 |
if (cpi->cpi_xmaxeax >= 0x80000005)
|
|
|
2294 |
return (X86_VENDOR_AMD);
|
|
|
2295 |
else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
|
|
|
2296 |
return (X86_VENDOR_Cyrix);
|
|
|
2297 |
else if (cpi->cpi_maxeax >= 2)
|
|
|
2298 |
return (X86_VENDOR_Intel);
|
|
|
2299 |
break;
|
|
|
2300 |
}
|
|
|
2301 |
return (-1);
|
|
|
2302 |
}
|
|
|
2303 |
|
|
|
2304 |
/*
|
|
|
2305 |
* create a node for the given cpu under the prom root node.
|
|
|
2306 |
* Also, create a cpu node in the device tree.
|
|
|
2307 |
*/
|
|
|
2308 |
static dev_info_t *cpu_nex_devi = NULL;
|
|
|
2309 |
static kmutex_t cpu_node_lock;
|
|
|
2310 |
|
|
|
2311 |
/*
|
|
|
2312 |
* Called from post_startup() and mp_startup()
|
|
|
2313 |
*/
|
|
|
2314 |
void
|
|
|
2315 |
add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi)
|
|
|
2316 |
{
|
|
|
2317 |
dev_info_t *cpu_devi;
|
|
|
2318 |
int create;
|
|
|
2319 |
|
|
|
2320 |
mutex_enter(&cpu_node_lock);
|
|
|
2321 |
|
|
|
2322 |
/*
|
|
|
2323 |
* create a nexus node for all cpus identified as 'cpu_id' under
|
|
|
2324 |
* the root node.
|
|
|
2325 |
*/
|
|
|
2326 |
if (cpu_nex_devi == NULL) {
|
|
|
2327 |
if (ndi_devi_alloc(ddi_root_node(), "cpus",
|
|
|
2328 |
(dnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) {
|
|
|
2329 |
mutex_exit(&cpu_node_lock);
|
|
|
2330 |
return;
|
|
|
2331 |
}
|
|
|
2332 |
(void) ndi_devi_online(cpu_nex_devi, 0);
|
|
|
2333 |
}
|
|
|
2334 |
|
|
|
2335 |
/*
|
|
|
2336 |
* create a child node for cpu identified as 'cpu_id'
|
|
|
2337 |
*/
|
|
|
2338 |
cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID,
|
|
|
2339 |
cpu_id);
|
|
|
2340 |
if (cpu_devi == NULL) {
|
|
|
2341 |
mutex_exit(&cpu_node_lock);
|
|
|
2342 |
return;
|
|
|
2343 |
}
|
|
|
2344 |
|
|
|
2345 |
/* device_type */
|
|
|
2346 |
|
|
|
2347 |
(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2348 |
"device_type", "cpu");
|
|
|
2349 |
|
|
|
2350 |
/* reg */
|
|
|
2351 |
|
|
|
2352 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2353 |
"reg", cpu_id);
|
|
|
2354 |
|
|
|
2355 |
/* cpu-mhz, and clock-frequency */
|
|
|
2356 |
|
|
|
2357 |
if (cpu_freq > 0) {
|
|
|
2358 |
long long mul;
|
|
|
2359 |
|
|
|
2360 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2361 |
"cpu-mhz", cpu_freq);
|
|
|
2362 |
|
|
|
2363 |
if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
|
|
|
2364 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2365 |
"clock-frequency", (int)mul);
|
|
|
2366 |
}
|
|
|
2367 |
|
|
|
2368 |
(void) ndi_devi_online(cpu_devi, 0);
|
|
|
2369 |
|
|
|
2370 |
if ((x86_feature & X86_CPUID) == 0) {
|
|
|
2371 |
mutex_exit(&cpu_node_lock);
|
|
|
2372 |
return;
|
|
|
2373 |
}
|
|
|
2374 |
|
|
|
2375 |
/* vendor-id */
|
|
|
2376 |
|
|
|
2377 |
(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2378 |
"vendor-id", cpi->cpi_vendorstr);
|
|
|
2379 |
|
|
|
2380 |
if (cpi->cpi_maxeax == 0) {
|
|
|
2381 |
mutex_exit(&cpu_node_lock);
|
|
|
2382 |
return;
|
|
|
2383 |
}
|
|
|
2384 |
|
|
|
2385 |
/*
|
|
|
2386 |
* family, model, and step
|
|
|
2387 |
*/
|
|
|
2388 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2389 |
"family", CPI_FAMILY(cpi));
|
|
|
2390 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2391 |
"cpu-model", CPI_MODEL(cpi));
|
|
|
2392 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2393 |
"stepping-id", CPI_STEP(cpi));
|
|
|
2394 |
|
|
|
2395 |
/* type */
|
|
|
2396 |
|
|
|
2397 |
switch (cpi->cpi_vendor) {
|
|
|
2398 |
case X86_VENDOR_Intel:
|
|
|
2399 |
create = 1;
|
|
|
2400 |
break;
|
|
|
2401 |
default:
|
|
|
2402 |
create = 0;
|
|
|
2403 |
break;
|
|
|
2404 |
}
|
|
|
2405 |
if (create)
|
|
|
2406 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2407 |
"type", CPI_TYPE(cpi));
|
|
|
2408 |
|
|
|
2409 |
/* ext-family */
|
|
|
2410 |
|
|
|
2411 |
switch (cpi->cpi_vendor) {
|
|
|
2412 |
case X86_VENDOR_Intel:
|
|
|
2413 |
case X86_VENDOR_AMD:
|
|
|
2414 |
create = cpi->cpi_family >= 0xf;
|
|
|
2415 |
break;
|
|
|
2416 |
default:
|
|
|
2417 |
create = 0;
|
|
|
2418 |
break;
|
|
|
2419 |
}
|
|
|
2420 |
if (create)
|
|
|
2421 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2422 |
"ext-family", CPI_FAMILY_XTD(cpi));
|
|
|
2423 |
|
|
|
2424 |
/* ext-model */
|
|
|
2425 |
|
|
|
2426 |
switch (cpi->cpi_vendor) {
|
|
|
2427 |
case X86_VENDOR_Intel:
|
|
|
2428 |
case X86_VENDOR_AMD:
|
|
|
2429 |
create = CPI_MODEL(cpi) == 0xf;
|
|
|
2430 |
break;
|
|
|
2431 |
default:
|
|
|
2432 |
create = 0;
|
|
|
2433 |
break;
|
|
|
2434 |
}
|
|
|
2435 |
if (create)
|
|
|
2436 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2437 |
"ext-model", CPI_MODEL_XTD(cpi));
|
|
|
2438 |
|
|
|
2439 |
/* generation */
|
|
|
2440 |
|
|
|
2441 |
switch (cpi->cpi_vendor) {
|
|
|
2442 |
case X86_VENDOR_AMD:
|
|
|
2443 |
/*
|
|
|
2444 |
* AMD K5 model 1 was the first part to support this
|
|
|
2445 |
*/
|
|
|
2446 |
create = cpi->cpi_xmaxeax >= 0x80000001;
|
|
|
2447 |
break;
|
|
|
2448 |
default:
|
|
|
2449 |
create = 0;
|
|
|
2450 |
break;
|
|
|
2451 |
}
|
|
|
2452 |
if (create)
|
|
|
2453 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2454 |
"generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
|
|
|
2455 |
|
|
|
2456 |
/* brand-id */
|
|
|
2457 |
|
|
|
2458 |
switch (cpi->cpi_vendor) {
|
|
|
2459 |
case X86_VENDOR_Intel:
|
|
|
2460 |
/*
|
|
|
2461 |
* brand id first appeared on Pentium III Xeon model 8,
|
|
|
2462 |
* and Celeron model 8 processors and Opteron
|
|
|
2463 |
*/
|
|
|
2464 |
create = cpi->cpi_family > 6 ||
|
|
|
2465 |
(cpi->cpi_family == 6 && cpi->cpi_model >= 8);
|
|
|
2466 |
break;
|
|
|
2467 |
case X86_VENDOR_AMD:
|
|
|
2468 |
create = cpi->cpi_family >= 0xf;
|
|
|
2469 |
break;
|
|
|
2470 |
default:
|
|
|
2471 |
create = 0;
|
|
|
2472 |
break;
|
|
|
2473 |
}
|
|
|
2474 |
if (create && cpi->cpi_brandid != 0) {
|
|
|
2475 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2476 |
"brand-id", cpi->cpi_brandid);
|
|
|
2477 |
}
|
|
|
2478 |
|
|
|
2479 |
/* chunks, and apic-id */
|
|
|
2480 |
|
|
|
2481 |
switch (cpi->cpi_vendor) {
|
|
|
2482 |
case X86_VENDOR_Intel:
|
|
|
2483 |
case X86_VENDOR_AMD:
|
|
|
2484 |
/*
|
|
|
2485 |
* first available on Pentium IV and Opteron (K8)
|
|
|
2486 |
*/
|
|
|
2487 |
create = cpi->cpi_family >= 0xf;
|
|
|
2488 |
break;
|
|
|
2489 |
default:
|
|
|
2490 |
create = 0;
|
|
|
2491 |
break;
|
|
|
2492 |
}
|
|
|
2493 |
if (create) {
|
|
|
2494 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2495 |
"chunks", CPI_CHUNKS(cpi));
|
|
|
2496 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2497 |
"apic-id", CPI_APIC_ID(cpi));
|
|
|
2498 |
if (cpi->cpi_chipid >= 0)
|
|
|
2499 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2500 |
"chip#", cpi->cpi_chipid);
|
|
|
2501 |
}
|
|
|
2502 |
|
|
|
2503 |
/* cpuid-features */
|
|
|
2504 |
|
|
|
2505 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2506 |
"cpuid-features", CPI_FEATURES_EDX(cpi));
|
|
|
2507 |
|
|
|
2508 |
|
|
|
2509 |
/* cpuid-features-ecx */
|
|
|
2510 |
|
|
|
2511 |
switch (cpi->cpi_vendor) {
|
|
|
2512 |
case X86_VENDOR_Intel:
|
|
|
2513 |
create = cpi->cpi_family >= 0xf;
|
|
|
2514 |
break;
|
|
|
2515 |
default:
|
|
|
2516 |
create = 0;
|
|
|
2517 |
break;
|
|
|
2518 |
}
|
|
|
2519 |
if (create)
|
|
|
2520 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2521 |
"cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
|
|
|
2522 |
|
|
|
2523 |
/* ext-cpuid-features */
|
|
|
2524 |
|
|
|
2525 |
switch (cpi->cpi_vendor) {
|
|
|
2526 |
case X86_VENDOR_AMD:
|
|
|
2527 |
case X86_VENDOR_Cyrix:
|
|
|
2528 |
case X86_VENDOR_TM:
|
|
|
2529 |
case X86_VENDOR_Centaur:
|
|
|
2530 |
/*
|
|
|
2531 |
* The extended cpuid features are not relevant on
|
|
|
2532 |
* Intel but are available from the AMD K5 model 1
|
|
|
2533 |
* and most Cyrix GXm and later.
|
|
|
2534 |
*/
|
|
|
2535 |
create = cpi->cpi_xmaxeax >= 0x80000001;
|
|
|
2536 |
break;
|
|
|
2537 |
default:
|
|
|
2538 |
create = 0;
|
|
|
2539 |
break;
|
|
|
2540 |
}
|
|
|
2541 |
if (create)
|
|
|
2542 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2543 |
"ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
|
|
|
2544 |
|
|
|
2545 |
/*
|
|
|
2546 |
* Brand String first appeared in Intel Pentium IV, AMD K5
|
|
|
2547 |
* model 1, and Cyrix GXm. On earlier models we try and
|
|
|
2548 |
* simulate something similar .. so this string should always
|
|
|
2549 |
* same -something- about the processor, however lame.
|
|
|
2550 |
*/
|
|
|
2551 |
(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
|
|
|
2552 |
"brand-string", cpi->cpi_brandstr);
|
|
|
2553 |
|
|
|
2554 |
/*
|
|
|
2555 |
* Finally, cache and tlb information
|
|
|
2556 |
*/
|
|
|
2557 |
switch (x86_which_cacheinfo(cpi)) {
|
|
|
2558 |
case X86_VENDOR_Intel:
|
|
|
2559 |
intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
|
|
|
2560 |
break;
|
|
|
2561 |
case X86_VENDOR_Cyrix:
|
|
|
2562 |
cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
|
|
|
2563 |
break;
|
|
|
2564 |
case X86_VENDOR_AMD:
|
|
|
2565 |
amd_cache_info(cpi, cpu_devi);
|
|
|
2566 |
break;
|
|
|
2567 |
default:
|
|
|
2568 |
break;
|
|
|
2569 |
}
|
|
|
2570 |
|
|
|
2571 |
mutex_exit(&cpu_node_lock);
|
|
|
2572 |
}
|
|
|
2573 |
|
|
|
2574 |
struct l2info {
|
|
|
2575 |
int *l2i_csz;
|
|
|
2576 |
int *l2i_lsz;
|
|
|
2577 |
int *l2i_assoc;
|
|
|
2578 |
int l2i_ret;
|
|
|
2579 |
};
|
|
|
2580 |
|
|
|
2581 |
/*
|
|
|
2582 |
* A cacheinfo walker that fetches the size, line-size and associativity
|
|
|
2583 |
* of the L2 cache
|
|
|
2584 |
*/
|
|
|
2585 |
static int
|
|
|
2586 |
intel_l2cinfo(void *arg, const struct cachetab *ct)
|
|
|
2587 |
{
|
|
|
2588 |
struct l2info *l2i = arg;
|
|
|
2589 |
int *ip;
|
|
|
2590 |
|
|
|
2591 |
if (ct->ct_label != l2_cache_str &&
|
|
|
2592 |
ct->ct_label != sl2_cache_str)
|
|
|
2593 |
return (0); /* not an L2 -- keep walking */
|
|
|
2594 |
|
|
|
2595 |
if ((ip = l2i->l2i_csz) != NULL)
|
|
|
2596 |
*ip = ct->ct_size;
|
|
|
2597 |
if ((ip = l2i->l2i_lsz) != NULL)
|
|
|
2598 |
*ip = ct->ct_line_size;
|
|
|
2599 |
if ((ip = l2i->l2i_assoc) != NULL)
|
|
|
2600 |
*ip = ct->ct_assoc;
|
|
|
2601 |
l2i->l2i_ret = ct->ct_size;
|
|
|
2602 |
return (1); /* was an L2 -- terminate walk */
|
|
|
2603 |
}
|
|
|
2604 |
|
|
|
2605 |
static void
|
|
|
2606 |
amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i)
|
|
|
2607 |
{
|
|
|
2608 |
struct cpuidr *cp;
|
|
|
2609 |
uint_t size, assoc;
|
|
|
2610 |
int *ip;
|
|
|
2611 |
|
|
|
2612 |
if (cpi->cpi_xmaxeax < 0x80000006)
|
|
|
2613 |
return;
|
|
|
2614 |
cp = &cpi->cpi_extd[6];
|
|
|
2615 |
|
|
|
2616 |
if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 &&
|
|
|
2617 |
(size = BITX(cp->cp_ecx, 31, 16)) != 0) {
|
|
|
2618 |
uint_t cachesz = size * 1024;
|
|
|
2619 |
|
|
|
2620 |
|
|
|
2621 |
if ((ip = l2i->l2i_csz) != NULL)
|
|
|
2622 |
*ip = cachesz;
|
|
|
2623 |
if ((ip = l2i->l2i_lsz) != NULL)
|
|
|
2624 |
*ip = BITX(cp->cp_ecx, 7, 0);
|
|
|
2625 |
if ((ip = l2i->l2i_assoc) != NULL)
|
|
|
2626 |
*ip = assoc;
|
|
|
2627 |
l2i->l2i_ret = cachesz;
|
|
|
2628 |
}
|
|
|
2629 |
}
|
|
|
2630 |
|
|
|
2631 |
int
|
|
|
2632 |
getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc)
|
|
|
2633 |
{
|
|
|
2634 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
|
|
|
2635 |
struct l2info __l2info, *l2i = &__l2info;
|
|
|
2636 |
|
|
|
2637 |
l2i->l2i_csz = csz;
|
|
|
2638 |
l2i->l2i_lsz = lsz;
|
|
|
2639 |
l2i->l2i_assoc = assoc;
|
|
|
2640 |
l2i->l2i_ret = -1;
|
|
|
2641 |
|
|
|
2642 |
switch (x86_which_cacheinfo(cpi)) {
|
|
|
2643 |
case X86_VENDOR_Intel:
|
|
|
2644 |
intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
|
|
|
2645 |
break;
|
|
|
2646 |
case X86_VENDOR_Cyrix:
|
|
|
2647 |
cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
|
|
|
2648 |
break;
|
|
|
2649 |
case X86_VENDOR_AMD:
|
|
|
2650 |
amd_l2cacheinfo(cpi, l2i);
|
|
|
2651 |
break;
|
|
|
2652 |
default:
|
|
|
2653 |
break;
|
|
|
2654 |
}
|
|
|
2655 |
return (l2i->l2i_ret);
|
|
|
2656 |
}
|