author | Mark Johnson <Mark.Johnson@Sun.COM> |
Mon, 15 Sep 2008 15:09:45 -0700 | |
changeset 7605 | b4a19682e632 |
parent 7532 | bb6372f778bb |
child 7656 | 2621e50fdf4a |
permissions | -rw-r--r-- |
0 | 1 |
/* |
2 |
* CDDL HEADER START |
|
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* |
|
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* The contents of this file are subject to the terms of the |
|
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* Common Development and Distribution License (the "License"). |
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* You may not use this file except in compliance with the License. |
0 | 7 |
* |
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE |
|
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* or http://www.opensolaris.org/os/licensing. |
|
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* See the License for the specific language governing permissions |
|
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* and limitations under the License. |
|
12 |
* |
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* When distributing Covered Code, include this CDDL HEADER in each |
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE. |
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* If applicable, add the following below this CDDL HEADER, with the |
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* fields enclosed by brackets "[]" replaced with your own identifying |
|
17 |
* information: Portions Copyright [yyyy] [name of copyright owner] |
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* |
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* CDDL HEADER END |
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*/ |
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/* |
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* Copyright 2008 Sun Microsystems, Inc. All rights reserved. |
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* Use is subject to license terms. |
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*/ |
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||
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#include <sys/types.h> |
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28 |
#include <sys/thread.h> |
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29 |
#include <sys/cpuvar.h> |
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30 |
#include <sys/t_lock.h> |
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31 |
#include <sys/param.h> |
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32 |
#include <sys/proc.h> |
|
33 |
#include <sys/disp.h> |
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34 |
#include <sys/class.h> |
|
35 |
#include <sys/cmn_err.h> |
|
36 |
#include <sys/debug.h> |
|
37 |
#include <sys/asm_linkage.h> |
|
38 |
#include <sys/x_call.h> |
|
39 |
#include <sys/systm.h> |
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40 |
#include <sys/var.h> |
|
41 |
#include <sys/vtrace.h> |
|
42 |
#include <vm/hat.h> |
|
43 |
#include <vm/as.h> |
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44 |
#include <vm/seg_kmem.h> |
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#include <vm/seg_kp.h> |
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#include <sys/segments.h> |
47 |
#include <sys/kmem.h> |
|
48 |
#include <sys/stack.h> |
|
49 |
#include <sys/smp_impldefs.h> |
|
50 |
#include <sys/x86_archext.h> |
|
51 |
#include <sys/machsystm.h> |
|
52 |
#include <sys/traptrace.h> |
|
53 |
#include <sys/clock.h> |
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54 |
#include <sys/cpc_impl.h> |
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#include <sys/pg.h> |
56 |
#include <sys/cmt.h> |
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#include <sys/dtrace.h> |
58 |
#include <sys/archsystm.h> |
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59 |
#include <sys/fp.h> |
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60 |
#include <sys/reboot.h> |
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#include <sys/kdi_machimpl.h> |
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#include <vm/hat_i86.h> |
63 |
#include <sys/memnode.h> |
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#include <sys/pci_cfgspace.h> |
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#include <sys/mach_mmu.h> |
66 |
#include <sys/sysmacros.h> |
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#if defined(__xpv) |
68 |
#include <sys/hypervisor.h> |
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#endif |
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#include <sys/cpu_module.h> |
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struct cpu cpus[1]; /* CPU data */ |
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73 |
struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ |
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74 |
cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ |
|
75 |
||
76 |
/* |
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* Useful for disabling MP bring-up on a MP capable system. |
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*/ |
79 |
int use_mp = 1; |
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/* |
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* to be set by a PSM to indicate what cpus |
83 |
* are sitting around on the system. |
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*/ |
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cpuset_t mp_cpus; |
0 | 86 |
|
87 |
/* |
|
88 |
* This variable is used by the hat layer to decide whether or not |
|
89 |
* critical sections are needed to prevent race conditions. For sun4m, |
|
90 |
* this variable is set once enough MP initialization has been done in |
|
91 |
* order to allow cross calls. |
|
92 |
*/ |
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int flushes_require_xcalls; |
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cpuset_t cpu_ready_set; /* initialized in startup() */ |
0 | 96 |
|
97 |
static void mp_startup(void); |
|
98 |
||
99 |
static void cpu_sep_enable(void); |
|
100 |
static void cpu_sep_disable(void); |
|
101 |
static void cpu_asysc_enable(void); |
|
102 |
static void cpu_asysc_disable(void); |
|
103 |
||
104 |
/* |
|
105 |
* Init CPU info - get CPU type info for processor_info system call. |
|
106 |
*/ |
|
107 |
void |
|
108 |
init_cpu_info(struct cpu *cp) |
|
109 |
{ |
|
110 |
processor_info_t *pi = &cp->cpu_type_info; |
|
111 |
char buf[CPU_IDSTRLEN]; |
|
112 |
||
113 |
/* |
|
114 |
* Get clock-frequency property for the CPU. |
|
115 |
*/ |
|
116 |
pi->pi_clock = cpu_freq; |
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117 |
||
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/* |
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* Current frequency in Hz. |
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*/ |
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cp->cpu_curr_clock = cpu_freq_hz; |
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122 |
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/* |
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* Supported frequencies. |
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*/ |
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cpu_set_supp_freqs(cp, NULL); |
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127 |
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0 | 128 |
(void) strcpy(pi->pi_processor_type, "i386"); |
129 |
if (fpu_exists) |
|
130 |
(void) strcpy(pi->pi_fputypes, "i387 compatible"); |
|
131 |
||
132 |
(void) cpuid_getidstr(cp, buf, sizeof (buf)); |
|
133 |
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134 |
cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); |
|
135 |
(void) strcpy(cp->cpu_idstr, buf); |
|
136 |
||
137 |
cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); |
|
138 |
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139 |
(void) cpuid_getbrandstr(cp, buf, sizeof (buf)); |
|
140 |
cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); |
|
141 |
(void) strcpy(cp->cpu_brandstr, buf); |
|
142 |
||
143 |
cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); |
|
144 |
} |
|
145 |
||
146 |
/* |
|
147 |
* Configure syscall support on this CPU. |
|
148 |
*/ |
|
149 |
/*ARGSUSED*/ |
|
5295 | 150 |
void |
0 | 151 |
init_cpu_syscall(struct cpu *cp) |
152 |
{ |
|
153 |
kpreempt_disable(); |
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154 |
||
155 |
#if defined(__amd64) |
|
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if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { |
0 | 157 |
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158 |
#if !defined(__lint) |
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159 |
/* |
|
160 |
* The syscall instruction imposes a certain ordering on |
|
161 |
* segment selectors, so we double-check that ordering |
|
162 |
* here. |
|
163 |
*/ |
|
164 |
ASSERT(KDS_SEL == KCS_SEL + 8); |
|
165 |
ASSERT(UDS_SEL == U32CS_SEL + 8); |
|
166 |
ASSERT(UCS_SEL == U32CS_SEL + 16); |
|
167 |
#endif |
|
168 |
/* |
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169 |
* Turn syscall/sysret extensions on. |
|
170 |
*/ |
|
171 |
cpu_asysc_enable(); |
|
172 |
||
173 |
/* |
|
174 |
* Program the magic registers .. |
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175 |
*/ |
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wrmsr(MSR_AMD_STAR, |
177 |
((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); |
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wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); |
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wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); |
0 | 180 |
|
181 |
/* |
|
182 |
* This list of flags is masked off the incoming |
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183 |
* %rfl when we enter the kernel. |
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*/ |
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wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); |
0 | 186 |
} |
187 |
#endif |
|
188 |
||
189 |
/* |
|
190 |
* On 32-bit kernels, we use sysenter/sysexit because it's too |
|
191 |
* hard to use syscall/sysret, and it is more portable anyway. |
|
192 |
* |
|
193 |
* On 64-bit kernels on Nocona machines, the 32-bit syscall |
|
194 |
* variant isn't available to 32-bit applications, but sysenter is. |
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195 |
*/ |
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if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { |
0 | 197 |
|
198 |
#if !defined(__lint) |
|
199 |
/* |
|
200 |
* The sysenter instruction imposes a certain ordering on |
|
201 |
* segment selectors, so we double-check that ordering |
|
202 |
* here. See "sysenter" in Intel document 245471-012, "IA-32 |
|
203 |
* Intel Architecture Software Developer's Manual Volume 2: |
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204 |
* Instruction Set Reference" |
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205 |
*/ |
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206 |
ASSERT(KDS_SEL == KCS_SEL + 8); |
|
207 |
||
208 |
ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); |
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209 |
ASSERT32(UDS_SEL == UCS_SEL + 8); |
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210 |
||
211 |
ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); |
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212 |
ASSERT64(UDS_SEL == U32CS_SEL + 8); |
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213 |
#endif |
|
214 |
||
215 |
cpu_sep_enable(); |
|
216 |
||
217 |
/* |
|
218 |
* resume() sets this value to the base of the threads stack |
|
219 |
* via a context handler. |
|
220 |
*/ |
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wrmsr(MSR_INTC_SEP_ESP, 0); |
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222 |
wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); |
0 | 223 |
} |
224 |
||
225 |
kpreempt_enable(); |
|
226 |
} |
|
227 |
||
228 |
/* |
|
229 |
* Multiprocessor initialization. |
|
230 |
* |
|
231 |
* Allocate and initialize the cpu structure, TRAPTRACE buffer, and the |
|
232 |
* startup and idle threads for the specified CPU. |
|
233 |
*/ |
|
3446 | 234 |
struct cpu * |
0 | 235 |
mp_startup_init(int cpun) |
236 |
{ |
|
237 |
struct cpu *cp; |
|
238 |
kthread_id_t tp; |
|
239 |
caddr_t sp; |
|
240 |
proc_t *procp; |
|
5084 | 241 |
#if !defined(__xpv) |
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242 |
extern int idle_cpu_prefer_mwait; |
5084 | 243 |
#endif |
0 | 244 |
extern void idle(); |
245 |
||
246 |
#ifdef TRAPTRACE |
|
247 |
trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; |
|
248 |
#endif |
|
249 |
||
250 |
ASSERT(cpun < NCPU && cpu[cpun] == NULL); |
|
251 |
||
3446 | 252 |
cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); |
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#if !defined(__xpv) |
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254 |
if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) |
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cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(CPU); |
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#endif |
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257 |
|
0 | 258 |
procp = curthread->t_procp; |
259 |
||
260 |
mutex_enter(&cpu_lock); |
|
261 |
/* |
|
262 |
* Initialize the dispatcher first. |
|
263 |
*/ |
|
264 |
disp_cpu_init(cp); |
|
265 |
mutex_exit(&cpu_lock); |
|
266 |
||
414 | 267 |
cpu_vm_data_init(cp); |
268 |
||
0 | 269 |
/* |
270 |
* Allocate and initialize the startup thread for this CPU. |
|
271 |
* Interrupt and process switch stacks get allocated later |
|
272 |
* when the CPU starts running. |
|
273 |
*/ |
|
274 |
tp = thread_create(NULL, 0, NULL, NULL, 0, procp, |
|
275 |
TS_STOPPED, maxclsyspri); |
|
276 |
||
277 |
/* |
|
278 |
* Set state to TS_ONPROC since this thread will start running |
|
279 |
* as soon as the CPU comes online. |
|
280 |
* |
|
281 |
* All the other fields of the thread structure are setup by |
|
282 |
* thread_create(). |
|
283 |
*/ |
|
284 |
THREAD_ONPROC(tp, cp); |
|
285 |
tp->t_preempt = 1; |
|
286 |
tp->t_bound_cpu = cp; |
|
287 |
tp->t_affinitycnt = 1; |
|
288 |
tp->t_cpu = cp; |
|
289 |
tp->t_disp_queue = cp->cpu_disp; |
|
290 |
||
291 |
/* |
|
292 |
* Setup thread to start in mp_startup. |
|
293 |
*/ |
|
294 |
sp = tp->t_stk; |
|
295 |
tp->t_pc = (uintptr_t)mp_startup; |
|
296 |
tp->t_sp = (uintptr_t)(sp - MINFRAME); |
|
3446 | 297 |
#if defined(__amd64) |
298 |
tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ |
|
299 |
#endif |
|
0 | 300 |
|
301 |
cp->cpu_id = cpun; |
|
302 |
cp->cpu_self = cp; |
|
303 |
cp->cpu_thread = tp; |
|
304 |
cp->cpu_lwp = NULL; |
|
305 |
cp->cpu_dispthread = tp; |
|
306 |
cp->cpu_dispatch_pri = DISP_PRIO(tp); |
|
307 |
||
308 |
/* |
|
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309 |
* cpu_base_spl must be set explicitly here to prevent any blocking |
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310 |
* operations in mp_startup from causing the spl of the cpu to drop |
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311 |
* to 0 (allowing device interrupts before we're ready) in resume(). |
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312 |
* cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. |
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313 |
* As an extra bit of security on DEBUG kernels, this is enforced with |
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314 |
* an assertion in mp_startup() -- before cpu_base_spl is set to its |
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315 |
* proper value. |
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316 |
*/ |
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|
317 |
cp->cpu_base_spl = ipltospl(LOCK_LEVEL); |
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318 |
|
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|
319 |
/* |
0 | 320 |
* Now, initialize per-CPU idle thread for this CPU. |
321 |
*/ |
|
322 |
tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); |
|
323 |
||
324 |
cp->cpu_idle_thread = tp; |
|
325 |
||
326 |
tp->t_preempt = 1; |
|
327 |
tp->t_bound_cpu = cp; |
|
328 |
tp->t_affinitycnt = 1; |
|
329 |
tp->t_cpu = cp; |
|
330 |
tp->t_disp_queue = cp->cpu_disp; |
|
331 |
||
332 |
/* |
|
3434 | 333 |
* Bootstrap the CPU's PG data |
60
747dee212c5e
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334 |
*/ |
3434 | 335 |
pg_cpu_bootstrap(cp); |
60
747dee212c5e
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diff
changeset
|
337 |
/* |
3446 | 338 |
* Perform CPC initialization on the new CPU. |
0 | 339 |
*/ |
340 |
kcpc_hw_init(cp); |
|
341 |
||
342 |
/* |
|
343 |
* Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 |
|
344 |
* for each CPU. |
|
345 |
*/ |
|
346 |
setup_vaddr_for_ppcopy(cp); |
|
347 |
||
348 |
/* |
|
3446 | 349 |
* Allocate page for new GDT and initialize from current GDT. |
0 | 350 |
*/ |
3446 | 351 |
#if !defined(__lint) |
352 |
ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); |
|
353 |
#endif |
|
5460
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
354 |
cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); |
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
355 |
bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); |
1626 | 356 |
|
3446 | 357 |
#if defined(__i386) |
0 | 358 |
/* |
359 |
* setup kernel %gs. |
|
360 |
*/ |
|
361 |
set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, |
|
362 |
SEL_KPL, 0, 1); |
|
3446 | 363 |
#endif |
0 | 364 |
|
365 |
/* |
|
366 |
* If we have more than one node, each cpu gets a copy of IDT |
|
367 |
* local to its node. If this is a Pentium box, we use cpu 0's |
|
368 |
* IDT. cpu 0's IDT has been made read-only to workaround the |
|
369 |
* cmpxchgl register bug |
|
370 |
*/ |
|
371 |
if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { |
|
5460
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
372 |
#if !defined(__lint) |
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
373 |
ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); |
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
374 |
#endif |
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
375 |
cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); |
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
376 |
bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); |
3446 | 377 |
} else { |
5460
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
378 |
cp->cpu_idt = CPU->cpu_idt; |
0 | 379 |
} |
380 |
||
381 |
/* |
|
3446 | 382 |
* Get interrupt priority data from cpu 0. |
0 | 383 |
*/ |
384 |
cp->cpu_pri_data = CPU->cpu_pri_data; |
|
385 |
||
3446 | 386 |
/* |
387 |
* alloc space for cpuid info |
|
388 |
*/ |
|
389 |
cpuid_alloc_space(cp); |
|
390 |
||
4581 | 391 |
/* |
392 |
* alloc space for ucode_info |
|
393 |
*/ |
|
394 |
ucode_alloc_space(cp); |
|
395 |
||
0 | 396 |
hat_cpu_online(cp); |
397 |
||
398 |
#ifdef TRAPTRACE |
|
399 |
/* |
|
3446 | 400 |
* If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers |
0 | 401 |
*/ |
402 |
ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); |
|
403 |
ttc->ttc_next = ttc->ttc_first; |
|
404 |
ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; |
|
405 |
#endif |
|
406 |
/* |
|
407 |
* Record that we have another CPU. |
|
408 |
*/ |
|
409 |
mutex_enter(&cpu_lock); |
|
410 |
/* |
|
411 |
* Initialize the interrupt threads for this CPU |
|
412 |
*/ |
|
1455
b43f098fa50c
6378953 allocation of interrupt threads could be more common
andrei
parents:
1414
diff
changeset
|
413 |
cpu_intr_alloc(cp, NINTR_THREADS); |
0 | 414 |
/* |
415 |
* Add CPU to list of available CPUs. It'll be on the active list |
|
416 |
* after mp_startup(). |
|
417 |
*/ |
|
418 |
cpu_add_unit(cp); |
|
419 |
mutex_exit(&cpu_lock); |
|
3446 | 420 |
|
421 |
return (cp); |
|
422 |
} |
|
423 |
||
424 |
/* |
|
425 |
* Undo what was done in mp_startup_init |
|
426 |
*/ |
|
427 |
static void |
|
428 |
mp_startup_fini(struct cpu *cp, int error) |
|
429 |
{ |
|
430 |
mutex_enter(&cpu_lock); |
|
431 |
||
432 |
/* |
|
433 |
* Remove the CPU from the list of available CPUs. |
|
434 |
*/ |
|
435 |
cpu_del_unit(cp->cpu_id); |
|
436 |
||
437 |
if (error == ETIMEDOUT) { |
|
438 |
/* |
|
439 |
* The cpu was started, but never *seemed* to run any |
|
440 |
* code in the kernel; it's probably off spinning in its |
|
441 |
* own private world, though with potential references to |
|
442 |
* our kmem-allocated IDTs and GDTs (for example). |
|
443 |
* |
|
444 |
* Worse still, it may actually wake up some time later, |
|
445 |
* so rather than guess what it might or might not do, we |
|
446 |
* leave the fundamental data structures intact. |
|
447 |
*/ |
|
448 |
cp->cpu_flags = 0; |
|
449 |
mutex_exit(&cpu_lock); |
|
450 |
return; |
|
451 |
} |
|
452 |
||
453 |
/* |
|
454 |
* At this point, the only threads bound to this CPU should |
|
455 |
* special per-cpu threads: it's idle thread, it's pause threads, |
|
456 |
* and it's interrupt threads. Clean these up. |
|
457 |
*/ |
|
458 |
cpu_destroy_bound_threads(cp); |
|
459 |
cp->cpu_idle_thread = NULL; |
|
460 |
||
461 |
/* |
|
462 |
* Free the interrupt stack. |
|
463 |
*/ |
|
464 |
segkp_release(segkp, |
|
465 |
cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); |
|
466 |
||
467 |
mutex_exit(&cpu_lock); |
|
468 |
||
469 |
#ifdef TRAPTRACE |
|
470 |
/* |
|
471 |
* Discard the trap trace buffer |
|
472 |
*/ |
|
473 |
{ |
|
474 |
trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; |
|
475 |
||
476 |
kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); |
|
477 |
ttc->ttc_first = NULL; |
|
478 |
} |
|
479 |
#endif |
|
480 |
||
481 |
hat_cpu_offline(cp); |
|
482 |
||
483 |
cpuid_free_space(cp); |
|
484 |
||
4581 | 485 |
ucode_free_space(cp); |
486 |
||
5460
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
487 |
if (cp->cpu_idt != CPU->cpu_idt) |
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
488 |
kmem_free(cp->cpu_idt, PAGESIZE); |
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
489 |
cp->cpu_idt = NULL; |
3446 | 490 |
|
5460
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
491 |
kmem_free(cp->cpu_gdt, PAGESIZE); |
265cc42b6f62
6624280 GDT, LDT, IDT and TSS should not share pages with other things
josephb
parents:
5295
diff
changeset
|
492 |
cp->cpu_gdt = NULL; |
3446 | 493 |
|
494 |
teardown_vaddr_for_ppcopy(cp); |
|
495 |
||
496 |
kcpc_hw_fini(cp); |
|
497 |
||
498 |
cp->cpu_dispthread = NULL; |
|
499 |
cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ |
|
500 |
||
501 |
cpu_vm_data_destroy(cp); |
|
502 |
||
503 |
mutex_enter(&cpu_lock); |
|
504 |
disp_cpu_fini(cp); |
|
505 |
mutex_exit(&cpu_lock); |
|
506 |
||
5084 | 507 |
#if !defined(__xpv) |
5045
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4877
diff
changeset
|
508 |
if (cp->cpu_m.mcpu_mwait != NULL) |
75a798a98460
6577948 mach_alloc_mwait leaks memory when a CPU fails to start
bholler
parents:
4877
diff
changeset
|
509 |
cpuid_mwait_free(cp); |
5084 | 510 |
#endif |
3446 | 511 |
kmem_free(cp, sizeof (*cp)); |
0 | 512 |
} |
513 |
||
514 |
/* |
|
515 |
* Apply workarounds for known errata, and warn about those that are absent. |
|
516 |
* |
|
517 |
* System vendors occasionally create configurations which contain different |
|
518 |
* revisions of the CPUs that are almost but not exactly the same. At the |
|
519 |
* time of writing, this meant that their clock rates were the same, their |
|
520 |
* feature sets were the same, but the required workaround were -not- |
|
521 |
* necessarily the same. So, this routine is invoked on -every- CPU soon |
|
522 |
* after starting to make sure that the resulting system contains the most |
|
523 |
* pessimal set of workarounds needed to cope with *any* of the CPUs in the |
|
524 |
* system. |
|
525 |
* |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
526 |
* workaround_errata is invoked early in mlsetup() for CPU 0, and in |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
527 |
* mp_startup() for all slave CPUs. Slaves process workaround_errata prior |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
528 |
* to acknowledging their readiness to the master, so this routine will |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
529 |
* never be executed by multiple CPUs in parallel, thus making updates to |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
530 |
* global data safe. |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
531 |
* |
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
532 |
* These workarounds are based on Rev 3.57 of the Revision Guide for |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
533 |
* AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. |
0 | 534 |
*/ |
535 |
||
3446 | 536 |
#if defined(OPTERON_ERRATUM_88) |
537 |
int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ |
|
538 |
#endif |
|
539 |
||
0 | 540 |
#if defined(OPTERON_ERRATUM_91) |
541 |
int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ |
|
542 |
#endif |
|
543 |
||
544 |
#if defined(OPTERON_ERRATUM_93) |
|
545 |
int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ |
|
546 |
#endif |
|
547 |
||
3446 | 548 |
#if defined(OPTERON_ERRATUM_95) |
549 |
int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ |
|
550 |
#endif |
|
551 |
||
0 | 552 |
#if defined(OPTERON_ERRATUM_100) |
553 |
int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ |
|
554 |
#endif |
|
555 |
||
3446 | 556 |
#if defined(OPTERON_ERRATUM_108) |
557 |
int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ |
|
558 |
#endif |
|
559 |
||
0 | 560 |
#if defined(OPTERON_ERRATUM_109) |
561 |
int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ |
|
562 |
#endif |
|
563 |
||
564 |
#if defined(OPTERON_ERRATUM_121) |
|
565 |
int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ |
|
566 |
#endif |
|
567 |
||
568 |
#if defined(OPTERON_ERRATUM_122) |
|
569 |
int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ |
|
570 |
#endif |
|
571 |
||
572 |
#if defined(OPTERON_ERRATUM_123) |
|
573 |
int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ |
|
574 |
#endif |
|
575 |
||
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
576 |
#if defined(OPTERON_ERRATUM_131) |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
577 |
int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
578 |
#endif |
0 | 579 |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
580 |
#if defined(OPTERON_WORKAROUND_6336786) |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
581 |
int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
582 |
int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
583 |
#endif |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
584 |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
585 |
#if defined(OPTERON_WORKAROUND_6323525) |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
586 |
int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
587 |
#endif |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
588 |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
589 |
#if defined(OPTERON_ERRATUM_298) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
590 |
int opteron_erratum_298; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
591 |
#endif |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
592 |
|
3446 | 593 |
static void |
594 |
workaround_warning(cpu_t *cp, uint_t erratum) |
|
595 |
{ |
|
596 |
cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", |
|
597 |
cp->cpu_id, erratum); |
|
598 |
} |
|
599 |
||
600 |
static void |
|
601 |
workaround_applied(uint_t erratum) |
|
602 |
{ |
|
603 |
if (erratum > 1000000) |
|
604 |
cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", |
|
605 |
erratum); |
|
606 |
else |
|
607 |
cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", |
|
608 |
erratum); |
|
609 |
} |
|
610 |
||
611 |
static void |
|
612 |
msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) |
|
613 |
{ |
|
614 |
cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", |
|
615 |
cp->cpu_id, rw, msr, error); |
|
616 |
} |
|
0 | 617 |
|
5893
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
618 |
/* |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
619 |
* Determine the number of nodes in an Opteron / Greyhound family system. |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
620 |
*/ |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
621 |
static uint_t |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
622 |
opteron_get_nnodes(void) |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
623 |
{ |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
624 |
static uint_t nnodes = 0; |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
625 |
|
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
626 |
#ifdef DEBUG |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
627 |
uint_t family; |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
628 |
|
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
629 |
family = cpuid_getfamily(CPU); |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
630 |
ASSERT(family == 0xf || family == 0x10); |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
631 |
#endif /* DEBUG */ |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
632 |
|
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
633 |
if (nnodes == 0) { |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
634 |
/* |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
635 |
* Obtain the number of nodes in the system from |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
636 |
* bits [6:4] of the Node ID register on node 0. |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
637 |
* |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
638 |
* The actual node count is NodeID[6:4] + 1 |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
639 |
* |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
640 |
* The Node ID register is accessed via function 0, |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
641 |
* offset 0x60. Node 0 is device 24. |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
642 |
*/ |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
643 |
nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
644 |
} |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
645 |
return (nnodes); |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
646 |
} |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
647 |
|
5084 | 648 |
#if defined(__xpv) |
649 |
||
650 |
/* |
|
651 |
* On dom0, we can determine the number of physical cpus on the machine. |
|
652 |
* This number is important when figuring out what workarounds are |
|
653 |
* appropriate, so compute it now. |
|
654 |
*/ |
|
6670 | 655 |
uint_t |
5084 | 656 |
xen_get_nphyscpus(void) |
657 |
{ |
|
658 |
static uint_t nphyscpus = 0; |
|
659 |
||
660 |
ASSERT(DOMAIN_IS_INITDOMAIN(xen_info)); |
|
661 |
||
662 |
if (nphyscpus == 0) { |
|
663 |
xen_sysctl_t op; |
|
664 |
xen_sysctl_physinfo_t *pi = &op.u.physinfo; |
|
665 |
||
666 |
op.cmd = XEN_SYSCTL_physinfo; |
|
667 |
op.interface_version = XEN_SYSCTL_INTERFACE_VERSION; |
|
668 |
if (HYPERVISOR_sysctl(&op) == 0) |
|
669 |
nphyscpus = pi->threads_per_core * |
|
670 |
pi->cores_per_socket * pi->sockets_per_node * |
|
671 |
pi->nr_nodes; |
|
672 |
} |
|
673 |
return (nphyscpus); |
|
674 |
} |
|
675 |
#endif |
|
676 |
||
0 | 677 |
uint_t |
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
678 |
do_erratum_298(struct cpu *cpu) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
679 |
{ |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
680 |
static int osvwrc = -3; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
681 |
extern int osvw_opteron_erratum(cpu_t *, uint_t); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
682 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
683 |
/* |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
684 |
* L2 Eviction May Occur During Processor Operation To Set |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
685 |
* Accessed or Dirty Bit. |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
686 |
*/ |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
687 |
if (osvwrc == -3) { |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
688 |
osvwrc = osvw_opteron_erratum(cpu, 298); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
689 |
} else { |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
690 |
/* osvw return codes should be consistent for all cpus */ |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
691 |
ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
692 |
} |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
693 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
694 |
switch (osvwrc) { |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
695 |
case 0: /* erratum is not present: do nothing */ |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
696 |
break; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
697 |
case 1: /* erratum is present: BIOS workaround applied */ |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
698 |
/* |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
699 |
* check if workaround is actually in place and issue warning |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
700 |
* if not. |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
701 |
*/ |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
702 |
if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
703 |
((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
704 |
#if defined(OPTERON_ERRATUM_298) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
705 |
opteron_erratum_298++; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
706 |
#else |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
707 |
workaround_warning(cpu, 298); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
708 |
return (1); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
709 |
#endif |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
710 |
} |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
711 |
break; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
712 |
case -1: /* cannot determine via osvw: check cpuid */ |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
713 |
if ((cpuid_opteron_erratum(cpu, 298) > 0) && |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
714 |
(((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
715 |
((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
716 |
#if defined(OPTERON_ERRATUM_298) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
717 |
opteron_erratum_298++; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
718 |
#else |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
719 |
workaround_warning(cpu, 298); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
720 |
return (1); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
721 |
#endif |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
722 |
} |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
723 |
break; |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
724 |
} |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
725 |
return (0); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
726 |
} |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
727 |
|
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
728 |
uint_t |
0 | 729 |
workaround_errata(struct cpu *cpu) |
730 |
{ |
|
731 |
uint_t missing = 0; |
|
732 |
||
733 |
ASSERT(cpu == CPU); |
|
734 |
||
735 |
/*LINTED*/ |
|
736 |
if (cpuid_opteron_erratum(cpu, 88) > 0) { |
|
737 |
/* |
|
738 |
* SWAPGS May Fail To Read Correct GS Base |
|
739 |
*/ |
|
740 |
#if defined(OPTERON_ERRATUM_88) |
|
741 |
/* |
|
742 |
* The workaround is an mfence in the relevant assembler code |
|
743 |
*/ |
|
3446 | 744 |
opteron_erratum_88++; |
0 | 745 |
#else |
3446 | 746 |
workaround_warning(cpu, 88); |
0 | 747 |
missing++; |
748 |
#endif |
|
749 |
} |
|
750 |
||
751 |
if (cpuid_opteron_erratum(cpu, 91) > 0) { |
|
752 |
/* |
|
753 |
* Software Prefetches May Report A Page Fault |
|
754 |
*/ |
|
755 |
#if defined(OPTERON_ERRATUM_91) |
|
756 |
/* |
|
757 |
* fix is in trap.c |
|
758 |
*/ |
|
759 |
opteron_erratum_91++; |
|
760 |
#else |
|
3446 | 761 |
workaround_warning(cpu, 91); |
0 | 762 |
missing++; |
763 |
#endif |
|
764 |
} |
|
765 |
||
766 |
if (cpuid_opteron_erratum(cpu, 93) > 0) { |
|
767 |
/* |
|
768 |
* RSM Auto-Halt Restart Returns to Incorrect RIP |
|
769 |
*/ |
|
770 |
#if defined(OPTERON_ERRATUM_93) |
|
771 |
/* |
|
772 |
* fix is in trap.c |
|
773 |
*/ |
|
774 |
opteron_erratum_93++; |
|
775 |
#else |
|
3446 | 776 |
workaround_warning(cpu, 93); |
0 | 777 |
missing++; |
778 |
#endif |
|
779 |
} |
|
780 |
||
781 |
/*LINTED*/ |
|
782 |
if (cpuid_opteron_erratum(cpu, 95) > 0) { |
|
783 |
/* |
|
784 |
* RET Instruction May Return to Incorrect EIP |
|
785 |
*/ |
|
786 |
#if defined(OPTERON_ERRATUM_95) |
|
787 |
#if defined(_LP64) |
|
788 |
/* |
|
789 |
* Workaround this by ensuring that 32-bit user code and |
|
790 |
* 64-bit kernel code never occupy the same address |
|
791 |
* range mod 4G. |
|
792 |
*/ |
|
793 |
if (_userlimit32 > 0xc0000000ul) |
|
794 |
*(uintptr_t *)&_userlimit32 = 0xc0000000ul; |
|
795 |
||
796 |
/*LINTED*/ |
|
797 |
ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); |
|
3446 | 798 |
opteron_erratum_95++; |
0 | 799 |
#endif /* _LP64 */ |
800 |
#else |
|
3446 | 801 |
workaround_warning(cpu, 95); |
0 | 802 |
missing++; |
3446 | 803 |
#endif |
0 | 804 |
} |
805 |
||
806 |
if (cpuid_opteron_erratum(cpu, 100) > 0) { |
|
807 |
/* |
|
808 |
* Compatibility Mode Branches Transfer to Illegal Address |
|
809 |
*/ |
|
810 |
#if defined(OPTERON_ERRATUM_100) |
|
811 |
/* |
|
812 |
* fix is in trap.c |
|
813 |
*/ |
|
814 |
opteron_erratum_100++; |
|
815 |
#else |
|
3446 | 816 |
workaround_warning(cpu, 100); |
0 | 817 |
missing++; |
818 |
#endif |
|
819 |
} |
|
820 |
||
821 |
/*LINTED*/ |
|
822 |
if (cpuid_opteron_erratum(cpu, 108) > 0) { |
|
823 |
/* |
|
824 |
* CPUID Instruction May Return Incorrect Model Number In |
|
825 |
* Some Processors |
|
826 |
*/ |
|
827 |
#if defined(OPTERON_ERRATUM_108) |
|
828 |
/* |
|
829 |
* (Our cpuid-handling code corrects the model number on |
|
830 |
* those processors) |
|
831 |
*/ |
|
832 |
#else |
|
3446 | 833 |
workaround_warning(cpu, 108); |
0 | 834 |
missing++; |
835 |
#endif |
|
836 |
} |
|
837 |
||
838 |
/*LINTED*/ |
|
3446 | 839 |
if (cpuid_opteron_erratum(cpu, 109) > 0) do { |
0 | 840 |
/* |
841 |
* Certain Reverse REP MOVS May Produce Unpredictable Behaviour |
|
842 |
*/ |
|
843 |
#if defined(OPTERON_ERRATUM_109) |
|
3446 | 844 |
/* |
845 |
* The "workaround" is to print a warning to upgrade the BIOS |
|
846 |
*/ |
|
847 |
uint64_t value; |
|
848 |
const uint_t msr = MSR_AMD_PATCHLEVEL; |
|
849 |
int err; |
|
0 | 850 |
|
3446 | 851 |
if ((err = checked_rdmsr(msr, &value)) != 0) { |
852 |
msr_warning(cpu, "rd", msr, err); |
|
853 |
workaround_warning(cpu, 109); |
|
854 |
missing++; |
|
855 |
} |
|
856 |
if (value == 0) |
|
0 | 857 |
opteron_erratum_109++; |
858 |
#else |
|
3446 | 859 |
workaround_warning(cpu, 109); |
0 | 860 |
missing++; |
861 |
#endif |
|
3446 | 862 |
/*CONSTANTCONDITION*/ |
863 |
} while (0); |
|
864 |
||
0 | 865 |
/*LINTED*/ |
866 |
if (cpuid_opteron_erratum(cpu, 121) > 0) { |
|
867 |
/* |
|
868 |
* Sequential Execution Across Non_Canonical Boundary Caused |
|
869 |
* Processor Hang |
|
870 |
*/ |
|
871 |
#if defined(OPTERON_ERRATUM_121) |
|
3446 | 872 |
#if defined(_LP64) |
0 | 873 |
/* |
874 |
* Erratum 121 is only present in long (64 bit) mode. |
|
875 |
* Workaround is to include the page immediately before the |
|
876 |
* va hole to eliminate the possibility of system hangs due to |
|
877 |
* sequential execution across the va hole boundary. |
|
878 |
*/ |
|
3446 | 879 |
if (opteron_erratum_121) |
880 |
opteron_erratum_121++; |
|
881 |
else { |
|
882 |
if (hole_start) { |
|
883 |
hole_start -= PAGESIZE; |
|
884 |
} else { |
|
885 |
/* |
|
886 |
* hole_start not yet initialized by |
|
887 |
* mmu_init. Initialize hole_start |
|
888 |
* with value to be subtracted. |
|
889 |
*/ |
|
890 |
hole_start = PAGESIZE; |
|
0 | 891 |
} |
3446 | 892 |
opteron_erratum_121++; |
0 | 893 |
} |
3446 | 894 |
#endif /* _LP64 */ |
0 | 895 |
#else |
3446 | 896 |
workaround_warning(cpu, 121); |
0 | 897 |
missing++; |
898 |
#endif |
|
899 |
} |
|
900 |
||
901 |
/*LINTED*/ |
|
3446 | 902 |
if (cpuid_opteron_erratum(cpu, 122) > 0) do { |
0 | 903 |
/* |
3446 | 904 |
* TLB Flush Filter May Cause Coherency Problem in |
0 | 905 |
* Multiprocessor Systems |
906 |
*/ |
|
907 |
#if defined(OPTERON_ERRATUM_122) |
|
3446 | 908 |
uint64_t value; |
909 |
const uint_t msr = MSR_AMD_HWCR; |
|
910 |
int error; |
|
911 |
||
0 | 912 |
/* |
913 |
* Erratum 122 is only present in MP configurations (multi-core |
|
914 |
* or multi-processor). |
|
915 |
*/ |
|
5084 | 916 |
#if defined(__xpv) |
917 |
if (!DOMAIN_IS_INITDOMAIN(xen_info)) |
|
918 |
break; |
|
919 |
if (!opteron_erratum_122 && xen_get_nphyscpus() == 1) |
|
920 |
break; |
|
921 |
#else |
|
5893
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
922 |
if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && |
3446 | 923 |
cpuid_get_ncpu_per_chip(cpu) == 1) |
924 |
break; |
|
5084 | 925 |
#endif |
3446 | 926 |
/* disable TLB Flush Filter */ |
927 |
||
928 |
if ((error = checked_rdmsr(msr, &value)) != 0) { |
|
929 |
msr_warning(cpu, "rd", msr, error); |
|
930 |
workaround_warning(cpu, 122); |
|
931 |
missing++; |
|
932 |
} else { |
|
933 |
value |= (uint64_t)AMD_HWCR_FFDIS; |
|
934 |
if ((error = checked_wrmsr(msr, value)) != 0) { |
|
935 |
msr_warning(cpu, "wr", msr, error); |
|
936 |
workaround_warning(cpu, 122); |
|
937 |
missing++; |
|
938 |
} |
|
0 | 939 |
} |
3446 | 940 |
opteron_erratum_122++; |
0 | 941 |
#else |
3446 | 942 |
workaround_warning(cpu, 122); |
0 | 943 |
missing++; |
944 |
#endif |
|
3446 | 945 |
/*CONSTANTCONDITION*/ |
946 |
} while (0); |
|
302
b21b2a25a939
6295986 False AMD Erratum 123 warning message on stinger dual-core machines
kchow
parents:
60
diff
changeset
|
947 |
|
0 | 948 |
/*LINTED*/ |
3446 | 949 |
if (cpuid_opteron_erratum(cpu, 123) > 0) do { |
0 | 950 |
/* |
951 |
* Bypassed Reads May Cause Data Corruption of System Hang in |
|
952 |
* Dual Core Processors |
|
953 |
*/ |
|
3446 | 954 |
#if defined(OPTERON_ERRATUM_123) |
955 |
uint64_t value; |
|
956 |
const uint_t msr = MSR_AMD_PATCHLEVEL; |
|
957 |
int err; |
|
958 |
||
0 | 959 |
/* |
960 |
* Erratum 123 applies only to multi-core cpus. |
|
961 |
*/ |
|
3446 | 962 |
if (cpuid_get_ncpu_per_chip(cpu) < 2) |
963 |
break; |
|
5084 | 964 |
#if defined(__xpv) |
965 |
if (!DOMAIN_IS_INITDOMAIN(xen_info)) |
|
966 |
break; |
|
967 |
#endif |
|
3446 | 968 |
/* |
969 |
* The "workaround" is to print a warning to upgrade the BIOS |
|
970 |
*/ |
|
971 |
if ((err = checked_rdmsr(msr, &value)) != 0) { |
|
972 |
msr_warning(cpu, "rd", msr, err); |
|
973 |
workaround_warning(cpu, 123); |
|
974 |
missing++; |
|
0 | 975 |
} |
3446 | 976 |
if (value == 0) |
977 |
opteron_erratum_123++; |
|
978 |
#else |
|
979 |
workaround_warning(cpu, 123); |
|
980 |
missing++; |
|
359
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|
981 |
|
3446 | 982 |
#endif |
983 |
/*CONSTANTCONDITION*/ |
|
984 |
} while (0); |
|
985 |
||
359
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|
986 |
/*LINTED*/ |
3446 | 987 |
if (cpuid_opteron_erratum(cpu, 131) > 0) do { |
359
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|
988 |
/* |
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parents:
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diff
changeset
|
989 |
* Multiprocessor Systems with Four or More Cores May Deadlock |
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changeset
|
990 |
* Waiting for a Probe Response |
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changeset
|
991 |
*/ |
3446 | 992 |
#if defined(OPTERON_ERRATUM_131) |
993 |
uint64_t nbcfg; |
|
994 |
const uint_t msr = MSR_AMD_NB_CFG; |
|
995 |
const uint64_t wabits = |
|
996 |
AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; |
|
997 |
int error; |
|
998 |
||
359
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|
999 |
/* |
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parents:
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diff
changeset
|
1000 |
* Erratum 131 applies to any system with four or more cores. |
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diff
changeset
|
1001 |
*/ |
3446 | 1002 |
if (opteron_erratum_131) |
1003 |
break; |
|
5084 | 1004 |
#if defined(__xpv) |
1005 |
if (!DOMAIN_IS_INITDOMAIN(xen_info)) |
|
1006 |
break; |
|
1007 |
if (xen_get_nphyscpus() < 4) |
|
1008 |
break; |
|
1009 |
#else |
|
5893
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
1010 |
if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) |
3446 | 1011 |
break; |
5084 | 1012 |
#endif |
3446 | 1013 |
/* |
1014 |
* Print a warning if neither of the workarounds for |
|
1015 |
* erratum 131 is present. |
|
1016 |
*/ |
|
1017 |
if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { |
|
1018 |
msr_warning(cpu, "rd", msr, error); |
|
1019 |
workaround_warning(cpu, 131); |
|
1020 |
missing++; |
|
1021 |
} else if ((nbcfg & wabits) == 0) { |
|
1022 |
opteron_erratum_131++; |
|
1023 |
} else { |
|
1024 |
/* cannot have both workarounds set */ |
|
1025 |
ASSERT((nbcfg & wabits) != wabits); |
|
359
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|
1026 |
} |
3446 | 1027 |
#else |
1028 |
workaround_warning(cpu, 131); |
|
1029 |
missing++; |
|
359
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|
1030 |
#endif |
3446 | 1031 |
/*CONSTANTCONDITION*/ |
1032 |
} while (0); |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
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parents:
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diff
changeset
|
1033 |
|
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
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diff
changeset
|
1034 |
/* |
3446 | 1035 |
* This isn't really an erratum, but for convenience the |
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
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parents:
770
diff
changeset
|
1036 |
* detection/workaround code lives here and in cpuid_opteron_erratum. |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
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parents:
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diff
changeset
|
1037 |
*/ |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1038 |
if (cpuid_opteron_erratum(cpu, 6336786) > 0) { |
3446 | 1039 |
#if defined(OPTERON_WORKAROUND_6336786) |
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1040 |
/* |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1041 |
* Disable C1-Clock ramping on multi-core/multi-processor |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1042 |
* K8 platforms to guard against TSC drift. |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
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diff
changeset
|
1043 |
*/ |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1044 |
if (opteron_workaround_6336786) { |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1045 |
opteron_workaround_6336786++; |
5084 | 1046 |
#if defined(__xpv) |
1047 |
} else if ((DOMAIN_IS_INITDOMAIN(xen_info) && |
|
1048 |
xen_get_nphyscpus() > 1) || |
|
1049 |
opteron_workaround_6336786_UP) { |
|
1050 |
/* |
|
5893
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
1051 |
* XXPV Hmm. We can't walk the Northbridges on |
5084 | 1052 |
* the hypervisor; so just complain and drive |
1053 |
* on. This probably needs to be fixed in |
|
1054 |
* the hypervisor itself. |
|
1055 |
*/ |
|
1056 |
opteron_workaround_6336786++; |
|
1057 |
workaround_warning(cpu, 6336786); |
|
1058 |
#else /* __xpv */ |
|
5893
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
1059 |
} else if ((opteron_get_nnodes() * |
5894
16a9cdac6a22
6629854 node interleaving can undermine C1 clock ramping workaround (fix cstyle)
esaxe
parents:
5893
diff
changeset
|
1060 |
cpuid_get_ncpu_per_chip(cpu) > 1) || |
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1061 |
opteron_workaround_6336786_UP) { |
5893
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
1062 |
|
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
1063 |
uint_t node, nnodes; |
3446 | 1064 |
uint8_t data; |
1065 |
||
5893
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
1066 |
nnodes = opteron_get_nnodes(); |
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
1067 |
for (node = 0; node < nnodes; node++) { |
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1068 |
/* |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1069 |
* Clear PMM7[1:0] (function 3, offset 0x87) |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1070 |
* Northbridge device is the node id + 24. |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1071 |
*/ |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1072 |
data = pci_getb_func(0, node + 24, 3, 0x87); |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1073 |
data &= 0xFC; |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1074 |
pci_putb_func(0, node + 24, 3, 0x87, data); |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1075 |
} |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1076 |
opteron_workaround_6336786++; |
5084 | 1077 |
#endif /* __xpv */ |
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1078 |
} |
3446 | 1079 |
#else |
1080 |
workaround_warning(cpu, 6336786); |
|
1081 |
missing++; |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
770
diff
changeset
|
1082 |
#endif |
3446 | 1083 |
} |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1084 |
|
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1085 |
/*LINTED*/ |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1086 |
/* |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1087 |
* Mutex primitives don't work as expected. |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1088 |
*/ |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1089 |
if (cpuid_opteron_erratum(cpu, 6323525) > 0) { |
3446 | 1090 |
#if defined(OPTERON_WORKAROUND_6323525) |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1091 |
/* |
3446 | 1092 |
* This problem only occurs with 2 or more cores. If bit in |
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1093 |
* MSR_AMD_BU_CFG set, then not applicable. The workaround |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1094 |
* is to patch the semaphone routines with the lfence |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1095 |
* instruction to provide necessary load memory barrier with |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1096 |
* possible subsequent read-modify-write ops. |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1097 |
* |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1098 |
* It is too early in boot to call the patch routine so |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1099 |
* set erratum variable to be done in startup_end(). |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1100 |
*/ |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1101 |
if (opteron_workaround_6323525) { |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1102 |
opteron_workaround_6323525++; |
5084 | 1103 |
#if defined(__xpv) |
1104 |
} else if (x86_feature & X86_SSE2) { |
|
1105 |
if (DOMAIN_IS_INITDOMAIN(xen_info)) { |
|
1106 |
/* |
|
1107 |
* XXPV Use dom0_msr here when extended |
|
1108 |
* operations are supported? |
|
1109 |
*/ |
|
1110 |
if (xen_get_nphyscpus() > 1) |
|
1111 |
opteron_workaround_6323525++; |
|
1112 |
} else { |
|
1113 |
/* |
|
1114 |
* We have no way to tell how many physical |
|
1115 |
* cpus there are, or even if this processor |
|
1116 |
* has the problem, so enable the workaround |
|
1117 |
* unconditionally (at some performance cost). |
|
1118 |
*/ |
|
1119 |
opteron_workaround_6323525++; |
|
1120 |
} |
|
1121 |
#else /* __xpv */ |
|
5893
6c165e7db1e4
6629854 node interleaving can undermine C1 clock ramping workaround
esaxe
parents:
5460
diff
changeset
|
1122 |
} else if ((x86_feature & X86_SSE2) && ((opteron_get_nnodes() * |
3446 | 1123 |
cpuid_get_ncpu_per_chip(cpu)) > 1)) { |
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1124 |
if ((xrdmsr(MSR_AMD_BU_CFG) & 0x02) == 0) |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1125 |
opteron_workaround_6323525++; |
5084 | 1126 |
#endif /* __xpv */ |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1127 |
} |
3446 | 1128 |
#else |
1129 |
workaround_warning(cpu, 6323525); |
|
1130 |
missing++; |
|
1131 |
#endif |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1482
diff
changeset
|
1132 |
} |
3446 | 1133 |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1134 |
missing += do_erratum_298(cpu); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1135 |
|
5084 | 1136 |
#ifdef __xpv |
1137 |
return (0); |
|
1138 |
#else |
|
0 | 1139 |
return (missing); |
5084 | 1140 |
#endif |
0 | 1141 |
} |
1142 |
||
1143 |
void |
|
1144 |
workaround_errata_end() |
|
1145 |
{ |
|
3446 | 1146 |
#if defined(OPTERON_ERRATUM_88) |
1147 |
if (opteron_erratum_88) |
|
1148 |
workaround_applied(88); |
|
1149 |
#endif |
|
1150 |
#if defined(OPTERON_ERRATUM_91) |
|
1151 |
if (opteron_erratum_91) |
|
1152 |
workaround_applied(91); |
|
1153 |
#endif |
|
1154 |
#if defined(OPTERON_ERRATUM_93) |
|
1155 |
if (opteron_erratum_93) |
|
1156 |
workaround_applied(93); |
|
1157 |
#endif |
|
1158 |
#if defined(OPTERON_ERRATUM_95) |
|
1159 |
if (opteron_erratum_95) |
|
1160 |
workaround_applied(95); |
|
1161 |
#endif |
|
1162 |
#if defined(OPTERON_ERRATUM_100) |
|
1163 |
if (opteron_erratum_100) |
|
1164 |
workaround_applied(100); |
|
1165 |
#endif |
|
1166 |
#if defined(OPTERON_ERRATUM_108) |
|
1167 |
if (opteron_erratum_108) |
|
1168 |
workaround_applied(108); |
|
1169 |
#endif |
|
0 | 1170 |
#if defined(OPTERON_ERRATUM_109) |
1171 |
if (opteron_erratum_109) { |
|
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1172 |
cmn_err(CE_WARN, |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1173 |
"BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1174 |
" processor\nerratum 109 was not detected; updating your" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1175 |
" system's BIOS to a version\ncontaining this" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1176 |
" microcode patch is HIGHLY recommended or erroneous" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1177 |
" system\noperation may occur.\n"); |
0 | 1178 |
} |
3446 | 1179 |
#endif |
1180 |
#if defined(OPTERON_ERRATUM_121) |
|
1181 |
if (opteron_erratum_121) |
|
1182 |
workaround_applied(121); |
|
1183 |
#endif |
|
1184 |
#if defined(OPTERON_ERRATUM_122) |
|
1185 |
if (opteron_erratum_122) |
|
1186 |
workaround_applied(122); |
|
1187 |
#endif |
|
0 | 1188 |
#if defined(OPTERON_ERRATUM_123) |
1189 |
if (opteron_erratum_123) { |
|
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1190 |
cmn_err(CE_WARN, |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1191 |
"BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1192 |
" processor\nerratum 123 was not detected; updating your" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1193 |
" system's BIOS to a version\ncontaining this" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1194 |
" microcode patch is HIGHLY recommended or erroneous" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1195 |
" system\noperation may occur.\n"); |
0 | 1196 |
} |
3446 | 1197 |
#endif |
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1198 |
#if defined(OPTERON_ERRATUM_131) |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1199 |
if (opteron_erratum_131) { |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1200 |
cmn_err(CE_WARN, |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1201 |
"BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1202 |
" processor\nerratum 131 was not detected; updating your" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1203 |
" system's BIOS to a version\ncontaining this" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1204 |
" microcode patch is HIGHLY recommended or erroneous" |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1205 |
" system\noperation may occur.\n"); |
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
302
diff
changeset
|
1206 |
} |
3446 | 1207 |
#endif |
1208 |
#if defined(OPTERON_WORKAROUND_6336786) |
|
1209 |
if (opteron_workaround_6336786) |
|
1210 |
workaround_applied(6336786); |
|
1211 |
#endif |
|
1212 |
#if defined(OPTERON_WORKAROUND_6323525) |
|
1213 |
if (opteron_workaround_6323525) |
|
1214 |
workaround_applied(6323525); |
|
1215 |
#endif |
|
6691
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1216 |
#if defined(OPTERON_ERRATUM_298) |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1217 |
if (opteron_erratum_298) { |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1218 |
cmn_err(CE_WARN, |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1219 |
"BIOS microcode patch for AMD 64/Opteron(tm)" |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1220 |
" processor\nerratum 298 was not detected; updating your" |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1221 |
" system's BIOS to a version\ncontaining this" |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1222 |
" microcode patch is HIGHLY recommended or erroneous" |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1223 |
" system\noperation may occur.\n"); |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1224 |
} |
f8848c7acc9e
6671130 Shanghai provides better TLB management for 1GB pages
kchow
parents:
6670
diff
changeset
|
1225 |
#endif |
0 | 1226 |
} |
1227 |
||
3446 | 1228 |
static cpuset_t procset; |
1229 |
||
1230 |
/* |
|
1231 |
* Start a single cpu, assuming that the kernel context is available |
|
1232 |
* to successfully start another cpu. |
|
1233 |
* |
|
1234 |
* (For example, real mode code is mapped into the right place |
|
1235 |
* in memory and is ready to be run.) |
|
1236 |
*/ |
|
1237 |
int |
|
1238 |
start_cpu(processorid_t who) |
|
1239 |
{ |
|
1240 |
void *ctx; |
|
1241 |
cpu_t *cp; |
|
1242 |
int delays; |
|
1243 |
int error = 0; |
|
1244 |
||
1245 |
ASSERT(who != 0); |
|
1246 |
||
1247 |
/* |
|
1248 |
* Check if there's at least a Mbyte of kmem available |
|
1249 |
* before attempting to start the cpu. |
|
1250 |
*/ |
|
1251 |
if (kmem_avail() < 1024 * 1024) { |
|
1252 |
/* |
|
1253 |
* Kick off a reap in case that helps us with |
|
1254 |
* later attempts .. |
|
1255 |
*/ |
|
1256 |
kmem_reap(); |
|
1257 |
return (ENOMEM); |
|
1258 |
} |
|
1259 |
||
1260 |
cp = mp_startup_init(who); |
|
1261 |
if ((ctx = mach_cpucontext_alloc(cp)) == NULL || |
|
1262 |
(error = mach_cpu_start(cp, ctx)) != 0) { |
|
1263 |
||
1264 |
/* |
|
1265 |
* Something went wrong before we even started it |
|
1266 |
*/ |
|
1267 |
if (ctx) |
|
1268 |
cmn_err(CE_WARN, |
|
1269 |
"cpu%d: failed to start error %d", |
|
1270 |
cp->cpu_id, error); |
|
1271 |
else |
|
1272 |
cmn_err(CE_WARN, |
|
1273 |
"cpu%d: failed to allocate context", cp->cpu_id); |
|
0 | 1274 |
|
3446 | 1275 |
if (ctx) |
1276 |
mach_cpucontext_free(cp, ctx, error); |
|
1277 |
else |
|
1278 |
error = EAGAIN; /* hmm. */ |
|
1279 |
mp_startup_fini(cp, error); |
|
1280 |
return (error); |
|
1281 |
} |
|
1282 |
||
1283 |
for (delays = 0; !CPU_IN_SET(procset, who); delays++) { |
|
1284 |
if (delays == 500) { |
|
1285 |
/* |
|
1286 |
* After five seconds, things are probably looking |
|
1287 |
* a bit bleak - explain the hang. |
|
1288 |
*/ |
|
1289 |
cmn_err(CE_NOTE, "cpu%d: started, " |
|
1290 |
"but not running in the kernel yet", who); |
|
1291 |
} else if (delays > 2000) { |
|
1292 |
/* |
|
1293 |
* We waited at least 20 seconds, bail .. |
|
1294 |
*/ |
|
1295 |
error = ETIMEDOUT; |
|
1296 |
cmn_err(CE_WARN, "cpu%d: timed out", who); |
|
1297 |
mach_cpucontext_free(cp, ctx, error); |
|
1298 |
mp_startup_fini(cp, error); |
|
1299 |
return (error); |
|
1300 |
} |
|
1301 |
||
1302 |
/* |
|
1303 |
* wait at least 10ms, then check again.. |
|
1304 |
*/ |
|
1305 |
delay(USEC_TO_TICK_ROUNDUP(10000)); |
|
1306 |
} |
|
1307 |
||
1308 |
mach_cpucontext_free(cp, ctx, 0); |
|
1309 |
||
5084 | 1310 |
#ifndef __xpv |
3446 | 1311 |
if (tsc_gethrtime_enable) |
1312 |
tsc_sync_master(who); |
|
5084 | 1313 |
#endif |
3446 | 1314 |
|
1315 |
if (dtrace_cpu_init != NULL) { |
|
1316 |
/* |
|
1317 |
* DTrace CPU initialization expects cpu_lock to be held. |
|
1318 |
*/ |
|
1319 |
mutex_enter(&cpu_lock); |
|
1320 |
(*dtrace_cpu_init)(who); |
|
1321 |
mutex_exit(&cpu_lock); |
|
1322 |
} |
|
1323 |
||
1324 |
while (!CPU_IN_SET(cpu_ready_set, who)) |
|
1325 |
delay(1); |
|
1326 |
||
1327 |
return (0); |
|
1328 |
} |
|
1329 |
||
2006 | 1330 |
|
0 | 1331 |
/*ARGSUSED*/ |
1332 |
void |
|
1333 |
start_other_cpus(int cprboot) |
|
1334 |
{ |
|
3446 | 1335 |
uint_t who; |
1336 |
uint_t skipped = 0; |
|
1337 |
uint_t bootcpuid = 0; |
|
0 | 1338 |
|
1339 |
/* |
|
1340 |
* Initialize our own cpu_info. |
|
1341 |
*/ |
|
1342 |
init_cpu_info(CPU); |
|
1343 |
||
1344 |
/* |
|
1345 |
* Initialize our syscall handlers |
|
1346 |
*/ |
|
1347 |
init_cpu_syscall(CPU); |
|
1348 |
||
1349 |
/* |
|
3446 | 1350 |
* Take the boot cpu out of the mp_cpus set because we know |
1351 |
* it's already running. Add it to the cpu_ready_set for |
|
1352 |
* precisely the same reason. |
|
1353 |
*/ |
|
1354 |
CPUSET_DEL(mp_cpus, bootcpuid); |
|
1355 |
CPUSET_ADD(cpu_ready_set, bootcpuid); |
|
1356 |
||
1357 |
/* |
|
0 | 1358 |
* if only 1 cpu or not using MP, skip the rest of this |
1359 |
*/ |
|
3446 | 1360 |
if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { |
0 | 1361 |
if (use_mp == 0) |
1362 |
cmn_err(CE_CONT, "?***** Not in MP mode\n"); |
|
1363 |
goto done; |
|
1364 |
} |
|
1365 |
||
1366 |
/* |
|
1367 |
* perform such initialization as is needed |
|
1368 |
* to be able to take CPUs on- and off-line. |
|
1369 |
*/ |
|
1370 |
cpu_pause_init(); |
|
1371 |
||
1372 |
xc_init(); /* initialize processor crosscalls */ |
|
1373 |
||
3446 | 1374 |
if (mach_cpucontext_init() != 0) |
0 | 1375 |
goto done; |
1376 |
||
1377 |
flushes_require_xcalls = 1; |
|
1378 |
||
2575
a95d80de4e01
6436283 anonymous tracing is broken on MP systems
nf202958
parents:
2519
diff
changeset
|
1379 |
/* |
a95d80de4e01
6436283 anonymous tracing is broken on MP systems
nf202958
parents:
2519
diff
changeset
|
1380 |
* We lock our affinity to the master CPU to ensure that all slave CPUs |
a95d80de4e01
6436283 anonymous tracing is broken on MP systems
nf202958
parents:
2519
diff
changeset
|
1381 |
* do their TSC syncs with the same CPU. |
a95d80de4e01
6436283 anonymous tracing is broken on MP systems
nf202958
parents:
2519
diff
changeset
|
1382 |
*/ |
0 | 1383 |
affinity_set(CPU_CURRENT); |
1384 |
||
1385 |
for (who = 0; who < NCPU; who++) { |
|
2575
a95d80de4e01
6436283 anonymous tracing is broken on MP systems
nf202958
parents:
2519
diff
changeset
|
1386 |
|
2006 | 1387 |
if (!CPU_IN_SET(mp_cpus, who)) |
1388 |
continue; |
|
3446 | 1389 |
ASSERT(who != bootcpuid); |
2006 | 1390 |
if (ncpus >= max_ncpus) { |
1391 |
skipped = who; |
|
0 | 1392 |
continue; |
2006 | 1393 |
} |
3446 | 1394 |
if (start_cpu(who) != 0) |
1395 |
CPUSET_DEL(mp_cpus, who); |
|
0 | 1396 |
} |
1397 |
||
4581 | 1398 |
/* Free the space allocated to hold the microcode file */ |
7605
b4a19682e632
6747590 microcode update support for AMD
Mark Johnson <Mark.Johnson@Sun.COM>
parents:
7532
diff
changeset
|
1399 |
ucode_cleanup(); |
4581 | 1400 |
|
0 | 1401 |
affinity_clear(); |
1402 |
||
2006 | 1403 |
if (skipped) { |
1404 |
cmn_err(CE_NOTE, |
|
3446 | 1405 |
"System detected %d cpus, but " |
1406 |
"only %d cpu(s) were enabled during boot.", |
|
2006 | 1407 |
skipped + 1, ncpus); |
1408 |
cmn_err(CE_NOTE, |
|
1409 |
"Use \"boot-ncpus\" parameter to enable more CPU(s). " |
|
1410 |
"See eeprom(1M)."); |
|
1411 |
} |
|
1412 |
||
0 | 1413 |
done: |
1414 |
workaround_errata_end(); |
|
3446 | 1415 |
mach_cpucontext_fini(); |
1642
f7086dc70948
6398359 do not enable amd dram scrubber if local node has no memory
gavinm
parents:
1626
diff
changeset
|
1416 |
|
f7086dc70948
6398359 do not enable amd dram scrubber if local node has no memory
gavinm
parents:
1626
diff
changeset
|
1417 |
cmi_post_mpstartup(); |
0 | 1418 |
} |
1419 |
||
1420 |
/* |
|
1421 |
* Dummy functions - no i86pc platforms support dynamic cpu allocation. |
|
1422 |
*/ |
|
1423 |
/*ARGSUSED*/ |
|
1424 |
int |
|
1425 |
mp_cpu_configure(int cpuid) |
|
1426 |
{ |
|
1427 |
return (ENOTSUP); /* not supported */ |
|
1428 |
} |
|
1429 |
||
1430 |
/*ARGSUSED*/ |
|
1431 |
int |
|
1432 |
mp_cpu_unconfigure(int cpuid) |
|
1433 |
{ |
|
1434 |
return (ENOTSUP); /* not supported */ |
|
1435 |
} |
|
1436 |
||
1437 |
/* |
|
1438 |
* Startup function for 'other' CPUs (besides boot cpu). |
|
2985
78b075f897aa
6480953 system seems hung,invisible panic, on debug kernel, never gets to mp_startup
dmick
parents:
2575
diff
changeset
|
1439 |
* Called from real_mode_start. |
1251
beb2ccc7537c
6305935 Attaching driver to CPU triggers ASSERT on MP systems on reboot
kchow
parents:
938
diff
changeset
|
1440 |
* |
beb2ccc7537c
6305935 Attaching driver to CPU triggers ASSERT on MP systems on reboot
kchow
parents:
938
diff
changeset
|
1441 |
* WARNING: until CPU_READY is set, mp_startup and routines called by |
beb2ccc7537c
6305935 Attaching driver to CPU triggers ASSERT on MP systems on reboot
kchow
parents:
938
diff
changeset
|
1442 |
* mp_startup should not call routines (e.g. kmem_free) that could call |
beb2ccc7537c
6305935 Attaching driver to CPU triggers ASSERT on MP systems on reboot
kchow
parents:
938
diff
changeset
|
1443 |
* hat_unload which requires CPU_READY to be set. |
0 | 1444 |
*/ |
1445 |
void |
|
1446 |
mp_startup(void) |
|
1447 |
{ |
|
1448 |
struct cpu *cp = CPU; |
|
1449 |
uint_t new_x86_feature; |
|
1450 |
||
2985
78b075f897aa
6480953 system seems hung,invisible panic, on debug kernel, never gets to mp_startup
dmick
parents:
2575
diff
changeset
|
1451 |
/* |
3021
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1452 |
* We need to get TSC on this proc synced (i.e., any delta |
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1453 |
* from cpu0 accounted for) as soon as we can, because many |
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1454 |
* many things use gethrtime/pc_gethrestime, including |
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1455 |
* interrupts, cmn_err, etc. |
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1456 |
*/ |
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1457 |
|
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1458 |
/* Let cpu0 continue into tsc_sync_master() */ |
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1459 |
CPUSET_ATOMIC_ADD(procset, cp->cpu_id); |
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1460 |
|
5084 | 1461 |
#ifndef __xpv |
3021
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1462 |
if (tsc_gethrtime_enable) |
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1463 |
tsc_sync_slave(); |
5084 | 1464 |
#endif |
3021
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1465 |
|
900097ae20cf
6446729 "cpu 1 failed to start" when TSC counters are not in sync
dmick
parents:
2985
diff
changeset
|
1466 |
/* |
2985
78b075f897aa
6480953 system seems hung,invisible panic, on debug kernel, never gets to mp_startup
dmick
parents:
2575
diff
changeset
|
1467 |
* Once this was done from assembly, but it's safer here; if |
78b075f897aa
6480953 system seems hung,invisible panic, on debug kernel, never gets to mp_startup
dmick
parents:
2575
diff
changeset
|
1468 |
* it blocks, we need to be able to swtch() to and from, and |
78b075f897aa
6480953 system seems hung,invisible panic, on debug kernel, never gets to mp_startup
dmick
parents:
2575
diff
changeset
|
1469 |
* since we get here by calling t_pc, we need to do that call |
78b075f897aa
6480953 system seems hung,invisible panic, on debug kernel, never gets to mp_startup
dmick
parents:
2575
diff
changeset
|
1470 |
* before swtch() overwrites it. |
78b075f897aa
6480953 system seems hung,invisible panic, on debug kernel, never gets to mp_startup
dmick
parents:
2575
diff
changeset
|
1471 |
*/ |
78b075f897aa
6480953 system seems hung,invisible panic, on debug kernel, never gets to mp_startup
dmick
parents:
2575
diff
changeset
|
1472 |
(void) (*ap_mlsetup)(); |
78b075f897aa
6480953 system seems hung,invisible panic, on debug kernel, never gets to mp_startup
dmick
parents:
2575
diff
changeset
|
1473 |
|
0 | 1474 |
new_x86_feature = cpuid_pass1(cp); |
1475 |
||
5084 | 1476 |
#ifndef __xpv |
0 | 1477 |
/* |
5159
6cdd421a2458
6590353 ancient mtrr crud in i86pc/os/startup.c must die
johnlev
parents:
5084
diff
changeset
|
1478 |
* Program this cpu's PAT |
0 | 1479 |
*/ |
5159
6cdd421a2458
6590353 ancient mtrr crud in i86pc/os/startup.c must die
johnlev
parents:
5084
diff
changeset
|
1480 |
if (x86_feature & X86_PAT) |
6cdd421a2458
6590353 ancient mtrr crud in i86pc/os/startup.c must die
johnlev
parents:
5084
diff
changeset
|
1481 |
pat_sync(); |
5084 | 1482 |
#endif |
0 | 1483 |
|
1484 |
/* |
|
3446 | 1485 |
* Set up TSC_AUX to contain the cpuid for this processor |
1486 |
* for the rdtscp instruction. |
|
1487 |
*/ |
|
1488 |
if (x86_feature & X86_TSCP) |
|
1489 |
(void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); |
|
1490 |
||
1491 |
/* |
|
0 | 1492 |
* Initialize this CPU's syscall handlers |
1493 |
*/ |
|
1494 |
init_cpu_syscall(cp); |
|
1495 |
||
1496 |
/* |
|
1497 |
* Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the |
|
1498 |
* highest level at which a routine is permitted to block on |
|
1499 |
* an adaptive mutex (allows for cpu poke interrupt in case |
|
1500 |
* the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks |
|
1501 |
* device interrupts that may end up in the hat layer issuing cross |
|
1502 |
* calls before CPU_READY is set. |
|
1503 |
*/ |
|
3446 | 1504 |
splx(ipltospl(LOCK_LEVEL)); |
1505 |
sti(); |
|
0 | 1506 |
|
1507 |
/* |
|
1508 |
* Do a sanity check to make sure this new CPU is a sane thing |
|
1509 |
* to add to the collection of processors running this system. |
|
1510 |
* |
|
1511 |
* XXX Clearly this needs to get more sophisticated, if x86 |
|
1512 |
* systems start to get built out of heterogenous CPUs; as is |
|
1513 |
* likely to happen once the number of processors in a configuration |
|
1514 |
* gets large enough. |
|
1515 |
*/ |
|
1516 |
if ((x86_feature & new_x86_feature) != x86_feature) { |
|
1517 |
cmn_err(CE_CONT, "?cpu%d: %b\n", |
|
1518 |
cp->cpu_id, new_x86_feature, FMT_X86_FEATURE); |
|
1519 |
cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); |
|
1520 |
} |
|
1521 |
||
1522 |
/* |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
3446
diff
changeset
|
1523 |
* We do not support cpus with mixed monitor/mwait support if the |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
3446
diff
changeset
|
1524 |
* boot cpu supports monitor/mwait. |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
3446
diff
changeset
|
1525 |
*/ |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
3446
diff
changeset
|
1526 |
if ((x86_feature & ~new_x86_feature) & X86_MWAIT) |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
3446
diff
changeset
|
1527 |
panic("unsupported mixed cpu monitor/mwait support detected"); |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
3446
diff
changeset
|
1528 |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
3446
diff
changeset
|
1529 |
/* |
0 | 1530 |
* We could be more sophisticated here, and just mark the CPU |
1531 |
* as "faulted" but at this point we'll opt for the easier |
|
1532 |
* answer of dieing horribly. Provided the boot cpu is ok, |
|
1533 |
* the system can be recovered by booting with use_mp set to zero. |
|
1534 |
*/ |
|
1535 |
if (workaround_errata(cp) != 0) |
|
1536 |
panic("critical workaround(s) missing for cpu%d", cp->cpu_id); |
|
1537 |
||
1538 |
cpuid_pass2(cp); |
|
1539 |
cpuid_pass3(cp); |
|
1540 |
(void) cpuid_pass4(cp); |
|
1541 |
||
1542 |
init_cpu_info(cp); |
|
1543 |
||
1544 |
mutex_enter(&cpu_lock); |
|
1545 |
/* |
|
3434 | 1546 |
* Processor group initialization for this CPU is dependent on the |
1547 |
* cpuid probing, which must be done in the context of the current |
|
1548 |
* CPU. |
|
0 | 1549 |
*/ |
3434 | 1550 |
pghw_physid_create(cp); |
1551 |
pg_cpu_init(cp); |
|
1552 |
pg_cmt_cpu_startup(cp); |
|
0 | 1553 |
|
6749
22c537726e3e
6657646 diskless mp system hangs during mp_startup(), with device interrupts masked
sherrym
parents:
6691
diff
changeset
|
1554 |
cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; |
2575
a95d80de4e01
6436283 anonymous tracing is broken on MP systems
nf202958
parents:
2519
diff
changeset
|
1555 |
|
a95d80de4e01
6436283 anonymous tracing is broken on MP systems
nf202958
parents:
2519
diff
changeset
|
1556 |
if (dtrace_cpu_init != NULL) { |
a95d80de4e01
6436283 anonymous tracing is broken on MP systems
nf202958
parents:
2519
diff
changeset
|
1557 |
(*dtrace_cpu_init)(cp->cpu_id); |
a95d80de4e01
6436283 anonymous tracing is broken on MP systems
nf202958
parents:
2519
diff
changeset
|
1558 |
} |
a95d80de4e01
6436283 anonymous tracing is broken on MP systems
nf202958
parents:
2519
diff
changeset
|
1559 |
|
4581 | 1560 |
/* |
1561 |
* Fill out cpu_ucode_info. Update microcode if necessary. |
|
1562 |
*/ |
|
1563 |
ucode_check(cp); |
|
1564 |
||
0 | 1565 |
mutex_exit(&cpu_lock); |
1566 |
||
3029
e8e4c69d4f79
6488621 mp_startup must enable kernel preemption as soon as CPUs are ready
sethg
parents:
3021
diff
changeset
|
1567 |
/* |
e8e4c69d4f79
6488621 mp_startup must enable kernel preemption as soon as CPUs are ready
sethg
parents:
3021
diff
changeset
|
1568 |
* Enable preemption here so that contention for any locks acquired |
e8e4c69d4f79
6488621 mp_startup must enable kernel preemption as soon as CPUs are ready
sethg
parents:
3021
diff
changeset
|
1569 |
* later in mp_startup may be preempted if the thread owning those |
e8e4c69d4f79
6488621 mp_startup must enable kernel preemption as soon as CPUs are ready
sethg
parents:
3021
diff
changeset
|
1570 |
* locks is continously executing on other CPUs (for example, this |
e8e4c69d4f79
6488621 mp_startup must enable kernel preemption as soon as CPUs are ready
sethg
parents:
3021
diff
changeset
|
1571 |
* CPU must be preemptible to allow other CPUs to pause it during their |
e8e4c69d4f79
6488621 mp_startup must enable kernel preemption as soon as CPUs are ready
sethg
parents:
3021
diff
changeset
|
1572 |
* startup phases). It's safe to enable preemption here because the |
e8e4c69d4f79
6488621 mp_startup must enable kernel preemption as soon as CPUs are ready
sethg
parents:
3021
diff
changeset
|
1573 |
* CPU state is pretty-much fully constructed. |
e8e4c69d4f79
6488621 mp_startup must enable kernel preemption as soon as CPUs are ready
sethg
parents:
3021
diff
changeset
|
1574 |
*/ |
e8e4c69d4f79
6488621 mp_startup must enable kernel preemption as soon as CPUs are ready
sethg
parents:
3021
diff
changeset
|
1575 |
curthread->t_preempt = 0; |
e8e4c69d4f79
6488621 mp_startup must enable kernel preemption as soon as CPUs are ready
sethg
parents:
3021
diff
changeset
|
1576 |
|
1482
dd0dbac7d2af
6381715 cpu_base_spl must be set before mp_startup to prevent device interrupts from inducing panics
sethg
parents:
1455
diff
changeset
|
1577 |
/* The base spl should still be at LOCK LEVEL here */ |
dd0dbac7d2af
6381715 cpu_base_spl must be set before mp_startup to prevent device interrupts from inducing panics
sethg
parents:
1455
diff
changeset
|
1578 |
ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); |
dd0dbac7d2af
6381715 cpu_base_spl must be set before mp_startup to prevent device interrupts from inducing panics
sethg
parents:
1455
diff
changeset
|
1579 |
set_base_spl(); /* Restore the spl to its proper value */ |
dd0dbac7d2af
6381715 cpu_base_spl must be set before mp_startup to prevent device interrupts from inducing panics
sethg
parents:
1455
diff
changeset
|
1580 |
|
6749
22c537726e3e
6657646 diskless mp system hangs during mp_startup(), with device interrupts masked
sherrym
parents:
6691
diff
changeset
|
1581 |
/* Enable interrupts */ |
22c537726e3e
6657646 diskless mp system hangs during mp_startup(), with device interrupts masked
sherrym
parents:
6691
diff
changeset
|
1582 |
(void) spl0(); |
22c537726e3e
6657646 diskless mp system hangs during mp_startup(), with device interrupts masked
sherrym
parents:
6691
diff
changeset
|
1583 |
mutex_enter(&cpu_lock); |
22c537726e3e
6657646 diskless mp system hangs during mp_startup(), with device interrupts masked
sherrym
parents:
6691
diff
changeset
|
1584 |
cpu_enable_intr(cp); |
22c537726e3e
6657646 diskless mp system hangs during mp_startup(), with device interrupts masked
sherrym
parents:
6691
diff
changeset
|
1585 |
cpu_add_active(cp); |
22c537726e3e
6657646 diskless mp system hangs during mp_startup(), with device interrupts masked
sherrym
parents:
6691
diff
changeset
|
1586 |
mutex_exit(&cpu_lock); |
22c537726e3e
6657646 diskless mp system hangs during mp_startup(), with device interrupts masked
sherrym
parents:
6691
diff
changeset
|
1587 |
|
22c537726e3e
6657646 diskless mp system hangs during mp_startup(), with device interrupts masked
sherrym
parents:
6691
diff
changeset
|
1588 |
add_cpunode2devtree(cp->cpu_id, cp->cpu_m.mcpu_cpi); |
0 | 1589 |
|
5254
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1590 |
#ifndef __xpv |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1591 |
{ |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1592 |
/* |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1593 |
* Set up the CPU module for this CPU. This can't be done |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1594 |
* before this CPU is made CPU_READY, because we may (in |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1595 |
* heterogeneous systems) need to go load another CPU module. |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1596 |
* The act of attempting to load a module may trigger a |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1597 |
* cross-call, which will ASSERT unless this cpu is CPU_READY. |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1598 |
*/ |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1599 |
cmi_hdl_t hdl; |
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1389
diff
changeset
|
1600 |
|
5254
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1601 |
if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), |
7532
bb6372f778bb
PSARC 2008/569 FMA Topology & Retire Agent Refinements
Cheng Sean Ye <Sean.Ye@Sun.COM>
parents:
7349
diff
changeset
|
1602 |
cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { |
5254
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1603 |
if (x86_feature & X86_MCA) |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1604 |
cmi_mca_init(hdl); |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1605 |
} |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1606 |
} |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1607 |
#endif /* __xpv */ |
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1389
diff
changeset
|
1608 |
|
0 | 1609 |
if (boothowto & RB_DEBUG) |
3446 | 1610 |
kdi_cpu_init(); |
0 | 1611 |
|
1612 |
/* |
|
1613 |
* Setting the bit in cpu_ready_set must be the last operation in |
|
1614 |
* processor initialization; the boot CPU will continue to boot once |
|
1615 |
* it sees this bit set for all active CPUs. |
|
1616 |
*/ |
|
1617 |
CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); |
|
1618 |
||
1619 |
/* |
|
1620 |
* Because mp_startup() gets fired off after init() starts, we |
|
1621 |
* can't use the '?' trick to do 'boot -v' printing - so we |
|
1622 |
* always direct the 'cpu .. online' messages to the log. |
|
1623 |
*/ |
|
1624 |
cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", |
|
1625 |
cp->cpu_id); |
|
1626 |
||
1627 |
/* |
|
1628 |
* Now we are done with the startup thread, so free it up. |
|
1629 |
*/ |
|
1630 |
thread_exit(); |
|
1631 |
panic("mp_startup: cannot return"); |
|
1632 |
/*NOTREACHED*/ |
|
1633 |
} |
|
1634 |
||
1635 |
||
1636 |
/* |
|
1637 |
* Start CPU on user request. |
|
1638 |
*/ |
|
1639 |
/* ARGSUSED */ |
|
1640 |
int |
|
1641 |
mp_cpu_start(struct cpu *cp) |
|
1642 |
{ |
|
1643 |
ASSERT(MUTEX_HELD(&cpu_lock)); |
|
1644 |
return (0); |
|
1645 |
} |
|
1646 |
||
1647 |
/* |
|
1648 |
* Stop CPU on user request. |
|
1649 |
*/ |
|
1650 |
/* ARGSUSED */ |
|
1651 |
int |
|
1652 |
mp_cpu_stop(struct cpu *cp) |
|
1653 |
{ |
|
1389 | 1654 |
extern int cbe_psm_timer_mode; |
0 | 1655 |
ASSERT(MUTEX_HELD(&cpu_lock)); |
1389 | 1656 |
|
5084 | 1657 |
#ifdef __xpv |
1658 |
/* |
|
1659 |
* We can't offline vcpu0. |
|
1660 |
*/ |
|
1661 |
if (cp->cpu_id == 0) |
|
1662 |
return (EBUSY); |
|
1663 |
#endif |
|
1664 |
||
1389 | 1665 |
/* |
1666 |
* If TIMER_PERIODIC mode is used, CPU0 is the one running it; |
|
1667 |
* can't stop it. (This is true only for machines with no TSC.) |
|
1668 |
*/ |
|
1669 |
||
1670 |
if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) |
|
5084 | 1671 |
return (EBUSY); |
0 | 1672 |
|
1673 |
return (0); |
|
1674 |
} |
|
1675 |
||
1676 |
/* |
|
1677 |
* Take the specified CPU out of participation in interrupts. |
|
1678 |
*/ |
|
1679 |
int |
|
1680 |
cpu_disable_intr(struct cpu *cp) |
|
1681 |
{ |
|
1682 |
if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) |
|
1683 |
return (EBUSY); |
|
1684 |
||
1685 |
cp->cpu_flags &= ~CPU_ENABLE; |
|
1686 |
return (0); |
|
1687 |
} |
|
1688 |
||
1689 |
/* |
|
1690 |
* Allow the specified CPU to participate in interrupts. |
|
1691 |
*/ |
|
1692 |
void |
|
1693 |
cpu_enable_intr(struct cpu *cp) |
|
1694 |
{ |
|
1695 |
ASSERT(MUTEX_HELD(&cpu_lock)); |
|
1696 |
cp->cpu_flags |= CPU_ENABLE; |
|
1697 |
psm_enable_intr(cp->cpu_id); |
|
1698 |
} |
|
1699 |
||
1700 |
||
5254
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1701 |
/*ARGSUSED*/ |
0 | 1702 |
void |
1703 |
mp_cpu_faulted_enter(struct cpu *cp) |
|
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1389
diff
changeset
|
1704 |
{ |
5254
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1705 |
#ifndef __xpv |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1706 |
cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1707 |
cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1708 |
|
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1709 |
if (hdl != NULL) { |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1710 |
cmi_faulted_enter(hdl); |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1711 |
cmi_hdl_rele(hdl); |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1712 |
} |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1713 |
#endif |
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1389
diff
changeset
|
1714 |
} |
0 | 1715 |
|
5254
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1716 |
/*ARGSUSED*/ |
0 | 1717 |
void |
1718 |
mp_cpu_faulted_exit(struct cpu *cp) |
|
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1389
diff
changeset
|
1719 |
{ |
5254
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1720 |
#ifndef __xpv |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1721 |
cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1722 |
cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1723 |
|
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1724 |
if (hdl != NULL) { |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1725 |
cmi_faulted_exit(hdl); |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1726 |
cmi_hdl_rele(hdl); |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1727 |
} |
38162db71c7d
PSARC 2007/591 Generic x86 Machine Check Architecture
gavinm
parents:
5159
diff
changeset
|
1728 |
#endif |
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1389
diff
changeset
|
1729 |
} |
0 | 1730 |
|
1731 |
/* |
|
1732 |
* The following two routines are used as context operators on threads belonging |
|
1733 |
* to processes with a private LDT (see sysi86). Due to the rarity of such |
|
1734 |
* processes, these routines are currently written for best code readability and |
|
1735 |
* organization rather than speed. We could avoid checking x86_feature at every |
|
1736 |
* context switch by installing different context ops, depending on the |
|
1737 |
* x86_feature flags, at LDT creation time -- one for each combination of fast |
|
1738 |
* syscall feature flags. |
|
1739 |
*/ |
|
1740 |
||
1741 |
/*ARGSUSED*/ |
|
1742 |
void |
|
1743 |
cpu_fast_syscall_disable(void *arg) |
|
1744 |
{ |
|
3446 | 1745 |
if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) |
0 | 1746 |
cpu_sep_disable(); |
3446 | 1747 |
if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) |
0 | 1748 |
cpu_asysc_disable(); |
1749 |
} |
|
1750 |
||
1751 |
/*ARGSUSED*/ |
|
1752 |
void |
|
1753 |
cpu_fast_syscall_enable(void *arg) |
|
1754 |
{ |
|
3446 | 1755 |
if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) |
0 | 1756 |
cpu_sep_enable(); |
3446 | 1757 |
if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) |
0 | 1758 |
cpu_asysc_enable(); |
1759 |
} |
|
1760 |
||
1761 |
static void |
|
1762 |
cpu_sep_enable(void) |
|
1763 |
{ |
|
1764 |
ASSERT(x86_feature & X86_SEP); |
|
1765 |
ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); |
|
1766 |
||
770
0eda482eb80f
6311933 rdmsr/wrmsr do not need to set/pass values via memory pointers
kucharsk
parents:
414
diff
changeset
|
1767 |
wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); |
0 | 1768 |
} |
1769 |
||
1770 |
static void |
|
1771 |
cpu_sep_disable(void) |
|
1772 |
{ |
|
1773 |
ASSERT(x86_feature & X86_SEP); |
|
1774 |
ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); |
|
1775 |
||
1776 |
/* |
|
1777 |
* Setting the SYSENTER_CS_MSR register to 0 causes software executing |
|
1778 |
* the sysenter or sysexit instruction to trigger a #gp fault. |
|
1779 |
*/ |
|
3446 | 1780 |
wrmsr(MSR_INTC_SEP_CS, 0); |
0 | 1781 |
} |
1782 |
||
1783 |
static void |
|
1784 |
cpu_asysc_enable(void) |
|
1785 |
{ |
|
1786 |
ASSERT(x86_feature & X86_ASYSC); |
|
1787 |
ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); |
|
1788 |
||
770
0eda482eb80f
6311933 rdmsr/wrmsr do not need to set/pass values via memory pointers
kucharsk
parents:
414
diff
changeset
|
1789 |
wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | |
0eda482eb80f
6311933 rdmsr/wrmsr do not need to set/pass values via memory pointers
kucharsk
parents:
414
diff
changeset
|
1790 |
(uint64_t)(uintptr_t)AMD_EFER_SCE); |
0 | 1791 |
} |
1792 |
||
1793 |
static void |
|
1794 |
cpu_asysc_disable(void) |
|
1795 |
{ |
|
1796 |
ASSERT(x86_feature & X86_ASYSC); |
|
1797 |
ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); |
|
1798 |
||
1799 |
/* |
|
1800 |
* Turn off the SCE (syscall enable) bit in the EFER register. Software |
|
1801 |
* executing syscall or sysret with this bit off will incur a #ud trap. |
|
1802 |
*/ |
|
770
0eda482eb80f
6311933 rdmsr/wrmsr do not need to set/pass values via memory pointers
kucharsk
parents:
414
diff
changeset
|
1803 |
wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & |
0eda482eb80f
6311933 rdmsr/wrmsr do not need to set/pass values via memory pointers
kucharsk
parents:
414
diff
changeset
|
1804 |
~((uint64_t)(uintptr_t)AMD_EFER_SCE)); |
0 | 1805 |
} |