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1 /* |
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2 * Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved. |
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3 */ |
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4 |
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5 /* |
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6 * Redistribution and use in source and binary forms, with or without modification, |
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7 * are permitted provided that the following conditions are met: |
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8 * |
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9 * 1. Redistributions of source code must retain the above copyright notice, |
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10 * this list of conditions and the following disclaimer. |
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11 * |
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12 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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13 * this list of conditions and the following disclaimer in the documentation |
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14 * and/or other materials provided with the distribution. |
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15 * |
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16 * 3. Neither the name of the copyright holder nor the names of its contributors |
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17 * may be used to endorse or promote products derived from this software without |
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18 * specific prior written permission. |
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19 * |
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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23 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
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24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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27 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
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28 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
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29 * OF THE POSSIBILITY OF SUCH DAMAGE. |
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30 */ |
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31 |
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32 #ifndef _PSIF_HW_CSR_H |
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33 #define _PSIF_HW_CSR_H |
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34 #ifdef __cplusplus |
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35 extern "C" { |
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36 #endif |
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37 |
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38 #include "psif_api.h" |
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39 |
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40 /* The psif base address setup access ids */ |
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41 enum psif_csr_map { |
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42 PSIF_CSR_ADDR_BASE_ADDR_ATSP = 0x5248, |
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43 PSIF_CSR_ADDR_BASE_ADDR_AH = 0x55948, |
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44 PSIF_CSR_ADDR_BASE_ADDR_QP = 0x55960, |
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45 PSIF_CSR_ADDR_BASE_ADDR_SQ_CMPL = 0x59d68, |
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46 PSIF_CSR_ADDR_BASE_ADDR_KEY = 0x59d80, |
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47 PSIF_CSR_ADDR_BASE_ADDR_RQSP = 0x59e08, |
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48 PSIF_CSR_ADDR_BASE_ADDR_RQ_SW = 0x59e20, |
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49 PSIF_CSR_ADDR_BASE_ADDR_RQ_HW = 0x59e38, |
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50 PSIF_CSR_ADDR_BASE_ADDR_SQ_SW = 0xc4548, |
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51 PSIF_CSR_ADDR_BASE_ADDR_SQ_HW = 0xc4560, |
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52 PSIF_CSR_ADDR_BASE_ADDR_SQ_RING = 0xc4d18, |
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53 PSIF_CSR_ADDR_BASE_ADDR_SQ_RSPQ = 0xc4f68, |
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54 PSIF_CSR_ADDR_BASE_ADDR_SQ_TVL = 0xc5388, |
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55 PSIF_CSR_ADDR_BASE_ADDR_CQ_SW = 0xcd7a0, |
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56 PSIF_CSR_ADDR_BASE_ADDR_CQ_HW = 0xcd7b8, |
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57 PSIF_CSR_ADDR_END = 0xce9f0 |
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58 }; /* enum psif_csr_map */ |
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59 |
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60 /* The psif base address setup access ids as offset in a struct */ |
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61 /* *** DEPRECATED DATA TYPE *** */ |
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62 struct psif_csr_be { |
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63 __be64 ingenting_01[((0x5248) / sizeof(__be64))]; |
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64 /* HW:TSU_HOST_QP_BASE_ADDR_0 -> struct base_addr_atsp [165 bits] */ |
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65 __be64 base_addr_atsp[3]; /* Offset 0x5248 */ |
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66 /* HW:TSU_QPS_AHA_BASE_ADDR_0 -> struct base_addr_ah [165 bits] */ |
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67 __be64 ingenting_03[((0x55948 - 0x5248) / sizeof(__be64)) - 3]; |
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68 __be64 base_addr_ah[3]; /* Offset 0x55948 */ |
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69 /* HW:TSU_QPS_QP_BASE_ADDR_0 -> struct base_addr_qp [165 bits] */ |
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70 __be64 ingenting_04[((0x55960 - 0x55948) / sizeof(__be64)) - 3]; |
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71 __be64 base_addr_qp[3]; /* Offset 0x55960 */ |
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72 /* HW:TSU_CMPL_SQ_BASE_ADDR_0 -> struct base_addr_sq_cmpl [165 bits] */ |
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73 __be64 ingenting_05[((0x59d68 - 0x55960) / sizeof(__be64)) - 3]; |
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74 __be64 base_addr_sq_cmpl[3]; /* Offset 0x59d68 */ |
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75 /* HW:TSU_VAL_KEY_BASE_ADDR_0 -> struct base_addr_key [165 bits] */ |
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76 __be64 ingenting_06[((0x59d80 - 0x59d68) / sizeof(__be64)) - 3]; |
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77 __be64 base_addr_key[3]; /* Offset 0x59d80 */ |
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78 /* HW:TSU_RQH_QP_BASE_ADDR_0 -> struct base_addr_rqsp [165 bits] */ |
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79 __be64 ingenting_07[((0x59e08 - 0x59d80) / sizeof(__be64)) - 3]; |
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80 __be64 base_addr_rqsp[3]; /* Offset 0x59e08 */ |
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81 /* HW:TSU_DSCR_RQ_BASE_ADDR_SW_0 -> struct base_addr_rq_sw [165 bits] */ |
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82 __be64 ingenting_08[((0x59e20 - 0x59e08) / sizeof(__be64)) - 3]; |
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83 __be64 base_addr_rq_sw[3]; /* Offset 0x59e20 */ |
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84 /* HW:TSU_DSCR_RQ_BASE_ADDR_HW_0 -> struct base_addr_rq_hw [165 bits] */ |
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85 __be64 ingenting_09[((0x59e38 - 0x59e20) / sizeof(__be64)) - 3]; |
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86 __be64 base_addr_rq_hw[3]; /* Offset 0x59e38 */ |
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87 /* HW:TSU_IBPR_P1_EOIB_MAC1 SW:ibpr_p1_eoib_mac1 |
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88 * -> struct psif_csr_ibpr_p1_eoib_mac1 [64 bits] */ |
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89 __be64 ingenting_10[((0xbfcb8 - 0x59e38) / sizeof(__be64)) - 1]; |
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90 __be64 ibpr_p1_eoib_mac1; /* Offset 0xbfcb8 */ |
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91 /* HW:TSU_IBPR_P1_EOIB_MAC2 SW:ibpr_p1_eoib_mac2 |
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92 * -> struct psif_csr_ibpr_p1_eoib_mac2 [64 bits] */ |
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93 __be64 ingenting_11[((0xbfcc0 - 0xbfcb8) / sizeof(__be64)) - 1]; |
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94 __be64 ibpr_p1_eoib_mac2; /* Offset 0xbfcc0 */ |
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95 /* HW:TSU_IBPR_P2_EOIB_MAC1 SW:ibpr_p2_eoib_mac1 |
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96 * -> struct psif_csr_ibpr_p2_eoib_mac1 [64 bits] */ |
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97 __be64 ingenting_12[((0xbfcc8 - 0xbfcc0) / sizeof(__be64)) - 1]; |
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98 __be64 ibpr_p2_eoib_mac1; /* Offset 0xbfcc8 */ |
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99 /* HW:TSU_IBPR_P2_EOIB_MAC2 SW:ibpr_p2_eoib_mac2 |
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100 * -> struct psif_csr_ibpr_p2_eoib_mac2 [64 bits] */ |
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101 __be64 ingenting_13[((0xbfcd0 - 0xbfcc8) / sizeof(__be64)) - 1]; |
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102 __be64 ibpr_p2_eoib_mac2; /* Offset 0xbfcd0 */ |
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103 /* HW:TSU_SQS_SQ_BASE_ADDR_SW_0 -> struct base_addr_sq_sw [165 bits] */ |
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104 __be64 ingenting_14[((0xc4548 - 0xbfcd0) / sizeof(__be64)) - 3]; |
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105 __be64 base_addr_sq_sw[3]; /* Offset 0xc4548 */ |
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106 /* HW:TSU_SQS_SQ_BASE_ADDR_HW_0 -> struct base_addr_sq_hw [165 bits] */ |
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107 __be64 ingenting_15[((0xc4560 - 0xc4548) / sizeof(__be64)) - 3]; |
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108 __be64 base_addr_sq_hw[3]; /* Offset 0xc4560 */ |
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109 /* HW:TSU_SQS_PIO_RING_BASE_ADDR_0 -> struct base_addr_sq_ring [165 bits] */ |
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110 __be64 ingenting_16[((0xc4d18 - 0xc4560) / sizeof(__be64)) - 3]; |
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111 __be64 base_addr_sq_ring[3]; /* Offset 0xc4d18 */ |
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112 /* HW:TSU_SQS_RSPQ_BASE_ADDR_0 -> struct base_addr_sq_rspq [165 bits] */ |
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113 __be64 ingenting_17[((0xc4f68 - 0xc4d18) / sizeof(__be64)) - 3]; |
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114 __be64 base_addr_sq_rspq[3]; /* Offset 0xc4f68 */ |
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115 /* HW:TSU_SQS_RSPQ_TVL_BASE_ADDR_0 -> struct base_addr_sq_tvl [165 bits] */ |
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116 __be64 ingenting_18[((0xc5388 - 0xc4f68) / sizeof(__be64)) - 3]; |
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117 __be64 base_addr_sq_tvl[3]; /* Offset 0xc5388 */ |
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118 /* HW:TSU_CBLD_CQ_BASE_ADDR_SW_0 -> struct base_addr_cq_sw [165 bits] */ |
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119 __be64 ingenting_19[((0xcd7a0 - 0xc5388) / sizeof(__be64)) - 3]; |
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120 __be64 base_addr_cq_sw[3]; /* Offset 0xcd7a0 */ |
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121 /* HW:TSU_CBLD_CQ_BASE_ADDR_HW_0 -> struct base_addr_cq_hw [165 bits] */ |
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122 __be64 ingenting_20[((0xcd7b8 - 0xcd7a0) / sizeof(__be64)) - 3]; |
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123 __be64 base_addr_cq_hw[3]; /* Offset 0xcd7b8 */ |
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124 __be64 ingenting_21[((0xce9f0 - 0xcd7b8) / sizeof(__be64)) - 3]; |
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125 }; /* struct psif_csr_be [6770560 bits] */ |
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126 |
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127 #ifdef __cplusplus |
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128 } |
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129 #endif |
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130 #endif /* _PSIF_HW_CSR_H */ |