/*

 * CDDL HEADER START

 *

 * The contents of this file are subject to the terms of the

 * Common Development and Distribution License (the "License").

 * You may not use this file except in compliance with the License.

 *

 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

 * or http://www.opensolaris.org/os/licensing.

 * See the License for the specific language governing permissions

 * and limitations under the License.

 *

 * When distributing Covered Code, include this CDDL HEADER in each

 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.

 * If applicable, add the following below this CDDL HEADER, with the

 * fields enclosed by brackets "[]" replaced with your own identifying

 * information: Portions Copyright [yyyy] [name of copyright owner]

 *

 * CDDL HEADER END

 */

/*

 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.

 * Use is subject to license terms.

 */

#pragma ident	"%Z%%M%	%I%	%E% SMI"

/*

 * Various routines to handle identification

 * and classification of x86 processors.

 */

#include <sys/types.h>

#include <sys/archsystm.h>

#include <sys/x86_archext.h>

#include <sys/kmem.h>

#include <sys/systm.h>

#include <sys/cmn_err.h>

#include <sys/sunddi.h>

#include <sys/sunndi.h>

#include <sys/cpuvar.h>

#include <sys/processor.h>

#include <sys/pg.h>

#include <sys/fp.h>

#include <sys/controlregs.h>

#include <sys/auxv_386.h>

#include <sys/bitmap.h>

#include <sys/memnode.h>

/*

 * Pass 0 of cpuid feature analysis happens in locore. It contains special code

 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with

 * them accordingly. For most modern processors, feature detection occurs here

 * in pass 1.

 *

 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()

 * for the boot CPU and does the basic analysis that the early kernel needs.

 * x86_feature is set based on the return value of cpuid_pass1() of the boot

 * CPU.

 *

 * Pass 1 includes:

 *

 *	o Determining vendor/model/family/stepping and setting x86_type and

 *	  x86_vendor accordingly.

 *	o Processing the feature flags returned by the cpuid instruction while

 *	  applying any workarounds or tricks for the specific processor.

 *	o Mapping the feature flags into Solaris feature bits (X86_*).

 *	o Processing extended feature flags if supported by the processor,

 *	  again while applying specific processor knowledge.

 *	o Determining the CMT characteristics of the system.

 *

 * Pass 1 is done on non-boot CPUs during their initialization and the results

 * are used only as a meager attempt at ensuring that all processors within the

 * system support the same features.

 *

 * Pass 2 of cpuid feature analysis happens just at the beginning

 * of startup().  It just copies in and corrects the remainder

 * of the cpuid data we depend on: standard cpuid functions that we didn't

 * need for pass1 feature analysis, and extended cpuid functions beyond the

 * simple feature processing done in pass1.

 *

 * Pass 3 of cpuid analysis is invoked after basic kernel services; in

 * particular kernel memory allocation has been made available. It creates a

 * readable brand string based on the data collected in the first two passes.

 *

 * Pass 4 of cpuid analysis is invoked after post_startup() when all

 * the support infrastructure for various hardware features has been

 * initialized. It determines which processor features will be reported

 * to userland via the aux vector.

 *

 * All passes are executed on all CPUs, but only the boot CPU determines what

 * features the kernel will use.

 *

 * Much of the worst junk in this file is for the support of processors

 * that didn't really implement the cpuid instruction properly.

 *

 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,

 * the pass numbers.  Accordingly, changes to the pass code may require changes

 * to the accessor code.

 */

uint_t x86_feature = 0;

uint_t x86_vendor = X86_VENDOR_IntelClone;

uint_t x86_type = X86_TYPE_OTHER;

uint_t pentiumpro_bug4046376;

uint_t pentiumpro_bug4064495;

uint_t enable486;

/*

 * This set of strings are for processors rumored to support the cpuid

 * instruction, and is used by locore.s to figure out how to set x86_vendor

 */

const char CyrixInstead[] = "CyrixInstead";

/*

 * These constants determine how many of the elements of the

 * cpuid we cache in the cpuid_info data structure; the

 * remaining elements are accessible via the cpuid instruction.

 */

#define	NMAX_CPI_STD	6		/* eax = 0 .. 5 */

#define	NMAX_CPI_EXTD	9		/* eax = 0x80000000 .. 0x80000008 */

struct cpuid_info {

	uint_t cpi_pass;		/* last pass completed */

	/*

	 * standard function information

	 */

	uint_t cpi_maxeax;		/* fn 0: %eax */

	char cpi_vendorstr[13];		/* fn 0: %ebx:%ecx:%edx */

	uint_t cpi_vendor;		/* enum of cpi_vendorstr */

	uint_t cpi_family;		/* fn 1: extended family */

	uint_t cpi_model;		/* fn 1: extended model */

	uint_t cpi_step;		/* fn 1: stepping */

	chipid_t cpi_chipid;		/* fn 1: %ebx: chip # on ht cpus */

	uint_t cpi_brandid;		/* fn 1: %ebx: brand ID */

	int cpi_clogid;			/* fn 1: %ebx: thread # */

	uint_t cpi_ncpu_per_chip;	/* fn 1: %ebx: logical cpu count */

	uint8_t cpi_cacheinfo[16];	/* fn 2: intel-style cache desc */

	uint_t cpi_ncache;		/* fn 2: number of elements */

	struct cpuid_regs cpi_std[NMAX_CPI_STD];	/* 0 .. 5 */

	/*

	 * extended function information

	 */

	uint_t cpi_xmaxeax;		/* fn 0x80000000: %eax */

	char cpi_brandstr[49];		/* fn 0x8000000[234] */

	uint8_t cpi_pabits;		/* fn 0x80000006: %eax */

	uint8_t cpi_vabits;		/* fn 0x80000006: %eax */

	struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */

	id_t cpi_coreid;

	uint_t cpi_ncore_per_chip;	/* AMD: fn 0x80000008: %ecx[7-0] */

					/* Intel: fn 4: %eax[31-26] */

	/*

	 * supported feature information

	 */

	uint32_t cpi_support[5];

#define	STD_EDX_FEATURES	0

#define	AMD_EDX_FEATURES	1

#define	TM_EDX_FEATURES		2

#define	STD_ECX_FEATURES	3

#define	AMD_ECX_FEATURES	4

	/*

	 * Synthesized information, where known.

	 */

	uint32_t cpi_chiprev;		/* See X86_CHIPREV_* in x86_archext.h */

	const char *cpi_chiprevstr;	/* May be NULL if chiprev unknown */

	uint32_t cpi_socket;		/* Chip package/socket type */

};

static struct cpuid_info cpuid_info0;

/*

 * These bit fields are defined by the Intel Application Note AP-485

 * "Intel Processor Identification and the CPUID Instruction"

 */

#define	CPI_FAMILY_XTD(cpi)	BITX((cpi)->cpi_std[1].cp_eax, 27, 20)

#define	CPI_MODEL_XTD(cpi)	BITX((cpi)->cpi_std[1].cp_eax, 19, 16)

#define	CPI_TYPE(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 13, 12)

#define	CPI_FAMILY(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 11, 8)

#define	CPI_STEP(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 3, 0)

#define	CPI_MODEL(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 7, 4)

#define	CPI_FEATURES_EDX(cpi)		((cpi)->cpi_std[1].cp_edx)

#define	CPI_FEATURES_ECX(cpi)		((cpi)->cpi_std[1].cp_ecx)

#define	CPI_FEATURES_XTD_EDX(cpi)	((cpi)->cpi_extd[1].cp_edx)

#define	CPI_FEATURES_XTD_ECX(cpi)	((cpi)->cpi_extd[1].cp_ecx)

#define	CPI_BRANDID(cpi)	BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)

#define	CPI_CHUNKS(cpi)		BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)

#define	CPI_CPU_COUNT(cpi)	BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)

#define	CPI_APIC_ID(cpi)	BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)

#define	CPI_MAXEAX_MAX		0x100		/* sanity control */

#define	CPI_XMAXEAX_MAX		0x80000100

/*

 * A couple of shorthand macros to identify "later" P6-family chips

 * like the Pentium M and Core.  First, the "older" P6-based stuff

 * (loosely defined as "pre-Pentium-4"):

 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon

 */

#define	IS_LEGACY_P6(cpi) (			\

	cpi->cpi_family == 6 && 		\

		(cpi->cpi_model == 1 ||		\

		cpi->cpi_model == 3 ||		\

		cpi->cpi_model == 5 ||		\

		cpi->cpi_model == 6 ||		\

		cpi->cpi_model == 7 ||		\

		cpi->cpi_model == 8 ||		\

		cpi->cpi_model == 0xA ||	\

		cpi->cpi_model == 0xB)		\

)

/* A "new F6" is everything with family 6 that's not the above */

#define	IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))

/*

 * AMD family 0xf socket types.

 * First index is 0 for revs B thru E, 1 for F and G.

 * Second index by (model & 0x3)

 */

static uint32_t amd_skts[2][4] = {

	{

		X86_SOCKET_754,		/* 0b00 */

		X86_SOCKET_940,		/* 0b01 */

		X86_SOCKET_754,		/* 0b10 */

		X86_SOCKET_939		/* 0b11 */

	},

	{

		X86_SOCKET_S1g1,	/* 0b00 */

		X86_SOCKET_F1207,	/* 0b01 */

		X86_SOCKET_UNKNOWN,	/* 0b10 */

		X86_SOCKET_AM2		/* 0b11 */

	}

};

/*

 * Table for mapping AMD Family 0xf model/stepping combination to

 * chip "revision" and socket type.  Only rm_family 0xf is used at the

 * moment, but AMD family 0x10 will extend the exsiting revision names

 * so will likely also use this table.

 *

 * The first member of this array that matches a given family, extended model

 * plus model range, and stepping range will be considered a match.

 */

static const struct amd_rev_mapent {

	uint_t rm_family;

	uint_t rm_modello;

	uint_t rm_modelhi;

	uint_t rm_steplo;

	uint_t rm_stephi;

	uint32_t rm_chiprev;

	const char *rm_chiprevstr;

	int rm_sktidx;

} amd_revmap[] = {

	/*

	 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1.

	 */

	{ 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", 0 },

	{ 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", 0 },

	/*

	 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8

	 */

	{ 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", 0 },

	/*

	 * Rev CG is the rest of extended model 0x0 - i.e., everything

	 * but the rev B and C0 combinations covered above.

	 */

	{ 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", 0 },

	/*

	 * Rev D has extended model 0x1.

	 */

	{ 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", 0 },

	/*

	 * Rev E has extended model 0x2.

	 * Extended model 0x3 is unused but available to grow into.

	 */

	{ 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", 0 },

	/*

	 * Rev F has extended models 0x4 and 0x5.

	 */

	{ 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", 1 },

	/*

	 * Rev G has extended model 0x6.

	 */

	{ 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", 1 },

};

static void

synth_amd_info(struct cpuid_info *cpi)

{

	const struct amd_rev_mapent *rmp;

	uint_t family, model, step;

	int i;

	/*

	 * Currently only AMD family 0xf uses these fields.

	 */

	if (cpi->cpi_family != 0xf)

		return;

	family = cpi->cpi_family;

	model = cpi->cpi_model;

	step = cpi->cpi_step;

	for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp);

	    i++, rmp++) {

		if (family == rmp->rm_family &&

		    model >= rmp->rm_modello && model <= rmp->rm_modelhi &&

		    step >= rmp->rm_steplo && step <= rmp->rm_stephi) {

			cpi->cpi_chiprev = rmp->rm_chiprev;

			cpi->cpi_chiprevstr = rmp->rm_chiprevstr;

			cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3];

			return;

		}

	}

}

static void

synth_info(struct cpuid_info *cpi)

{

	cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN;

	cpi->cpi_chiprevstr = "Unknown";

	cpi->cpi_socket = X86_SOCKET_UNKNOWN;

	switch (cpi->cpi_vendor) {

	case X86_VENDOR_AMD:

		synth_amd_info(cpi);

		break;

	default:

		break;

	}

}

/*

 * Apply up various platform-dependent restrictions where the

 * underlying platform restrictions mean the CPU can be marked

 * as less capable than its cpuid instruction would imply.

 */

#define	platform_cpuid_mangle(vendor, eax, cp)	/* nothing */

/*

 *  Some undocumented ways of patching the results of the cpuid

 *  instruction to permit running Solaris 10 on future cpus that

 *  we don't currently support.  Could be set to non-zero values

 *  via settings in eeprom.

 */

uint32_t cpuid_feature_ecx_include;

uint32_t cpuid_feature_ecx_exclude;

uint32_t cpuid_feature_edx_include;

uint32_t cpuid_feature_edx_exclude;

void

cpuid_alloc_space(cpu_t *cpu)

{

	/*

	 * By convention, cpu0 is the boot cpu, which is set up

	 * before memory allocation is available.  All other cpus get

	 * their cpuid_info struct allocated here.

	 */

	ASSERT(cpu->cpu_id != 0);

	cpu->cpu_m.mcpu_cpi =

	    kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);

}

void

cpuid_free_space(cpu_t *cpu)

{

	ASSERT(cpu->cpu_id != 0);

	kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi));

}

uint_t

cpuid_pass1(cpu_t *cpu)

{

	uint32_t mask_ecx, mask_edx;

	uint_t feature = X86_CPUID;

	struct cpuid_info *cpi;

	struct cpuid_regs *cp;

	int xcpuid;

	/*

	 * Space statically allocated for cpu0, ensure pointer is set

	 */

	if (cpu->cpu_id == 0)

		cpu->cpu_m.mcpu_cpi = &cpuid_info0;

	cpi = cpu->cpu_m.mcpu_cpi;

	ASSERT(cpi != NULL);

	cp = &cpi->cpi_std[0];

	cp->cp_eax = 0;

	cpi->cpi_maxeax = __cpuid_insn(cp);

	{

		uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr;

		*iptr++ = cp->cp_ebx;

		*iptr++ = cp->cp_edx;

		*iptr++ = cp->cp_ecx;

		*(char *)&cpi->cpi_vendorstr[12] = '\0';

	}

	/*

	 * Map the vendor string to a type code

	 */

	if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0)

		cpi->cpi_vendor = X86_VENDOR_Intel;

	else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0)

		cpi->cpi_vendor = X86_VENDOR_AMD;

	else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0)

		cpi->cpi_vendor = X86_VENDOR_TM;

	else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0)

		/*

		 * CyrixInstead is a variable used by the Cyrix detection code

		 * in locore.

		 */

		cpi->cpi_vendor = X86_VENDOR_Cyrix;

	else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0)

		cpi->cpi_vendor = X86_VENDOR_UMC;

	else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0)

		cpi->cpi_vendor = X86_VENDOR_NexGen;

	else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0)

		cpi->cpi_vendor = X86_VENDOR_Centaur;

	else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0)

		cpi->cpi_vendor = X86_VENDOR_Rise;

	else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0)

		cpi->cpi_vendor = X86_VENDOR_SiS;

	else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0)

		cpi->cpi_vendor = X86_VENDOR_NSC;

	else

		cpi->cpi_vendor = X86_VENDOR_IntelClone;

	x86_vendor = cpi->cpi_vendor; /* for compatibility */

	/*

	 * Limit the range in case of weird hardware

	 */

	if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)

		cpi->cpi_maxeax = CPI_MAXEAX_MAX;

	if (cpi->cpi_maxeax < 1)

		goto pass1_done;

	cp = &cpi->cpi_std[1];

	cp->cp_eax = 1;

	(void) __cpuid_insn(cp);

	/*

	 * Extract identifying constants for easy access.

	 */

	cpi->cpi_model = CPI_MODEL(cpi);

	cpi->cpi_family = CPI_FAMILY(cpi);

	if (cpi->cpi_family == 0xf)

		cpi->cpi_family += CPI_FAMILY_XTD(cpi);

	/*

	 * Intel, and presumably everyone else, uses model == 0xf, as

	 * one would expect (max value means possible overflow).  Sigh.

	 */

	switch (cpi->cpi_vendor) {

	case X86_VENDOR_AMD:

			cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;

		break;

	default:

		if (cpi->cpi_model == 0xf)

			cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;

		break;

	}

	cpi->cpi_step = CPI_STEP(cpi);

	cpi->cpi_brandid = CPI_BRANDID(cpi);

	/*

	 * *default* assumptions:

	 * - believe %edx feature word

	 * - ignore %ecx feature word

	 * - 32-bit virtual and physical addressing

	 */

	mask_edx = 0xffffffff;

	mask_ecx = 0;

	cpi->cpi_pabits = cpi->cpi_vabits = 32;

	switch (cpi->cpi_vendor) {

	case X86_VENDOR_Intel:

		if (cpi->cpi_family == 5)

			x86_type = X86_TYPE_P5;

		else if (IS_LEGACY_P6(cpi)) {

			x86_type = X86_TYPE_P6;

			pentiumpro_bug4046376 = 1;

			pentiumpro_bug4064495 = 1;

			/*

			 * Clear the SEP bit when it was set erroneously

			 */

			if (cpi->cpi_model < 3 && cpi->cpi_step < 3)

				cp->cp_edx &= ~CPUID_INTC_EDX_SEP;

		} else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) {

			x86_type = X86_TYPE_P4;

			/*

			 * We don't currently depend on any of the %ecx

			 * features until Prescott, so we'll only check