author | sherrym |
Mon, 02 Jul 2007 14:05:35 -0700 | |
changeset 4581 | b6104e41b06c |
parent 4481 | 2bb321aaf3c3 |
child 4606 | ffcd05844ec5 |
permissions | -rw-r--r-- |
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/* |
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* CDDL HEADER START |
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* |
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* The contents of this file are subject to the terms of the |
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* Common Development and Distribution License (the "License"). |
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* You may not use this file except in compliance with the License. |
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* |
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE |
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* or http://www.opensolaris.org/os/licensing. |
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* See the License for the specific language governing permissions |
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* and limitations under the License. |
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* |
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* When distributing Covered Code, include this CDDL HEADER in each |
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE. |
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* If applicable, add the following below this CDDL HEADER, with the |
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* fields enclosed by brackets "[]" replaced with your own identifying |
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* information: Portions Copyright [yyyy] [name of copyright owner] |
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* |
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* CDDL HEADER END |
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*/ |
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/* |
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* Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
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* Use is subject to license terms. |
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*/ |
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#pragma ident "%Z%%M% %I% %E% SMI" |
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/* |
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* Various routines to handle identification |
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* and classification of x86 processors. |
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*/ |
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#include <sys/types.h> |
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#include <sys/archsystm.h> |
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#include <sys/x86_archext.h> |
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#include <sys/kmem.h> |
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#include <sys/systm.h> |
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#include <sys/cmn_err.h> |
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#include <sys/sunddi.h> |
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#include <sys/sunndi.h> |
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#include <sys/cpuvar.h> |
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#include <sys/processor.h> |
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#include <sys/pg.h> |
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#include <sys/fp.h> |
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#include <sys/controlregs.h> |
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#include <sys/auxv_386.h> |
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#include <sys/bitmap.h> |
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#include <sys/memnode.h> |
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/* |
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* Pass 0 of cpuid feature analysis happens in locore. It contains special code |
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* to recognize Cyrix processors that are not cpuid-compliant, and to deal with |
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* them accordingly. For most modern processors, feature detection occurs here |
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* in pass 1. |
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* |
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* Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() |
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* for the boot CPU and does the basic analysis that the early kernel needs. |
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* x86_feature is set based on the return value of cpuid_pass1() of the boot |
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* CPU. |
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* |
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* Pass 1 includes: |
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* |
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* o Determining vendor/model/family/stepping and setting x86_type and |
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* x86_vendor accordingly. |
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* o Processing the feature flags returned by the cpuid instruction while |
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* applying any workarounds or tricks for the specific processor. |
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* o Mapping the feature flags into Solaris feature bits (X86_*). |
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* o Processing extended feature flags if supported by the processor, |
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* again while applying specific processor knowledge. |
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* o Determining the CMT characteristics of the system. |
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* |
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* Pass 1 is done on non-boot CPUs during their initialization and the results |
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* are used only as a meager attempt at ensuring that all processors within the |
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* system support the same features. |
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* |
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* Pass 2 of cpuid feature analysis happens just at the beginning |
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* of startup(). It just copies in and corrects the remainder |
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* of the cpuid data we depend on: standard cpuid functions that we didn't |
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* need for pass1 feature analysis, and extended cpuid functions beyond the |
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* simple feature processing done in pass1. |
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* |
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* Pass 3 of cpuid analysis is invoked after basic kernel services; in |
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* particular kernel memory allocation has been made available. It creates a |
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* readable brand string based on the data collected in the first two passes. |
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* |
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* Pass 4 of cpuid analysis is invoked after post_startup() when all |
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* the support infrastructure for various hardware features has been |
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* initialized. It determines which processor features will be reported |
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* to userland via the aux vector. |
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* |
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* All passes are executed on all CPUs, but only the boot CPU determines what |
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* features the kernel will use. |
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* |
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* Much of the worst junk in this file is for the support of processors |
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* that didn't really implement the cpuid instruction properly. |
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* |
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* NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, |
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* the pass numbers. Accordingly, changes to the pass code may require changes |
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* to the accessor code. |
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*/ |
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uint_t x86_feature = 0; |
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uint_t x86_vendor = X86_VENDOR_IntelClone; |
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uint_t x86_type = X86_TYPE_OTHER; |
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uint_t pentiumpro_bug4046376; |
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uint_t pentiumpro_bug4064495; |
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uint_t enable486; |
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/* |
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* This set of strings are for processors rumored to support the cpuid |
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* instruction, and is used by locore.s to figure out how to set x86_vendor |
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*/ |
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const char CyrixInstead[] = "CyrixInstead"; |
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/* |
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* monitor/mwait info. |
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*/ |
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struct mwait_info { |
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size_t mon_min; /* min size to avoid missed wakeups */ |
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size_t mon_max; /* size to avoid false wakeups */ |
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uint32_t support; /* processor support of monitor/mwait */ |
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}; |
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/* |
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* These constants determine how many of the elements of the |
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* cpuid we cache in the cpuid_info data structure; the |
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* remaining elements are accessible via the cpuid instruction. |
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*/ |
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#define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ |
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#define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ |
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struct cpuid_info { |
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uint_t cpi_pass; /* last pass completed */ |
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/* |
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* standard function information |
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*/ |
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uint_t cpi_maxeax; /* fn 0: %eax */ |
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char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ |
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uint_t cpi_vendor; /* enum of cpi_vendorstr */ |
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uint_t cpi_family; /* fn 1: extended family */ |
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uint_t cpi_model; /* fn 1: extended model */ |
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uint_t cpi_step; /* fn 1: stepping */ |
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chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ |
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uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ |
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int cpi_clogid; /* fn 1: %ebx: thread # */ |
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uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ |
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uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ |
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uint_t cpi_ncache; /* fn 2: number of elements */ |
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struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ |
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/* |
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* extended function information |
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*/ |
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uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ |
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char cpi_brandstr[49]; /* fn 0x8000000[234] */ |
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uint8_t cpi_pabits; /* fn 0x80000006: %eax */ |
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uint8_t cpi_vabits; /* fn 0x80000006: %eax */ |
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struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ |
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id_t cpi_coreid; |
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uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ |
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/* Intel: fn 4: %eax[31-26] */ |
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/* |
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* supported feature information |
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*/ |
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uint32_t cpi_support[5]; |
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#define STD_EDX_FEATURES 0 |
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#define AMD_EDX_FEATURES 1 |
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#define TM_EDX_FEATURES 2 |
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#define STD_ECX_FEATURES 3 |
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#define AMD_ECX_FEATURES 4 |
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/* |
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* Synthesized information, where known. |
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*/ |
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uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ |
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const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ |
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uint32_t cpi_socket; /* Chip package/socket type */ |
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struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ |
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}; |
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static struct cpuid_info cpuid_info0; |
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/* |
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* These bit fields are defined by the Intel Application Note AP-485 |
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* "Intel Processor Identification and the CPUID Instruction" |
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*/ |
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#define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) |
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#define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) |
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#define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) |
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#define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) |
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#define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) |
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#define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) |
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#define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) |
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#define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) |
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#define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) |
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#define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) |
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#define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) |
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#define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) |
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#define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) |
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#define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) |
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#define CPI_MAXEAX_MAX 0x100 /* sanity control */ |
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#define CPI_XMAXEAX_MAX 0x80000100 |
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/* |
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* A couple of shorthand macros to identify "later" P6-family chips |
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* like the Pentium M and Core. First, the "older" P6-based stuff |
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* (loosely defined as "pre-Pentium-4"): |
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* P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon |
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*/ |
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|
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#define IS_LEGACY_P6(cpi) ( \ |
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cpi->cpi_family == 6 && \ |
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(cpi->cpi_model == 1 || \ |
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cpi->cpi_model == 3 || \ |
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cpi->cpi_model == 5 || \ |
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cpi->cpi_model == 6 || \ |
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cpi->cpi_model == 7 || \ |
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cpi->cpi_model == 8 || \ |
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cpi->cpi_model == 0xA || \ |
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cpi->cpi_model == 0xB) \ |
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) |
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229 |
|
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230 |
/* A "new F6" is everything with family 6 that's not the above */ |
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231 |
#define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) |
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|
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/* |
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234 |
* AMD family 0xf socket types. |
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* First index is 0 for revs B thru E, 1 for F and G. |
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* Second index by (model & 0x3) |
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*/ |
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static uint32_t amd_skts[2][4] = { |
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{ |
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240 |
X86_SOCKET_754, /* 0b00 */ |
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241 |
X86_SOCKET_940, /* 0b01 */ |
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X86_SOCKET_754, /* 0b10 */ |
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X86_SOCKET_939 /* 0b11 */ |
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}, |
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{ |
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X86_SOCKET_S1g1, /* 0b00 */ |
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X86_SOCKET_F1207, /* 0b01 */ |
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X86_SOCKET_UNKNOWN, /* 0b10 */ |
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X86_SOCKET_AM2 /* 0b11 */ |
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} |
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}; |
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|
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253 |
/* |
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* Table for mapping AMD Family 0xf model/stepping combination to |
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* chip "revision" and socket type. Only rm_family 0xf is used at the |
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* moment, but AMD family 0x10 will extend the exsiting revision names |
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* so will likely also use this table. |
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* |
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* The first member of this array that matches a given family, extended model |
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* plus model range, and stepping range will be considered a match. |
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*/ |
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262 |
static const struct amd_rev_mapent { |
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uint_t rm_family; |
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uint_t rm_modello; |
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uint_t rm_modelhi; |
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uint_t rm_steplo; |
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uint_t rm_stephi; |
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uint32_t rm_chiprev; |
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const char *rm_chiprevstr; |
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int rm_sktidx; |
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} amd_revmap[] = { |
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/* |
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* Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. |
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*/ |
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{ 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", 0 }, |
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{ 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", 0 }, |
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277 |
/* |
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* Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 |
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*/ |
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{ 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", 0 }, |
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281 |
/* |
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282 |
* Rev CG is the rest of extended model 0x0 - i.e., everything |
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* but the rev B and C0 combinations covered above. |
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284 |
*/ |
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285 |
{ 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", 0 }, |
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286 |
/* |
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* Rev D has extended model 0x1. |
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*/ |
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{ 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", 0 }, |
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290 |
/* |
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291 |
* Rev E has extended model 0x2. |
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* Extended model 0x3 is unused but available to grow into. |
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293 |
*/ |
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294 |
{ 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", 0 }, |
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295 |
/* |
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296 |
* Rev F has extended models 0x4 and 0x5. |
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297 |
*/ |
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298 |
{ 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", 1 }, |
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299 |
/* |
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300 |
* Rev G has extended model 0x6. |
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301 |
*/ |
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302 |
{ 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", 1 }, |
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303 |
}; |
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304 |
|
4481
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305 |
/* |
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306 |
* Info for monitor/mwait idle loop. |
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* |
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* See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's |
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309 |
* Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November |
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* 2006. |
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* See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual |
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* Documentation Updates" #33633, Rev 2.05, December 2006. |
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313 |
*/ |
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314 |
#define MWAIT_SUPPORT (0x00000001) /* mwait supported */ |
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315 |
#define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ |
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#define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ |
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#define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) |
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#define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) |
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#define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) |
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320 |
#define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) |
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321 |
#define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) |
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322 |
/* |
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323 |
* Number of sub-cstates for a given c-state. |
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|
324 |
*/ |
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325 |
#define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ |
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326 |
BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) |
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|
327 |
|
2869
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328 |
static void |
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329 |
synth_amd_info(struct cpuid_info *cpi) |
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330 |
{ |
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331 |
const struct amd_rev_mapent *rmp; |
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332 |
uint_t family, model, step; |
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|
333 |
int i; |
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|
334 |
|
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|
335 |
/* |
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|
336 |
* Currently only AMD family 0xf uses these fields. |
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|
337 |
*/ |
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|
338 |
if (cpi->cpi_family != 0xf) |
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339 |
return; |
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|
340 |
|
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341 |
family = cpi->cpi_family; |
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342 |
model = cpi->cpi_model; |
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343 |
step = cpi->cpi_step; |
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344 |
|
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345 |
for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp); |
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346 |
i++, rmp++) { |
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347 |
if (family == rmp->rm_family && |
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348 |
model >= rmp->rm_modello && model <= rmp->rm_modelhi && |
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349 |
step >= rmp->rm_steplo && step <= rmp->rm_stephi) { |
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350 |
cpi->cpi_chiprev = rmp->rm_chiprev; |
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351 |
cpi->cpi_chiprevstr = rmp->rm_chiprevstr; |
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352 |
cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3]; |
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353 |
return; |
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|
354 |
} |
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355 |
} |
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|
356 |
} |
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|
357 |
|
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|
358 |
static void |
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359 |
synth_info(struct cpuid_info *cpi) |
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|
360 |
{ |
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361 |
cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN; |
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362 |
cpi->cpi_chiprevstr = "Unknown"; |
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363 |
cpi->cpi_socket = X86_SOCKET_UNKNOWN; |
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gavinm
parents:
2584
diff
changeset
|
364 |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
365 |
switch (cpi->cpi_vendor) { |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
366 |
case X86_VENDOR_AMD: |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
367 |
synth_amd_info(cpi); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
368 |
break; |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
369 |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
370 |
default: |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
371 |
break; |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
372 |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
373 |
} |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
374 |
} |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
375 |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
376 |
/* |
3446 | 377 |
* Apply up various platform-dependent restrictions where the |
378 |
* underlying platform restrictions mean the CPU can be marked |
|
379 |
* as less capable than its cpuid instruction would imply. |
|
380 |
*/ |
|
381 |
||
382 |
#define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ |
|
383 |
||
384 |
/* |
|
0 | 385 |
* Some undocumented ways of patching the results of the cpuid |
386 |
* instruction to permit running Solaris 10 on future cpus that |
|
387 |
* we don't currently support. Could be set to non-zero values |
|
388 |
* via settings in eeprom. |
|
389 |
*/ |
|
390 |
||
391 |
uint32_t cpuid_feature_ecx_include; |
|
392 |
uint32_t cpuid_feature_ecx_exclude; |
|
393 |
uint32_t cpuid_feature_edx_include; |
|
394 |
uint32_t cpuid_feature_edx_exclude; |
|
395 |
||
3446 | 396 |
void |
397 |
cpuid_alloc_space(cpu_t *cpu) |
|
398 |
{ |
|
399 |
/* |
|
400 |
* By convention, cpu0 is the boot cpu, which is set up |
|
401 |
* before memory allocation is available. All other cpus get |
|
402 |
* their cpuid_info struct allocated here. |
|
403 |
*/ |
|
404 |
ASSERT(cpu->cpu_id != 0); |
|
405 |
cpu->cpu_m.mcpu_cpi = |
|
406 |
kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); |
|
407 |
} |
|
408 |
||
409 |
void |
|
410 |
cpuid_free_space(cpu_t *cpu) |
|
411 |
{ |
|
412 |
ASSERT(cpu->cpu_id != 0); |
|
413 |
kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); |
|
414 |
} |
|
415 |
||
0 | 416 |
uint_t |
417 |
cpuid_pass1(cpu_t *cpu) |
|
418 |
{ |
|
419 |
uint32_t mask_ecx, mask_edx; |
|
420 |
uint_t feature = X86_CPUID; |
|
421 |
struct cpuid_info *cpi; |
|
1228 | 422 |
struct cpuid_regs *cp; |
0 | 423 |
int xcpuid; |
424 |
||
3446 | 425 |
|
0 | 426 |
/* |
3446 | 427 |
* Space statically allocated for cpu0, ensure pointer is set |
0 | 428 |
*/ |
429 |
if (cpu->cpu_id == 0) |
|
3446 | 430 |
cpu->cpu_m.mcpu_cpi = &cpuid_info0; |
431 |
cpi = cpu->cpu_m.mcpu_cpi; |
|
432 |
ASSERT(cpi != NULL); |
|
0 | 433 |
cp = &cpi->cpi_std[0]; |
1228 | 434 |
cp->cp_eax = 0; |
435 |
cpi->cpi_maxeax = __cpuid_insn(cp); |
|
0 | 436 |
{ |
437 |
uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; |
|
438 |
*iptr++ = cp->cp_ebx; |
|
439 |
*iptr++ = cp->cp_edx; |
|
440 |
*iptr++ = cp->cp_ecx; |
|
441 |
*(char *)&cpi->cpi_vendorstr[12] = '\0'; |
|
442 |
} |
|
443 |
||
444 |
/* |
|
445 |
* Map the vendor string to a type code |
|
446 |
*/ |
|
447 |
if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) |
|
448 |
cpi->cpi_vendor = X86_VENDOR_Intel; |
|
449 |
else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) |
|
450 |
cpi->cpi_vendor = X86_VENDOR_AMD; |
|
451 |
else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) |
|
452 |
cpi->cpi_vendor = X86_VENDOR_TM; |
|
453 |
else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) |
|
454 |
/* |
|
455 |
* CyrixInstead is a variable used by the Cyrix detection code |
|
456 |
* in locore. |
|
457 |
*/ |
|
458 |
cpi->cpi_vendor = X86_VENDOR_Cyrix; |
|
459 |
else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) |
|
460 |
cpi->cpi_vendor = X86_VENDOR_UMC; |
|
461 |
else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) |
|
462 |
cpi->cpi_vendor = X86_VENDOR_NexGen; |
|
463 |
else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) |
|
464 |
cpi->cpi_vendor = X86_VENDOR_Centaur; |
|
465 |
else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) |
|
466 |
cpi->cpi_vendor = X86_VENDOR_Rise; |
|
467 |
else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) |
|
468 |
cpi->cpi_vendor = X86_VENDOR_SiS; |
|
469 |
else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) |
|
470 |
cpi->cpi_vendor = X86_VENDOR_NSC; |
|
471 |
else |
|
472 |
cpi->cpi_vendor = X86_VENDOR_IntelClone; |
|
473 |
||
474 |
x86_vendor = cpi->cpi_vendor; /* for compatibility */ |
|
475 |
||
476 |
/* |
|
477 |
* Limit the range in case of weird hardware |
|
478 |
*/ |
|
479 |
if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) |
|
480 |
cpi->cpi_maxeax = CPI_MAXEAX_MAX; |
|
481 |
if (cpi->cpi_maxeax < 1) |
|
482 |
goto pass1_done; |
|
483 |
||
484 |
cp = &cpi->cpi_std[1]; |
|
1228 | 485 |
cp->cp_eax = 1; |
486 |
(void) __cpuid_insn(cp); |
|
0 | 487 |
|
488 |
/* |
|
489 |
* Extract identifying constants for easy access. |
|
490 |
*/ |
|
491 |
cpi->cpi_model = CPI_MODEL(cpi); |
|
492 |
cpi->cpi_family = CPI_FAMILY(cpi); |
|
493 |
||
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
494 |
if (cpi->cpi_family == 0xf) |
0 | 495 |
cpi->cpi_family += CPI_FAMILY_XTD(cpi); |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
496 |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
497 |
/* |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
498 |
* Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. |
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
499 |
* Intel, and presumably everyone else, uses model == 0xf, as |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
500 |
* one would expect (max value means possible overflow). Sigh. |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
501 |
*/ |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
502 |
|
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
503 |
switch (cpi->cpi_vendor) { |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
504 |
case X86_VENDOR_AMD: |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
505 |
if (CPI_FAMILY(cpi) == 0xf) |
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
506 |
cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
507 |
break; |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
508 |
default: |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
509 |
if (cpi->cpi_model == 0xf) |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
510 |
cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
511 |
break; |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
512 |
} |
0 | 513 |
|
514 |
cpi->cpi_step = CPI_STEP(cpi); |
|
515 |
cpi->cpi_brandid = CPI_BRANDID(cpi); |
|
516 |
||
517 |
/* |
|
518 |
* *default* assumptions: |
|
519 |
* - believe %edx feature word |
|
520 |
* - ignore %ecx feature word |
|
521 |
* - 32-bit virtual and physical addressing |
|
522 |
*/ |
|
523 |
mask_edx = 0xffffffff; |
|
524 |
mask_ecx = 0; |
|
525 |
||
526 |
cpi->cpi_pabits = cpi->cpi_vabits = 32; |
|
527 |
||
528 |
switch (cpi->cpi_vendor) { |
|
529 |
case X86_VENDOR_Intel: |
|
530 |
if (cpi->cpi_family == 5) |
|
531 |
x86_type = X86_TYPE_P5; |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
532 |
else if (IS_LEGACY_P6(cpi)) { |
0 | 533 |
x86_type = X86_TYPE_P6; |
534 |
pentiumpro_bug4046376 = 1; |
|
535 |
pentiumpro_bug4064495 = 1; |
|
536 |
/* |
|
537 |
* Clear the SEP bit when it was set erroneously |
|
538 |
*/ |
|
539 |
if (cpi->cpi_model < 3 && cpi->cpi_step < 3) |
|
540 |
cp->cp_edx &= ~CPUID_INTC_EDX_SEP; |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
541 |
} else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { |
0 | 542 |
x86_type = X86_TYPE_P4; |
543 |
/* |
|
544 |
* We don't currently depend on any of the %ecx |
|
545 |
* features until Prescott, so we'll only check |
|
546 |
* this from P4 onwards. We might want to revisit |
|
547 |
* that idea later. |
|
548 |
*/ |
|
549 |
mask_ecx = 0xffffffff; |
|
550 |
} else if (cpi->cpi_family > 0xf) |
|
551 |
mask_ecx = 0xffffffff; |
|
552 |
break; |
|
553 |
case X86_VENDOR_IntelClone: |
|
554 |
default: |
|
555 |
break; |
|
556 |
case X86_VENDOR_AMD: |
|
557 |
#if defined(OPTERON_ERRATUM_108) |
|
558 |
if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { |
|
559 |
cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; |
|
560 |
cpi->cpi_model = 0xc; |
|
561 |
} else |
|
562 |
#endif |
|
563 |
if (cpi->cpi_family == 5) { |
|
564 |
/* |
|
565 |
* AMD K5 and K6 |
|
566 |
* |
|
567 |
* These CPUs have an incomplete implementation |
|
568 |
* of MCA/MCE which we mask away. |
|
569 |
*/ |
|
1228 | 570 |
mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); |
571 |
||
572 |
/* |
|
573 |
* Model 0 uses the wrong (APIC) bit |
|
574 |
* to indicate PGE. Fix it here. |
|
575 |
*/ |
|
0 | 576 |
if (cpi->cpi_model == 0) { |
577 |
if (cp->cp_edx & 0x200) { |
|
578 |
cp->cp_edx &= ~0x200; |
|
579 |
cp->cp_edx |= CPUID_INTC_EDX_PGE; |
|
580 |
} |
|
1228 | 581 |
} |
582 |
||
583 |
/* |
|
584 |
* Early models had problems w/ MMX; disable. |
|
585 |
*/ |
|
586 |
if (cpi->cpi_model < 6) |
|
587 |
mask_edx &= ~CPUID_INTC_EDX_MMX; |
|
588 |
} |
|
589 |
||
590 |
/* |
|
591 |
* For newer families, SSE3 and CX16, at least, are valid; |
|
592 |
* enable all |
|
593 |
*/ |
|
594 |
if (cpi->cpi_family >= 0xf) |
|
771
1c25a2120ec0
6327969 cpuid sse3 feature bit not noted on any AMD processor
dmick
parents:
359
diff
changeset
|
595 |
mask_ecx = 0xffffffff; |
0 | 596 |
break; |
597 |
case X86_VENDOR_TM: |
|
598 |
/* |
|
599 |
* workaround the NT workaround in CMS 4.1 |
|
600 |
*/ |
|
601 |
if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && |
|
602 |
(cpi->cpi_step == 2 || cpi->cpi_step == 3)) |
|
603 |
cp->cp_edx |= CPUID_INTC_EDX_CX8; |
|
604 |
break; |
|
605 |
case X86_VENDOR_Centaur: |
|
606 |
/* |
|
607 |
* workaround the NT workarounds again |
|
608 |
*/ |
|
609 |
if (cpi->cpi_family == 6) |
|
610 |
cp->cp_edx |= CPUID_INTC_EDX_CX8; |
|
611 |
break; |
|
612 |
case X86_VENDOR_Cyrix: |
|
613 |
/* |
|
614 |
* We rely heavily on the probing in locore |
|
615 |
* to actually figure out what parts, if any, |
|
616 |
* of the Cyrix cpuid instruction to believe. |
|
617 |
*/ |
|
618 |
switch (x86_type) { |
|
619 |
case X86_TYPE_CYRIX_486: |
|
620 |
mask_edx = 0; |
|
621 |
break; |
|
622 |
case X86_TYPE_CYRIX_6x86: |
|
623 |
mask_edx = 0; |
|
624 |
break; |
|
625 |
case X86_TYPE_CYRIX_6x86L: |
|
626 |
mask_edx = |
|
627 |
CPUID_INTC_EDX_DE | |
|
628 |
CPUID_INTC_EDX_CX8; |
|
629 |
break; |
|
630 |
case X86_TYPE_CYRIX_6x86MX: |
|
631 |
mask_edx = |
|
632 |
CPUID_INTC_EDX_DE | |
|
633 |
CPUID_INTC_EDX_MSR | |
|
634 |
CPUID_INTC_EDX_CX8 | |
|
635 |
CPUID_INTC_EDX_PGE | |
|
636 |
CPUID_INTC_EDX_CMOV | |
|
637 |
CPUID_INTC_EDX_MMX; |
|
638 |
break; |
|
639 |
case X86_TYPE_CYRIX_GXm: |
|
640 |
mask_edx = |
|
641 |
CPUID_INTC_EDX_MSR | |
|
642 |
CPUID_INTC_EDX_CX8 | |
|
643 |
CPUID_INTC_EDX_CMOV | |
|
644 |
CPUID_INTC_EDX_MMX; |
|
645 |
break; |
|
646 |
case X86_TYPE_CYRIX_MediaGX: |
|
647 |
break; |
|
648 |
case X86_TYPE_CYRIX_MII: |
|
649 |
case X86_TYPE_VIA_CYRIX_III: |
|
650 |
mask_edx = |
|
651 |
CPUID_INTC_EDX_DE | |
|
652 |
CPUID_INTC_EDX_TSC | |
|
653 |
CPUID_INTC_EDX_MSR | |
|
654 |
CPUID_INTC_EDX_CX8 | |
|
655 |
CPUID_INTC_EDX_PGE | |
|
656 |
CPUID_INTC_EDX_CMOV | |
|
657 |
CPUID_INTC_EDX_MMX; |
|
658 |
break; |
|
659 |
default: |
|
660 |
break; |
|
661 |
} |
|
662 |
break; |
|
663 |
} |
|
664 |
||
665 |
/* |
|
666 |
* Now we've figured out the masks that determine |
|
667 |
* which bits we choose to believe, apply the masks |
|
668 |
* to the feature words, then map the kernel's view |
|
669 |
* of these feature words into its feature word. |
|
670 |
*/ |
|
671 |
cp->cp_edx &= mask_edx; |
|
672 |
cp->cp_ecx &= mask_ecx; |
|
673 |
||
674 |
/* |
|
3446 | 675 |
* apply any platform restrictions (we don't call this |
676 |
* immediately after __cpuid_insn here, because we need the |
|
677 |
* workarounds applied above first) |
|
0 | 678 |
*/ |
3446 | 679 |
platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); |
0 | 680 |
|
3446 | 681 |
/* |
682 |
* fold in overrides from the "eeprom" mechanism |
|
683 |
*/ |
|
0 | 684 |
cp->cp_edx |= cpuid_feature_edx_include; |
685 |
cp->cp_edx &= ~cpuid_feature_edx_exclude; |
|
686 |
||
687 |
cp->cp_ecx |= cpuid_feature_ecx_include; |
|
688 |
cp->cp_ecx &= ~cpuid_feature_ecx_exclude; |
|
689 |
||
690 |
if (cp->cp_edx & CPUID_INTC_EDX_PSE) |
|
691 |
feature |= X86_LARGEPAGE; |
|
692 |
if (cp->cp_edx & CPUID_INTC_EDX_TSC) |
|
693 |
feature |= X86_TSC; |
|
694 |
if (cp->cp_edx & CPUID_INTC_EDX_MSR) |
|
695 |
feature |= X86_MSR; |
|
696 |
if (cp->cp_edx & CPUID_INTC_EDX_MTRR) |
|
697 |
feature |= X86_MTRR; |
|
698 |
if (cp->cp_edx & CPUID_INTC_EDX_PGE) |
|
699 |
feature |= X86_PGE; |
|
700 |
if (cp->cp_edx & CPUID_INTC_EDX_CMOV) |
|
701 |
feature |= X86_CMOV; |
|
702 |
if (cp->cp_edx & CPUID_INTC_EDX_MMX) |
|
703 |
feature |= X86_MMX; |
|
704 |
if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && |
|
705 |
(cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) |
|
706 |
feature |= X86_MCA; |
|
707 |
if (cp->cp_edx & CPUID_INTC_EDX_PAE) |
|
708 |
feature |= X86_PAE; |
|
709 |
if (cp->cp_edx & CPUID_INTC_EDX_CX8) |
|
710 |
feature |= X86_CX8; |
|
711 |
if (cp->cp_ecx & CPUID_INTC_ECX_CX16) |
|
712 |
feature |= X86_CX16; |
|
713 |
if (cp->cp_edx & CPUID_INTC_EDX_PAT) |
|
714 |
feature |= X86_PAT; |
|
715 |
if (cp->cp_edx & CPUID_INTC_EDX_SEP) |
|
716 |
feature |= X86_SEP; |
|
717 |
if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { |
|
718 |
/* |
|
719 |
* In our implementation, fxsave/fxrstor |
|
720 |
* are prerequisites before we'll even |
|
721 |
* try and do SSE things. |
|
722 |
*/ |
|
723 |
if (cp->cp_edx & CPUID_INTC_EDX_SSE) |
|
724 |
feature |= X86_SSE; |
|
725 |
if (cp->cp_edx & CPUID_INTC_EDX_SSE2) |
|
726 |
feature |= X86_SSE2; |
|
727 |
if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) |
|
728 |
feature |= X86_SSE3; |
|
729 |
} |
|
730 |
if (cp->cp_edx & CPUID_INTC_EDX_DE) |
|
3446 | 731 |
feature |= X86_DE; |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
732 |
if (cp->cp_ecx & CPUID_INTC_ECX_MON) { |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
733 |
cpi->cpi_mwait.support |= MWAIT_SUPPORT; |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
734 |
feature |= X86_MWAIT; |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
735 |
} |
0 | 736 |
|
737 |
if (feature & X86_PAE) |
|
738 |
cpi->cpi_pabits = 36; |
|
739 |
||
740 |
/* |
|
741 |
* Hyperthreading configuration is slightly tricky on Intel |
|
742 |
* and pure clones, and even trickier on AMD. |
|
743 |
* |
|
744 |
* (AMD chose to set the HTT bit on their CMP processors, |
|
745 |
* even though they're not actually hyperthreaded. Thus it |
|
746 |
* takes a bit more work to figure out what's really going |
|
3446 | 747 |
* on ... see the handling of the CMP_LGCY bit below) |
0 | 748 |
*/ |
749 |
if (cp->cp_edx & CPUID_INTC_EDX_HTT) { |
|
750 |
cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); |
|
751 |
if (cpi->cpi_ncpu_per_chip > 1) |
|
752 |
feature |= X86_HTT; |
|
1228 | 753 |
} else { |
754 |
cpi->cpi_ncpu_per_chip = 1; |
|
0 | 755 |
} |
756 |
||
757 |
/* |
|
758 |
* Work on the "extended" feature information, doing |
|
759 |
* some basic initialization for cpuid_pass2() |
|
760 |
*/ |
|
761 |
xcpuid = 0; |
|
762 |
switch (cpi->cpi_vendor) { |
|
763 |
case X86_VENDOR_Intel: |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
764 |
if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) |
0 | 765 |
xcpuid++; |
766 |
break; |
|
767 |
case X86_VENDOR_AMD: |
|
768 |
if (cpi->cpi_family > 5 || |
|
769 |
(cpi->cpi_family == 5 && cpi->cpi_model >= 1)) |
|
770 |
xcpuid++; |
|
771 |
break; |
|
772 |
case X86_VENDOR_Cyrix: |
|
773 |
/* |
|
774 |
* Only these Cyrix CPUs are -known- to support |
|
775 |
* extended cpuid operations. |
|
776 |
*/ |
|
777 |
if (x86_type == X86_TYPE_VIA_CYRIX_III || |
|
778 |
x86_type == X86_TYPE_CYRIX_GXm) |
|
779 |
xcpuid++; |
|
780 |
break; |
|
781 |
case X86_VENDOR_Centaur: |
|
782 |
case X86_VENDOR_TM: |
|
783 |
default: |
|
784 |
xcpuid++; |
|
785 |
break; |
|
786 |
} |
|
787 |
||
788 |
if (xcpuid) { |
|
789 |
cp = &cpi->cpi_extd[0]; |
|
1228 | 790 |
cp->cp_eax = 0x80000000; |
791 |
cpi->cpi_xmaxeax = __cpuid_insn(cp); |
|
0 | 792 |
} |
793 |
||
794 |
if (cpi->cpi_xmaxeax & 0x80000000) { |
|
795 |
||
796 |
if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) |
|
797 |
cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; |
|
798 |
||
799 |
switch (cpi->cpi_vendor) { |
|
800 |
case X86_VENDOR_Intel: |
|
801 |
case X86_VENDOR_AMD: |
|
802 |
if (cpi->cpi_xmaxeax < 0x80000001) |
|
803 |
break; |
|
804 |
cp = &cpi->cpi_extd[1]; |
|
1228 | 805 |
cp->cp_eax = 0x80000001; |
806 |
(void) __cpuid_insn(cp); |
|
3446 | 807 |
|
0 | 808 |
if (cpi->cpi_vendor == X86_VENDOR_AMD && |
809 |
cpi->cpi_family == 5 && |
|
810 |
cpi->cpi_model == 6 && |
|
811 |
cpi->cpi_step == 6) { |
|
812 |
/* |
|
813 |
* K6 model 6 uses bit 10 to indicate SYSC |
|
814 |
* Later models use bit 11. Fix it here. |
|
815 |
*/ |
|
816 |
if (cp->cp_edx & 0x400) { |
|
817 |
cp->cp_edx &= ~0x400; |
|
818 |
cp->cp_edx |= CPUID_AMD_EDX_SYSC; |
|
819 |
} |
|
820 |
} |
|
821 |
||
3446 | 822 |
platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); |
823 |
||
0 | 824 |
/* |
825 |
* Compute the additions to the kernel's feature word. |
|
826 |
*/ |
|
827 |
if (cp->cp_edx & CPUID_AMD_EDX_NX) |
|
828 |
feature |= X86_NX; |
|
829 |
||
830 |
/* |
|
3446 | 831 |
* If both the HTT and CMP_LGCY bits are set, |
1228 | 832 |
* then we're not actually HyperThreaded. Read |
833 |
* "AMD CPUID Specification" for more details. |
|
0 | 834 |
*/ |
835 |
if (cpi->cpi_vendor == X86_VENDOR_AMD && |
|
1228 | 836 |
(feature & X86_HTT) && |
3446 | 837 |
(cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { |
0 | 838 |
feature &= ~X86_HTT; |
1228 | 839 |
feature |= X86_CMP; |
840 |
} |
|
3446 | 841 |
#if defined(__amd64) |
0 | 842 |
/* |
843 |
* It's really tricky to support syscall/sysret in |
|
844 |
* the i386 kernel; we rely on sysenter/sysexit |
|
845 |
* instead. In the amd64 kernel, things are -way- |
|
846 |
* better. |
|
847 |
*/ |
|
848 |
if (cp->cp_edx & CPUID_AMD_EDX_SYSC) |
|
849 |
feature |= X86_ASYSC; |
|
850 |
||
851 |
/* |
|
852 |
* While we're thinking about system calls, note |
|
853 |
* that AMD processors don't support sysenter |
|
854 |
* in long mode at all, so don't try to program them. |
|
855 |
*/ |
|
856 |
if (x86_vendor == X86_VENDOR_AMD) |
|
857 |
feature &= ~X86_SEP; |
|
858 |
#endif |
|
3446 | 859 |
if (cp->cp_edx & CPUID_AMD_EDX_TSCP) |
860 |
feature |= X86_TSCP; |
|
0 | 861 |
break; |
862 |
default: |
|
863 |
break; |
|
864 |
} |
|
865 |
||
1228 | 866 |
/* |
867 |
* Get CPUID data about processor cores and hyperthreads. |
|
868 |
*/ |
|
0 | 869 |
switch (cpi->cpi_vendor) { |
870 |
case X86_VENDOR_Intel: |
|
1228 | 871 |
if (cpi->cpi_maxeax >= 4) { |
872 |
cp = &cpi->cpi_std[4]; |
|
873 |
cp->cp_eax = 4; |
|
874 |
cp->cp_ecx = 0; |
|
875 |
(void) __cpuid_insn(cp); |
|
3446 | 876 |
platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); |
1228 | 877 |
} |
878 |
/*FALLTHROUGH*/ |
|
0 | 879 |
case X86_VENDOR_AMD: |
880 |
if (cpi->cpi_xmaxeax < 0x80000008) |
|
881 |
break; |
|
882 |
cp = &cpi->cpi_extd[8]; |
|
1228 | 883 |
cp->cp_eax = 0x80000008; |
884 |
(void) __cpuid_insn(cp); |
|
3446 | 885 |
platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); |
886 |
||
0 | 887 |
/* |
888 |
* Virtual and physical address limits from |
|
889 |
* cpuid override previously guessed values. |
|
890 |
*/ |
|
891 |
cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); |
|
892 |
cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); |
|
893 |
break; |
|
894 |
default: |
|
895 |
break; |
|
896 |
} |
|
1228 | 897 |
|
898 |
switch (cpi->cpi_vendor) { |
|
899 |
case X86_VENDOR_Intel: |
|
900 |
if (cpi->cpi_maxeax < 4) { |
|
901 |
cpi->cpi_ncore_per_chip = 1; |
|
902 |
break; |
|
903 |
} else { |
|
904 |
cpi->cpi_ncore_per_chip = |
|
905 |
BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; |
|
906 |
} |
|
907 |
break; |
|
908 |
case X86_VENDOR_AMD: |
|
909 |
if (cpi->cpi_xmaxeax < 0x80000008) { |
|
910 |
cpi->cpi_ncore_per_chip = 1; |
|
911 |
break; |
|
912 |
} else { |
|
913 |
cpi->cpi_ncore_per_chip = |
|
914 |
BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; |
|
915 |
} |
|
916 |
break; |
|
917 |
default: |
|
918 |
cpi->cpi_ncore_per_chip = 1; |
|
919 |
break; |
|
920 |
} |
|
0 | 921 |
} |
922 |
||
1228 | 923 |
/* |
924 |
* If more than one core, then this processor is CMP. |
|
925 |
*/ |
|
926 |
if (cpi->cpi_ncore_per_chip > 1) |
|
927 |
feature |= X86_CMP; |
|
3446 | 928 |
|
1228 | 929 |
/* |
930 |
* If the number of cores is the same as the number |
|
931 |
* of CPUs, then we cannot have HyperThreading. |
|
932 |
*/ |
|
933 |
if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) |
|
934 |
feature &= ~X86_HTT; |
|
935 |
||
0 | 936 |
if ((feature & (X86_HTT | X86_CMP)) == 0) { |
1228 | 937 |
/* |
938 |
* Single-core single-threaded processors. |
|
939 |
*/ |
|
0 | 940 |
cpi->cpi_chipid = -1; |
941 |
cpi->cpi_clogid = 0; |
|
1228 | 942 |
cpi->cpi_coreid = cpu->cpu_id; |
0 | 943 |
} else if (cpi->cpi_ncpu_per_chip > 1) { |
1228 | 944 |
uint_t i; |
945 |
uint_t chipid_shift = 0; |
|
946 |
uint_t coreid_shift = 0; |
|
947 |
uint_t apic_id = CPI_APIC_ID(cpi); |
|
948 |
||
949 |
for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) |
|
950 |
chipid_shift++; |
|
951 |
cpi->cpi_chipid = apic_id >> chipid_shift; |
|
952 |
cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); |
|
0 | 953 |
|
1228 | 954 |
if (cpi->cpi_vendor == X86_VENDOR_Intel) { |
955 |
if (feature & X86_CMP) { |
|
956 |
/* |
|
957 |
* Multi-core (and possibly multi-threaded) |
|
958 |
* processors. |
|
959 |
*/ |
|
960 |
uint_t ncpu_per_core; |
|
961 |
if (cpi->cpi_ncore_per_chip == 1) |
|
962 |
ncpu_per_core = cpi->cpi_ncpu_per_chip; |
|
963 |
else if (cpi->cpi_ncore_per_chip > 1) |
|
964 |
ncpu_per_core = cpi->cpi_ncpu_per_chip / |
|
965 |
cpi->cpi_ncore_per_chip; |
|
966 |
/* |
|
967 |
* 8bit APIC IDs on dual core Pentiums |
|
968 |
* look like this: |
|
969 |
* |
|
970 |
* +-----------------------+------+------+ |
|
971 |
* | Physical Package ID | MC | HT | |
|
972 |
* +-----------------------+------+------+ |
|
973 |
* <------- chipid --------> |
|
974 |
* <------- coreid ---------------> |
|
975 |
* <--- clogid --> |
|
976 |
* |
|
977 |
* Where the number of bits necessary to |
|
978 |
* represent MC and HT fields together equals |
|
979 |
* to the minimum number of bits necessary to |
|
980 |
* store the value of cpi->cpi_ncpu_per_chip. |
|
981 |
* Of those bits, the MC part uses the number |
|
982 |
* of bits necessary to store the value of |
|
983 |
* cpi->cpi_ncore_per_chip. |
|
984 |
*/ |
|
985 |
for (i = 1; i < ncpu_per_core; i <<= 1) |
|
986 |
coreid_shift++; |
|
1727
592b097f02d0
6406224 CPU core detection is broken on multi-core Pentium D
andrei
parents:
1582
diff
changeset
|
987 |
cpi->cpi_coreid = apic_id >> coreid_shift; |
1228 | 988 |
} else if (feature & X86_HTT) { |
989 |
/* |
|
990 |
* Single-core multi-threaded processors. |
|
991 |
*/ |
|
992 |
cpi->cpi_coreid = cpi->cpi_chipid; |
|
993 |
} |
|
994 |
} else if (cpi->cpi_vendor == X86_VENDOR_AMD) { |
|
995 |
/* |
|
996 |
* AMD currently only has dual-core processors with |
|
997 |
* single-threaded cores. If they ever release |
|
998 |
* multi-threaded processors, then this code |
|
999 |
* will have to be updated. |
|
1000 |
*/ |
|
1001 |
cpi->cpi_coreid = cpu->cpu_id; |
|
1002 |
} else { |
|
1003 |
/* |
|
1004 |
* All other processors are currently |
|
1005 |
* assumed to have single cores. |
|
1006 |
*/ |
|
1007 |
cpi->cpi_coreid = cpi->cpi_chipid; |
|
1008 |
} |
|
0 | 1009 |
} |
1010 |
||
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1011 |
/* |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1012 |
* Synthesize chip "revision" and socket type |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1013 |
*/ |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1014 |
synth_info(cpi); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
1015 |
|
0 | 1016 |
pass1_done: |
1017 |
cpi->cpi_pass = 1; |
|
1018 |
return (feature); |
|
1019 |
} |
|
1020 |
||
1021 |
/* |
|
1022 |
* Make copies of the cpuid table entries we depend on, in |
|
1023 |
* part for ease of parsing now, in part so that we have only |
|
1024 |
* one place to correct any of it, in part for ease of |
|
1025 |
* later export to userland, and in part so we can look at |
|
1026 |
* this stuff in a crash dump. |
|
1027 |
*/ |
|
1028 |
||
1029 |
/*ARGSUSED*/ |
|
1030 |
void |
|
1031 |
cpuid_pass2(cpu_t *cpu) |
|
1032 |
{ |
|
1033 |
uint_t n, nmax; |
|
1034 |
int i; |
|
1228 | 1035 |
struct cpuid_regs *cp; |
0 | 1036 |
uint8_t *dp; |
1037 |
uint32_t *iptr; |
|
1038 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
|
1039 |
||
1040 |
ASSERT(cpi->cpi_pass == 1); |
|
1041 |
||
1042 |
if (cpi->cpi_maxeax < 1) |
|
1043 |
goto pass2_done; |
|
1044 |
||
1045 |
if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) |
|
1046 |
nmax = NMAX_CPI_STD; |
|
1047 |
/* |
|
1048 |
* (We already handled n == 0 and n == 1 in pass 1) |
|
1049 |
*/ |
|
1050 |
for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { |
|
1228 | 1051 |
cp->cp_eax = n; |
1052 |
(void) __cpuid_insn(cp); |
|
3446 | 1053 |
platform_cpuid_mangle(cpi->cpi_vendor, n, cp); |
0 | 1054 |
switch (n) { |
1055 |
case 2: |
|
1056 |
/* |
|
1057 |
* "the lower 8 bits of the %eax register |
|
1058 |
* contain a value that identifies the number |
|
1059 |
* of times the cpuid [instruction] has to be |
|
1060 |
* executed to obtain a complete image of the |
|
1061 |
* processor's caching systems." |
|
1062 |
* |
|
1063 |
* How *do* they make this stuff up? |
|
1064 |
*/ |
|
1065 |
cpi->cpi_ncache = sizeof (*cp) * |
|
1066 |
BITX(cp->cp_eax, 7, 0); |
|
1067 |
if (cpi->cpi_ncache == 0) |
|
1068 |
break; |
|
1069 |
cpi->cpi_ncache--; /* skip count byte */ |
|
1070 |
||
1071 |
/* |
|
1072 |
* Well, for now, rather than attempt to implement |
|
1073 |
* this slightly dubious algorithm, we just look |
|
1074 |
* at the first 15 .. |
|
1075 |
*/ |
|
1076 |
if (cpi->cpi_ncache > (sizeof (*cp) - 1)) |
|
1077 |
cpi->cpi_ncache = sizeof (*cp) - 1; |
|
1078 |
||
1079 |
dp = cpi->cpi_cacheinfo; |
|
1080 |
if (BITX(cp->cp_eax, 31, 31) == 0) { |
|
1081 |
uint8_t *p = (void *)&cp->cp_eax; |
|
1082 |
for (i = 1; i < 3; i++) |
|
1083 |
if (p[i] != 0) |
|
1084 |
*dp++ = p[i]; |
|
1085 |
} |
|
1086 |
if (BITX(cp->cp_ebx, 31, 31) == 0) { |
|
1087 |
uint8_t *p = (void *)&cp->cp_ebx; |
|
1088 |
for (i = 0; i < 4; i++) |
|
1089 |
if (p[i] != 0) |
|
1090 |
*dp++ = p[i]; |
|
1091 |
} |
|
1092 |
if (BITX(cp->cp_ecx, 31, 31) == 0) { |
|
1093 |
uint8_t *p = (void *)&cp->cp_ecx; |
|
1094 |
for (i = 0; i < 4; i++) |
|
1095 |
if (p[i] != 0) |
|
1096 |
*dp++ = p[i]; |
|
1097 |
} |
|
1098 |
if (BITX(cp->cp_edx, 31, 31) == 0) { |
|
1099 |
uint8_t *p = (void *)&cp->cp_edx; |
|
1100 |
for (i = 0; i < 4; i++) |
|
1101 |
if (p[i] != 0) |
|
1102 |
*dp++ = p[i]; |
|
1103 |
} |
|
1104 |
break; |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1105 |
|
0 | 1106 |
case 3: /* Processor serial number, if PSN supported */ |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1107 |
break; |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1108 |
|
0 | 1109 |
case 4: /* Deterministic cache parameters */ |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1110 |
break; |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1111 |
|
0 | 1112 |
case 5: /* Monitor/Mwait parameters */ |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1113 |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1114 |
/* |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1115 |
* check cpi_mwait.support which was set in cpuid_pass1 |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1116 |
*/ |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1117 |
if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1118 |
break; |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1119 |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1120 |
cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1121 |
cpi->cpi_mwait.mon_max = (size_t)MWAIT_SIZE_MAX(cpi); |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1122 |
if (MWAIT_EXTENSION(cpi)) { |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1123 |
cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1124 |
if (MWAIT_INT_ENABLE(cpi)) |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1125 |
cpi->cpi_mwait.support |= |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1126 |
MWAIT_ECX_INT_ENABLE; |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1127 |
} |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1128 |
break; |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
1129 |
|
0 | 1130 |
default: |
1131 |
break; |
|
1132 |
} |
|
1133 |
} |
|
1134 |
||
1135 |
if ((cpi->cpi_xmaxeax & 0x80000000) == 0) |
|
1136 |
goto pass2_done; |
|
1137 |
||
1138 |
if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) |
|
1139 |
nmax = NMAX_CPI_EXTD; |
|
1140 |
/* |
|
1141 |
* Copy the extended properties, fixing them as we go. |
|
1142 |
* (We already handled n == 0 and n == 1 in pass 1) |
|
1143 |
*/ |
|
1144 |
iptr = (void *)cpi->cpi_brandstr; |
|
1145 |
for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { |
|
1228 | 1146 |
cp->cp_eax = 0x80000000 + n; |
1147 |
(void) __cpuid_insn(cp); |
|
3446 | 1148 |
platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); |
0 | 1149 |
switch (n) { |
1150 |
case 2: |
|
1151 |
case 3: |
|
1152 |
case 4: |
|
1153 |
/* |
|
1154 |
* Extract the brand string |
|
1155 |
*/ |
|
1156 |
*iptr++ = cp->cp_eax; |
|
1157 |
*iptr++ = cp->cp_ebx; |
|
1158 |
*iptr++ = cp->cp_ecx; |
|
1159 |
*iptr++ = cp->cp_edx; |
|
1160 |
break; |
|
1161 |
case 5: |
|
1162 |
switch (cpi->cpi_vendor) { |
|
1163 |
case X86_VENDOR_AMD: |
|
1164 |
/* |
|
1165 |
* The Athlon and Duron were the first |
|
1166 |
* parts to report the sizes of the |
|
1167 |
* TLB for large pages. Before then, |
|
1168 |
* we don't trust the data. |
|
1169 |
*/ |
|
1170 |
if (cpi->cpi_family < 6 || |
|
1171 |
(cpi->cpi_family == 6 && |
|
1172 |
cpi->cpi_model < 1)) |
|
1173 |
cp->cp_eax = 0; |
|
1174 |
break; |
|
1175 |
default: |
|
1176 |
break; |
|
1177 |
} |
|
1178 |
break; |
|
1179 |
case 6: |
|
1180 |
switch (cpi->cpi_vendor) { |
|
1181 |
case X86_VENDOR_AMD: |
|
1182 |
/* |
|
1183 |
* The Athlon and Duron were the first |
|
1184 |
* AMD parts with L2 TLB's. |
|
1185 |
* Before then, don't trust the data. |
|
1186 |
*/ |
|
1187 |
if (cpi->cpi_family < 6 || |
|
1188 |
cpi->cpi_family == 6 && |
|
1189 |
cpi->cpi_model < 1) |
|
1190 |
cp->cp_eax = cp->cp_ebx = 0; |
|
1191 |
/* |
|
1192 |
* AMD Duron rev A0 reports L2 |
|
1193 |
* cache size incorrectly as 1K |
|
1194 |
* when it is really 64K |
|
1195 |
*/ |
|
1196 |
if (cpi->cpi_family == 6 && |
|
1197 |
cpi->cpi_model == 3 && |
|
1198 |
cpi->cpi_step == 0) { |
|
1199 |
cp->cp_ecx &= 0xffff; |
|
1200 |
cp->cp_ecx |= 0x400000; |
|
1201 |
} |
|
1202 |
break; |
|
1203 |
case X86_VENDOR_Cyrix: /* VIA C3 */ |
|
1204 |
/* |
|
1205 |
* VIA C3 processors are a bit messed |
|
1206 |
* up w.r.t. encoding cache sizes in %ecx |
|
1207 |
*/ |
|
1208 |
if (cpi->cpi_family != 6) |
|
1209 |
break; |
|
1210 |
/* |
|
1211 |
* model 7 and 8 were incorrectly encoded |
|
1212 |
* |
|
1213 |
* xxx is model 8 really broken? |
|
1214 |
*/ |
|
1215 |
if (cpi->cpi_model == 7 || |
|
1216 |
cpi->cpi_model == 8) |
|
1217 |
cp->cp_ecx = |
|
1218 |
BITX(cp->cp_ecx, 31, 24) << 16 | |
|
1219 |
BITX(cp->cp_ecx, 23, 16) << 12 | |
|
1220 |
BITX(cp->cp_ecx, 15, 8) << 8 | |
|
1221 |
BITX(cp->cp_ecx, 7, 0); |
|
1222 |
/* |
|
1223 |
* model 9 stepping 1 has wrong associativity |
|
1224 |
*/ |
|
1225 |
if (cpi->cpi_model == 9 && cpi->cpi_step == 1) |
|
1226 |
cp->cp_ecx |= 8 << 12; |
|
1227 |
break; |
|
1228 |
case X86_VENDOR_Intel: |
|
1229 |
/* |
|
1230 |
* Extended L2 Cache features function. |
|
1231 |
* First appeared on Prescott. |
|
1232 |
*/ |
|
1233 |
default: |
|
1234 |
break; |
|
1235 |
} |
|
1236 |
break; |
|
1237 |
default: |
|
1238 |
break; |
|
1239 |
} |
|
1240 |
} |
|
1241 |
||
1242 |
pass2_done: |
|
1243 |
cpi->cpi_pass = 2; |
|
1244 |
} |
|
1245 |
||
1246 |
static const char * |
|
1247 |
intel_cpubrand(const struct cpuid_info *cpi) |
|
1248 |
{ |
|
1249 |
int i; |
|
1250 |
||
1251 |
if ((x86_feature & X86_CPUID) == 0 || |
|
1252 |
cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) |
|
1253 |
return ("i486"); |
|
1254 |
||
1255 |
switch (cpi->cpi_family) { |
|
1256 |
case 5: |
|
1257 |
return ("Intel Pentium(r)"); |
|
1258 |
case 6: |
|
1259 |
switch (cpi->cpi_model) { |
|
1260 |
uint_t celeron, xeon; |
|
1228 | 1261 |
const struct cpuid_regs *cp; |
0 | 1262 |
case 0: |
1263 |
case 1: |
|
1264 |
case 2: |
|
1265 |
return ("Intel Pentium(r) Pro"); |
|
1266 |
case 3: |
|
1267 |
case 4: |
|
1268 |
return ("Intel Pentium(r) II"); |
|
1269 |
case 6: |
|
1270 |
return ("Intel Celeron(r)"); |
|
1271 |
case 5: |
|
1272 |
case 7: |
|
1273 |
celeron = xeon = 0; |
|
1274 |
cp = &cpi->cpi_std[2]; /* cache info */ |
|
1275 |
||
1276 |
for (i = 1; i < 3; i++) { |
|
1277 |
uint_t tmp; |
|
1278 |
||
1279 |
tmp = (cp->cp_eax >> (8 * i)) & 0xff; |
|
1280 |
if (tmp == 0x40) |
|
1281 |
celeron++; |
|
1282 |
if (tmp >= 0x44 && tmp <= 0x45) |
|
1283 |
xeon++; |
|
1284 |
} |
|
1285 |
||
1286 |
for (i = 0; i < 2; i++) { |
|
1287 |
uint_t tmp; |
|
1288 |
||
1289 |
tmp = (cp->cp_ebx >> (8 * i)) & 0xff; |
|
1290 |
if (tmp == 0x40) |
|
1291 |
celeron++; |
|
1292 |
else if (tmp >= 0x44 && tmp <= 0x45) |
|
1293 |
xeon++; |
|
1294 |
} |
|
1295 |
||
1296 |
for (i = 0; i < 4; i++) { |
|
1297 |
uint_t tmp; |
|
1298 |
||
1299 |
tmp = (cp->cp_ecx >> (8 * i)) & 0xff; |
|
1300 |
if (tmp == 0x40) |
|
1301 |
celeron++; |
|
1302 |
else if (tmp >= 0x44 && tmp <= 0x45) |
|
1303 |
xeon++; |
|
1304 |
} |
|
1305 |
||
1306 |
for (i = 0; i < 4; i++) { |
|
1307 |
uint_t tmp; |
|
1308 |
||
1309 |
tmp = (cp->cp_edx >> (8 * i)) & 0xff; |
|
1310 |
if (tmp == 0x40) |
|
1311 |
celeron++; |
|
1312 |
else if (tmp >= 0x44 && tmp <= 0x45) |
|
1313 |
xeon++; |
|
1314 |
} |
|
1315 |
||
1316 |
if (celeron) |
|
1317 |
return ("Intel Celeron(r)"); |
|
1318 |
if (xeon) |
|
1319 |
return (cpi->cpi_model == 5 ? |
|
1320 |
"Intel Pentium(r) II Xeon(tm)" : |
|
1321 |
"Intel Pentium(r) III Xeon(tm)"); |
|
1322 |
return (cpi->cpi_model == 5 ? |
|
1323 |
"Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : |
|
1324 |
"Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); |
|
1325 |
default: |
|
1326 |
break; |
|
1327 |
} |
|
1328 |
default: |
|
1329 |
break; |
|
1330 |
} |
|
1331 |
||
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1332 |
/* BrandID is present if the field is nonzero */ |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1333 |
if (cpi->cpi_brandid != 0) { |
0 | 1334 |
static const struct { |
1335 |
uint_t bt_bid; |
|
1336 |
const char *bt_str; |
|
1337 |
} brand_tbl[] = { |
|
1338 |
{ 0x1, "Intel(r) Celeron(r)" }, |
|
1339 |
{ 0x2, "Intel(r) Pentium(r) III" }, |
|
1340 |
{ 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, |
|
1341 |
{ 0x4, "Intel(r) Pentium(r) III" }, |
|
1342 |
{ 0x6, "Mobile Intel(r) Pentium(r) III" }, |
|
1343 |
{ 0x7, "Mobile Intel(r) Celeron(r)" }, |
|
1344 |
{ 0x8, "Intel(r) Pentium(r) 4" }, |
|
1345 |
{ 0x9, "Intel(r) Pentium(r) 4" }, |
|
1346 |
{ 0xa, "Intel(r) Celeron(r)" }, |
|
1347 |
{ 0xb, "Intel(r) Xeon(tm)" }, |
|
1348 |
{ 0xc, "Intel(r) Xeon(tm) MP" }, |
|
1349 |
{ 0xe, "Mobile Intel(r) Pentium(r) 4" }, |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1350 |
{ 0xf, "Mobile Intel(r) Celeron(r)" }, |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1351 |
{ 0x11, "Mobile Genuine Intel(r)" }, |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1352 |
{ 0x12, "Intel(r) Celeron(r) M" }, |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1353 |
{ 0x13, "Mobile Intel(r) Celeron(r)" }, |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1354 |
{ 0x14, "Intel(r) Celeron(r)" }, |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1355 |
{ 0x15, "Mobile Genuine Intel(r)" }, |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1356 |
{ 0x16, "Intel(r) Pentium(r) M" }, |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
1357 |
{ 0x17, "Mobile Intel(r) Celeron(r)" } |
0 | 1358 |
}; |
1359 |
uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); |
|
1360 |
uint_t sgn; |
|
1361 |
||
1362 |
sgn = (cpi->cpi_family << 8) | |
|
1363 |
(cpi->cpi_model << 4) | cpi->cpi_step; |
|
1364 |
||
1365 |
for (i = 0; i < btblmax; i++) |
|
1366 |
if (brand_tbl[i].bt_bid == cpi->cpi_brandid) |
|
1367 |
break; |
|
1368 |
if (i < btblmax) { |
|
1369 |
if (sgn == 0x6b1 && cpi->cpi_brandid == 3) |
|
1370 |
return ("Intel(r) Celeron(r)"); |
|
1371 |
if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) |
|
1372 |
return ("Intel(r) Xeon(tm) MP"); |
|
1373 |
if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) |
|
1374 |
return ("Intel(r) Xeon(tm)"); |
|
1375 |
return (brand_tbl[i].bt_str); |
|
1376 |
} |
|
1377 |
} |
|
1378 |
||
1379 |
return (NULL); |
|
1380 |
} |
|
1381 |
||
1382 |
static const char * |
|
1383 |
amd_cpubrand(const struct cpuid_info *cpi) |
|
1384 |
{ |
|
1385 |
if ((x86_feature & X86_CPUID) == 0 || |
|
1386 |
cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) |
|
1387 |
return ("i486 compatible"); |
|
1388 |
||
1389 |
switch (cpi->cpi_family) { |
|
1390 |
case 5: |
|
1391 |
switch (cpi->cpi_model) { |
|
1392 |
case 0: |
|
1393 |
case 1: |
|
1394 |
case 2: |
|
1395 |
case 3: |
|
1396 |
case 4: |
|
1397 |
case 5: |
|
1398 |
return ("AMD-K5(r)"); |
|
1399 |
case 6: |
|
1400 |
case 7: |
|
1401 |
return ("AMD-K6(r)"); |
|
1402 |
case 8: |
|
1403 |
return ("AMD-K6(r)-2"); |
|
1404 |
case 9: |
|
1405 |
return ("AMD-K6(r)-III"); |
|
1406 |
default: |
|
1407 |
return ("AMD (family 5)"); |
|
1408 |
} |
|
1409 |
case 6: |
|
1410 |
switch (cpi->cpi_model) { |
|
1411 |
case 1: |
|
1412 |
return ("AMD-K7(tm)"); |
|
1413 |
case 0: |
|
1414 |
case 2: |
|
1415 |
case 4: |
|
1416 |
return ("AMD Athlon(tm)"); |
|
1417 |
case 3: |
|
1418 |
case 7: |
|
1419 |
return ("AMD Duron(tm)"); |
|
1420 |
case 6: |
|
1421 |
case 8: |
|
1422 |
case 10: |
|
1423 |
/* |
|
1424 |
* Use the L2 cache size to distinguish |
|
1425 |
*/ |
|
1426 |
return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? |
|
1427 |
"AMD Athlon(tm)" : "AMD Duron(tm)"); |
|
1428 |
default: |
|
1429 |
return ("AMD (family 6)"); |
|
1430 |
} |
|
1431 |
default: |
|
1432 |
break; |
|
1433 |
} |
|
1434 |
||
1435 |
if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && |
|
1436 |
cpi->cpi_brandid != 0) { |
|
1437 |
switch (BITX(cpi->cpi_brandid, 7, 5)) { |
|
1438 |
case 3: |
|
1439 |
return ("AMD Opteron(tm) UP 1xx"); |
|
1440 |
case 4: |
|
1441 |
return ("AMD Opteron(tm) DP 2xx"); |
|
1442 |
case 5: |
|
1443 |
return ("AMD Opteron(tm) MP 8xx"); |
|
1444 |
default: |
|
1445 |
return ("AMD Opteron(tm)"); |
|
1446 |
} |
|
1447 |
} |
|
1448 |
||
1449 |
return (NULL); |
|
1450 |
} |
|
1451 |
||
1452 |
static const char * |
|
1453 |
cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) |
|
1454 |
{ |
|
1455 |
if ((x86_feature & X86_CPUID) == 0 || |
|
1456 |
cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || |
|
1457 |
type == X86_TYPE_CYRIX_486) |
|
1458 |
return ("i486 compatible"); |
|
1459 |
||
1460 |
switch (type) { |
|
1461 |
case X86_TYPE_CYRIX_6x86: |
|
1462 |
return ("Cyrix 6x86"); |
|
1463 |
case X86_TYPE_CYRIX_6x86L: |
|
1464 |
return ("Cyrix 6x86L"); |
|
1465 |
case X86_TYPE_CYRIX_6x86MX: |
|
1466 |
return ("Cyrix 6x86MX"); |
|
1467 |
case X86_TYPE_CYRIX_GXm: |
|
1468 |
return ("Cyrix GXm"); |
|
1469 |
case X86_TYPE_CYRIX_MediaGX: |
|
1470 |
return ("Cyrix MediaGX"); |
|
1471 |
case X86_TYPE_CYRIX_MII: |
|
1472 |
return ("Cyrix M2"); |
|
1473 |
case X86_TYPE_VIA_CYRIX_III: |
|
1474 |
return ("VIA Cyrix M3"); |
|
1475 |
default: |
|
1476 |
/* |
|
1477 |
* Have another wild guess .. |
|
1478 |
*/ |
|
1479 |
if (cpi->cpi_family == 4 && cpi->cpi_model == 9) |
|
1480 |
return ("Cyrix 5x86"); |
|
1481 |
else if (cpi->cpi_family == 5) { |
|
1482 |
switch (cpi->cpi_model) { |
|
1483 |
case 2: |
|
1484 |
return ("Cyrix 6x86"); /* Cyrix M1 */ |
|
1485 |
case 4: |
|
1486 |
return ("Cyrix MediaGX"); |
|
1487 |
default: |
|
1488 |
break; |
|
1489 |
} |
|
1490 |
} else if (cpi->cpi_family == 6) { |
|
1491 |
switch (cpi->cpi_model) { |
|
1492 |
case 0: |
|
1493 |
return ("Cyrix 6x86MX"); /* Cyrix M2? */ |
|
1494 |
case 5: |
|
1495 |
case 6: |
|
1496 |
case 7: |
|
1497 |
case 8: |
|
1498 |
case 9: |
|
1499 |
return ("VIA C3"); |
|
1500 |
default: |
|
1501 |
break; |
|
1502 |
} |
|
1503 |
} |
|
1504 |
break; |
|
1505 |
} |
|
1506 |
return (NULL); |
|
1507 |
} |
|
1508 |
||
1509 |
/* |
|
1510 |
* This only gets called in the case that the CPU extended |
|
1511 |
* feature brand string (0x80000002, 0x80000003, 0x80000004) |
|
1512 |
* aren't available, or contain null bytes for some reason. |
|
1513 |
*/ |
|
1514 |
static void |
|
1515 |
fabricate_brandstr(struct cpuid_info *cpi) |
|
1516 |
{ |
|
1517 |
const char *brand = NULL; |
|
1518 |
||
1519 |
switch (cpi->cpi_vendor) { |
|
1520 |
case X86_VENDOR_Intel: |
|
1521 |
brand = intel_cpubrand(cpi); |
|
1522 |
break; |
|
1523 |
case X86_VENDOR_AMD: |
|
1524 |
brand = amd_cpubrand(cpi); |
|
1525 |
break; |
|
1526 |
case X86_VENDOR_Cyrix: |
|
1527 |
brand = cyrix_cpubrand(cpi, x86_type); |
|
1528 |
break; |
|
1529 |
case X86_VENDOR_NexGen: |
|
1530 |
if (cpi->cpi_family == 5 && cpi->cpi_model == 0) |
|
1531 |
brand = "NexGen Nx586"; |
|
1532 |
break; |
|
1533 |
case X86_VENDOR_Centaur: |
|
1534 |
if (cpi->cpi_family == 5) |
|
1535 |
switch (cpi->cpi_model) { |
|
1536 |
case 4: |
|
1537 |
brand = "Centaur C6"; |
|
1538 |
break; |
|
1539 |
case 8: |
|
1540 |
brand = "Centaur C2"; |
|
1541 |
break; |
|
1542 |
case 9: |
|
1543 |
brand = "Centaur C3"; |
|
1544 |
break; |
|
1545 |
default: |
|
1546 |
break; |
|
1547 |
} |
|
1548 |
break; |
|
1549 |
case X86_VENDOR_Rise: |
|
1550 |
if (cpi->cpi_family == 5 && |
|
1551 |
(cpi->cpi_model == 0 || cpi->cpi_model == 2)) |
|
1552 |
brand = "Rise mP6"; |
|
1553 |
break; |
|
1554 |
case X86_VENDOR_SiS: |
|
1555 |
if (cpi->cpi_family == 5 && cpi->cpi_model == 0) |
|
1556 |
brand = "SiS 55x"; |
|
1557 |
break; |
|
1558 |
case X86_VENDOR_TM: |
|
1559 |
if (cpi->cpi_family == 5 && cpi->cpi_model == 4) |
|
1560 |
brand = "Transmeta Crusoe TM3x00 or TM5x00"; |
|
1561 |
break; |
|
1562 |
case X86_VENDOR_NSC: |
|
1563 |
case X86_VENDOR_UMC: |
|
1564 |
default: |
|
1565 |
break; |
|
1566 |
} |
|
1567 |
if (brand) { |
|
1568 |
(void) strcpy((char *)cpi->cpi_brandstr, brand); |
|
1569 |
return; |
|
1570 |
} |
|
1571 |
||
1572 |
/* |
|
1573 |
* If all else fails ... |
|
1574 |
*/ |
|
1575 |
(void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), |
|
1576 |
"%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, |
|
1577 |
cpi->cpi_model, cpi->cpi_step); |
|
1578 |
} |
|
1579 |
||
1580 |
/* |
|
1581 |
* This routine is called just after kernel memory allocation |
|
1582 |
* becomes available on cpu0, and as part of mp_startup() on |
|
1583 |
* the other cpus. |
|
1584 |
* |
|
1585 |
* Fixup the brand string. |
|
1586 |
*/ |
|
1587 |
/*ARGSUSED*/ |
|
1588 |
void |
|
1589 |
cpuid_pass3(cpu_t *cpu) |
|
1590 |
{ |
|
1591 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
|
1592 |
||
1593 |
ASSERT(cpi->cpi_pass == 2); |
|
1594 |
||
1595 |
if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { |
|
1596 |
fabricate_brandstr(cpi); |
|
1597 |
goto pass3_done; |
|
1598 |
} |
|
1599 |
||
1600 |
/* |
|
1601 |
* If we successfully extracted a brand string from the cpuid |
|
1602 |
* instruction, clean it up by removing leading spaces and |
|
1603 |
* similar junk. |
|
1604 |
*/ |
|
1605 |
if (cpi->cpi_brandstr[0]) { |
|
1606 |
size_t maxlen = sizeof (cpi->cpi_brandstr); |
|
1607 |
char *src, *dst; |
|
1608 |
||
1609 |
dst = src = (char *)cpi->cpi_brandstr; |
|
1610 |
src[maxlen - 1] = '\0'; |
|
1611 |
/* |
|
1612 |
* strip leading spaces |
|
1613 |
*/ |
|
1614 |
while (*src == ' ') |
|
1615 |
src++; |
|
1616 |
/* |
|
1617 |
* Remove any 'Genuine' or "Authentic" prefixes |
|
1618 |
*/ |
|
1619 |
if (strncmp(src, "Genuine ", 8) == 0) |
|
1620 |
src += 8; |
|
1621 |
if (strncmp(src, "Authentic ", 10) == 0) |
|
1622 |
src += 10; |
|
1623 |
||
1624 |
/* |
|
1625 |
* Now do an in-place copy. |
|
1626 |
* Map (R) to (r) and (TM) to (tm). |
|
1627 |
* The era of teletypes is long gone, and there's |
|
1628 |
* -really- no need to shout. |
|
1629 |
*/ |
|
1630 |
while (*src != '\0') { |
|
1631 |
if (src[0] == '(') { |
|
1632 |
if (strncmp(src + 1, "R)", 2) == 0) { |
|
1633 |
(void) strncpy(dst, "(r)", 3); |
|
1634 |
src += 3; |
|
1635 |
dst += 3; |
|
1636 |
continue; |
|
1637 |
} |
|
1638 |
if (strncmp(src + 1, "TM)", 3) == 0) { |
|
1639 |
(void) strncpy(dst, "(tm)", 4); |
|
1640 |
src += 4; |
|
1641 |
dst += 4; |
|
1642 |
continue; |
|
1643 |
} |
|
1644 |
} |
|
1645 |
*dst++ = *src++; |
|
1646 |
} |
|
1647 |
*dst = '\0'; |
|
1648 |
||
1649 |
/* |
|
1650 |
* Finally, remove any trailing spaces |
|
1651 |
*/ |
|
1652 |
while (--dst > cpi->cpi_brandstr) |
|
1653 |
if (*dst == ' ') |
|
1654 |
*dst = '\0'; |
|
1655 |
else |
|
1656 |
break; |
|
1657 |
} else |
|
1658 |
fabricate_brandstr(cpi); |
|
1659 |
||
1660 |
pass3_done: |
|
1661 |
cpi->cpi_pass = 3; |
|
1662 |
} |
|
1663 |
||
1664 |
/* |
|
1665 |
* This routine is called out of bind_hwcap() much later in the life |
|
1666 |
* of the kernel (post_startup()). The job of this routine is to resolve |
|
1667 |
* the hardware feature support and kernel support for those features into |
|
1668 |
* what we're actually going to tell applications via the aux vector. |
|
1669 |
*/ |
|
1670 |
uint_t |
|
1671 |
cpuid_pass4(cpu_t *cpu) |
|
1672 |
{ |
|
1673 |
struct cpuid_info *cpi; |
|
1674 |
uint_t hwcap_flags = 0; |
|
1675 |
||
1676 |
if (cpu == NULL) |
|
1677 |
cpu = CPU; |
|
1678 |
cpi = cpu->cpu_m.mcpu_cpi; |
|
1679 |
||
1680 |
ASSERT(cpi->cpi_pass == 3); |
|
1681 |
||
1682 |
if (cpi->cpi_maxeax >= 1) { |
|
1683 |
uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; |
|
1684 |
uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; |
|
1685 |
||
1686 |
*edx = CPI_FEATURES_EDX(cpi); |
|
1687 |
*ecx = CPI_FEATURES_ECX(cpi); |
|
1688 |
||
1689 |
/* |
|
1690 |
* [these require explicit kernel support] |
|
1691 |
*/ |
|
1692 |
if ((x86_feature & X86_SEP) == 0) |
|
1693 |
*edx &= ~CPUID_INTC_EDX_SEP; |
|
1694 |
||
1695 |
if ((x86_feature & X86_SSE) == 0) |
|
1696 |
*edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); |
|
1697 |
if ((x86_feature & X86_SSE2) == 0) |
|
1698 |
*edx &= ~CPUID_INTC_EDX_SSE2; |
|
1699 |
||
1700 |
if ((x86_feature & X86_HTT) == 0) |
|
1701 |
*edx &= ~CPUID_INTC_EDX_HTT; |
|
1702 |
||
1703 |
if ((x86_feature & X86_SSE3) == 0) |
|
1704 |
*ecx &= ~CPUID_INTC_ECX_SSE3; |
|
1705 |
||
1706 |
/* |
|
1707 |
* [no explicit support required beyond x87 fp context] |
|
1708 |
*/ |
|
1709 |
if (!fpu_exists) |
|
1710 |
*edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); |
|
1711 |
||
1712 |
/* |
|
1713 |
* Now map the supported feature vector to things that we |
|
1714 |
* think userland will care about. |
|
1715 |
*/ |
|
1716 |
if (*edx & CPUID_INTC_EDX_SEP) |
|
1717 |
hwcap_flags |= AV_386_SEP; |
|
1718 |
if (*edx & CPUID_INTC_EDX_SSE) |
|
1719 |
hwcap_flags |= AV_386_FXSR | AV_386_SSE; |
|
1720 |
if (*edx & CPUID_INTC_EDX_SSE2) |
|
1721 |
hwcap_flags |= AV_386_SSE2; |
|
1722 |
if (*ecx & CPUID_INTC_ECX_SSE3) |
|
1723 |
hwcap_flags |= AV_386_SSE3; |
|
1724 |
||
1725 |
if (*edx & CPUID_INTC_EDX_FPU) |
|
1726 |
hwcap_flags |= AV_386_FPU; |
|
1727 |
if (*edx & CPUID_INTC_EDX_MMX) |
|
1728 |
hwcap_flags |= AV_386_MMX; |
|
1729 |
||
1730 |
if (*edx & CPUID_INTC_EDX_TSC) |
|
1731 |
hwcap_flags |= AV_386_TSC; |
|
1732 |
if (*edx & CPUID_INTC_EDX_CX8) |
|
1733 |
hwcap_flags |= AV_386_CX8; |
|
1734 |
if (*edx & CPUID_INTC_EDX_CMOV) |
|
1735 |
hwcap_flags |= AV_386_CMOV; |
|
1736 |
if (*ecx & CPUID_INTC_ECX_MON) |
|
1737 |
hwcap_flags |= AV_386_MON; |
|
1738 |
if (*ecx & CPUID_INTC_ECX_CX16) |
|
1739 |
hwcap_flags |= AV_386_CX16; |
|
1740 |
} |
|
1741 |
||
1228 | 1742 |
if (x86_feature & X86_HTT) |
0 | 1743 |
hwcap_flags |= AV_386_PAUSE; |
1744 |
||
1745 |
if (cpi->cpi_xmaxeax < 0x80000001) |
|
1746 |
goto pass4_done; |
|
1747 |
||
1748 |
switch (cpi->cpi_vendor) { |
|
1228 | 1749 |
struct cpuid_regs cp; |
3446 | 1750 |
uint32_t *edx, *ecx; |
0 | 1751 |
|
3446 | 1752 |
case X86_VENDOR_Intel: |
1753 |
/* |
|
1754 |
* Seems like Intel duplicated what we necessary |
|
1755 |
* here to make the initial crop of 64-bit OS's work. |
|
1756 |
* Hopefully, those are the only "extended" bits |
|
1757 |
* they'll add. |
|
1758 |
*/ |
|
1759 |
/*FALLTHROUGH*/ |
|
1760 |
||
0 | 1761 |
case X86_VENDOR_AMD: |
1762 |
edx = &cpi->cpi_support[AMD_EDX_FEATURES]; |
|
3446 | 1763 |
ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; |
0 | 1764 |
|
1765 |
*edx = CPI_FEATURES_XTD_EDX(cpi); |
|
3446 | 1766 |
*ecx = CPI_FEATURES_XTD_ECX(cpi); |
1767 |
||
1768 |
/* |
|
1769 |
* [these features require explicit kernel support] |
|
1770 |
*/ |
|
1771 |
switch (cpi->cpi_vendor) { |
|
1772 |
case X86_VENDOR_Intel: |
|
1773 |
break; |
|
1774 |
||
1775 |
case X86_VENDOR_AMD: |
|
1776 |
if ((x86_feature & X86_TSCP) == 0) |
|
1777 |
*edx &= ~CPUID_AMD_EDX_TSCP; |
|
1778 |
break; |
|
1779 |
||
1780 |
default: |
|
1781 |
break; |
|
1782 |
} |
|
0 | 1783 |
|
1784 |
/* |
|
1785 |
* [no explicit support required beyond |
|
1786 |
* x87 fp context and exception handlers] |
|
1787 |
*/ |
|
1788 |
if (!fpu_exists) |
|
1789 |
*edx &= ~(CPUID_AMD_EDX_MMXamd | |
|
1790 |
CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); |
|
1791 |
||
1792 |
if ((x86_feature & X86_NX) == 0) |
|
1793 |
*edx &= ~CPUID_AMD_EDX_NX; |
|
3446 | 1794 |
#if !defined(__amd64) |
0 | 1795 |
*edx &= ~CPUID_AMD_EDX_LM; |
1796 |
#endif |
|
1797 |
/* |
|
1798 |
* Now map the supported feature vector to |
|
1799 |
* things that we think userland will care about. |
|
1800 |
*/ |
|
3446 | 1801 |
#if defined(__amd64) |
0 | 1802 |
if (*edx & CPUID_AMD_EDX_SYSC) |
1803 |
hwcap_flags |= AV_386_AMD_SYSC; |
|
3446 | 1804 |
#endif |
0 | 1805 |
if (*edx & CPUID_AMD_EDX_MMXamd) |
1806 |
hwcap_flags |= AV_386_AMD_MMX; |
|
1807 |
if (*edx & CPUID_AMD_EDX_3DNow) |
|
1808 |
hwcap_flags |= AV_386_AMD_3DNow; |
|
1809 |
if (*edx & CPUID_AMD_EDX_3DNowx) |
|
1810 |
hwcap_flags |= AV_386_AMD_3DNowx; |
|
3446 | 1811 |
|
1812 |
switch (cpi->cpi_vendor) { |
|
1813 |
case X86_VENDOR_AMD: |
|
1814 |
if (*edx & CPUID_AMD_EDX_TSCP) |
|
1815 |
hwcap_flags |= AV_386_TSCP; |
|
1816 |
if (*ecx & CPUID_AMD_ECX_AHF64) |
|
1817 |
hwcap_flags |= AV_386_AHF; |
|
1818 |
break; |
|
1819 |
||
1820 |
case X86_VENDOR_Intel: |
|
1821 |
/* |
|
1822 |
* Aarrgh. |
|
1823 |
* Intel uses a different bit in the same word. |
|
1824 |
*/ |
|
1825 |
if (*ecx & CPUID_INTC_ECX_AHF64) |
|
1826 |
hwcap_flags |= AV_386_AHF; |
|
1827 |
break; |
|
1828 |
||
1829 |
default: |
|
1830 |
break; |
|
1831 |
} |
|
0 | 1832 |
break; |
1833 |
||
1834 |
case X86_VENDOR_TM: |
|
1228 | 1835 |
cp.cp_eax = 0x80860001; |
1836 |
(void) __cpuid_insn(&cp); |
|
1837 |
cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; |
|
0 | 1838 |
break; |
1839 |
||
1840 |
default: |
|
1841 |
break; |
|
1842 |
} |
|
1843 |
||
1844 |
pass4_done: |
|
1845 |
cpi->cpi_pass = 4; |
|
1846 |
return (hwcap_flags); |
|
1847 |
} |
|
1848 |
||
1849 |
||
1850 |
/* |
|
1851 |
* Simulate the cpuid instruction using the data we previously |
|
1852 |
* captured about this CPU. We try our best to return the truth |
|
1853 |
* about the hardware, independently of kernel support. |
|
1854 |
*/ |
|
1855 |
uint32_t |
|
1228 | 1856 |
cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) |
0 | 1857 |
{ |
1858 |
struct cpuid_info *cpi; |
|
1228 | 1859 |
struct cpuid_regs *xcp; |
0 | 1860 |
|
1861 |
if (cpu == NULL) |
|
1862 |
cpu = CPU; |
|
1863 |
cpi = cpu->cpu_m.mcpu_cpi; |
|
1864 |
||
1865 |
ASSERT(cpuid_checkpass(cpu, 3)); |
|
1866 |
||
1867 |
/* |
|
1868 |
* CPUID data is cached in two separate places: cpi_std for standard |
|
1869 |
* CPUID functions, and cpi_extd for extended CPUID functions. |
|
1870 |
*/ |
|
1228 | 1871 |
if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) |
1872 |
xcp = &cpi->cpi_std[cp->cp_eax]; |
|
1873 |
else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && |
|
1874 |
cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) |
|
1875 |
xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; |
|
0 | 1876 |
else |
1877 |
/* |
|
1878 |
* The caller is asking for data from an input parameter which |
|
1879 |
* the kernel has not cached. In this case we go fetch from |
|
1880 |
* the hardware and return the data directly to the user. |
|
1881 |
*/ |
|
1228 | 1882 |
return (__cpuid_insn(cp)); |
1883 |
||
1884 |
cp->cp_eax = xcp->cp_eax; |
|
1885 |
cp->cp_ebx = xcp->cp_ebx; |
|
1886 |
cp->cp_ecx = xcp->cp_ecx; |
|
1887 |
cp->cp_edx = xcp->cp_edx; |
|
0 | 1888 |
return (cp->cp_eax); |
1889 |
} |
|
1890 |
||
1891 |
int |
|
1892 |
cpuid_checkpass(cpu_t *cpu, int pass) |
|
1893 |
{ |
|
1894 |
return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && |
|
1895 |
cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); |
|
1896 |
} |
|
1897 |
||
1898 |
int |
|
1899 |
cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) |
|
1900 |
{ |
|
1901 |
ASSERT(cpuid_checkpass(cpu, 3)); |
|
1902 |
||
1903 |
return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); |
|
1904 |
} |
|
1905 |
||
1906 |
int |
|
1228 | 1907 |
cpuid_is_cmt(cpu_t *cpu) |
0 | 1908 |
{ |
1909 |
if (cpu == NULL) |
|
1910 |
cpu = CPU; |
|
1911 |
||
1912 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
1913 |
||
1914 |
return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); |
|
1915 |
} |
|
1916 |
||
1917 |
/* |
|
1918 |
* AMD and Intel both implement the 64-bit variant of the syscall |
|
1919 |
* instruction (syscallq), so if there's -any- support for syscall, |
|
1920 |
* cpuid currently says "yes, we support this". |
|
1921 |
* |
|
1922 |
* However, Intel decided to -not- implement the 32-bit variant of the |
|
1923 |
* syscall instruction, so we provide a predicate to allow our caller |
|
1924 |
* to test that subtlety here. |
|
1925 |
*/ |
|
1926 |
/*ARGSUSED*/ |
|
1927 |
int |
|
1928 |
cpuid_syscall32_insn(cpu_t *cpu) |
|
1929 |
{ |
|
1930 |
ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); |
|
1931 |
||
3446 | 1932 |
if (cpu == NULL) |
1933 |
cpu = CPU; |
|
1934 |
||
1935 |
/*CSTYLED*/ |
|
1936 |
{ |
|
1937 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
|
1938 |
||
1939 |
if (cpi->cpi_vendor == X86_VENDOR_AMD && |
|
1940 |
cpi->cpi_xmaxeax >= 0x80000001 && |
|
1941 |
(CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) |
|
1942 |
return (1); |
|
1943 |
} |
|
0 | 1944 |
return (0); |
1945 |
} |
|
1946 |
||
1947 |
int |
|
1948 |
cpuid_getidstr(cpu_t *cpu, char *s, size_t n) |
|
1949 |
{ |
|
1950 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
|
1951 |
||
1952 |
static const char fmt[] = |
|
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
1953 |
"x86 (%s %X family %d model %d step %d clock %d MHz)"; |
0 | 1954 |
static const char fmt_ht[] = |
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
1955 |
"x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; |
0 | 1956 |
|
1957 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
1958 |
||
1228 | 1959 |
if (cpuid_is_cmt(cpu)) |
0 | 1960 |
return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, |
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
1961 |
cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, |
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
1962 |
cpi->cpi_family, cpi->cpi_model, |
0 | 1963 |
cpi->cpi_step, cpu->cpu_type_info.pi_clock)); |
1964 |
return (snprintf(s, n, fmt, |
|
3779
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
1965 |
cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, |
f34a44686f8b
6532527 psrinfo output should show "EAX Page 1" hex value to identify processors
dmick
parents:
3446
diff
changeset
|
1966 |
cpi->cpi_family, cpi->cpi_model, |
0 | 1967 |
cpi->cpi_step, cpu->cpu_type_info.pi_clock)); |
1968 |
} |
|
1969 |
||
1970 |
const char * |
|
1971 |
cpuid_getvendorstr(cpu_t *cpu) |
|
1972 |
{ |
|
1973 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
1974 |
return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); |
|
1975 |
} |
|
1976 |
||
1977 |
uint_t |
|
1978 |
cpuid_getvendor(cpu_t *cpu) |
|
1979 |
{ |
|
1980 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
1981 |
return (cpu->cpu_m.mcpu_cpi->cpi_vendor); |
|
1982 |
} |
|
1983 |
||
1984 |
uint_t |
|
1985 |
cpuid_getfamily(cpu_t *cpu) |
|
1986 |
{ |
|
1987 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
1988 |
return (cpu->cpu_m.mcpu_cpi->cpi_family); |
|
1989 |
} |
|
1990 |
||
1991 |
uint_t |
|
1992 |
cpuid_getmodel(cpu_t *cpu) |
|
1993 |
{ |
|
1994 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
1995 |
return (cpu->cpu_m.mcpu_cpi->cpi_model); |
|
1996 |
} |
|
1997 |
||
1998 |
uint_t |
|
1999 |
cpuid_get_ncpu_per_chip(cpu_t *cpu) |
|
2000 |
{ |
|
2001 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
2002 |
return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); |
|
2003 |
} |
|
2004 |
||
2005 |
uint_t |
|
1228 | 2006 |
cpuid_get_ncore_per_chip(cpu_t *cpu) |
2007 |
{ |
|
2008 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
2009 |
return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); |
|
2010 |
} |
|
2011 |
||
2012 |
uint_t |
|
0 | 2013 |
cpuid_getstep(cpu_t *cpu) |
2014 |
{ |
|
2015 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
2016 |
return (cpu->cpu_m.mcpu_cpi->cpi_step); |
|
2017 |
} |
|
2018 |
||
4581 | 2019 |
uint_t |
2020 |
cpuid_getsig(struct cpu *cpu) |
|
2021 |
{ |
|
2022 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
2023 |
return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); |
|
2024 |
} |
|
2025 |
||
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2026 |
uint32_t |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2027 |
cpuid_getchiprev(struct cpu *cpu) |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2028 |
{ |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2029 |
ASSERT(cpuid_checkpass(cpu, 1)); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2030 |
return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2031 |
} |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2032 |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2033 |
const char * |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2034 |
cpuid_getchiprevstr(struct cpu *cpu) |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2035 |
{ |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2036 |
ASSERT(cpuid_checkpass(cpu, 1)); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2037 |
return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2038 |
} |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2039 |
|
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2040 |
uint32_t |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2041 |
cpuid_getsockettype(struct cpu *cpu) |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2042 |
{ |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2043 |
ASSERT(cpuid_checkpass(cpu, 1)); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2044 |
return (cpu->cpu_m.mcpu_cpi->cpi_socket); |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2045 |
} |
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2046 |
|
3434 | 2047 |
int |
2048 |
cpuid_get_chipid(cpu_t *cpu) |
|
0 | 2049 |
{ |
2050 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
2051 |
||
1228 | 2052 |
if (cpuid_is_cmt(cpu)) |
0 | 2053 |
return (cpu->cpu_m.mcpu_cpi->cpi_chipid); |
2054 |
return (cpu->cpu_id); |
|
2055 |
} |
|
2056 |
||
1228 | 2057 |
id_t |
3434 | 2058 |
cpuid_get_coreid(cpu_t *cpu) |
1228 | 2059 |
{ |
2060 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
2061 |
return (cpu->cpu_m.mcpu_cpi->cpi_coreid); |
|
2062 |
} |
|
2063 |
||
0 | 2064 |
int |
3434 | 2065 |
cpuid_get_clogid(cpu_t *cpu) |
0 | 2066 |
{ |
2067 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
2068 |
return (cpu->cpu_m.mcpu_cpi->cpi_clogid); |
|
2069 |
} |
|
2070 |
||
2071 |
void |
|
2072 |
cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) |
|
2073 |
{ |
|
2074 |
struct cpuid_info *cpi; |
|
2075 |
||
2076 |
if (cpu == NULL) |
|
2077 |
cpu = CPU; |
|
2078 |
cpi = cpu->cpu_m.mcpu_cpi; |
|
2079 |
||
2080 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
2081 |
||
2082 |
if (pabits) |
|
2083 |
*pabits = cpi->cpi_pabits; |
|
2084 |
if (vabits) |
|
2085 |
*vabits = cpi->cpi_vabits; |
|
2086 |
} |
|
2087 |
||
2088 |
/* |
|
2089 |
* Returns the number of data TLB entries for a corresponding |
|
2090 |
* pagesize. If it can't be computed, or isn't known, the |
|
2091 |
* routine returns zero. If you ask about an architecturally |
|
2092 |
* impossible pagesize, the routine will panic (so that the |
|
2093 |
* hat implementor knows that things are inconsistent.) |
|
2094 |
*/ |
|
2095 |
uint_t |
|
2096 |
cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) |
|
2097 |
{ |
|
2098 |
struct cpuid_info *cpi; |
|
2099 |
uint_t dtlb_nent = 0; |
|
2100 |
||
2101 |
if (cpu == NULL) |
|
2102 |
cpu = CPU; |
|
2103 |
cpi = cpu->cpu_m.mcpu_cpi; |
|
2104 |
||
2105 |
ASSERT(cpuid_checkpass(cpu, 1)); |
|
2106 |
||
2107 |
/* |
|
2108 |
* Check the L2 TLB info |
|
2109 |
*/ |
|
2110 |
if (cpi->cpi_xmaxeax >= 0x80000006) { |
|
1228 | 2111 |
struct cpuid_regs *cp = &cpi->cpi_extd[6]; |
0 | 2112 |
|
2113 |
switch (pagesize) { |
|
2114 |
||
2115 |
case 4 * 1024: |
|
2116 |
/* |
|
2117 |
* All zero in the top 16 bits of the register |
|
2118 |
* indicates a unified TLB. Size is in low 16 bits. |
|
2119 |
*/ |
|
2120 |
if ((cp->cp_ebx & 0xffff0000) == 0) |
|
2121 |
dtlb_nent = cp->cp_ebx & 0x0000ffff; |
|
2122 |
else |
|
2123 |
dtlb_nent = BITX(cp->cp_ebx, 27, 16); |
|
2124 |
break; |
|
2125 |
||
2126 |
case 2 * 1024 * 1024: |
|
2127 |
if ((cp->cp_eax & 0xffff0000) == 0) |
|
2128 |
dtlb_nent = cp->cp_eax & 0x0000ffff; |
|
2129 |
else |
|
2130 |
dtlb_nent = BITX(cp->cp_eax, 27, 16); |
|
2131 |
break; |
|
2132 |
||
2133 |
default: |
|
2134 |
panic("unknown L2 pagesize"); |
|
2135 |
/*NOTREACHED*/ |
|
2136 |
} |
|
2137 |
} |
|
2138 |
||
2139 |
if (dtlb_nent != 0) |
|
2140 |
return (dtlb_nent); |
|
2141 |
||
2142 |
/* |
|
2143 |
* No L2 TLB support for this size, try L1. |
|
2144 |
*/ |
|
2145 |
if (cpi->cpi_xmaxeax >= 0x80000005) { |
|
1228 | 2146 |
struct cpuid_regs *cp = &cpi->cpi_extd[5]; |
0 | 2147 |
|
2148 |
switch (pagesize) { |
|
2149 |
case 4 * 1024: |
|
2150 |
dtlb_nent = BITX(cp->cp_ebx, 23, 16); |
|
2151 |
break; |
|
2152 |
case 2 * 1024 * 1024: |
|
2153 |
dtlb_nent = BITX(cp->cp_eax, 23, 16); |
|
2154 |
break; |
|
2155 |
default: |
|
2156 |
panic("unknown L1 d-TLB pagesize"); |
|
2157 |
/*NOTREACHED*/ |
|
2158 |
} |
|
2159 |
} |
|
2160 |
||
2161 |
return (dtlb_nent); |
|
2162 |
} |
|
2163 |
||
2164 |
/* |
|
2165 |
* Return 0 if the erratum is not present or not applicable, positive |
|
2166 |
* if it is, and negative if the status of the erratum is unknown. |
|
2167 |
* |
|
2168 |
* See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) |
|
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
0
diff
changeset
|
2169 |
* Processors" #25759, Rev 3.57, August 2005 |
0 | 2170 |
*/ |
2171 |
int |
|
2172 |
cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) |
|
2173 |
{ |
|
2174 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
|
1228 | 2175 |
uint_t eax; |
0 | 2176 |
|
2584
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2177 |
/* |
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2178 |
* Bail out if this CPU isn't an AMD CPU, or if it's |
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2179 |
* a legacy (32-bit) AMD CPU. |
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2180 |
*/ |
c8f937287646
6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs
sethg
parents:
2519
diff
changeset
|
2181 |
if (cpi->cpi_vendor != X86_VENDOR_AMD || |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2182 |
cpi->cpi_family == 4 || cpi->cpi_family == 5 || |
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2183 |
cpi->cpi_family == 6) |
2869
324151eecd58
PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors
gavinm
parents:
2584
diff
changeset
|
2184 |
|
0 | 2185 |
return (0); |
2186 |
||
2187 |
eax = cpi->cpi_std[1].cp_eax; |
|
2188 |
||
2189 |
#define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) |
|
2190 |
#define SH_B3(eax) (eax == 0xf51) |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2191 |
#define B(eax) (SH_B0(eax) || SH_B3(eax)) |
0 | 2192 |
|
2193 |
#define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) |
|
2194 |
||
2195 |
#define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) |
|
2196 |
#define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) |
|
2197 |
#define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2198 |
#define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) |
0 | 2199 |
|
2200 |
#define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) |
|
2201 |
#define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) |
|
2202 |
#define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2203 |
#define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) |
0 | 2204 |
|
2205 |
#define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) |
|
2206 |
#define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ |
|
2207 |
#define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) |
|
2208 |
#define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) |
|
2209 |
#define BH_E4(eax) (eax == 0x20fb1) |
|
2210 |
#define SH_E5(eax) (eax == 0x20f42) |
|
2211 |
#define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) |
|
2212 |
#define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) |
|
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2213 |
#define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2214 |
SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2215 |
DH_E6(eax) || JH_E6(eax)) |
0 | 2216 |
|
2217 |
switch (erratum) { |
|
2218 |
case 1: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2219 |
return (cpi->cpi_family < 0x10); |
0 | 2220 |
case 51: /* what does the asterisk mean? */ |
2221 |
return (B(eax) || SH_C0(eax) || CG(eax)); |
|
2222 |
case 52: |
|
2223 |
return (B(eax)); |
|
2224 |
case 57: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2225 |
return (cpi->cpi_family <= 0x10); |
0 | 2226 |
case 58: |
2227 |
return (B(eax)); |
|
2228 |
case 60: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2229 |
return (cpi->cpi_family <= 0x10); |
0 | 2230 |
case 61: |
2231 |
case 62: |
|
2232 |
case 63: |
|
2233 |
case 64: |
|
2234 |
case 65: |
|
2235 |
case 66: |
|
2236 |
case 68: |
|
2237 |
case 69: |
|
2238 |
case 70: |
|
2239 |
case 71: |
|
2240 |
return (B(eax)); |
|
2241 |
case 72: |
|
2242 |
return (SH_B0(eax)); |
|
2243 |
case 74: |
|
2244 |
return (B(eax)); |
|
2245 |
case 75: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2246 |
return (cpi->cpi_family < 0x10); |
0 | 2247 |
case 76: |
2248 |
return (B(eax)); |
|
2249 |
case 77: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2250 |
return (cpi->cpi_family <= 0x10); |
0 | 2251 |
case 78: |
2252 |
return (B(eax) || SH_C0(eax)); |
|
2253 |
case 79: |
|
2254 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); |
|
2255 |
case 80: |
|
2256 |
case 81: |
|
2257 |
case 82: |
|
2258 |
return (B(eax)); |
|
2259 |
case 83: |
|
2260 |
return (B(eax) || SH_C0(eax) || CG(eax)); |
|
2261 |
case 85: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2262 |
return (cpi->cpi_family < 0x10); |
0 | 2263 |
case 86: |
2264 |
return (SH_C0(eax) || CG(eax)); |
|
2265 |
case 88: |
|
2266 |
#if !defined(__amd64) |
|
2267 |
return (0); |
|
2268 |
#else |
|
2269 |
return (B(eax) || SH_C0(eax)); |
|
2270 |
#endif |
|
2271 |
case 89: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2272 |
return (cpi->cpi_family < 0x10); |
0 | 2273 |
case 90: |
2274 |
return (B(eax) || SH_C0(eax) || CG(eax)); |
|
2275 |
case 91: |
|
2276 |
case 92: |
|
2277 |
return (B(eax) || SH_C0(eax)); |
|
2278 |
case 93: |
|
2279 |
return (SH_C0(eax)); |
|
2280 |
case 94: |
|
2281 |
return (B(eax) || SH_C0(eax) || CG(eax)); |
|
2282 |
case 95: |
|
2283 |
#if !defined(__amd64) |
|
2284 |
return (0); |
|
2285 |
#else |
|
2286 |
return (B(eax) || SH_C0(eax)); |
|
2287 |
#endif |
|
2288 |
case 96: |
|
2289 |
return (B(eax) || SH_C0(eax) || CG(eax)); |
|
2290 |
case 97: |
|
2291 |
case 98: |
|
2292 |
return (SH_C0(eax) || CG(eax)); |
|
2293 |
case 99: |
|
2294 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); |
|
2295 |
case 100: |
|
2296 |
return (B(eax) || SH_C0(eax)); |
|
2297 |
case 101: |
|
2298 |
case 103: |
|
2299 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); |
|
2300 |
case 104: |
|
2301 |
return (SH_C0(eax) || CG(eax) || D0(eax)); |
|
2302 |
case 105: |
|
2303 |
case 106: |
|
2304 |
case 107: |
|
2305 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); |
|
2306 |
case 108: |
|
2307 |
return (DH_CG(eax)); |
|
2308 |
case 109: |
|
2309 |
return (SH_C0(eax) || CG(eax) || D0(eax)); |
|
2310 |
case 110: |
|
2311 |
return (D0(eax) || EX(eax)); |
|
2312 |
case 111: |
|
2313 |
return (CG(eax)); |
|
2314 |
case 112: |
|
2315 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); |
|
2316 |
case 113: |
|
2317 |
return (eax == 0x20fc0); |
|
2318 |
case 114: |
|
2319 |
return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); |
|
2320 |
case 115: |
|
2321 |
return (SH_E0(eax) || JH_E1(eax)); |
|
2322 |
case 116: |
|
2323 |
return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); |
|
2324 |
case 117: |
|
2325 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); |
|
2326 |
case 118: |
|
2327 |
return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || |
|
2328 |
JH_E6(eax)); |
|
2329 |
case 121: |
|
2330 |
return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); |
|
2331 |
case 122: |
|
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2332 |
return (cpi->cpi_family < 0x10); |
0 | 2333 |
case 123: |
2334 |
return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); |
|
359
a88cb999e7ec
6288246 amd64 kernel needs to detect AMD Opteron erratum 131
kucharsk
parents:
0
diff
changeset
|
2335 |
case 131: |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2336 |
return (cpi->cpi_family < 0x10); |
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2337 |
case 6336786: |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2338 |
/* |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2339 |
* Test for AdvPowerMgmtInfo.TscPStateInvariant |
4265
6be078c4d3b4
6555108 workarounds being applied for errata not present in greyhound processors
kchow
parents:
3779
diff
changeset
|
2340 |
* if this is a K8 family or newer processor |
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2341 |
*/ |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2342 |
if (CPI_FAMILY(cpi) == 0xf) { |
1228 | 2343 |
struct cpuid_regs regs; |
2344 |
regs.cp_eax = 0x80000007; |
|
2345 |
(void) __cpuid_insn(®s); |
|
2346 |
return (!(regs.cp_edx & 0x100)); |
|
938
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2347 |
} |
2d438f28c673
6336786 time doesn't fly when CPUs are not having fun
esaxe
parents:
789
diff
changeset
|
2348 |
return (0); |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2349 |
case 6323525: |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2350 |
return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2351 |
(((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); |
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2352 |
|
0 | 2353 |
default: |
2354 |
return (-1); |
|
2355 |
} |
|
2356 |
} |
|
2357 |
||
2358 |
static const char assoc_str[] = "associativity"; |
|
2359 |
static const char line_str[] = "line-size"; |
|
2360 |
static const char size_str[] = "size"; |
|
2361 |
||
2362 |
static void |
|
2363 |
add_cache_prop(dev_info_t *devi, const char *label, const char *type, |
|
2364 |
uint32_t val) |
|
2365 |
{ |
|
2366 |
char buf[128]; |
|
2367 |
||
2368 |
/* |
|
2369 |
* ndi_prop_update_int() is used because it is desirable for |
|
2370 |
* DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. |
|
2371 |
*/ |
|
2372 |
if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) |
|
2373 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); |
|
2374 |
} |
|
2375 |
||
2376 |
/* |
|
2377 |
* Intel-style cache/tlb description |
|
2378 |
* |
|
2379 |
* Standard cpuid level 2 gives a randomly ordered |
|
2380 |
* selection of tags that index into a table that describes |
|
2381 |
* cache and tlb properties. |
|
2382 |
*/ |
|
2383 |
||
2384 |
static const char l1_icache_str[] = "l1-icache"; |
|
2385 |
static const char l1_dcache_str[] = "l1-dcache"; |
|
2386 |
static const char l2_cache_str[] = "l2-cache"; |
|
3446 | 2387 |
static const char l3_cache_str[] = "l3-cache"; |
0 | 2388 |
static const char itlb4k_str[] = "itlb-4K"; |
2389 |
static const char dtlb4k_str[] = "dtlb-4K"; |
|
2390 |
static const char itlb4M_str[] = "itlb-4M"; |
|
2391 |
static const char dtlb4M_str[] = "dtlb-4M"; |
|
2392 |
static const char itlb424_str[] = "itlb-4K-2M-4M"; |
|
2393 |
static const char dtlb44_str[] = "dtlb-4K-4M"; |
|
2394 |
static const char sl1_dcache_str[] = "sectored-l1-dcache"; |
|
2395 |
static const char sl2_cache_str[] = "sectored-l2-cache"; |
|
2396 |
static const char itrace_str[] = "itrace-cache"; |
|
2397 |
static const char sl3_cache_str[] = "sectored-l3-cache"; |
|
2398 |
||
2399 |
static const struct cachetab { |
|
2400 |
uint8_t ct_code; |
|
2401 |
uint8_t ct_assoc; |
|
2402 |
uint16_t ct_line_size; |
|
2403 |
size_t ct_size; |
|
2404 |
const char *ct_label; |
|
2405 |
} intel_ctab[] = { |
|
2406 |
/* maintain descending order! */ |
|
3446 | 2407 |
{ 0xb4, 4, 0, 256, dtlb4k_str }, |
0 | 2408 |
{ 0xb3, 4, 0, 128, dtlb4k_str }, |
2409 |
{ 0xb0, 4, 0, 128, itlb4k_str }, |
|
2410 |
{ 0x87, 8, 64, 1024*1024, l2_cache_str}, |
|
2411 |
{ 0x86, 4, 64, 512*1024, l2_cache_str}, |
|
2412 |
{ 0x85, 8, 32, 2*1024*1024, l2_cache_str}, |
|
2413 |
{ 0x84, 8, 32, 1024*1024, l2_cache_str}, |
|
2414 |
{ 0x83, 8, 32, 512*1024, l2_cache_str}, |
|
2415 |
{ 0x82, 8, 32, 256*1024, l2_cache_str}, |
|
2416 |
{ 0x7f, 2, 64, 512*1024, l2_cache_str}, |
|
2417 |
{ 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, |
|
2418 |
{ 0x7c, 8, 64, 1024*1024, sl2_cache_str}, |
|
2419 |
{ 0x7b, 8, 64, 512*1024, sl2_cache_str}, |
|
2420 |
{ 0x7a, 8, 64, 256*1024, sl2_cache_str}, |
|
2421 |
{ 0x79, 8, 64, 128*1024, sl2_cache_str}, |
|
2422 |
{ 0x78, 8, 64, 1024*1024, l2_cache_str}, |
|
3446 | 2423 |
{ 0x73, 8, 0, 64*1024, itrace_str}, |
0 | 2424 |
{ 0x72, 8, 0, 32*1024, itrace_str}, |
2425 |
{ 0x71, 8, 0, 16*1024, itrace_str}, |
|
2426 |
{ 0x70, 8, 0, 12*1024, itrace_str}, |
|
2427 |
{ 0x68, 4, 64, 32*1024, sl1_dcache_str}, |
|
2428 |
{ 0x67, 4, 64, 16*1024, sl1_dcache_str}, |
|
2429 |
{ 0x66, 4, 64, 8*1024, sl1_dcache_str}, |
|
2430 |
{ 0x60, 8, 64, 16*1024, sl1_dcache_str}, |
|
2431 |
{ 0x5d, 0, 0, 256, dtlb44_str}, |
|
2432 |
{ 0x5c, 0, 0, 128, dtlb44_str}, |
|
2433 |
{ 0x5b, 0, 0, 64, dtlb44_str}, |
|
2434 |
{ 0x52, 0, 0, 256, itlb424_str}, |
|
2435 |
{ 0x51, 0, 0, 128, itlb424_str}, |
|
2436 |
{ 0x50, 0, 0, 64, itlb424_str}, |
|
3446 | 2437 |
{ 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, |
2438 |
{ 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, |
|
2439 |
{ 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, |
|
2440 |
{ 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, |
|
2441 |
{ 0x49, 16, 64, 4*1024*1024, l3_cache_str}, |
|
2442 |
{ 0x47, 8, 64, 8*1024*1024, l3_cache_str}, |
|
2443 |
{ 0x46, 4, 64, 4*1024*1024, l3_cache_str}, |
|
0 | 2444 |
{ 0x45, 4, 32, 2*1024*1024, l2_cache_str}, |
2445 |
{ 0x44, 4, 32, 1024*1024, l2_cache_str}, |
|
2446 |
{ 0x43, 4, 32, 512*1024, l2_cache_str}, |
|
2447 |
{ 0x42, 4, 32, 256*1024, l2_cache_str}, |
|
2448 |
{ 0x41, 4, 32, 128*1024, l2_cache_str}, |
|
3446 | 2449 |
{ 0x3e, 4, 64, 512*1024, sl2_cache_str}, |
2450 |
{ 0x3d, 6, 64, 384*1024, sl2_cache_str}, |
|
0 | 2451 |
{ 0x3c, 4, 64, 256*1024, sl2_cache_str}, |
2452 |
{ 0x3b, 2, 64, 128*1024, sl2_cache_str}, |
|
3446 | 2453 |
{ 0x3a, 6, 64, 192*1024, sl2_cache_str}, |
0 | 2454 |
{ 0x39, 4, 64, 128*1024, sl2_cache_str}, |
2455 |
{ 0x30, 8, 64, 32*1024, l1_icache_str}, |
|
2456 |
{ 0x2c, 8, 64, 32*1024, l1_dcache_str}, |
|
2457 |
{ 0x29, 8, 64, 4096*1024, sl3_cache_str}, |
|
2458 |
{ 0x25, 8, 64, 2048*1024, sl3_cache_str}, |
|
2459 |
{ 0x23, 8, 64, 1024*1024, sl3_cache_str}, |
|
2460 |
{ 0x22, 4, 64, 512*1024, sl3_cache_str}, |
|
2461 |
{ 0x0c, 4, 32, 16*1024, l1_dcache_str}, |
|
3446 | 2462 |
{ 0x0b, 4, 0, 4, itlb4M_str}, |
0 | 2463 |
{ 0x0a, 2, 32, 8*1024, l1_dcache_str}, |
2464 |
{ 0x08, 4, 32, 16*1024, l1_icache_str}, |
|
2465 |
{ 0x06, 4, 32, 8*1024, l1_icache_str}, |
|
2466 |
{ 0x04, 4, 0, 8, dtlb4M_str}, |
|
2467 |
{ 0x03, 4, 0, 64, dtlb4k_str}, |
|
2468 |
{ 0x02, 4, 0, 2, itlb4M_str}, |
|
2469 |
{ 0x01, 4, 0, 32, itlb4k_str}, |
|
2470 |
{ 0 } |
|
2471 |
}; |
|
2472 |
||
2473 |
static const struct cachetab cyrix_ctab[] = { |
|
2474 |
{ 0x70, 4, 0, 32, "tlb-4K" }, |
|
2475 |
{ 0x80, 4, 16, 16*1024, "l1-cache" }, |
|
2476 |
{ 0 } |
|
2477 |
}; |
|
2478 |
||
2479 |
/* |
|
2480 |
* Search a cache table for a matching entry |
|
2481 |
*/ |
|
2482 |
static const struct cachetab * |
|
2483 |
find_cacheent(const struct cachetab *ct, uint_t code) |
|
2484 |
{ |
|
2485 |
if (code != 0) { |
|
2486 |
for (; ct->ct_code != 0; ct++) |
|
2487 |
if (ct->ct_code <= code) |
|
2488 |
break; |
|
2489 |
if (ct->ct_code == code) |
|
2490 |
return (ct); |
|
2491 |
} |
|
2492 |
return (NULL); |
|
2493 |
} |
|
2494 |
||
2495 |
/* |
|
2496 |
* Walk the cacheinfo descriptor, applying 'func' to every valid element |
|
2497 |
* The walk is terminated if the walker returns non-zero. |
|
2498 |
*/ |
|
2499 |
static void |
|
2500 |
intel_walk_cacheinfo(struct cpuid_info *cpi, |
|
2501 |
void *arg, int (*func)(void *, const struct cachetab *)) |
|
2502 |
{ |
|
2503 |
const struct cachetab *ct; |
|
2504 |
uint8_t *dp; |
|
2505 |
int i; |
|
2506 |
||
2507 |
if ((dp = cpi->cpi_cacheinfo) == NULL) |
|
2508 |
return; |
|
2509 |
for (i = 0; i < cpi->cpi_ncache; i++, dp++) |
|
2510 |
if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { |
|
2511 |
if (func(arg, ct) != 0) |
|
2512 |
break; |
|
2513 |
} |
|
2514 |
} |
|
2515 |
||
2516 |
/* |
|
2517 |
* (Like the Intel one, except for Cyrix CPUs) |
|
2518 |
*/ |
|
2519 |
static void |
|
2520 |
cyrix_walk_cacheinfo(struct cpuid_info *cpi, |
|
2521 |
void *arg, int (*func)(void *, const struct cachetab *)) |
|
2522 |
{ |
|
2523 |
const struct cachetab *ct; |
|
2524 |
uint8_t *dp; |
|
2525 |
int i; |
|
2526 |
||
2527 |
if ((dp = cpi->cpi_cacheinfo) == NULL) |
|
2528 |
return; |
|
2529 |
for (i = 0; i < cpi->cpi_ncache; i++, dp++) { |
|
2530 |
/* |
|
2531 |
* Search Cyrix-specific descriptor table first .. |
|
2532 |
*/ |
|
2533 |
if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { |
|
2534 |
if (func(arg, ct) != 0) |
|
2535 |
break; |
|
2536 |
continue; |
|
2537 |
} |
|
2538 |
/* |
|
2539 |
* .. else fall back to the Intel one |
|
2540 |
*/ |
|
2541 |
if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { |
|
2542 |
if (func(arg, ct) != 0) |
|
2543 |
break; |
|
2544 |
continue; |
|
2545 |
} |
|
2546 |
} |
|
2547 |
} |
|
2548 |
||
2549 |
/* |
|
2550 |
* A cacheinfo walker that adds associativity, line-size, and size properties |
|
2551 |
* to the devinfo node it is passed as an argument. |
|
2552 |
*/ |
|
2553 |
static int |
|
2554 |
add_cacheent_props(void *arg, const struct cachetab *ct) |
|
2555 |
{ |
|
2556 |
dev_info_t *devi = arg; |
|
2557 |
||
2558 |
add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); |
|
2559 |
if (ct->ct_line_size != 0) |
|
2560 |
add_cache_prop(devi, ct->ct_label, line_str, |
|
2561 |
ct->ct_line_size); |
|
2562 |
add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); |
|
2563 |
return (0); |
|
2564 |
} |
|
2565 |
||
2566 |
static const char fully_assoc[] = "fully-associative?"; |
|
2567 |
||
2568 |
/* |
|
2569 |
* AMD style cache/tlb description |
|
2570 |
* |
|
2571 |
* Extended functions 5 and 6 directly describe properties of |
|
2572 |
* tlbs and various cache levels. |
|
2573 |
*/ |
|
2574 |
static void |
|
2575 |
add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) |
|
2576 |
{ |
|
2577 |
switch (assoc) { |
|
2578 |
case 0: /* reserved; ignore */ |
|
2579 |
break; |
|
2580 |
default: |
|
2581 |
add_cache_prop(devi, label, assoc_str, assoc); |
|
2582 |
break; |
|
2583 |
case 0xff: |
|
2584 |
add_cache_prop(devi, label, fully_assoc, 1); |
|
2585 |
break; |
|
2586 |
} |
|
2587 |
} |
|
2588 |
||
2589 |
static void |
|
2590 |
add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) |
|
2591 |
{ |
|
2592 |
if (size == 0) |
|
2593 |
return; |
|
2594 |
add_cache_prop(devi, label, size_str, size); |
|
2595 |
add_amd_assoc(devi, label, assoc); |
|
2596 |
} |
|
2597 |
||
2598 |
static void |
|
2599 |
add_amd_cache(dev_info_t *devi, const char *label, |
|
2600 |
uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) |
|
2601 |
{ |
|
2602 |
if (size == 0 || line_size == 0) |
|
2603 |
return; |
|
2604 |
add_amd_assoc(devi, label, assoc); |
|
2605 |
/* |
|
2606 |
* Most AMD parts have a sectored cache. Multiple cache lines are |
|
2607 |
* associated with each tag. A sector consists of all cache lines |
|
2608 |
* associated with a tag. For example, the AMD K6-III has a sector |
|
2609 |
* size of 2 cache lines per tag. |
|
2610 |
*/ |
|
2611 |
if (lines_per_tag != 0) |
|
2612 |
add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); |
|
2613 |
add_cache_prop(devi, label, line_str, line_size); |
|
2614 |
add_cache_prop(devi, label, size_str, size * 1024); |
|
2615 |
} |
|
2616 |
||
2617 |
static void |
|
2618 |
add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) |
|
2619 |
{ |
|
2620 |
switch (assoc) { |
|
2621 |
case 0: /* off */ |
|
2622 |
break; |
|
2623 |
case 1: |
|
2624 |
case 2: |
|
2625 |
case 4: |
|
2626 |
add_cache_prop(devi, label, assoc_str, assoc); |
|
2627 |
break; |
|
2628 |
case 6: |
|
2629 |
add_cache_prop(devi, label, assoc_str, 8); |
|
2630 |
break; |
|
2631 |
case 8: |
|
2632 |
add_cache_prop(devi, label, assoc_str, 16); |
|
2633 |
break; |
|
2634 |
case 0xf: |
|
2635 |
add_cache_prop(devi, label, fully_assoc, 1); |
|
2636 |
break; |
|
2637 |
default: /* reserved; ignore */ |
|
2638 |
break; |
|
2639 |
} |
|
2640 |
} |
|
2641 |
||
2642 |
static void |
|
2643 |
add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) |
|
2644 |
{ |
|
2645 |
if (size == 0 || assoc == 0) |
|
2646 |
return; |
|
2647 |
add_amd_l2_assoc(devi, label, assoc); |
|
2648 |
add_cache_prop(devi, label, size_str, size); |
|
2649 |
} |
|
2650 |
||
2651 |
static void |
|
2652 |
add_amd_l2_cache(dev_info_t *devi, const char *label, |
|
2653 |
uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) |
|
2654 |
{ |
|
2655 |
if (size == 0 || assoc == 0 || line_size == 0) |
|
2656 |
return; |
|
2657 |
add_amd_l2_assoc(devi, label, assoc); |
|
2658 |
if (lines_per_tag != 0) |
|
2659 |
add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); |
|
2660 |
add_cache_prop(devi, label, line_str, line_size); |
|
2661 |
add_cache_prop(devi, label, size_str, size * 1024); |
|
2662 |
} |
|
2663 |
||
2664 |
static void |
|
2665 |
amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) |
|
2666 |
{ |
|
1228 | 2667 |
struct cpuid_regs *cp; |
0 | 2668 |
|
2669 |
if (cpi->cpi_xmaxeax < 0x80000005) |
|
2670 |
return; |
|
2671 |
cp = &cpi->cpi_extd[5]; |
|
2672 |
||
2673 |
/* |
|
2674 |
* 4M/2M L1 TLB configuration |
|
2675 |
* |
|
2676 |
* We report the size for 2M pages because AMD uses two |
|
2677 |
* TLB entries for one 4M page. |
|
2678 |
*/ |
|
2679 |
add_amd_tlb(devi, "dtlb-2M", |
|
2680 |
BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); |
|
2681 |
add_amd_tlb(devi, "itlb-2M", |
|
2682 |
BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); |
|
2683 |
||
2684 |
/* |
|
2685 |
* 4K L1 TLB configuration |
|
2686 |
*/ |
|
2687 |
||
2688 |
switch (cpi->cpi_vendor) { |
|
2689 |
uint_t nentries; |
|
2690 |
case X86_VENDOR_TM: |
|
2691 |
if (cpi->cpi_family >= 5) { |
|
2692 |
/* |
|
2693 |
* Crusoe processors have 256 TLB entries, but |
|
2694 |
* cpuid data format constrains them to only |
|
2695 |
* reporting 255 of them. |
|
2696 |
*/ |
|
2697 |
if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) |
|
2698 |
nentries = 256; |
|
2699 |
/* |
|
2700 |
* Crusoe processors also have a unified TLB |
|
2701 |
*/ |
|
2702 |
add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), |
|
2703 |
nentries); |
|
2704 |
break; |
|
2705 |
} |
|
2706 |
/*FALLTHROUGH*/ |
|
2707 |
default: |
|
2708 |
add_amd_tlb(devi, itlb4k_str, |
|
2709 |
BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); |
|
2710 |
add_amd_tlb(devi, dtlb4k_str, |
|
2711 |
BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); |
|
2712 |
break; |
|
2713 |
} |
|
2714 |
||
2715 |
/* |
|
2716 |
* data L1 cache configuration |
|
2717 |
*/ |
|
2718 |
||
2719 |
add_amd_cache(devi, l1_dcache_str, |
|
2720 |
BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), |
|
2721 |
BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); |
|
2722 |
||
2723 |
/* |
|
2724 |
* code L1 cache configuration |
|
2725 |
*/ |
|
2726 |
||
2727 |
add_amd_cache(devi, l1_icache_str, |
|
2728 |
BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), |
|
2729 |
BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); |
|
2730 |
||
2731 |
if (cpi->cpi_xmaxeax < 0x80000006) |
|
2732 |
return; |
|
2733 |
cp = &cpi->cpi_extd[6]; |
|
2734 |
||
2735 |
/* Check for a unified L2 TLB for large pages */ |
|
2736 |
||
2737 |
if (BITX(cp->cp_eax, 31, 16) == 0) |
|
2738 |
add_amd_l2_tlb(devi, "l2-tlb-2M", |
|
2739 |
BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); |
|
2740 |
else { |
|
2741 |
add_amd_l2_tlb(devi, "l2-dtlb-2M", |
|
2742 |
BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); |
|
2743 |
add_amd_l2_tlb(devi, "l2-itlb-2M", |
|
2744 |
BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); |
|
2745 |
} |
|
2746 |
||
2747 |
/* Check for a unified L2 TLB for 4K pages */ |
|
2748 |
||
2749 |
if (BITX(cp->cp_ebx, 31, 16) == 0) { |
|
2750 |
add_amd_l2_tlb(devi, "l2-tlb-4K", |
|
2751 |
BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); |
|
2752 |
} else { |
|
2753 |
add_amd_l2_tlb(devi, "l2-dtlb-4K", |
|
2754 |
BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); |
|
2755 |
add_amd_l2_tlb(devi, "l2-itlb-4K", |
|
2756 |
BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); |
|
2757 |
} |
|
2758 |
||
2759 |
add_amd_l2_cache(devi, l2_cache_str, |
|
2760 |
BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), |
|
2761 |
BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); |
|
2762 |
} |
|
2763 |
||
2764 |
/* |
|
2765 |
* There are two basic ways that the x86 world describes it cache |
|
2766 |
* and tlb architecture - Intel's way and AMD's way. |
|
2767 |
* |
|
2768 |
* Return which flavor of cache architecture we should use |
|
2769 |
*/ |
|
2770 |
static int |
|
2771 |
x86_which_cacheinfo(struct cpuid_info *cpi) |
|
2772 |
{ |
|
2773 |
switch (cpi->cpi_vendor) { |
|
2774 |
case X86_VENDOR_Intel: |
|
2775 |
if (cpi->cpi_maxeax >= 2) |
|
2776 |
return (X86_VENDOR_Intel); |
|
2777 |
break; |
|
2778 |
case X86_VENDOR_AMD: |
|
2779 |
/* |
|
2780 |
* The K5 model 1 was the first part from AMD that reported |
|
2781 |
* cache sizes via extended cpuid functions. |
|
2782 |
*/ |
|
2783 |
if (cpi->cpi_family > 5 || |
|
2784 |
(cpi->cpi_family == 5 && cpi->cpi_model >= 1)) |
|
2785 |
return (X86_VENDOR_AMD); |
|
2786 |
break; |
|
2787 |
case X86_VENDOR_TM: |
|
2788 |
if (cpi->cpi_family >= 5) |
|
2789 |
return (X86_VENDOR_AMD); |
|
2790 |
/*FALLTHROUGH*/ |
|
2791 |
default: |
|
2792 |
/* |
|
2793 |
* If they have extended CPU data for 0x80000005 |
|
2794 |
* then we assume they have AMD-format cache |
|
2795 |
* information. |
|
2796 |
* |
|
2797 |
* If not, and the vendor happens to be Cyrix, |
|
2798 |
* then try our-Cyrix specific handler. |
|
2799 |
* |
|
2800 |
* If we're not Cyrix, then assume we're using Intel's |
|
2801 |
* table-driven format instead. |
|
2802 |
*/ |
|
2803 |
if (cpi->cpi_xmaxeax >= 0x80000005) |
|
2804 |
return (X86_VENDOR_AMD); |
|
2805 |
else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) |
|
2806 |
return (X86_VENDOR_Cyrix); |
|
2807 |
else if (cpi->cpi_maxeax >= 2) |
|
2808 |
return (X86_VENDOR_Intel); |
|
2809 |
break; |
|
2810 |
} |
|
2811 |
return (-1); |
|
2812 |
} |
|
2813 |
||
2814 |
/* |
|
2815 |
* create a node for the given cpu under the prom root node. |
|
2816 |
* Also, create a cpu node in the device tree. |
|
2817 |
*/ |
|
2818 |
static dev_info_t *cpu_nex_devi = NULL; |
|
2819 |
static kmutex_t cpu_node_lock; |
|
2820 |
||
2821 |
/* |
|
2822 |
* Called from post_startup() and mp_startup() |
|
2823 |
*/ |
|
2824 |
void |
|
2825 |
add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) |
|
2826 |
{ |
|
2827 |
dev_info_t *cpu_devi; |
|
2828 |
int create; |
|
2829 |
||
2830 |
mutex_enter(&cpu_node_lock); |
|
2831 |
||
2832 |
/* |
|
2833 |
* create a nexus node for all cpus identified as 'cpu_id' under |
|
2834 |
* the root node. |
|
2835 |
*/ |
|
2836 |
if (cpu_nex_devi == NULL) { |
|
2837 |
if (ndi_devi_alloc(ddi_root_node(), "cpus", |
|
789 | 2838 |
(pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { |
0 | 2839 |
mutex_exit(&cpu_node_lock); |
2840 |
return; |
|
2841 |
} |
|
2842 |
(void) ndi_devi_online(cpu_nex_devi, 0); |
|
2843 |
} |
|
2844 |
||
2845 |
/* |
|
2846 |
* create a child node for cpu identified as 'cpu_id' |
|
2847 |
*/ |
|
2848 |
cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
2849 |
cpu_id); |
0 | 2850 |
if (cpu_devi == NULL) { |
2851 |
mutex_exit(&cpu_node_lock); |
|
2852 |
return; |
|
2853 |
} |
|
2854 |
||
2855 |
/* device_type */ |
|
2856 |
||
2857 |
(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, |
|
2858 |
"device_type", "cpu"); |
|
2859 |
||
2860 |
/* reg */ |
|
2861 |
||
2862 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
2863 |
"reg", cpu_id); |
|
2864 |
||
2865 |
/* cpu-mhz, and clock-frequency */ |
|
2866 |
||
2867 |
if (cpu_freq > 0) { |
|
2868 |
long long mul; |
|
2869 |
||
2870 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
2871 |
"cpu-mhz", cpu_freq); |
|
2872 |
||
2873 |
if ((mul = cpu_freq * 1000000LL) <= INT_MAX) |
|
2874 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
2875 |
"clock-frequency", (int)mul); |
|
2876 |
} |
|
2877 |
||
2878 |
(void) ndi_devi_online(cpu_devi, 0); |
|
2879 |
||
2880 |
if ((x86_feature & X86_CPUID) == 0) { |
|
2881 |
mutex_exit(&cpu_node_lock); |
|
2882 |
return; |
|
2883 |
} |
|
2884 |
||
2885 |
/* vendor-id */ |
|
2886 |
||
2887 |
(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
2888 |
"vendor-id", cpi->cpi_vendorstr); |
0 | 2889 |
|
2890 |
if (cpi->cpi_maxeax == 0) { |
|
2891 |
mutex_exit(&cpu_node_lock); |
|
2892 |
return; |
|
2893 |
} |
|
2894 |
||
2895 |
/* |
|
2896 |
* family, model, and step |
|
2897 |
*/ |
|
2898 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
2899 |
"family", CPI_FAMILY(cpi)); |
0 | 2900 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
2901 |
"cpu-model", CPI_MODEL(cpi)); |
0 | 2902 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
2903 |
"stepping-id", CPI_STEP(cpi)); |
0 | 2904 |
|
2905 |
/* type */ |
|
2906 |
||
2907 |
switch (cpi->cpi_vendor) { |
|
2908 |
case X86_VENDOR_Intel: |
|
2909 |
create = 1; |
|
2910 |
break; |
|
2911 |
default: |
|
2912 |
create = 0; |
|
2913 |
break; |
|
2914 |
} |
|
2915 |
if (create) |
|
2916 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
2917 |
"type", CPI_TYPE(cpi)); |
0 | 2918 |
|
2919 |
/* ext-family */ |
|
2920 |
||
2921 |
switch (cpi->cpi_vendor) { |
|
2922 |
case X86_VENDOR_Intel: |
|
2923 |
case X86_VENDOR_AMD: |
|
2924 |
create = cpi->cpi_family >= 0xf; |
|
2925 |
break; |
|
2926 |
default: |
|
2927 |
create = 0; |
|
2928 |
break; |
|
2929 |
} |
|
2930 |
if (create) |
|
2931 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
2932 |
"ext-family", CPI_FAMILY_XTD(cpi)); |
|
2933 |
||
2934 |
/* ext-model */ |
|
2935 |
||
2936 |
switch (cpi->cpi_vendor) { |
|
2937 |
case X86_VENDOR_Intel: |
|
2001
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
2938 |
create = CPI_MODEL(cpi) == 0xf; |
427a702b03e2
6427092 extended-model CPUID information is different between AMD and Intel
dmick
parents:
1975
diff
changeset
|
2939 |
break; |
0 | 2940 |
case X86_VENDOR_AMD: |
1582
eb879d43ab47
6323525 Mutual exclusion primitives don't work as expected on Opteron systems
kchow
parents:
1414
diff
changeset
|
2941 |
create = CPI_FAMILY(cpi) == 0xf; |
0 | 2942 |
break; |
2943 |
default: |
|
2944 |
create = 0; |
|
2945 |
break; |
|
2946 |
} |
|
2947 |
if (create) |
|
2948 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
2949 |
"ext-model", CPI_MODEL_XTD(cpi)); |
0 | 2950 |
|
2951 |
/* generation */ |
|
2952 |
||
2953 |
switch (cpi->cpi_vendor) { |
|
2954 |
case X86_VENDOR_AMD: |
|
2955 |
/* |
|
2956 |
* AMD K5 model 1 was the first part to support this |
|
2957 |
*/ |
|
2958 |
create = cpi->cpi_xmaxeax >= 0x80000001; |
|
2959 |
break; |
|
2960 |
default: |
|
2961 |
create = 0; |
|
2962 |
break; |
|
2963 |
} |
|
2964 |
if (create) |
|
2965 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
2966 |
"generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); |
|
2967 |
||
2968 |
/* brand-id */ |
|
2969 |
||
2970 |
switch (cpi->cpi_vendor) { |
|
2971 |
case X86_VENDOR_Intel: |
|
2972 |
/* |
|
2973 |
* brand id first appeared on Pentium III Xeon model 8, |
|
2974 |
* and Celeron model 8 processors and Opteron |
|
2975 |
*/ |
|
2976 |
create = cpi->cpi_family > 6 || |
|
2977 |
(cpi->cpi_family == 6 && cpi->cpi_model >= 8); |
|
2978 |
break; |
|
2979 |
case X86_VENDOR_AMD: |
|
2980 |
create = cpi->cpi_family >= 0xf; |
|
2981 |
break; |
|
2982 |
default: |
|
2983 |
create = 0; |
|
2984 |
break; |
|
2985 |
} |
|
2986 |
if (create && cpi->cpi_brandid != 0) { |
|
2987 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
2988 |
"brand-id", cpi->cpi_brandid); |
|
2989 |
} |
|
2990 |
||
2991 |
/* chunks, and apic-id */ |
|
2992 |
||
2993 |
switch (cpi->cpi_vendor) { |
|
2994 |
/* |
|
2995 |
* first available on Pentium IV and Opteron (K8) |
|
2996 |
*/ |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
2997 |
case X86_VENDOR_Intel: |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
2998 |
create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
2999 |
break; |
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3000 |
case X86_VENDOR_AMD: |
0 | 3001 |
create = cpi->cpi_family >= 0xf; |
3002 |
break; |
|
3003 |
default: |
|
3004 |
create = 0; |
|
3005 |
break; |
|
3006 |
} |
|
3007 |
if (create) { |
|
3008 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3009 |
"chunks", CPI_CHUNKS(cpi)); |
0 | 3010 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3011 |
"apic-id", CPI_APIC_ID(cpi)); |
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3012 |
if (cpi->cpi_chipid >= 0) { |
0 | 3013 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
3014 |
"chip#", cpi->cpi_chipid); |
|
1414
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3015 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3016 |
"clog#", cpi->cpi_clogid); |
b4126407ac5b
PSARC 2006/020 FMA for Athlon 64 and Opteron Processors
cindi
parents:
1228
diff
changeset
|
3017 |
} |
0 | 3018 |
} |
3019 |
||
3020 |
/* cpuid-features */ |
|
3021 |
||
3022 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
3023 |
"cpuid-features", CPI_FEATURES_EDX(cpi)); |
|
3024 |
||
3025 |
||
3026 |
/* cpuid-features-ecx */ |
|
3027 |
||
3028 |
switch (cpi->cpi_vendor) { |
|
3029 |
case X86_VENDOR_Intel: |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3030 |
create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; |
0 | 3031 |
break; |
3032 |
default: |
|
3033 |
create = 0; |
|
3034 |
break; |
|
3035 |
} |
|
3036 |
if (create) |
|
3037 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
|
3038 |
"cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); |
|
3039 |
||
3040 |
/* ext-cpuid-features */ |
|
3041 |
||
3042 |
switch (cpi->cpi_vendor) { |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3043 |
case X86_VENDOR_Intel: |
0 | 3044 |
case X86_VENDOR_AMD: |
3045 |
case X86_VENDOR_Cyrix: |
|
3046 |
case X86_VENDOR_TM: |
|
3047 |
case X86_VENDOR_Centaur: |
|
3048 |
create = cpi->cpi_xmaxeax >= 0x80000001; |
|
3049 |
break; |
|
3050 |
default: |
|
3051 |
create = 0; |
|
3052 |
break; |
|
3053 |
} |
|
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3054 |
if (create) { |
0 | 3055 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3056 |
"ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3057 |
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, |
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3058 |
"ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); |
1975
7490b056500b
6183891 Missing brand ID strings for several common x86 CPUs
dmick
parents:
1727
diff
changeset
|
3059 |
} |
0 | 3060 |
|
3061 |
/* |
|
3062 |
* Brand String first appeared in Intel Pentium IV, AMD K5 |
|
3063 |
* model 1, and Cyrix GXm. On earlier models we try and |
|
3064 |
* simulate something similar .. so this string should always |
|
3065 |
* same -something- about the processor, however lame. |
|
3066 |
*/ |
|
3067 |
(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, |
|
3068 |
"brand-string", cpi->cpi_brandstr); |
|
3069 |
||
3070 |
/* |
|
3071 |
* Finally, cache and tlb information |
|
3072 |
*/ |
|
3073 |
switch (x86_which_cacheinfo(cpi)) { |
|
3074 |
case X86_VENDOR_Intel: |
|
3075 |
intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); |
|
3076 |
break; |
|
3077 |
case X86_VENDOR_Cyrix: |
|
3078 |
cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); |
|
3079 |
break; |
|
3080 |
case X86_VENDOR_AMD: |
|
3081 |
amd_cache_info(cpi, cpu_devi); |
|
3082 |
break; |
|
3083 |
default: |
|
3084 |
break; |
|
3085 |
} |
|
3086 |
||
3087 |
mutex_exit(&cpu_node_lock); |
|
3088 |
} |
|
3089 |
||
3090 |
struct l2info { |
|
3091 |
int *l2i_csz; |
|
3092 |
int *l2i_lsz; |
|
3093 |
int *l2i_assoc; |
|
3094 |
int l2i_ret; |
|
3095 |
}; |
|
3096 |
||
3097 |
/* |
|
3098 |
* A cacheinfo walker that fetches the size, line-size and associativity |
|
3099 |
* of the L2 cache |
|
3100 |
*/ |
|
3101 |
static int |
|
3102 |
intel_l2cinfo(void *arg, const struct cachetab *ct) |
|
3103 |
{ |
|
3104 |
struct l2info *l2i = arg; |
|
3105 |
int *ip; |
|
3106 |
||
3107 |
if (ct->ct_label != l2_cache_str && |
|
3108 |
ct->ct_label != sl2_cache_str) |
|
3109 |
return (0); /* not an L2 -- keep walking */ |
|
3110 |
||
3111 |
if ((ip = l2i->l2i_csz) != NULL) |
|
3112 |
*ip = ct->ct_size; |
|
3113 |
if ((ip = l2i->l2i_lsz) != NULL) |
|
3114 |
*ip = ct->ct_line_size; |
|
3115 |
if ((ip = l2i->l2i_assoc) != NULL) |
|
3116 |
*ip = ct->ct_assoc; |
|
3117 |
l2i->l2i_ret = ct->ct_size; |
|
3118 |
return (1); /* was an L2 -- terminate walk */ |
|
3119 |
} |
|
3120 |
||
3121 |
static void |
|
3122 |
amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) |
|
3123 |
{ |
|
1228 | 3124 |
struct cpuid_regs *cp; |
0 | 3125 |
uint_t size, assoc; |
3126 |
int *ip; |
|
3127 |
||
3128 |
if (cpi->cpi_xmaxeax < 0x80000006) |
|
3129 |
return; |
|
3130 |
cp = &cpi->cpi_extd[6]; |
|
3131 |
||
3132 |
if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 && |
|
3133 |
(size = BITX(cp->cp_ecx, 31, 16)) != 0) { |
|
3134 |
uint_t cachesz = size * 1024; |
|
3135 |
||
3136 |
||
3137 |
if ((ip = l2i->l2i_csz) != NULL) |
|
3138 |
*ip = cachesz; |
|
3139 |
if ((ip = l2i->l2i_lsz) != NULL) |
|
3140 |
*ip = BITX(cp->cp_ecx, 7, 0); |
|
3141 |
if ((ip = l2i->l2i_assoc) != NULL) |
|
3142 |
*ip = assoc; |
|
3143 |
l2i->l2i_ret = cachesz; |
|
3144 |
} |
|
3145 |
} |
|
3146 |
||
3147 |
int |
|
3148 |
getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) |
|
3149 |
{ |
|
3150 |
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; |
|
3151 |
struct l2info __l2info, *l2i = &__l2info; |
|
3152 |
||
3153 |
l2i->l2i_csz = csz; |
|
3154 |
l2i->l2i_lsz = lsz; |
|
3155 |
l2i->l2i_assoc = assoc; |
|
3156 |
l2i->l2i_ret = -1; |
|
3157 |
||
3158 |
switch (x86_which_cacheinfo(cpi)) { |
|
3159 |
case X86_VENDOR_Intel: |
|
3160 |
intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); |
|
3161 |
break; |
|
3162 |
case X86_VENDOR_Cyrix: |
|
3163 |
cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); |
|
3164 |
break; |
|
3165 |
case X86_VENDOR_AMD: |
|
3166 |
amd_l2cacheinfo(cpi, l2i); |
|
3167 |
break; |
|
3168 |
default: |
|
3169 |
break; |
|
3170 |
} |
|
3171 |
return (l2i->l2i_ret); |
|
3172 |
} |
|
4481
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3173 |
|
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3174 |
size_t |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3175 |
cpuid_get_mwait_size(cpu_t *cpu) |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3176 |
{ |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3177 |
ASSERT(cpuid_checkpass(cpu, 2)); |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3178 |
return (cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max); |
2bb321aaf3c3
6495392 use monitor/mwait for halting idle CPUs where supported
bholler
parents:
4265
diff
changeset
|
3179 |
} |